/export/starexec/sandbox/solver/bin/starexec_run_termcomp17 /export/starexec/sandbox/benchmark/theBenchmark.smt2 /export/starexec/sandbox/output/output_files -------------------------------------------------------------------------------- NO Solver Timeout: 4 Global Timeout: 300 Maximum number of concurrent processes: 900 No parsing errors! Init Location: 0 Transitions: 0}> 0}> (1 + addr^0)}> (0 + fd^0), added^0 -> (1 + added^0)}> 1}> undef241}> (0 + __const_10^0)}> undef314}> 1}> undef483}> 1}> undef563}> undef688}> undef804}> undef910}> (1 + listen_index^0)}> undef1239}> undef1330}> 0}> 1}> (0 + addrs^0)}> 1}> undef1627}> undef1704, MaxBackends^0 -> undef1705, added^0 -> 0, addrs^0 -> undef1711, listen_index^0 -> 0, one^0 -> 1, ret^0 -> undef1719}> Fresh variables: undef241, undef314, undef483, undef563, undef688, undef804, undef910, undef1239, undef1330, undef1627, undef1704, undef1705, undef1711, undef1719, Undef variables: undef241, undef314, undef483, undef563, undef688, undef804, undef910, undef1239, undef1330, undef1627, undef1704, undef1705, undef1711, undef1719, Abstraction variables: Exit nodes: Accepting locations: Asserts: Preprocessed LLVMGraph Init Location: 0 Transitions: (1 + addr^0)}> (1 + addr^0)}> (0 + fd^0), added^0 -> (1 + added^0), addr^0 -> (1 + addr^0)}> (1 + addr^0)}> (0 + fd^0), added^0 -> (1 + added^0), addr^0 -> (1 + addr^0)}> (1 + addr^0)}> (0 + fd^0), added^0 -> (1 + added^0), addr^0 -> (1 + addr^0)}> (1 + addr^0)}> (0 + fd^0), added^0 -> (1 + added^0), addr^0 -> (1 + addr^0)}> (1 + addr^0)}> (0 + fd^0), added^0 -> (1 + added^0), addr^0 -> (1 + addr^0)}> (1 + addr^0)}> (0 + fd^0), added^0 -> (1 + added^0), addr^0 -> (1 + addr^0)}> (1 + addr^0)}> (1 + addr^0)}> (1 + addr^0)}> (1 + addr^0)}> (1 + addr^0)}> (1 + addr^0)}> (1 + addr^0)}> (1 + addr^0)}> (1 + listen_index^0)}> (1 + listen_index^0)}> undef910, tmp___35^0 -> undef804}> (1 + addr^0), fd^0 -> undef910}> (1 + addr^0), fd^0 -> undef910}> Fresh variables: undef241, undef314, undef483, undef563, undef688, undef804, undef910, undef1239, undef1330, undef1627, undef1704, undef1705, undef1711, undef1719, Undef variables: undef241, undef314, undef483, undef563, undef688, undef804, undef910, undef1239, undef1330, undef1627, undef1704, undef1705, undef1711, undef1719, Abstraction variables: Exit nodes: Accepting locations: Asserts: ************************************************************* ******************************************************************************************* *********************** WORKING TRANSITION SYSTEM (DAG) *********************** ******************************************************************************************* Init Location: 0 Graph 0: Transitions: Variables: Graph 1: Transitions: 1 + addr^0, rest remain the same}> 1 + addr^0, rest remain the same}> fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> 1 + addr^0, rest remain the same}> fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> 1 + addr^0, rest remain the same}> fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> 1 + addr^0, rest remain the same}> fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> 1 + addr^0, rest remain the same}> fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> 1 + addr^0, rest remain the same}> fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> 1 + addr^0, rest remain the same}> 1 + addr^0, rest remain the same}> 1 + addr^0, rest remain the same}> 1 + addr^0, rest remain the same}> 1 + addr^0, rest remain the same}> 1 + addr^0, rest remain the same}> 1 + addr^0, rest remain the same}> 1 + addr^0, rest remain the same}> 1 + listen_index^0, rest remain the same}> 1 + listen_index^0, rest remain the same}> undef910, tmp___35^0 -> undef804, rest remain the same}> 1 + addr^0, fd^0 -> undef910, rest remain the same}> 1 + addr^0, fd^0 -> undef910, rest remain the same}> Variables: MAXADDR^0, addr^0, ListenSocket_OF_listen_index^0, __const_10^0, added^0, addr_ai_family^0, fd^0, tmp___35^0, MaxListen^0, listen_index^0 Graph 2: Transitions: Variables: Graph 3: Transitions: Variables: Precedence: Graph 0 Graph 1 Graph 2 Graph 3 Map Locations to Subgraph: ( 0 , 0 ) ( 5 , 3 ) ( 8 , 2 ) ( 10 , 1 ) ( 17 , 1 ) ( 24 , 1 ) ( 27 , 1 ) ******************************************************************************************* ******************************** CHECKING ASSERTIONS ******************************** ******************************************************************************************* Proving termination of subgraph 0 Proving termination of subgraph 1 Checking unfeasibility... Time used: 0.923948 Checking conditional termination of SCC {l10, l17, l24, l27}... LOG: CALL solveLinear LOG: RETURN solveLinear - Elapsed time: 0.023405s Ranking function: -7 + 7*MAXADDR^0 - 7*addr^0 New Graphs: Transitions: fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> 1 + addr^0, rest remain the same}> fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> 1 + addr^0, rest remain the same}> fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> 1 + addr^0, rest remain the same}> fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> 1 + addr^0, rest remain the same}> fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> 1 + addr^0, rest remain the same}> fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> 1 + addr^0, rest remain the same}> 1 + listen_index^0, rest remain the same}> 1 + listen_index^0, rest remain the same}> undef910, tmp___35^0 -> undef804, rest remain the same}> 1 + addr^0, fd^0 -> undef910, tmp___35^0 -> undef804, rest remain the same}> undef910, tmp___35^0 -> undef804, rest remain the same}> 1 + addr^0, fd^0 -> undef910, tmp___35^0 -> undef804, rest remain the same}> 1 + addr^0, fd^0 -> undef910, tmp___35^0 -> undef804, rest remain the same}> 1 + addr^0, fd^0 -> undef910, tmp___35^0 -> undef804, rest remain the same}> undef910, tmp___35^0 -> undef804, rest remain the same}> 1 + addr^0, fd^0 -> undef910, tmp___35^0 -> undef804, rest remain the same}> 1 + addr^0, fd^0 -> undef910, tmp___35^0 -> undef804, rest remain the same}> 1 + addr^0, fd^0 -> undef910, tmp___35^0 -> undef804, rest remain the same}> 1 + addr^0, fd^0 -> undef910, rest remain the same}> 1 + addr^0, fd^0 -> undef910, rest remain the same}> Variables: ListenSocket_OF_listen_index^0, MAXADDR^0, MaxListen^0, __const_10^0, added^0, addr^0, addr_ai_family^0, fd^0, listen_index^0, tmp___35^0 Checking conditional termination of SCC {l10, l17, l27}... LOG: CALL solveLinear LOG: RETURN solveLinear - Elapsed time: 0.021872s Ranking function: MaxListen^0 - listen_index^0 New Graphs: Transitions: undef910, tmp___35^0 -> undef804, rest remain the same}> 1 + addr^0, fd^0 -> undef910, tmp___35^0 -> undef804, rest remain the same}> undef910, tmp___35^0 -> undef804, rest remain the same}> 1 + addr^0, fd^0 -> undef910, tmp___35^0 -> undef804, rest remain the same}> 1 + addr^0, fd^0 -> undef910, tmp___35^0 -> undef804, rest remain the same}> 1 + addr^0, fd^0 -> undef910, tmp___35^0 -> undef804, rest remain the same}> undef910, tmp___35^0 -> undef804, rest remain the same}> 1 + addr^0, fd^0 -> undef910, tmp___35^0 -> undef804, rest remain the same}> 1 + addr^0, fd^0 -> undef910, tmp___35^0 -> undef804, rest remain the same}> 1 + addr^0, fd^0 -> undef910, tmp___35^0 -> undef804, rest remain the same}> 1 + addr^0, fd^0 -> undef910, rest remain the same}> 1 + addr^0, fd^0 -> undef910, rest remain the same}> undef910, tmp___35^0 -> undef804, rest remain the same}> 1 + addr^0, fd^0 -> undef910, tmp___35^0 -> undef804, rest remain the same}> undef910, tmp___35^0 -> undef804, rest remain the same}> 1 + addr^0, fd^0 -> undef910, tmp___35^0 -> undef804, rest remain the same}> 1 + addr^0, fd^0 -> undef910, tmp___35^0 -> undef804, rest remain the same}> 1 + addr^0, fd^0 -> undef910, tmp___35^0 -> undef804, rest remain the same}> undef910, tmp___35^0 -> undef804, rest remain the same}> 1 + addr^0, fd^0 -> undef910, tmp___35^0 -> undef804, rest remain the same}> 1 + addr^0, fd^0 -> undef910, tmp___35^0 -> undef804, rest remain the same}> 1 + addr^0, fd^0 -> undef910, tmp___35^0 -> undef804, rest remain the same}> 1 + addr^0, fd^0 -> undef910, rest remain the same}> 1 + addr^0, fd^0 -> undef910, rest remain the same}> undef910, tmp___35^0 -> undef804, rest remain the same}> 1 + addr^0, fd^0 -> undef910, tmp___35^0 -> undef804, rest remain the same}> undef910, tmp___35^0 -> undef804, rest remain the same}> 1 + addr^0, fd^0 -> undef910, tmp___35^0 -> undef804, rest remain the same}> 1 + addr^0, fd^0 -> undef910, tmp___35^0 -> undef804, rest remain the same}> 1 + addr^0, fd^0 -> undef910, tmp___35^0 -> undef804, rest remain the same}> undef910, tmp___35^0 -> undef804, rest remain the same}> 1 + addr^0, fd^0 -> undef910, tmp___35^0 -> undef804, rest remain the same}> 1 + addr^0, fd^0 -> undef910, tmp___35^0 -> undef804, rest remain the same}> 1 + addr^0, fd^0 -> undef910, tmp___35^0 -> undef804, rest remain the same}> 1 + addr^0, fd^0 -> undef910, rest remain the same}> 1 + addr^0, fd^0 -> undef910, rest remain the same}> fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> 1 + addr^0, rest remain the same}> fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> 1 + addr^0, rest remain the same}> fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> 1 + addr^0, rest remain the same}> fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> 1 + addr^0, rest remain the same}> fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> 1 + addr^0, rest remain the same}> fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> 1 + addr^0, rest remain the same}> Variables: ListenSocket_OF_listen_index^0, MAXADDR^0, MaxListen^0, __const_10^0, added^0, addr^0, addr_ai_family^0, fd^0, listen_index^0, tmp___35^0 Checking conditional termination of SCC {l10, l17}... LOG: CALL solveLinear LOG: RETURN solveLinear - Elapsed time: 0.094180s Ranking function: -7 + 6*MAXADDR^0 + MaxListen^0 - 6*addr^0 - listen_index^0 New Graphs: Transitions: undef910, tmp___35^0 -> undef804, rest remain the same}> undef910, tmp___35^0 -> undef804, rest remain the same}> undef910, tmp___35^0 -> undef804, rest remain the same}> undef910, tmp___35^0 -> undef804, rest remain the same}> undef910, tmp___35^0 -> undef804, rest remain the same}> undef910, tmp___35^0 -> undef804, rest remain the same}> undef910, tmp___35^0 -> undef804, rest remain the same}> undef910, tmp___35^0 -> undef804, rest remain the same}> undef910, tmp___35^0 -> undef804, rest remain the same}> fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> 1 + addr^0, rest remain the same}> fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> 1 + addr^0, rest remain the same}> fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> 1 + addr^0, rest remain the same}> fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> 1 + addr^0, rest remain the same}> fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> 1 + addr^0, rest remain the same}> fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> 1 + addr^0, rest remain the same}> Variables: ListenSocket_OF_listen_index^0, MAXADDR^0, MaxListen^0, __const_10^0, added^0, addr^0, addr_ai_family^0, fd^0, listen_index^0, tmp___35^0 Checking conditional termination of SCC {l10, l17}... LOG: CALL solveLinear LOG: RETURN solveLinear - Elapsed time: 0.015831s LOG: CALL solveLinear LOG: RETURN solveLinear - Elapsed time: 0.198925s [44726 : 44879] [44726 : 44880] Successful child: 44879 [ Invariant Graph ] Strengthening and disabling transitions... LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility Strengthening transition (result): fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility Strengthening transition (result): 1 + addr^0, rest remain the same}> LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility Strengthening transition (result): fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility Strengthening transition (result): 1 + addr^0, rest remain the same}> LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility Strengthening transition (result): fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility Strengthening transition (result): 1 + addr^0, rest remain the same}> LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility Strengthening transition (result): fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility Strengthening transition (result): 1 + addr^0, rest remain the same}> LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility Strengthening transition (result): fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility Strengthening transition (result): 1 + addr^0, rest remain the same}> LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility Strengthening transition (result): fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility Strengthening transition (result): 1 + addr^0, rest remain the same}> LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility Strengthening transition (result): LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility Strengthening transition (result): 1 + addr^0, rest remain the same}> LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility Strengthening transition (result): LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility Strengthening transition (result): 1 + addr^0, rest remain the same}> LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility Strengthening transition (result): 1 + addr^0, rest remain the same}> LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility Strengthening transition (result): 1 + addr^0, rest remain the same}> LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility Strengthening transition (result): LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility Strengthening transition (result): 1 + addr^0, rest remain the same}> LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility Strengthening transition (result): 1 + addr^0, rest remain the same}> LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility Strengthening transition (result): 1 + addr^0, rest remain the same}> LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility Strengthening transition (result): 1 + listen_index^0, rest remain the same}> LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility Strengthening transition (result): 1 + listen_index^0, rest remain the same}> LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility Strengthening transition (result): undef910, tmp___35^0 -> undef804, rest remain the same}> LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility Strengthening transition (result): 1 + addr^0, fd^0 -> undef910, rest remain the same}> LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility Strengthening transition (result): 1 + addr^0, fd^0 -> undef910, rest remain the same}> [ Termination Graph ] Strengthening and disabling transitions... LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility Strengthening transition (result): fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility Strengthening transition (result): 1 + addr^0, rest remain the same}> LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility Strengthening transition (result): fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility Strengthening transition (result): 1 + addr^0, rest remain the same}> LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility Strengthening transition (result): fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility Strengthening transition (result): 1 + addr^0, rest remain the same}> LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility Strengthening transition (result): fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility Strengthening transition (result): 1 + addr^0, rest remain the same}> LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility Strengthening transition (result): fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility Strengthening transition (result): 1 + addr^0, rest remain the same}> LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility Strengthening transition (result): fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> LOG: CALL solverLinear in Graph for feasibility LOG: RETURN solveLinear in Graph for feasibility Strengthening transition (result): 1 + addr^0, rest remain the same}> Ranking function: MAXADDR^0 - addr^0 New Graphs: INVARIANTS: 17: addr^0 <= MAXADDR^0 , 24: addr^0 <= MAXADDR^0 , 27: addr^0 <= MAXADDR^0 , Quasi-INVARIANTS to narrow Graph: 17: 24: 27: Proving termination of subgraph 2 Checking unfeasibility... Time used: 0.002302 > No variable changes in termination graph. Checking conditional unfeasibility... Termination failed. Trying to show unreachability... Proving unreachability of entry: LOG: CALL check - Post:1 <= 0 - Process 1 * Exit transition: * Postcondition : 1 <= 0 Postcodition moved up: 1 <= 0 LOG: Try proving POST [44726 : 44993] [44726 : 44994] [44726 : 44995] [44726 : 44996] [44726 : 44997] [44726 : 44998] [44726 : 44999] [44726 : 45000] [44726 : 45001] [44726 : 45002] [44726 : 45003] [44726 : 45004] LOG: NarrowEntry size 1 LOG: NarrowEntry size 1 LOG: NarrowEntry size 1 LOG: NarrowEntry size 1 LOG: NarrowEntry size 1 LOG: NarrowEntry size 1 LOG: NarrowEntry size 1 LOG: NarrowEntry size 1 LOG: NarrowEntry size 1 LOG: NarrowEntry size 1 LOG: NarrowEntry size 1 LOG: NarrowEntry size 1 Narrowing transition: LOG: Narrow transition size 1 Narrowing transition: 1 + addr^0, rest remain the same}> LOG: Narrow transition size 1 Narrowing transition: 1 + addr^0, rest remain the same}> LOG: Narrow transition size 1 Narrowing transition: LOG: Narrow transition size 1 Narrowing transition: LOG: Narrow transition size 1 Narrowing transition: fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> LOG: Narrow transition size 1 Narrowing transition: 1 + addr^0, rest remain the same}> LOG: Narrow transition size 1 Narrowing transition: fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> LOG: Narrow transition size 1 Narrowing transition: 1 + addr^0, rest remain the same}> LOG: Narrow transition size 1 Narrowing transition: fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> LOG: Narrow transition size 1 Narrowing transition: 1 + addr^0, rest remain the same}> LOG: Narrow transition size 1 Narrowing transition: fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> LOG: Narrow transition size 1 Narrowing transition: 1 + addr^0, rest remain the same}> LOG: Narrow transition size 1 Narrowing transition: fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> LOG: Narrow transition size 1 Narrowing transition: 1 + addr^0, rest remain the same}> LOG: Narrow transition size 1 Narrowing transition: fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> LOG: Narrow transition size 1 Narrowing transition: 1 + addr^0, rest remain the same}> LOG: Narrow transition size 1 Narrowing transition: LOG: Narrow transition size 1 Narrowing transition: 1 + addr^0, rest remain the same}> LOG: Narrow transition size 1 Narrowing transition: LOG: Narrow transition size 1 Narrowing transition: 1 + addr^0, rest remain the same}> LOG: Narrow transition size 1 Narrowing transition: 1 + addr^0, rest remain the same}> LOG: Narrow transition size 1 Narrowing transition: 1 + addr^0, rest remain the same}> LOG: Narrow transition size 1 Narrowing transition: LOG: Narrow transition size 1 Narrowing transition: 1 + addr^0, rest remain the same}> LOG: Narrow transition size 1 Narrowing transition: 1 + addr^0, rest remain the same}> LOG: Narrow transition size 1 Narrowing transition: 1 + addr^0, rest remain the same}> LOG: Narrow transition size 1 Narrowing transition: 1 + listen_index^0, rest remain the same}> LOG: Narrow transition size 1 Narrowing transition: 1 + listen_index^0, rest remain the same}> LOG: Narrow transition size 1 Narrowing transition: undef910, tmp___35^0 -> undef804, rest remain the same}> LOG: Narrow transition size 1 Narrowing transition: 1 + addr^0, fd^0 -> undef910, rest remain the same}> LOG: Narrow transition size 1 Narrowing transition: 1 + addr^0, fd^0 -> undef910, rest remain the same}> LOG: Narrow transition size 1 ENTRIES: END ENTRIES: GRAPH: 1 + addr^0, rest remain the same}> 1 + addr^0, rest remain the same}> fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> 1 + addr^0, rest remain the same}> fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> 1 + addr^0, rest remain the same}> fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> 1 + addr^0, rest remain the same}> fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> 1 + addr^0, rest remain the same}> fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> 1 + addr^0, rest remain the same}> fd^0, added^0 -> 1 + added^0, addr^0 -> 1 + addr^0, rest remain the same}> 1 + addr^0, rest remain the same}> 1 + addr^0, rest remain the same}> 1 + addr^0, rest remain the same}> 1 + addr^0, rest remain the same}> 1 + addr^0, rest remain the same}> 1 + addr^0, rest remain the same}> 1 + addr^0, rest remain the same}> 1 + addr^0, rest remain the same}> 1 + listen_index^0, rest remain the same}> 1 + listen_index^0, rest remain the same}> undef910, tmp___35^0 -> undef804, rest remain the same}> 1 + addr^0, fd^0 -> undef910, rest remain the same}> 1 + addr^0, fd^0 -> undef910, rest remain the same}> END GRAPH: EXIT: POST: 1 <= 0 LOG: Try proving POST [44726 : 45005] [44726 : 45006] [44726 : 45007] LOG: Postcondition is not implied - no solution > Postcondition is not implied! LOG: RETURN check - Elapsed time: 4.466936s Cannot prove unreachability [44726 : 45008] [44726 : 45009] Successful child: 45008 Program does NOT terminate