33.10/10.22	YES
33.10/10.24	proof of /export/starexec/sandbox/benchmark/theBenchmark.c
33.10/10.24	# AProVE Commit ID: 48fb2092695e11cc9f56e44b17a92a5f88ffb256 marcel 20180622 unpublished dirty
33.10/10.24	
33.10/10.24	
33.10/10.24	Termination of the given C Problem could be proven:
33.10/10.24	
33.10/10.24	(0) C Problem
33.10/10.24	(1) CToLLVMProof [EQUIVALENT, 172 ms]
33.10/10.24	(2) LLVM problem
33.10/10.24	(3) LLVMToTerminationGraphProof [EQUIVALENT, 4492 ms]
33.10/10.24	(4) LLVM Symbolic Execution Graph
33.10/10.24	(5) SymbolicExecutionGraphToSCCProof [SOUND, 0 ms]
33.10/10.24	(6) AND
33.10/10.24	    (7) LLVM Symbolic Execution SCC
33.10/10.24	        (8) SCC2IRS [SOUND, 78 ms]
33.10/10.24	        (9) IntTRS
33.10/10.24	        (10) IntTRSCompressionProof [EQUIVALENT, 0 ms]
33.10/10.24	        (11) IntTRS
33.10/10.24	        (12) PolynomialOrderProcessor [EQUIVALENT, 0 ms]
33.10/10.24	        (13) YES
33.10/10.24	    (14) LLVM Symbolic Execution SCC
33.10/10.24	        (15) SCC2IRS [SOUND, 118 ms]
33.10/10.24	        (16) IntTRS
33.10/10.24	        (17) IntTRSCompressionProof [EQUIVALENT, 0 ms]
33.10/10.24	        (18) IntTRS
33.10/10.24	        (19) RankingReductionPairProof [EQUIVALENT, 28 ms]
33.10/10.24	        (20) YES
33.10/10.24	
33.10/10.24	
33.10/10.24	----------------------------------------
33.10/10.24	
33.10/10.24	(0)
33.10/10.24	Obligation:
33.10/10.24	c file /export/starexec/sandbox/benchmark/theBenchmark.c
33.10/10.24	----------------------------------------
33.10/10.24	
33.10/10.24	(1) CToLLVMProof (EQUIVALENT)
33.10/10.24	Compiled c-file /export/starexec/sandbox/benchmark/theBenchmark.c to LLVM.
33.10/10.24	----------------------------------------
33.10/10.24	
33.10/10.24	(2)
33.10/10.24	Obligation:
33.10/10.24	LLVM Problem
33.10/10.24	
33.10/10.24	Aliases:
33.10/10.24	
33.10/10.24	Data layout:
33.10/10.24	
33.10/10.24	"e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
33.10/10.24	
33.10/10.24	Machine:
33.10/10.24	
33.10/10.24	"x86_64-pc-linux-gnu"
33.10/10.24	
33.10/10.24	Type definitions:
33.10/10.24	
33.10/10.24	Global variables:
33.10/10.24	
33.10/10.24	Function declarations and definitions:
33.10/10.24	
33.10/10.24	*BasicFunctionTypename: "__VERIFIER_nondet_int" returnParam: i32 parameters: () variableLength: false visibilityType: DEFAULT callingConvention: ccc
33.10/10.24	*BasicFunctionTypename: "main" linkageType: EXTERNALLY_VISIBLE returnParam: i32 parameters: () variableLength: false visibilityType: DEFAULT callingConvention: ccc
33.10/10.24		0:
33.10/10.24			%1 = alloca i32, align 4
33.10/10.24			%a = alloca i32, align 4
33.10/10.24			%b = alloca i32, align 4
33.10/10.24			%x = alloca i32, align 4
33.10/10.24			%y = alloca i32, align 4
33.10/10.24			store 0, %1
33.10/10.24			%2 = call i32 @__VERIFIER_nondet_int()
33.10/10.24			store %2, %a
33.10/10.24			%3 = call i32 @__VERIFIER_nondet_int()
33.10/10.24			store %3, %b
33.10/10.24			%4 = call i32 @__VERIFIER_nondet_int()
33.10/10.24			store %4, %x
33.10/10.24			%5 = call i32 @__VERIFIER_nondet_int()
33.10/10.24			store %5, %y
33.10/10.24			%6 = load %a
33.10/10.24			%7 = load %b
33.10/10.24			%8 = icmp ne %6 %7
33.10/10.24			br %8, %9, %10
33.10/10.24		9:
33.10/10.24			store 0, %1
33.10/10.24			br %33
33.10/10.24		10:
33.10/10.24			br %11
33.10/10.24		11:
33.10/10.24			%12 = load %x
33.10/10.24			%13 = icmp sge %12 0
33.10/10.24			br %13, %17, %14
33.10/10.24		14:
33.10/10.24			%15 = load %y
33.10/10.24			%16 = icmp sge %15 0
33.10/10.24			br %17
33.10/10.24		17:
33.10/10.24			%18 = phi [1, %11], [%16, %14]
33.10/10.24			br %18, %19, %32
33.10/10.24		19:
33.10/10.24			%20 = load %x
33.10/10.24			%21 = load %a
33.10/10.24			%22 = add %20 %21
33.10/10.24			%23 = load %b
33.10/10.24			%24 = sub %22 %23
33.10/10.24			%25 = sub %24 1
33.10/10.24			store %25, %x
33.10/10.24			%26 = load %y
33.10/10.24			%27 = load %b
33.10/10.24			%28 = add %26 %27
33.10/10.24			%29 = load %a
33.10/10.24			%30 = sub %28 %29
33.10/10.24			%31 = sub %30 1
33.10/10.24			store %31, %y
33.10/10.24			br %11
33.10/10.24		32:
33.10/10.24			store 0, %1
33.10/10.24			br %33
33.10/10.24		33:
33.10/10.24			%34 = load %1
33.10/10.24			ret %34
33.10/10.24	
33.10/10.24	
33.10/10.24	Analyze Termination of all function calls matching the pattern:
33.10/10.24	main()
33.10/10.24	----------------------------------------
33.10/10.24	
33.10/10.24	(3) LLVMToTerminationGraphProof (EQUIVALENT)
33.10/10.24	Constructed symbolic execution graph for LLVM program and proved memory safety.
33.10/10.24	----------------------------------------
33.10/10.24	
33.10/10.24	(4)
33.10/10.24	Obligation:
33.10/10.24	SE Graph
33.10/10.24	----------------------------------------
33.10/10.24	
33.10/10.24	(5) SymbolicExecutionGraphToSCCProof (SOUND)
33.10/10.24	Splitted symbolic execution graph to 2 SCCs.
33.10/10.24	----------------------------------------
33.10/10.24	
33.10/10.24	(6)
33.10/10.24	Complex Obligation (AND)
33.10/10.24	
33.10/10.24	----------------------------------------
33.10/10.24	
33.10/10.24	(7)
33.10/10.24	Obligation:
33.10/10.24	SCC
33.10/10.24	----------------------------------------
33.10/10.24	
33.10/10.24	(8) SCC2IRS (SOUND)
33.10/10.24	Transformed LLVM symbolic execution graph SCC into a rewrite problem. Log: 
33.10/10.24	Generated rules. Obtained 25 rulesP rules:
33.10/10.24	f_442(v943, v944, v945, v946, v947, v948, v949, v950, 0, v956, v953, 1, v952, v955, v957, v958, v959, v960, v961, v962, v963, 3, 2, 4) -> f_443(v943, v944, v945, v946, v947, v948, v949, v950, 0, v956, v953, 1, v952, v955, v957, v958, v959, v960, v961, v962, v963, 3, 2, 4) :|: 0 = 0
33.10/10.24	f_443(v943, v944, v945, v946, v947, v948, v949, v950, 0, v956, v953, 1, v952, v955, v957, v958, v959, v960, v961, v962, v963, 3, 2, 4) -> f_444(v943, v944, v945, v946, v947, v948, v949, v950, 0, v956, v953, 1, v952, v955, v957, v958, v959, v960, v961, v962, v963, 3, 2, 4) :|: TRUE
33.10/10.24	f_444(v943, v944, v945, v946, v947, v948, v949, v950, 0, v956, v953, 1, v952, v955, v957, v958, v959, v960, v961, v962, v963, 3, 2, 4) -> f_445(v943, v944, v945, v946, v947, v948, v949, v950, 0, v956, v958, 1, v952, v955, v953, v957, v959, v960, v961, v962, v963, 3, 2, 4) :|: 0 = 0
33.10/10.24	f_445(v943, v944, v945, v946, v947, v948, v949, v950, 0, v956, v958, 1, v952, v955, v953, v957, v959, v960, v961, v962, v963, 3, 2, 4) -> f_446(v943, v944, v945, v946, v947, v948, v949, v950, 0, v956, v958, 1, v952, v955, v953, v957, v959, v960, v961, v962, v963, 3, 2, 4) :|: 0 <= v958 && 1 <= v953 && 1 <= v950
33.10/10.24	f_446(v943, v944, v945, v946, v947, v948, v949, v950, 0, v956, v958, 1, v952, v955, v953, v957, v959, v960, v961, v962, v963, 3, 2, 4) -> f_448(v943, v944, v945, v946, v947, v948, v949, v950, 0, v956, v958, 1, v952, v955, v953, v957, v959, v960, v961, v962, v963, 3, 2, 4) :|: 0 = 0
33.10/10.24	f_448(v943, v944, v945, v946, v947, v948, v949, v950, 0, v956, v958, 1, v952, v955, v953, v957, v959, v960, v961, v962, v963, 3, 2, 4) -> f_450(v943, v944, v945, v946, v947, v948, v949, v950, 0, v956, v958, 1, v952, v955, v953, v957, v959, v960, v961, v962, v963, 3, 2, 4) :|: 0 = 0
33.10/10.24	f_450(v943, v944, v945, v946, v947, v948, v949, v950, 0, v956, v958, 1, v952, v955, v953, v957, v959, v960, v961, v962, v963, 3, 2, 4) -> f_451(v943, v944, v945, v946, v947, v948, v949, v950, 0, v956, 1, v952, v955, v953, v957, v958, v959, v960, v961, v962, v963, 3, 4) :|: TRUE
33.10/10.24	f_451(v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, 0, v1022, 1, v1024, v1025, v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 3, 4) -> f_453(v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, 0, v1022, 1, v1024, v1025, v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 3, 4) :|: TRUE
33.10/10.24	f_453(v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, 0, v1022, 1, v1024, v1025, v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 3, 4) -> f_455(v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, 0, v1022, 1, v1025, v1024, v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 3, 4) :|: 0 = 0
33.10/10.24	f_455(v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, 0, v1022, 1, v1025, v1024, v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 3, 4) -> f_457(v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, 0, v1022, 1, v1025, v1024, v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 3, 4) :|: 0 = 0
33.10/10.24	f_457(v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, 0, v1022, 1, v1025, v1024, v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 3, 4) -> f_459(v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, 0, v1022, 1, v1105, v1024, v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 3, 4) :|: v1105 = v1022 + v1018
33.10/10.24	f_459(v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, 0, v1022, 1, v1105, v1024, v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 3, 4) -> f_461(v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, 0, v1022, 1, v1105, v1024, v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 3, 4) :|: 0 = 0
33.10/10.24	f_461(v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, 0, v1022, 1, v1105, v1024, v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 3, 4) -> f_462(v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, 0, v1022, 1, v1105, v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 3, 4) :|: v1022 + v1018 = v1105
33.10/10.24	f_462(v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, 0, v1022, 1, v1105, v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 3, 4) -> f_463(v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, 0, v1022, 1, v1105, v1106, v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 3, 4, 2) :|: 1 + v1106 = v1022 && 2 + v1106 <= 0
33.10/10.24	f_463(v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, 0, v1022, 1, v1105, v1106, v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 3, 4, 2) -> f_464(v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, 0, v1022, 1, v1105, v1106, v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 3, 4, 2) :|: TRUE
33.10/10.24	f_464(v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, 0, v1022, 1, v1105, v1106, v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 3, 4, 2) -> f_465(v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, 0, v1022, 1, v1105, v1106, v1028, v1027, v1026, v1029, v1030, v1031, v1032, v1033, 3, 4, 2) :|: 0 = 0
33.10/10.24	f_465(v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, 0, v1022, 1, v1105, v1106, v1028, v1027, v1026, v1029, v1030, v1031, v1032, v1033, 3, 4, 2) -> f_466(v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, 0, v1022, 1, v1105, v1106, v1028, v1027, v1026, v1029, v1030, v1031, v1032, v1033, 3, 4, 2) :|: 0 = 0
33.10/10.24	f_466(v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, 0, v1022, 1, v1105, v1106, v1028, v1027, v1026, v1029, v1030, v1031, v1032, v1033, 3, 4, 2) -> f_467(v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, 0, v1022, 1, v1105, v1106, v1028, v1108, v1026, v1029, v1030, v1031, v1032, v1033, 3, 4, 2) :|: v1108 = v1028 + v1018
33.10/10.24	f_467(v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, 0, v1022, 1, v1105, v1106, v1028, v1108, v1026, v1029, v1030, v1031, v1032, v1033, 3, 4, 2) -> f_468(v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, 0, v1022, 1, v1105, v1106, v1028, v1108, v1026, v1029, v1030, v1031, v1032, v1033, 3, 4, 2) :|: 0 = 0
33.10/10.24	f_468(v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, 0, v1022, 1, v1105, v1106, v1028, v1108, v1026, v1029, v1030, v1031, v1032, v1033, 3, 4, 2) -> f_469(v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, 0, v1022, 1, v1105, v1106, v1028, v1108, v1029, v1030, v1031, v1032, v1033, 3, 4, 2) :|: v1028 + v1018 = v1108
33.10/10.24	f_469(v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, 0, v1022, 1, v1105, v1106, v1028, v1108, v1029, v1030, v1031, v1032, v1033, 3, 4, 2) -> f_470(v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, 0, v1022, 1, v1105, v1106, v1028, v1108, v1109, v1029, v1030, v1031, v1032, v1033, 3, 4, 2) :|: 1 + v1109 = v1028 && 0 <= 1 + v1109
33.10/10.24	f_470(v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, 0, v1022, 1, v1105, v1106, v1028, v1108, v1109, v1029, v1030, v1031, v1032, v1033, 3, 4, 2) -> f_471(v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, 0, v1022, 1, v1105, v1106, v1028, v1108, v1109, v1029, v1030, v1031, v1032, v1033, 3, 4, 2) :|: TRUE
33.10/10.24	f_471(v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, 0, v1022, 1, v1105, v1106, v1028, v1108, v1109, v1029, v1030, v1031, v1032, v1033, 3, 4, 2) -> f_472(v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, 0, v1022, 1, v1105, v1106, v1028, v1108, v1109, v1029, v1030, v1031, v1032, v1033, 3, 4, 2) :|: TRUE
33.10/10.24	f_472(v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, 0, v1022, 1, v1105, v1106, v1028, v1108, v1109, v1029, v1030, v1031, v1032, v1033, 3, 4, 2) -> f_441(v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, 0, v1022, v1028, 1, v1105, v1106, v1108, v1109, v1029, v1030, v1031, v1032, v1033, 3, 2, 4) :|: TRUE
33.10/10.24	f_441(v943, v944, v945, v946, v947, v948, v949, v950, 0, v952, v953, 1, v955, v956, v957, v958, v959, v960, v961, v962, v963, 3, 2, 4) -> f_442(v943, v944, v945, v946, v947, v948, v949, v950, 0, v956, v953, 1, v952, v955, v957, v958, v959, v960, v961, v962, v963, 3, 2, 4) :|: 0 = 0
33.10/10.24	Combined rules. Obtained 1 rulesP rules:
33.10/10.24	f_442(v943:0, v944:0, v945:0, v946:0, v947:0, v948:0, v949:0, v950:0, 0, 1 + v1106:0, v953:0, 1, v952:0, v955:0, v957:0, 1 + v1109:0, v959:0, v960:0, v961:0, v962:0, v963:0, 3, 2, 4) -> f_442(v943:0, v944:0, v945:0, v946:0, v947:0, v948:0, v949:0, v950:0, 0, v1106:0, 1 + v1109:0, 1, 1 + v1106:0, 1 + v1106:0 + v948:0, 1 + v1109:0 + v948:0, v1109:0, v959:0, v960:0, v961:0, v962:0, v963:0, 3, 2, 4) :|: v953:0 > 0 && v1109:0 > -2 && v950:0 > 0 && v1106:0 < -1
33.10/10.24	Filtered unneeded arguments:
33.10/10.24	   f_442(x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, x16, x17, x18, x19, x20, x21, x22, x23, x24) -> f_442(x8, x10, x11, x16)
33.10/10.24	Removed division, modulo operations, cleaned up constraints. Obtained 1 rules.P rules:
33.10/10.24	f_442(v950:0, sum~cons_1~v1106:0, v953:0, sum~cons_1~v1109:0) -> f_442(v950:0, v1106:0, 1 + v1109:0, v1109:0) :|: v1109:0 > -2 && v953:0 > 0 && v1106:0 < -1 && v950:0 > 0 && sum~cons_1~v1106:0 = 1 + v1106:0 && sum~cons_1~v1109:0 = 1 + v1109:0
33.10/10.24	
33.10/10.24	----------------------------------------
33.10/10.24	
33.10/10.24	(9)
33.10/10.24	Obligation:
33.10/10.24	Rules:
33.10/10.24	f_442(v950:0, sum~cons_1~v1106:0, v953:0, sum~cons_1~v1109:0) -> f_442(v950:0, v1106:0, 1 + v1109:0, v1109:0) :|: v1109:0 > -2 && v953:0 > 0 && v1106:0 < -1 && v950:0 > 0 && sum~cons_1~v1106:0 = 1 + v1106:0 && sum~cons_1~v1109:0 = 1 + v1109:0
33.10/10.24	
33.10/10.24	----------------------------------------
33.10/10.24	
33.10/10.24	(10) IntTRSCompressionProof (EQUIVALENT)
33.10/10.24	Compressed rules.
33.10/10.24	----------------------------------------
33.10/10.24	
33.10/10.24	(11)
33.10/10.24	Obligation:
33.10/10.24	Rules:
33.10/10.24	f_442(v950:0:0, sum~cons_1~v1106:0:0, v953:0:0, sum~cons_1~v1109:0:0) -> f_442(v950:0:0, v1106:0:0, 1 + v1109:0:0, v1109:0:0) :|: v1106:0:0 < -1 && v950:0:0 > 0 && v953:0:0 > 0 && v1109:0:0 > -2 && sum~cons_1~v1106:0:0 = 1 + v1106:0:0 && sum~cons_1~v1109:0:0 = 1 + v1109:0:0
33.10/10.24	
33.10/10.24	----------------------------------------
33.10/10.24	
33.10/10.24	(12) PolynomialOrderProcessor (EQUIVALENT)
33.10/10.24	Found the following polynomial interpretation:
33.10/10.24	[f_442(x, x1, x2, x3)] = x3
33.10/10.24	
33.10/10.24	The following rules are decreasing:
33.10/10.24	f_442(v950:0:0, sum~cons_1~v1106:0:0, v953:0:0, sum~cons_1~v1109:0:0) -> f_442(v950:0:0, v1106:0:0, 1 + v1109:0:0, v1109:0:0) :|: v1106:0:0 < -1 && v950:0:0 > 0 && v953:0:0 > 0 && v1109:0:0 > -2 && sum~cons_1~v1106:0:0 = 1 + v1106:0:0 && sum~cons_1~v1109:0:0 = 1 + v1109:0:0
33.10/10.24	The following rules are bounded:
33.10/10.24	f_442(v950:0:0, sum~cons_1~v1106:0:0, v953:0:0, sum~cons_1~v1109:0:0) -> f_442(v950:0:0, v1106:0:0, 1 + v1109:0:0, v1109:0:0) :|: v1106:0:0 < -1 && v950:0:0 > 0 && v953:0:0 > 0 && v1109:0:0 > -2 && sum~cons_1~v1106:0:0 = 1 + v1106:0:0 && sum~cons_1~v1109:0:0 = 1 + v1109:0:0
33.10/10.24	
33.10/10.24	----------------------------------------
33.10/10.24	
33.10/10.24	(13)
33.10/10.24	YES
33.10/10.24	
33.10/10.24	----------------------------------------
33.10/10.24	
33.10/10.24	(14)
33.10/10.24	Obligation:
33.10/10.24	SCC
33.10/10.24	----------------------------------------
33.10/10.24	
33.10/10.24	(15) SCC2IRS (SOUND)
33.10/10.24	Transformed LLVM symbolic execution graph SCC into a rewrite problem. Log: 
33.10/10.24	Generated rules. Obtained 21 rulesP rules:
33.10/10.24	f_360(v579, v580, v581, v582, v583, v584, v585, v586, 0, v591, 1, v588, v590, v592, v593, v594, v595, v596, v597, v598, v599, 3, 4) -> f_362(v579, v580, v581, v582, v583, v584, v585, v586, 0, v591, 1, v588, v590, v592, v593, v594, v595, v596, v597, v598, v599, 3, 4) :|: 0 <= v591 && 1 <= v588 && 1 <= v585
33.10/10.24	f_362(v579, v580, v581, v582, v583, v584, v585, v586, 0, v591, 1, v588, v590, v592, v593, v594, v595, v596, v597, v598, v599, 3, 4) -> f_365(v579, v580, v581, v582, v583, v584, v585, v586, 0, v591, 1, v588, v590, v592, v593, v594, v595, v596, v597, v598, v599, 3, 4) :|: 0 = 0
33.10/10.24	f_365(v579, v580, v581, v582, v583, v584, v585, v586, 0, v591, 1, v588, v590, v592, v593, v594, v595, v596, v597, v598, v599, 3, 4) -> f_368(v579, v580, v581, v582, v583, v584, v585, v586, 0, v591, 1, v588, v590, v592, v593, v594, v595, v596, v597, v598, v599, 3, 4) :|: 0 = 0
33.10/10.24	f_368(v579, v580, v581, v582, v583, v584, v585, v586, 0, v591, 1, v588, v590, v592, v593, v594, v595, v596, v597, v598, v599, 3, 4) -> f_371(v579, v580, v581, v582, v583, v584, v585, v586, 0, v591, 1, v588, v590, v592, v593, v594, v595, v596, v597, v598, v599, 3, 4) :|: TRUE
33.10/10.24	f_371(v579, v580, v581, v582, v583, v584, v585, v586, 0, v591, 1, v588, v590, v592, v593, v594, v595, v596, v597, v598, v599, 3, 4) -> f_374(v579, v580, v581, v582, v583, v584, v585, v586, 0, v591, 1, v590, v588, v592, v593, v594, v595, v596, v597, v598, v599, 3, 4) :|: 0 = 0
33.10/10.24	f_374(v579, v580, v581, v582, v583, v584, v585, v586, 0, v591, 1, v590, v588, v592, v593, v594, v595, v596, v597, v598, v599, 3, 4) -> f_378(v579, v580, v581, v582, v583, v584, v585, v586, 0, v591, 1, v590, v588, v592, v593, v594, v595, v596, v597, v598, v599, 3, 4) :|: 0 = 0
33.10/10.24	f_378(v579, v580, v581, v582, v583, v584, v585, v586, 0, v591, 1, v590, v588, v592, v593, v594, v595, v596, v597, v598, v599, 3, 4) -> f_382(v579, v580, v581, v582, v583, v584, v585, v586, 0, v591, 1, v655, v588, v592, v593, v594, v595, v596, v597, v598, v599, 3, 4) :|: v655 = v591 + v584
33.10/10.24	f_382(v579, v580, v581, v582, v583, v584, v585, v586, 0, v591, 1, v655, v588, v592, v593, v594, v595, v596, v597, v598, v599, 3, 4) -> f_386(v579, v580, v581, v582, v583, v584, v585, v586, 0, v591, 1, v655, v588, v592, v593, v594, v595, v596, v597, v598, v599, 3, 4) :|: 0 = 0
33.10/10.24	f_386(v579, v580, v581, v582, v583, v584, v585, v586, 0, v591, 1, v655, v588, v592, v593, v594, v595, v596, v597, v598, v599, 3, 4) -> f_390(v579, v580, v581, v582, v583, v584, v585, v586, 0, v591, 1, v655, v592, v593, v594, v595, v596, v597, v598, v599, 3, 4) :|: v591 + v584 = v655
33.10/10.24	f_390(v579, v580, v581, v582, v583, v584, v585, v586, 0, v591, 1, v655, v592, v593, v594, v595, v596, v597, v598, v599, 3, 4) -> f_395(v579, v580, v581, v582, v583, v584, v585, v586, 0, v591, 1, v655, v780, v592, v593, v594, v595, v596, v597, v598, v599, 3, 4) :|: 1 + v780 = v591 && 0 <= 1 + v780
33.10/10.24	f_395(v579, v580, v581, v582, v583, v584, v585, v586, 0, v591, 1, v655, v780, v592, v593, v594, v595, v596, v597, v598, v599, 3, 4) -> f_399(v579, v580, v581, v582, v583, v584, v585, v586, 0, v591, 1, v655, v780, v592, v593, v594, v595, v596, v597, v598, v599, 3, 4) :|: TRUE
33.10/10.24	f_399(v579, v580, v581, v582, v583, v584, v585, v586, 0, v591, 1, v655, v780, v592, v593, v594, v595, v596, v597, v598, v599, 3, 4) -> f_403(v579, v580, v581, v582, v583, v584, v585, v586, 0, v591, 1, v655, v780, v594, v593, v592, v595, v596, v597, v598, v599, 3, 4) :|: 0 = 0
33.10/10.24	f_403(v579, v580, v581, v582, v583, v584, v585, v586, 0, v591, 1, v655, v780, v594, v593, v592, v595, v596, v597, v598, v599, 3, 4) -> f_406(v579, v580, v581, v582, v583, v584, v585, v586, 0, v591, 1, v655, v780, v594, v593, v592, v595, v596, v597, v598, v599, 3, 4) :|: 0 = 0
33.10/10.24	f_406(v579, v580, v581, v582, v583, v584, v585, v586, 0, v591, 1, v655, v780, v594, v593, v592, v595, v596, v597, v598, v599, 3, 4) -> f_409(v579, v580, v581, v582, v583, v584, v585, v586, 0, v591, 1, v655, v780, v594, v796, v592, v595, v596, v597, v598, v599, 3, 4) :|: v796 = v594 + v584
33.10/10.24	f_409(v579, v580, v581, v582, v583, v584, v585, v586, 0, v591, 1, v655, v780, v594, v796, v592, v595, v596, v597, v598, v599, 3, 4) -> f_413(v579, v580, v581, v582, v583, v584, v585, v586, 0, v591, 1, v655, v780, v594, v796, v592, v595, v596, v597, v598, v599, 3, 4) :|: 0 = 0
33.10/10.24	f_413(v579, v580, v581, v582, v583, v584, v585, v586, 0, v591, 1, v655, v780, v594, v796, v592, v595, v596, v597, v598, v599, 3, 4) -> f_417(v579, v580, v581, v582, v583, v584, v585, v586, 0, v591, 1, v655, v780, v594, v796, v595, v596, v597, v598, v599, 3, 4) :|: v594 + v584 = v796
33.10/10.24	f_417(v579, v580, v581, v582, v583, v584, v585, v586, 0, v591, 1, v655, v780, v594, v796, v595, v596, v597, v598, v599, 3, 4) -> f_421(v579, v580, v581, v582, v583, v584, v585, v586, 0, v591, 1, v655, v780, v594, v796, v864, v595, v596, v597, v598, v599, 3, 4) :|: 1 + v864 = v594
33.10/10.24	f_421(v579, v580, v581, v582, v583, v584, v585, v586, 0, v591, 1, v655, v780, v594, v796, v864, v595, v596, v597, v598, v599, 3, 4) -> f_425(v579, v580, v581, v582, v583, v584, v585, v586, 0, v591, 1, v655, v780, v594, v796, v864, v595, v596, v597, v598, v599, 3, 4) :|: TRUE
33.10/10.24	f_425(v579, v580, v581, v582, v583, v584, v585, v586, 0, v591, 1, v655, v780, v594, v796, v864, v595, v596, v597, v598, v599, 3, 4) -> f_429(v579, v580, v581, v582, v583, v584, v585, v586, 0, v591, 1, v655, v780, v594, v796, v864, v595, v596, v597, v598, v599, 3, 4) :|: TRUE
33.10/10.24	f_429(v579, v580, v581, v582, v583, v584, v585, v586, 0, v591, 1, v655, v780, v594, v796, v864, v595, v596, v597, v598, v599, 3, 4) -> f_358(v579, v580, v581, v582, v583, v584, v585, v586, 0, v591, 1, v655, v780, v594, v796, v864, v595, v596, v597, v598, v599, 3, 4) :|: TRUE
33.10/10.24	f_358(v579, v580, v581, v582, v583, v584, v585, v586, 0, v588, 1, v590, v591, v592, v593, v594, v595, v596, v597, v598, v599, 3, 4) -> f_360(v579, v580, v581, v582, v583, v584, v585, v586, 0, v591, 1, v588, v590, v592, v593, v594, v595, v596, v597, v598, v599, 3, 4) :|: 0 = 0
33.10/10.24	Combined rules. Obtained 1 rulesP rules:
33.10/10.24	f_360(v579:0, v580:0, v581:0, v582:0, v583:0, v584:0, v585:0, v586:0, 0, 1 + v780:0, 1, v588:0, v590:0, v592:0, v593:0, 1 + v864:0, v595:0, v596:0, v597:0, v598:0, v599:0, 3, 4) -> f_360(v579:0, v580:0, v581:0, v582:0, v583:0, v584:0, v585:0, v586:0, 0, v780:0, 1, 1 + v780:0, 1 + v780:0 + v584:0, 1 + v864:0, 1 + v864:0 + v584:0, v864:0, v595:0, v596:0, v597:0, v598:0, v599:0, 3, 4) :|: v588:0 > 0 && v780:0 > -2 && v585:0 > 0
33.10/10.24	Filtered unneeded arguments:
33.10/10.24	   f_360(x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, x16, x17, x18, x19, x20, x21, x22, x23) -> f_360(x7, x10, x12, x16)
33.10/10.24	Removed division, modulo operations, cleaned up constraints. Obtained 1 rules.P rules:
33.10/10.24	f_360(v585:0, sum~cons_1~v780:0, v588:0, sum~cons_1~v864:0) -> f_360(v585:0, v780:0, 1 + v780:0, v864:0) :|: v780:0 > -2 && v585:0 > 0 && v588:0 > 0 && sum~cons_1~v780:0 = 1 + v780:0 && sum~cons_1~v864:0 = 1 + v864:0
33.10/10.24	
33.10/10.24	----------------------------------------
33.10/10.24	
33.10/10.24	(16)
33.10/10.24	Obligation:
33.10/10.24	Rules:
33.10/10.24	f_360(v585:0, sum~cons_1~v780:0, v588:0, sum~cons_1~v864:0) -> f_360(v585:0, v780:0, 1 + v780:0, v864:0) :|: v780:0 > -2 && v585:0 > 0 && v588:0 > 0 && sum~cons_1~v780:0 = 1 + v780:0 && sum~cons_1~v864:0 = 1 + v864:0
33.10/10.24	
33.10/10.24	----------------------------------------
33.10/10.24	
33.10/10.24	(17) IntTRSCompressionProof (EQUIVALENT)
33.10/10.24	Compressed rules.
33.10/10.24	----------------------------------------
33.10/10.24	
33.10/10.24	(18)
33.10/10.24	Obligation:
33.10/10.24	Rules:
33.10/10.24	f_360(v585:0:0, sum~cons_1~v780:0:0, v588:0:0, sum~cons_1~v864:0:0) -> f_360(v585:0:0, v780:0:0, 1 + v780:0:0, v864:0:0) :|: v780:0:0 > -2 && v585:0:0 > 0 && v588:0:0 > 0 && sum~cons_1~v780:0:0 = 1 + v780:0:0 && sum~cons_1~v864:0:0 = 1 + v864:0:0
33.10/10.24	
33.10/10.24	----------------------------------------
33.10/10.24	
33.10/10.24	(19) RankingReductionPairProof (EQUIVALENT)
33.10/10.24	Interpretation:
33.10/10.24	[ f_360 ] = f_360_2
33.10/10.24	
33.10/10.24	The following rules are decreasing:
33.10/10.24	f_360(v585:0:0, sum~cons_1~v780:0:0, v588:0:0, sum~cons_1~v864:0:0) -> f_360(v585:0:0, v780:0:0, 1 + v780:0:0, v864:0:0) :|: v780:0:0 > -2 && v585:0:0 > 0 && v588:0:0 > 0 && sum~cons_1~v780:0:0 = 1 + v780:0:0 && sum~cons_1~v864:0:0 = 1 + v864:0:0
33.10/10.24	
33.10/10.24	The following rules are bounded:
33.10/10.24	f_360(v585:0:0, sum~cons_1~v780:0:0, v588:0:0, sum~cons_1~v864:0:0) -> f_360(v585:0:0, v780:0:0, 1 + v780:0:0, v864:0:0) :|: v780:0:0 > -2 && v585:0:0 > 0 && v588:0:0 > 0 && sum~cons_1~v780:0:0 = 1 + v780:0:0 && sum~cons_1~v864:0:0 = 1 + v864:0:0
33.10/10.24	
33.10/10.24	
33.10/10.24	----------------------------------------
33.10/10.24	
33.10/10.24	(20)
33.10/10.24	YES
33.52/12.91	EOF