33.77/12.79 NO 33.77/12.79 33.77/12.79 Ultimate: Cannot open display: 33.77/12.79 This is Ultimate 0.1.24-8dc7c08-m 33.77/12.79 [2019-03-28 12:21:59,827 INFO L170 SettingsManager]: Resetting all preferences to default values... 33.77/12.79 [2019-03-28 12:21:59,830 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values 33.77/12.79 [2019-03-28 12:21:59,842 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... 33.77/12.79 [2019-03-28 12:21:59,842 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values 33.77/12.79 [2019-03-28 12:21:59,843 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values 33.77/12.79 [2019-03-28 12:21:59,844 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values 33.77/12.79 [2019-03-28 12:21:59,846 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values 33.77/12.79 [2019-03-28 12:21:59,848 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values 33.77/12.79 [2019-03-28 12:21:59,848 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values 33.77/12.79 [2019-03-28 12:21:59,849 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... 33.77/12.79 [2019-03-28 12:21:59,850 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values 33.77/12.79 [2019-03-28 12:21:59,851 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values 33.77/12.79 [2019-03-28 12:21:59,852 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values 33.77/12.79 [2019-03-28 12:21:59,853 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values 33.77/12.79 [2019-03-28 12:21:59,853 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values 33.77/12.79 [2019-03-28 12:21:59,854 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values 33.77/12.79 [2019-03-28 12:21:59,856 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values 33.77/12.79 [2019-03-28 12:21:59,858 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values 33.77/12.79 [2019-03-28 12:21:59,859 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values 33.77/12.79 [2019-03-28 12:21:59,860 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values 33.77/12.79 [2019-03-28 12:21:59,862 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values 33.77/12.79 [2019-03-28 12:21:59,864 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 33.77/12.79 [2019-03-28 12:21:59,864 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... 33.77/12.79 [2019-03-28 12:21:59,864 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values 33.77/12.79 [2019-03-28 12:21:59,865 INFO L174 SettingsManager]: Resetting IcfgToChc preferences to default values 33.77/12.79 [2019-03-28 12:21:59,866 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values 33.77/12.79 [2019-03-28 12:21:59,867 INFO L177 SettingsManager]: ReqToTest provides no preferences, ignoring... 33.77/12.79 [2019-03-28 12:21:59,867 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values 33.77/12.79 [2019-03-28 12:21:59,867 INFO L174 SettingsManager]: Resetting ChcSmtPrinter preferences to default values 33.77/12.79 [2019-03-28 12:21:59,868 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values 33.77/12.79 [2019-03-28 12:21:59,869 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values 33.77/12.79 [2019-03-28 12:21:59,870 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... 33.77/12.79 [2019-03-28 12:21:59,870 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values 33.77/12.79 [2019-03-28 12:21:59,871 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... 33.77/12.79 [2019-03-28 12:21:59,871 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... 33.77/12.79 [2019-03-28 12:21:59,871 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values 33.77/12.79 [2019-03-28 12:21:59,872 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values 33.77/12.79 [2019-03-28 12:21:59,873 INFO L181 SettingsManager]: Finished resetting all preferences to default values... 33.77/12.79 [2019-03-28 12:21:59,873 INFO L98 SettingsManager]: Beginning loading settings from /export/starexec/sandbox/solver/bin/./../termcomp2017.epf 33.77/12.79 [2019-03-28 12:21:59,888 INFO L110 SettingsManager]: Loading preferences was successful 33.77/12.79 [2019-03-28 12:21:59,888 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: 33.77/12.79 [2019-03-28 12:21:59,890 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: 33.77/12.79 [2019-03-28 12:21:59,890 INFO L133 SettingsManager]: * Rewrite not-equals=true 33.77/12.79 [2019-03-28 12:21:59,890 INFO L133 SettingsManager]: * Create parallel compositions if possible=false 33.77/12.79 [2019-03-28 12:21:59,890 INFO L133 SettingsManager]: * Minimize states using LBE with the strategy=SINGLE 33.77/12.79 [2019-03-28 12:21:59,890 INFO L133 SettingsManager]: * Use SBE=true 33.77/12.79 [2019-03-28 12:21:59,891 INFO L131 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: 33.77/12.79 [2019-03-28 12:21:59,891 INFO L133 SettingsManager]: * Use old map elimination=false 33.77/12.79 [2019-03-28 12:21:59,891 INFO L133 SettingsManager]: * Use external solver (rank synthesis)=false 33.77/12.79 [2019-03-28 12:21:59,891 INFO L133 SettingsManager]: * Buchi interpolant automaton construction strategy=DANDELION 33.77/12.79 [2019-03-28 12:21:59,891 INFO L133 SettingsManager]: * Use only trivial implications for array writes=true 33.77/12.79 [2019-03-28 12:21:59,892 INFO L133 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES 33.77/12.79 [2019-03-28 12:21:59,892 INFO L133 SettingsManager]: * Construct termination proof for TermComp=true 33.77/12.79 [2019-03-28 12:21:59,892 INFO L133 SettingsManager]: * Command for external solver (GNTA synthesis)=z3 SMTLIB2_COMPLIANT=true -memory:4560 -smt2 -in -t:12000 33.77/12.79 [2019-03-28 12:21:59,892 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: 33.77/12.79 [2019-03-28 12:21:59,892 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false 33.77/12.79 [2019-03-28 12:21:59,892 INFO L133 SettingsManager]: * Check division by zero=IGNORE 33.77/12.79 [2019-03-28 12:21:59,893 INFO L133 SettingsManager]: * Check if freed pointer was valid=false 33.77/12.79 [2019-03-28 12:21:59,893 INFO L133 SettingsManager]: * Assume nondeterminstic values are in range=false 33.77/12.79 [2019-03-28 12:21:59,893 INFO L133 SettingsManager]: * How to treat unsigned ints differently from normal ones=IGNORE 33.77/12.79 [2019-03-28 12:21:59,893 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: 33.77/12.79 [2019-03-28 12:21:59,893 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements 33.77/12.79 [2019-03-28 12:21:59,894 INFO L133 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump 33.77/12.79 [2019-03-28 12:21:59,894 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:4560 -smt2 -in -t:5000 33.77/12.79 [2019-03-28 12:21:59,894 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: 33.77/12.79 [2019-03-28 12:21:59,894 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles 33.77/12.79 [2019-03-28 12:21:59,894 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL 33.77/12.79 [2019-03-28 12:21:59,895 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true 33.77/12.79 [2019-03-28 12:21:59,921 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp 33.77/12.79 [2019-03-28 12:21:59,934 INFO L259 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized 33.77/12.79 [2019-03-28 12:21:59,938 INFO L215 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. 33.77/12.79 [2019-03-28 12:21:59,939 INFO L271 PluginConnector]: Initializing CDTParser... 33.77/12.79 [2019-03-28 12:21:59,940 INFO L276 PluginConnector]: CDTParser initialized 33.77/12.79 [2019-03-28 12:21:59,940 INFO L430 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /export/starexec/sandbox/benchmark/theBenchmark.c 33.77/12.79 [2019-03-28 12:22:00,010 INFO L221 CDTParser]: Created temporary CDT project at /export/starexec/sandbox/tmp/36288334e4e445609463a94be2ca3d62/FLAGe9855274f 33.77/12.79 [2019-03-28 12:22:00,363 INFO L307 CDTParser]: Found 1 translation units. 33.77/12.79 [2019-03-28 12:22:00,363 INFO L161 CDTParser]: Scanning /export/starexec/sandbox/benchmark/theBenchmark.c 33.77/12.79 [2019-03-28 12:22:00,373 INFO L355 CDTParser]: About to delete temporary CDT project at /export/starexec/sandbox/tmp/36288334e4e445609463a94be2ca3d62/FLAGe9855274f 33.77/12.79 [2019-03-28 12:22:00,797 INFO L363 CDTParser]: Successfully deleted /export/starexec/sandbox/tmp/36288334e4e445609463a94be2ca3d62 33.77/12.79 [2019-03-28 12:22:00,809 INFO L297 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### 33.77/12.79 [2019-03-28 12:22:00,810 INFO L131 ToolchainWalker]: Walking toolchain with 7 elements. 33.77/12.79 [2019-03-28 12:22:00,811 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- 33.77/12.79 [2019-03-28 12:22:00,811 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... 33.77/12.79 [2019-03-28 12:22:00,815 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized 33.77/12.79 [2019-03-28 12:22:00,816 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.03 12:22:00" (1/1) ... 33.77/12.79 [2019-03-28 12:22:00,820 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6161d2d1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:22:00, skipping insertion in model container 33.77/12.79 [2019-03-28 12:22:00,820 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.03 12:22:00" (1/1) ... 33.77/12.79 [2019-03-28 12:22:00,827 INFO L145 MainTranslator]: Starting translation in SV-COMP mode 33.77/12.79 [2019-03-28 12:22:00,858 INFO L176 MainTranslator]: Built tables and reachable declarations 33.77/12.79 [2019-03-28 12:22:01,052 INFO L206 PostProcessor]: Analyzing one entry point: main 33.77/12.79 [2019-03-28 12:22:01,060 INFO L191 MainTranslator]: Completed pre-run 33.77/12.79 [2019-03-28 12:22:01,162 INFO L206 PostProcessor]: Analyzing one entry point: main 33.77/12.79 [2019-03-28 12:22:01,181 INFO L195 MainTranslator]: Completed translation 33.77/12.79 [2019-03-28 12:22:01,182 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:22:01 WrapperNode 33.77/12.79 [2019-03-28 12:22:01,182 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- 33.77/12.79 [2019-03-28 12:22:01,183 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- 33.77/12.79 [2019-03-28 12:22:01,183 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... 33.77/12.79 [2019-03-28 12:22:01,183 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized 33.77/12.79 [2019-03-28 12:22:01,193 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:22:01" (1/1) ... 33.77/12.79 [2019-03-28 12:22:01,201 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:22:01" (1/1) ... 33.77/12.79 [2019-03-28 12:22:01,236 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- 33.77/12.79 [2019-03-28 12:22:01,237 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- 33.77/12.79 [2019-03-28 12:22:01,237 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... 33.77/12.79 [2019-03-28 12:22:01,237 INFO L276 PluginConnector]: Boogie Preprocessor initialized 33.77/12.79 [2019-03-28 12:22:01,247 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:22:01" (1/1) ... 33.77/12.79 [2019-03-28 12:22:01,247 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:22:01" (1/1) ... 33.77/12.79 [2019-03-28 12:22:01,251 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:22:01" (1/1) ... 33.77/12.79 [2019-03-28 12:22:01,251 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:22:01" (1/1) ... 33.77/12.79 [2019-03-28 12:22:01,258 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:22:01" (1/1) ... 33.77/12.79 [2019-03-28 12:22:01,269 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:22:01" (1/1) ... 33.77/12.79 [2019-03-28 12:22:01,271 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:22:01" (1/1) ... 33.77/12.79 [2019-03-28 12:22:01,275 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- 33.77/12.79 [2019-03-28 12:22:01,275 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- 33.77/12.79 [2019-03-28 12:22:01,275 INFO L271 PluginConnector]: Initializing RCFGBuilder... 33.77/12.79 [2019-03-28 12:22:01,276 INFO L276 PluginConnector]: RCFGBuilder initialized 33.77/12.79 [2019-03-28 12:22:01,277 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:22:01" (1/1) ... 33.77/12.79 No working directory specified, using /export/starexec/sandbox/solver/bin/z3 33.77/12.79 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:4560 -smt2 -in -t:5000 (exit command is (exit), workingDir is null) 33.77/12.79 Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:4560 -smt2 -in -t:5000 33.77/12.79 [2019-03-28 12:22:01,350 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start 33.77/12.79 [2019-03-28 12:22:01,350 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start 33.77/12.79 [2019-03-28 12:22:01,878 INFO L281 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) 33.77/12.79 [2019-03-28 12:22:01,878 INFO L286 CfgBuilder]: Removed 82 assue(true) statements. 33.77/12.79 [2019-03-28 12:22:01,879 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.03 12:22:01 BoogieIcfgContainer 33.77/12.79 [2019-03-28 12:22:01,880 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- 33.77/12.79 [2019-03-28 12:22:01,880 INFO L113 PluginConnector]: ------------------------BlockEncodingV2---------------------------- 33.77/12.79 [2019-03-28 12:22:01,880 INFO L271 PluginConnector]: Initializing BlockEncodingV2... 33.77/12.79 [2019-03-28 12:22:01,883 INFO L276 PluginConnector]: BlockEncodingV2 initialized 33.77/12.79 [2019-03-28 12:22:01,883 INFO L185 PluginConnector]: Executing the observer BlockEncodingObserver from plugin BlockEncodingV2 for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.03 12:22:01" (1/1) ... 33.77/12.79 [2019-03-28 12:22:01,909 INFO L313 BlockEncoder]: Initial Icfg 146 locations, 229 edges 33.77/12.79 [2019-03-28 12:22:01,911 INFO L258 BlockEncoder]: Using Remove infeasible edges 33.77/12.79 [2019-03-28 12:22:01,912 INFO L263 BlockEncoder]: Using Maximize final states 33.77/12.79 [2019-03-28 12:22:01,913 INFO L270 BlockEncoder]: Using Minimize states even if more edges are added than removed.=false 33.77/12.79 [2019-03-28 12:22:01,913 INFO L276 BlockEncoder]: Using Minimize states using LBE with the strategy=SINGLE 33.77/12.79 [2019-03-28 12:22:01,915 INFO L296 BlockEncoder]: Using Remove sink states 33.77/12.79 [2019-03-28 12:22:01,916 INFO L171 BlockEncoder]: Using Apply optimizations until nothing changes=true 33.77/12.79 [2019-03-28 12:22:01,916 INFO L179 BlockEncoder]: Using Rewrite not-equals 33.77/12.79 [2019-03-28 12:22:01,960 INFO L185 BlockEncoder]: Using Use SBE 33.77/12.79 [2019-03-28 12:22:02,006 INFO L200 BlockEncoder]: SBE split 72 edges 33.77/12.79 [2019-03-28 12:22:02,013 INFO L70 emoveInfeasibleEdges]: Removed 10 edges and 0 locations because of local infeasibility 33.77/12.79 [2019-03-28 12:22:02,016 INFO L71 MaximizeFinalStates]: 0 new accepting states 33.77/12.79 [2019-03-28 12:22:02,063 INFO L100 BaseMinimizeStates]: Removed 52 edges and 26 locations by large block encoding 33.77/12.79 [2019-03-28 12:22:02,065 INFO L70 RemoveSinkStates]: Removed 6 edges and 4 locations by removing sink states 33.77/12.79 [2019-03-28 12:22:02,067 INFO L70 emoveInfeasibleEdges]: Removed 0 edges and 0 locations because of local infeasibility 33.77/12.79 [2019-03-28 12:22:02,068 INFO L71 MaximizeFinalStates]: 0 new accepting states 33.77/12.79 [2019-03-28 12:22:02,074 INFO L100 BaseMinimizeStates]: Removed 4 edges and 2 locations by large block encoding 33.77/12.79 [2019-03-28 12:22:02,075 INFO L70 RemoveSinkStates]: Removed 0 edges and 0 locations by removing sink states 33.77/12.79 [2019-03-28 12:22:02,076 INFO L70 emoveInfeasibleEdges]: Removed 0 edges and 0 locations because of local infeasibility 33.77/12.79 [2019-03-28 12:22:02,076 INFO L71 MaximizeFinalStates]: 0 new accepting states 33.77/12.79 [2019-03-28 12:22:02,077 INFO L100 BaseMinimizeStates]: Removed 0 edges and 0 locations by large block encoding 33.77/12.79 [2019-03-28 12:22:02,077 INFO L70 RemoveSinkStates]: Removed 0 edges and 0 locations by removing sink states 33.77/12.79 [2019-03-28 12:22:02,078 INFO L313 BlockEncoder]: Encoded RCFG 114 locations, 257 edges 33.77/12.79 [2019-03-28 12:22:02,078 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.blockencoding CFG 28.03 12:22:02 BasicIcfg 33.77/12.79 [2019-03-28 12:22:02,079 INFO L132 PluginConnector]: ------------------------ END BlockEncodingV2---------------------------- 33.77/12.79 [2019-03-28 12:22:02,080 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- 33.77/12.79 [2019-03-28 12:22:02,080 INFO L271 PluginConnector]: Initializing TraceAbstraction... 33.77/12.79 [2019-03-28 12:22:02,083 INFO L276 PluginConnector]: TraceAbstraction initialized 33.77/12.79 [2019-03-28 12:22:02,084 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 28.03 12:22:00" (1/4) ... 33.77/12.79 [2019-03-28 12:22:02,084 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4cee6979 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.03 12:22:02, skipping insertion in model container 33.77/12.79 [2019-03-28 12:22:02,085 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:22:01" (2/4) ... 33.77/12.79 [2019-03-28 12:22:02,085 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4cee6979 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.03 12:22:02, skipping insertion in model container 33.77/12.79 [2019-03-28 12:22:02,085 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.03 12:22:01" (3/4) ... 33.77/12.79 [2019-03-28 12:22:02,086 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4cee6979 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.03 12:22:02, skipping insertion in model container 33.77/12.79 [2019-03-28 12:22:02,086 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.blockencoding CFG 28.03 12:22:02" (4/4) ... 33.77/12.79 [2019-03-28 12:22:02,088 INFO L112 eAbstractionObserver]: Analyzing ICFG theBenchmark.c_BEv2 33.77/12.79 [2019-03-28 12:22:02,098 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:ForwardPredicates Determinization: PREDICATE_ABSTRACTION 33.77/12.79 [2019-03-28 12:22:02,107 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 0 error locations. 33.77/12.79 [2019-03-28 12:22:02,125 INFO L257 AbstractCegarLoop]: Starting to check reachability of 0 error locations. 33.77/12.79 [2019-03-28 12:22:02,157 INFO L133 ementStrategyFactory]: Using default assertion order modulation 33.77/12.79 [2019-03-28 12:22:02,158 INFO L382 AbstractCegarLoop]: Interprodecural is true 33.77/12.79 [2019-03-28 12:22:02,158 INFO L383 AbstractCegarLoop]: Hoare is true 33.77/12.79 [2019-03-28 12:22:02,158 INFO L384 AbstractCegarLoop]: Compute interpolants for ForwardPredicates 33.77/12.79 [2019-03-28 12:22:02,158 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE 33.77/12.79 [2019-03-28 12:22:02,158 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION 33.77/12.79 [2019-03-28 12:22:02,159 INFO L387 AbstractCegarLoop]: Difference is false 33.77/12.79 [2019-03-28 12:22:02,159 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA 33.77/12.79 [2019-03-28 12:22:02,159 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== 33.77/12.79 [2019-03-28 12:22:02,176 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states. 33.77/12.79 [2019-03-28 12:22:02,185 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. 33.77/12.79 [2019-03-28 12:22:02,191 INFO L343 DoubleDeckerVisitor]: Before removal of dead ends 114 states. 33.77/12.79 [2019-03-28 12:22:02,284 INFO L448 ceAbstractionStarter]: For program point L225(lines 225 232) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,285 INFO L448 ceAbstractionStarter]: For program point L126(lines 126 135) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,285 INFO L451 ceAbstractionStarter]: At program point L93(lines 93 97) the Hoare annotation is: true 33.77/12.79 [2019-03-28 12:22:02,285 INFO L448 ceAbstractionStarter]: For program point L126-2(lines 126 135) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,285 INFO L448 ceAbstractionStarter]: For program point L126-3(lines 126 135) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,285 INFO L451 ceAbstractionStarter]: At program point L217(lines 217 221) the Hoare annotation is: true 33.77/12.79 [2019-03-28 12:22:02,286 INFO L448 ceAbstractionStarter]: For program point L126-5(lines 126 135) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,286 INFO L448 ceAbstractionStarter]: For program point L217-1(lines 212 250) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,286 INFO L448 ceAbstractionStarter]: For program point L126-6(lines 126 135) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,286 INFO L448 ceAbstractionStarter]: For program point L126-8(lines 126 135) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,286 INFO L448 ceAbstractionStarter]: For program point L126-9(lines 126 135) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,286 INFO L448 ceAbstractionStarter]: For program point L126-11(lines 126 135) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,287 INFO L448 ceAbstractionStarter]: For program point L126-12(lines 126 135) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,287 INFO L448 ceAbstractionStarter]: For program point L126-14(lines 126 135) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,287 INFO L451 ceAbstractionStarter]: At program point L449(lines 449 458) the Hoare annotation is: true 33.77/12.79 [2019-03-28 12:22:02,287 INFO L451 ceAbstractionStarter]: At program point L449-1(lines 449 458) the Hoare annotation is: true 33.77/12.79 [2019-03-28 12:22:02,287 INFO L448 ceAbstractionStarter]: For program point L127(lines 127 132) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,287 INFO L448 ceAbstractionStarter]: For program point L127-1(lines 127 132) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,288 INFO L451 ceAbstractionStarter]: At program point ULTIMATE.startENTRY(line -1) the Hoare annotation is: true 33.77/12.79 [2019-03-28 12:22:02,288 INFO L448 ceAbstractionStarter]: For program point L127-2(lines 127 132) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,288 INFO L448 ceAbstractionStarter]: For program point L127-3(lines 127 132) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,288 INFO L448 ceAbstractionStarter]: For program point L127-4(lines 127 132) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,288 INFO L451 ceAbstractionStarter]: At program point L276-1(lines 257 284) the Hoare annotation is: true 33.77/12.79 [2019-03-28 12:22:02,288 INFO L451 ceAbstractionStarter]: At program point L276-3(lines 257 284) the Hoare annotation is: true 33.77/12.79 [2019-03-28 12:22:02,289 INFO L451 ceAbstractionStarter]: At program point L177-1(lines 261 265) the Hoare annotation is: true 33.77/12.79 [2019-03-28 12:22:02,289 INFO L448 ceAbstractionStarter]: For program point L367-1(lines 361 384) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,289 INFO L451 ceAbstractionStarter]: At program point L202(lines 189 204) the Hoare annotation is: true 33.77/12.79 [2019-03-28 12:22:02,289 INFO L451 ceAbstractionStarter]: At program point L202-1(lines 189 204) the Hoare annotation is: true 33.77/12.79 [2019-03-28 12:22:02,289 INFO L451 ceAbstractionStarter]: At program point L202-2(lines 189 204) the Hoare annotation is: true 33.77/12.79 [2019-03-28 12:22:02,289 INFO L451 ceAbstractionStarter]: At program point L70(lines 33 84) the Hoare annotation is: true 33.77/12.79 [2019-03-28 12:22:02,290 INFO L451 ceAbstractionStarter]: At program point L37(lines 37 41) the Hoare annotation is: true 33.77/12.79 [2019-03-28 12:22:02,290 INFO L448 ceAbstractionStarter]: For program point L194(lines 194 199) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,290 INFO L448 ceAbstractionStarter]: For program point L194-1(lines 194 199) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,290 INFO L448 ceAbstractionStarter]: For program point L194-2(lines 194 199) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,290 INFO L448 ceAbstractionStarter]: For program point L145(lines 145 154) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,290 INFO L448 ceAbstractionStarter]: For program point L145-2(lines 145 154) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,290 INFO L448 ceAbstractionStarter]: For program point L145-3(lines 145 154) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,291 INFO L451 ceAbstractionStarter]: At program point L236(lines 212 250) the Hoare annotation is: true 33.77/12.79 [2019-03-28 12:22:02,291 INFO L448 ceAbstractionStarter]: For program point L145-5(lines 145 154) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,291 INFO L448 ceAbstractionStarter]: For program point L145-6(lines 145 154) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,291 INFO L451 ceAbstractionStarter]: At program point L137(lines 125 139) the Hoare annotation is: true 33.77/12.79 [2019-03-28 12:22:02,291 INFO L448 ceAbstractionStarter]: For program point L145-8(lines 145 154) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,291 INFO L451 ceAbstractionStarter]: At program point L137-1(lines 125 139) the Hoare annotation is: true 33.77/12.79 [2019-03-28 12:22:02,292 INFO L448 ceAbstractionStarter]: For program point L145-9(lines 145 154) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,292 INFO L448 ceAbstractionStarter]: For program point L71(lines 71 75) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,292 INFO L451 ceAbstractionStarter]: At program point L137-2(lines 125 139) the Hoare annotation is: true 33.77/12.79 [2019-03-28 12:22:02,292 INFO L451 ceAbstractionStarter]: At program point L137-3(lines 125 139) the Hoare annotation is: true 33.77/12.79 [2019-03-28 12:22:02,292 INFO L448 ceAbstractionStarter]: For program point L145-11(lines 145 154) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,292 INFO L448 ceAbstractionStarter]: For program point L294-1(lines 288 311) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,292 INFO L451 ceAbstractionStarter]: At program point L137-4(lines 125 139) the Hoare annotation is: true 33.77/12.79 [2019-03-28 12:22:02,293 INFO L448 ceAbstractionStarter]: For program point L145-12(lines 145 154) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,293 INFO L448 ceAbstractionStarter]: For program point L261-1(lines 260 283) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,293 INFO L448 ceAbstractionStarter]: For program point L261-2(lines 261 265) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,293 INFO L448 ceAbstractionStarter]: For program point L294-3(lines 288 311) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,293 INFO L448 ceAbstractionStarter]: For program point L145-14(lines 145 154) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,293 INFO L448 ceAbstractionStarter]: For program point L261-4(lines 260 283) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,293 INFO L448 ceAbstractionStarter]: For program point L146(lines 146 151) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,294 INFO L448 ceAbstractionStarter]: For program point L146-1(lines 146 151) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,294 INFO L448 ceAbstractionStarter]: For program point L146-2(lines 146 151) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,294 INFO L448 ceAbstractionStarter]: For program point L146-3(lines 146 151) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,294 INFO L448 ceAbstractionStarter]: For program point L146-4(lines 146 151) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,294 INFO L448 ceAbstractionStarter]: For program point L72(lines 72 74) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,294 INFO L448 ceAbstractionStarter]: For program point L64(lines 64 68) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,294 INFO L448 ceAbstractionStarter]: For program point L64-1(lines 63 77) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,295 INFO L451 ceAbstractionStarter]: At program point L411(lines 400 413) the Hoare annotation is: true 33.77/12.79 [2019-03-28 12:22:02,295 INFO L448 ceAbstractionStarter]: For program point L271-1(lines 260 283) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,295 INFO L451 ceAbstractionStarter]: At program point L304-3(lines 285 312) the Hoare annotation is: true 33.77/12.79 [2019-03-28 12:22:02,295 INFO L448 ceAbstractionStarter]: For program point L271-3(lines 260 283) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,295 INFO L448 ceAbstractionStarter]: For program point L172-1(lines 171 184) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,295 INFO L448 ceAbstractionStarter]: For program point L329(lines 329 333) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,296 INFO L448 ceAbstractionStarter]: For program point L362-1(lines 361 384) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,296 INFO L451 ceAbstractionStarter]: At program point L329-2(lines 289 293) the Hoare annotation is: true 33.77/12.79 [2019-03-28 12:22:02,296 INFO L448 ceAbstractionStarter]: For program point L329-3(lines 329 333) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,296 INFO L451 ceAbstractionStarter]: At program point L329-5(lines 1 485) the Hoare annotation is: true 33.77/12.79 [2019-03-28 12:22:02,296 INFO L448 ceAbstractionStarter]: For program point L329-6(lines 329 333) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,296 INFO L448 ceAbstractionStarter]: For program point L321(lines 321 325) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,296 INFO L448 ceAbstractionStarter]: For program point L65(lines 65 67) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,297 INFO L451 ceAbstractionStarter]: At program point L329-8(lines 1 485) the Hoare annotation is: true 33.77/12.79 [2019-03-28 12:22:02,297 INFO L448 ceAbstractionStarter]: For program point L329-9(lines 329 333) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,297 INFO L448 ceAbstractionStarter]: For program point L321-2(lines 321 325) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,297 INFO L451 ceAbstractionStarter]: At program point L222(lines 212 250) the Hoare annotation is: true 33.77/12.79 [2019-03-28 12:22:02,297 INFO L448 ceAbstractionStarter]: For program point L321-3(lines 321 325) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,297 INFO L451 ceAbstractionStarter]: At program point L329-11(lines 289 293) the Hoare annotation is: true 33.77/12.79 [2019-03-28 12:22:02,298 INFO L448 ceAbstractionStarter]: For program point L329-12(lines 329 333) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,298 INFO L451 ceAbstractionStarter]: At program point L156(lines 144 158) the Hoare annotation is: true 33.77/12.79 [2019-03-28 12:22:02,298 INFO L448 ceAbstractionStarter]: For program point L321-5(lines 321 325) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,298 INFO L448 ceAbstractionStarter]: For program point L321-6(lines 321 325) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,298 INFO L451 ceAbstractionStarter]: At program point L156-1(lines 144 158) the Hoare annotation is: true 33.77/12.79 [2019-03-28 12:22:02,298 INFO L451 ceAbstractionStarter]: At program point L329-14(lines 362 366) the Hoare annotation is: true 33.77/12.79 [2019-03-28 12:22:02,298 INFO L448 ceAbstractionStarter]: For program point L90(lines 90 98) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,299 INFO L451 ceAbstractionStarter]: At program point L156-2(lines 144 158) the Hoare annotation is: true 33.77/12.79 [2019-03-28 12:22:02,299 INFO L451 ceAbstractionStarter]: At program point L156-3(lines 144 158) the Hoare annotation is: true 33.77/12.79 [2019-03-28 12:22:02,299 INFO L448 ceAbstractionStarter]: For program point L321-8(lines 321 325) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,299 INFO L448 ceAbstractionStarter]: For program point L321-9(lines 321 325) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,299 INFO L451 ceAbstractionStarter]: At program point L156-4(lines 144 158) the Hoare annotation is: true 33.77/12.79 [2019-03-28 12:22:02,299 INFO L448 ceAbstractionStarter]: For program point L321-11(lines 321 325) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,299 INFO L448 ceAbstractionStarter]: For program point L321-12(lines 321 325) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,300 INFO L448 ceAbstractionStarter]: For program point L404(lines 404 409) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,300 INFO L448 ceAbstractionStarter]: For program point L321-14(lines 321 325) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,300 INFO L448 ceAbstractionStarter]: For program point L239(lines 239 246) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,300 INFO L451 ceAbstractionStarter]: At program point L165(lines 172 176) the Hoare annotation is: true 33.77/12.79 [2019-03-28 12:22:02,300 INFO L448 ceAbstractionStarter]: For program point L289-1(lines 288 311) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,300 INFO L448 ceAbstractionStarter]: For program point L190(lines 190 200) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,301 INFO L448 ceAbstractionStarter]: For program point L289-3(lines 288 311) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,301 INFO L448 ceAbstractionStarter]: For program point L190-1(lines 190 200) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,301 INFO L448 ceAbstractionStarter]: For program point L190-2(lines 190 200) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,301 INFO L448 ceAbstractionStarter]: For program point L372-1(lines 361 384) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,301 INFO L451 ceAbstractionStarter]: At program point L430-1(lines 285 467) the Hoare annotation is: true 33.77/12.79 [2019-03-28 12:22:02,301 INFO L448 ceAbstractionStarter]: For program point L34(lines 34 42) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,301 INFO L448 ceAbstractionStarter]: For program point L299-1(lines 288 311) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,302 INFO L448 ceAbstractionStarter]: For program point L266-1(lines 260 283) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,302 INFO L448 ceAbstractionStarter]: For program point L299-3(lines 288 311) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,302 INFO L448 ceAbstractionStarter]: For program point L266-3(lines 260 283) no Hoare annotation was computed. 33.77/12.79 [2019-03-28 12:22:02,302 INFO L451 ceAbstractionStarter]: At program point L101-1(lines 89 120) the Hoare annotation is: true 33.77/12.79 [2019-03-28 12:22:02,313 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.03 12:22:02 BasicIcfg 33.77/12.79 [2019-03-28 12:22:02,313 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- 33.77/12.79 [2019-03-28 12:22:02,313 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- 33.77/12.79 [2019-03-28 12:22:02,314 INFO L271 PluginConnector]: Initializing BuchiAutomizer... 33.77/12.79 [2019-03-28 12:22:02,317 INFO L276 PluginConnector]: BuchiAutomizer initialized 33.77/12.79 [2019-03-28 12:22:02,318 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis 33.77/12.79 [2019-03-28 12:22:02,318 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 28.03 12:22:00" (1/5) ... 33.77/12.79 [2019-03-28 12:22:02,319 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@332dd0fa and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.03 12:22:02, skipping insertion in model container 33.77/12.79 [2019-03-28 12:22:02,319 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis 33.77/12.79 [2019-03-28 12:22:02,319 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:22:01" (2/5) ... 33.77/12.79 [2019-03-28 12:22:02,319 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@332dd0fa and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.03 12:22:02, skipping insertion in model container 33.77/12.79 [2019-03-28 12:22:02,319 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis 33.77/12.79 [2019-03-28 12:22:02,319 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.03 12:22:01" (3/5) ... 33.77/12.79 [2019-03-28 12:22:02,320 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@332dd0fa and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 28.03 12:22:02, skipping insertion in model container 33.77/12.79 [2019-03-28 12:22:02,320 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis 33.77/12.79 [2019-03-28 12:22:02,320 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.blockencoding CFG 28.03 12:22:02" (4/5) ... 33.77/12.79 [2019-03-28 12:22:02,320 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@332dd0fa and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 28.03 12:22:02, skipping insertion in model container 33.77/12.79 [2019-03-28 12:22:02,321 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis 33.77/12.79 [2019-03-28 12:22:02,321 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.03 12:22:02" (5/5) ... 33.77/12.79 [2019-03-28 12:22:02,322 INFO L375 chiAutomizerObserver]: Analyzing ICFG theBenchmark.c_BEv2 33.77/12.79 [2019-03-28 12:22:02,347 INFO L133 ementStrategyFactory]: Using default assertion order modulation 33.77/12.79 [2019-03-28 12:22:02,348 INFO L374 BuchiCegarLoop]: Interprodecural is true 33.77/12.79 [2019-03-28 12:22:02,348 INFO L375 BuchiCegarLoop]: Hoare is true 33.77/12.79 [2019-03-28 12:22:02,348 INFO L376 BuchiCegarLoop]: Compute interpolants for ForwardPredicates 33.77/12.79 [2019-03-28 12:22:02,348 INFO L377 BuchiCegarLoop]: Backedges is STRAIGHT_LINE 33.77/12.79 [2019-03-28 12:22:02,348 INFO L378 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION 33.77/12.79 [2019-03-28 12:22:02,348 INFO L379 BuchiCegarLoop]: Difference is false 33.77/12.79 [2019-03-28 12:22:02,348 INFO L380 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA 33.77/12.79 [2019-03-28 12:22:02,349 INFO L383 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== 33.77/12.79 [2019-03-28 12:22:02,355 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 114 states. 33.77/12.79 [2019-03-28 12:22:02,380 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 91 33.77/12.79 [2019-03-28 12:22:02,380 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 33.77/12.79 [2019-03-28 12:22:02,380 INFO L119 BuchiIsEmpty]: Starting construction of run 33.77/12.79 [2019-03-28 12:22:02,389 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 33.77/12.79 [2019-03-28 12:22:02,389 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 33.77/12.79 [2019-03-28 12:22:02,390 INFO L442 BuchiCegarLoop]: ======== Iteration 1============ 33.77/12.79 [2019-03-28 12:22:02,390 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 114 states. 33.77/12.79 [2019-03-28 12:22:02,396 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 91 33.77/12.79 [2019-03-28 12:22:02,396 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 33.77/12.79 [2019-03-28 12:22:02,396 INFO L119 BuchiIsEmpty]: Starting construction of run 33.77/12.79 [2019-03-28 12:22:02,398 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 33.77/12.79 [2019-03-28 12:22:02,398 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 33.77/12.79 [2019-03-28 12:22:02,404 INFO L794 eck$LassoCheckResult]: Stem: 58#ULTIMATE.startENTRYtrue [1057] ULTIMATE.startENTRY-->L165: Formula: (and (= 0 v_~m_st~0_20) (= 2 v_~E_M~0_30) (= v_~t1_pc~0_18 0) (= 0 v_~t1_st~0_20) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 0 v_~token~0_8) (= v_~M_E~0_19 2) (= v_~local~0_6 0) (= v_~m_i~0_7 1) (= 2 v_~E_1~0_30) (= v_~m_pc~0_18 0) (= 1 v_~t1_i~0_7)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ~t1_st~0=v_~t1_st~0_20, ~t1_pc~0=v_~t1_pc~0_18, ~M_E~0=v_~M_E~0_19, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_#t~ret8=|v_ULTIMATE.start_start_simulation_#t~ret8_4|, ~token~0=v_~token~0_8, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~E_1~0=v_~E_1~0_30, ~E_M~0=v_~E_M~0_30, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~T1_E~0=v_~T1_E~0_18, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_20, ~m_pc~0=v_~m_pc~0_18, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ~t1_st~0, ~t1_pc~0, ~M_E~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_#t~ret8, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~E_1~0, ~E_M~0, ULTIMATE.start_main_#res, ~T1_E~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0, ULTIMATE.start_main_~__retres1~3] 54#L165true [913] L165-->L172-1: Formula: (and (= v_~m_st~0_4 2) (< v_~m_i~0_4 1)) InVars {~m_i~0=v_~m_i~0_4} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_4} AuxVars[] AssignedVars[~m_st~0] 21#L172-1true [915] L172-1-->L177-1: Formula: (and (> 1 v_~t1_i~0_4) (= v_~t1_st~0_3 2)) InVars {~t1_i~0=v_~t1_i~0_4} OutVars{~t1_st~0=v_~t1_st~0_3, ~t1_i~0=v_~t1_i~0_4} AuxVars[] AssignedVars[~t1_st~0] 27#L177-1true [654] L177-1-->L261-1: Formula: (and (= 0 v_~M_E~0_3) (= v_~M_E~0_2 1)) InVars {~M_E~0=v_~M_E~0_3} OutVars{~M_E~0=v_~M_E~0_2} AuxVars[] AssignedVars[~M_E~0] 88#L261-1true [781] L261-1-->L266-1: Formula: (and (= v_~T1_E~0_2 1) (= 0 v_~T1_E~0_3)) InVars {~T1_E~0=v_~T1_E~0_3} OutVars{~T1_E~0=v_~T1_E~0_2} AuxVars[] AssignedVars[~T1_E~0] 102#L266-1true [921] L266-1-->L271-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 25#L271-1true [923] L271-1-->L276-1: Formula: (< v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 29#L276-1true [657] L276-1-->L126: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_3, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_4, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_1|, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_3|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_master_triggered_#res] 73#L126true [755] L126-->L127: Formula: (= v_~m_pc~0_2 1) InVars {~m_pc~0=v_~m_pc~0_2} OutVars{~m_pc~0=v_~m_pc~0_2} AuxVars[] AssignedVars[] 52#L127true [712] L127-->L137: Formula: (and (= v_~E_M~0_8 1) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_4 1)) InVars {~E_M~0=v_~E_M~0_8} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_4, ~E_M~0=v_~E_M~0_8} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 74#L137true [1058] L137-->L321: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_16| v_ULTIMATE.start_activate_threads_~tmp~1_29) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_29 |v_ULTIMATE.start_is_master_triggered_#res_16|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_29, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_16|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 5#L321true [611] L321-->L321-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_8) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8} AuxVars[] AssignedVars[] 8#L321-2true [615] L321-2-->L145: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 95#L145true [931] L145-->L145-2: Formula: (> v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 89#L145-2true [783] L145-2-->L156: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 96#L156true [1059] L156-->L329: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_29 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_29, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_16|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_transmit1_triggered_#res] 9#L329true [618] L329-->L329-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_9) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} AuxVars[] AssignedVars[] 13#L329-2true [937] L329-2-->L289-1: Formula: (> v_~M_E~0_10 1) InVars {~M_E~0=v_~M_E~0_10} OutVars{~M_E~0=v_~M_E~0_10} AuxVars[] AssignedVars[] 59#L289-1true [939] L289-1-->L294-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 61#L294-1true [941] L294-1-->L299-1: Formula: (> 1 v_~E_M~0_12) InVars {~E_M~0=v_~E_M~0_12} OutVars{~E_M~0=v_~E_M~0_12} AuxVars[] AssignedVars[] 10#L299-1true [943] L299-1-->L430-1: Formula: (> 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 34#L430-1true 33.77/12.79 [2019-03-28 12:22:02,405 INFO L796 eck$LassoCheckResult]: Loop: 34#L430-1true [1060] L430-1-->L236: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 108#L236true [1061] L236-->L190: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_22, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 50#L190true [708] L190-->L202: Formula: (and (= v_~m_st~0_8 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11 1)) InVars {~m_st~0=v_~m_st~0_8} OutVars{~m_st~0=v_~m_st~0_8, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 30#L202true [1062] L202-->L217: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 86#L217true [1064] L217-->L261-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 83#L261-2true [946] L261-2-->L261-4: Formula: (> v_~M_E~0_13 0) InVars {~M_E~0=v_~M_E~0_13} OutVars{~M_E~0=v_~M_E~0_13} AuxVars[] AssignedVars[] 80#L261-4true [950] L261-4-->L266-3: Formula: (< v_~T1_E~0_13 0) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 97#L266-3true [952] L266-3-->L271-3: Formula: (< 0 v_~E_M~0_21) InVars {~E_M~0=v_~E_M~0_21} OutVars{~E_M~0=v_~E_M~0_21} AuxVars[] AssignedVars[] 23#L271-3true [646] L271-3-->L276-3: Formula: (and (= 0 v_~E_1~0_22) (= v_~E_1~0_21 1)) InVars {~E_1~0=v_~E_1~0_22} OutVars{~E_1~0=v_~E_1~0_21} AuxVars[] AssignedVars[~E_1~0] 28#L276-3true [656] L276-3-->L126-9: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_19, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_17, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_20, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_10|, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_12|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_master_triggered_#res] 77#L126-9true [763] L126-9-->L127-3: Formula: (= v_~m_pc~0_13 1) InVars {~m_pc~0=v_~m_pc~0_13} OutVars{~m_pc~0=v_~m_pc~0_13} AuxVars[] AssignedVars[] 35#L127-3true [670] L127-3-->L137-3: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_20 1) (= 1 v_~E_M~0_22)) InVars {~E_M~0=v_~E_M~0_22} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_20, ~E_M~0=v_~E_M~0_22} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 65#L137-3true [1070] L137-3-->L321-9: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_34 |v_ULTIMATE.start_is_master_triggered_#res_21|) (= |v_ULTIMATE.start_is_master_triggered_#res_21| v_ULTIMATE.start_activate_threads_~tmp~1_34)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_34} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_34, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_34, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_21|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_21|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 93#L321-9true [789] L321-9-->L321-11: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_24) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_24} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_24} AuxVars[] AssignedVars[] 98#L321-11true [796] L321-11-->L145-9: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 72#L145-9true [990] L145-9-->L145-11: Formula: (< v_~t1_pc~0_16 1) InVars {~t1_pc~0=v_~t1_pc~0_16} OutVars{~t1_pc~0=v_~t1_pc~0_16} AuxVars[] AssignedVars[] 66#L145-11true [745] L145-11-->L156-3: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_29 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_29} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 115#L156-3true [1073] L156-3-->L329-9: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_34 |v_ULTIMATE.start_is_transmit1_triggered_#res_19|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_34 |v_ULTIMATE.start_is_transmit1_triggered_#res_19|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_34} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_34, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_34, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_21|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_19|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_transmit1_triggered_#res] 7#L329-9true [614] L329-9-->L329-11: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_25 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_25} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_25} AuxVars[] AssignedVars[] 104#L329-11true [1008] L329-11-->L289-3: Formula: (< v_~M_E~0_16 1) InVars {~M_E~0=v_~M_E~0_16} OutVars{~M_E~0=v_~M_E~0_16} AuxVars[] AssignedVars[] 51#L289-3true [1012] L289-3-->L294-3: Formula: (< v_~T1_E~0_16 1) InVars {~T1_E~0=v_~T1_E~0_16} OutVars{~T1_E~0=v_~T1_E~0_16} AuxVars[] AssignedVars[] 84#L294-3true [1014] L294-3-->L299-3: Formula: (> 1 v_~E_M~0_26) InVars {~E_M~0=v_~E_M~0_26} OutVars{~E_M~0=v_~E_M~0_26} AuxVars[] AssignedVars[] 99#L299-3true [1018] L299-3-->L304-3: Formula: (< 1 v_~E_1~0_28) InVars {~E_1~0=v_~E_1~0_28} OutVars{~E_1~0=v_~E_1~0_28} AuxVars[] AssignedVars[] 17#L304-3true [637] L304-3-->L190-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 48#L190-1true [705] L190-1-->L202-1: Formula: (and (= 0 v_~m_st~0_17) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18 1)) InVars {~m_st~0=v_~m_st~0_17} OutVars{~m_st~0=v_~m_st~0_17, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 19#L202-1true [1074] L202-1-->L449: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_~tmp~3] 47#L449true [1026] L449-->L449-1: Formula: (< 0 v_ULTIMATE.start_start_simulation_~tmp~3_4) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_4} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_4} AuxVars[] AssignedVars[] 49#L449-1true [707] L449-1-->L190-2: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_1, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret6=|v_ULTIMATE.start_stop_simulation_#t~ret6_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret6, ULTIMATE.start_stop_simulation_#res] 45#L190-2true [698] L190-2-->L202-2: Formula: (and (= v_~m_st~0_5 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_4 1)) InVars {~m_st~0=v_~m_st~0_5} OutVars{~m_st~0=v_~m_st~0_5, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 18#L202-2true [1076] L202-2-->L404: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_stop_simulation_#t~ret6=|v_ULTIMATE.start_stop_simulation_#t~ret6_4|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret6] 76#L404true [761] L404-->L411: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 32#L411true [1083] L411-->L430-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|, ULTIMATE.start_start_simulation_#t~ret8=|v_ULTIMATE.start_start_simulation_#t~ret8_6|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_#t~ret8] 34#L430-1true 33.77/12.79 [2019-03-28 12:22:02,412 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 33.77/12.79 [2019-03-28 12:22:02,412 INFO L82 PathProgramCache]: Analyzing trace with hash 1434516410, now seen corresponding path program 1 times 33.77/12.79 [2019-03-28 12:22:02,414 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 33.77/12.79 [2019-03-28 12:22:02,415 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 33.77/12.79 [2019-03-28 12:22:02,435 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:02,435 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:02,435 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:02,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 33.77/12.79 [2019-03-28 12:22:02,512 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 33.77/12.79 [2019-03-28 12:22:02,514 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 33.77/12.79 [2019-03-28 12:22:02,514 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 33.77/12.79 [2019-03-28 12:22:02,519 INFO L799 eck$LassoCheckResult]: stem already infeasible 33.77/12.79 [2019-03-28 12:22:02,520 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 33.77/12.79 [2019-03-28 12:22:02,520 INFO L82 PathProgramCache]: Analyzing trace with hash 88454859, now seen corresponding path program 1 times 33.77/12.79 [2019-03-28 12:22:02,520 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 33.77/12.79 [2019-03-28 12:22:02,520 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 33.77/12.79 [2019-03-28 12:22:02,521 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:02,521 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:02,522 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:02,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 33.77/12.79 [2019-03-28 12:22:02,569 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 33.77/12.79 [2019-03-28 12:22:02,569 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 33.77/12.79 [2019-03-28 12:22:02,569 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 33.77/12.79 [2019-03-28 12:22:02,571 INFO L811 eck$LassoCheckResult]: loop already infeasible 33.77/12.79 [2019-03-28 12:22:02,586 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 33.77/12.79 [2019-03-28 12:22:02,587 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 33.77/12.79 [2019-03-28 12:22:02,589 INFO L87 Difference]: Start difference. First operand 114 states. Second operand 3 states. 33.77/12.79 [2019-03-28 12:22:02,810 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 33.77/12.79 [2019-03-28 12:22:02,810 INFO L93 Difference]: Finished difference Result 114 states and 256 transitions. 33.77/12.79 [2019-03-28 12:22:02,811 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 33.77/12.79 [2019-03-28 12:22:02,815 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 114 states and 256 transitions. 33.77/12.79 [2019-03-28 12:22:02,819 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 91 33.77/12.79 [2019-03-28 12:22:02,826 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 114 states to 114 states and 256 transitions. 33.77/12.79 [2019-03-28 12:22:02,827 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 114 33.77/12.79 [2019-03-28 12:22:02,828 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 114 33.77/12.79 [2019-03-28 12:22:02,829 INFO L73 IsDeterministic]: Start isDeterministic. Operand 114 states and 256 transitions. 33.77/12.79 [2019-03-28 12:22:02,830 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 33.77/12.79 [2019-03-28 12:22:02,830 INFO L706 BuchiCegarLoop]: Abstraction has 114 states and 256 transitions. 33.77/12.79 [2019-03-28 12:22:02,851 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 114 states and 256 transitions. 33.77/12.79 [2019-03-28 12:22:02,867 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 114 to 114. 33.77/12.79 [2019-03-28 12:22:02,868 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. 33.77/12.79 [2019-03-28 12:22:02,869 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 256 transitions. 33.77/12.79 [2019-03-28 12:22:02,870 INFO L729 BuchiCegarLoop]: Abstraction has 114 states and 256 transitions. 33.77/12.79 [2019-03-28 12:22:02,871 INFO L609 BuchiCegarLoop]: Abstraction has 114 states and 256 transitions. 33.77/12.79 [2019-03-28 12:22:02,871 INFO L442 BuchiCegarLoop]: ======== Iteration 2============ 33.77/12.79 [2019-03-28 12:22:02,871 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 114 states and 256 transitions. 33.77/12.79 [2019-03-28 12:22:02,874 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 91 33.77/12.79 [2019-03-28 12:22:02,874 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 33.77/12.79 [2019-03-28 12:22:02,874 INFO L119 BuchiIsEmpty]: Starting construction of run 33.77/12.79 [2019-03-28 12:22:02,875 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 33.77/12.79 [2019-03-28 12:22:02,875 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 33.77/12.79 [2019-03-28 12:22:02,876 INFO L794 eck$LassoCheckResult]: Stem: 326#ULTIMATE.startENTRY [1057] ULTIMATE.startENTRY-->L165: Formula: (and (= 0 v_~m_st~0_20) (= 2 v_~E_M~0_30) (= v_~t1_pc~0_18 0) (= 0 v_~t1_st~0_20) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 0 v_~token~0_8) (= v_~M_E~0_19 2) (= v_~local~0_6 0) (= v_~m_i~0_7 1) (= 2 v_~E_1~0_30) (= v_~m_pc~0_18 0) (= 1 v_~t1_i~0_7)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ~t1_st~0=v_~t1_st~0_20, ~t1_pc~0=v_~t1_pc~0_18, ~M_E~0=v_~M_E~0_19, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_#t~ret8=|v_ULTIMATE.start_start_simulation_#t~ret8_4|, ~token~0=v_~token~0_8, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~E_1~0=v_~E_1~0_30, ~E_M~0=v_~E_M~0_30, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~T1_E~0=v_~T1_E~0_18, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_20, ~m_pc~0=v_~m_pc~0_18, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ~t1_st~0, ~t1_pc~0, ~M_E~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_#t~ret8, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~E_1~0, ~E_M~0, ULTIMATE.start_main_#res, ~T1_E~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0, ULTIMATE.start_main_~__retres1~3] 325#L165 [912] L165-->L172-1: Formula: (and (= v_~m_st~0_4 2) (> v_~m_i~0_4 1)) InVars {~m_i~0=v_~m_i~0_4} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_4} AuxVars[] AssignedVars[~m_st~0] 270#L172-1 [915] L172-1-->L177-1: Formula: (and (> 1 v_~t1_i~0_4) (= v_~t1_st~0_3 2)) InVars {~t1_i~0=v_~t1_i~0_4} OutVars{~t1_st~0=v_~t1_st~0_3, ~t1_i~0=v_~t1_i~0_4} AuxVars[] AssignedVars[~t1_st~0] 271#L177-1 [654] L177-1-->L261-1: Formula: (and (= 0 v_~M_E~0_3) (= v_~M_E~0_2 1)) InVars {~M_E~0=v_~M_E~0_3} OutVars{~M_E~0=v_~M_E~0_2} AuxVars[] AssignedVars[~M_E~0] 280#L261-1 [781] L261-1-->L266-1: Formula: (and (= v_~T1_E~0_2 1) (= 0 v_~T1_E~0_3)) InVars {~T1_E~0=v_~T1_E~0_3} OutVars{~T1_E~0=v_~T1_E~0_2} AuxVars[] AssignedVars[~T1_E~0] 345#L266-1 [921] L266-1-->L271-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 277#L271-1 [923] L271-1-->L276-1: Formula: (< v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 278#L276-1 [657] L276-1-->L126: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_3, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_4, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_1|, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_3|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_master_triggered_#res] 282#L126 [755] L126-->L127: Formula: (= v_~m_pc~0_2 1) InVars {~m_pc~0=v_~m_pc~0_2} OutVars{~m_pc~0=v_~m_pc~0_2} AuxVars[] AssignedVars[] 319#L127 [712] L127-->L137: Formula: (and (= v_~E_M~0_8 1) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_4 1)) InVars {~E_M~0=v_~E_M~0_8} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_4, ~E_M~0=v_~E_M~0_8} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 320#L137 [1058] L137-->L321: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_16| v_ULTIMATE.start_activate_threads_~tmp~1_29) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_29 |v_ULTIMATE.start_is_master_triggered_#res_16|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_29, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_16|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 243#L321 [611] L321-->L321-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_8) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8} AuxVars[] AssignedVars[] 244#L321-2 [615] L321-2-->L145: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 248#L145 [931] L145-->L145-2: Formula: (> v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 313#L145-2 [783] L145-2-->L156: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 314#L156 [1059] L156-->L329: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_29 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_29, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_16|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_transmit1_triggered_#res] 249#L329 [618] L329-->L329-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_9) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} AuxVars[] AssignedVars[] 250#L329-2 [937] L329-2-->L289-1: Formula: (> v_~M_E~0_10 1) InVars {~M_E~0=v_~M_E~0_10} OutVars{~M_E~0=v_~M_E~0_10} AuxVars[] AssignedVars[] 257#L289-1 [939] L289-1-->L294-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 327#L294-1 [941] L294-1-->L299-1: Formula: (> 1 v_~E_M~0_12) InVars {~E_M~0=v_~E_M~0_12} OutVars{~E_M~0=v_~E_M~0_12} AuxVars[] AssignedVars[] 251#L299-1 [943] L299-1-->L430-1: Formula: (> 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 252#L430-1 33.77/12.79 [2019-03-28 12:22:02,877 INFO L796 eck$LassoCheckResult]: Loop: 252#L430-1 [1060] L430-1-->L236: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 289#L236 [1061] L236-->L190: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_22, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 316#L190 [708] L190-->L202: Formula: (and (= v_~m_st~0_8 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11 1)) InVars {~m_st~0=v_~m_st~0_8} OutVars{~m_st~0=v_~m_st~0_8, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 276#L202 [1062] L202-->L217: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 283#L217 [1064] L217-->L261-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 343#L261-2 [946] L261-2-->L261-4: Formula: (> v_~M_E~0_13 0) InVars {~M_E~0=v_~M_E~0_13} OutVars{~M_E~0=v_~M_E~0_13} AuxVars[] AssignedVars[] 339#L261-4 [950] L261-4-->L266-3: Formula: (< v_~T1_E~0_13 0) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 340#L266-3 [952] L266-3-->L271-3: Formula: (< 0 v_~E_M~0_21) InVars {~E_M~0=v_~E_M~0_21} OutVars{~E_M~0=v_~E_M~0_21} AuxVars[] AssignedVars[] 273#L271-3 [646] L271-3-->L276-3: Formula: (and (= 0 v_~E_1~0_22) (= v_~E_1~0_21 1)) InVars {~E_1~0=v_~E_1~0_22} OutVars{~E_1~0=v_~E_1~0_21} AuxVars[] AssignedVars[~E_1~0] 274#L276-3 [656] L276-3-->L126-9: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_19, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_17, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_20, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_10|, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_12|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_master_triggered_#res] 281#L126-9 [763] L126-9-->L127-3: Formula: (= v_~m_pc~0_13 1) InVars {~m_pc~0=v_~m_pc~0_13} OutVars{~m_pc~0=v_~m_pc~0_13} AuxVars[] AssignedVars[] 290#L127-3 [670] L127-3-->L137-3: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_20 1) (= 1 v_~E_M~0_22)) InVars {~E_M~0=v_~E_M~0_22} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_20, ~E_M~0=v_~E_M~0_22} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 292#L137-3 [1070] L137-3-->L321-9: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_34 |v_ULTIMATE.start_is_master_triggered_#res_21|) (= |v_ULTIMATE.start_is_master_triggered_#res_21| v_ULTIMATE.start_activate_threads_~tmp~1_34)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_34} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_34, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_34, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_21|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_21|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 332#L321-9 [789] L321-9-->L321-11: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_24) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_24} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_24} AuxVars[] AssignedVars[] 348#L321-11 [796] L321-11-->L145-9: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 337#L145-9 [990] L145-9-->L145-11: Formula: (< v_~t1_pc~0_16 1) InVars {~t1_pc~0=v_~t1_pc~0_16} OutVars{~t1_pc~0=v_~t1_pc~0_16} AuxVars[] AssignedVars[] 304#L145-11 [745] L145-11-->L156-3: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_29 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_29} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 303#L156-3 [1073] L156-3-->L329-9: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_34 |v_ULTIMATE.start_is_transmit1_triggered_#res_19|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_34 |v_ULTIMATE.start_is_transmit1_triggered_#res_19|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_34} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_34, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_34, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_21|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_19|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_transmit1_triggered_#res] 246#L329-9 [614] L329-9-->L329-11: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_25 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_25} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_25} AuxVars[] AssignedVars[] 247#L329-11 [1008] L329-11-->L289-3: Formula: (< v_~M_E~0_16 1) InVars {~M_E~0=v_~M_E~0_16} OutVars{~M_E~0=v_~M_E~0_16} AuxVars[] AssignedVars[] 317#L289-3 [1012] L289-3-->L294-3: Formula: (< v_~T1_E~0_16 1) InVars {~T1_E~0=v_~T1_E~0_16} OutVars{~T1_E~0=v_~T1_E~0_16} AuxVars[] AssignedVars[] 318#L294-3 [1014] L294-3-->L299-3: Formula: (> 1 v_~E_M~0_26) InVars {~E_M~0=v_~E_M~0_26} OutVars{~E_M~0=v_~E_M~0_26} AuxVars[] AssignedVars[] 344#L299-3 [1018] L299-3-->L304-3: Formula: (< 1 v_~E_1~0_28) InVars {~E_1~0=v_~E_1~0_28} OutVars{~E_1~0=v_~E_1~0_28} AuxVars[] AssignedVars[] 263#L304-3 [637] L304-3-->L190-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 264#L190-1 [705] L190-1-->L202-1: Formula: (and (= 0 v_~m_st~0_17) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18 1)) InVars {~m_st~0=v_~m_st~0_17} OutVars{~m_st~0=v_~m_st~0_17, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 267#L202-1 [1074] L202-1-->L449: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_~tmp~3] 268#L449 [1026] L449-->L449-1: Formula: (< 0 v_ULTIMATE.start_start_simulation_~tmp~3_4) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_4} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_4} AuxVars[] AssignedVars[] 301#L449-1 [707] L449-1-->L190-2: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_1, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret6=|v_ULTIMATE.start_stop_simulation_#t~ret6_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret6, ULTIMATE.start_stop_simulation_#res] 311#L190-2 [698] L190-2-->L202-2: Formula: (and (= v_~m_st~0_5 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_4 1)) InVars {~m_st~0=v_~m_st~0_5} OutVars{~m_st~0=v_~m_st~0_5, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 265#L202-2 [1076] L202-2-->L404: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_stop_simulation_#t~ret6=|v_ULTIMATE.start_stop_simulation_#t~ret6_4|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret6] 266#L404 [761] L404-->L411: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 285#L411 [1083] L411-->L430-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|, ULTIMATE.start_start_simulation_#t~ret8=|v_ULTIMATE.start_start_simulation_#t~ret8_6|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_#t~ret8] 252#L430-1 33.77/12.79 [2019-03-28 12:22:02,878 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 33.77/12.79 [2019-03-28 12:22:02,878 INFO L82 PathProgramCache]: Analyzing trace with hash 1843340635, now seen corresponding path program 1 times 33.77/12.79 [2019-03-28 12:22:02,879 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 33.77/12.79 [2019-03-28 12:22:02,879 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 33.77/12.79 [2019-03-28 12:22:02,880 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:02,880 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:02,880 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:02,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 33.77/12.79 [2019-03-28 12:22:02,898 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 33.77/12.79 [2019-03-28 12:22:02,898 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 33.77/12.79 [2019-03-28 12:22:02,898 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 33.77/12.79 [2019-03-28 12:22:02,899 INFO L799 eck$LassoCheckResult]: stem already infeasible 33.77/12.79 [2019-03-28 12:22:02,899 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 33.77/12.79 [2019-03-28 12:22:02,899 INFO L82 PathProgramCache]: Analyzing trace with hash 88454859, now seen corresponding path program 2 times 33.77/12.79 [2019-03-28 12:22:02,899 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 33.77/12.79 [2019-03-28 12:22:02,899 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 33.77/12.79 [2019-03-28 12:22:02,900 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:02,900 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:02,900 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:02,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 33.77/12.79 [2019-03-28 12:22:02,941 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 33.77/12.79 [2019-03-28 12:22:02,941 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 33.77/12.79 [2019-03-28 12:22:02,942 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 33.77/12.79 [2019-03-28 12:22:02,942 INFO L811 eck$LassoCheckResult]: loop already infeasible 33.77/12.79 [2019-03-28 12:22:02,942 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 33.77/12.79 [2019-03-28 12:22:02,942 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 33.77/12.79 [2019-03-28 12:22:02,943 INFO L87 Difference]: Start difference. First operand 114 states and 256 transitions. cyclomatic complexity: 143 Second operand 3 states. 33.77/12.79 [2019-03-28 12:22:03,142 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 33.77/12.79 [2019-03-28 12:22:03,142 INFO L93 Difference]: Finished difference Result 114 states and 255 transitions. 33.77/12.79 [2019-03-28 12:22:03,142 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 33.77/12.79 [2019-03-28 12:22:03,143 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 114 states and 255 transitions. 33.77/12.79 [2019-03-28 12:22:03,146 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 91 33.77/12.79 [2019-03-28 12:22:03,147 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 114 states to 114 states and 255 transitions. 33.77/12.79 [2019-03-28 12:22:03,148 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 114 33.77/12.79 [2019-03-28 12:22:03,148 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 114 33.77/12.79 [2019-03-28 12:22:03,148 INFO L73 IsDeterministic]: Start isDeterministic. Operand 114 states and 255 transitions. 33.77/12.79 [2019-03-28 12:22:03,149 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 33.77/12.79 [2019-03-28 12:22:03,149 INFO L706 BuchiCegarLoop]: Abstraction has 114 states and 255 transitions. 33.77/12.79 [2019-03-28 12:22:03,150 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 114 states and 255 transitions. 33.77/12.79 [2019-03-28 12:22:03,156 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 114 to 114. 33.77/12.79 [2019-03-28 12:22:03,156 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. 33.77/12.79 [2019-03-28 12:22:03,157 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 255 transitions. 33.77/12.79 [2019-03-28 12:22:03,157 INFO L729 BuchiCegarLoop]: Abstraction has 114 states and 255 transitions. 33.77/12.79 [2019-03-28 12:22:03,157 INFO L609 BuchiCegarLoop]: Abstraction has 114 states and 255 transitions. 33.77/12.79 [2019-03-28 12:22:03,157 INFO L442 BuchiCegarLoop]: ======== Iteration 3============ 33.77/12.79 [2019-03-28 12:22:03,158 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 114 states and 255 transitions. 33.77/12.79 [2019-03-28 12:22:03,159 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 91 33.77/12.79 [2019-03-28 12:22:03,159 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 33.77/12.79 [2019-03-28 12:22:03,159 INFO L119 BuchiIsEmpty]: Starting construction of run 33.77/12.79 [2019-03-28 12:22:03,161 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 33.77/12.79 [2019-03-28 12:22:03,161 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 33.77/12.79 [2019-03-28 12:22:03,162 INFO L794 eck$LassoCheckResult]: Stem: 562#ULTIMATE.startENTRY [1057] ULTIMATE.startENTRY-->L165: Formula: (and (= 0 v_~m_st~0_20) (= 2 v_~E_M~0_30) (= v_~t1_pc~0_18 0) (= 0 v_~t1_st~0_20) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 0 v_~token~0_8) (= v_~M_E~0_19 2) (= v_~local~0_6 0) (= v_~m_i~0_7 1) (= 2 v_~E_1~0_30) (= v_~m_pc~0_18 0) (= 1 v_~t1_i~0_7)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ~t1_st~0=v_~t1_st~0_20, ~t1_pc~0=v_~t1_pc~0_18, ~M_E~0=v_~M_E~0_19, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_#t~ret8=|v_ULTIMATE.start_start_simulation_#t~ret8_4|, ~token~0=v_~token~0_8, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~E_1~0=v_~E_1~0_30, ~E_M~0=v_~E_M~0_30, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~T1_E~0=v_~T1_E~0_18, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_20, ~m_pc~0=v_~m_pc~0_18, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ~t1_st~0, ~t1_pc~0, ~M_E~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_#t~ret8, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~E_1~0, ~E_M~0, ULTIMATE.start_main_#res, ~T1_E~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0, ULTIMATE.start_main_~__retres1~3] 561#L165 [720] L165-->L172-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_3 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_3, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 506#L172-1 [915] L172-1-->L177-1: Formula: (and (> 1 v_~t1_i~0_4) (= v_~t1_st~0_3 2)) InVars {~t1_i~0=v_~t1_i~0_4} OutVars{~t1_st~0=v_~t1_st~0_3, ~t1_i~0=v_~t1_i~0_4} AuxVars[] AssignedVars[~t1_st~0] 507#L177-1 [654] L177-1-->L261-1: Formula: (and (= 0 v_~M_E~0_3) (= v_~M_E~0_2 1)) InVars {~M_E~0=v_~M_E~0_3} OutVars{~M_E~0=v_~M_E~0_2} AuxVars[] AssignedVars[~M_E~0] 516#L261-1 [781] L261-1-->L266-1: Formula: (and (= v_~T1_E~0_2 1) (= 0 v_~T1_E~0_3)) InVars {~T1_E~0=v_~T1_E~0_3} OutVars{~T1_E~0=v_~T1_E~0_2} AuxVars[] AssignedVars[~T1_E~0] 581#L266-1 [921] L266-1-->L271-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 513#L271-1 [923] L271-1-->L276-1: Formula: (< v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 514#L276-1 [657] L276-1-->L126: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_3, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_4, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_1|, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_3|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_master_triggered_#res] 518#L126 [755] L126-->L127: Formula: (= v_~m_pc~0_2 1) InVars {~m_pc~0=v_~m_pc~0_2} OutVars{~m_pc~0=v_~m_pc~0_2} AuxVars[] AssignedVars[] 555#L127 [712] L127-->L137: Formula: (and (= v_~E_M~0_8 1) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_4 1)) InVars {~E_M~0=v_~E_M~0_8} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_4, ~E_M~0=v_~E_M~0_8} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 556#L137 [1058] L137-->L321: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_16| v_ULTIMATE.start_activate_threads_~tmp~1_29) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_29 |v_ULTIMATE.start_is_master_triggered_#res_16|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_29, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_16|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 479#L321 [611] L321-->L321-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_8) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8} AuxVars[] AssignedVars[] 480#L321-2 [615] L321-2-->L145: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 484#L145 [931] L145-->L145-2: Formula: (> v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 549#L145-2 [783] L145-2-->L156: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 550#L156 [1059] L156-->L329: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_29 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_29, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_16|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_transmit1_triggered_#res] 485#L329 [618] L329-->L329-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_9) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} AuxVars[] AssignedVars[] 486#L329-2 [937] L329-2-->L289-1: Formula: (> v_~M_E~0_10 1) InVars {~M_E~0=v_~M_E~0_10} OutVars{~M_E~0=v_~M_E~0_10} AuxVars[] AssignedVars[] 493#L289-1 [939] L289-1-->L294-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 563#L294-1 [941] L294-1-->L299-1: Formula: (> 1 v_~E_M~0_12) InVars {~E_M~0=v_~E_M~0_12} OutVars{~E_M~0=v_~E_M~0_12} AuxVars[] AssignedVars[] 487#L299-1 [943] L299-1-->L430-1: Formula: (> 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 488#L430-1 33.77/12.79 [2019-03-28 12:22:03,163 INFO L796 eck$LassoCheckResult]: Loop: 488#L430-1 [1060] L430-1-->L236: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 525#L236 [1061] L236-->L190: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_22, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 552#L190 [708] L190-->L202: Formula: (and (= v_~m_st~0_8 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11 1)) InVars {~m_st~0=v_~m_st~0_8} OutVars{~m_st~0=v_~m_st~0_8, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 512#L202 [1062] L202-->L217: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 519#L217 [1064] L217-->L261-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 579#L261-2 [946] L261-2-->L261-4: Formula: (> v_~M_E~0_13 0) InVars {~M_E~0=v_~M_E~0_13} OutVars{~M_E~0=v_~M_E~0_13} AuxVars[] AssignedVars[] 575#L261-4 [950] L261-4-->L266-3: Formula: (< v_~T1_E~0_13 0) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 576#L266-3 [952] L266-3-->L271-3: Formula: (< 0 v_~E_M~0_21) InVars {~E_M~0=v_~E_M~0_21} OutVars{~E_M~0=v_~E_M~0_21} AuxVars[] AssignedVars[] 509#L271-3 [646] L271-3-->L276-3: Formula: (and (= 0 v_~E_1~0_22) (= v_~E_1~0_21 1)) InVars {~E_1~0=v_~E_1~0_22} OutVars{~E_1~0=v_~E_1~0_21} AuxVars[] AssignedVars[~E_1~0] 510#L276-3 [656] L276-3-->L126-9: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_19, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_17, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_20, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_10|, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_12|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_master_triggered_#res] 517#L126-9 [763] L126-9-->L127-3: Formula: (= v_~m_pc~0_13 1) InVars {~m_pc~0=v_~m_pc~0_13} OutVars{~m_pc~0=v_~m_pc~0_13} AuxVars[] AssignedVars[] 526#L127-3 [670] L127-3-->L137-3: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_20 1) (= 1 v_~E_M~0_22)) InVars {~E_M~0=v_~E_M~0_22} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_20, ~E_M~0=v_~E_M~0_22} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 528#L137-3 [1070] L137-3-->L321-9: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_34 |v_ULTIMATE.start_is_master_triggered_#res_21|) (= |v_ULTIMATE.start_is_master_triggered_#res_21| v_ULTIMATE.start_activate_threads_~tmp~1_34)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_34} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_34, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_34, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_21|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_21|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 568#L321-9 [789] L321-9-->L321-11: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_24) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_24} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_24} AuxVars[] AssignedVars[] 584#L321-11 [796] L321-11-->L145-9: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 573#L145-9 [753] L145-9-->L146-3: Formula: (= v_~t1_pc~0_15 1) InVars {~t1_pc~0=v_~t1_pc~0_15} OutVars{~t1_pc~0=v_~t1_pc~0_15} AuxVars[] AssignedVars[] 538#L146-3 [688] L146-3-->L156-3: Formula: (and (= 1 v_~E_1~0_24) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_28 1)) InVars {~E_1~0=v_~E_1~0_24} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_28, ~E_1~0=v_~E_1~0_24} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 539#L156-3 [1073] L156-3-->L329-9: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_34 |v_ULTIMATE.start_is_transmit1_triggered_#res_19|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_34 |v_ULTIMATE.start_is_transmit1_triggered_#res_19|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_34} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_34, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_34, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_21|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_19|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_transmit1_triggered_#res] 482#L329-9 [614] L329-9-->L329-11: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_25 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_25} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_25} AuxVars[] AssignedVars[] 483#L329-11 [1008] L329-11-->L289-3: Formula: (< v_~M_E~0_16 1) InVars {~M_E~0=v_~M_E~0_16} OutVars{~M_E~0=v_~M_E~0_16} AuxVars[] AssignedVars[] 553#L289-3 [1012] L289-3-->L294-3: Formula: (< v_~T1_E~0_16 1) InVars {~T1_E~0=v_~T1_E~0_16} OutVars{~T1_E~0=v_~T1_E~0_16} AuxVars[] AssignedVars[] 554#L294-3 [1014] L294-3-->L299-3: Formula: (> 1 v_~E_M~0_26) InVars {~E_M~0=v_~E_M~0_26} OutVars{~E_M~0=v_~E_M~0_26} AuxVars[] AssignedVars[] 580#L299-3 [1018] L299-3-->L304-3: Formula: (< 1 v_~E_1~0_28) InVars {~E_1~0=v_~E_1~0_28} OutVars{~E_1~0=v_~E_1~0_28} AuxVars[] AssignedVars[] 499#L304-3 [637] L304-3-->L190-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 500#L190-1 [705] L190-1-->L202-1: Formula: (and (= 0 v_~m_st~0_17) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18 1)) InVars {~m_st~0=v_~m_st~0_17} OutVars{~m_st~0=v_~m_st~0_17, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 503#L202-1 [1074] L202-1-->L449: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_~tmp~3] 504#L449 [1026] L449-->L449-1: Formula: (< 0 v_ULTIMATE.start_start_simulation_~tmp~3_4) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_4} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_4} AuxVars[] AssignedVars[] 537#L449-1 [707] L449-1-->L190-2: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_1, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret6=|v_ULTIMATE.start_stop_simulation_#t~ret6_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret6, ULTIMATE.start_stop_simulation_#res] 547#L190-2 [698] L190-2-->L202-2: Formula: (and (= v_~m_st~0_5 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_4 1)) InVars {~m_st~0=v_~m_st~0_5} OutVars{~m_st~0=v_~m_st~0_5, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 501#L202-2 [1076] L202-2-->L404: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_stop_simulation_#t~ret6=|v_ULTIMATE.start_stop_simulation_#t~ret6_4|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret6] 502#L404 [761] L404-->L411: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 521#L411 [1083] L411-->L430-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|, ULTIMATE.start_start_simulation_#t~ret8=|v_ULTIMATE.start_start_simulation_#t~ret8_6|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_#t~ret8] 488#L430-1 33.77/12.79 [2019-03-28 12:22:03,163 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 33.77/12.79 [2019-03-28 12:22:03,164 INFO L82 PathProgramCache]: Analyzing trace with hash -1266786789, now seen corresponding path program 1 times 33.77/12.79 [2019-03-28 12:22:03,164 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 33.77/12.79 [2019-03-28 12:22:03,164 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 33.77/12.79 [2019-03-28 12:22:03,165 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:03,165 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:03,165 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:03,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 33.77/12.79 [2019-03-28 12:22:03,185 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 33.77/12.79 [2019-03-28 12:22:03,185 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 33.77/12.79 [2019-03-28 12:22:03,185 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 33.77/12.79 [2019-03-28 12:22:03,186 INFO L799 eck$LassoCheckResult]: stem already infeasible 33.77/12.79 [2019-03-28 12:22:03,186 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 33.77/12.79 [2019-03-28 12:22:03,186 INFO L82 PathProgramCache]: Analyzing trace with hash 512280887, now seen corresponding path program 1 times 33.77/12.79 [2019-03-28 12:22:03,186 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 33.77/12.79 [2019-03-28 12:22:03,186 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 33.77/12.79 [2019-03-28 12:22:03,187 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:03,187 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:03,187 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:03,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 33.77/12.79 [2019-03-28 12:22:03,215 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 33.77/12.79 [2019-03-28 12:22:03,215 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 33.77/12.79 [2019-03-28 12:22:03,215 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 33.77/12.79 [2019-03-28 12:22:03,216 INFO L811 eck$LassoCheckResult]: loop already infeasible 33.77/12.79 [2019-03-28 12:22:03,216 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 33.77/12.79 [2019-03-28 12:22:03,216 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 33.77/12.79 [2019-03-28 12:22:03,216 INFO L87 Difference]: Start difference. First operand 114 states and 255 transitions. cyclomatic complexity: 142 Second operand 3 states. 33.77/12.79 [2019-03-28 12:22:03,378 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 33.77/12.79 [2019-03-28 12:22:03,379 INFO L93 Difference]: Finished difference Result 114 states and 254 transitions. 33.77/12.79 [2019-03-28 12:22:03,379 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 33.77/12.79 [2019-03-28 12:22:03,379 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 114 states and 254 transitions. 33.77/12.79 [2019-03-28 12:22:03,381 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 91 33.77/12.79 [2019-03-28 12:22:03,383 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 114 states to 114 states and 254 transitions. 33.77/12.79 [2019-03-28 12:22:03,383 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 114 33.77/12.79 [2019-03-28 12:22:03,384 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 114 33.77/12.79 [2019-03-28 12:22:03,384 INFO L73 IsDeterministic]: Start isDeterministic. Operand 114 states and 254 transitions. 33.77/12.79 [2019-03-28 12:22:03,385 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 33.77/12.79 [2019-03-28 12:22:03,385 INFO L706 BuchiCegarLoop]: Abstraction has 114 states and 254 transitions. 33.77/12.79 [2019-03-28 12:22:03,385 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 114 states and 254 transitions. 33.77/12.79 [2019-03-28 12:22:03,390 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 114 to 114. 33.77/12.79 [2019-03-28 12:22:03,390 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. 33.77/12.79 [2019-03-28 12:22:03,391 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 254 transitions. 33.77/12.79 [2019-03-28 12:22:03,392 INFO L729 BuchiCegarLoop]: Abstraction has 114 states and 254 transitions. 33.77/12.79 [2019-03-28 12:22:03,392 INFO L609 BuchiCegarLoop]: Abstraction has 114 states and 254 transitions. 33.77/12.79 [2019-03-28 12:22:03,392 INFO L442 BuchiCegarLoop]: ======== Iteration 4============ 33.77/12.79 [2019-03-28 12:22:03,392 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 114 states and 254 transitions. 33.77/12.79 [2019-03-28 12:22:03,393 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 91 33.77/12.79 [2019-03-28 12:22:03,394 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 33.77/12.79 [2019-03-28 12:22:03,394 INFO L119 BuchiIsEmpty]: Starting construction of run 33.77/12.79 [2019-03-28 12:22:03,395 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 33.77/12.79 [2019-03-28 12:22:03,395 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 33.77/12.79 [2019-03-28 12:22:03,396 INFO L794 eck$LassoCheckResult]: Stem: 798#ULTIMATE.startENTRY [1057] ULTIMATE.startENTRY-->L165: Formula: (and (= 0 v_~m_st~0_20) (= 2 v_~E_M~0_30) (= v_~t1_pc~0_18 0) (= 0 v_~t1_st~0_20) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 0 v_~token~0_8) (= v_~M_E~0_19 2) (= v_~local~0_6 0) (= v_~m_i~0_7 1) (= 2 v_~E_1~0_30) (= v_~m_pc~0_18 0) (= 1 v_~t1_i~0_7)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ~t1_st~0=v_~t1_st~0_20, ~t1_pc~0=v_~t1_pc~0_18, ~M_E~0=v_~M_E~0_19, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_#t~ret8=|v_ULTIMATE.start_start_simulation_#t~ret8_4|, ~token~0=v_~token~0_8, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~E_1~0=v_~E_1~0_30, ~E_M~0=v_~E_M~0_30, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~T1_E~0=v_~T1_E~0_18, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_20, ~m_pc~0=v_~m_pc~0_18, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ~t1_st~0, ~t1_pc~0, ~M_E~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_#t~ret8, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~E_1~0, ~E_M~0, ULTIMATE.start_main_#res, ~T1_E~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0, ULTIMATE.start_main_~__retres1~3] 797#L165 [720] L165-->L172-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_3 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_3, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 742#L172-1 [914] L172-1-->L177-1: Formula: (and (< 1 v_~t1_i~0_4) (= v_~t1_st~0_3 2)) InVars {~t1_i~0=v_~t1_i~0_4} OutVars{~t1_st~0=v_~t1_st~0_3, ~t1_i~0=v_~t1_i~0_4} AuxVars[] AssignedVars[~t1_st~0] 743#L177-1 [654] L177-1-->L261-1: Formula: (and (= 0 v_~M_E~0_3) (= v_~M_E~0_2 1)) InVars {~M_E~0=v_~M_E~0_3} OutVars{~M_E~0=v_~M_E~0_2} AuxVars[] AssignedVars[~M_E~0] 752#L261-1 [781] L261-1-->L266-1: Formula: (and (= v_~T1_E~0_2 1) (= 0 v_~T1_E~0_3)) InVars {~T1_E~0=v_~T1_E~0_3} OutVars{~T1_E~0=v_~T1_E~0_2} AuxVars[] AssignedVars[~T1_E~0] 817#L266-1 [921] L266-1-->L271-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 749#L271-1 [923] L271-1-->L276-1: Formula: (< v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 750#L276-1 [657] L276-1-->L126: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_3, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_4, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_1|, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_3|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_master_triggered_#res] 754#L126 [755] L126-->L127: Formula: (= v_~m_pc~0_2 1) InVars {~m_pc~0=v_~m_pc~0_2} OutVars{~m_pc~0=v_~m_pc~0_2} AuxVars[] AssignedVars[] 791#L127 [712] L127-->L137: Formula: (and (= v_~E_M~0_8 1) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_4 1)) InVars {~E_M~0=v_~E_M~0_8} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_4, ~E_M~0=v_~E_M~0_8} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 792#L137 [1058] L137-->L321: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_16| v_ULTIMATE.start_activate_threads_~tmp~1_29) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_29 |v_ULTIMATE.start_is_master_triggered_#res_16|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_29, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_16|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 715#L321 [611] L321-->L321-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_8) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8} AuxVars[] AssignedVars[] 716#L321-2 [615] L321-2-->L145: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 720#L145 [931] L145-->L145-2: Formula: (> v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 785#L145-2 [783] L145-2-->L156: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 786#L156 [1059] L156-->L329: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_29 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_29, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_16|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_transmit1_triggered_#res] 721#L329 [618] L329-->L329-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_9) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} AuxVars[] AssignedVars[] 722#L329-2 [937] L329-2-->L289-1: Formula: (> v_~M_E~0_10 1) InVars {~M_E~0=v_~M_E~0_10} OutVars{~M_E~0=v_~M_E~0_10} AuxVars[] AssignedVars[] 729#L289-1 [939] L289-1-->L294-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 799#L294-1 [941] L294-1-->L299-1: Formula: (> 1 v_~E_M~0_12) InVars {~E_M~0=v_~E_M~0_12} OutVars{~E_M~0=v_~E_M~0_12} AuxVars[] AssignedVars[] 723#L299-1 [943] L299-1-->L430-1: Formula: (> 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 724#L430-1 33.77/12.79 [2019-03-28 12:22:03,397 INFO L796 eck$LassoCheckResult]: Loop: 724#L430-1 [1060] L430-1-->L236: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 761#L236 [1061] L236-->L190: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_22, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 788#L190 [708] L190-->L202: Formula: (and (= v_~m_st~0_8 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11 1)) InVars {~m_st~0=v_~m_st~0_8} OutVars{~m_st~0=v_~m_st~0_8, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 748#L202 [1062] L202-->L217: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 755#L217 [1064] L217-->L261-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 815#L261-2 [946] L261-2-->L261-4: Formula: (> v_~M_E~0_13 0) InVars {~M_E~0=v_~M_E~0_13} OutVars{~M_E~0=v_~M_E~0_13} AuxVars[] AssignedVars[] 811#L261-4 [950] L261-4-->L266-3: Formula: (< v_~T1_E~0_13 0) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 812#L266-3 [952] L266-3-->L271-3: Formula: (< 0 v_~E_M~0_21) InVars {~E_M~0=v_~E_M~0_21} OutVars{~E_M~0=v_~E_M~0_21} AuxVars[] AssignedVars[] 745#L271-3 [646] L271-3-->L276-3: Formula: (and (= 0 v_~E_1~0_22) (= v_~E_1~0_21 1)) InVars {~E_1~0=v_~E_1~0_22} OutVars{~E_1~0=v_~E_1~0_21} AuxVars[] AssignedVars[~E_1~0] 746#L276-3 [656] L276-3-->L126-9: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_19, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_17, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_20, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_10|, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_12|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_master_triggered_#res] 753#L126-9 [763] L126-9-->L127-3: Formula: (= v_~m_pc~0_13 1) InVars {~m_pc~0=v_~m_pc~0_13} OutVars{~m_pc~0=v_~m_pc~0_13} AuxVars[] AssignedVars[] 762#L127-3 [670] L127-3-->L137-3: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_20 1) (= 1 v_~E_M~0_22)) InVars {~E_M~0=v_~E_M~0_22} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_20, ~E_M~0=v_~E_M~0_22} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 764#L137-3 [1070] L137-3-->L321-9: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_34 |v_ULTIMATE.start_is_master_triggered_#res_21|) (= |v_ULTIMATE.start_is_master_triggered_#res_21| v_ULTIMATE.start_activate_threads_~tmp~1_34)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_34} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_34, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_34, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_21|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_21|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 804#L321-9 [789] L321-9-->L321-11: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_24) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_24} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_24} AuxVars[] AssignedVars[] 820#L321-11 [796] L321-11-->L145-9: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 809#L145-9 [753] L145-9-->L146-3: Formula: (= v_~t1_pc~0_15 1) InVars {~t1_pc~0=v_~t1_pc~0_15} OutVars{~t1_pc~0=v_~t1_pc~0_15} AuxVars[] AssignedVars[] 774#L146-3 [688] L146-3-->L156-3: Formula: (and (= 1 v_~E_1~0_24) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_28 1)) InVars {~E_1~0=v_~E_1~0_24} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_28, ~E_1~0=v_~E_1~0_24} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 775#L156-3 [1073] L156-3-->L329-9: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_34 |v_ULTIMATE.start_is_transmit1_triggered_#res_19|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_34 |v_ULTIMATE.start_is_transmit1_triggered_#res_19|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_34} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_34, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_34, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_21|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_19|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_transmit1_triggered_#res] 718#L329-9 [614] L329-9-->L329-11: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_25 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_25} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_25} AuxVars[] AssignedVars[] 719#L329-11 [1008] L329-11-->L289-3: Formula: (< v_~M_E~0_16 1) InVars {~M_E~0=v_~M_E~0_16} OutVars{~M_E~0=v_~M_E~0_16} AuxVars[] AssignedVars[] 789#L289-3 [1012] L289-3-->L294-3: Formula: (< v_~T1_E~0_16 1) InVars {~T1_E~0=v_~T1_E~0_16} OutVars{~T1_E~0=v_~T1_E~0_16} AuxVars[] AssignedVars[] 790#L294-3 [1014] L294-3-->L299-3: Formula: (> 1 v_~E_M~0_26) InVars {~E_M~0=v_~E_M~0_26} OutVars{~E_M~0=v_~E_M~0_26} AuxVars[] AssignedVars[] 816#L299-3 [1018] L299-3-->L304-3: Formula: (< 1 v_~E_1~0_28) InVars {~E_1~0=v_~E_1~0_28} OutVars{~E_1~0=v_~E_1~0_28} AuxVars[] AssignedVars[] 735#L304-3 [637] L304-3-->L190-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 736#L190-1 [705] L190-1-->L202-1: Formula: (and (= 0 v_~m_st~0_17) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18 1)) InVars {~m_st~0=v_~m_st~0_17} OutVars{~m_st~0=v_~m_st~0_17, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 739#L202-1 [1074] L202-1-->L449: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_~tmp~3] 740#L449 [1026] L449-->L449-1: Formula: (< 0 v_ULTIMATE.start_start_simulation_~tmp~3_4) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_4} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_4} AuxVars[] AssignedVars[] 773#L449-1 [707] L449-1-->L190-2: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_1, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret6=|v_ULTIMATE.start_stop_simulation_#t~ret6_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret6, ULTIMATE.start_stop_simulation_#res] 783#L190-2 [698] L190-2-->L202-2: Formula: (and (= v_~m_st~0_5 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_4 1)) InVars {~m_st~0=v_~m_st~0_5} OutVars{~m_st~0=v_~m_st~0_5, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 737#L202-2 [1076] L202-2-->L404: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_stop_simulation_#t~ret6=|v_ULTIMATE.start_stop_simulation_#t~ret6_4|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret6] 738#L404 [761] L404-->L411: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 757#L411 [1083] L411-->L430-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|, ULTIMATE.start_start_simulation_#t~ret8=|v_ULTIMATE.start_start_simulation_#t~ret8_6|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_#t~ret8] 724#L430-1 33.77/12.79 [2019-03-28 12:22:03,397 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 33.77/12.79 [2019-03-28 12:22:03,398 INFO L82 PathProgramCache]: Analyzing trace with hash -422314918, now seen corresponding path program 1 times 33.77/12.79 [2019-03-28 12:22:03,398 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 33.77/12.79 [2019-03-28 12:22:03,398 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 33.77/12.79 [2019-03-28 12:22:03,399 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:03,399 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:03,399 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:03,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 33.77/12.79 [2019-03-28 12:22:03,416 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 33.77/12.79 [2019-03-28 12:22:03,416 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 33.77/12.79 [2019-03-28 12:22:03,416 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 33.77/12.79 [2019-03-28 12:22:03,417 INFO L799 eck$LassoCheckResult]: stem already infeasible 33.77/12.79 [2019-03-28 12:22:03,417 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 33.77/12.79 [2019-03-28 12:22:03,417 INFO L82 PathProgramCache]: Analyzing trace with hash 512280887, now seen corresponding path program 2 times 33.77/12.79 [2019-03-28 12:22:03,417 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 33.77/12.79 [2019-03-28 12:22:03,417 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 33.77/12.79 [2019-03-28 12:22:03,418 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:03,418 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:03,419 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:03,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 33.77/12.79 [2019-03-28 12:22:03,442 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 33.77/12.79 [2019-03-28 12:22:03,442 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 33.77/12.79 [2019-03-28 12:22:03,442 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 33.77/12.79 [2019-03-28 12:22:03,443 INFO L811 eck$LassoCheckResult]: loop already infeasible 33.77/12.79 [2019-03-28 12:22:03,443 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 33.77/12.79 [2019-03-28 12:22:03,443 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 33.77/12.79 [2019-03-28 12:22:03,443 INFO L87 Difference]: Start difference. First operand 114 states and 254 transitions. cyclomatic complexity: 141 Second operand 3 states. 33.77/12.79 [2019-03-28 12:22:03,599 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 33.77/12.79 [2019-03-28 12:22:03,600 INFO L93 Difference]: Finished difference Result 114 states and 253 transitions. 33.77/12.79 [2019-03-28 12:22:03,600 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 33.77/12.79 [2019-03-28 12:22:03,600 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 114 states and 253 transitions. 33.77/12.79 [2019-03-28 12:22:03,602 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 91 33.77/12.79 [2019-03-28 12:22:03,603 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 114 states to 114 states and 253 transitions. 33.77/12.79 [2019-03-28 12:22:03,604 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 114 33.77/12.79 [2019-03-28 12:22:03,604 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 114 33.77/12.79 [2019-03-28 12:22:03,604 INFO L73 IsDeterministic]: Start isDeterministic. Operand 114 states and 253 transitions. 33.77/12.79 [2019-03-28 12:22:03,605 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 33.77/12.79 [2019-03-28 12:22:03,605 INFO L706 BuchiCegarLoop]: Abstraction has 114 states and 253 transitions. 33.77/12.79 [2019-03-28 12:22:03,605 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 114 states and 253 transitions. 33.77/12.79 [2019-03-28 12:22:03,610 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 114 to 114. 33.77/12.79 [2019-03-28 12:22:03,610 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. 33.77/12.79 [2019-03-28 12:22:03,611 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 253 transitions. 33.77/12.79 [2019-03-28 12:22:03,611 INFO L729 BuchiCegarLoop]: Abstraction has 114 states and 253 transitions. 33.77/12.79 [2019-03-28 12:22:03,611 INFO L609 BuchiCegarLoop]: Abstraction has 114 states and 253 transitions. 33.77/12.79 [2019-03-28 12:22:03,611 INFO L442 BuchiCegarLoop]: ======== Iteration 5============ 33.77/12.79 [2019-03-28 12:22:03,611 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 114 states and 253 transitions. 33.77/12.79 [2019-03-28 12:22:03,612 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 91 33.77/12.79 [2019-03-28 12:22:03,612 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 33.77/12.79 [2019-03-28 12:22:03,612 INFO L119 BuchiIsEmpty]: Starting construction of run 33.77/12.79 [2019-03-28 12:22:03,613 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 33.77/12.79 [2019-03-28 12:22:03,614 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 33.77/12.79 [2019-03-28 12:22:03,614 INFO L794 eck$LassoCheckResult]: Stem: 1034#ULTIMATE.startENTRY [1057] ULTIMATE.startENTRY-->L165: Formula: (and (= 0 v_~m_st~0_20) (= 2 v_~E_M~0_30) (= v_~t1_pc~0_18 0) (= 0 v_~t1_st~0_20) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 0 v_~token~0_8) (= v_~M_E~0_19 2) (= v_~local~0_6 0) (= v_~m_i~0_7 1) (= 2 v_~E_1~0_30) (= v_~m_pc~0_18 0) (= 1 v_~t1_i~0_7)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ~t1_st~0=v_~t1_st~0_20, ~t1_pc~0=v_~t1_pc~0_18, ~M_E~0=v_~M_E~0_19, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_#t~ret8=|v_ULTIMATE.start_start_simulation_#t~ret8_4|, ~token~0=v_~token~0_8, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~E_1~0=v_~E_1~0_30, ~E_M~0=v_~E_M~0_30, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~T1_E~0=v_~T1_E~0_18, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_20, ~m_pc~0=v_~m_pc~0_18, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ~t1_st~0, ~t1_pc~0, ~M_E~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_#t~ret8, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~E_1~0, ~E_M~0, ULTIMATE.start_main_#res, ~T1_E~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0, ULTIMATE.start_main_~__retres1~3] 1033#L165 [720] L165-->L172-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_3 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_3, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 978#L172-1 [642] L172-1-->L177-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 979#L177-1 [654] L177-1-->L261-1: Formula: (and (= 0 v_~M_E~0_3) (= v_~M_E~0_2 1)) InVars {~M_E~0=v_~M_E~0_3} OutVars{~M_E~0=v_~M_E~0_2} AuxVars[] AssignedVars[~M_E~0] 988#L261-1 [781] L261-1-->L266-1: Formula: (and (= v_~T1_E~0_2 1) (= 0 v_~T1_E~0_3)) InVars {~T1_E~0=v_~T1_E~0_3} OutVars{~T1_E~0=v_~T1_E~0_2} AuxVars[] AssignedVars[~T1_E~0] 1053#L266-1 [921] L266-1-->L271-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 985#L271-1 [923] L271-1-->L276-1: Formula: (< v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 986#L276-1 [657] L276-1-->L126: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_3, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_4, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_1|, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_3|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_master_triggered_#res] 990#L126 [755] L126-->L127: Formula: (= v_~m_pc~0_2 1) InVars {~m_pc~0=v_~m_pc~0_2} OutVars{~m_pc~0=v_~m_pc~0_2} AuxVars[] AssignedVars[] 1027#L127 [712] L127-->L137: Formula: (and (= v_~E_M~0_8 1) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_4 1)) InVars {~E_M~0=v_~E_M~0_8} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_4, ~E_M~0=v_~E_M~0_8} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 1028#L137 [1058] L137-->L321: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_16| v_ULTIMATE.start_activate_threads_~tmp~1_29) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_29 |v_ULTIMATE.start_is_master_triggered_#res_16|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_29, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_16|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 951#L321 [611] L321-->L321-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_8) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8} AuxVars[] AssignedVars[] 952#L321-2 [615] L321-2-->L145: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 956#L145 [931] L145-->L145-2: Formula: (> v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 1021#L145-2 [783] L145-2-->L156: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 1022#L156 [1059] L156-->L329: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_29 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_29, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_16|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_transmit1_triggered_#res] 957#L329 [618] L329-->L329-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_9) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} AuxVars[] AssignedVars[] 958#L329-2 [937] L329-2-->L289-1: Formula: (> v_~M_E~0_10 1) InVars {~M_E~0=v_~M_E~0_10} OutVars{~M_E~0=v_~M_E~0_10} AuxVars[] AssignedVars[] 965#L289-1 [939] L289-1-->L294-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 1035#L294-1 [941] L294-1-->L299-1: Formula: (> 1 v_~E_M~0_12) InVars {~E_M~0=v_~E_M~0_12} OutVars{~E_M~0=v_~E_M~0_12} AuxVars[] AssignedVars[] 959#L299-1 [943] L299-1-->L430-1: Formula: (> 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 960#L430-1 33.77/12.79 [2019-03-28 12:22:03,615 INFO L796 eck$LassoCheckResult]: Loop: 960#L430-1 [1060] L430-1-->L236: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 997#L236 [1061] L236-->L190: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_22, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 1024#L190 [708] L190-->L202: Formula: (and (= v_~m_st~0_8 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11 1)) InVars {~m_st~0=v_~m_st~0_8} OutVars{~m_st~0=v_~m_st~0_8, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 984#L202 [1062] L202-->L217: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 991#L217 [1064] L217-->L261-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 1051#L261-2 [946] L261-2-->L261-4: Formula: (> v_~M_E~0_13 0) InVars {~M_E~0=v_~M_E~0_13} OutVars{~M_E~0=v_~M_E~0_13} AuxVars[] AssignedVars[] 1047#L261-4 [950] L261-4-->L266-3: Formula: (< v_~T1_E~0_13 0) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 1048#L266-3 [952] L266-3-->L271-3: Formula: (< 0 v_~E_M~0_21) InVars {~E_M~0=v_~E_M~0_21} OutVars{~E_M~0=v_~E_M~0_21} AuxVars[] AssignedVars[] 981#L271-3 [646] L271-3-->L276-3: Formula: (and (= 0 v_~E_1~0_22) (= v_~E_1~0_21 1)) InVars {~E_1~0=v_~E_1~0_22} OutVars{~E_1~0=v_~E_1~0_21} AuxVars[] AssignedVars[~E_1~0] 982#L276-3 [656] L276-3-->L126-9: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_19, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_17, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_20, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_10|, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_12|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_master_triggered_#res] 989#L126-9 [763] L126-9-->L127-3: Formula: (= v_~m_pc~0_13 1) InVars {~m_pc~0=v_~m_pc~0_13} OutVars{~m_pc~0=v_~m_pc~0_13} AuxVars[] AssignedVars[] 998#L127-3 [670] L127-3-->L137-3: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_20 1) (= 1 v_~E_M~0_22)) InVars {~E_M~0=v_~E_M~0_22} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_20, ~E_M~0=v_~E_M~0_22} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 1000#L137-3 [1070] L137-3-->L321-9: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_34 |v_ULTIMATE.start_is_master_triggered_#res_21|) (= |v_ULTIMATE.start_is_master_triggered_#res_21| v_ULTIMATE.start_activate_threads_~tmp~1_34)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_34} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_34, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_34, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_21|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_21|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 1040#L321-9 [789] L321-9-->L321-11: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_24) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_24} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_24} AuxVars[] AssignedVars[] 1056#L321-11 [796] L321-11-->L145-9: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 1045#L145-9 [753] L145-9-->L146-3: Formula: (= v_~t1_pc~0_15 1) InVars {~t1_pc~0=v_~t1_pc~0_15} OutVars{~t1_pc~0=v_~t1_pc~0_15} AuxVars[] AssignedVars[] 1010#L146-3 [688] L146-3-->L156-3: Formula: (and (= 1 v_~E_1~0_24) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_28 1)) InVars {~E_1~0=v_~E_1~0_24} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_28, ~E_1~0=v_~E_1~0_24} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 1011#L156-3 [1073] L156-3-->L329-9: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_34 |v_ULTIMATE.start_is_transmit1_triggered_#res_19|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_34 |v_ULTIMATE.start_is_transmit1_triggered_#res_19|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_34} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_34, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_34, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_21|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_19|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_transmit1_triggered_#res] 954#L329-9 [614] L329-9-->L329-11: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_25 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_25} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_25} AuxVars[] AssignedVars[] 955#L329-11 [1008] L329-11-->L289-3: Formula: (< v_~M_E~0_16 1) InVars {~M_E~0=v_~M_E~0_16} OutVars{~M_E~0=v_~M_E~0_16} AuxVars[] AssignedVars[] 1025#L289-3 [1012] L289-3-->L294-3: Formula: (< v_~T1_E~0_16 1) InVars {~T1_E~0=v_~T1_E~0_16} OutVars{~T1_E~0=v_~T1_E~0_16} AuxVars[] AssignedVars[] 1026#L294-3 [1014] L294-3-->L299-3: Formula: (> 1 v_~E_M~0_26) InVars {~E_M~0=v_~E_M~0_26} OutVars{~E_M~0=v_~E_M~0_26} AuxVars[] AssignedVars[] 1052#L299-3 [1018] L299-3-->L304-3: Formula: (< 1 v_~E_1~0_28) InVars {~E_1~0=v_~E_1~0_28} OutVars{~E_1~0=v_~E_1~0_28} AuxVars[] AssignedVars[] 971#L304-3 [637] L304-3-->L190-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 972#L190-1 [705] L190-1-->L202-1: Formula: (and (= 0 v_~m_st~0_17) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18 1)) InVars {~m_st~0=v_~m_st~0_17} OutVars{~m_st~0=v_~m_st~0_17, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 975#L202-1 [1074] L202-1-->L449: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_~tmp~3] 976#L449 [1026] L449-->L449-1: Formula: (< 0 v_ULTIMATE.start_start_simulation_~tmp~3_4) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_4} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_4} AuxVars[] AssignedVars[] 1009#L449-1 [707] L449-1-->L190-2: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_1, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret6=|v_ULTIMATE.start_stop_simulation_#t~ret6_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret6, ULTIMATE.start_stop_simulation_#res] 1019#L190-2 [698] L190-2-->L202-2: Formula: (and (= v_~m_st~0_5 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_4 1)) InVars {~m_st~0=v_~m_st~0_5} OutVars{~m_st~0=v_~m_st~0_5, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 973#L202-2 [1076] L202-2-->L404: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_stop_simulation_#t~ret6=|v_ULTIMATE.start_stop_simulation_#t~ret6_4|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret6] 974#L404 [761] L404-->L411: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 993#L411 [1083] L411-->L430-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|, ULTIMATE.start_start_simulation_#t~ret8=|v_ULTIMATE.start_start_simulation_#t~ret8_6|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_#t~ret8] 960#L430-1 33.77/12.79 [2019-03-28 12:22:03,615 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 33.77/12.79 [2019-03-28 12:22:03,616 INFO L82 PathProgramCache]: Analyzing trace with hash 1640767306, now seen corresponding path program 1 times 33.77/12.79 [2019-03-28 12:22:03,616 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 33.77/12.79 [2019-03-28 12:22:03,616 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 33.77/12.79 [2019-03-28 12:22:03,617 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:03,617 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:03,617 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:03,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 33.77/12.79 [2019-03-28 12:22:03,634 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 33.77/12.79 [2019-03-28 12:22:03,634 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 33.77/12.79 [2019-03-28 12:22:03,634 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 33.77/12.79 [2019-03-28 12:22:03,635 INFO L799 eck$LassoCheckResult]: stem already infeasible 33.77/12.79 [2019-03-28 12:22:03,635 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 33.77/12.79 [2019-03-28 12:22:03,635 INFO L82 PathProgramCache]: Analyzing trace with hash 512280887, now seen corresponding path program 3 times 33.77/12.79 [2019-03-28 12:22:03,635 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 33.77/12.79 [2019-03-28 12:22:03,635 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 33.77/12.79 [2019-03-28 12:22:03,636 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:03,636 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:03,636 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:03,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 33.77/12.79 [2019-03-28 12:22:03,665 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 33.77/12.79 [2019-03-28 12:22:03,666 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 33.77/12.79 [2019-03-28 12:22:03,666 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 33.77/12.79 [2019-03-28 12:22:03,666 INFO L811 eck$LassoCheckResult]: loop already infeasible 33.77/12.79 [2019-03-28 12:22:03,666 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 33.77/12.79 [2019-03-28 12:22:03,666 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 33.77/12.79 [2019-03-28 12:22:03,667 INFO L87 Difference]: Start difference. First operand 114 states and 253 transitions. cyclomatic complexity: 140 Second operand 3 states. 33.77/12.79 [2019-03-28 12:22:03,903 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 33.77/12.79 [2019-03-28 12:22:03,904 INFO L93 Difference]: Finished difference Result 193 states and 421 transitions. 33.77/12.79 [2019-03-28 12:22:03,904 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 33.77/12.79 [2019-03-28 12:22:03,904 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 193 states and 421 transitions. 33.77/12.79 [2019-03-28 12:22:03,906 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 170 33.77/12.79 [2019-03-28 12:22:03,909 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 193 states to 193 states and 421 transitions. 33.77/12.79 [2019-03-28 12:22:03,909 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 193 33.77/12.79 [2019-03-28 12:22:03,909 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 193 33.77/12.79 [2019-03-28 12:22:03,909 INFO L73 IsDeterministic]: Start isDeterministic. Operand 193 states and 421 transitions. 33.77/12.79 [2019-03-28 12:22:03,910 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 33.77/12.79 [2019-03-28 12:22:03,911 INFO L706 BuchiCegarLoop]: Abstraction has 193 states and 421 transitions. 33.77/12.79 [2019-03-28 12:22:03,911 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 193 states and 421 transitions. 33.77/12.79 [2019-03-28 12:22:03,919 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 193 to 193. 33.77/12.79 [2019-03-28 12:22:03,919 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 193 states. 33.77/12.79 [2019-03-28 12:22:03,920 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 193 states to 193 states and 421 transitions. 33.77/12.79 [2019-03-28 12:22:03,921 INFO L729 BuchiCegarLoop]: Abstraction has 193 states and 421 transitions. 33.77/12.79 [2019-03-28 12:22:03,921 INFO L609 BuchiCegarLoop]: Abstraction has 193 states and 421 transitions. 33.77/12.79 [2019-03-28 12:22:03,921 INFO L442 BuchiCegarLoop]: ======== Iteration 6============ 33.77/12.79 [2019-03-28 12:22:03,921 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 193 states and 421 transitions. 33.77/12.79 [2019-03-28 12:22:03,922 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 170 33.77/12.79 [2019-03-28 12:22:03,923 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 33.77/12.79 [2019-03-28 12:22:03,923 INFO L119 BuchiIsEmpty]: Starting construction of run 33.77/12.79 [2019-03-28 12:22:03,924 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 33.77/12.79 [2019-03-28 12:22:03,924 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 33.77/12.79 [2019-03-28 12:22:03,924 INFO L794 eck$LassoCheckResult]: Stem: 1351#ULTIMATE.startENTRY [1057] ULTIMATE.startENTRY-->L165: Formula: (and (= 0 v_~m_st~0_20) (= 2 v_~E_M~0_30) (= v_~t1_pc~0_18 0) (= 0 v_~t1_st~0_20) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 0 v_~token~0_8) (= v_~M_E~0_19 2) (= v_~local~0_6 0) (= v_~m_i~0_7 1) (= 2 v_~E_1~0_30) (= v_~m_pc~0_18 0) (= 1 v_~t1_i~0_7)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ~t1_st~0=v_~t1_st~0_20, ~t1_pc~0=v_~t1_pc~0_18, ~M_E~0=v_~M_E~0_19, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_#t~ret8=|v_ULTIMATE.start_start_simulation_#t~ret8_4|, ~token~0=v_~token~0_8, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~E_1~0=v_~E_1~0_30, ~E_M~0=v_~E_M~0_30, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~T1_E~0=v_~T1_E~0_18, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_20, ~m_pc~0=v_~m_pc~0_18, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ~t1_st~0, ~t1_pc~0, ~M_E~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_#t~ret8, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~E_1~0, ~E_M~0, ULTIMATE.start_main_#res, ~T1_E~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0, ULTIMATE.start_main_~__retres1~3] 1350#L165 [720] L165-->L172-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_3 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_3, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 1294#L172-1 [642] L172-1-->L177-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 1295#L177-1 [917] L177-1-->L261-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 1304#L261-1 [781] L261-1-->L266-1: Formula: (and (= v_~T1_E~0_2 1) (= 0 v_~T1_E~0_3)) InVars {~T1_E~0=v_~T1_E~0_3} OutVars{~T1_E~0=v_~T1_E~0_2} AuxVars[] AssignedVars[~T1_E~0] 1372#L266-1 [921] L266-1-->L271-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 1301#L271-1 [923] L271-1-->L276-1: Formula: (< v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 1302#L276-1 [657] L276-1-->L126: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_3, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_4, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_1|, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_3|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_master_triggered_#res] 1306#L126 [755] L126-->L127: Formula: (= v_~m_pc~0_2 1) InVars {~m_pc~0=v_~m_pc~0_2} OutVars{~m_pc~0=v_~m_pc~0_2} AuxVars[] AssignedVars[] 1344#L127 [712] L127-->L137: Formula: (and (= v_~E_M~0_8 1) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_4 1)) InVars {~E_M~0=v_~E_M~0_8} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_4, ~E_M~0=v_~E_M~0_8} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 1345#L137 [1058] L137-->L321: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_16| v_ULTIMATE.start_activate_threads_~tmp~1_29) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_29 |v_ULTIMATE.start_is_master_triggered_#res_16|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_29, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_16|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 1266#L321 [611] L321-->L321-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_8) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8} AuxVars[] AssignedVars[] 1267#L321-2 [615] L321-2-->L145: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 1271#L145 [931] L145-->L145-2: Formula: (> v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 1338#L145-2 [783] L145-2-->L156: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 1339#L156 [1059] L156-->L329: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_29 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_29, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_16|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_transmit1_triggered_#res] 1272#L329 [618] L329-->L329-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_9) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} AuxVars[] AssignedVars[] 1273#L329-2 [937] L329-2-->L289-1: Formula: (> v_~M_E~0_10 1) InVars {~M_E~0=v_~M_E~0_10} OutVars{~M_E~0=v_~M_E~0_10} AuxVars[] AssignedVars[] 1280#L289-1 [939] L289-1-->L294-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 1352#L294-1 [941] L294-1-->L299-1: Formula: (> 1 v_~E_M~0_12) InVars {~E_M~0=v_~E_M~0_12} OutVars{~E_M~0=v_~E_M~0_12} AuxVars[] AssignedVars[] 1274#L299-1 [943] L299-1-->L430-1: Formula: (> 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 1275#L430-1 33.77/12.79 [2019-03-28 12:22:03,925 INFO L796 eck$LassoCheckResult]: Loop: 1275#L430-1 [1060] L430-1-->L236: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 1313#L236 [1061] L236-->L190: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_22, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 1341#L190 [708] L190-->L202: Formula: (and (= v_~m_st~0_8 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11 1)) InVars {~m_st~0=v_~m_st~0_8} OutVars{~m_st~0=v_~m_st~0_8, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 1300#L202 [1062] L202-->L217: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 1307#L217 [1064] L217-->L261-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 1369#L261-2 [946] L261-2-->L261-4: Formula: (> v_~M_E~0_13 0) InVars {~M_E~0=v_~M_E~0_13} OutVars{~M_E~0=v_~M_E~0_13} AuxVars[] AssignedVars[] 1370#L261-4 [950] L261-4-->L266-3: Formula: (< v_~T1_E~0_13 0) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 1444#L266-3 [952] L266-3-->L271-3: Formula: (< 0 v_~E_M~0_21) InVars {~E_M~0=v_~E_M~0_21} OutVars{~E_M~0=v_~E_M~0_21} AuxVars[] AssignedVars[] 1443#L271-3 [646] L271-3-->L276-3: Formula: (and (= 0 v_~E_1~0_22) (= v_~E_1~0_21 1)) InVars {~E_1~0=v_~E_1~0_22} OutVars{~E_1~0=v_~E_1~0_21} AuxVars[] AssignedVars[~E_1~0] 1442#L276-3 [656] L276-3-->L126-9: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_19, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_17, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_20, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_10|, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_12|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_master_triggered_#res] 1441#L126-9 [763] L126-9-->L127-3: Formula: (= v_~m_pc~0_13 1) InVars {~m_pc~0=v_~m_pc~0_13} OutVars{~m_pc~0=v_~m_pc~0_13} AuxVars[] AssignedVars[] 1440#L127-3 [670] L127-3-->L137-3: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_20 1) (= 1 v_~E_M~0_22)) InVars {~E_M~0=v_~E_M~0_22} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_20, ~E_M~0=v_~E_M~0_22} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 1438#L137-3 [1070] L137-3-->L321-9: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_34 |v_ULTIMATE.start_is_master_triggered_#res_21|) (= |v_ULTIMATE.start_is_master_triggered_#res_21| v_ULTIMATE.start_activate_threads_~tmp~1_34)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_34} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_34, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_34, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_21|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_21|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 1437#L321-9 [789] L321-9-->L321-11: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_24) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_24} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_24} AuxVars[] AssignedVars[] 1436#L321-11 [796] L321-11-->L145-9: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 1435#L145-9 [753] L145-9-->L146-3: Formula: (= v_~t1_pc~0_15 1) InVars {~t1_pc~0=v_~t1_pc~0_15} OutVars{~t1_pc~0=v_~t1_pc~0_15} AuxVars[] AssignedVars[] 1433#L146-3 [688] L146-3-->L156-3: Formula: (and (= 1 v_~E_1~0_24) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_28 1)) InVars {~E_1~0=v_~E_1~0_24} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_28, ~E_1~0=v_~E_1~0_24} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 1432#L156-3 [1073] L156-3-->L329-9: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_34 |v_ULTIMATE.start_is_transmit1_triggered_#res_19|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_34 |v_ULTIMATE.start_is_transmit1_triggered_#res_19|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_34} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_34, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_34, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_21|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_19|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_transmit1_triggered_#res] 1269#L329-9 [614] L329-9-->L329-11: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_25 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_25} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_25} AuxVars[] AssignedVars[] 1270#L329-11 [1009] L329-11-->L289-3: Formula: (> v_~M_E~0_16 1) InVars {~M_E~0=v_~M_E~0_16} OutVars{~M_E~0=v_~M_E~0_16} AuxVars[] AssignedVars[] 1377#L289-3 [1012] L289-3-->L294-3: Formula: (< v_~T1_E~0_16 1) InVars {~T1_E~0=v_~T1_E~0_16} OutVars{~T1_E~0=v_~T1_E~0_16} AuxVars[] AssignedVars[] 1412#L294-3 [1014] L294-3-->L299-3: Formula: (> 1 v_~E_M~0_26) InVars {~E_M~0=v_~E_M~0_26} OutVars{~E_M~0=v_~E_M~0_26} AuxVars[] AssignedVars[] 1411#L299-3 [1018] L299-3-->L304-3: Formula: (< 1 v_~E_1~0_28) InVars {~E_1~0=v_~E_1~0_28} OutVars{~E_1~0=v_~E_1~0_28} AuxVars[] AssignedVars[] 1410#L304-3 [637] L304-3-->L190-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 1409#L190-1 [705] L190-1-->L202-1: Formula: (and (= 0 v_~m_st~0_17) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18 1)) InVars {~m_st~0=v_~m_st~0_17} OutVars{~m_st~0=v_~m_st~0_17, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 1406#L202-1 [1074] L202-1-->L449: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_~tmp~3] 1405#L449 [1026] L449-->L449-1: Formula: (< 0 v_ULTIMATE.start_start_simulation_~tmp~3_4) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_4} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_4} AuxVars[] AssignedVars[] 1404#L449-1 [707] L449-1-->L190-2: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_1, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret6=|v_ULTIMATE.start_stop_simulation_#t~ret6_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret6, ULTIMATE.start_stop_simulation_#res] 1403#L190-2 [698] L190-2-->L202-2: Formula: (and (= v_~m_st~0_5 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_4 1)) InVars {~m_st~0=v_~m_st~0_5} OutVars{~m_st~0=v_~m_st~0_5, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 1401#L202-2 [1076] L202-2-->L404: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_stop_simulation_#t~ret6=|v_ULTIMATE.start_stop_simulation_#t~ret6_4|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret6] 1363#L404 [761] L404-->L411: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 1309#L411 [1083] L411-->L430-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|, ULTIMATE.start_start_simulation_#t~ret8=|v_ULTIMATE.start_start_simulation_#t~ret8_6|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_#t~ret8] 1275#L430-1 33.77/12.79 [2019-03-28 12:22:03,925 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 33.77/12.79 [2019-03-28 12:22:03,926 INFO L82 PathProgramCache]: Analyzing trace with hash 1403743523, now seen corresponding path program 1 times 33.77/12.79 [2019-03-28 12:22:03,926 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 33.77/12.79 [2019-03-28 12:22:03,926 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 33.77/12.79 [2019-03-28 12:22:03,927 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:03,927 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:03,927 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:03,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 33.77/12.79 [2019-03-28 12:22:03,947 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 33.77/12.79 [2019-03-28 12:22:03,947 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 33.77/12.79 [2019-03-28 12:22:03,947 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 33.77/12.79 [2019-03-28 12:22:03,948 INFO L799 eck$LassoCheckResult]: stem already infeasible 33.77/12.79 [2019-03-28 12:22:03,948 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 33.77/12.79 [2019-03-28 12:22:03,948 INFO L82 PathProgramCache]: Analyzing trace with hash 218877880, now seen corresponding path program 1 times 33.77/12.79 [2019-03-28 12:22:03,948 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 33.77/12.79 [2019-03-28 12:22:03,948 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 33.77/12.79 [2019-03-28 12:22:03,949 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:03,949 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:03,950 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:03,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 33.77/12.79 [2019-03-28 12:22:03,990 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 33.77/12.79 [2019-03-28 12:22:03,991 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 33.77/12.79 [2019-03-28 12:22:03,991 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 33.77/12.79 [2019-03-28 12:22:03,991 INFO L811 eck$LassoCheckResult]: loop already infeasible 33.77/12.79 [2019-03-28 12:22:03,991 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 33.77/12.79 [2019-03-28 12:22:03,991 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 33.77/12.79 [2019-03-28 12:22:03,992 INFO L87 Difference]: Start difference. First operand 193 states and 421 transitions. cyclomatic complexity: 229 Second operand 3 states. 33.77/12.79 [2019-03-28 12:22:04,157 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 33.77/12.79 [2019-03-28 12:22:04,157 INFO L93 Difference]: Finished difference Result 193 states and 405 transitions. 33.77/12.79 [2019-03-28 12:22:04,157 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 33.77/12.79 [2019-03-28 12:22:04,158 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 193 states and 405 transitions. 33.77/12.79 [2019-03-28 12:22:04,160 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 170 33.77/12.79 [2019-03-28 12:22:04,161 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 193 states to 193 states and 405 transitions. 33.77/12.79 [2019-03-28 12:22:04,162 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 193 33.77/12.79 [2019-03-28 12:22:04,162 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 193 33.77/12.79 [2019-03-28 12:22:04,162 INFO L73 IsDeterministic]: Start isDeterministic. Operand 193 states and 405 transitions. 33.77/12.79 [2019-03-28 12:22:04,163 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 33.77/12.79 [2019-03-28 12:22:04,163 INFO L706 BuchiCegarLoop]: Abstraction has 193 states and 405 transitions. 33.77/12.79 [2019-03-28 12:22:04,163 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 193 states and 405 transitions. 33.77/12.79 [2019-03-28 12:22:04,169 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 193 to 193. 33.77/12.79 [2019-03-28 12:22:04,169 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 193 states. 33.77/12.79 [2019-03-28 12:22:04,170 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 193 states to 193 states and 405 transitions. 33.77/12.79 [2019-03-28 12:22:04,171 INFO L729 BuchiCegarLoop]: Abstraction has 193 states and 405 transitions. 33.77/12.79 [2019-03-28 12:22:04,171 INFO L609 BuchiCegarLoop]: Abstraction has 193 states and 405 transitions. 33.77/12.79 [2019-03-28 12:22:04,171 INFO L442 BuchiCegarLoop]: ======== Iteration 7============ 33.77/12.79 [2019-03-28 12:22:04,171 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 193 states and 405 transitions. 33.77/12.79 [2019-03-28 12:22:04,172 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 170 33.77/12.79 [2019-03-28 12:22:04,172 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 33.77/12.79 [2019-03-28 12:22:04,173 INFO L119 BuchiIsEmpty]: Starting construction of run 33.77/12.79 [2019-03-28 12:22:04,173 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 33.77/12.79 [2019-03-28 12:22:04,174 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 33.77/12.79 [2019-03-28 12:22:04,178 INFO L794 eck$LassoCheckResult]: Stem: 1743#ULTIMATE.startENTRY [1057] ULTIMATE.startENTRY-->L165: Formula: (and (= 0 v_~m_st~0_20) (= 2 v_~E_M~0_30) (= v_~t1_pc~0_18 0) (= 0 v_~t1_st~0_20) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 0 v_~token~0_8) (= v_~M_E~0_19 2) (= v_~local~0_6 0) (= v_~m_i~0_7 1) (= 2 v_~E_1~0_30) (= v_~m_pc~0_18 0) (= 1 v_~t1_i~0_7)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ~t1_st~0=v_~t1_st~0_20, ~t1_pc~0=v_~t1_pc~0_18, ~M_E~0=v_~M_E~0_19, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_#t~ret8=|v_ULTIMATE.start_start_simulation_#t~ret8_4|, ~token~0=v_~token~0_8, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~E_1~0=v_~E_1~0_30, ~E_M~0=v_~E_M~0_30, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~T1_E~0=v_~T1_E~0_18, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_20, ~m_pc~0=v_~m_pc~0_18, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ~t1_st~0, ~t1_pc~0, ~M_E~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_#t~ret8, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~E_1~0, ~E_M~0, ULTIMATE.start_main_#res, ~T1_E~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0, ULTIMATE.start_main_~__retres1~3] 1742#L165 [720] L165-->L172-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_3 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_3, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 1687#L172-1 [642] L172-1-->L177-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 1688#L177-1 [917] L177-1-->L261-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 1697#L261-1 [919] L261-1-->L266-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 1763#L266-1 [921] L266-1-->L271-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 1694#L271-1 [923] L271-1-->L276-1: Formula: (< v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 1695#L276-1 [657] L276-1-->L126: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_3, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_4, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_1|, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_3|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_master_triggered_#res] 1699#L126 [755] L126-->L127: Formula: (= v_~m_pc~0_2 1) InVars {~m_pc~0=v_~m_pc~0_2} OutVars{~m_pc~0=v_~m_pc~0_2} AuxVars[] AssignedVars[] 1736#L127 [712] L127-->L137: Formula: (and (= v_~E_M~0_8 1) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_4 1)) InVars {~E_M~0=v_~E_M~0_8} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_4, ~E_M~0=v_~E_M~0_8} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 1737#L137 [1058] L137-->L321: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_16| v_ULTIMATE.start_activate_threads_~tmp~1_29) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_29 |v_ULTIMATE.start_is_master_triggered_#res_16|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_29, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_16|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 1661#L321 [611] L321-->L321-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_8) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8} AuxVars[] AssignedVars[] 1662#L321-2 [615] L321-2-->L145: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 1665#L145 [931] L145-->L145-2: Formula: (> v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 1731#L145-2 [783] L145-2-->L156: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 1732#L156 [1059] L156-->L329: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_29 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_29, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_16|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_transmit1_triggered_#res] 1668#L329 [618] L329-->L329-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_9) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} AuxVars[] AssignedVars[] 1669#L329-2 [937] L329-2-->L289-1: Formula: (> v_~M_E~0_10 1) InVars {~M_E~0=v_~M_E~0_10} OutVars{~M_E~0=v_~M_E~0_10} AuxVars[] AssignedVars[] 1674#L289-1 [939] L289-1-->L294-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 1744#L294-1 [941] L294-1-->L299-1: Formula: (> 1 v_~E_M~0_12) InVars {~E_M~0=v_~E_M~0_12} OutVars{~E_M~0=v_~E_M~0_12} AuxVars[] AssignedVars[] 1670#L299-1 [943] L299-1-->L430-1: Formula: (> 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 1671#L430-1 33.77/12.79 [2019-03-28 12:22:04,179 INFO L796 eck$LassoCheckResult]: Loop: 1671#L430-1 [1060] L430-1-->L236: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 1706#L236 [1061] L236-->L190: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_22, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 1735#L190 [708] L190-->L202: Formula: (and (= v_~m_st~0_8 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11 1)) InVars {~m_st~0=v_~m_st~0_8} OutVars{~m_st~0=v_~m_st~0_8, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 1693#L202 [1062] L202-->L217: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 1700#L217 [1064] L217-->L261-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 1761#L261-2 [946] L261-2-->L261-4: Formula: (> v_~M_E~0_13 0) InVars {~M_E~0=v_~M_E~0_13} OutVars{~M_E~0=v_~M_E~0_13} AuxVars[] AssignedVars[] 1762#L261-4 [951] L261-4-->L266-3: Formula: (> v_~T1_E~0_13 0) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 1767#L266-3 [952] L266-3-->L271-3: Formula: (< 0 v_~E_M~0_21) InVars {~E_M~0=v_~E_M~0_21} OutVars{~E_M~0=v_~E_M~0_21} AuxVars[] AssignedVars[] 1690#L271-3 [646] L271-3-->L276-3: Formula: (and (= 0 v_~E_1~0_22) (= v_~E_1~0_21 1)) InVars {~E_1~0=v_~E_1~0_22} OutVars{~E_1~0=v_~E_1~0_21} AuxVars[] AssignedVars[~E_1~0] 1691#L276-3 [656] L276-3-->L126-9: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_19, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_17, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_20, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_10|, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_12|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_master_triggered_#res] 1698#L126-9 [763] L126-9-->L127-3: Formula: (= v_~m_pc~0_13 1) InVars {~m_pc~0=v_~m_pc~0_13} OutVars{~m_pc~0=v_~m_pc~0_13} AuxVars[] AssignedVars[] 1707#L127-3 [670] L127-3-->L137-3: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_20 1) (= 1 v_~E_M~0_22)) InVars {~E_M~0=v_~E_M~0_22} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_20, ~E_M~0=v_~E_M~0_22} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 1709#L137-3 [1070] L137-3-->L321-9: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_34 |v_ULTIMATE.start_is_master_triggered_#res_21|) (= |v_ULTIMATE.start_is_master_triggered_#res_21| v_ULTIMATE.start_activate_threads_~tmp~1_34)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_34} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_34, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_34, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_21|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_21|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 1749#L321-9 [789] L321-9-->L321-11: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_24) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_24} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_24} AuxVars[] AssignedVars[] 1766#L321-11 [796] L321-11-->L145-9: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 1754#L145-9 [753] L145-9-->L146-3: Formula: (= v_~t1_pc~0_15 1) InVars {~t1_pc~0=v_~t1_pc~0_15} OutVars{~t1_pc~0=v_~t1_pc~0_15} AuxVars[] AssignedVars[] 1719#L146-3 [688] L146-3-->L156-3: Formula: (and (= 1 v_~E_1~0_24) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_28 1)) InVars {~E_1~0=v_~E_1~0_24} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_28, ~E_1~0=v_~E_1~0_24} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 1720#L156-3 [1073] L156-3-->L329-9: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_34 |v_ULTIMATE.start_is_transmit1_triggered_#res_19|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_34 |v_ULTIMATE.start_is_transmit1_triggered_#res_19|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_34} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_34, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_34, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_21|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_19|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_transmit1_triggered_#res] 1663#L329-9 [614] L329-9-->L329-11: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_25 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_25} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_25} AuxVars[] AssignedVars[] 1664#L329-11 [1009] L329-11-->L289-3: Formula: (> v_~M_E~0_16 1) InVars {~M_E~0=v_~M_E~0_16} OutVars{~M_E~0=v_~M_E~0_16} AuxVars[] AssignedVars[] 1733#L289-3 [1013] L289-3-->L294-3: Formula: (> v_~T1_E~0_16 1) InVars {~T1_E~0=v_~T1_E~0_16} OutVars{~T1_E~0=v_~T1_E~0_16} AuxVars[] AssignedVars[] 1734#L294-3 [1014] L294-3-->L299-3: Formula: (> 1 v_~E_M~0_26) InVars {~E_M~0=v_~E_M~0_26} OutVars{~E_M~0=v_~E_M~0_26} AuxVars[] AssignedVars[] 1760#L299-3 [1018] L299-3-->L304-3: Formula: (< 1 v_~E_1~0_28) InVars {~E_1~0=v_~E_1~0_28} OutVars{~E_1~0=v_~E_1~0_28} AuxVars[] AssignedVars[] 1679#L304-3 [637] L304-3-->L190-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 1680#L190-1 [705] L190-1-->L202-1: Formula: (and (= 0 v_~m_st~0_17) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18 1)) InVars {~m_st~0=v_~m_st~0_17} OutVars{~m_st~0=v_~m_st~0_17, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 1684#L202-1 [1074] L202-1-->L449: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_~tmp~3] 1685#L449 [1026] L449-->L449-1: Formula: (< 0 v_ULTIMATE.start_start_simulation_~tmp~3_4) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_4} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_4} AuxVars[] AssignedVars[] 1718#L449-1 [707] L449-1-->L190-2: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_1, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret6=|v_ULTIMATE.start_stop_simulation_#t~ret6_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret6, ULTIMATE.start_stop_simulation_#res] 1728#L190-2 [698] L190-2-->L202-2: Formula: (and (= v_~m_st~0_5 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_4 1)) InVars {~m_st~0=v_~m_st~0_5} OutVars{~m_st~0=v_~m_st~0_5, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 1682#L202-2 [1076] L202-2-->L404: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_stop_simulation_#t~ret6=|v_ULTIMATE.start_stop_simulation_#t~ret6_4|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret6] 1683#L404 [761] L404-->L411: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 1702#L411 [1083] L411-->L430-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|, ULTIMATE.start_start_simulation_#t~ret8=|v_ULTIMATE.start_start_simulation_#t~ret8_6|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_#t~ret8] 1671#L430-1 33.77/12.79 [2019-03-28 12:22:04,179 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 33.77/12.79 [2019-03-28 12:22:04,179 INFO L82 PathProgramCache]: Analyzing trace with hash -818079315, now seen corresponding path program 1 times 33.77/12.79 [2019-03-28 12:22:04,179 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 33.77/12.79 [2019-03-28 12:22:04,180 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 33.77/12.79 [2019-03-28 12:22:04,180 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:04,181 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:04,181 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:04,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 33.77/12.79 [2019-03-28 12:22:04,205 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 33.77/12.79 [2019-03-28 12:22:04,205 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 33.77/12.79 [2019-03-28 12:22:04,205 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 33.77/12.79 [2019-03-28 12:22:04,205 INFO L799 eck$LassoCheckResult]: stem already infeasible 33.77/12.79 [2019-03-28 12:22:04,206 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 33.77/12.79 [2019-03-28 12:22:04,206 INFO L82 PathProgramCache]: Analyzing trace with hash 378980406, now seen corresponding path program 1 times 33.77/12.79 [2019-03-28 12:22:04,206 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 33.77/12.79 [2019-03-28 12:22:04,206 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 33.77/12.79 [2019-03-28 12:22:04,207 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:04,207 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:04,207 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:04,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 33.77/12.79 [2019-03-28 12:22:04,228 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 33.77/12.79 [2019-03-28 12:22:04,228 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 33.77/12.79 [2019-03-28 12:22:04,228 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 33.77/12.79 [2019-03-28 12:22:04,229 INFO L811 eck$LassoCheckResult]: loop already infeasible 33.77/12.79 [2019-03-28 12:22:04,229 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 33.77/12.79 [2019-03-28 12:22:04,229 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 33.77/12.79 [2019-03-28 12:22:04,229 INFO L87 Difference]: Start difference. First operand 193 states and 405 transitions. cyclomatic complexity: 213 Second operand 3 states. 33.77/12.79 [2019-03-28 12:22:04,367 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 33.77/12.79 [2019-03-28 12:22:04,368 INFO L93 Difference]: Finished difference Result 201 states and 389 transitions. 33.77/12.79 [2019-03-28 12:22:04,368 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 33.77/12.79 [2019-03-28 12:22:04,368 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 201 states and 389 transitions. 33.77/12.79 [2019-03-28 12:22:04,370 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 178 33.77/12.79 [2019-03-28 12:22:04,372 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 201 states to 201 states and 389 transitions. 33.77/12.79 [2019-03-28 12:22:04,372 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 201 33.77/12.79 [2019-03-28 12:22:04,372 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 201 33.77/12.79 [2019-03-28 12:22:04,372 INFO L73 IsDeterministic]: Start isDeterministic. Operand 201 states and 389 transitions. 33.77/12.79 [2019-03-28 12:22:04,373 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 33.77/12.79 [2019-03-28 12:22:04,373 INFO L706 BuchiCegarLoop]: Abstraction has 201 states and 389 transitions. 33.77/12.79 [2019-03-28 12:22:04,373 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 201 states and 389 transitions. 33.77/12.79 [2019-03-28 12:22:04,378 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 201 to 193. 33.77/12.79 [2019-03-28 12:22:04,378 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 193 states. 33.77/12.79 [2019-03-28 12:22:04,379 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 193 states to 193 states and 377 transitions. 33.77/12.79 [2019-03-28 12:22:04,379 INFO L729 BuchiCegarLoop]: Abstraction has 193 states and 377 transitions. 33.77/12.79 [2019-03-28 12:22:04,379 INFO L609 BuchiCegarLoop]: Abstraction has 193 states and 377 transitions. 33.77/12.79 [2019-03-28 12:22:04,380 INFO L442 BuchiCegarLoop]: ======== Iteration 8============ 33.77/12.79 [2019-03-28 12:22:04,380 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 193 states and 377 transitions. 33.77/12.79 [2019-03-28 12:22:04,381 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 170 33.77/12.79 [2019-03-28 12:22:04,381 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 33.77/12.79 [2019-03-28 12:22:04,381 INFO L119 BuchiIsEmpty]: Starting construction of run 33.77/12.79 [2019-03-28 12:22:04,382 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 33.77/12.79 [2019-03-28 12:22:04,382 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 33.77/12.79 [2019-03-28 12:22:04,383 INFO L794 eck$LassoCheckResult]: Stem: 2142#ULTIMATE.startENTRY [1057] ULTIMATE.startENTRY-->L165: Formula: (and (= 0 v_~m_st~0_20) (= 2 v_~E_M~0_30) (= v_~t1_pc~0_18 0) (= 0 v_~t1_st~0_20) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 0 v_~token~0_8) (= v_~M_E~0_19 2) (= v_~local~0_6 0) (= v_~m_i~0_7 1) (= 2 v_~E_1~0_30) (= v_~m_pc~0_18 0) (= 1 v_~t1_i~0_7)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ~t1_st~0=v_~t1_st~0_20, ~t1_pc~0=v_~t1_pc~0_18, ~M_E~0=v_~M_E~0_19, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_#t~ret8=|v_ULTIMATE.start_start_simulation_#t~ret8_4|, ~token~0=v_~token~0_8, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~E_1~0=v_~E_1~0_30, ~E_M~0=v_~E_M~0_30, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~T1_E~0=v_~T1_E~0_18, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_20, ~m_pc~0=v_~m_pc~0_18, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ~t1_st~0, ~t1_pc~0, ~M_E~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_#t~ret8, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~E_1~0, ~E_M~0, ULTIMATE.start_main_#res, ~T1_E~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0, ULTIMATE.start_main_~__retres1~3] 2141#L165 [720] L165-->L172-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_3 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_3, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 2090#L172-1 [642] L172-1-->L177-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 2091#L177-1 [917] L177-1-->L261-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 2100#L261-1 [919] L261-1-->L266-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 2166#L266-1 [921] L266-1-->L271-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 2097#L271-1 [922] L271-1-->L276-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 2098#L276-1 [657] L276-1-->L126: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_3, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_4, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_1|, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_3|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_master_triggered_#res] 2102#L126 [755] L126-->L127: Formula: (= v_~m_pc~0_2 1) InVars {~m_pc~0=v_~m_pc~0_2} OutVars{~m_pc~0=v_~m_pc~0_2} AuxVars[] AssignedVars[] 2136#L127 [712] L127-->L137: Formula: (and (= v_~E_M~0_8 1) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_4 1)) InVars {~E_M~0=v_~E_M~0_8} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_4, ~E_M~0=v_~E_M~0_8} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 2137#L137 [1058] L137-->L321: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_16| v_ULTIMATE.start_activate_threads_~tmp~1_29) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_29 |v_ULTIMATE.start_is_master_triggered_#res_16|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_29, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_16|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 2063#L321 [611] L321-->L321-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_8) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8} AuxVars[] AssignedVars[] 2064#L321-2 [615] L321-2-->L145: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 2067#L145 [931] L145-->L145-2: Formula: (> v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 2132#L145-2 [783] L145-2-->L156: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 2167#L156 [1059] L156-->L329: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_29 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_29, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_16|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_transmit1_triggered_#res] 2068#L329 [618] L329-->L329-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_9) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} AuxVars[] AssignedVars[] 2069#L329-2 [937] L329-2-->L289-1: Formula: (> v_~M_E~0_10 1) InVars {~M_E~0=v_~M_E~0_10} OutVars{~M_E~0=v_~M_E~0_10} AuxVars[] AssignedVars[] 2076#L289-1 [939] L289-1-->L294-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 2143#L294-1 [941] L294-1-->L299-1: Formula: (> 1 v_~E_M~0_12) InVars {~E_M~0=v_~E_M~0_12} OutVars{~E_M~0=v_~E_M~0_12} AuxVars[] AssignedVars[] 2070#L299-1 [942] L299-1-->L430-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 2071#L430-1 33.77/12.79 [2019-03-28 12:22:04,384 INFO L796 eck$LassoCheckResult]: Loop: 2071#L430-1 [1060] L430-1-->L236: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 2109#L236 [1061] L236-->L190: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_22, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 2135#L190 [708] L190-->L202: Formula: (and (= v_~m_st~0_8 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11 1)) InVars {~m_st~0=v_~m_st~0_8} OutVars{~m_st~0=v_~m_st~0_8, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 2096#L202 [1062] L202-->L217: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 2103#L217 [1064] L217-->L261-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 2164#L261-2 [946] L261-2-->L261-4: Formula: (> v_~M_E~0_13 0) InVars {~M_E~0=v_~M_E~0_13} OutVars{~M_E~0=v_~M_E~0_13} AuxVars[] AssignedVars[] 2158#L261-4 [951] L261-4-->L266-3: Formula: (> v_~T1_E~0_13 0) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 2159#L266-3 [952] L266-3-->L271-3: Formula: (< 0 v_~E_M~0_21) InVars {~E_M~0=v_~E_M~0_21} OutVars{~E_M~0=v_~E_M~0_21} AuxVars[] AssignedVars[] 2093#L271-3 [956] L271-3-->L276-3: Formula: (< 0 v_~E_1~0_23) InVars {~E_1~0=v_~E_1~0_23} OutVars{~E_1~0=v_~E_1~0_23} AuxVars[] AssignedVars[] 2094#L276-3 [656] L276-3-->L126-9: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_19, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_17, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_20, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_10|, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_12|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_master_triggered_#res] 2101#L126-9 [763] L126-9-->L127-3: Formula: (= v_~m_pc~0_13 1) InVars {~m_pc~0=v_~m_pc~0_13} OutVars{~m_pc~0=v_~m_pc~0_13} AuxVars[] AssignedVars[] 2110#L127-3 [670] L127-3-->L137-3: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_20 1) (= 1 v_~E_M~0_22)) InVars {~E_M~0=v_~E_M~0_22} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_20, ~E_M~0=v_~E_M~0_22} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 2112#L137-3 [1070] L137-3-->L321-9: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_34 |v_ULTIMATE.start_is_master_triggered_#res_21|) (= |v_ULTIMATE.start_is_master_triggered_#res_21| v_ULTIMATE.start_activate_threads_~tmp~1_34)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_34} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_34, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_34, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_21|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_21|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 2148#L321-9 [789] L321-9-->L321-11: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_24) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_24} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_24} AuxVars[] AssignedVars[] 2170#L321-11 [796] L321-11-->L145-9: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 2154#L145-9 [990] L145-9-->L145-11: Formula: (< v_~t1_pc~0_16 1) InVars {~t1_pc~0=v_~t1_pc~0_16} OutVars{~t1_pc~0=v_~t1_pc~0_16} AuxVars[] AssignedVars[] 2123#L145-11 [745] L145-11-->L156-3: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_29 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_29} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 2149#L156-3 [1073] L156-3-->L329-9: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_34 |v_ULTIMATE.start_is_transmit1_triggered_#res_19|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_34 |v_ULTIMATE.start_is_transmit1_triggered_#res_19|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_34} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_34, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_34, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_21|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_19|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_transmit1_triggered_#res] 2065#L329-9 [614] L329-9-->L329-11: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_25 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_25} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_25} AuxVars[] AssignedVars[] 2066#L329-11 [1009] L329-11-->L289-3: Formula: (> v_~M_E~0_16 1) InVars {~M_E~0=v_~M_E~0_16} OutVars{~M_E~0=v_~M_E~0_16} AuxVars[] AssignedVars[] 2133#L289-3 [1013] L289-3-->L294-3: Formula: (> v_~T1_E~0_16 1) InVars {~T1_E~0=v_~T1_E~0_16} OutVars{~T1_E~0=v_~T1_E~0_16} AuxVars[] AssignedVars[] 2134#L294-3 [1014] L294-3-->L299-3: Formula: (> 1 v_~E_M~0_26) InVars {~E_M~0=v_~E_M~0_26} OutVars{~E_M~0=v_~E_M~0_26} AuxVars[] AssignedVars[] 2163#L299-3 [1018] L299-3-->L304-3: Formula: (< 1 v_~E_1~0_28) InVars {~E_1~0=v_~E_1~0_28} OutVars{~E_1~0=v_~E_1~0_28} AuxVars[] AssignedVars[] 2082#L304-3 [637] L304-3-->L190-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 2083#L190-1 [705] L190-1-->L202-1: Formula: (and (= 0 v_~m_st~0_17) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18 1)) InVars {~m_st~0=v_~m_st~0_17} OutVars{~m_st~0=v_~m_st~0_17, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 2087#L202-1 [1074] L202-1-->L449: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_~tmp~3] 2088#L449 [1026] L449-->L449-1: Formula: (< 0 v_ULTIMATE.start_start_simulation_~tmp~3_4) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_4} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_4} AuxVars[] AssignedVars[] 2121#L449-1 [707] L449-1-->L190-2: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_1, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret6=|v_ULTIMATE.start_stop_simulation_#t~ret6_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret6, ULTIMATE.start_stop_simulation_#res] 2129#L190-2 [698] L190-2-->L202-2: Formula: (and (= v_~m_st~0_5 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_4 1)) InVars {~m_st~0=v_~m_st~0_5} OutVars{~m_st~0=v_~m_st~0_5, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 2085#L202-2 [1076] L202-2-->L404: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_stop_simulation_#t~ret6=|v_ULTIMATE.start_stop_simulation_#t~ret6_4|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret6] 2086#L404 [761] L404-->L411: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 2105#L411 [1083] L411-->L430-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|, ULTIMATE.start_start_simulation_#t~ret8=|v_ULTIMATE.start_start_simulation_#t~ret8_6|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_#t~ret8] 2071#L430-1 33.77/12.79 [2019-03-28 12:22:04,384 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 33.77/12.79 [2019-03-28 12:22:04,384 INFO L82 PathProgramCache]: Analyzing trace with hash 1969336171, now seen corresponding path program 1 times 33.77/12.79 [2019-03-28 12:22:04,384 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 33.77/12.79 [2019-03-28 12:22:04,384 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 33.77/12.79 [2019-03-28 12:22:04,385 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:04,385 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:04,385 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:04,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 33.77/12.79 [2019-03-28 12:22:04,405 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 33.77/12.79 [2019-03-28 12:22:04,406 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 33.77/12.79 [2019-03-28 12:22:04,406 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 33.77/12.79 [2019-03-28 12:22:04,406 INFO L799 eck$LassoCheckResult]: stem already infeasible 33.77/12.79 [2019-03-28 12:22:04,406 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 33.77/12.79 [2019-03-28 12:22:04,406 INFO L82 PathProgramCache]: Analyzing trace with hash 657897428, now seen corresponding path program 1 times 33.77/12.79 [2019-03-28 12:22:04,407 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 33.77/12.79 [2019-03-28 12:22:04,407 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 33.77/12.79 [2019-03-28 12:22:04,408 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:04,408 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:04,408 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:04,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 33.77/12.79 [2019-03-28 12:22:04,428 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 33.77/12.79 [2019-03-28 12:22:04,428 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 33.77/12.79 [2019-03-28 12:22:04,428 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 33.77/12.79 [2019-03-28 12:22:04,429 INFO L811 eck$LassoCheckResult]: loop already infeasible 33.77/12.79 [2019-03-28 12:22:04,429 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 33.77/12.79 [2019-03-28 12:22:04,429 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 33.77/12.79 [2019-03-28 12:22:04,429 INFO L87 Difference]: Start difference. First operand 193 states and 377 transitions. cyclomatic complexity: 185 Second operand 3 states. 33.77/12.79 [2019-03-28 12:22:04,632 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 33.77/12.79 [2019-03-28 12:22:04,632 INFO L93 Difference]: Finished difference Result 345 states and 651 transitions. 33.77/12.79 [2019-03-28 12:22:04,633 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 33.77/12.79 [2019-03-28 12:22:04,633 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 345 states and 651 transitions. 33.77/12.79 [2019-03-28 12:22:04,636 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 323 33.77/12.79 [2019-03-28 12:22:04,638 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 345 states to 345 states and 651 transitions. 33.77/12.79 [2019-03-28 12:22:04,638 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 345 33.77/12.79 [2019-03-28 12:22:04,639 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 345 33.77/12.79 [2019-03-28 12:22:04,639 INFO L73 IsDeterministic]: Start isDeterministic. Operand 345 states and 651 transitions. 33.77/12.79 [2019-03-28 12:22:04,640 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 33.77/12.79 [2019-03-28 12:22:04,640 INFO L706 BuchiCegarLoop]: Abstraction has 345 states and 651 transitions. 33.77/12.79 [2019-03-28 12:22:04,640 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 345 states and 651 transitions. 33.77/12.79 [2019-03-28 12:22:04,646 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 345 to 325. 33.77/12.79 [2019-03-28 12:22:04,647 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 325 states. 33.77/12.79 [2019-03-28 12:22:04,648 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 325 states to 325 states and 615 transitions. 33.77/12.79 [2019-03-28 12:22:04,648 INFO L729 BuchiCegarLoop]: Abstraction has 325 states and 615 transitions. 33.77/12.79 [2019-03-28 12:22:04,648 INFO L609 BuchiCegarLoop]: Abstraction has 325 states and 615 transitions. 33.77/12.79 [2019-03-28 12:22:04,649 INFO L442 BuchiCegarLoop]: ======== Iteration 9============ 33.77/12.79 [2019-03-28 12:22:04,649 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 325 states and 615 transitions. 33.77/12.79 [2019-03-28 12:22:04,650 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 303 33.77/12.79 [2019-03-28 12:22:04,651 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 33.77/12.79 [2019-03-28 12:22:04,651 INFO L119 BuchiIsEmpty]: Starting construction of run 33.77/12.79 [2019-03-28 12:22:04,652 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 33.77/12.79 [2019-03-28 12:22:04,652 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 33.77/12.79 [2019-03-28 12:22:04,652 INFO L794 eck$LassoCheckResult]: Stem: 2692#ULTIMATE.startENTRY [1057] ULTIMATE.startENTRY-->L165: Formula: (and (= 0 v_~m_st~0_20) (= 2 v_~E_M~0_30) (= v_~t1_pc~0_18 0) (= 0 v_~t1_st~0_20) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 0 v_~token~0_8) (= v_~M_E~0_19 2) (= v_~local~0_6 0) (= v_~m_i~0_7 1) (= 2 v_~E_1~0_30) (= v_~m_pc~0_18 0) (= 1 v_~t1_i~0_7)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ~t1_st~0=v_~t1_st~0_20, ~t1_pc~0=v_~t1_pc~0_18, ~M_E~0=v_~M_E~0_19, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_#t~ret8=|v_ULTIMATE.start_start_simulation_#t~ret8_4|, ~token~0=v_~token~0_8, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~E_1~0=v_~E_1~0_30, ~E_M~0=v_~E_M~0_30, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~T1_E~0=v_~T1_E~0_18, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_20, ~m_pc~0=v_~m_pc~0_18, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ~t1_st~0, ~t1_pc~0, ~M_E~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_#t~ret8, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~E_1~0, ~E_M~0, ULTIMATE.start_main_#res, ~T1_E~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0, ULTIMATE.start_main_~__retres1~3] 2687#L165 [720] L165-->L172-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_3 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_3, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 2635#L172-1 [642] L172-1-->L177-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 2636#L177-1 [917] L177-1-->L261-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 2646#L261-1 [919] L261-1-->L266-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 2725#L266-1 [921] L266-1-->L271-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 2642#L271-1 [922] L271-1-->L276-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 2643#L276-1 [657] L276-1-->L126: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_3, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_4, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_1|, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_3|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_master_triggered_#res] 2648#L126 [924] L126-->L126-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 2701#L126-2 [746] L126-2-->L137: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 2702#L137 [1058] L137-->L321: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_16| v_ULTIMATE.start_activate_threads_~tmp~1_29) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_29 |v_ULTIMATE.start_is_master_triggered_#res_16|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_29, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_16|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 2609#L321 [611] L321-->L321-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_8) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8} AuxVars[] AssignedVars[] 2610#L321-2 [615] L321-2-->L145: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 2613#L145 [931] L145-->L145-2: Formula: (> v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 2680#L145-2 [783] L145-2-->L156: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 2726#L156 [1059] L156-->L329: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_29 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_29, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_16|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_transmit1_triggered_#res] 2614#L329 [618] L329-->L329-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_9) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} AuxVars[] AssignedVars[] 2615#L329-2 [937] L329-2-->L289-1: Formula: (> v_~M_E~0_10 1) InVars {~M_E~0=v_~M_E~0_10} OutVars{~M_E~0=v_~M_E~0_10} AuxVars[] AssignedVars[] 2622#L289-1 [939] L289-1-->L294-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 2693#L294-1 [941] L294-1-->L299-1: Formula: (> 1 v_~E_M~0_12) InVars {~E_M~0=v_~E_M~0_12} OutVars{~E_M~0=v_~E_M~0_12} AuxVars[] AssignedVars[] 2616#L299-1 [942] L299-1-->L430-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 2617#L430-1 33.77/12.79 [2019-03-28 12:22:04,653 INFO L796 eck$LassoCheckResult]: Loop: 2617#L430-1 [1060] L430-1-->L236: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 2655#L236 [1061] L236-->L190: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_22, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 2684#L190 [708] L190-->L202: Formula: (and (= v_~m_st~0_8 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11 1)) InVars {~m_st~0=v_~m_st~0_8} OutVars{~m_st~0=v_~m_st~0_8, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 2641#L202 [1062] L202-->L217: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 2649#L217 [1064] L217-->L261-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 2721#L261-2 [946] L261-2-->L261-4: Formula: (> v_~M_E~0_13 0) InVars {~M_E~0=v_~M_E~0_13} OutVars{~M_E~0=v_~M_E~0_13} AuxVars[] AssignedVars[] 2722#L261-4 [951] L261-4-->L266-3: Formula: (> v_~T1_E~0_13 0) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 2921#L266-3 [952] L266-3-->L271-3: Formula: (< 0 v_~E_M~0_21) InVars {~E_M~0=v_~E_M~0_21} OutVars{~E_M~0=v_~E_M~0_21} AuxVars[] AssignedVars[] 2638#L271-3 [956] L271-3-->L276-3: Formula: (< 0 v_~E_1~0_23) InVars {~E_1~0=v_~E_1~0_23} OutVars{~E_1~0=v_~E_1~0_23} AuxVars[] AssignedVars[] 2639#L276-3 [656] L276-3-->L126-9: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_19, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_17, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_20, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_10|, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_12|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_master_triggered_#res] 2647#L126-9 [964] L126-9-->L126-11: Formula: (< v_~m_pc~0_14 1) InVars {~m_pc~0=v_~m_pc~0_14} OutVars{~m_pc~0=v_~m_pc~0_14} AuxVars[] AssignedVars[] 2690#L126-11 [726] L126-11-->L137-3: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_21 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_21} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 2691#L137-3 [1070] L137-3-->L321-9: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_34 |v_ULTIMATE.start_is_master_triggered_#res_21|) (= |v_ULTIMATE.start_is_master_triggered_#res_21| v_ULTIMATE.start_activate_threads_~tmp~1_34)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_34} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_34, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_34, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_21|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_21|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 2699#L321-9 [789] L321-9-->L321-11: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_24) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_24} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_24} AuxVars[] AssignedVars[] 2729#L321-11 [796] L321-11-->L145-9: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 2708#L145-9 [990] L145-9-->L145-11: Formula: (< v_~t1_pc~0_16 1) InVars {~t1_pc~0=v_~t1_pc~0_16} OutVars{~t1_pc~0=v_~t1_pc~0_16} AuxVars[] AssignedVars[] 2671#L145-11 [745] L145-11-->L156-3: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_29 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_29} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 2700#L156-3 [1073] L156-3-->L329-9: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_34 |v_ULTIMATE.start_is_transmit1_triggered_#res_19|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_34 |v_ULTIMATE.start_is_transmit1_triggered_#res_19|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_34} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_34, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_34, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_21|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_19|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_transmit1_triggered_#res] 2905#L329-9 [614] L329-9-->L329-11: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_25 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_25} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_25} AuxVars[] AssignedVars[] 2901#L329-11 [1009] L329-11-->L289-3: Formula: (> v_~M_E~0_16 1) InVars {~M_E~0=v_~M_E~0_16} OutVars{~M_E~0=v_~M_E~0_16} AuxVars[] AssignedVars[] 2899#L289-3 [1013] L289-3-->L294-3: Formula: (> v_~T1_E~0_16 1) InVars {~T1_E~0=v_~T1_E~0_16} OutVars{~T1_E~0=v_~T1_E~0_16} AuxVars[] AssignedVars[] 2898#L294-3 [1014] L294-3-->L299-3: Formula: (> 1 v_~E_M~0_26) InVars {~E_M~0=v_~E_M~0_26} OutVars{~E_M~0=v_~E_M~0_26} AuxVars[] AssignedVars[] 2895#L299-3 [1018] L299-3-->L304-3: Formula: (< 1 v_~E_1~0_28) InVars {~E_1~0=v_~E_1~0_28} OutVars{~E_1~0=v_~E_1~0_28} AuxVars[] AssignedVars[] 2887#L304-3 [637] L304-3-->L190-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 2886#L190-1 [705] L190-1-->L202-1: Formula: (and (= 0 v_~m_st~0_17) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18 1)) InVars {~m_st~0=v_~m_st~0_17} OutVars{~m_st~0=v_~m_st~0_17, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 2884#L202-1 [1074] L202-1-->L449: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_~tmp~3] 2882#L449 [1026] L449-->L449-1: Formula: (< 0 v_ULTIMATE.start_start_simulation_~tmp~3_4) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_4} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_4} AuxVars[] AssignedVars[] 2681#L449-1 [707] L449-1-->L190-2: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_1, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret6=|v_ULTIMATE.start_stop_simulation_#t~ret6_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret6, ULTIMATE.start_stop_simulation_#res] 2677#L190-2 [698] L190-2-->L202-2: Formula: (and (= v_~m_st~0_5 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_4 1)) InVars {~m_st~0=v_~m_st~0_5} OutVars{~m_st~0=v_~m_st~0_5, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 2634#L202-2 [1076] L202-2-->L404: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_stop_simulation_#t~ret6=|v_ULTIMATE.start_stop_simulation_#t~ret6_4|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret6] 2710#L404 [761] L404-->L411: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 2651#L411 [1083] L411-->L430-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|, ULTIMATE.start_start_simulation_#t~ret8=|v_ULTIMATE.start_start_simulation_#t~ret8_6|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_#t~ret8] 2617#L430-1 33.77/12.79 [2019-03-28 12:22:04,653 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 33.77/12.79 [2019-03-28 12:22:04,654 INFO L82 PathProgramCache]: Analyzing trace with hash -277286606, now seen corresponding path program 1 times 33.77/12.79 [2019-03-28 12:22:04,654 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 33.77/12.79 [2019-03-28 12:22:04,654 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 33.77/12.79 [2019-03-28 12:22:04,655 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:04,655 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:04,655 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:04,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 33.77/12.79 [2019-03-28 12:22:04,674 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 33.77/12.79 [2019-03-28 12:22:04,674 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 33.77/12.79 [2019-03-28 12:22:04,674 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 33.77/12.79 [2019-03-28 12:22:04,675 INFO L799 eck$LassoCheckResult]: stem already infeasible 33.77/12.79 [2019-03-28 12:22:04,675 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 33.77/12.79 [2019-03-28 12:22:04,675 INFO L82 PathProgramCache]: Analyzing trace with hash -2018774301, now seen corresponding path program 1 times 33.77/12.79 [2019-03-28 12:22:04,675 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 33.77/12.79 [2019-03-28 12:22:04,675 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 33.77/12.79 [2019-03-28 12:22:04,676 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:04,676 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:04,677 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:04,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 33.77/12.79 [2019-03-28 12:22:04,715 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 33.77/12.79 [2019-03-28 12:22:04,715 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 33.77/12.79 [2019-03-28 12:22:04,715 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 33.77/12.79 [2019-03-28 12:22:04,715 INFO L811 eck$LassoCheckResult]: loop already infeasible 33.77/12.79 [2019-03-28 12:22:04,716 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 33.77/12.79 [2019-03-28 12:22:04,716 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 33.77/12.79 [2019-03-28 12:22:04,716 INFO L87 Difference]: Start difference. First operand 325 states and 615 transitions. cyclomatic complexity: 291 Second operand 3 states. 33.77/12.79 [2019-03-28 12:22:04,926 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 33.77/12.79 [2019-03-28 12:22:04,926 INFO L93 Difference]: Finished difference Result 589 states and 1101 transitions. 33.77/12.79 [2019-03-28 12:22:04,945 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 33.77/12.79 [2019-03-28 12:22:04,946 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 589 states and 1101 transitions. 33.77/12.79 [2019-03-28 12:22:04,949 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 568 33.77/12.79 [2019-03-28 12:22:04,953 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 589 states to 589 states and 1101 transitions. 33.77/12.79 [2019-03-28 12:22:04,953 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 589 33.77/12.79 [2019-03-28 12:22:04,954 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 589 33.77/12.79 [2019-03-28 12:22:04,954 INFO L73 IsDeterministic]: Start isDeterministic. Operand 589 states and 1101 transitions. 33.77/12.79 [2019-03-28 12:22:04,955 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 33.77/12.79 [2019-03-28 12:22:04,955 INFO L706 BuchiCegarLoop]: Abstraction has 589 states and 1101 transitions. 33.77/12.79 [2019-03-28 12:22:04,956 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 589 states and 1101 transitions. 33.77/12.79 [2019-03-28 12:22:04,967 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 589 to 569. 33.77/12.79 [2019-03-28 12:22:04,968 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 569 states. 33.77/12.79 [2019-03-28 12:22:04,970 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 569 states to 569 states and 1073 transitions. 33.77/12.79 [2019-03-28 12:22:04,970 INFO L729 BuchiCegarLoop]: Abstraction has 569 states and 1073 transitions. 33.77/12.79 [2019-03-28 12:22:04,970 INFO L609 BuchiCegarLoop]: Abstraction has 569 states and 1073 transitions. 33.77/12.79 [2019-03-28 12:22:04,970 INFO L442 BuchiCegarLoop]: ======== Iteration 10============ 33.77/12.79 [2019-03-28 12:22:04,970 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 569 states and 1073 transitions. 33.77/12.79 [2019-03-28 12:22:04,973 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 548 33.77/12.79 [2019-03-28 12:22:04,973 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 33.77/12.79 [2019-03-28 12:22:04,974 INFO L119 BuchiIsEmpty]: Starting construction of run 33.77/12.79 [2019-03-28 12:22:04,975 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 33.77/12.79 [2019-03-28 12:22:04,975 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 33.77/12.79 [2019-03-28 12:22:04,976 INFO L794 eck$LassoCheckResult]: Stem: 3614#ULTIMATE.startENTRY [1057] ULTIMATE.startENTRY-->L165: Formula: (and (= 0 v_~m_st~0_20) (= 2 v_~E_M~0_30) (= v_~t1_pc~0_18 0) (= 0 v_~t1_st~0_20) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 0 v_~token~0_8) (= v_~M_E~0_19 2) (= v_~local~0_6 0) (= v_~m_i~0_7 1) (= 2 v_~E_1~0_30) (= v_~m_pc~0_18 0) (= 1 v_~t1_i~0_7)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ~t1_st~0=v_~t1_st~0_20, ~t1_pc~0=v_~t1_pc~0_18, ~M_E~0=v_~M_E~0_19, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_#t~ret8=|v_ULTIMATE.start_start_simulation_#t~ret8_4|, ~token~0=v_~token~0_8, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~E_1~0=v_~E_1~0_30, ~E_M~0=v_~E_M~0_30, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~T1_E~0=v_~T1_E~0_18, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_20, ~m_pc~0=v_~m_pc~0_18, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ~t1_st~0, ~t1_pc~0, ~M_E~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_#t~ret8, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~E_1~0, ~E_M~0, ULTIMATE.start_main_#res, ~T1_E~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0, ULTIMATE.start_main_~__retres1~3] 3610#L165 [720] L165-->L172-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_3 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_3, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 3557#L172-1 [642] L172-1-->L177-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 3558#L177-1 [917] L177-1-->L261-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 3568#L261-1 [919] L261-1-->L266-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 3643#L266-1 [921] L266-1-->L271-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 3564#L271-1 [922] L271-1-->L276-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 3565#L276-1 [657] L276-1-->L126: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_3, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_4, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_1|, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_3|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_master_triggered_#res] 3570#L126 [924] L126-->L126-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 3625#L126-2 [746] L126-2-->L137: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 3626#L137 [1058] L137-->L321: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_16| v_ULTIMATE.start_activate_threads_~tmp~1_29) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_29 |v_ULTIMATE.start_is_master_triggered_#res_16|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_29, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_16|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 3532#L321 [611] L321-->L321-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_8) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8} AuxVars[] AssignedVars[] 3533#L321-2 [615] L321-2-->L145: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 3536#L145 [930] L145-->L145-2: Formula: (< v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 3644#L145-2 [783] L145-2-->L156: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 3645#L156 [1059] L156-->L329: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_29 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_29, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_16|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_transmit1_triggered_#res] 3539#L329 [618] L329-->L329-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_9) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} AuxVars[] AssignedVars[] 3540#L329-2 [937] L329-2-->L289-1: Formula: (> v_~M_E~0_10 1) InVars {~M_E~0=v_~M_E~0_10} OutVars{~M_E~0=v_~M_E~0_10} AuxVars[] AssignedVars[] 3545#L289-1 [939] L289-1-->L294-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 3615#L294-1 [941] L294-1-->L299-1: Formula: (> 1 v_~E_M~0_12) InVars {~E_M~0=v_~E_M~0_12} OutVars{~E_M~0=v_~E_M~0_12} AuxVars[] AssignedVars[] 3541#L299-1 [942] L299-1-->L430-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 3542#L430-1 33.77/12.79 [2019-03-28 12:22:04,976 INFO L796 eck$LassoCheckResult]: Loop: 3542#L430-1 [1060] L430-1-->L236: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 4032#L236 [1061] L236-->L190: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_22, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 4030#L190 [708] L190-->L202: Formula: (and (= v_~m_st~0_8 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11 1)) InVars {~m_st~0=v_~m_st~0_8} OutVars{~m_st~0=v_~m_st~0_8, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 3571#L202 [1062] L202-->L217: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 3572#L217 [1064] L217-->L261-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 3640#L261-2 [946] L261-2-->L261-4: Formula: (> v_~M_E~0_13 0) InVars {~M_E~0=v_~M_E~0_13} OutVars{~M_E~0=v_~M_E~0_13} AuxVars[] AssignedVars[] 3633#L261-4 [951] L261-4-->L266-3: Formula: (> v_~T1_E~0_13 0) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 3634#L266-3 [952] L266-3-->L271-3: Formula: (< 0 v_~E_M~0_21) InVars {~E_M~0=v_~E_M~0_21} OutVars{~E_M~0=v_~E_M~0_21} AuxVars[] AssignedVars[] 3560#L271-3 [956] L271-3-->L276-3: Formula: (< 0 v_~E_1~0_23) InVars {~E_1~0=v_~E_1~0_23} OutVars{~E_1~0=v_~E_1~0_23} AuxVars[] AssignedVars[] 3561#L276-3 [656] L276-3-->L126-9: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_19, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_17, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_20, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_10|, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_12|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_master_triggered_#res] 3569#L126-9 [964] L126-9-->L126-11: Formula: (< v_~m_pc~0_14 1) InVars {~m_pc~0=v_~m_pc~0_14} OutVars{~m_pc~0=v_~m_pc~0_14} AuxVars[] AssignedVars[] 3612#L126-11 [726] L126-11-->L137-3: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_21 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_21} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 3613#L137-3 [1070] L137-3-->L321-9: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_34 |v_ULTIMATE.start_is_master_triggered_#res_21|) (= |v_ULTIMATE.start_is_master_triggered_#res_21| v_ULTIMATE.start_activate_threads_~tmp~1_34)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_34} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_34, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_34, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_21|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_21|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 3622#L321-9 [789] L321-9-->L321-11: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_24) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_24} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_24} AuxVars[] AssignedVars[] 3650#L321-11 [796] L321-11-->L145-9: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 3629#L145-9 [990] L145-9-->L145-11: Formula: (< v_~t1_pc~0_16 1) InVars {~t1_pc~0=v_~t1_pc~0_16} OutVars{~t1_pc~0=v_~t1_pc~0_16} AuxVars[] AssignedVars[] 3623#L145-11 [745] L145-11-->L156-3: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_29 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_29} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 3624#L156-3 [1073] L156-3-->L329-9: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_34 |v_ULTIMATE.start_is_transmit1_triggered_#res_19|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_34 |v_ULTIMATE.start_is_transmit1_triggered_#res_19|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_34} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_34, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_34, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_21|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_19|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_transmit1_triggered_#res] 3534#L329-9 [614] L329-9-->L329-11: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_25 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_25} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_25} AuxVars[] AssignedVars[] 3535#L329-11 [1009] L329-11-->L289-3: Formula: (> v_~M_E~0_16 1) InVars {~M_E~0=v_~M_E~0_16} OutVars{~M_E~0=v_~M_E~0_16} AuxVars[] AssignedVars[] 3653#L289-3 [1013] L289-3-->L294-3: Formula: (> v_~T1_E~0_16 1) InVars {~T1_E~0=v_~T1_E~0_16} OutVars{~T1_E~0=v_~T1_E~0_16} AuxVars[] AssignedVars[] 4050#L294-3 [1014] L294-3-->L299-3: Formula: (> 1 v_~E_M~0_26) InVars {~E_M~0=v_~E_M~0_26} OutVars{~E_M~0=v_~E_M~0_26} AuxVars[] AssignedVars[] 4049#L299-3 [1018] L299-3-->L304-3: Formula: (< 1 v_~E_1~0_28) InVars {~E_1~0=v_~E_1~0_28} OutVars{~E_1~0=v_~E_1~0_28} AuxVars[] AssignedVars[] 4048#L304-3 [637] L304-3-->L190-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 4047#L190-1 [705] L190-1-->L202-1: Formula: (and (= 0 v_~m_st~0_17) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18 1)) InVars {~m_st~0=v_~m_st~0_17} OutVars{~m_st~0=v_~m_st~0_17, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 4045#L202-1 [1074] L202-1-->L449: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_~tmp~3] 4042#L449 [1026] L449-->L449-1: Formula: (< 0 v_ULTIMATE.start_start_simulation_~tmp~3_4) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_4} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_4} AuxVars[] AssignedVars[] 4041#L449-1 [707] L449-1-->L190-2: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_1, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret6=|v_ULTIMATE.start_stop_simulation_#t~ret6_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret6, ULTIMATE.start_stop_simulation_#res] 4040#L190-2 [698] L190-2-->L202-2: Formula: (and (= v_~m_st~0_5 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_4 1)) InVars {~m_st~0=v_~m_st~0_5} OutVars{~m_st~0=v_~m_st~0_5, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 4037#L202-2 [1076] L202-2-->L404: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_stop_simulation_#t~ret6=|v_ULTIMATE.start_stop_simulation_#t~ret6_4|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret6] 4036#L404 [761] L404-->L411: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 4035#L411 [1083] L411-->L430-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|, ULTIMATE.start_start_simulation_#t~ret8=|v_ULTIMATE.start_start_simulation_#t~ret8_6|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_#t~ret8] 3542#L430-1 33.77/12.79 [2019-03-28 12:22:04,977 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 33.77/12.79 [2019-03-28 12:22:04,977 INFO L82 PathProgramCache]: Analyzing trace with hash -2020096941, now seen corresponding path program 1 times 33.77/12.79 [2019-03-28 12:22:04,977 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 33.77/12.79 [2019-03-28 12:22:04,977 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 33.77/12.79 [2019-03-28 12:22:04,978 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:04,978 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:04,978 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:04,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 33.77/12.79 [2019-03-28 12:22:05,008 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 33.77/12.79 [2019-03-28 12:22:05,008 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 33.77/12.79 [2019-03-28 12:22:05,008 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 33.77/12.79 [2019-03-28 12:22:05,009 INFO L799 eck$LassoCheckResult]: stem already infeasible 33.77/12.79 [2019-03-28 12:22:05,009 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 33.77/12.79 [2019-03-28 12:22:05,009 INFO L82 PathProgramCache]: Analyzing trace with hash -2018774301, now seen corresponding path program 2 times 33.77/12.79 [2019-03-28 12:22:05,009 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 33.77/12.79 [2019-03-28 12:22:05,009 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 33.77/12.79 [2019-03-28 12:22:05,010 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:05,010 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:05,010 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:05,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 33.77/12.79 [2019-03-28 12:22:05,033 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 33.77/12.79 [2019-03-28 12:22:05,034 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 33.77/12.79 [2019-03-28 12:22:05,034 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 33.77/12.79 [2019-03-28 12:22:05,034 INFO L811 eck$LassoCheckResult]: loop already infeasible 33.77/12.79 [2019-03-28 12:22:05,035 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. 33.77/12.79 [2019-03-28 12:22:05,035 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 33.77/12.79 [2019-03-28 12:22:05,035 INFO L87 Difference]: Start difference. First operand 569 states and 1073 transitions. cyclomatic complexity: 505 Second operand 4 states. 33.77/12.79 [2019-03-28 12:22:05,216 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 33.77/12.79 [2019-03-28 12:22:05,216 INFO L93 Difference]: Finished difference Result 589 states and 1031 transitions. 33.77/12.79 [2019-03-28 12:22:05,216 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. 33.77/12.79 [2019-03-28 12:22:05,217 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 589 states and 1031 transitions. 33.77/12.79 [2019-03-28 12:22:05,220 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 568 33.77/12.79 [2019-03-28 12:22:05,224 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 589 states to 589 states and 1031 transitions. 33.77/12.79 [2019-03-28 12:22:05,224 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 589 33.77/12.79 [2019-03-28 12:22:05,224 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 589 33.77/12.79 [2019-03-28 12:22:05,224 INFO L73 IsDeterministic]: Start isDeterministic. Operand 589 states and 1031 transitions. 33.77/12.79 [2019-03-28 12:22:05,226 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 33.77/12.79 [2019-03-28 12:22:05,226 INFO L706 BuchiCegarLoop]: Abstraction has 589 states and 1031 transitions. 33.77/12.79 [2019-03-28 12:22:05,226 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 589 states and 1031 transitions. 33.77/12.79 [2019-03-28 12:22:05,235 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 589 to 569. 33.77/12.79 [2019-03-28 12:22:05,236 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 569 states. 33.77/12.79 [2019-03-28 12:22:05,237 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 569 states to 569 states and 999 transitions. 33.77/12.79 [2019-03-28 12:22:05,238 INFO L729 BuchiCegarLoop]: Abstraction has 569 states and 999 transitions. 33.77/12.79 [2019-03-28 12:22:05,238 INFO L609 BuchiCegarLoop]: Abstraction has 569 states and 999 transitions. 33.77/12.79 [2019-03-28 12:22:05,238 INFO L442 BuchiCegarLoop]: ======== Iteration 11============ 33.77/12.79 [2019-03-28 12:22:05,238 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 569 states and 999 transitions. 33.77/12.79 [2019-03-28 12:22:05,240 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 548 33.77/12.79 [2019-03-28 12:22:05,241 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 33.77/12.79 [2019-03-28 12:22:05,241 INFO L119 BuchiIsEmpty]: Starting construction of run 33.77/12.79 [2019-03-28 12:22:05,242 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 33.77/12.79 [2019-03-28 12:22:05,242 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 33.77/12.79 [2019-03-28 12:22:05,242 INFO L794 eck$LassoCheckResult]: Stem: 4776#ULTIMATE.startENTRY [1057] ULTIMATE.startENTRY-->L165: Formula: (and (= 0 v_~m_st~0_20) (= 2 v_~E_M~0_30) (= v_~t1_pc~0_18 0) (= 0 v_~t1_st~0_20) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 0 v_~token~0_8) (= v_~M_E~0_19 2) (= v_~local~0_6 0) (= v_~m_i~0_7 1) (= 2 v_~E_1~0_30) (= v_~m_pc~0_18 0) (= 1 v_~t1_i~0_7)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ~t1_st~0=v_~t1_st~0_20, ~t1_pc~0=v_~t1_pc~0_18, ~M_E~0=v_~M_E~0_19, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_#t~ret8=|v_ULTIMATE.start_start_simulation_#t~ret8_4|, ~token~0=v_~token~0_8, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~E_1~0=v_~E_1~0_30, ~E_M~0=v_~E_M~0_30, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~T1_E~0=v_~T1_E~0_18, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_20, ~m_pc~0=v_~m_pc~0_18, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ~t1_st~0, ~t1_pc~0, ~M_E~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_#t~ret8, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~E_1~0, ~E_M~0, ULTIMATE.start_main_#res, ~T1_E~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0, ULTIMATE.start_main_~__retres1~3] 4772#L165 [720] L165-->L172-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_3 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_3, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 4725#L172-1 [642] L172-1-->L177-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 4726#L177-1 [917] L177-1-->L261-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 4735#L261-1 [919] L261-1-->L266-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 4810#L266-1 [921] L266-1-->L271-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 4732#L271-1 [922] L271-1-->L276-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 4733#L276-1 [657] L276-1-->L126: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_3, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_4, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_1|, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_3|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_master_triggered_#res] 4737#L126 [924] L126-->L126-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 4785#L126-2 [746] L126-2-->L137: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 4786#L137 [1058] L137-->L321: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_16| v_ULTIMATE.start_activate_threads_~tmp~1_29) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_29 |v_ULTIMATE.start_is_master_triggered_#res_16|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_29, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_16|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 4697#L321 [611] L321-->L321-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_8) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8} AuxVars[] AssignedVars[] 4698#L321-2 [615] L321-2-->L145: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 4703#L145 [930] L145-->L145-2: Formula: (< v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 4811#L145-2 [783] L145-2-->L156: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 4812#L156 [1059] L156-->L329: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_29 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_29, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_16|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_transmit1_triggered_#res] 4704#L329 [618] L329-->L329-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_9) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} AuxVars[] AssignedVars[] 4705#L329-2 [937] L329-2-->L289-1: Formula: (> v_~M_E~0_10 1) InVars {~M_E~0=v_~M_E~0_10} OutVars{~M_E~0=v_~M_E~0_10} AuxVars[] AssignedVars[] 4712#L289-1 [939] L289-1-->L294-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 4777#L294-1 [940] L294-1-->L299-1: Formula: (< 1 v_~E_M~0_12) InVars {~E_M~0=v_~E_M~0_12} OutVars{~E_M~0=v_~E_M~0_12} AuxVars[] AssignedVars[] 4706#L299-1 [942] L299-1-->L430-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 4707#L430-1 33.77/12.79 [2019-03-28 12:22:05,243 INFO L796 eck$LassoCheckResult]: Loop: 4707#L430-1 [1060] L430-1-->L236: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 4743#L236 [1061] L236-->L190: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_22, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 4767#L190 [708] L190-->L202: Formula: (and (= v_~m_st~0_8 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11 1)) InVars {~m_st~0=v_~m_st~0_8} OutVars{~m_st~0=v_~m_st~0_8, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 4731#L202 [1062] L202-->L217: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 4738#L217 [1064] L217-->L261-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 4807#L261-2 [946] L261-2-->L261-4: Formula: (> v_~M_E~0_13 0) InVars {~M_E~0=v_~M_E~0_13} OutVars{~M_E~0=v_~M_E~0_13} AuxVars[] AssignedVars[] 5239#L261-4 [951] L261-4-->L266-3: Formula: (> v_~T1_E~0_13 0) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 5238#L266-3 [952] L266-3-->L271-3: Formula: (< 0 v_~E_M~0_21) InVars {~E_M~0=v_~E_M~0_21} OutVars{~E_M~0=v_~E_M~0_21} AuxVars[] AssignedVars[] 5235#L271-3 [956] L271-3-->L276-3: Formula: (< 0 v_~E_1~0_23) InVars {~E_1~0=v_~E_1~0_23} OutVars{~E_1~0=v_~E_1~0_23} AuxVars[] AssignedVars[] 5230#L276-3 [656] L276-3-->L126-9: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_19, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_17, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_20, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_10|, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_12|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_master_triggered_#res] 5173#L126-9 [964] L126-9-->L126-11: Formula: (< v_~m_pc~0_14 1) InVars {~m_pc~0=v_~m_pc~0_14} OutVars{~m_pc~0=v_~m_pc~0_14} AuxVars[] AssignedVars[] 5172#L126-11 [726] L126-11-->L137-3: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_21 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_21} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 5171#L137-3 [1070] L137-3-->L321-9: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_34 |v_ULTIMATE.start_is_master_triggered_#res_21|) (= |v_ULTIMATE.start_is_master_triggered_#res_21| v_ULTIMATE.start_activate_threads_~tmp~1_34)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_34} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_34, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_34, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_21|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_21|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 4945#L321-9 [789] L321-9-->L321-11: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_24) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_24} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_24} AuxVars[] AssignedVars[] 4946#L321-11 [796] L321-11-->L145-9: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 4940#L145-9 [990] L145-9-->L145-11: Formula: (< v_~t1_pc~0_16 1) InVars {~t1_pc~0=v_~t1_pc~0_16} OutVars{~t1_pc~0=v_~t1_pc~0_16} AuxVars[] AssignedVars[] 4938#L145-11 [745] L145-11-->L156-3: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_29 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_29} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 4936#L156-3 [1073] L156-3-->L329-9: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_34 |v_ULTIMATE.start_is_transmit1_triggered_#res_19|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_34 |v_ULTIMATE.start_is_transmit1_triggered_#res_19|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_34} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_34, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_34, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_21|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_19|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_transmit1_triggered_#res] 4934#L329-9 [614] L329-9-->L329-11: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_25 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_25} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_25} AuxVars[] AssignedVars[] 4932#L329-11 [1009] L329-11-->L289-3: Formula: (> v_~M_E~0_16 1) InVars {~M_E~0=v_~M_E~0_16} OutVars{~M_E~0=v_~M_E~0_16} AuxVars[] AssignedVars[] 4927#L289-3 [1013] L289-3-->L294-3: Formula: (> v_~T1_E~0_16 1) InVars {~T1_E~0=v_~T1_E~0_16} OutVars{~T1_E~0=v_~T1_E~0_16} AuxVars[] AssignedVars[] 4924#L294-3 [1015] L294-3-->L299-3: Formula: (< 1 v_~E_M~0_26) InVars {~E_M~0=v_~E_M~0_26} OutVars{~E_M~0=v_~E_M~0_26} AuxVars[] AssignedVars[] 4922#L299-3 [1018] L299-3-->L304-3: Formula: (< 1 v_~E_1~0_28) InVars {~E_1~0=v_~E_1~0_28} OutVars{~E_1~0=v_~E_1~0_28} AuxVars[] AssignedVars[] 4918#L304-3 [637] L304-3-->L190-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 4919#L190-1 [705] L190-1-->L202-1: Formula: (and (= 0 v_~m_st~0_17) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18 1)) InVars {~m_st~0=v_~m_st~0_17} OutVars{~m_st~0=v_~m_st~0_17, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 5247#L202-1 [1074] L202-1-->L449: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_~tmp~3] 5244#L449 [1026] L449-->L449-1: Formula: (< 0 v_ULTIMATE.start_start_simulation_~tmp~3_4) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_4} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_4} AuxVars[] AssignedVars[] 5243#L449-1 [707] L449-1-->L190-2: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_1, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret6=|v_ULTIMATE.start_stop_simulation_#t~ret6_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret6, ULTIMATE.start_stop_simulation_#res] 5242#L190-2 [698] L190-2-->L202-2: Formula: (and (= v_~m_st~0_5 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_4 1)) InVars {~m_st~0=v_~m_st~0_5} OutVars{~m_st~0=v_~m_st~0_5, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 5240#L202-2 [1076] L202-2-->L404: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_stop_simulation_#t~ret6=|v_ULTIMATE.start_stop_simulation_#t~ret6_4|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret6] 5236#L404 [761] L404-->L411: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 4740#L411 [1083] L411-->L430-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|, ULTIMATE.start_start_simulation_#t~ret8=|v_ULTIMATE.start_start_simulation_#t~ret8_6|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_#t~ret8] 4707#L430-1 33.77/12.79 [2019-03-28 12:22:05,243 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 33.77/12.79 [2019-03-28 12:22:05,243 INFO L82 PathProgramCache]: Analyzing trace with hash -2020096972, now seen corresponding path program 1 times 33.77/12.79 [2019-03-28 12:22:05,244 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 33.77/12.79 [2019-03-28 12:22:05,244 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 33.77/12.79 [2019-03-28 12:22:05,245 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:05,245 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:05,245 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:05,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 33.77/12.79 [2019-03-28 12:22:05,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 33.77/12.79 [2019-03-28 12:22:05,278 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 33.77/12.79 [2019-03-28 12:22:05,278 INFO L82 PathProgramCache]: Analyzing trace with hash 479241636, now seen corresponding path program 1 times 33.77/12.79 [2019-03-28 12:22:05,278 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 33.77/12.79 [2019-03-28 12:22:05,278 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 33.77/12.79 [2019-03-28 12:22:05,279 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:05,279 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:05,279 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:05,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 33.77/12.79 [2019-03-28 12:22:05,300 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 33.77/12.79 [2019-03-28 12:22:05,300 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 33.77/12.79 [2019-03-28 12:22:05,300 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 33.77/12.79 [2019-03-28 12:22:05,301 INFO L811 eck$LassoCheckResult]: loop already infeasible 33.77/12.79 [2019-03-28 12:22:05,301 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. 33.77/12.79 [2019-03-28 12:22:05,301 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 33.77/12.79 [2019-03-28 12:22:05,301 INFO L87 Difference]: Start difference. First operand 569 states and 999 transitions. cyclomatic complexity: 431 Second operand 4 states. 33.77/12.79 [2019-03-28 12:22:05,609 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 33.77/12.79 [2019-03-28 12:22:05,609 INFO L93 Difference]: Finished difference Result 957 states and 1677 transitions. 33.77/12.79 [2019-03-28 12:22:05,610 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. 33.77/12.79 [2019-03-28 12:22:05,610 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 957 states and 1677 transitions. 33.77/12.79 [2019-03-28 12:22:05,616 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 936 33.77/12.79 [2019-03-28 12:22:05,621 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 957 states to 957 states and 1677 transitions. 33.77/12.79 [2019-03-28 12:22:05,621 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 957 33.77/12.79 [2019-03-28 12:22:05,622 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 957 33.77/12.79 [2019-03-28 12:22:05,622 INFO L73 IsDeterministic]: Start isDeterministic. Operand 957 states and 1677 transitions. 33.77/12.79 [2019-03-28 12:22:05,624 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 33.77/12.79 [2019-03-28 12:22:05,624 INFO L706 BuchiCegarLoop]: Abstraction has 957 states and 1677 transitions. 33.77/12.79 [2019-03-28 12:22:05,625 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 957 states and 1677 transitions. 33.77/12.79 [2019-03-28 12:22:05,636 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 957 to 585. 33.77/12.79 [2019-03-28 12:22:05,636 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 585 states. 33.77/12.79 [2019-03-28 12:22:05,638 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 585 states to 585 states and 1023 transitions. 33.77/12.79 [2019-03-28 12:22:05,638 INFO L729 BuchiCegarLoop]: Abstraction has 585 states and 1023 transitions. 33.77/12.79 [2019-03-28 12:22:05,638 INFO L609 BuchiCegarLoop]: Abstraction has 585 states and 1023 transitions. 33.77/12.79 [2019-03-28 12:22:05,638 INFO L442 BuchiCegarLoop]: ======== Iteration 12============ 33.77/12.79 [2019-03-28 12:22:05,638 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 585 states and 1023 transitions. 33.77/12.79 [2019-03-28 12:22:05,641 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 564 33.77/12.79 [2019-03-28 12:22:05,641 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 33.77/12.79 [2019-03-28 12:22:05,641 INFO L119 BuchiIsEmpty]: Starting construction of run 33.77/12.79 [2019-03-28 12:22:05,642 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 33.77/12.79 [2019-03-28 12:22:05,642 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 33.77/12.79 [2019-03-28 12:22:05,643 INFO L794 eck$LassoCheckResult]: Stem: 6314#ULTIMATE.startENTRY [1057] ULTIMATE.startENTRY-->L165: Formula: (and (= 0 v_~m_st~0_20) (= 2 v_~E_M~0_30) (= v_~t1_pc~0_18 0) (= 0 v_~t1_st~0_20) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 0 v_~token~0_8) (= v_~M_E~0_19 2) (= v_~local~0_6 0) (= v_~m_i~0_7 1) (= 2 v_~E_1~0_30) (= v_~m_pc~0_18 0) (= 1 v_~t1_i~0_7)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ~t1_st~0=v_~t1_st~0_20, ~t1_pc~0=v_~t1_pc~0_18, ~M_E~0=v_~M_E~0_19, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_#t~ret8=|v_ULTIMATE.start_start_simulation_#t~ret8_4|, ~token~0=v_~token~0_8, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~E_1~0=v_~E_1~0_30, ~E_M~0=v_~E_M~0_30, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~T1_E~0=v_~T1_E~0_18, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_20, ~m_pc~0=v_~m_pc~0_18, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ~t1_st~0, ~t1_pc~0, ~M_E~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_#t~ret8, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~E_1~0, ~E_M~0, ULTIMATE.start_main_#res, ~T1_E~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0, ULTIMATE.start_main_~__retres1~3] 6308#L165 [720] L165-->L172-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_3 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_3, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 6259#L172-1 [642] L172-1-->L177-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 6260#L177-1 [917] L177-1-->L261-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 6270#L261-1 [919] L261-1-->L266-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 6348#L266-1 [921] L266-1-->L271-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 6267#L271-1 [922] L271-1-->L276-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 6268#L276-1 [657] L276-1-->L126: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_3, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_4, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_1|, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_3|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_master_triggered_#res] 6272#L126 [924] L126-->L126-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 6324#L126-2 [746] L126-2-->L137: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 6325#L137 [1058] L137-->L321: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_16| v_ULTIMATE.start_activate_threads_~tmp~1_29) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_29 |v_ULTIMATE.start_is_master_triggered_#res_16|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_29, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_16|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 6233#L321 [611] L321-->L321-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_8) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8} AuxVars[] AssignedVars[] 6234#L321-2 [615] L321-2-->L145: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 6237#L145 [930] L145-->L145-2: Formula: (< v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 6349#L145-2 [783] L145-2-->L156: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 6350#L156 [1059] L156-->L329: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_29 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_29, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_16|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_transmit1_triggered_#res] 6238#L329 [618] L329-->L329-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_9) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} AuxVars[] AssignedVars[] 6239#L329-2 [937] L329-2-->L289-1: Formula: (> v_~M_E~0_10 1) InVars {~M_E~0=v_~M_E~0_10} OutVars{~M_E~0=v_~M_E~0_10} AuxVars[] AssignedVars[] 6246#L289-1 [939] L289-1-->L294-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 6315#L294-1 [940] L294-1-->L299-1: Formula: (< 1 v_~E_M~0_12) InVars {~E_M~0=v_~E_M~0_12} OutVars{~E_M~0=v_~E_M~0_12} AuxVars[] AssignedVars[] 6240#L299-1 [942] L299-1-->L430-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 6241#L430-1 33.77/12.79 [2019-03-28 12:22:05,643 INFO L796 eck$LassoCheckResult]: Loop: 6241#L430-1 [1060] L430-1-->L236: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 6363#L236 [1061] L236-->L190: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_22, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 6364#L190 [944] L190-->L194: Formula: (< v_~m_st~0_9 0) InVars {~m_st~0=v_~m_st~0_9} OutVars{~m_st~0=v_~m_st~0_9} AuxVars[] AssignedVars[] 6609#L194 [948] L194-->L202: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_13 0) (< v_~t1_st~0_9 0)) InVars {~t1_st~0=v_~t1_st~0_9} OutVars{~t1_st~0=v_~t1_st~0_9, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_13} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 6606#L202 [1062] L202-->L217: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 6607#L217 [1064] L217-->L261-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 6344#L261-2 [946] L261-2-->L261-4: Formula: (> v_~M_E~0_13 0) InVars {~M_E~0=v_~M_E~0_13} OutVars{~M_E~0=v_~M_E~0_13} AuxVars[] AssignedVars[] 6335#L261-4 [951] L261-4-->L266-3: Formula: (> v_~T1_E~0_13 0) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 6336#L266-3 [952] L266-3-->L271-3: Formula: (< 0 v_~E_M~0_21) InVars {~E_M~0=v_~E_M~0_21} OutVars{~E_M~0=v_~E_M~0_21} AuxVars[] AssignedVars[] 6262#L271-3 [956] L271-3-->L276-3: Formula: (< 0 v_~E_1~0_23) InVars {~E_1~0=v_~E_1~0_23} OutVars{~E_1~0=v_~E_1~0_23} AuxVars[] AssignedVars[] 6263#L276-3 [656] L276-3-->L126-9: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_19, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_17, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_20, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_10|, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_12|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_master_triggered_#res] 6271#L126-9 [964] L126-9-->L126-11: Formula: (< v_~m_pc~0_14 1) InVars {~m_pc~0=v_~m_pc~0_14} OutVars{~m_pc~0=v_~m_pc~0_14} AuxVars[] AssignedVars[] 6312#L126-11 [726] L126-11-->L137-3: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_21 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_21} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 6313#L137-3 [1070] L137-3-->L321-9: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_34 |v_ULTIMATE.start_is_master_triggered_#res_21|) (= |v_ULTIMATE.start_is_master_triggered_#res_21| v_ULTIMATE.start_activate_threads_~tmp~1_34)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_34} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_34, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_34, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_21|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_21|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 6322#L321-9 [789] L321-9-->L321-11: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_24) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_24} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_24} AuxVars[] AssignedVars[] 6355#L321-11 [796] L321-11-->L145-9: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 6328#L145-9 [990] L145-9-->L145-11: Formula: (< v_~t1_pc~0_16 1) InVars {~t1_pc~0=v_~t1_pc~0_16} OutVars{~t1_pc~0=v_~t1_pc~0_16} AuxVars[] AssignedVars[] 6329#L145-11 [745] L145-11-->L156-3: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_29 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_29} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 6765#L156-3 [1073] L156-3-->L329-9: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_34 |v_ULTIMATE.start_is_transmit1_triggered_#res_19|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_34 |v_ULTIMATE.start_is_transmit1_triggered_#res_19|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_34} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_34, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_34, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_21|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_19|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_transmit1_triggered_#res] 6763#L329-9 [614] L329-9-->L329-11: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_25 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_25} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_25} AuxVars[] AssignedVars[] 6761#L329-11 [1009] L329-11-->L289-3: Formula: (> v_~M_E~0_16 1) InVars {~M_E~0=v_~M_E~0_16} OutVars{~M_E~0=v_~M_E~0_16} AuxVars[] AssignedVars[] 6757#L289-3 [1013] L289-3-->L294-3: Formula: (> v_~T1_E~0_16 1) InVars {~T1_E~0=v_~T1_E~0_16} OutVars{~T1_E~0=v_~T1_E~0_16} AuxVars[] AssignedVars[] 6758#L294-3 [1015] L294-3-->L299-3: Formula: (< 1 v_~E_M~0_26) InVars {~E_M~0=v_~E_M~0_26} OutVars{~E_M~0=v_~E_M~0_26} AuxVars[] AssignedVars[] 6751#L299-3 [1018] L299-3-->L304-3: Formula: (< 1 v_~E_1~0_28) InVars {~E_1~0=v_~E_1~0_28} OutVars{~E_1~0=v_~E_1~0_28} AuxVars[] AssignedVars[] 6752#L304-3 [637] L304-3-->L190-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 6747#L190-1 [705] L190-1-->L202-1: Formula: (and (= 0 v_~m_st~0_17) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18 1)) InVars {~m_st~0=v_~m_st~0_17} OutVars{~m_st~0=v_~m_st~0_17, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 6746#L202-1 [1074] L202-1-->L449: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_~tmp~3] 6741#L449 [1026] L449-->L449-1: Formula: (< 0 v_ULTIMATE.start_start_simulation_~tmp~3_4) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_4} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_4} AuxVars[] AssignedVars[] 6742#L449-1 [707] L449-1-->L190-2: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_1, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret6=|v_ULTIMATE.start_stop_simulation_#t~ret6_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret6, ULTIMATE.start_stop_simulation_#res] 6806#L190-2 [698] L190-2-->L202-2: Formula: (and (= v_~m_st~0_5 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_4 1)) InVars {~m_st~0=v_~m_st~0_5} OutVars{~m_st~0=v_~m_st~0_5, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 6804#L202-2 [1076] L202-2-->L404: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_stop_simulation_#t~ret6=|v_ULTIMATE.start_stop_simulation_#t~ret6_4|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret6] 6802#L404 [761] L404-->L411: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 6800#L411 [1083] L411-->L430-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|, ULTIMATE.start_start_simulation_#t~ret8=|v_ULTIMATE.start_start_simulation_#t~ret8_6|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_#t~ret8] 6241#L430-1 33.77/12.79 [2019-03-28 12:22:05,644 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 33.77/12.79 [2019-03-28 12:22:05,644 INFO L82 PathProgramCache]: Analyzing trace with hash -2020096972, now seen corresponding path program 2 times 33.77/12.79 [2019-03-28 12:22:05,644 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 33.77/12.79 [2019-03-28 12:22:05,644 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 33.77/12.79 [2019-03-28 12:22:05,645 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:05,645 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:05,645 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:05,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 33.77/12.79 [2019-03-28 12:22:05,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 33.77/12.79 [2019-03-28 12:22:05,657 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 33.77/12.79 [2019-03-28 12:22:05,657 INFO L82 PathProgramCache]: Analyzing trace with hash -1999847136, now seen corresponding path program 1 times 33.77/12.79 [2019-03-28 12:22:05,657 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 33.77/12.79 [2019-03-28 12:22:05,657 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 33.77/12.79 [2019-03-28 12:22:05,658 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:05,658 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:05,658 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:05,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 33.77/12.79 [2019-03-28 12:22:05,683 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 33.77/12.79 [2019-03-28 12:22:05,683 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 33.77/12.79 [2019-03-28 12:22:05,684 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 33.77/12.79 [2019-03-28 12:22:05,684 INFO L811 eck$LassoCheckResult]: loop already infeasible 33.77/12.79 [2019-03-28 12:22:05,684 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 33.77/12.79 [2019-03-28 12:22:05,684 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 33.77/12.79 [2019-03-28 12:22:05,684 INFO L87 Difference]: Start difference. First operand 585 states and 1023 transitions. cyclomatic complexity: 439 Second operand 3 states. 33.77/12.79 [2019-03-28 12:22:05,920 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 33.77/12.79 [2019-03-28 12:22:05,920 INFO L93 Difference]: Finished difference Result 1047 states and 1767 transitions. 33.77/12.79 [2019-03-28 12:22:05,921 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 33.77/12.79 [2019-03-28 12:22:05,921 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1047 states and 1767 transitions. 33.77/12.79 [2019-03-28 12:22:05,927 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1026 33.77/12.79 [2019-03-28 12:22:05,933 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1047 states to 1047 states and 1767 transitions. 33.77/12.79 [2019-03-28 12:22:05,933 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1047 33.77/12.79 [2019-03-28 12:22:05,934 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1047 33.77/12.79 [2019-03-28 12:22:05,934 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1047 states and 1767 transitions. 33.77/12.79 [2019-03-28 12:22:05,936 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 33.77/12.79 [2019-03-28 12:22:05,936 INFO L706 BuchiCegarLoop]: Abstraction has 1047 states and 1767 transitions. 33.77/12.79 [2019-03-28 12:22:05,937 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1047 states and 1767 transitions. 33.77/12.79 [2019-03-28 12:22:05,953 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1047 to 1047. 33.77/12.79 [2019-03-28 12:22:05,953 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1047 states. 33.77/12.79 [2019-03-28 12:22:05,956 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1047 states to 1047 states and 1767 transitions. 33.77/12.79 [2019-03-28 12:22:05,956 INFO L729 BuchiCegarLoop]: Abstraction has 1047 states and 1767 transitions. 33.77/12.79 [2019-03-28 12:22:05,956 INFO L609 BuchiCegarLoop]: Abstraction has 1047 states and 1767 transitions. 33.77/12.79 [2019-03-28 12:22:05,956 INFO L442 BuchiCegarLoop]: ======== Iteration 13============ 33.77/12.79 [2019-03-28 12:22:05,956 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1047 states and 1767 transitions. 33.77/12.79 [2019-03-28 12:22:05,961 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1026 33.77/12.79 [2019-03-28 12:22:05,961 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 33.77/12.79 [2019-03-28 12:22:05,961 INFO L119 BuchiIsEmpty]: Starting construction of run 33.77/12.79 [2019-03-28 12:22:05,962 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 33.77/12.79 [2019-03-28 12:22:05,962 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 33.77/12.79 [2019-03-28 12:22:05,963 INFO L794 eck$LassoCheckResult]: Stem: 7953#ULTIMATE.startENTRY [1057] ULTIMATE.startENTRY-->L165: Formula: (and (= 0 v_~m_st~0_20) (= 2 v_~E_M~0_30) (= v_~t1_pc~0_18 0) (= 0 v_~t1_st~0_20) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 0 v_~token~0_8) (= v_~M_E~0_19 2) (= v_~local~0_6 0) (= v_~m_i~0_7 1) (= 2 v_~E_1~0_30) (= v_~m_pc~0_18 0) (= 1 v_~t1_i~0_7)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ~t1_st~0=v_~t1_st~0_20, ~t1_pc~0=v_~t1_pc~0_18, ~M_E~0=v_~M_E~0_19, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_#t~ret8=|v_ULTIMATE.start_start_simulation_#t~ret8_4|, ~token~0=v_~token~0_8, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~E_1~0=v_~E_1~0_30, ~E_M~0=v_~E_M~0_30, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~T1_E~0=v_~T1_E~0_18, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_20, ~m_pc~0=v_~m_pc~0_18, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ~t1_st~0, ~t1_pc~0, ~M_E~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_#t~ret8, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~E_1~0, ~E_M~0, ULTIMATE.start_main_#res, ~T1_E~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0, ULTIMATE.start_main_~__retres1~3] 7948#L165 [720] L165-->L172-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_3 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_3, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 7896#L172-1 [642] L172-1-->L177-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 7897#L177-1 [917] L177-1-->L261-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 7908#L261-1 [919] L261-1-->L266-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 7992#L266-1 [921] L266-1-->L271-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 7904#L271-1 [922] L271-1-->L276-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 7905#L276-1 [657] L276-1-->L126: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_3, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_4, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_1|, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_3|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_master_triggered_#res] 7910#L126 [924] L126-->L126-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 7965#L126-2 [746] L126-2-->L137: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 7966#L137 [1058] L137-->L321: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_16| v_ULTIMATE.start_activate_threads_~tmp~1_29) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_29 |v_ULTIMATE.start_is_master_triggered_#res_16|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_29, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_16|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 7870#L321 [611] L321-->L321-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_8) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8} AuxVars[] AssignedVars[] 7871#L321-2 [615] L321-2-->L145: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 7875#L145 [930] L145-->L145-2: Formula: (< v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 7993#L145-2 [783] L145-2-->L156: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 7994#L156 [1059] L156-->L329: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_29 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_29, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_16|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_transmit1_triggered_#res] 7876#L329 [618] L329-->L329-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_9) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} AuxVars[] AssignedVars[] 7877#L329-2 [937] L329-2-->L289-1: Formula: (> v_~M_E~0_10 1) InVars {~M_E~0=v_~M_E~0_10} OutVars{~M_E~0=v_~M_E~0_10} AuxVars[] AssignedVars[] 7884#L289-1 [939] L289-1-->L294-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 7954#L294-1 [940] L294-1-->L299-1: Formula: (< 1 v_~E_M~0_12) InVars {~E_M~0=v_~E_M~0_12} OutVars{~E_M~0=v_~E_M~0_12} AuxVars[] AssignedVars[] 7878#L299-1 [942] L299-1-->L430-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 7879#L430-1 33.77/12.79 [2019-03-28 12:22:05,963 INFO L796 eck$LassoCheckResult]: Loop: 7879#L430-1 [1060] L430-1-->L236: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 8414#L236 [1061] L236-->L190: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_22, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 8466#L190 [945] L190-->L194: Formula: (> v_~m_st~0_9 0) InVars {~m_st~0=v_~m_st~0_9} OutVars{~m_st~0=v_~m_st~0_9} AuxVars[] AssignedVars[] 8464#L194 [948] L194-->L202: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_13 0) (< v_~t1_st~0_9 0)) InVars {~t1_st~0=v_~t1_st~0_9} OutVars{~t1_st~0=v_~t1_st~0_9, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_13} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 8461#L202 [1062] L202-->L217: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 8462#L217 [1064] L217-->L261-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 8770#L261-2 [946] L261-2-->L261-4: Formula: (> v_~M_E~0_13 0) InVars {~M_E~0=v_~M_E~0_13} OutVars{~M_E~0=v_~M_E~0_13} AuxVars[] AssignedVars[] 8768#L261-4 [951] L261-4-->L266-3: Formula: (> v_~T1_E~0_13 0) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 8766#L266-3 [952] L266-3-->L271-3: Formula: (< 0 v_~E_M~0_21) InVars {~E_M~0=v_~E_M~0_21} OutVars{~E_M~0=v_~E_M~0_21} AuxVars[] AssignedVars[] 8763#L271-3 [956] L271-3-->L276-3: Formula: (< 0 v_~E_1~0_23) InVars {~E_1~0=v_~E_1~0_23} OutVars{~E_1~0=v_~E_1~0_23} AuxVars[] AssignedVars[] 8744#L276-3 [656] L276-3-->L126-9: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_19, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_17, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_20, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_10|, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_12|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_master_triggered_#res] 7974#L126-9 [964] L126-9-->L126-11: Formula: (< v_~m_pc~0_14 1) InVars {~m_pc~0=v_~m_pc~0_14} OutVars{~m_pc~0=v_~m_pc~0_14} AuxVars[] AssignedVars[] 7975#L126-11 [726] L126-11-->L137-3: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_21 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_21} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 8740#L137-3 [1070] L137-3-->L321-9: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_34 |v_ULTIMATE.start_is_master_triggered_#res_21|) (= |v_ULTIMATE.start_is_master_triggered_#res_21| v_ULTIMATE.start_activate_threads_~tmp~1_34)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_34} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_34, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_34, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_21|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_21|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 8711#L321-9 [789] L321-9-->L321-11: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_24) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_24} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_24} AuxVars[] AssignedVars[] 8707#L321-11 [796] L321-11-->L145-9: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 8698#L145-9 [990] L145-9-->L145-11: Formula: (< v_~t1_pc~0_16 1) InVars {~t1_pc~0=v_~t1_pc~0_16} OutVars{~t1_pc~0=v_~t1_pc~0_16} AuxVars[] AssignedVars[] 8523#L145-11 [745] L145-11-->L156-3: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_29 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_29} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 8687#L156-3 [1073] L156-3-->L329-9: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_34 |v_ULTIMATE.start_is_transmit1_triggered_#res_19|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_34 |v_ULTIMATE.start_is_transmit1_triggered_#res_19|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_34} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_34, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_34, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_21|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_19|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_transmit1_triggered_#res] 8682#L329-9 [614] L329-9-->L329-11: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_25 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_25} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_25} AuxVars[] AssignedVars[] 8656#L329-11 [1009] L329-11-->L289-3: Formula: (> v_~M_E~0_16 1) InVars {~M_E~0=v_~M_E~0_16} OutVars{~M_E~0=v_~M_E~0_16} AuxVars[] AssignedVars[] 8654#L289-3 [1013] L289-3-->L294-3: Formula: (> v_~T1_E~0_16 1) InVars {~T1_E~0=v_~T1_E~0_16} OutVars{~T1_E~0=v_~T1_E~0_16} AuxVars[] AssignedVars[] 8652#L294-3 [1015] L294-3-->L299-3: Formula: (< 1 v_~E_M~0_26) InVars {~E_M~0=v_~E_M~0_26} OutVars{~E_M~0=v_~E_M~0_26} AuxVars[] AssignedVars[] 8650#L299-3 [1018] L299-3-->L304-3: Formula: (< 1 v_~E_1~0_28) InVars {~E_1~0=v_~E_1~0_28} OutVars{~E_1~0=v_~E_1~0_28} AuxVars[] AssignedVars[] 8648#L304-3 [637] L304-3-->L190-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 8646#L190-1 [705] L190-1-->L202-1: Formula: (and (= 0 v_~m_st~0_17) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18 1)) InVars {~m_st~0=v_~m_st~0_17} OutVars{~m_st~0=v_~m_st~0_17, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 8643#L202-1 [1074] L202-1-->L449: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_~tmp~3] 8637#L449 [1026] L449-->L449-1: Formula: (< 0 v_ULTIMATE.start_start_simulation_~tmp~3_4) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_4} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_4} AuxVars[] AssignedVars[] 8632#L449-1 [707] L449-1-->L190-2: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_1, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret6=|v_ULTIMATE.start_stop_simulation_#t~ret6_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret6, ULTIMATE.start_stop_simulation_#res] 8630#L190-2 [698] L190-2-->L202-2: Formula: (and (= v_~m_st~0_5 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_4 1)) InVars {~m_st~0=v_~m_st~0_5} OutVars{~m_st~0=v_~m_st~0_5, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 8628#L202-2 [1076] L202-2-->L404: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_stop_simulation_#t~ret6=|v_ULTIMATE.start_stop_simulation_#t~ret6_4|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret6] 8627#L404 [761] L404-->L411: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 8626#L411 [1083] L411-->L430-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|, ULTIMATE.start_start_simulation_#t~ret8=|v_ULTIMATE.start_start_simulation_#t~ret8_6|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_#t~ret8] 7879#L430-1 33.77/12.79 [2019-03-28 12:22:05,964 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 33.77/12.79 [2019-03-28 12:22:05,964 INFO L82 PathProgramCache]: Analyzing trace with hash -2020096972, now seen corresponding path program 3 times 33.77/12.79 [2019-03-28 12:22:05,964 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 33.77/12.79 [2019-03-28 12:22:05,964 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 33.77/12.79 [2019-03-28 12:22:05,965 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:05,965 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:05,965 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:05,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 33.77/12.79 [2019-03-28 12:22:05,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 33.77/12.79 [2019-03-28 12:22:05,977 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 33.77/12.79 [2019-03-28 12:22:05,978 INFO L82 PathProgramCache]: Analyzing trace with hash -1649047199, now seen corresponding path program 1 times 33.77/12.79 [2019-03-28 12:22:05,978 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 33.77/12.79 [2019-03-28 12:22:05,978 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 33.77/12.79 [2019-03-28 12:22:05,979 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.79 [2019-03-28 12:22:05,979 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 33.77/12.80 [2019-03-28 12:22:05,979 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.80 [2019-03-28 12:22:05,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 33.77/12.80 [2019-03-28 12:22:06,001 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 33.77/12.80 [2019-03-28 12:22:06,001 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 33.77/12.80 [2019-03-28 12:22:06,001 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 33.77/12.80 [2019-03-28 12:22:06,002 INFO L811 eck$LassoCheckResult]: loop already infeasible 33.77/12.80 [2019-03-28 12:22:06,002 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 33.77/12.80 [2019-03-28 12:22:06,002 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 33.77/12.80 [2019-03-28 12:22:06,002 INFO L87 Difference]: Start difference. First operand 1047 states and 1767 transitions. cyclomatic complexity: 721 Second operand 3 states. 33.77/12.80 [2019-03-28 12:22:06,275 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 33.77/12.80 [2019-03-28 12:22:06,275 INFO L93 Difference]: Finished difference Result 1419 states and 2341 transitions. 33.77/12.80 [2019-03-28 12:22:06,276 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 33.77/12.80 [2019-03-28 12:22:06,276 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1419 states and 2341 transitions. 33.77/12.80 [2019-03-28 12:22:06,283 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1398 33.77/12.80 [2019-03-28 12:22:06,291 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1419 states to 1419 states and 2341 transitions. 33.77/12.80 [2019-03-28 12:22:06,292 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1419 33.77/12.80 [2019-03-28 12:22:06,293 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1419 33.77/12.80 [2019-03-28 12:22:06,293 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1419 states and 2341 transitions. 33.77/12.80 [2019-03-28 12:22:06,295 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 33.77/12.80 [2019-03-28 12:22:06,295 INFO L706 BuchiCegarLoop]: Abstraction has 1419 states and 2341 transitions. 33.77/12.80 [2019-03-28 12:22:06,296 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1419 states and 2341 transitions. 33.77/12.80 [2019-03-28 12:22:06,317 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1419 to 1393. 33.77/12.80 [2019-03-28 12:22:06,317 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1393 states. 33.77/12.80 [2019-03-28 12:22:06,321 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1393 states to 1393 states and 2299 transitions. 33.77/12.80 [2019-03-28 12:22:06,321 INFO L729 BuchiCegarLoop]: Abstraction has 1393 states and 2299 transitions. 33.77/12.80 [2019-03-28 12:22:06,321 INFO L609 BuchiCegarLoop]: Abstraction has 1393 states and 2299 transitions. 33.77/12.80 [2019-03-28 12:22:06,321 INFO L442 BuchiCegarLoop]: ======== Iteration 14============ 33.77/12.80 [2019-03-28 12:22:06,322 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1393 states and 2299 transitions. 33.77/12.80 [2019-03-28 12:22:06,327 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1372 33.77/12.80 [2019-03-28 12:22:06,327 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 33.77/12.80 [2019-03-28 12:22:06,327 INFO L119 BuchiIsEmpty]: Starting construction of run 33.77/12.80 [2019-03-28 12:22:06,329 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 33.77/12.80 [2019-03-28 12:22:06,329 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 33.77/12.80 [2019-03-28 12:22:06,329 INFO L794 eck$LassoCheckResult]: Stem: 10426#ULTIMATE.startENTRY [1057] ULTIMATE.startENTRY-->L165: Formula: (and (= 0 v_~m_st~0_20) (= 2 v_~E_M~0_30) (= v_~t1_pc~0_18 0) (= 0 v_~t1_st~0_20) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 0 v_~token~0_8) (= v_~M_E~0_19 2) (= v_~local~0_6 0) (= v_~m_i~0_7 1) (= 2 v_~E_1~0_30) (= v_~m_pc~0_18 0) (= 1 v_~t1_i~0_7)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ~t1_st~0=v_~t1_st~0_20, ~t1_pc~0=v_~t1_pc~0_18, ~M_E~0=v_~M_E~0_19, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_#t~ret8=|v_ULTIMATE.start_start_simulation_#t~ret8_4|, ~token~0=v_~token~0_8, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~E_1~0=v_~E_1~0_30, ~E_M~0=v_~E_M~0_30, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~T1_E~0=v_~T1_E~0_18, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_20, ~m_pc~0=v_~m_pc~0_18, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ~t1_st~0, ~t1_pc~0, ~M_E~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_#t~ret8, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~E_1~0, ~E_M~0, ULTIMATE.start_main_#res, ~T1_E~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0, ULTIMATE.start_main_~__retres1~3] 10420#L165 [720] L165-->L172-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_3 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_3, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 10369#L172-1 [642] L172-1-->L177-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 10370#L177-1 [917] L177-1-->L261-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 10380#L261-1 [919] L261-1-->L266-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 10456#L266-1 [921] L266-1-->L271-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 10377#L271-1 [922] L271-1-->L276-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 10378#L276-1 [657] L276-1-->L126: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_3, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_4, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_1|, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_3|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_master_triggered_#res] 10382#L126 [924] L126-->L126-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 10436#L126-2 [746] L126-2-->L137: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 10437#L137 [1058] L137-->L321: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_16| v_ULTIMATE.start_activate_threads_~tmp~1_29) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_29 |v_ULTIMATE.start_is_master_triggered_#res_16|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_29, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_16|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 10343#L321 [611] L321-->L321-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_8) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8} AuxVars[] AssignedVars[] 10344#L321-2 [615] L321-2-->L145: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 10347#L145 [930] L145-->L145-2: Formula: (< v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 10457#L145-2 [783] L145-2-->L156: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 10458#L156 [1059] L156-->L329: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_29 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_29, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_16|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_transmit1_triggered_#res] 10348#L329 [618] L329-->L329-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_9) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} AuxVars[] AssignedVars[] 10349#L329-2 [937] L329-2-->L289-1: Formula: (> v_~M_E~0_10 1) InVars {~M_E~0=v_~M_E~0_10} OutVars{~M_E~0=v_~M_E~0_10} AuxVars[] AssignedVars[] 10356#L289-1 [939] L289-1-->L294-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 10427#L294-1 [940] L294-1-->L299-1: Formula: (< 1 v_~E_M~0_12) InVars {~E_M~0=v_~E_M~0_12} OutVars{~E_M~0=v_~E_M~0_12} AuxVars[] AssignedVars[] 10350#L299-1 [942] L299-1-->L430-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 10351#L430-1 33.77/12.80 [2019-03-28 12:22:06,330 INFO L796 eck$LassoCheckResult]: Loop: 10351#L430-1 [1060] L430-1-->L236: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 11237#L236 [1061] L236-->L190: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_22, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 11246#L190 [944] L190-->L194: Formula: (< v_~m_st~0_9 0) InVars {~m_st~0=v_~m_st~0_9} OutVars{~m_st~0=v_~m_st~0_9} AuxVars[] AssignedVars[] 11247#L194 [948] L194-->L202: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_13 0) (< v_~t1_st~0_9 0)) InVars {~t1_st~0=v_~t1_st~0_9} OutVars{~t1_st~0=v_~t1_st~0_9, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_13} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 11467#L202 [1062] L202-->L217: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 11468#L217 [1064] L217-->L261-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 11665#L261-2 [946] L261-2-->L261-4: Formula: (> v_~M_E~0_13 0) InVars {~M_E~0=v_~M_E~0_13} OutVars{~M_E~0=v_~M_E~0_13} AuxVars[] AssignedVars[] 11663#L261-4 [951] L261-4-->L266-3: Formula: (> v_~T1_E~0_13 0) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 11661#L266-3 [952] L266-3-->L271-3: Formula: (< 0 v_~E_M~0_21) InVars {~E_M~0=v_~E_M~0_21} OutVars{~E_M~0=v_~E_M~0_21} AuxVars[] AssignedVars[] 11659#L271-3 [956] L271-3-->L276-3: Formula: (< 0 v_~E_1~0_23) InVars {~E_1~0=v_~E_1~0_23} OutVars{~E_1~0=v_~E_1~0_23} AuxVars[] AssignedVars[] 11658#L276-3 [656] L276-3-->L126-9: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_19, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_17, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_20, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_10|, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_12|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_master_triggered_#res] 11657#L126-9 [964] L126-9-->L126-11: Formula: (< v_~m_pc~0_14 1) InVars {~m_pc~0=v_~m_pc~0_14} OutVars{~m_pc~0=v_~m_pc~0_14} AuxVars[] AssignedVars[] 11450#L126-11 [726] L126-11-->L137-3: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_21 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_21} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 11651#L137-3 [1070] L137-3-->L321-9: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_34 |v_ULTIMATE.start_is_master_triggered_#res_21|) (= |v_ULTIMATE.start_is_master_triggered_#res_21| v_ULTIMATE.start_activate_threads_~tmp~1_34)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_34} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_34, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_34, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_21|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_21|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 11635#L321-9 [982] L321-9-->L321-11: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_23) (= v_~m_st~0_16 0)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_23} OutVars{~m_st~0=v_~m_st~0_16, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_23} AuxVars[] AssignedVars[~m_st~0] 10465#L321-11 [796] L321-11-->L145-9: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 11342#L145-9 [990] L145-9-->L145-11: Formula: (< v_~t1_pc~0_16 1) InVars {~t1_pc~0=v_~t1_pc~0_16} OutVars{~t1_pc~0=v_~t1_pc~0_16} AuxVars[] AssignedVars[] 11101#L145-11 [745] L145-11-->L156-3: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_29 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_29} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 11340#L156-3 [1073] L156-3-->L329-9: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_34 |v_ULTIMATE.start_is_transmit1_triggered_#res_19|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_34 |v_ULTIMATE.start_is_transmit1_triggered_#res_19|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_34} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_34, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_34, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_21|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_19|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_transmit1_triggered_#res] 11338#L329-9 [614] L329-9-->L329-11: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_25 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_25} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_25} AuxVars[] AssignedVars[] 11336#L329-11 [1009] L329-11-->L289-3: Formula: (> v_~M_E~0_16 1) InVars {~M_E~0=v_~M_E~0_16} OutVars{~M_E~0=v_~M_E~0_16} AuxVars[] AssignedVars[] 11334#L289-3 [1013] L289-3-->L294-3: Formula: (> v_~T1_E~0_16 1) InVars {~T1_E~0=v_~T1_E~0_16} OutVars{~T1_E~0=v_~T1_E~0_16} AuxVars[] AssignedVars[] 11332#L294-3 [1015] L294-3-->L299-3: Formula: (< 1 v_~E_M~0_26) InVars {~E_M~0=v_~E_M~0_26} OutVars{~E_M~0=v_~E_M~0_26} AuxVars[] AssignedVars[] 11330#L299-3 [1018] L299-3-->L304-3: Formula: (< 1 v_~E_1~0_28) InVars {~E_1~0=v_~E_1~0_28} OutVars{~E_1~0=v_~E_1~0_28} AuxVars[] AssignedVars[] 11328#L304-3 [637] L304-3-->L190-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 11324#L190-1 [705] L190-1-->L202-1: Formula: (and (= 0 v_~m_st~0_17) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18 1)) InVars {~m_st~0=v_~m_st~0_17} OutVars{~m_st~0=v_~m_st~0_17, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 11320#L202-1 [1074] L202-1-->L449: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_~tmp~3] 11294#L449 [1026] L449-->L449-1: Formula: (< 0 v_ULTIMATE.start_start_simulation_~tmp~3_4) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_4} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_4} AuxVars[] AssignedVars[] 11292#L449-1 [707] L449-1-->L190-2: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_1, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret6=|v_ULTIMATE.start_stop_simulation_#t~ret6_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret6, ULTIMATE.start_stop_simulation_#res] 11289#L190-2 [698] L190-2-->L202-2: Formula: (and (= v_~m_st~0_5 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_4 1)) InVars {~m_st~0=v_~m_st~0_5} OutVars{~m_st~0=v_~m_st~0_5, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 11287#L202-2 [1076] L202-2-->L404: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_stop_simulation_#t~ret6=|v_ULTIMATE.start_stop_simulation_#t~ret6_4|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret6] 11256#L404 [761] L404-->L411: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 11252#L411 [1083] L411-->L430-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|, ULTIMATE.start_start_simulation_#t~ret8=|v_ULTIMATE.start_start_simulation_#t~ret8_6|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_#t~ret8] 10351#L430-1 33.77/12.80 [2019-03-28 12:22:06,330 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 33.77/12.80 [2019-03-28 12:22:06,331 INFO L82 PathProgramCache]: Analyzing trace with hash -2020096972, now seen corresponding path program 4 times 33.77/12.80 [2019-03-28 12:22:06,331 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 33.77/12.80 [2019-03-28 12:22:06,331 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 33.77/12.80 [2019-03-28 12:22:06,333 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.80 [2019-03-28 12:22:06,333 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 33.77/12.80 [2019-03-28 12:22:06,333 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.80 [2019-03-28 12:22:06,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 33.77/12.80 [2019-03-28 12:22:06,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 33.77/12.80 [2019-03-28 12:22:06,345 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 33.77/12.80 [2019-03-28 12:22:06,345 INFO L82 PathProgramCache]: Analyzing trace with hash -1774160991, now seen corresponding path program 1 times 33.77/12.80 [2019-03-28 12:22:06,345 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 33.77/12.80 [2019-03-28 12:22:06,345 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 33.77/12.80 [2019-03-28 12:22:06,346 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.80 [2019-03-28 12:22:06,346 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 33.77/12.80 [2019-03-28 12:22:06,346 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.80 [2019-03-28 12:22:06,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 33.77/12.80 [2019-03-28 12:22:06,381 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 33.77/12.80 [2019-03-28 12:22:06,382 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 33.77/12.80 [2019-03-28 12:22:06,382 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 33.77/12.80 [2019-03-28 12:22:06,382 INFO L811 eck$LassoCheckResult]: loop already infeasible 33.77/12.80 [2019-03-28 12:22:06,382 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. 33.77/12.80 [2019-03-28 12:22:06,382 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 33.77/12.80 [2019-03-28 12:22:06,383 INFO L87 Difference]: Start difference. First operand 1393 states and 2299 transitions. cyclomatic complexity: 907 Second operand 6 states. 33.77/12.80 [2019-03-28 12:22:07,277 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 33.77/12.80 [2019-03-28 12:22:07,278 INFO L93 Difference]: Finished difference Result 3116 states and 5219 transitions. 33.77/12.80 [2019-03-28 12:22:07,278 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. 33.77/12.80 [2019-03-28 12:22:07,278 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3116 states and 5219 transitions. 33.77/12.80 [2019-03-28 12:22:07,295 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3094 33.77/12.80 [2019-03-28 12:22:07,313 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3116 states to 3116 states and 5219 transitions. 33.77/12.80 [2019-03-28 12:22:07,313 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3116 33.77/12.80 [2019-03-28 12:22:07,316 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3116 33.77/12.80 [2019-03-28 12:22:07,316 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3116 states and 5219 transitions. 33.77/12.80 [2019-03-28 12:22:07,319 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 33.77/12.80 [2019-03-28 12:22:07,319 INFO L706 BuchiCegarLoop]: Abstraction has 3116 states and 5219 transitions. 33.77/12.80 [2019-03-28 12:22:07,321 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3116 states and 5219 transitions. 33.77/12.80 [2019-03-28 12:22:07,353 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3116 to 1405. 33.77/12.80 [2019-03-28 12:22:07,353 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1405 states. 33.77/12.80 [2019-03-28 12:22:07,357 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1405 states to 1405 states and 2262 transitions. 33.77/12.80 [2019-03-28 12:22:07,357 INFO L729 BuchiCegarLoop]: Abstraction has 1405 states and 2262 transitions. 33.77/12.80 [2019-03-28 12:22:07,357 INFO L609 BuchiCegarLoop]: Abstraction has 1405 states and 2262 transitions. 33.77/12.80 [2019-03-28 12:22:07,357 INFO L442 BuchiCegarLoop]: ======== Iteration 15============ 33.77/12.80 [2019-03-28 12:22:07,357 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1405 states and 2262 transitions. 33.77/12.80 [2019-03-28 12:22:07,363 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1384 33.77/12.80 [2019-03-28 12:22:07,363 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 33.77/12.80 [2019-03-28 12:22:07,363 INFO L119 BuchiIsEmpty]: Starting construction of run 33.77/12.80 [2019-03-28 12:22:07,365 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 33.77/12.80 [2019-03-28 12:22:07,365 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 33.77/12.80 [2019-03-28 12:22:07,365 INFO L794 eck$LassoCheckResult]: Stem: 14979#ULTIMATE.startENTRY [1057] ULTIMATE.startENTRY-->L165: Formula: (and (= 0 v_~m_st~0_20) (= 2 v_~E_M~0_30) (= v_~t1_pc~0_18 0) (= 0 v_~t1_st~0_20) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 0 v_~token~0_8) (= v_~M_E~0_19 2) (= v_~local~0_6 0) (= v_~m_i~0_7 1) (= 2 v_~E_1~0_30) (= v_~m_pc~0_18 0) (= 1 v_~t1_i~0_7)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ~t1_st~0=v_~t1_st~0_20, ~t1_pc~0=v_~t1_pc~0_18, ~M_E~0=v_~M_E~0_19, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_#t~ret8=|v_ULTIMATE.start_start_simulation_#t~ret8_4|, ~token~0=v_~token~0_8, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~E_1~0=v_~E_1~0_30, ~E_M~0=v_~E_M~0_30, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~T1_E~0=v_~T1_E~0_18, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_20, ~m_pc~0=v_~m_pc~0_18, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ~t1_st~0, ~t1_pc~0, ~M_E~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_#t~ret8, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~E_1~0, ~E_M~0, ULTIMATE.start_main_#res, ~T1_E~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0, ULTIMATE.start_main_~__retres1~3] 14974#L165 [720] L165-->L172-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_3 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_3, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 14915#L172-1 [642] L172-1-->L177-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 14916#L177-1 [917] L177-1-->L261-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 14927#L261-1 [919] L261-1-->L266-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 15021#L266-1 [921] L266-1-->L271-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 14923#L271-1 [922] L271-1-->L276-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 14924#L276-1 [657] L276-1-->L126: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_3, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_4, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_1|, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_3|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_master_triggered_#res] 14930#L126 [924] L126-->L126-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 14991#L126-2 [746] L126-2-->L137: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 14992#L137 [1058] L137-->L321: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_16| v_ULTIMATE.start_activate_threads_~tmp~1_29) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_29 |v_ULTIMATE.start_is_master_triggered_#res_16|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_29, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_16|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 14887#L321 [611] L321-->L321-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_8) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8} AuxVars[] AssignedVars[] 14888#L321-2 [615] L321-2-->L145: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 14892#L145 [930] L145-->L145-2: Formula: (< v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 15022#L145-2 [783] L145-2-->L156: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 15023#L156 [1059] L156-->L329: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_29 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_29, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_16|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_transmit1_triggered_#res] 14893#L329 [618] L329-->L329-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_9) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} AuxVars[] AssignedVars[] 14894#L329-2 [937] L329-2-->L289-1: Formula: (> v_~M_E~0_10 1) InVars {~M_E~0=v_~M_E~0_10} OutVars{~M_E~0=v_~M_E~0_10} AuxVars[] AssignedVars[] 14901#L289-1 [939] L289-1-->L294-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 14980#L294-1 [940] L294-1-->L299-1: Formula: (< 1 v_~E_M~0_12) InVars {~E_M~0=v_~E_M~0_12} OutVars{~E_M~0=v_~E_M~0_12} AuxVars[] AssignedVars[] 14895#L299-1 [942] L299-1-->L430-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 14896#L430-1 33.77/12.80 [2019-03-28 12:22:07,366 INFO L796 eck$LassoCheckResult]: Loop: 14896#L430-1 [1060] L430-1-->L236: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 15113#L236 [1061] L236-->L190: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_22, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 15108#L190 [944] L190-->L194: Formula: (< v_~m_st~0_9 0) InVars {~m_st~0=v_~m_st~0_9} OutVars{~m_st~0=v_~m_st~0_9} AuxVars[] AssignedVars[] 15109#L194 [948] L194-->L202: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_13 0) (< v_~t1_st~0_9 0)) InVars {~t1_st~0=v_~t1_st~0_9} OutVars{~t1_st~0=v_~t1_st~0_9, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_13} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 15428#L202 [1062] L202-->L217: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 15422#L217 [1064] L217-->L261-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 15415#L261-2 [946] L261-2-->L261-4: Formula: (> v_~M_E~0_13 0) InVars {~M_E~0=v_~M_E~0_13} OutVars{~M_E~0=v_~M_E~0_13} AuxVars[] AssignedVars[] 15410#L261-4 [951] L261-4-->L266-3: Formula: (> v_~T1_E~0_13 0) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 15405#L266-3 [952] L266-3-->L271-3: Formula: (< 0 v_~E_M~0_21) InVars {~E_M~0=v_~E_M~0_21} OutVars{~E_M~0=v_~E_M~0_21} AuxVars[] AssignedVars[] 15397#L271-3 [956] L271-3-->L276-3: Formula: (< 0 v_~E_1~0_23) InVars {~E_1~0=v_~E_1~0_23} OutVars{~E_1~0=v_~E_1~0_23} AuxVars[] AssignedVars[] 15248#L276-3 [656] L276-3-->L126-9: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_19, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_17, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_20, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_10|, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_12|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_master_triggered_#res] 15249#L126-9 [964] L126-9-->L126-11: Formula: (< v_~m_pc~0_14 1) InVars {~m_pc~0=v_~m_pc~0_14} OutVars{~m_pc~0=v_~m_pc~0_14} AuxVars[] AssignedVars[] 15317#L126-11 [726] L126-11-->L137-3: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_21 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_21} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 15384#L137-3 [1070] L137-3-->L321-9: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_34 |v_ULTIMATE.start_is_master_triggered_#res_21|) (= |v_ULTIMATE.start_is_master_triggered_#res_21| v_ULTIMATE.start_activate_threads_~tmp~1_34)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_34} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_34, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_34, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_21|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_21|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 15385#L321-9 [983] L321-9-->L321-11: Formula: (and (= v_~m_st~0_16 0) (> 0 v_ULTIMATE.start_activate_threads_~tmp~1_23)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_23} OutVars{~m_st~0=v_~m_st~0_16, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_23} AuxVars[] AssignedVars[~m_st~0] 15029#L321-11 [796] L321-11-->L145-9: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 15211#L145-9 [990] L145-9-->L145-11: Formula: (< v_~t1_pc~0_16 1) InVars {~t1_pc~0=v_~t1_pc~0_16} OutVars{~t1_pc~0=v_~t1_pc~0_16} AuxVars[] AssignedVars[] 15209#L145-11 [745] L145-11-->L156-3: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_29 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_29} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 15207#L156-3 [1073] L156-3-->L329-9: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_34 |v_ULTIMATE.start_is_transmit1_triggered_#res_19|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_34 |v_ULTIMATE.start_is_transmit1_triggered_#res_19|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_34} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_34, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_34, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_21|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_19|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_transmit1_triggered_#res] 15205#L329-9 [614] L329-9-->L329-11: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_25 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_25} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_25} AuxVars[] AssignedVars[] 15203#L329-11 [1009] L329-11-->L289-3: Formula: (> v_~M_E~0_16 1) InVars {~M_E~0=v_~M_E~0_16} OutVars{~M_E~0=v_~M_E~0_16} AuxVars[] AssignedVars[] 15199#L289-3 [1013] L289-3-->L294-3: Formula: (> v_~T1_E~0_16 1) InVars {~T1_E~0=v_~T1_E~0_16} OutVars{~T1_E~0=v_~T1_E~0_16} AuxVars[] AssignedVars[] 15200#L294-3 [1015] L294-3-->L299-3: Formula: (< 1 v_~E_M~0_26) InVars {~E_M~0=v_~E_M~0_26} OutVars{~E_M~0=v_~E_M~0_26} AuxVars[] AssignedVars[] 15195#L299-3 [1018] L299-3-->L304-3: Formula: (< 1 v_~E_1~0_28) InVars {~E_1~0=v_~E_1~0_28} OutVars{~E_1~0=v_~E_1~0_28} AuxVars[] AssignedVars[] 15196#L304-3 [637] L304-3-->L190-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 15189#L190-1 [705] L190-1-->L202-1: Formula: (and (= 0 v_~m_st~0_17) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18 1)) InVars {~m_st~0=v_~m_st~0_17} OutVars{~m_st~0=v_~m_st~0_17, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 15190#L202-1 [1074] L202-1-->L449: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_~tmp~3] 15184#L449 [1026] L449-->L449-1: Formula: (< 0 v_ULTIMATE.start_start_simulation_~tmp~3_4) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_4} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_4} AuxVars[] AssignedVars[] 15143#L449-1 [707] L449-1-->L190-2: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_1, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret6=|v_ULTIMATE.start_stop_simulation_#t~ret6_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret6, ULTIMATE.start_stop_simulation_#res] 15144#L190-2 [698] L190-2-->L202-2: Formula: (and (= v_~m_st~0_5 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_4 1)) InVars {~m_st~0=v_~m_st~0_5} OutVars{~m_st~0=v_~m_st~0_5, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 15137#L202-2 [1076] L202-2-->L404: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_stop_simulation_#t~ret6=|v_ULTIMATE.start_stop_simulation_#t~ret6_4|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret6] 15138#L404 [761] L404-->L411: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 15134#L411 [1083] L411-->L430-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|, ULTIMATE.start_start_simulation_#t~ret8=|v_ULTIMATE.start_start_simulation_#t~ret8_6|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_#t~ret8] 14896#L430-1 33.77/12.80 [2019-03-28 12:22:07,366 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 33.77/12.80 [2019-03-28 12:22:07,366 INFO L82 PathProgramCache]: Analyzing trace with hash -2020096972, now seen corresponding path program 5 times 33.77/12.80 [2019-03-28 12:22:07,367 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 33.77/12.80 [2019-03-28 12:22:07,367 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 33.77/12.80 [2019-03-28 12:22:07,368 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.80 [2019-03-28 12:22:07,368 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 33.77/12.80 [2019-03-28 12:22:07,368 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.80 [2019-03-28 12:22:07,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 33.77/12.80 [2019-03-28 12:22:07,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 33.77/12.80 [2019-03-28 12:22:07,379 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 33.77/12.80 [2019-03-28 12:22:07,380 INFO L82 PathProgramCache]: Analyzing trace with hash 1676334434, now seen corresponding path program 1 times 33.77/12.80 [2019-03-28 12:22:07,380 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 33.77/12.80 [2019-03-28 12:22:07,380 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 33.77/12.80 [2019-03-28 12:22:07,381 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.80 [2019-03-28 12:22:07,381 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 33.77/12.80 [2019-03-28 12:22:07,381 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.80 [2019-03-28 12:22:07,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 33.77/12.80 [2019-03-28 12:22:07,413 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 33.77/12.80 [2019-03-28 12:22:07,413 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 33.77/12.80 [2019-03-28 12:22:07,413 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 33.77/12.80 [2019-03-28 12:22:07,414 INFO L811 eck$LassoCheckResult]: loop already infeasible 33.77/12.80 [2019-03-28 12:22:07,414 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. 33.77/12.80 [2019-03-28 12:22:07,414 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 33.77/12.80 [2019-03-28 12:22:07,414 INFO L87 Difference]: Start difference. First operand 1405 states and 2262 transitions. cyclomatic complexity: 858 Second operand 6 states. 33.77/12.80 [2019-03-28 12:22:07,708 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 33.77/12.80 [2019-03-28 12:22:07,708 INFO L93 Difference]: Finished difference Result 1209 states and 1833 transitions. 33.77/12.80 [2019-03-28 12:22:07,709 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. 33.77/12.80 [2019-03-28 12:22:07,709 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1209 states and 1833 transitions. 33.77/12.80 [2019-03-28 12:22:07,716 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1174 33.77/12.80 [2019-03-28 12:22:07,723 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1209 states to 1209 states and 1833 transitions. 33.77/12.80 [2019-03-28 12:22:07,723 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1209 33.77/12.80 [2019-03-28 12:22:07,724 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1209 33.77/12.80 [2019-03-28 12:22:07,724 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1209 states and 1833 transitions. 33.77/12.80 [2019-03-28 12:22:07,726 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 33.77/12.80 [2019-03-28 12:22:07,726 INFO L706 BuchiCegarLoop]: Abstraction has 1209 states and 1833 transitions. 33.77/12.80 [2019-03-28 12:22:07,727 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1209 states and 1833 transitions. 33.77/12.80 [2019-03-28 12:22:07,746 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1209 to 1126. 33.77/12.80 [2019-03-28 12:22:07,746 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1126 states. 33.77/12.80 [2019-03-28 12:22:07,749 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1126 states to 1126 states and 1716 transitions. 33.77/12.80 [2019-03-28 12:22:07,749 INFO L729 BuchiCegarLoop]: Abstraction has 1126 states and 1716 transitions. 33.77/12.80 [2019-03-28 12:22:07,749 INFO L609 BuchiCegarLoop]: Abstraction has 1126 states and 1716 transitions. 33.77/12.80 [2019-03-28 12:22:07,749 INFO L442 BuchiCegarLoop]: ======== Iteration 16============ 33.77/12.80 [2019-03-28 12:22:07,750 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1126 states and 1716 transitions. 33.77/12.80 [2019-03-28 12:22:07,754 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1094 33.77/12.80 [2019-03-28 12:22:07,754 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 33.77/12.80 [2019-03-28 12:22:07,754 INFO L119 BuchiIsEmpty]: Starting construction of run 33.77/12.80 [2019-03-28 12:22:07,755 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 33.77/12.80 [2019-03-28 12:22:07,755 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] 33.77/12.80 [2019-03-28 12:22:07,756 INFO L794 eck$LassoCheckResult]: Stem: 17618#ULTIMATE.startENTRY [1057] ULTIMATE.startENTRY-->L165: Formula: (and (= 0 v_~m_st~0_20) (= 2 v_~E_M~0_30) (= v_~t1_pc~0_18 0) (= 0 v_~t1_st~0_20) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 0 v_~token~0_8) (= v_~M_E~0_19 2) (= v_~local~0_6 0) (= v_~m_i~0_7 1) (= 2 v_~E_1~0_30) (= v_~m_pc~0_18 0) (= 1 v_~t1_i~0_7)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ~t1_st~0=v_~t1_st~0_20, ~t1_pc~0=v_~t1_pc~0_18, ~M_E~0=v_~M_E~0_19, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_#t~ret8=|v_ULTIMATE.start_start_simulation_#t~ret8_4|, ~token~0=v_~token~0_8, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~E_1~0=v_~E_1~0_30, ~E_M~0=v_~E_M~0_30, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~T1_E~0=v_~T1_E~0_18, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_20, ~m_pc~0=v_~m_pc~0_18, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ~t1_st~0, ~t1_pc~0, ~M_E~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_#t~ret8, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~E_1~0, ~E_M~0, ULTIMATE.start_main_#res, ~T1_E~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0, ULTIMATE.start_main_~__retres1~3] 17611#L165 [720] L165-->L172-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_3 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_3, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 17556#L172-1 [642] L172-1-->L177-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 17557#L177-1 [917] L177-1-->L261-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 17569#L261-1 [919] L261-1-->L266-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 17657#L266-1 [921] L266-1-->L271-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 17565#L271-1 [922] L271-1-->L276-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 17566#L276-1 [657] L276-1-->L126: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_3, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_4, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_1|, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_3|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_master_triggered_#res] 17572#L126 [924] L126-->L126-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 17629#L126-2 [746] L126-2-->L137: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 17630#L137 [1058] L137-->L321: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_16| v_ULTIMATE.start_activate_threads_~tmp~1_29) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_29 |v_ULTIMATE.start_is_master_triggered_#res_16|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_29, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_16|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 17529#L321 [611] L321-->L321-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_8) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8} AuxVars[] AssignedVars[] 17530#L321-2 [615] L321-2-->L145: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 17533#L145 [930] L145-->L145-2: Formula: (< v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 17658#L145-2 [783] L145-2-->L156: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 17659#L156 [1059] L156-->L329: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_29 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_29, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_16|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_transmit1_triggered_#res] 17536#L329 [618] L329-->L329-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_9) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} AuxVars[] AssignedVars[] 17537#L329-2 [937] L329-2-->L289-1: Formula: (> v_~M_E~0_10 1) InVars {~M_E~0=v_~M_E~0_10} OutVars{~M_E~0=v_~M_E~0_10} AuxVars[] AssignedVars[] 17542#L289-1 [939] L289-1-->L294-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 17619#L294-1 [940] L294-1-->L299-1: Formula: (< 1 v_~E_M~0_12) InVars {~E_M~0=v_~E_M~0_12} OutVars{~E_M~0=v_~E_M~0_12} AuxVars[] AssignedVars[] 17538#L299-1 [942] L299-1-->L430-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 17539#L430-1 [1060] L430-1-->L236: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 17726#L236 33.77/12.80 [2019-03-28 12:22:07,756 INFO L796 eck$LassoCheckResult]: Loop: 17726#L236 [1061] L236-->L190: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_22, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 17722#L190 [708] L190-->L202: Formula: (and (= v_~m_st~0_8 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11 1)) InVars {~m_st~0=v_~m_st~0_8} OutVars{~m_st~0=v_~m_st~0_8, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 17720#L202 [1062] L202-->L217: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 17719#L217 [954] L217-->L217-1: Formula: (> v_ULTIMATE.start_eval_~tmp~0_4 0) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} OutVars{ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} AuxVars[] AssignedVars[] 17717#L217-1 [769] L217-1-->L225: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_2 |v_ULTIMATE.start_eval_#t~nondet2_3|) (= 0 v_~m_st~0_10)) InVars {~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_3|} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_2|, ~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_1~0] 17715#L225 [817] L225-->L222: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} AuxVars[] AssignedVars[] 17716#L222 [962] L222-->L236: Formula: (> 0 v_~t1_st~0_15) InVars {~t1_st~0=v_~t1_st~0_15} OutVars{~t1_st~0=v_~t1_st~0_15} AuxVars[] AssignedVars[] 17726#L236 33.77/12.80 [2019-03-28 12:22:07,756 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 33.77/12.80 [2019-03-28 12:22:07,756 INFO L82 PathProgramCache]: Analyzing trace with hash 1801504368, now seen corresponding path program 1 times 33.77/12.80 [2019-03-28 12:22:07,758 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 33.77/12.80 [2019-03-28 12:22:07,758 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 33.77/12.80 [2019-03-28 12:22:07,759 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.80 [2019-03-28 12:22:07,759 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 33.77/12.80 [2019-03-28 12:22:07,759 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.80 [2019-03-28 12:22:07,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 33.77/12.80 [2019-03-28 12:22:07,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 33.77/12.80 [2019-03-28 12:22:07,771 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 33.77/12.80 [2019-03-28 12:22:07,772 INFO L82 PathProgramCache]: Analyzing trace with hash -1704021602, now seen corresponding path program 1 times 33.77/12.80 [2019-03-28 12:22:07,772 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 33.77/12.80 [2019-03-28 12:22:07,772 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 33.77/12.80 [2019-03-28 12:22:07,773 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.80 [2019-03-28 12:22:07,773 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 33.77/12.80 [2019-03-28 12:22:07,773 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.80 [2019-03-28 12:22:07,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 33.77/12.80 [2019-03-28 12:22:07,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 33.77/12.80 [2019-03-28 12:22:07,780 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 33.77/12.80 [2019-03-28 12:22:07,780 INFO L82 PathProgramCache]: Analyzing trace with hash -697982897, now seen corresponding path program 1 times 33.77/12.80 [2019-03-28 12:22:07,780 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 33.77/12.80 [2019-03-28 12:22:07,780 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 33.77/12.80 [2019-03-28 12:22:07,781 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.80 [2019-03-28 12:22:07,781 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 33.77/12.80 [2019-03-28 12:22:07,781 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.80 [2019-03-28 12:22:07,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 33.77/12.80 [2019-03-28 12:22:07,811 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 33.77/12.80 [2019-03-28 12:22:07,811 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 33.77/12.80 [2019-03-28 12:22:07,812 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 33.77/12.80 [2019-03-28 12:22:07,869 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 33.77/12.80 [2019-03-28 12:22:07,869 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 33.77/12.80 [2019-03-28 12:22:07,869 INFO L87 Difference]: Start difference. First operand 1126 states and 1716 transitions. cyclomatic complexity: 594 Second operand 3 states. 33.77/12.80 [2019-03-28 12:22:08,130 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 33.77/12.80 [2019-03-28 12:22:08,130 INFO L93 Difference]: Finished difference Result 1126 states and 1647 transitions. 33.77/12.80 [2019-03-28 12:22:08,131 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 33.77/12.80 [2019-03-28 12:22:08,131 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1126 states and 1647 transitions. 33.77/12.80 [2019-03-28 12:22:08,136 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1094 33.77/12.80 [2019-03-28 12:22:08,142 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1126 states to 1126 states and 1647 transitions. 33.77/12.80 [2019-03-28 12:22:08,142 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1126 33.77/12.80 [2019-03-28 12:22:08,143 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1126 33.77/12.80 [2019-03-28 12:22:08,143 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1126 states and 1647 transitions. 33.77/12.80 [2019-03-28 12:22:08,144 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 33.77/12.80 [2019-03-28 12:22:08,144 INFO L706 BuchiCegarLoop]: Abstraction has 1126 states and 1647 transitions. 33.77/12.80 [2019-03-28 12:22:08,145 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1126 states and 1647 transitions. 33.77/12.80 [2019-03-28 12:22:08,162 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1126 to 1126. 33.77/12.80 [2019-03-28 12:22:08,163 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1126 states. 33.77/12.80 [2019-03-28 12:22:08,166 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1126 states to 1126 states and 1647 transitions. 33.77/12.80 [2019-03-28 12:22:08,166 INFO L729 BuchiCegarLoop]: Abstraction has 1126 states and 1647 transitions. 33.77/12.80 [2019-03-28 12:22:08,166 INFO L609 BuchiCegarLoop]: Abstraction has 1126 states and 1647 transitions. 33.77/12.80 [2019-03-28 12:22:08,166 INFO L442 BuchiCegarLoop]: ======== Iteration 17============ 33.77/12.80 [2019-03-28 12:22:08,166 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1126 states and 1647 transitions. 33.77/12.80 [2019-03-28 12:22:08,169 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1094 33.77/12.80 [2019-03-28 12:22:08,169 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 33.77/12.80 [2019-03-28 12:22:08,169 INFO L119 BuchiIsEmpty]: Starting construction of run 33.77/12.80 [2019-03-28 12:22:08,170 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 33.77/12.80 [2019-03-28 12:22:08,170 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] 33.77/12.80 [2019-03-28 12:22:08,171 INFO L794 eck$LassoCheckResult]: Stem: 19870#ULTIMATE.startENTRY [1057] ULTIMATE.startENTRY-->L165: Formula: (and (= 0 v_~m_st~0_20) (= 2 v_~E_M~0_30) (= v_~t1_pc~0_18 0) (= 0 v_~t1_st~0_20) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 0 v_~token~0_8) (= v_~M_E~0_19 2) (= v_~local~0_6 0) (= v_~m_i~0_7 1) (= 2 v_~E_1~0_30) (= v_~m_pc~0_18 0) (= 1 v_~t1_i~0_7)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ~t1_st~0=v_~t1_st~0_20, ~t1_pc~0=v_~t1_pc~0_18, ~M_E~0=v_~M_E~0_19, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_#t~ret8=|v_ULTIMATE.start_start_simulation_#t~ret8_4|, ~token~0=v_~token~0_8, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~E_1~0=v_~E_1~0_30, ~E_M~0=v_~E_M~0_30, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~T1_E~0=v_~T1_E~0_18, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_20, ~m_pc~0=v_~m_pc~0_18, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ~t1_st~0, ~t1_pc~0, ~M_E~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_#t~ret8, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~E_1~0, ~E_M~0, ULTIMATE.start_main_#res, ~T1_E~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0, ULTIMATE.start_main_~__retres1~3] 19863#L165 [720] L165-->L172-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_3 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_3, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 19813#L172-1 [642] L172-1-->L177-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 19814#L177-1 [917] L177-1-->L261-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 19824#L261-1 [919] L261-1-->L266-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 19903#L266-1 [921] L266-1-->L271-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 19821#L271-1 [922] L271-1-->L276-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 19822#L276-1 [657] L276-1-->L126: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_3, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_4, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_1|, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_3|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_master_triggered_#res] 19826#L126 [924] L126-->L126-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 19880#L126-2 [746] L126-2-->L137: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 19881#L137 [1058] L137-->L321: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_16| v_ULTIMATE.start_activate_threads_~tmp~1_29) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_29 |v_ULTIMATE.start_is_master_triggered_#res_16|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_29, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_16|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 19787#L321 [611] L321-->L321-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_8) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8} AuxVars[] AssignedVars[] 19788#L321-2 [615] L321-2-->L145: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 19792#L145 [930] L145-->L145-2: Formula: (< v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 19904#L145-2 [783] L145-2-->L156: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 19905#L156 [1059] L156-->L329: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_29 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_29, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_16|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_transmit1_triggered_#res] 19793#L329 [618] L329-->L329-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_9) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} AuxVars[] AssignedVars[] 19794#L329-2 [937] L329-2-->L289-1: Formula: (> v_~M_E~0_10 1) InVars {~M_E~0=v_~M_E~0_10} OutVars{~M_E~0=v_~M_E~0_10} AuxVars[] AssignedVars[] 19801#L289-1 [939] L289-1-->L294-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 19871#L294-1 [940] L294-1-->L299-1: Formula: (< 1 v_~E_M~0_12) InVars {~E_M~0=v_~E_M~0_12} OutVars{~E_M~0=v_~E_M~0_12} AuxVars[] AssignedVars[] 19795#L299-1 [942] L299-1-->L430-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 19796#L430-1 [1060] L430-1-->L236: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 19957#L236 33.77/12.80 [2019-03-28 12:22:08,171 INFO L796 eck$LassoCheckResult]: Loop: 19957#L236 [1061] L236-->L190: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_22, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 19954#L190 [708] L190-->L202: Formula: (and (= v_~m_st~0_8 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11 1)) InVars {~m_st~0=v_~m_st~0_8} OutVars{~m_st~0=v_~m_st~0_8, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 19953#L202 [1062] L202-->L217: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 19952#L217 [954] L217-->L217-1: Formula: (> v_ULTIMATE.start_eval_~tmp~0_4 0) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} OutVars{ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} AuxVars[] AssignedVars[] 19949#L217-1 [769] L217-1-->L225: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_2 |v_ULTIMATE.start_eval_#t~nondet2_3|) (= 0 v_~m_st~0_10)) InVars {~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_3|} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_2|, ~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_1~0] 19947#L225 [817] L225-->L222: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} AuxVars[] AssignedVars[] 19948#L222 [963] L222-->L236: Formula: (< 0 v_~t1_st~0_15) InVars {~t1_st~0=v_~t1_st~0_15} OutVars{~t1_st~0=v_~t1_st~0_15} AuxVars[] AssignedVars[] 19957#L236 33.77/12.80 [2019-03-28 12:22:08,171 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 33.77/12.80 [2019-03-28 12:22:08,171 INFO L82 PathProgramCache]: Analyzing trace with hash 1801504368, now seen corresponding path program 2 times 33.77/12.80 [2019-03-28 12:22:08,171 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 33.77/12.80 [2019-03-28 12:22:08,172 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 33.77/12.80 [2019-03-28 12:22:08,172 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.80 [2019-03-28 12:22:08,172 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 33.77/12.80 [2019-03-28 12:22:08,173 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.80 [2019-03-28 12:22:08,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 33.77/12.80 [2019-03-28 12:22:08,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 33.77/12.80 [2019-03-28 12:22:08,184 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 33.77/12.80 [2019-03-28 12:22:08,184 INFO L82 PathProgramCache]: Analyzing trace with hash -1704021601, now seen corresponding path program 1 times 33.77/12.80 [2019-03-28 12:22:08,185 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 33.77/12.80 [2019-03-28 12:22:08,185 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 33.77/12.80 [2019-03-28 12:22:08,185 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.80 [2019-03-28 12:22:08,186 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 33.77/12.80 [2019-03-28 12:22:08,186 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.80 [2019-03-28 12:22:08,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 33.77/12.80 [2019-03-28 12:22:08,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 33.77/12.80 [2019-03-28 12:22:08,192 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 33.77/12.80 [2019-03-28 12:22:08,192 INFO L82 PathProgramCache]: Analyzing trace with hash -697982896, now seen corresponding path program 1 times 33.77/12.80 [2019-03-28 12:22:08,192 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 33.77/12.80 [2019-03-28 12:22:08,192 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 33.77/12.80 [2019-03-28 12:22:08,193 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.80 [2019-03-28 12:22:08,193 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 33.77/12.80 [2019-03-28 12:22:08,193 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.80 [2019-03-28 12:22:08,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 33.77/12.80 [2019-03-28 12:22:08,212 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 33.77/12.80 [2019-03-28 12:22:08,213 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 33.77/12.80 [2019-03-28 12:22:08,213 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 33.77/12.80 [2019-03-28 12:22:08,298 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 33.77/12.80 [2019-03-28 12:22:08,298 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 33.77/12.80 [2019-03-28 12:22:08,298 INFO L87 Difference]: Start difference. First operand 1126 states and 1647 transitions. cyclomatic complexity: 525 Second operand 3 states. 33.77/12.80 [2019-03-28 12:22:08,654 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 33.77/12.80 [2019-03-28 12:22:08,654 INFO L93 Difference]: Finished difference Result 1684 states and 2390 transitions. 33.77/12.80 [2019-03-28 12:22:08,654 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 33.77/12.80 [2019-03-28 12:22:08,655 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1684 states and 2390 transitions. 33.77/12.80 [2019-03-28 12:22:08,662 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1648 33.77/12.80 [2019-03-28 12:22:08,671 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1684 states to 1684 states and 2390 transitions. 33.77/12.80 [2019-03-28 12:22:08,672 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1684 33.77/12.80 [2019-03-28 12:22:08,673 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1684 33.77/12.80 [2019-03-28 12:22:08,673 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1684 states and 2390 transitions. 33.77/12.80 [2019-03-28 12:22:08,675 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 33.77/12.80 [2019-03-28 12:22:08,675 INFO L706 BuchiCegarLoop]: Abstraction has 1684 states and 2390 transitions. 33.77/12.80 [2019-03-28 12:22:08,677 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1684 states and 2390 transitions. 33.77/12.80 [2019-03-28 12:22:08,705 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1684 to 1660. 33.77/12.80 [2019-03-28 12:22:08,706 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1660 states. 33.77/12.80 [2019-03-28 12:22:08,710 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1660 states to 1660 states and 2366 transitions. 33.77/12.80 [2019-03-28 12:22:08,710 INFO L729 BuchiCegarLoop]: Abstraction has 1660 states and 2366 transitions. 33.77/12.80 [2019-03-28 12:22:08,710 INFO L609 BuchiCegarLoop]: Abstraction has 1660 states and 2366 transitions. 33.77/12.80 [2019-03-28 12:22:08,711 INFO L442 BuchiCegarLoop]: ======== Iteration 18============ 33.77/12.80 [2019-03-28 12:22:08,711 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1660 states and 2366 transitions. 33.77/12.80 [2019-03-28 12:22:08,715 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1624 33.77/12.80 [2019-03-28 12:22:08,716 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 33.77/12.80 [2019-03-28 12:22:08,716 INFO L119 BuchiIsEmpty]: Starting construction of run 33.77/12.80 [2019-03-28 12:22:08,716 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 33.77/12.80 [2019-03-28 12:22:08,716 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] 33.77/12.80 [2019-03-28 12:22:08,717 INFO L794 eck$LassoCheckResult]: Stem: 22691#ULTIMATE.startENTRY [1057] ULTIMATE.startENTRY-->L165: Formula: (and (= 0 v_~m_st~0_20) (= 2 v_~E_M~0_30) (= v_~t1_pc~0_18 0) (= 0 v_~t1_st~0_20) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 0 v_~token~0_8) (= v_~M_E~0_19 2) (= v_~local~0_6 0) (= v_~m_i~0_7 1) (= 2 v_~E_1~0_30) (= v_~m_pc~0_18 0) (= 1 v_~t1_i~0_7)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ~t1_st~0=v_~t1_st~0_20, ~t1_pc~0=v_~t1_pc~0_18, ~M_E~0=v_~M_E~0_19, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_#t~ret8=|v_ULTIMATE.start_start_simulation_#t~ret8_4|, ~token~0=v_~token~0_8, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~E_1~0=v_~E_1~0_30, ~E_M~0=v_~E_M~0_30, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~T1_E~0=v_~T1_E~0_18, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_20, ~m_pc~0=v_~m_pc~0_18, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ~t1_st~0, ~t1_pc~0, ~M_E~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_#t~ret8, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~E_1~0, ~E_M~0, ULTIMATE.start_main_#res, ~T1_E~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0, ULTIMATE.start_main_~__retres1~3] 22686#L165 [720] L165-->L172-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_3 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_3, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 22633#L172-1 [642] L172-1-->L177-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 22634#L177-1 [917] L177-1-->L261-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 22644#L261-1 [919] L261-1-->L266-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 22729#L266-1 [921] L266-1-->L271-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 22640#L271-1 [922] L271-1-->L276-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 22641#L276-1 [657] L276-1-->L126: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_3, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_4, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_1|, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_3|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_master_triggered_#res] 22647#L126 [924] L126-->L126-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 22703#L126-2 [746] L126-2-->L137: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 22704#L137 [1058] L137-->L321: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_16| v_ULTIMATE.start_activate_threads_~tmp~1_29) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_29 |v_ULTIMATE.start_is_master_triggered_#res_16|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_29, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_16|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 22605#L321 [611] L321-->L321-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_8) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8} AuxVars[] AssignedVars[] 22606#L321-2 [615] L321-2-->L145: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 22611#L145 [930] L145-->L145-2: Formula: (< v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 22730#L145-2 [783] L145-2-->L156: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 22731#L156 [1059] L156-->L329: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_29 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_31, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_29, ULTIMATE.start_activate_threads_#t~ret5=|v_ULTIMATE.start_activate_threads_#t~ret5_16|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret5, ULTIMATE.start_is_transmit1_triggered_#res] 22612#L329 [618] L329-->L329-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_9) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} AuxVars[] AssignedVars[] 22613#L329-2 [937] L329-2-->L289-1: Formula: (> v_~M_E~0_10 1) InVars {~M_E~0=v_~M_E~0_10} OutVars{~M_E~0=v_~M_E~0_10} AuxVars[] AssignedVars[] 22620#L289-1 [939] L289-1-->L294-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 22692#L294-1 [940] L294-1-->L299-1: Formula: (< 1 v_~E_M~0_12) InVars {~E_M~0=v_~E_M~0_12} OutVars{~E_M~0=v_~E_M~0_12} AuxVars[] AssignedVars[] 22614#L299-1 [942] L299-1-->L430-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 22615#L430-1 [1060] L430-1-->L236: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 22796#L236 33.77/12.80 [2019-03-28 12:22:08,717 INFO L796 eck$LassoCheckResult]: Loop: 22796#L236 [1061] L236-->L190: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_22, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 22793#L190 [708] L190-->L202: Formula: (and (= v_~m_st~0_8 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11 1)) InVars {~m_st~0=v_~m_st~0_8} OutVars{~m_st~0=v_~m_st~0_8, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 22792#L202 [1062] L202-->L217: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 22791#L217 [954] L217-->L217-1: Formula: (> v_ULTIMATE.start_eval_~tmp~0_4 0) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} OutVars{ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} AuxVars[] AssignedVars[] 22788#L217-1 [769] L217-1-->L225: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_2 |v_ULTIMATE.start_eval_#t~nondet2_3|) (= 0 v_~m_st~0_10)) InVars {~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_3|} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_2|, ~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_1~0] 22786#L225 [817] L225-->L222: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} AuxVars[] AssignedVars[] 22787#L222 [799] L222-->L239: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_2 |v_ULTIMATE.start_eval_#t~nondet3_3|) (= 0 v_~t1_st~0_11)) InVars {ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_3|, ~t1_st~0=v_~t1_st~0_11} OutVars{ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_2|, ~t1_st~0=v_~t1_st~0_11, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_~tmp_ndt_2~0] 22797#L239 [732] L239-->L236: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} AuxVars[] AssignedVars[] 22796#L236 33.77/12.80 [2019-03-28 12:22:08,718 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 33.77/12.80 [2019-03-28 12:22:08,718 INFO L82 PathProgramCache]: Analyzing trace with hash 1801504368, now seen corresponding path program 3 times 33.77/12.80 [2019-03-28 12:22:08,718 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 33.77/12.80 [2019-03-28 12:22:08,718 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 33.77/12.80 [2019-03-28 12:22:08,719 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.80 [2019-03-28 12:22:08,719 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 33.77/12.80 [2019-03-28 12:22:08,719 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.80 [2019-03-28 12:22:08,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 33.77/12.80 [2019-03-28 12:22:08,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 33.77/12.80 [2019-03-28 12:22:08,730 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 33.77/12.80 [2019-03-28 12:22:08,731 INFO L82 PathProgramCache]: Analyzing trace with hash -1285066431, now seen corresponding path program 1 times 33.77/12.80 [2019-03-28 12:22:08,731 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 33.77/12.80 [2019-03-28 12:22:08,731 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 33.77/12.80 [2019-03-28 12:22:08,732 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.80 [2019-03-28 12:22:08,732 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 33.77/12.80 [2019-03-28 12:22:08,732 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.80 [2019-03-28 12:22:08,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 33.77/12.80 [2019-03-28 12:22:08,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 33.77/12.80 [2019-03-28 12:22:08,738 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 33.77/12.80 [2019-03-28 12:22:08,738 INFO L82 PathProgramCache]: Analyzing trace with hash -162637648, now seen corresponding path program 1 times 33.77/12.80 [2019-03-28 12:22:08,738 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 33.77/12.80 [2019-03-28 12:22:08,738 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 33.77/12.80 [2019-03-28 12:22:08,739 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.80 [2019-03-28 12:22:08,739 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 33.77/12.80 [2019-03-28 12:22:08,739 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 33.77/12.80 [2019-03-28 12:22:08,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 33.77/12.80 [2019-03-28 12:22:08,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 33.77/12.80 [2019-03-28 12:22:08,962 WARN L188 SmtUtils]: Spent 136.00 ms on a formula simplification. DAG size of input: 60 DAG size of output: 48 33.77/12.80 [2019-03-28 12:22:09,045 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 28.03 12:22:09 BasicIcfg 33.77/12.80 [2019-03-28 12:22:09,046 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- 33.77/12.80 [2019-03-28 12:22:09,046 INFO L168 Benchmark]: Toolchain (without parser) took 8237.21 ms. Allocated memory was 649.6 MB in the beginning and 853.5 MB in the end (delta: 203.9 MB). Free memory was 564.9 MB in the beginning and 450.5 MB in the end (delta: 114.4 MB). Peak memory consumption was 318.3 MB. Max. memory is 50.3 GB. 33.77/12.80 [2019-03-28 12:22:09,047 INFO L168 Benchmark]: CDTParser took 0.18 ms. Allocated memory is still 649.6 MB. Free memory is still 591.9 MB. There was no memory consumed. Max. memory is 50.3 GB. 33.77/12.80 [2019-03-28 12:22:09,048 INFO L168 Benchmark]: CACSL2BoogieTranslator took 371.07 ms. Allocated memory was 649.6 MB in the beginning and 684.7 MB in the end (delta: 35.1 MB). Free memory was 564.9 MB in the beginning and 647.7 MB in the end (delta: -82.8 MB). Peak memory consumption was 32.8 MB. Max. memory is 50.3 GB. 33.77/12.80 [2019-03-28 12:22:09,048 INFO L168 Benchmark]: Boogie Procedure Inliner took 53.81 ms. Allocated memory is still 684.7 MB. Free memory was 647.7 MB in the beginning and 643.6 MB in the end (delta: 4.1 MB). Peak memory consumption was 4.1 MB. Max. memory is 50.3 GB. 33.77/12.80 [2019-03-28 12:22:09,049 INFO L168 Benchmark]: Boogie Preprocessor took 38.19 ms. Allocated memory is still 684.7 MB. Free memory was 643.6 MB in the beginning and 640.9 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 50.3 GB. 33.77/12.80 [2019-03-28 12:22:09,050 INFO L168 Benchmark]: RCFGBuilder took 604.55 ms. Allocated memory is still 684.7 MB. Free memory was 640.9 MB in the beginning and 594.5 MB in the end (delta: 46.4 MB). Peak memory consumption was 46.4 MB. Max. memory is 50.3 GB. 33.77/12.80 [2019-03-28 12:22:09,050 INFO L168 Benchmark]: BlockEncodingV2 took 198.55 ms. Allocated memory is still 684.7 MB. Free memory was 594.5 MB in the beginning and 574.2 MB in the end (delta: 20.2 MB). Peak memory consumption was 20.2 MB. Max. memory is 50.3 GB. 33.77/12.80 [2019-03-28 12:22:09,051 INFO L168 Benchmark]: TraceAbstraction took 233.35 ms. Allocated memory is still 684.7 MB. Free memory was 572.9 MB in the beginning and 549.9 MB in the end (delta: 23.0 MB). Peak memory consumption was 23.0 MB. Max. memory is 50.3 GB. 33.77/12.80 [2019-03-28 12:22:09,051 INFO L168 Benchmark]: BuchiAutomizer took 6732.36 ms. Allocated memory was 684.7 MB in the beginning and 853.5 MB in the end (delta: 168.8 MB). Free memory was 549.9 MB in the beginning and 450.5 MB in the end (delta: 99.4 MB). Peak memory consumption was 268.2 MB. Max. memory is 50.3 GB. 33.77/12.80 [2019-03-28 12:22:09,056 INFO L337 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### 33.77/12.80 --- Results --- 33.77/12.80 * Results from de.uni_freiburg.informatik.ultimate.plugins.blockencoding: 33.77/12.80 - StatisticsResult: Initial Icfg 33.77/12.80 146 locations, 229 edges 33.77/12.80 - StatisticsResult: Encoded RCFG 33.77/12.80 114 locations, 257 edges 33.77/12.80 * Results from de.uni_freiburg.informatik.ultimate.core: 33.77/12.80 - StatisticsResult: Toolchain Benchmarks 33.77/12.80 Benchmark results are: 33.77/12.80 * CDTParser took 0.18 ms. Allocated memory is still 649.6 MB. Free memory is still 591.9 MB. There was no memory consumed. Max. memory is 50.3 GB. 33.77/12.80 * CACSL2BoogieTranslator took 371.07 ms. Allocated memory was 649.6 MB in the beginning and 684.7 MB in the end (delta: 35.1 MB). Free memory was 564.9 MB in the beginning and 647.7 MB in the end (delta: -82.8 MB). Peak memory consumption was 32.8 MB. Max. memory is 50.3 GB. 33.77/12.80 * Boogie Procedure Inliner took 53.81 ms. Allocated memory is still 684.7 MB. Free memory was 647.7 MB in the beginning and 643.6 MB in the end (delta: 4.1 MB). Peak memory consumption was 4.1 MB. Max. memory is 50.3 GB. 33.77/12.80 * Boogie Preprocessor took 38.19 ms. Allocated memory is still 684.7 MB. Free memory was 643.6 MB in the beginning and 640.9 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 50.3 GB. 33.77/12.80 * RCFGBuilder took 604.55 ms. Allocated memory is still 684.7 MB. Free memory was 640.9 MB in the beginning and 594.5 MB in the end (delta: 46.4 MB). Peak memory consumption was 46.4 MB. Max. memory is 50.3 GB. 33.77/12.80 * BlockEncodingV2 took 198.55 ms. Allocated memory is still 684.7 MB. Free memory was 594.5 MB in the beginning and 574.2 MB in the end (delta: 20.2 MB). Peak memory consumption was 20.2 MB. Max. memory is 50.3 GB. 33.77/12.80 * TraceAbstraction took 233.35 ms. Allocated memory is still 684.7 MB. Free memory was 572.9 MB in the beginning and 549.9 MB in the end (delta: 23.0 MB). Peak memory consumption was 23.0 MB. Max. memory is 50.3 GB. 33.77/12.80 * BuchiAutomizer took 6732.36 ms. Allocated memory was 684.7 MB in the beginning and 853.5 MB in the end (delta: 168.8 MB). Free memory was 549.9 MB in the beginning and 450.5 MB in the end (delta: 99.4 MB). Peak memory consumption was 268.2 MB. Max. memory is 50.3 GB. 33.77/12.80 * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: 33.77/12.80 - AllSpecificationsHoldResult: All specifications hold 33.77/12.80 We were not able to verify any specifiation because the program does not contain any specification. 33.77/12.80 - InvariantResult [Line: 1]: Loop Invariant 33.77/12.80 Derived loop invariant: 1 33.77/12.80 - InvariantResult [Line: 125]: Loop Invariant 33.77/12.80 Derived loop invariant: 1 33.77/12.80 - InvariantResult [Line: 261]: Loop Invariant 33.77/12.80 Derived loop invariant: 1 33.77/12.80 - InvariantResult [Line: 125]: Loop Invariant 33.77/12.80 Derived loop invariant: 1 33.77/12.80 - InvariantResult [Line: 257]: Loop Invariant 33.77/12.80 Derived loop invariant: 1 33.77/12.80 - InvariantResult [Line: 125]: Loop Invariant 33.77/12.80 Derived loop invariant: 1 33.77/12.80 - InvariantResult [Line: 1]: Loop Invariant 33.77/12.80 Derived loop invariant: 1 33.77/12.80 - InvariantResult [Line: 449]: Loop Invariant 33.77/12.80 Derived loop invariant: 1 33.77/12.80 - InvariantResult [Line: 93]: Loop Invariant 33.77/12.80 Derived loop invariant: 1 33.77/12.80 - InvariantResult [Line: 125]: Loop Invariant 33.77/12.80 Derived loop invariant: 1 33.77/12.80 - InvariantResult [Line: 257]: Loop Invariant 33.77/12.80 Derived loop invariant: 1 33.77/12.80 - InvariantResult [Line: 449]: Loop Invariant 33.77/12.80 Derived loop invariant: 1 33.77/12.80 - InvariantResult [Line: 125]: Loop Invariant 33.77/12.80 Derived loop invariant: 1 33.77/12.80 - InvariantResult [Line: 189]: Loop Invariant 33.77/12.80 Derived loop invariant: 1 33.77/12.80 - InvariantResult [Line: 289]: Loop Invariant 33.77/12.80 Derived loop invariant: 1 33.77/12.80 - InvariantResult [Line: 400]: Loop Invariant 33.77/12.80 Derived loop invariant: 1 33.77/12.80 - InvariantResult [Line: 217]: Loop Invariant 33.77/12.80 Derived loop invariant: 1 33.77/12.80 - InvariantResult [Line: 144]: Loop Invariant 33.77/12.80 Derived loop invariant: 1 33.77/12.80 - InvariantResult [Line: 172]: Loop Invariant 33.77/12.80 Derived loop invariant: 1 33.77/12.80 - InvariantResult [Line: 37]: Loop Invariant 33.77/12.80 Derived loop invariant: 1 33.77/12.80 - InvariantResult [Line: 144]: Loop Invariant 33.77/12.80 Derived loop invariant: 1 33.77/12.80 - InvariantResult [Line: 33]: Loop Invariant 33.77/12.80 Derived loop invariant: 1 33.77/12.80 - InvariantResult [Line: 285]: Loop Invariant 33.77/12.80 Derived loop invariant: 1 33.77/12.80 - InvariantResult [Line: 285]: Loop Invariant 33.77/12.80 Derived loop invariant: 1 33.77/12.80 - InvariantResult [Line: 144]: Loop Invariant 33.77/12.80 Derived loop invariant: 1 33.77/12.80 - InvariantResult [Line: 189]: Loop Invariant 33.77/12.80 Derived loop invariant: 1 33.77/12.80 - InvariantResult [Line: 212]: Loop Invariant 33.77/12.80 Derived loop invariant: 1 33.77/12.80 - InvariantResult [Line: 189]: Loop Invariant 33.77/12.80 Derived loop invariant: 1 33.77/12.80 - InvariantResult [Line: 289]: Loop Invariant 33.77/12.80 Derived loop invariant: 1 33.77/12.80 - InvariantResult [Line: -1]: Loop Invariant 33.77/12.80 Derived loop invariant: 1 33.77/12.80 - InvariantResult [Line: 212]: Loop Invariant 33.77/12.80 Derived loop invariant: 1 33.77/12.80 - InvariantResult [Line: 144]: Loop Invariant 33.77/12.80 Derived loop invariant: 1 33.77/12.80 - InvariantResult [Line: 362]: Loop Invariant 33.77/12.80 Derived loop invariant: 1 33.77/12.80 - InvariantResult [Line: 144]: Loop Invariant 33.77/12.80 Derived loop invariant: 1 33.77/12.80 - InvariantResult [Line: 89]: Loop Invariant 33.77/12.80 Derived loop invariant: 1 33.77/12.80 - StatisticsResult: Ultimate Automizer benchmark data 33.77/12.80 CFG has 1 procedures, 114 locations, 0 error locations. SAFE Result, 0.1s OverallTime, 0 OverallIterations, 0 TraceHistogramMax, 0.0s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: No data available, PredicateUnifierStatistics: No data available, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=114occurred in iteration=0, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: No data available, HoareAnnotationStatistics: 0.0s HoareAnnotationTime, 35 LocationsWithAnnotation, 35 PreInvPairs, 35 NumberOfFragments, 35 HoareAnnotationTreeSize, 35 FomulaSimplifications, 0 FormulaSimplificationTreeSizeReduction, 0.0s HoareSimplificationTime, 35 FomulaSimplificationsInter, 0 FormulaSimplificationTreeSizeReductionInter, 0.0s HoareSimplificationTimeInter, RefinementEngineStatistics: No data available, ReuseStatistics: No data available 33.77/12.80 - StatisticsResult: Constructed decomposition of program 33.77/12.80 Your program was decomposed into 17 terminating modules (17 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.17 modules have a trivial ranking function, the largest among these consists of 6 locations. The remainder module has 1660 locations. 33.77/12.80 - StatisticsResult: Timing statistics 33.77/12.80 BüchiAutomizer plugin needed 6.6s and 18 iterations. TraceHistogramMax:1. Analysis of lassos took 1.4s. Construction of modules took 3.1s. Büchi inclusion checks took 1.3s. Highest rank in rank-based complementation 0. Minimization of det autom 17. Minimization of nondet autom 0. Automata minimization 0.2s AutomataMinimizationTime, 17 MinimizatonAttempts, 2284 StatesRemovedByMinimization, 9 NontrivialMinimizations. Non-live state removal took 0.1s Buchi closure took 0.0s. Biggest automaton had 1660 states and ocurred in iteration 17. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 1804 SDtfs, 4285 SDslu, 2201 SDs, 0 SdLazy, 3845 SolverSat, 213 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 3.1s Time LassoAnalysisResults: nont1 unkn0 SFLI5 SFLT0 conc2 concLT0 SILN0 SILU0 SILI10 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s 33.77/12.80 - TerminationAnalysisResult: Nontermination possible 33.77/12.80 Buchi Automizer proved that your program is nonterminating for some inputs 33.77/12.80 - FixpointNonTerminationResult [Line: 212]: Nontermination argument in form of an infinite program execution. 33.77/12.80 Nontermination argument in form of an infinite execution 33.77/12.80 State at position 0 is 33.77/12.80 {} 33.77/12.80 State at position 1 is 33.77/12.80 {\result=0, token=0, __retres1=0, tmp=1, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3a54e2a9=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2d3f4098=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@790a1ee1=0, kernel_st=1, __retres1=0, tmp___0=0, t1_pc=0, __retres1=1, T1_E=2, \result=0, E_1=2, tmp_ndt_1=0, M_E=2, tmp_ndt_2=0, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@799dba6d=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@51fae7f3=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@54aba238=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@42573c0e=0, t1_st=0, local=0, m_st=0, E_M=2, tmp___0=0, tmp=0, __retres1=0, t1_i=1, m_pc=0, \result=1} 33.77/12.80 - StatisticsResult: NonterminationArgumentStatistics 33.77/12.80 Fixpoint 33.77/12.80 - NonterminatingLassoResult [Line: 212]: Nonterminating execution 33.77/12.80 Found a nonterminating execution for the following lasso shaped sequence of statements. 33.77/12.80 Stem: 33.77/12.80 [L14] int m_pc = 0; 33.77/12.80 [L15] int t1_pc = 0; 33.77/12.80 [L16] int m_st ; 33.77/12.80 [L17] int t1_st ; 33.77/12.80 [L18] int m_i ; 33.77/12.80 [L19] int t1_i ; 33.77/12.80 [L20] int M_E = 2; 33.77/12.80 [L21] int T1_E = 2; 33.77/12.80 [L22] int E_M = 2; 33.77/12.80 [L23] int E_1 = 2; 33.77/12.80 [L27] int token ; 33.77/12.80 [L29] int local ; 33.77/12.80 [L475] int __retres1 ; 33.77/12.80 [L390] m_i = 1 33.77/12.80 [L391] t1_i = 1 33.77/12.80 [L416] int kernel_st ; 33.77/12.80 [L417] int tmp ; 33.77/12.80 [L418] int tmp___0 ; 33.77/12.80 [L422] kernel_st = 0 33.77/12.80 [L172] COND TRUE m_i == 1 33.77/12.80 [L173] m_st = 0 33.77/12.80 [L177] COND TRUE t1_i == 1 33.77/12.80 [L178] t1_st = 0 33.77/12.80 [L261] COND FALSE !(M_E == 0) 33.77/12.80 [L266] COND FALSE !(T1_E == 0) 33.77/12.80 [L271] COND FALSE !(E_M == 0) 33.77/12.80 [L276] COND FALSE !(E_1 == 0) 33.77/12.80 [L314] int tmp ; 33.77/12.80 [L315] int tmp___0 ; 33.77/12.80 [L123] int __retres1 ; 33.77/12.80 [L126] COND FALSE !(m_pc == 1) 33.77/12.80 [L136] __retres1 = 0 33.77/12.80 [L138] return (__retres1); 33.77/12.80 [L319] tmp = is_master_triggered() 33.77/12.80 [L321] COND FALSE !(\read(tmp)) 33.77/12.80 [L142] int __retres1 ; 33.77/12.80 [L145] COND FALSE !(t1_pc == 1) 33.77/12.80 [L155] __retres1 = 0 33.77/12.80 [L157] return (__retres1); 33.77/12.80 [L327] tmp___0 = is_transmit1_triggered() 33.77/12.80 [L329] COND FALSE !(\read(tmp___0)) 33.77/12.80 [L289] COND FALSE !(M_E == 1) 33.77/12.80 [L294] COND FALSE !(T1_E == 1) 33.77/12.80 [L299] COND FALSE !(E_M == 1) 33.77/12.80 [L304] COND FALSE !(E_1 == 1) 33.77/12.80 [L430] COND TRUE 1 33.77/12.80 [L433] kernel_st = 1 33.77/12.80 [L208] int tmp ; 33.77/12.80 Loop: 33.77/12.80 [L212] COND TRUE 1 33.77/12.80 [L187] int __retres1 ; 33.77/12.80 [L190] COND TRUE m_st == 0 33.77/12.80 [L191] __retres1 = 1 33.77/12.80 [L203] return (__retres1); 33.77/12.80 [L215] tmp = exists_runnable_thread() 33.77/12.80 [L217] COND TRUE \read(tmp) 33.77/12.80 [L222] COND TRUE m_st == 0 33.77/12.80 [L223] int tmp_ndt_1; 33.77/12.80 [L224] tmp_ndt_1 = __VERIFIER_nondet_int() 33.77/12.80 [L225] COND FALSE !(\read(tmp_ndt_1)) 33.77/12.80 [L236] COND TRUE t1_st == 0 33.77/12.80 [L237] int tmp_ndt_2; 33.77/12.80 [L238] tmp_ndt_2 = __VERIFIER_nondet_int() 33.77/12.80 [L239] COND FALSE !(\read(tmp_ndt_2)) 33.77/12.80 End of lasso representation. 33.77/12.80 RESULT: Ultimate proved your program to be incorrect! 33.77/12.80 !SESSION 2019-03-28 12:21:57.418 ----------------------------------------------- 33.77/12.80 eclipse.buildId=unknown 33.77/12.80 java.version=1.8.0_181 33.77/12.80 java.vendor=Oracle Corporation 33.77/12.80 BootLoader constants: OS=linux, ARCH=x86_64, WS=gtk, NL=en_US 33.77/12.80 Framework arguments: -tc ./../AutomizerAndBuchiAutomizerCInlineWithBlockEncoding.xml -s ./../termcomp2017.epf -i /export/starexec/sandbox/benchmark/theBenchmark.c 33.77/12.80 Command-line arguments: -os linux -ws gtk -arch x86_64 -consoleLog -data @user.home/.ultimate -tc ./../AutomizerAndBuchiAutomizerCInlineWithBlockEncoding.xml -s ./../termcomp2017.epf -data /export/starexec/sandbox/tmp -i /export/starexec/sandbox/benchmark/theBenchmark.c 33.77/12.80 33.77/12.80 !ENTRY org.eclipse.core.resources 2 10035 2019-03-28 12:22:09.304 33.77/12.80 !MESSAGE The workspace will exit with unsaved changes in this session. 33.77/12.80 Received shutdown request... 33.77/12.80 Ultimate: 33.77/12.80 GTK+ Version Check 33.77/12.80 EOF