312.69/160.47 NO 312.69/160.47 312.69/160.47 Ultimate: Cannot open display: 312.69/160.47 This is Ultimate 0.1.24-8dc7c08-m 312.69/160.47 [2019-03-28 12:21:46,951 INFO L170 SettingsManager]: Resetting all preferences to default values... 312.69/160.47 [2019-03-28 12:21:46,953 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values 312.69/160.47 [2019-03-28 12:21:46,965 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... 312.69/160.47 [2019-03-28 12:21:46,966 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values 312.69/160.47 [2019-03-28 12:21:46,966 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values 312.69/160.47 [2019-03-28 12:21:46,968 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values 312.69/160.47 [2019-03-28 12:21:46,969 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values 312.69/160.47 [2019-03-28 12:21:46,971 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values 312.69/160.47 [2019-03-28 12:21:46,972 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values 312.69/160.47 [2019-03-28 12:21:46,972 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... 312.69/160.47 [2019-03-28 12:21:46,973 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values 312.69/160.47 [2019-03-28 12:21:46,974 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values 312.69/160.47 [2019-03-28 12:21:46,974 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values 312.69/160.47 [2019-03-28 12:21:46,976 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values 312.69/160.47 [2019-03-28 12:21:46,976 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values 312.69/160.47 [2019-03-28 12:21:46,977 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values 312.69/160.47 [2019-03-28 12:21:46,979 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values 312.69/160.47 [2019-03-28 12:21:46,981 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values 312.69/160.47 [2019-03-28 12:21:46,983 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values 312.69/160.47 [2019-03-28 12:21:46,984 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values 312.69/160.47 [2019-03-28 12:21:46,985 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values 312.69/160.47 [2019-03-28 12:21:46,987 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 312.69/160.47 [2019-03-28 12:21:46,987 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... 312.69/160.47 [2019-03-28 12:21:46,987 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values 312.69/160.47 [2019-03-28 12:21:46,988 INFO L174 SettingsManager]: Resetting IcfgToChc preferences to default values 312.69/160.47 [2019-03-28 12:21:46,989 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values 312.69/160.47 [2019-03-28 12:21:46,989 INFO L177 SettingsManager]: ReqToTest provides no preferences, ignoring... 312.69/160.47 [2019-03-28 12:21:46,990 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values 312.69/160.47 [2019-03-28 12:21:46,990 INFO L174 SettingsManager]: Resetting ChcSmtPrinter preferences to default values 312.69/160.47 [2019-03-28 12:21:46,991 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values 312.69/160.47 [2019-03-28 12:21:46,992 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values 312.69/160.47 [2019-03-28 12:21:46,993 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... 312.69/160.47 [2019-03-28 12:21:46,993 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values 312.69/160.47 [2019-03-28 12:21:46,994 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... 312.69/160.47 [2019-03-28 12:21:46,994 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... 312.69/160.47 [2019-03-28 12:21:46,994 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values 312.69/160.47 [2019-03-28 12:21:46,995 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values 312.69/160.47 [2019-03-28 12:21:46,996 INFO L181 SettingsManager]: Finished resetting all preferences to default values... 312.69/160.47 [2019-03-28 12:21:46,997 INFO L98 SettingsManager]: Beginning loading settings from /export/starexec/sandbox2/solver/bin/./../termcomp2017.epf 312.69/160.47 [2019-03-28 12:21:47,012 INFO L110 SettingsManager]: Loading preferences was successful 312.69/160.47 [2019-03-28 12:21:47,012 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: 312.69/160.47 [2019-03-28 12:21:47,013 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: 312.69/160.47 [2019-03-28 12:21:47,013 INFO L133 SettingsManager]: * Rewrite not-equals=true 312.69/160.47 [2019-03-28 12:21:47,013 INFO L133 SettingsManager]: * Create parallel compositions if possible=false 312.69/160.47 [2019-03-28 12:21:47,014 INFO L133 SettingsManager]: * Minimize states using LBE with the strategy=SINGLE 312.69/160.47 [2019-03-28 12:21:47,014 INFO L133 SettingsManager]: * Use SBE=true 312.69/160.47 [2019-03-28 12:21:47,014 INFO L131 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: 312.69/160.47 [2019-03-28 12:21:47,014 INFO L133 SettingsManager]: * Use old map elimination=false 312.69/160.47 [2019-03-28 12:21:47,014 INFO L133 SettingsManager]: * Use external solver (rank synthesis)=false 312.69/160.47 [2019-03-28 12:21:47,015 INFO L133 SettingsManager]: * Buchi interpolant automaton construction strategy=DANDELION 312.69/160.47 [2019-03-28 12:21:47,015 INFO L133 SettingsManager]: * Use only trivial implications for array writes=true 312.69/160.47 [2019-03-28 12:21:47,015 INFO L133 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES 312.69/160.47 [2019-03-28 12:21:47,015 INFO L133 SettingsManager]: * Construct termination proof for TermComp=true 312.69/160.47 [2019-03-28 12:21:47,015 INFO L133 SettingsManager]: * Command for external solver (GNTA synthesis)=z3 SMTLIB2_COMPLIANT=true -memory:4560 -smt2 -in -t:12000 312.69/160.47 [2019-03-28 12:21:47,016 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: 312.69/160.47 [2019-03-28 12:21:47,016 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false 312.69/160.47 [2019-03-28 12:21:47,016 INFO L133 SettingsManager]: * Check division by zero=IGNORE 312.69/160.47 [2019-03-28 12:21:47,016 INFO L133 SettingsManager]: * Check if freed pointer was valid=false 312.69/160.47 [2019-03-28 12:21:47,016 INFO L133 SettingsManager]: * Assume nondeterminstic values are in range=false 312.69/160.47 [2019-03-28 12:21:47,017 INFO L133 SettingsManager]: * How to treat unsigned ints differently from normal ones=IGNORE 312.69/160.47 [2019-03-28 12:21:47,017 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: 312.69/160.47 [2019-03-28 12:21:47,017 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements 312.69/160.47 [2019-03-28 12:21:47,017 INFO L133 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump 312.69/160.47 [2019-03-28 12:21:47,017 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:4560 -smt2 -in -t:5000 312.69/160.47 [2019-03-28 12:21:47,018 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: 312.69/160.47 [2019-03-28 12:21:47,018 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles 312.69/160.47 [2019-03-28 12:21:47,018 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL 312.69/160.47 [2019-03-28 12:21:47,018 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true 312.69/160.47 [2019-03-28 12:21:47,043 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp 312.69/160.47 [2019-03-28 12:21:47,056 INFO L259 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized 312.69/160.47 [2019-03-28 12:21:47,059 INFO L215 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. 312.69/160.47 [2019-03-28 12:21:47,061 INFO L271 PluginConnector]: Initializing CDTParser... 312.69/160.47 [2019-03-28 12:21:47,061 INFO L276 PluginConnector]: CDTParser initialized 312.69/160.47 [2019-03-28 12:21:47,062 INFO L430 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /export/starexec/sandbox2/benchmark/theBenchmark.c 312.69/160.47 [2019-03-28 12:21:47,123 INFO L221 CDTParser]: Created temporary CDT project at /export/starexec/sandbox2/tmp/638a48142df34b35a9b12f3ae8637b94/FLAGf9c0442b6 312.69/160.47 [2019-03-28 12:21:47,494 INFO L307 CDTParser]: Found 1 translation units. 312.69/160.47 [2019-03-28 12:21:47,495 INFO L161 CDTParser]: Scanning /export/starexec/sandbox2/benchmark/theBenchmark.c 312.69/160.47 [2019-03-28 12:21:47,507 INFO L355 CDTParser]: About to delete temporary CDT project at /export/starexec/sandbox2/tmp/638a48142df34b35a9b12f3ae8637b94/FLAGf9c0442b6 312.69/160.47 [2019-03-28 12:21:47,882 INFO L363 CDTParser]: Successfully deleted /export/starexec/sandbox2/tmp/638a48142df34b35a9b12f3ae8637b94 312.69/160.47 [2019-03-28 12:21:47,894 INFO L297 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### 312.69/160.47 [2019-03-28 12:21:47,895 INFO L131 ToolchainWalker]: Walking toolchain with 7 elements. 312.69/160.47 [2019-03-28 12:21:47,896 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- 312.69/160.47 [2019-03-28 12:21:47,896 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... 312.69/160.47 [2019-03-28 12:21:47,900 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized 312.69/160.47 [2019-03-28 12:21:47,901 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.03 12:21:47" (1/1) ... 312.69/160.47 [2019-03-28 12:21:47,904 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@e364eee and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:21:47, skipping insertion in model container 312.69/160.47 [2019-03-28 12:21:47,904 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.03 12:21:47" (1/1) ... 312.69/160.47 [2019-03-28 12:21:47,912 INFO L145 MainTranslator]: Starting translation in SV-COMP mode 312.69/160.47 [2019-03-28 12:21:47,955 INFO L176 MainTranslator]: Built tables and reachable declarations 312.69/160.47 [2019-03-28 12:21:48,249 INFO L206 PostProcessor]: Analyzing one entry point: main 312.69/160.47 [2019-03-28 12:21:48,257 INFO L191 MainTranslator]: Completed pre-run 312.69/160.47 [2019-03-28 12:21:48,318 INFO L206 PostProcessor]: Analyzing one entry point: main 312.69/160.47 [2019-03-28 12:21:48,342 INFO L195 MainTranslator]: Completed translation 312.69/160.47 [2019-03-28 12:21:48,343 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:21:48 WrapperNode 312.69/160.47 [2019-03-28 12:21:48,343 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- 312.69/160.47 [2019-03-28 12:21:48,344 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- 312.69/160.47 [2019-03-28 12:21:48,344 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... 312.69/160.47 [2019-03-28 12:21:48,344 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized 312.69/160.47 [2019-03-28 12:21:48,354 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:21:48" (1/1) ... 312.69/160.47 [2019-03-28 12:21:48,364 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:21:48" (1/1) ... 312.69/160.47 [2019-03-28 12:21:48,424 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- 312.69/160.47 [2019-03-28 12:21:48,425 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- 312.69/160.47 [2019-03-28 12:21:48,425 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... 312.69/160.47 [2019-03-28 12:21:48,425 INFO L276 PluginConnector]: Boogie Preprocessor initialized 312.69/160.47 [2019-03-28 12:21:48,436 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:21:48" (1/1) ... 312.69/160.47 [2019-03-28 12:21:48,437 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:21:48" (1/1) ... 312.69/160.47 [2019-03-28 12:21:48,441 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:21:48" (1/1) ... 312.69/160.47 [2019-03-28 12:21:48,441 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:21:48" (1/1) ... 312.69/160.47 [2019-03-28 12:21:48,460 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:21:48" (1/1) ... 312.69/160.47 [2019-03-28 12:21:48,485 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:21:48" (1/1) ... 312.69/160.47 [2019-03-28 12:21:48,488 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:21:48" (1/1) ... 312.69/160.47 [2019-03-28 12:21:48,494 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- 312.69/160.47 [2019-03-28 12:21:48,495 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- 312.69/160.47 [2019-03-28 12:21:48,495 INFO L271 PluginConnector]: Initializing RCFGBuilder... 312.69/160.47 [2019-03-28 12:21:48,495 INFO L276 PluginConnector]: RCFGBuilder initialized 312.69/160.47 [2019-03-28 12:21:48,496 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:21:48" (1/1) ... 312.69/160.47 No working directory specified, using /export/starexec/sandbox2/solver/bin/z3 312.69/160.47 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:4560 -smt2 -in -t:5000 (exit command is (exit), workingDir is null) 312.69/160.47 Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:4560 -smt2 -in -t:5000 312.69/160.47 [2019-03-28 12:21:48,566 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start 312.69/160.47 [2019-03-28 12:21:48,566 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start 312.69/160.47 [2019-03-28 12:21:49,840 INFO L281 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) 312.69/160.47 [2019-03-28 12:21:49,840 INFO L286 CfgBuilder]: Removed 198 assue(true) statements. 312.69/160.47 [2019-03-28 12:21:49,842 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.03 12:21:49 BoogieIcfgContainer 312.69/160.47 [2019-03-28 12:21:49,842 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- 312.69/160.47 [2019-03-28 12:21:49,842 INFO L113 PluginConnector]: ------------------------BlockEncodingV2---------------------------- 312.69/160.48 [2019-03-28 12:21:49,842 INFO L271 PluginConnector]: Initializing BlockEncodingV2... 312.69/160.48 [2019-03-28 12:21:49,845 INFO L276 PluginConnector]: BlockEncodingV2 initialized 312.69/160.48 [2019-03-28 12:21:49,845 INFO L185 PluginConnector]: Executing the observer BlockEncodingObserver from plugin BlockEncodingV2 for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.03 12:21:49" (1/1) ... 312.69/160.48 [2019-03-28 12:21:49,886 INFO L313 BlockEncoder]: Initial Icfg 538 locations, 833 edges 312.69/160.48 [2019-03-28 12:21:49,888 INFO L258 BlockEncoder]: Using Remove infeasible edges 312.69/160.48 [2019-03-28 12:21:49,888 INFO L263 BlockEncoder]: Using Maximize final states 312.69/160.48 [2019-03-28 12:21:49,889 INFO L270 BlockEncoder]: Using Minimize states even if more edges are added than removed.=false 312.69/160.48 [2019-03-28 12:21:49,889 INFO L276 BlockEncoder]: Using Minimize states using LBE with the strategy=SINGLE 312.69/160.48 [2019-03-28 12:21:49,891 INFO L296 BlockEncoder]: Using Remove sink states 312.69/160.48 [2019-03-28 12:21:49,892 INFO L171 BlockEncoder]: Using Apply optimizations until nothing changes=true 312.69/160.48 [2019-03-28 12:21:49,892 INFO L179 BlockEncoder]: Using Rewrite not-equals 312.69/160.48 [2019-03-28 12:21:49,973 INFO L185 BlockEncoder]: Using Use SBE 312.69/160.48 [2019-03-28 12:21:50,062 INFO L200 BlockEncoder]: SBE split 276 edges 312.69/160.48 [2019-03-28 12:21:50,072 INFO L70 emoveInfeasibleEdges]: Removed 18 edges and 0 locations because of local infeasibility 312.69/160.48 [2019-03-28 12:21:50,075 INFO L71 MaximizeFinalStates]: 0 new accepting states 312.69/160.48 [2019-03-28 12:21:50,203 INFO L100 BaseMinimizeStates]: Removed 156 edges and 78 locations by large block encoding 312.69/160.48 [2019-03-28 12:21:50,206 INFO L70 RemoveSinkStates]: Removed 6 edges and 4 locations by removing sink states 312.69/160.48 [2019-03-28 12:21:50,210 INFO L70 emoveInfeasibleEdges]: Removed 0 edges and 0 locations because of local infeasibility 312.69/160.48 [2019-03-28 12:21:50,211 INFO L71 MaximizeFinalStates]: 0 new accepting states 312.69/160.48 [2019-03-28 12:21:50,214 INFO L100 BaseMinimizeStates]: Removed 4 edges and 2 locations by large block encoding 312.69/160.48 [2019-03-28 12:21:50,215 INFO L70 RemoveSinkStates]: Removed 0 edges and 0 locations by removing sink states 312.69/160.48 [2019-03-28 12:21:50,218 INFO L70 emoveInfeasibleEdges]: Removed 0 edges and 0 locations because of local infeasibility 312.69/160.48 [2019-03-28 12:21:50,219 INFO L71 MaximizeFinalStates]: 0 new accepting states 312.69/160.48 [2019-03-28 12:21:50,220 INFO L100 BaseMinimizeStates]: Removed 0 edges and 0 locations by large block encoding 312.69/160.48 [2019-03-28 12:21:50,221 INFO L70 RemoveSinkStates]: Removed 0 edges and 0 locations by removing sink states 312.69/160.48 [2019-03-28 12:21:50,223 INFO L313 BlockEncoder]: Encoded RCFG 454 locations, 1005 edges 312.69/160.48 [2019-03-28 12:21:50,223 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.blockencoding CFG 28.03 12:21:50 BasicIcfg 312.69/160.48 [2019-03-28 12:21:50,224 INFO L132 PluginConnector]: ------------------------ END BlockEncodingV2---------------------------- 312.69/160.48 [2019-03-28 12:21:50,224 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- 312.69/160.48 [2019-03-28 12:21:50,225 INFO L271 PluginConnector]: Initializing TraceAbstraction... 312.69/160.48 [2019-03-28 12:21:50,228 INFO L276 PluginConnector]: TraceAbstraction initialized 312.69/160.48 [2019-03-28 12:21:50,229 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 28.03 12:21:47" (1/4) ... 312.69/160.48 [2019-03-28 12:21:50,230 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2753617e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.03 12:21:50, skipping insertion in model container 312.69/160.48 [2019-03-28 12:21:50,231 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:21:48" (2/4) ... 312.69/160.48 [2019-03-28 12:21:50,231 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2753617e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.03 12:21:50, skipping insertion in model container 312.69/160.48 [2019-03-28 12:21:50,231 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.03 12:21:49" (3/4) ... 312.69/160.48 [2019-03-28 12:21:50,231 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2753617e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.03 12:21:50, skipping insertion in model container 312.69/160.48 [2019-03-28 12:21:50,232 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.blockencoding CFG 28.03 12:21:50" (4/4) ... 312.69/160.48 [2019-03-28 12:21:50,233 INFO L112 eAbstractionObserver]: Analyzing ICFG theBenchmark.c_BEv2 312.69/160.48 [2019-03-28 12:21:50,243 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:ForwardPredicates Determinization: PREDICATE_ABSTRACTION 312.69/160.48 [2019-03-28 12:21:50,253 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 0 error locations. 312.69/160.48 [2019-03-28 12:21:50,271 INFO L257 AbstractCegarLoop]: Starting to check reachability of 0 error locations. 312.69/160.48 [2019-03-28 12:21:50,304 INFO L133 ementStrategyFactory]: Using default assertion order modulation 312.69/160.48 [2019-03-28 12:21:50,305 INFO L382 AbstractCegarLoop]: Interprodecural is true 312.69/160.48 [2019-03-28 12:21:50,305 INFO L383 AbstractCegarLoop]: Hoare is true 312.69/160.48 [2019-03-28 12:21:50,305 INFO L384 AbstractCegarLoop]: Compute interpolants for ForwardPredicates 312.69/160.48 [2019-03-28 12:21:50,305 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE 312.69/160.48 [2019-03-28 12:21:50,305 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION 312.69/160.48 [2019-03-28 12:21:50,305 INFO L387 AbstractCegarLoop]: Difference is false 312.69/160.48 [2019-03-28 12:21:50,306 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA 312.69/160.48 [2019-03-28 12:21:50,306 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== 312.69/160.48 [2019-03-28 12:21:50,331 INFO L276 IsEmpty]: Start isEmpty. Operand 454 states. 312.69/160.48 [2019-03-28 12:21:50,345 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. 312.69/160.48 [2019-03-28 12:21:50,357 INFO L343 DoubleDeckerVisitor]: Before removal of dead ends 454 states. 312.69/160.48 [2019-03-28 12:21:50,528 INFO L448 ceAbstractionStarter]: For program point L332-11(lines 332 341) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,528 INFO L448 ceAbstractionStarter]: For program point L761-24(lines 761 765) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,528 INFO L448 ceAbstractionStarter]: For program point L332-12(lines 332 341) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,529 INFO L448 ceAbstractionStarter]: For program point L761-26(lines 761 765) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,529 INFO L448 ceAbstractionStarter]: For program point L332-14(lines 332 341) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,529 INFO L448 ceAbstractionStarter]: For program point L332-15(lines 332 341) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,529 INFO L448 ceAbstractionStarter]: For program point L332-17(lines 332 341) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,529 INFO L448 ceAbstractionStarter]: For program point L828-1(lines 817 880) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,529 INFO L448 ceAbstractionStarter]: For program point L332-18(lines 332 341) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,529 INFO L448 ceAbstractionStarter]: For program point L332-20(lines 332 341) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,530 INFO L448 ceAbstractionStarter]: For program point L332-21(lines 332 341) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,530 INFO L448 ceAbstractionStarter]: For program point L332-23(lines 332 341) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,530 INFO L448 ceAbstractionStarter]: For program point L332-24(lines 332 341) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,530 INFO L448 ceAbstractionStarter]: For program point L332-26(lines 332 341) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,530 INFO L448 ceAbstractionStarter]: For program point L333(lines 333 338) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,530 INFO L448 ceAbstractionStarter]: For program point L333-1(lines 333 338) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,531 INFO L448 ceAbstractionStarter]: For program point L333-2(lines 333 338) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,531 INFO L448 ceAbstractionStarter]: For program point L333-3(lines 333 338) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,531 INFO L448 ceAbstractionStarter]: For program point L333-4(lines 333 338) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,532 INFO L448 ceAbstractionStarter]: For program point L333-5(lines 333 338) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,532 INFO L448 ceAbstractionStarter]: For program point L333-6(lines 333 338) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,532 INFO L448 ceAbstractionStarter]: For program point L333-7(lines 333 338) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,532 INFO L448 ceAbstractionStarter]: For program point L333-8(lines 333 338) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,532 INFO L448 ceAbstractionStarter]: For program point L631-1(lines 600 663) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,532 INFO L448 ceAbstractionStarter]: For program point L565(lines 565 572) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,532 INFO L448 ceAbstractionStarter]: For program point L631-3(lines 600 663) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,533 INFO L448 ceAbstractionStarter]: For program point L466(lines 466 481) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,533 INFO L448 ceAbstractionStarter]: For program point L466-1(lines 466 481) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,533 INFO L451 ceAbstractionStarter]: At program point L400(lines 388 402) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,533 INFO L448 ceAbstractionStarter]: For program point L466-2(lines 466 481) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,533 INFO L451 ceAbstractionStarter]: At program point L400-1(lines 388 402) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,533 INFO L451 ceAbstractionStarter]: At program point L400-2(lines 388 402) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,534 INFO L451 ceAbstractionStarter]: At program point L400-3(lines 388 402) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,534 INFO L451 ceAbstractionStarter]: At program point L400-4(lines 388 402) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,534 INFO L451 ceAbstractionStarter]: At program point L400-5(lines 388 402) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,534 INFO L451 ceAbstractionStarter]: At program point L400-6(lines 388 402) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,534 INFO L451 ceAbstractionStarter]: At program point L400-7(lines 388 402) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,534 INFO L451 ceAbstractionStarter]: At program point L400-8(lines 388 402) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,534 INFO L448 ceAbstractionStarter]: For program point L863-1(lines 817 880) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,535 INFO L451 ceAbstractionStarter]: At program point L269-1(lines 257 288) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,535 INFO L451 ceAbstractionStarter]: At program point L930-1(lines 665 967) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,535 INFO L448 ceAbstractionStarter]: For program point L699-1(lines 668 731) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,535 INFO L448 ceAbstractionStarter]: For program point L699-3(lines 668 731) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,535 INFO L451 ceAbstractionStarter]: At program point L534(lines 496 590) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,535 INFO L451 ceAbstractionStarter]: At program point L501(lines 501 505) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,536 INFO L448 ceAbstractionStarter]: For program point L501-1(lines 496 590) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,536 INFO L448 ceAbstractionStarter]: For program point L601-1(lines 600 663) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,536 INFO L448 ceAbstractionStarter]: For program point L601-2(lines 601 605) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,536 INFO L448 ceAbstractionStarter]: For program point L601-4(lines 600 663) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,536 INFO L448 ceAbstractionStarter]: For program point L436-1(lines 415 448) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,536 INFO L448 ceAbstractionStarter]: For program point L370(lines 370 379) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,536 INFO L448 ceAbstractionStarter]: For program point L370-2(lines 370 379) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,537 INFO L448 ceAbstractionStarter]: For program point L370-3(lines 370 379) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,537 INFO L448 ceAbstractionStarter]: For program point L370-5(lines 370 379) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,537 INFO L448 ceAbstractionStarter]: For program point L370-6(lines 370 379) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,537 INFO L448 ceAbstractionStarter]: For program point L370-8(lines 370 379) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,538 INFO L448 ceAbstractionStarter]: For program point L370-9(lines 370 379) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,538 INFO L448 ceAbstractionStarter]: For program point L370-11(lines 370 379) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,538 INFO L448 ceAbstractionStarter]: For program point L370-12(lines 370 379) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,538 INFO L448 ceAbstractionStarter]: For program point L370-14(lines 370 379) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,538 INFO L448 ceAbstractionStarter]: For program point L370-15(lines 370 379) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,538 INFO L448 ceAbstractionStarter]: For program point L370-17(lines 370 379) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,538 INFO L448 ceAbstractionStarter]: For program point L370-18(lines 370 379) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,539 INFO L448 ceAbstractionStarter]: For program point L833-1(lines 817 880) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,539 INFO L448 ceAbstractionStarter]: For program point L370-20(lines 370 379) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,539 INFO L448 ceAbstractionStarter]: For program point L370-21(lines 370 379) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,539 INFO L448 ceAbstractionStarter]: For program point L370-23(lines 370 379) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,539 INFO L448 ceAbstractionStarter]: For program point L370-24(lines 370 379) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,539 INFO L448 ceAbstractionStarter]: For program point L370-26(lines 370 379) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,539 INFO L448 ceAbstractionStarter]: For program point L470(lines 470 480) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,540 INFO L448 ceAbstractionStarter]: For program point L470-1(lines 470 480) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,540 INFO L448 ceAbstractionStarter]: For program point L470-2(lines 470 480) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,540 INFO L448 ceAbstractionStarter]: For program point L371(lines 371 376) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,540 INFO L448 ceAbstractionStarter]: For program point L371-1(lines 371 376) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,540 INFO L451 ceAbstractionStarter]: At program point L305(lines 293 307) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,540 INFO L448 ceAbstractionStarter]: For program point L371-2(lines 371 376) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,540 INFO L451 ceAbstractionStarter]: At program point L305-1(lines 293 307) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,541 INFO L448 ceAbstractionStarter]: For program point L371-3(lines 371 376) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,541 INFO L451 ceAbstractionStarter]: At program point L305-2(lines 293 307) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,541 INFO L448 ceAbstractionStarter]: For program point L371-4(lines 371 376) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,541 INFO L451 ceAbstractionStarter]: At program point L305-3(lines 293 307) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,541 INFO L448 ceAbstractionStarter]: For program point L371-5(lines 371 376) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,541 INFO L451 ceAbstractionStarter]: At program point L305-4(lines 293 307) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,541 INFO L448 ceAbstractionStarter]: For program point L371-6(lines 371 376) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,542 INFO L451 ceAbstractionStarter]: At program point L305-5(lines 293 307) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,542 INFO L448 ceAbstractionStarter]: For program point L371-7(lines 371 376) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,542 INFO L451 ceAbstractionStarter]: At program point L305-6(lines 293 307) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,542 INFO L448 ceAbstractionStarter]: For program point L371-8(lines 371 376) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,542 INFO L451 ceAbstractionStarter]: At program point L305-7(lines 293 307) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,542 INFO L451 ceAbstractionStarter]: At program point L305-8(lines 293 307) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,542 INFO L448 ceAbstractionStarter]: For program point L669-1(lines 668 731) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,543 INFO L448 ceAbstractionStarter]: For program point L636-1(lines 600 663) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,543 INFO L448 ceAbstractionStarter]: For program point L669-3(lines 668 731) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,543 INFO L448 ceAbstractionStarter]: For program point L537(lines 537 544) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,543 INFO L448 ceAbstractionStarter]: For program point L636-3(lines 600 663) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,543 INFO L448 ceAbstractionStarter]: For program point L868-1(lines 817 880) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,543 INFO L448 ceAbstractionStarter]: For program point L769(lines 769 773) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,543 INFO L448 ceAbstractionStarter]: For program point L769-2(lines 769 773) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,543 INFO L448 ceAbstractionStarter]: For program point L769-3(lines 769 773) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,544 INFO L448 ceAbstractionStarter]: For program point L769-5(lines 769 773) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,544 INFO L448 ceAbstractionStarter]: For program point L769-6(lines 769 773) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,544 INFO L448 ceAbstractionStarter]: For program point L769-8(lines 769 773) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,544 INFO L448 ceAbstractionStarter]: For program point L769-9(lines 769 773) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,544 INFO L448 ceAbstractionStarter]: For program point L769-11(lines 769 773) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,544 INFO L448 ceAbstractionStarter]: For program point L769-12(lines 769 773) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,544 INFO L448 ceAbstractionStarter]: For program point L769-14(lines 769 773) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,569 INFO L448 ceAbstractionStarter]: For program point L769-15(lines 769 773) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,569 INFO L448 ceAbstractionStarter]: For program point L769-17(lines 769 773) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,569 INFO L448 ceAbstractionStarter]: For program point L769-18(lines 769 773) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,569 INFO L448 ceAbstractionStarter]: For program point L769-20(lines 769 773) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,570 INFO L448 ceAbstractionStarter]: For program point L769-21(lines 769 773) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,570 INFO L448 ceAbstractionStarter]: For program point L769-23(lines 769 773) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,570 INFO L448 ceAbstractionStarter]: For program point L769-24(lines 769 773) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,570 INFO L448 ceAbstractionStarter]: For program point L769-26(lines 769 773) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,570 INFO L448 ceAbstractionStarter]: For program point L704-1(lines 668 731) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,570 INFO L448 ceAbstractionStarter]: For program point L704-3(lines 668 731) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,573 INFO L451 ceAbstractionStarter]: At program point L506(lines 496 590) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,573 INFO L448 ceAbstractionStarter]: For program point L606-1(lines 600 663) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,573 INFO L448 ceAbstractionStarter]: For program point L606-3(lines 600 663) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,574 INFO L448 ceAbstractionStarter]: For program point L474(lines 474 479) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,574 INFO L448 ceAbstractionStarter]: For program point L474-1(lines 474 479) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,574 INFO L451 ceAbstractionStarter]: At program point L441-1(lines 601 605) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,574 INFO L448 ceAbstractionStarter]: For program point L474-2(lines 474 479) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,574 INFO L448 ceAbstractionStarter]: For program point L904(lines 904 909) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,574 INFO L448 ceAbstractionStarter]: For program point L838-1(lines 817 880) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,575 INFO L451 ceAbstractionStarter]: At program point L409(lines 416 420) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,575 INFO L451 ceAbstractionStarter]: At program point L343(lines 331 345) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,575 INFO L451 ceAbstractionStarter]: At program point L343-1(lines 331 345) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,575 INFO L451 ceAbstractionStarter]: At program point L343-2(lines 331 345) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,575 INFO L451 ceAbstractionStarter]: At program point L343-3(lines 331 345) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,575 INFO L451 ceAbstractionStarter]: At program point L343-4(lines 331 345) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,575 INFO L451 ceAbstractionStarter]: At program point L343-5(lines 331 345) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,576 INFO L451 ceAbstractionStarter]: At program point L343-6(lines 331 345) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,576 INFO L451 ceAbstractionStarter]: At program point L343-7(lines 331 345) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,576 INFO L451 ceAbstractionStarter]: At program point L343-8(lines 331 345) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,576 INFO L448 ceAbstractionStarter]: For program point L674-1(lines 668 731) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,576 INFO L448 ceAbstractionStarter]: For program point L641-1(lines 600 663) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,576 INFO L448 ceAbstractionStarter]: For program point L674-3(lines 668 731) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,576 INFO L448 ceAbstractionStarter]: For program point L641-3(lines 600 663) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,577 INFO L448 ceAbstractionStarter]: For program point L509(lines 509 516) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,577 INFO L451 ceAbstractionStarter]: At program point L576(lines 496 590) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,577 INFO L448 ceAbstractionStarter]: For program point L114(lines 114 122) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,577 INFO L448 ceAbstractionStarter]: For program point L709-1(lines 668 731) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,577 INFO L448 ceAbstractionStarter]: For program point L709-3(lines 668 731) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,577 INFO L448 ceAbstractionStarter]: For program point L313(lines 313 322) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,577 INFO L448 ceAbstractionStarter]: For program point L313-2(lines 313 322) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,577 INFO L448 ceAbstractionStarter]: For program point L313-3(lines 313 322) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,578 INFO L448 ceAbstractionStarter]: For program point L313-5(lines 313 322) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,578 INFO L448 ceAbstractionStarter]: For program point L313-6(lines 313 322) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,578 INFO L448 ceAbstractionStarter]: For program point L313-8(lines 313 322) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,578 INFO L448 ceAbstractionStarter]: For program point L313-9(lines 313 322) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,578 INFO L448 ceAbstractionStarter]: For program point L313-11(lines 313 322) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,578 INFO L448 ceAbstractionStarter]: For program point L313-12(lines 313 322) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,578 INFO L448 ceAbstractionStarter]: For program point L313-14(lines 313 322) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,578 INFO L448 ceAbstractionStarter]: For program point L313-15(lines 313 322) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,579 INFO L448 ceAbstractionStarter]: For program point L313-17(lines 313 322) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,579 INFO L448 ceAbstractionStarter]: For program point L313-18(lines 313 322) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,579 INFO L448 ceAbstractionStarter]: For program point L313-20(lines 313 322) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,579 INFO L448 ceAbstractionStarter]: For program point L313-21(lines 313 322) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,579 INFO L448 ceAbstractionStarter]: For program point L611-1(lines 600 663) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,579 INFO L448 ceAbstractionStarter]: For program point L313-23(lines 313 322) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,579 INFO L448 ceAbstractionStarter]: For program point L313-24(lines 313 322) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,580 INFO L448 ceAbstractionStarter]: For program point L611-3(lines 600 663) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,580 INFO L448 ceAbstractionStarter]: For program point L313-26(lines 313 322) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,580 INFO L448 ceAbstractionStarter]: For program point L314(lines 314 319) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,580 INFO L448 ceAbstractionStarter]: For program point L314-1(lines 314 319) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,580 INFO L448 ceAbstractionStarter]: For program point L314-2(lines 314 319) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,580 INFO L448 ceAbstractionStarter]: For program point L314-3(lines 314 319) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,580 INFO L448 ceAbstractionStarter]: For program point L314-4(lines 314 319) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,580 INFO L448 ceAbstractionStarter]: For program point L314-5(lines 314 319) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,581 INFO L448 ceAbstractionStarter]: For program point L314-6(lines 314 319) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,581 INFO L448 ceAbstractionStarter]: For program point L314-7(lines 314 319) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,581 INFO L448 ceAbstractionStarter]: For program point L314-8(lines 314 319) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,581 INFO L448 ceAbstractionStarter]: For program point L843-1(lines 817 880) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,581 INFO L448 ceAbstractionStarter]: For program point L777(lines 777 781) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,581 INFO L448 ceAbstractionStarter]: For program point L777-2(lines 777 781) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,581 INFO L448 ceAbstractionStarter]: For program point L777-3(lines 777 781) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,581 INFO L448 ceAbstractionStarter]: For program point L777-5(lines 777 781) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,582 INFO L448 ceAbstractionStarter]: For program point L579(lines 579 586) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,582 INFO L448 ceAbstractionStarter]: For program point L777-6(lines 777 781) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,582 INFO L448 ceAbstractionStarter]: For program point L777-8(lines 777 781) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,582 INFO L448 ceAbstractionStarter]: For program point L777-9(lines 777 781) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,582 INFO L448 ceAbstractionStarter]: For program point L777-11(lines 777 781) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,582 INFO L451 ceAbstractionStarter]: At program point L381(lines 369 383) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,582 INFO L448 ceAbstractionStarter]: For program point L777-12(lines 777 781) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,583 INFO L451 ceAbstractionStarter]: At program point L381-1(lines 369 383) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,583 INFO L451 ceAbstractionStarter]: At program point L381-2(lines 369 383) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,583 INFO L448 ceAbstractionStarter]: For program point L777-14(lines 777 781) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,583 INFO L451 ceAbstractionStarter]: At program point L381-3(lines 369 383) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,583 INFO L448 ceAbstractionStarter]: For program point L777-15(lines 777 781) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,583 INFO L451 ceAbstractionStarter]: At program point L381-4(lines 369 383) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,583 INFO L451 ceAbstractionStarter]: At program point L381-5(lines 369 383) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,584 INFO L448 ceAbstractionStarter]: For program point L777-17(lines 777 781) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,584 INFO L451 ceAbstractionStarter]: At program point L381-6(lines 369 383) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,584 INFO L448 ceAbstractionStarter]: For program point L777-18(lines 777 781) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,584 INFO L448 ceAbstractionStarter]: For program point L150(lines 150 158) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,584 INFO L451 ceAbstractionStarter]: At program point L381-7(lines 369 383) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,584 INFO L451 ceAbstractionStarter]: At program point L117(lines 117 121) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,584 INFO L448 ceAbstractionStarter]: For program point L777-20(lines 777 781) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,584 INFO L451 ceAbstractionStarter]: At program point L381-8(lines 369 383) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,585 INFO L448 ceAbstractionStarter]: For program point L777-21(lines 777 781) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,585 INFO L448 ceAbstractionStarter]: For program point L777-23(lines 777 781) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,585 INFO L448 ceAbstractionStarter]: For program point L777-24(lines 777 781) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,585 INFO L448 ceAbstractionStarter]: For program point L777-26(lines 777 781) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,585 INFO L448 ceAbstractionStarter]: For program point L745(lines 745 749) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,585 INFO L448 ceAbstractionStarter]: For program point L745-2(lines 745 749) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,585 INFO L448 ceAbstractionStarter]: For program point L679-1(lines 668 731) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,586 INFO L448 ceAbstractionStarter]: For program point L745-3(lines 745 749) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,586 INFO L448 ceAbstractionStarter]: For program point L646-1(lines 600 663) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,586 INFO L448 ceAbstractionStarter]: For program point L745-5(lines 745 749) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,586 INFO L448 ceAbstractionStarter]: For program point L679-3(lines 668 731) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,586 INFO L448 ceAbstractionStarter]: For program point L646-3(lines 600 663) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,586 INFO L448 ceAbstractionStarter]: For program point L745-6(lines 745 749) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,586 INFO L448 ceAbstractionStarter]: For program point L745-8(lines 745 749) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,586 INFO L448 ceAbstractionStarter]: For program point L745-9(lines 745 749) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,587 INFO L448 ceAbstractionStarter]: For program point L745-11(lines 745 749) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,587 INFO L448 ceAbstractionStarter]: For program point L745-12(lines 745 749) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,587 INFO L448 ceAbstractionStarter]: For program point L745-14(lines 745 749) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,587 INFO L448 ceAbstractionStarter]: For program point L745-15(lines 745 749) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,587 INFO L448 ceAbstractionStarter]: For program point L745-17(lines 745 749) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,587 INFO L448 ceAbstractionStarter]: For program point L745-18(lines 745 749) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,587 INFO L448 ceAbstractionStarter]: For program point L745-20(lines 745 749) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,587 INFO L448 ceAbstractionStarter]: For program point L745-21(lines 745 749) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,588 INFO L448 ceAbstractionStarter]: For program point L745-23(lines 745 749) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,588 INFO L448 ceAbstractionStarter]: For program point L745-24(lines 745 749) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,588 INFO L451 ceAbstractionStarter]: At program point L911(lines 900 913) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,588 INFO L448 ceAbstractionStarter]: For program point L745-26(lines 745 749) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,588 INFO L451 ceAbstractionStarter]: At program point L548(lines 496 590) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,588 INFO L448 ceAbstractionStarter]: For program point L416-1(lines 415 448) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,588 INFO L451 ceAbstractionStarter]: At program point ULTIMATE.startENTRY(line -1) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,589 INFO L448 ceAbstractionStarter]: For program point L714-1(lines 668 731) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,589 INFO L448 ceAbstractionStarter]: For program point L714-3(lines 668 731) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,589 INFO L448 ceAbstractionStarter]: For program point L351(lines 351 360) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,589 INFO L448 ceAbstractionStarter]: For program point L351-2(lines 351 360) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,589 INFO L448 ceAbstractionStarter]: For program point L351-3(lines 351 360) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,589 INFO L448 ceAbstractionStarter]: For program point L186(lines 186 194) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,589 INFO L448 ceAbstractionStarter]: For program point L351-5(lines 351 360) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,589 INFO L451 ceAbstractionStarter]: At program point L153(lines 153 157) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,590 INFO L448 ceAbstractionStarter]: For program point L351-6(lines 351 360) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,590 INFO L448 ceAbstractionStarter]: For program point L351-8(lines 351 360) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,590 INFO L448 ceAbstractionStarter]: For program point L351-9(lines 351 360) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,590 INFO L448 ceAbstractionStarter]: For program point L351-11(lines 351 360) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,590 INFO L448 ceAbstractionStarter]: For program point L351-12(lines 351 360) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,590 INFO L448 ceAbstractionStarter]: For program point L351-14(lines 351 360) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,590 INFO L448 ceAbstractionStarter]: For program point L351-15(lines 351 360) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,590 INFO L448 ceAbstractionStarter]: For program point L351-17(lines 351 360) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,591 INFO L448 ceAbstractionStarter]: For program point L351-18(lines 351 360) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,591 INFO L448 ceAbstractionStarter]: For program point L351-20(lines 351 360) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,591 INFO L448 ceAbstractionStarter]: For program point L351-21(lines 351 360) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,591 INFO L448 ceAbstractionStarter]: For program point L351-23(lines 351 360) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,591 INFO L448 ceAbstractionStarter]: For program point L616-1(lines 600 663) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,591 INFO L448 ceAbstractionStarter]: For program point L351-24(lines 351 360) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,591 INFO L448 ceAbstractionStarter]: For program point L616-3(lines 600 663) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,591 INFO L448 ceAbstractionStarter]: For program point L351-26(lines 351 360) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,592 INFO L448 ceAbstractionStarter]: For program point L352(lines 352 357) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,592 INFO L448 ceAbstractionStarter]: For program point L352-1(lines 352 357) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,592 INFO L448 ceAbstractionStarter]: For program point L352-2(lines 352 357) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,592 INFO L448 ceAbstractionStarter]: For program point L352-3(lines 352 357) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,592 INFO L448 ceAbstractionStarter]: For program point L352-4(lines 352 357) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,592 INFO L448 ceAbstractionStarter]: For program point L352-5(lines 352 357) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,592 INFO L448 ceAbstractionStarter]: For program point L352-6(lines 352 357) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,592 INFO L448 ceAbstractionStarter]: For program point L352-7(lines 352 357) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,593 INFO L448 ceAbstractionStarter]: For program point L88(lines 88 92) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,593 INFO L448 ceAbstractionStarter]: For program point L352-8(lines 352 357) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,593 INFO L448 ceAbstractionStarter]: For program point L88-1(lines 87 101) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,593 INFO L448 ceAbstractionStarter]: For program point L848-1(lines 817 880) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,593 INFO L448 ceAbstractionStarter]: For program point L551(lines 551 558) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,593 INFO L448 ceAbstractionStarter]: For program point L89(lines 89 91) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,593 INFO L448 ceAbstractionStarter]: For program point L684-1(lines 668 731) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,593 INFO L448 ceAbstractionStarter]: For program point L651-1(lines 600 663) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,594 INFO L448 ceAbstractionStarter]: For program point L684-3(lines 668 731) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,594 INFO L448 ceAbstractionStarter]: For program point L651-3(lines 600 663) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,594 INFO L451 ceAbstractionStarter]: At program point L486(lines 453 488) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,594 INFO L451 ceAbstractionStarter]: At program point L486-1(lines 453 488) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,594 INFO L451 ceAbstractionStarter]: At program point L486-2(lines 453 488) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,594 INFO L448 ceAbstractionStarter]: For program point L222(lines 222 230) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,594 INFO L451 ceAbstractionStarter]: At program point L189(lines 189 193) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,595 INFO L451 ceAbstractionStarter]: At program point L949(lines 949 958) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,595 INFO L451 ceAbstractionStarter]: At program point L949-1(lines 949 958) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,595 INFO L451 ceAbstractionStarter]: At program point L520(lines 496 590) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,595 INFO L448 ceAbstractionStarter]: For program point L454(lines 454 484) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,595 INFO L448 ceAbstractionStarter]: For program point L454-1(lines 454 484) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,595 INFO L448 ceAbstractionStarter]: For program point L421-1(lines 415 448) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,595 INFO L448 ceAbstractionStarter]: For program point L454-2(lines 454 484) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,596 INFO L448 ceAbstractionStarter]: For program point L58(lines 58 66) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,596 INFO L448 ceAbstractionStarter]: For program point L785(lines 785 789) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,596 INFO L448 ceAbstractionStarter]: For program point L818-1(lines 817 880) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,596 INFO L451 ceAbstractionStarter]: At program point L785-2(lines 669 673) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,596 INFO L448 ceAbstractionStarter]: For program point L719-1(lines 668 731) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,596 INFO L448 ceAbstractionStarter]: For program point L785-3(lines 785 789) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,596 INFO L451 ceAbstractionStarter]: At program point L785-5(lines 1 985) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,596 INFO L448 ceAbstractionStarter]: For program point L719-3(lines 668 731) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,597 INFO L448 ceAbstractionStarter]: For program point L785-6(lines 785 789) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,597 INFO L451 ceAbstractionStarter]: At program point L785-8(lines 1 985) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,597 INFO L448 ceAbstractionStarter]: For program point L785-9(lines 785 789) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,597 INFO L451 ceAbstractionStarter]: At program point L785-11(lines 1 985) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,597 INFO L448 ceAbstractionStarter]: For program point L389(lines 389 398) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,597 INFO L448 ceAbstractionStarter]: For program point L785-12(lines 785 789) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,597 INFO L448 ceAbstractionStarter]: For program point L389-2(lines 389 398) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,597 INFO L451 ceAbstractionStarter]: At program point L785-14(lines 1 985) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,598 INFO L448 ceAbstractionStarter]: For program point L389-3(lines 389 398) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,598 INFO L448 ceAbstractionStarter]: For program point L785-15(lines 785 789) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,598 INFO L448 ceAbstractionStarter]: For program point L389-5(lines 389 398) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,598 INFO L451 ceAbstractionStarter]: At program point L785-17(lines 1 985) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,598 INFO L448 ceAbstractionStarter]: For program point L389-6(lines 389 398) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,598 INFO L448 ceAbstractionStarter]: For program point L785-18(lines 785 789) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,598 INFO L448 ceAbstractionStarter]: For program point L389-8(lines 389 398) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,598 INFO L451 ceAbstractionStarter]: At program point L785-20(lines 1 985) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,599 INFO L451 ceAbstractionStarter]: At program point L125-1(lines 113 144) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,599 INFO L448 ceAbstractionStarter]: For program point L389-9(lines 389 398) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,599 INFO L448 ceAbstractionStarter]: For program point L785-21(lines 785 789) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,599 INFO L448 ceAbstractionStarter]: For program point L389-11(lines 389 398) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,599 INFO L451 ceAbstractionStarter]: At program point L785-23(lines 669 673) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,599 INFO L448 ceAbstractionStarter]: For program point L389-12(lines 389 398) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,599 INFO L448 ceAbstractionStarter]: For program point L785-24(lines 785 789) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,600 INFO L448 ceAbstractionStarter]: For program point L389-14(lines 389 398) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,600 INFO L451 ceAbstractionStarter]: At program point L785-26(lines 818 822) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,600 INFO L448 ceAbstractionStarter]: For program point L389-15(lines 389 398) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,600 INFO L448 ceAbstractionStarter]: For program point L389-17(lines 389 398) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,600 INFO L448 ceAbstractionStarter]: For program point L389-18(lines 389 398) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,600 INFO L448 ceAbstractionStarter]: For program point L753(lines 753 757) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,600 INFO L448 ceAbstractionStarter]: For program point L389-20(lines 389 398) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,600 INFO L448 ceAbstractionStarter]: For program point L389-21(lines 389 398) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,601 INFO L448 ceAbstractionStarter]: For program point L753-2(lines 753 757) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,601 INFO L448 ceAbstractionStarter]: For program point L753-3(lines 753 757) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,601 INFO L448 ceAbstractionStarter]: For program point L389-23(lines 389 398) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,601 INFO L448 ceAbstractionStarter]: For program point L389-24(lines 389 398) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,601 INFO L448 ceAbstractionStarter]: For program point L621-1(lines 600 663) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,601 INFO L448 ceAbstractionStarter]: For program point L753-5(lines 753 757) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,601 INFO L448 ceAbstractionStarter]: For program point L753-6(lines 753 757) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,601 INFO L448 ceAbstractionStarter]: For program point L389-26(lines 389 398) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,602 INFO L448 ceAbstractionStarter]: For program point L621-3(lines 600 663) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,602 INFO L448 ceAbstractionStarter]: For program point L753-8(lines 753 757) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,602 INFO L448 ceAbstractionStarter]: For program point L753-9(lines 753 757) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,602 INFO L448 ceAbstractionStarter]: For program point L390(lines 390 395) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,602 INFO L448 ceAbstractionStarter]: For program point L753-11(lines 753 757) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,602 INFO L448 ceAbstractionStarter]: For program point L753-12(lines 753 757) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,602 INFO L448 ceAbstractionStarter]: For program point L390-1(lines 390 395) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,603 INFO L451 ceAbstractionStarter]: At program point L324(lines 312 326) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,603 INFO L448 ceAbstractionStarter]: For program point L390-2(lines 390 395) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,603 INFO L451 ceAbstractionStarter]: At program point L324-1(lines 312 326) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,603 INFO L448 ceAbstractionStarter]: For program point L753-14(lines 753 757) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,603 INFO L448 ceAbstractionStarter]: For program point L390-3(lines 390 395) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,603 INFO L448 ceAbstractionStarter]: For program point L258(lines 258 266) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,603 INFO L451 ceAbstractionStarter]: At program point L324-2(lines 312 326) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,604 INFO L448 ceAbstractionStarter]: For program point L753-15(lines 753 757) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,604 INFO L448 ceAbstractionStarter]: For program point L390-4(lines 390 395) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,604 INFO L451 ceAbstractionStarter]: At program point L225(lines 225 229) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,604 INFO L451 ceAbstractionStarter]: At program point L324-3(lines 312 326) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,604 INFO L448 ceAbstractionStarter]: For program point L390-5(lines 390 395) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,604 INFO L451 ceAbstractionStarter]: At program point L324-4(lines 312 326) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,604 INFO L448 ceAbstractionStarter]: For program point L753-17(lines 753 757) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,604 INFO L448 ceAbstractionStarter]: For program point L390-6(lines 390 395) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,605 INFO L451 ceAbstractionStarter]: At program point L324-5(lines 312 326) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,605 INFO L448 ceAbstractionStarter]: For program point L753-18(lines 753 757) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,605 INFO L448 ceAbstractionStarter]: For program point L390-7(lines 390 395) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,605 INFO L451 ceAbstractionStarter]: At program point L324-6(lines 312 326) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,605 INFO L448 ceAbstractionStarter]: For program point L390-8(lines 390 395) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,605 INFO L451 ceAbstractionStarter]: At program point L324-7(lines 312 326) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,605 INFO L448 ceAbstractionStarter]: For program point L753-20(lines 753 757) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,605 INFO L448 ceAbstractionStarter]: For program point L753-21(lines 753 757) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,606 INFO L451 ceAbstractionStarter]: At program point L324-8(lines 312 326) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,606 INFO L448 ceAbstractionStarter]: For program point L753-23(lines 753 757) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,606 INFO L448 ceAbstractionStarter]: For program point L753-24(lines 753 757) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,606 INFO L448 ceAbstractionStarter]: For program point L753-26(lines 753 757) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,606 INFO L448 ceAbstractionStarter]: For program point L853-1(lines 817 880) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,606 INFO L448 ceAbstractionStarter]: For program point L523(lines 523 530) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,606 INFO L451 ceAbstractionStarter]: At program point L94(lines 57 108) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,606 INFO L451 ceAbstractionStarter]: At program point L61(lines 61 65) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,606 INFO L448 ceAbstractionStarter]: For program point L689-1(lines 668 731) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,607 INFO L451 ceAbstractionStarter]: At program point L656-1(lines 597 664) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,607 INFO L448 ceAbstractionStarter]: For program point L689-3(lines 668 731) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,607 INFO L451 ceAbstractionStarter]: At program point L656-3(lines 597 664) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,607 INFO L448 ceAbstractionStarter]: For program point L458(lines 458 483) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,607 INFO L448 ceAbstractionStarter]: For program point L458-1(lines 458 483) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,607 INFO L448 ceAbstractionStarter]: For program point L458-2(lines 458 483) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,607 INFO L451 ceAbstractionStarter]: At program point L161-1(lines 149 180) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,607 INFO L448 ceAbstractionStarter]: For program point L95(lines 95 99) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,608 INFO L448 ceAbstractionStarter]: For program point L426-1(lines 415 448) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,608 INFO L448 ceAbstractionStarter]: For program point L294(lines 294 303) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,608 INFO L451 ceAbstractionStarter]: At program point L261(lines 261 265) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,608 INFO L448 ceAbstractionStarter]: For program point L294-2(lines 294 303) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,608 INFO L448 ceAbstractionStarter]: For program point L294-3(lines 294 303) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,608 INFO L448 ceAbstractionStarter]: For program point L294-5(lines 294 303) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,608 INFO L448 ceAbstractionStarter]: For program point L294-6(lines 294 303) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,608 INFO L448 ceAbstractionStarter]: For program point L96(lines 96 98) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,609 INFO L448 ceAbstractionStarter]: For program point L294-8(lines 294 303) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,609 INFO L448 ceAbstractionStarter]: For program point L294-9(lines 294 303) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,609 INFO L448 ceAbstractionStarter]: For program point L294-11(lines 294 303) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,609 INFO L448 ceAbstractionStarter]: For program point L294-12(lines 294 303) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,609 INFO L448 ceAbstractionStarter]: For program point L294-14(lines 294 303) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,609 INFO L448 ceAbstractionStarter]: For program point L294-15(lines 294 303) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,609 INFO L448 ceAbstractionStarter]: For program point L823-1(lines 817 880) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,609 INFO L448 ceAbstractionStarter]: For program point L294-17(lines 294 303) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,609 INFO L448 ceAbstractionStarter]: For program point L294-18(lines 294 303) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,610 INFO L448 ceAbstractionStarter]: For program point L294-20(lines 294 303) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,610 INFO L448 ceAbstractionStarter]: For program point L294-21(lines 294 303) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,610 INFO L451 ceAbstractionStarter]: At program point L724-3(lines 665 732) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,610 INFO L448 ceAbstractionStarter]: For program point L294-23(lines 294 303) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,610 INFO L448 ceAbstractionStarter]: For program point L294-24(lines 294 303) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,610 INFO L448 ceAbstractionStarter]: For program point L294-26(lines 294 303) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,610 INFO L448 ceAbstractionStarter]: For program point L295(lines 295 300) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,610 INFO L448 ceAbstractionStarter]: For program point L295-1(lines 295 300) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,610 INFO L448 ceAbstractionStarter]: For program point L295-2(lines 295 300) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,611 INFO L448 ceAbstractionStarter]: For program point L295-3(lines 295 300) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,611 INFO L448 ceAbstractionStarter]: For program point L295-4(lines 295 300) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,611 INFO L448 ceAbstractionStarter]: For program point L295-5(lines 295 300) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,611 INFO L448 ceAbstractionStarter]: For program point L295-6(lines 295 300) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,611 INFO L448 ceAbstractionStarter]: For program point L295-7(lines 295 300) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,611 INFO L448 ceAbstractionStarter]: For program point L295-8(lines 295 300) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,611 INFO L448 ceAbstractionStarter]: For program point L626-1(lines 600 663) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,611 INFO L448 ceAbstractionStarter]: For program point L626-3(lines 600 663) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,612 INFO L451 ceAbstractionStarter]: At program point L362(lines 350 364) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,612 INFO L451 ceAbstractionStarter]: At program point L362-1(lines 350 364) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,612 INFO L451 ceAbstractionStarter]: At program point L362-2(lines 350 364) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,612 INFO L451 ceAbstractionStarter]: At program point L362-3(lines 350 364) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,612 INFO L451 ceAbstractionStarter]: At program point L362-4(lines 350 364) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,612 INFO L451 ceAbstractionStarter]: At program point L362-5(lines 350 364) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,612 INFO L451 ceAbstractionStarter]: At program point L197-1(lines 185 216) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,612 INFO L451 ceAbstractionStarter]: At program point L362-6(lines 350 364) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,613 INFO L451 ceAbstractionStarter]: At program point L362-7(lines 350 364) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,613 INFO L451 ceAbstractionStarter]: At program point L362-8(lines 350 364) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,613 INFO L448 ceAbstractionStarter]: For program point L858-1(lines 817 880) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,613 INFO L448 ceAbstractionStarter]: For program point L462(lines 462 482) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,613 INFO L448 ceAbstractionStarter]: For program point L462-1(lines 462 482) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,613 INFO L448 ceAbstractionStarter]: For program point L462-2(lines 462 482) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,613 INFO L448 ceAbstractionStarter]: For program point L694-1(lines 668 731) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,613 INFO L448 ceAbstractionStarter]: For program point L694-3(lines 668 731) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,614 INFO L451 ceAbstractionStarter]: At program point L562(lines 496 590) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,614 INFO L448 ceAbstractionStarter]: For program point L761(lines 761 765) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,614 INFO L448 ceAbstractionStarter]: For program point L761-2(lines 761 765) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,614 INFO L448 ceAbstractionStarter]: For program point L761-3(lines 761 765) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,614 INFO L448 ceAbstractionStarter]: For program point L761-5(lines 761 765) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,614 INFO L448 ceAbstractionStarter]: For program point L761-6(lines 761 765) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,614 INFO L448 ceAbstractionStarter]: For program point L761-8(lines 761 765) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,614 INFO L448 ceAbstractionStarter]: For program point L761-9(lines 761 765) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,614 INFO L448 ceAbstractionStarter]: For program point L431-1(lines 415 448) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,615 INFO L448 ceAbstractionStarter]: For program point L761-11(lines 761 765) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,615 INFO L448 ceAbstractionStarter]: For program point L761-12(lines 761 765) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,615 INFO L448 ceAbstractionStarter]: For program point L332(lines 332 341) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,615 INFO L448 ceAbstractionStarter]: For program point L761-14(lines 761 765) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,615 INFO L448 ceAbstractionStarter]: For program point L332-2(lines 332 341) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,615 INFO L448 ceAbstractionStarter]: For program point L761-15(lines 761 765) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,615 INFO L448 ceAbstractionStarter]: For program point L332-3(lines 332 341) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,615 INFO L451 ceAbstractionStarter]: At program point L233-1(lines 221 252) the Hoare annotation is: true 312.69/160.48 [2019-03-28 12:21:50,616 INFO L448 ceAbstractionStarter]: For program point L761-17(lines 761 765) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,616 INFO L448 ceAbstractionStarter]: For program point L332-5(lines 332 341) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,616 INFO L448 ceAbstractionStarter]: For program point L761-18(lines 761 765) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,616 INFO L448 ceAbstractionStarter]: For program point L332-6(lines 332 341) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,616 INFO L448 ceAbstractionStarter]: For program point L761-20(lines 761 765) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,616 INFO L448 ceAbstractionStarter]: For program point L332-8(lines 332 341) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,616 INFO L448 ceAbstractionStarter]: For program point L761-21(lines 761 765) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,616 INFO L448 ceAbstractionStarter]: For program point L332-9(lines 332 341) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,616 INFO L448 ceAbstractionStarter]: For program point L761-23(lines 761 765) no Hoare annotation was computed. 312.69/160.48 [2019-03-28 12:21:50,629 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.03 12:21:50 BasicIcfg 312.69/160.48 [2019-03-28 12:21:50,629 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- 312.69/160.48 [2019-03-28 12:21:50,630 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- 312.69/160.48 [2019-03-28 12:21:50,630 INFO L271 PluginConnector]: Initializing BuchiAutomizer... 312.69/160.48 [2019-03-28 12:21:50,633 INFO L276 PluginConnector]: BuchiAutomizer initialized 312.69/160.48 [2019-03-28 12:21:50,634 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis 312.69/160.48 [2019-03-28 12:21:50,634 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 28.03 12:21:47" (1/5) ... 312.69/160.48 [2019-03-28 12:21:50,635 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@19c37689 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.03 12:21:50, skipping insertion in model container 312.69/160.48 [2019-03-28 12:21:50,635 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis 312.69/160.48 [2019-03-28 12:21:50,635 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:21:48" (2/5) ... 312.69/160.48 [2019-03-28 12:21:50,635 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@19c37689 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.03 12:21:50, skipping insertion in model container 312.69/160.48 [2019-03-28 12:21:50,635 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis 312.69/160.48 [2019-03-28 12:21:50,636 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.03 12:21:49" (3/5) ... 312.69/160.48 [2019-03-28 12:21:50,636 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@19c37689 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 28.03 12:21:50, skipping insertion in model container 312.69/160.48 [2019-03-28 12:21:50,636 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis 312.69/160.48 [2019-03-28 12:21:50,636 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.blockencoding CFG 28.03 12:21:50" (4/5) ... 312.69/160.48 [2019-03-28 12:21:50,636 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@19c37689 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 28.03 12:21:50, skipping insertion in model container 312.69/160.48 [2019-03-28 12:21:50,637 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis 312.69/160.48 [2019-03-28 12:21:50,637 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.03 12:21:50" (5/5) ... 312.69/160.48 [2019-03-28 12:21:50,638 INFO L375 chiAutomizerObserver]: Analyzing ICFG theBenchmark.c_BEv2 312.69/160.48 [2019-03-28 12:21:50,663 INFO L133 ementStrategyFactory]: Using default assertion order modulation 312.69/160.48 [2019-03-28 12:21:50,663 INFO L374 BuchiCegarLoop]: Interprodecural is true 312.69/160.48 [2019-03-28 12:21:50,664 INFO L375 BuchiCegarLoop]: Hoare is true 312.69/160.48 [2019-03-28 12:21:50,664 INFO L376 BuchiCegarLoop]: Compute interpolants for ForwardPredicates 312.69/160.48 [2019-03-28 12:21:50,664 INFO L377 BuchiCegarLoop]: Backedges is STRAIGHT_LINE 312.69/160.48 [2019-03-28 12:21:50,664 INFO L378 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION 312.69/160.48 [2019-03-28 12:21:50,664 INFO L379 BuchiCegarLoop]: Difference is false 312.69/160.48 [2019-03-28 12:21:50,664 INFO L380 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA 312.69/160.48 [2019-03-28 12:21:50,664 INFO L383 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== 312.69/160.48 [2019-03-28 12:21:50,672 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 454 states. 312.69/160.48 [2019-03-28 12:21:50,710 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 387 312.69/160.48 [2019-03-28 12:21:50,710 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.48 [2019-03-28 12:21:50,710 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.48 [2019-03-28 12:21:50,721 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.48 [2019-03-28 12:21:50,722 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.48 [2019-03-28 12:21:50,722 INFO L442 BuchiCegarLoop]: ======== Iteration 1============ 312.69/160.48 [2019-03-28 12:21:50,722 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 454 states. 312.69/160.48 [2019-03-28 12:21:50,731 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 387 312.69/160.48 [2019-03-28 12:21:50,731 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.48 [2019-03-28 12:21:50,731 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.48 [2019-03-28 12:21:50,735 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.48 [2019-03-28 12:21:50,735 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.48 [2019-03-28 12:21:50,742 INFO L794 eck$LassoCheckResult]: Stem: 284#ULTIMATE.startENTRYtrue [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 139#L409true [3221] L409-->L416-1: Formula: (and (= v_~m_st~0_5 2) (< v_~m_i~0_4 1)) InVars {~m_i~0=v_~m_i~0_4} OutVars{~m_st~0=v_~m_st~0_5, ~m_i~0=v_~m_i~0_4} AuxVars[] AssignedVars[~m_st~0] 384#L416-1true [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 181#L421-1true [3225] L421-1-->L426-1: Formula: (and (> 1 v_~t2_i~0_4) (= v_~t2_st~0_5 2)) InVars {~t2_i~0=v_~t2_i~0_4} OutVars{~t2_i~0=v_~t2_i~0_4, ~t2_st~0=v_~t2_st~0_5} AuxVars[] AssignedVars[~t2_st~0] 421#L426-1true [3227] L426-1-->L431-1: Formula: (and (= v_~t3_st~0_5 2) (< v_~t3_i~0_4 1)) InVars {~t3_i~0=v_~t3_i~0_4} OutVars{~t3_st~0=v_~t3_st~0_5, ~t3_i~0=v_~t3_i~0_4} AuxVars[] AssignedVars[~t3_st~0] 140#L431-1true [3229] L431-1-->L436-1: Formula: (and (< v_~t4_i~0_4 1) (= v_~t4_st~0_5 2)) InVars {~t4_i~0=v_~t4_i~0_4} OutVars{~t4_i~0=v_~t4_i~0_4, ~t4_st~0=v_~t4_st~0_5} AuxVars[] AssignedVars[~t4_st~0] 342#L436-1true [3231] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_5 2) (> v_~t5_i~0_4 1)) InVars {~t5_i~0=v_~t5_i~0_4} OutVars{~t5_i~0=v_~t5_i~0_4, ~t5_st~0=v_~t5_st~0_5} AuxVars[] AssignedVars[~t5_st~0] 167#L441-1true [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 360#L601-1true [2765] L601-1-->L606-1: Formula: (and (= v_~T1_E~0_2 1) (= 0 v_~T1_E~0_3)) InVars {~T1_E~0=v_~T1_E~0_3} OutVars{~T1_E~0=v_~T1_E~0_2} AuxVars[] AssignedVars[~T1_E~0] 170#L606-1true [2407] L606-1-->L611-1: Formula: (and (= 0 v_~T2_E~0_3) (= v_~T2_E~0_2 1)) InVars {~T2_E~0=v_~T2_E~0_3} OutVars{~T2_E~0=v_~T2_E~0_2} AuxVars[] AssignedVars[~T2_E~0] 79#L611-1true [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 298#L616-1true [3241] L616-1-->L621-1: Formula: (< v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 8#L621-1true [3243] L621-1-->L626-1: Formula: (< v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 264#L626-1true [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 63#L631-1true [3247] L631-1-->L636-1: Formula: (< v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 389#L636-1true [2819] L636-1-->L641-1: Formula: (and (= v_~E_2~0_3 0) (= v_~E_2~0_2 1)) InVars {~E_2~0=v_~E_2~0_3} OutVars{~E_2~0=v_~E_2~0_2} AuxVars[] AssignedVars[~E_2~0] 197#L641-1true [2474] L641-1-->L646-1: Formula: (and (= v_~E_3~0_3 0) (= v_~E_3~0_2 1)) InVars {~E_3~0=v_~E_3~0_3} OutVars{~E_3~0=v_~E_3~0_2} AuxVars[] AssignedVars[~E_3~0] 455#L646-1true [2935] L646-1-->L651-1: Formula: (and (= v_~E_4~0_2 1) (= v_~E_4~0_3 0)) InVars {~E_4~0=v_~E_4~0_3} OutVars{~E_4~0=v_~E_4~0_2} AuxVars[] AssignedVars[~E_4~0] 162#L651-1true [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 371#L656-1true [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 410#L294true [2854] L294-->L295: Formula: (= v_~m_pc~0_2 1) InVars {~m_pc~0=v_~m_pc~0_2} OutVars{~m_pc~0=v_~m_pc~0_2} AuxVars[] AssignedVars[] 272#L295true [2595] L295-->L305: Formula: (and (= v_~E_M~0_5 1) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_4 1)) InVars {~E_M~0=v_~E_M~0_5} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_4, ~E_M~0=v_~E_M~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 429#L305true [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 448#L745true [3261] L745-->L745-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_5) (= v_~m_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} OutVars{~m_st~0=v_~m_st~0_6, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} AuxVars[] AssignedVars[~m_st~0] 451#L745-2true [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 112#L313true [2301] L313-->L314: Formula: (= v_~t1_pc~0_2 1) InVars {~t1_pc~0=v_~t1_pc~0_2} OutVars{~t1_pc~0=v_~t1_pc~0_2} AuxVars[] AssignedVars[] 76#L314true [2241] L314-->L324: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_4 1) (= v_~E_1~0_5 1)) InVars {~E_1~0=v_~E_1~0_5} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_4, ~E_1~0=v_~E_1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 110#L324true [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 16#L753true [3267] L753-->L753-2: Formula: (and (> 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_5) (= v_~t1_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_5, ~t1_st~0=v_~t1_st~0_6} AuxVars[] AssignedVars[~t1_st~0] 19#L753-2true [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 144#L332true [3269] L332-->L332-2: Formula: (> v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 148#L332-2true [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 143#L343true [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 158#L761true [3273] L761-->L761-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_5) (= v_~t2_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5, ~t2_st~0=v_~t2_st~0_6} AuxVars[] AssignedVars[~t2_st~0] 159#L761-2true [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 259#L351true [2567] L351-->L352: Formula: (= 1 v_~t3_pc~0_2) InVars {~t3_pc~0=v_~t3_pc~0_2} OutVars{~t3_pc~0=v_~t3_pc~0_2} AuxVars[] AssignedVars[] 294#L352true [2655] L352-->L362: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_4 1) (= v_~E_3~0_5 1)) InVars {~E_3~0=v_~E_3~0_5} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_4, ~E_3~0=v_~E_3~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 258#L362true [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 268#L769true [3279] L769-->L769-2: Formula: (and (= v_~t3_st~0_6 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_5)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} OutVars{~t3_st~0=v_~t3_st~0_6, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} AuxVars[] AssignedVars[~t3_st~0] 269#L769-2true [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 348#L370true [3281] L370-->L370-2: Formula: (> v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 352#L370-2true [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 345#L381true [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 367#L777true [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 368#L777-2true [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 56#L389true [2193] L389-->L390: Formula: (= 1 v_~t5_pc~0_2) InVars {~t5_pc~0=v_~t5_pc~0_2} OutVars{~t5_pc~0=v_~t5_pc~0_2} AuxVars[] AssignedVars[] 134#L390true [2343] L390-->L400: Formula: (and (= v_~E_5~0_5 1) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4 1)) InVars {~E_5~0=v_~E_5~0_5} OutVars{~E_5~0=v_~E_5~0_5, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 54#L400true [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 67#L785true [3291] L785-->L785-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_5) (= v_~t5_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} OutVars{~t5_st~0=v_~t5_st~0_6, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} AuxVars[] AssignedVars[~t5_st~0] 69#L785-2true [3293] L785-2-->L669-1: Formula: (> 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 387#L669-1true [3295] L669-1-->L674-1: Formula: (> 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 196#L674-1true [2472] L674-1-->L679-1: Formula: (and (= 1 v_~T2_E~0_6) (= v_~T2_E~0_5 2)) InVars {~T2_E~0=v_~T2_E~0_6} OutVars{~T2_E~0=v_~T2_E~0_5} AuxVars[] AssignedVars[~T2_E~0] 452#L679-1true [3299] L679-1-->L684-1: Formula: (< v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 161#L684-1true [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 370#L689-1true [2782] L689-1-->L694-1: Formula: (and (= v_~T5_E~0_6 1) (= v_~T5_E~0_5 2)) InVars {~T5_E~0=v_~T5_E~0_6} OutVars{~T5_E~0=v_~T5_E~0_5} AuxVars[] AssignedVars[~T5_E~0] 279#L694-1true [3305] L694-1-->L699-1: Formula: (< v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 91#L699-1true [3307] L699-1-->L704-1: Formula: (< v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 308#L704-1true [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 3#L709-1true [3311] L709-1-->L714-1: Formula: (< v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 260#L714-1true [2569] L714-1-->L719-1: Formula: (and (= v_~E_4~0_8 1) (= v_~E_4~0_7 2)) InVars {~E_4~0=v_~E_4~0_8} OutVars{~E_4~0=v_~E_4~0_7} AuxVars[] AssignedVars[~E_4~0] 59#L719-1true [2198] L719-1-->L930-1: Formula: (and (= v_~E_5~0_8 1) (= v_~E_5~0_7 2)) InVars {~E_5~0=v_~E_5~0_8} OutVars{~E_5~0=v_~E_5~0_7} AuxVars[] AssignedVars[~E_5~0] 96#L930-1true 312.69/160.48 [2019-03-28 12:21:50,745 INFO L796 eck$LassoCheckResult]: Loop: 96#L930-1true [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 65#L576true [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 192#L454true [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 155#L486true [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 85#L501true [3784] L501-->L601-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 362#L601-2true [2768] L601-2-->L601-4: Formula: (and (= v_~M_E~0_8 1) (= 0 v_~M_E~0_9)) InVars {~M_E~0=v_~M_E~0_9} OutVars{~M_E~0=v_~M_E~0_8} AuxVars[] AssignedVars[~M_E~0] 365#L601-4true [2773] L601-4-->L606-3: Formula: (and (= v_~T1_E~0_8 1) (= 0 v_~T1_E~0_9)) InVars {~T1_E~0=v_~T1_E~0_9} OutVars{~T1_E~0=v_~T1_E~0_8} AuxVars[] AssignedVars[~T1_E~0] 173#L606-3true [2413] L606-3-->L611-3: Formula: (and (= v_~T2_E~0_8 1) (= 0 v_~T2_E~0_9)) InVars {~T2_E~0=v_~T2_E~0_9} OutVars{~T2_E~0=v_~T2_E~0_8} AuxVars[] AssignedVars[~T2_E~0] 84#L611-3true [2256] L611-3-->L616-3: Formula: (and (= v_~T3_E~0_8 1) (= v_~T3_E~0_9 0)) InVars {~T3_E~0=v_~T3_E~0_9} OutVars{~T3_E~0=v_~T3_E~0_8} AuxVars[] AssignedVars[~T3_E~0] 300#L616-3true [3338] L616-3-->L621-3: Formula: (< v_~T4_E~0_10 0) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 12#L621-3true [3346] L621-3-->L626-3: Formula: (< 0 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 266#L626-3true [2580] L626-3-->L631-3: Formula: (and (= v_~E_M~0_24 1) (= 0 v_~E_M~0_25)) InVars {~E_M~0=v_~E_M~0_25} OutVars{~E_M~0=v_~E_M~0_24} AuxVars[] AssignedVars[~E_M~0] 48#L631-3true [2180] L631-3-->L636-3: Formula: (and (= v_~E_1~0_24 1) (= 0 v_~E_1~0_25)) InVars {~E_1~0=v_~E_1~0_25} OutVars{~E_1~0=v_~E_1~0_24} AuxVars[] AssignedVars[~E_1~0] 381#L636-3true [3376] L636-3-->L641-3: Formula: (< 0 v_~E_2~0_26) InVars {~E_2~0=v_~E_2~0_26} OutVars{~E_2~0=v_~E_2~0_26} AuxVars[] AssignedVars[] 188#L641-3true [2455] L641-3-->L646-3: Formula: (and (= 0 v_~E_3~0_25) (= v_~E_3~0_24 1)) InVars {~E_3~0=v_~E_3~0_25} OutVars{~E_3~0=v_~E_3~0_24} AuxVars[] AssignedVars[~E_3~0] 442#L646-3true [2912] L646-3-->L651-3: Formula: (and (= 0 v_~E_4~0_25) (= v_~E_4~0_24 1)) InVars {~E_4~0=v_~E_4~0_25} OutVars{~E_4~0=v_~E_4~0_24} AuxVars[] AssignedVars[~E_4~0] 153#L651-3true [3410] L651-3-->L656-3: Formula: (> 0 v_~E_5~0_26) InVars {~E_5~0=v_~E_5~0_26} OutVars{~E_5~0=v_~E_5~0_26} AuxVars[] AssignedVars[] 361#L656-3true [2767] L656-3-->L294-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_37, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_37, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_22|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_22|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_22|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_37, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_37, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_22|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_22|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_22|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_22|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_37, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_37, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_37} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 382#L294-21true [2808] L294-21-->L295-7: Formula: (= v_~m_pc~0_21 1) InVars {~m_pc~0=v_~m_pc~0_21} OutVars{~m_pc~0=v_~m_pc~0_21} AuxVars[] AssignedVars[] 274#L295-7true [2602] L295-7-->L305-7: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_40 1) (= 1 v_~E_M~0_27)) InVars {~E_M~0=v_~E_M~0_27} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_40, ~E_M~0=v_~E_M~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 419#L305-7true [3806] L305-7-->L745-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 397#L745-21true [2835] L745-21-->L745-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_42) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} AuxVars[] AssignedVars[] 400#L745-23true [2838] L745-23-->L313-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_43, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 77#L313-21true [3468] L313-21-->L313-23: Formula: (> v_~t1_pc~0_22 1) InVars {~t1_pc~0=v_~t1_pc~0_22} OutVars{~t1_pc~0=v_~t1_pc~0_22} AuxVars[] AssignedVars[] 80#L313-23true [2249] L313-23-->L324-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 104#L324-7true [3813] L324-7-->L753-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 105#L753-21true [2292] L753-21-->L753-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} AuxVars[] AssignedVars[] 109#L753-23true [2297] L753-23-->L332-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_22|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 195#L332-21true [2470] L332-21-->L333-7: Formula: (= 1 v_~t2_pc~0_21) InVars {~t2_pc~0=v_~t2_pc~0_21} OutVars{~t2_pc~0=v_~t2_pc~0_21} AuxVars[] AssignedVars[] 179#L333-7true [2431] L333-7-->L343-7: Formula: (and (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_46 1) (= 1 v_~E_2~0_27)) InVars {~E_2~0=v_~E_2~0_27} OutVars{~E_2~0=v_~E_2~0_27, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_46} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 227#L343-7true [3820] L343-7-->L761-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 207#L761-21true [3538] L761-21-->L761-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___1~0_41 0) (= v_~t2_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41, ~t2_st~0=v_~t2_st~0_19} AuxVars[] AssignedVars[~t2_st~0] 209#L761-23true [2493] L761-23-->L351-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_22|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 307#L351-21true [3552] L351-21-->L351-23: Formula: (< v_~t3_pc~0_22 1) InVars {~t3_pc~0=v_~t3_pc~0_22} OutVars{~t3_pc~0=v_~t3_pc~0_22} AuxVars[] AssignedVars[] 296#L351-23true [2660] L351-23-->L362-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 233#L362-7true [3827] L362-7-->L769-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 237#L769-21true [2534] L769-21-->L769-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} AuxVars[] AssignedVars[] 239#L769-23true [2537] L769-23-->L370-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_43, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 450#L370-21true [3594] L370-21-->L370-23: Formula: (< 1 v_~t4_pc~0_22) InVars {~t4_pc~0=v_~t4_pc~0_22} OutVars{~t4_pc~0=v_~t4_pc~0_22} AuxVars[] AssignedVars[] 454#L370-23true [2934] L370-23-->L381-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 334#L381-7true [3834] L381-7-->L777-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 320#L777-21true [2705] L777-21-->L777-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} AuxVars[] AssignedVars[] 322#L777-23true [2708] L777-23-->L389-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_22|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 18#L389-21true [2132] L389-21-->L390-7: Formula: (= v_~t5_pc~0_21 1) InVars {~t5_pc~0=v_~t5_pc~0_21} OutVars{~t5_pc~0=v_~t5_pc~0_21} AuxVars[] AssignedVars[] 128#L390-7true [2330] L390-7-->L400-7: Formula: (and (= 1 v_~E_5~0_27) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46 1)) InVars {~E_5~0=v_~E_5~0_27} OutVars{~E_5~0=v_~E_5~0_27, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 27#L400-7true [3837] L400-7-->L785-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 32#L785-21true [3654] L785-21-->L785-23: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_41 0) (= v_~t5_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} OutVars{~t5_st~0=v_~t5_st~0_19, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} AuxVars[] AssignedVars[~t5_st~0] 34#L785-23true [2161] L785-23-->L669-3: Formula: (and (= v_~M_E~0_12 1) (= v_~M_E~0_11 2)) InVars {~M_E~0=v_~M_E~0_12} OutVars{~M_E~0=v_~M_E~0_11} AuxVars[] AssignedVars[~M_E~0] 391#L669-3true [2824] L669-3-->L674-3: Formula: (and (= v_~T1_E~0_11 2) (= v_~T1_E~0_12 1)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 199#L674-3true [2477] L674-3-->L679-3: Formula: (and (= 1 v_~T2_E~0_12) (= v_~T2_E~0_11 2)) InVars {~T2_E~0=v_~T2_E~0_12} OutVars{~T2_E~0=v_~T2_E~0_11} AuxVars[] AssignedVars[~T2_E~0] 440#L679-3true [3664] L679-3-->L684-3: Formula: (< 1 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 151#L684-3true [3666] L684-3-->L689-3: Formula: (> v_~T4_E~0_13 1) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 357#L689-3true [3668] L689-3-->L694-3: Formula: (< 1 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 169#L694-3true [2405] L694-3-->L699-3: Formula: (and (= 1 v_~E_M~0_30) (= v_~E_M~0_29 2)) InVars {~E_M~0=v_~E_M~0_30} OutVars{~E_M~0=v_~E_M~0_29} AuxVars[] AssignedVars[~E_M~0] 78#L699-3true [2245] L699-3-->L704-3: Formula: (and (= v_~E_1~0_29 2) (= 1 v_~E_1~0_30)) InVars {~E_1~0=v_~E_1~0_30} OutVars{~E_1~0=v_~E_1~0_29} AuxVars[] AssignedVars[~E_1~0] 297#L704-3true [2661] L704-3-->L709-3: Formula: (and (= v_~E_2~0_29 2) (= 1 v_~E_2~0_30)) InVars {~E_2~0=v_~E_2~0_30} OutVars{~E_2~0=v_~E_2~0_29} AuxVars[] AssignedVars[~E_2~0] 7#L709-3true [2114] L709-3-->L714-3: Formula: (and (= v_~E_3~0_29 2) (= 1 v_~E_3~0_30)) InVars {~E_3~0=v_~E_3~0_30} OutVars{~E_3~0=v_~E_3~0_29} AuxVars[] AssignedVars[~E_3~0] 262#L714-3true [2573] L714-3-->L719-3: Formula: (and (= v_~E_4~0_29 2) (= 1 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 62#L719-3true [3680] L719-3-->L724-3: Formula: (> 1 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 388#L724-3true [2818] L724-3-->L454-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_23} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 193#L454-1true [2466] L454-1-->L486-1: Formula: (and (= 0 v_~m_st~0_20) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26 1)) InVars {~m_st~0=v_~m_st~0_20} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 157#L486-1true [3838] L486-1-->L949: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret15, ULTIMATE.start_start_simulation_~tmp~3] 216#L949true [3688] L949-->L949-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_1) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} AuxVars[] AssignedVars[] 200#L949-1true [2479] L949-1-->L454-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_1} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 182#L454-2true [2438] L454-2-->L486-2: Formula: (and (= v_~m_st~0_2 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4 1)) InVars {~m_st~0=v_~m_st~0_2} OutVars{~m_st~0=v_~m_st~0_2, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 138#L486-2true [3840] L486-2-->L904: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 163#L904true [2393] L904-->L911: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 404#L911true [3851] L911-->L930-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_6|, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 96#L930-1true 312.69/160.48 [2019-03-28 12:21:50,752 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.48 [2019-03-28 12:21:50,753 INFO L82 PathProgramCache]: Analyzing trace with hash -1232512505, now seen corresponding path program 1 times 312.69/160.48 [2019-03-28 12:21:50,755 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.48 [2019-03-28 12:21:50,755 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.48 [2019-03-28 12:21:50,776 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:50,776 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:50,776 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:50,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.48 [2019-03-28 12:21:50,874 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.48 [2019-03-28 12:21:50,876 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.48 [2019-03-28 12:21:50,877 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 312.69/160.48 [2019-03-28 12:21:50,881 INFO L799 eck$LassoCheckResult]: stem already infeasible 312.69/160.48 [2019-03-28 12:21:50,882 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.48 [2019-03-28 12:21:50,882 INFO L82 PathProgramCache]: Analyzing trace with hash 447377326, now seen corresponding path program 1 times 312.69/160.48 [2019-03-28 12:21:50,882 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.48 [2019-03-28 12:21:50,882 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.48 [2019-03-28 12:21:50,883 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:50,883 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:50,883 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:50,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.48 [2019-03-28 12:21:50,958 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.48 [2019-03-28 12:21:50,958 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.48 [2019-03-28 12:21:50,958 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 312.69/160.48 [2019-03-28 12:21:50,960 INFO L811 eck$LassoCheckResult]: loop already infeasible 312.69/160.48 [2019-03-28 12:21:50,975 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 312.69/160.48 [2019-03-28 12:21:50,976 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 312.69/160.48 [2019-03-28 12:21:50,978 INFO L87 Difference]: Start difference. First operand 454 states. Second operand 3 states. 312.69/160.48 [2019-03-28 12:21:51,588 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.48 [2019-03-28 12:21:51,589 INFO L93 Difference]: Finished difference Result 454 states and 1004 transitions. 312.69/160.48 [2019-03-28 12:21:51,589 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 312.69/160.48 [2019-03-28 12:21:51,592 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 454 states and 1004 transitions. 312.69/160.48 [2019-03-28 12:21:51,598 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 387 312.69/160.48 [2019-03-28 12:21:51,608 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 454 states to 454 states and 1004 transitions. 312.69/160.48 [2019-03-28 12:21:51,610 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 454 312.69/160.48 [2019-03-28 12:21:51,611 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 454 312.69/160.48 [2019-03-28 12:21:51,612 INFO L73 IsDeterministic]: Start isDeterministic. Operand 454 states and 1004 transitions. 312.69/160.48 [2019-03-28 12:21:51,616 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.48 [2019-03-28 12:21:51,616 INFO L706 BuchiCegarLoop]: Abstraction has 454 states and 1004 transitions. 312.69/160.48 [2019-03-28 12:21:51,636 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 454 states and 1004 transitions. 312.69/160.48 [2019-03-28 12:21:51,670 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 454 to 454. 312.69/160.48 [2019-03-28 12:21:51,670 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 454 states. 312.69/160.48 [2019-03-28 12:21:51,673 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 454 states to 454 states and 1004 transitions. 312.69/160.48 [2019-03-28 12:21:51,674 INFO L729 BuchiCegarLoop]: Abstraction has 454 states and 1004 transitions. 312.69/160.48 [2019-03-28 12:21:51,674 INFO L609 BuchiCegarLoop]: Abstraction has 454 states and 1004 transitions. 312.69/160.48 [2019-03-28 12:21:51,674 INFO L442 BuchiCegarLoop]: ======== Iteration 2============ 312.69/160.48 [2019-03-28 12:21:51,675 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 454 states and 1004 transitions. 312.69/160.48 [2019-03-28 12:21:51,678 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 387 312.69/160.48 [2019-03-28 12:21:51,678 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.48 [2019-03-28 12:21:51,678 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.48 [2019-03-28 12:21:51,680 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.48 [2019-03-28 12:21:51,680 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.48 [2019-03-28 12:21:51,682 INFO L794 eck$LassoCheckResult]: Stem: 1288#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 1104#L409 [3220] L409-->L416-1: Formula: (and (= v_~m_st~0_5 2) (> v_~m_i~0_4 1)) InVars {~m_i~0=v_~m_i~0_4} OutVars{~m_st~0=v_~m_st~0_5, ~m_i~0=v_~m_i~0_4} AuxVars[] AssignedVars[~m_st~0] 1105#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 1172#L421-1 [3225] L421-1-->L426-1: Formula: (and (> 1 v_~t2_i~0_4) (= v_~t2_st~0_5 2)) InVars {~t2_i~0=v_~t2_i~0_4} OutVars{~t2_i~0=v_~t2_i~0_4, ~t2_st~0=v_~t2_st~0_5} AuxVars[] AssignedVars[~t2_st~0] 1173#L426-1 [3227] L426-1-->L431-1: Formula: (and (= v_~t3_st~0_5 2) (< v_~t3_i~0_4 1)) InVars {~t3_i~0=v_~t3_i~0_4} OutVars{~t3_st~0=v_~t3_st~0_5, ~t3_i~0=v_~t3_i~0_4} AuxVars[] AssignedVars[~t3_st~0] 1106#L431-1 [3229] L431-1-->L436-1: Formula: (and (< v_~t4_i~0_4 1) (= v_~t4_st~0_5 2)) InVars {~t4_i~0=v_~t4_i~0_4} OutVars{~t4_i~0=v_~t4_i~0_4, ~t4_st~0=v_~t4_st~0_5} AuxVars[] AssignedVars[~t4_st~0] 1107#L436-1 [3231] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_5 2) (> v_~t5_i~0_4 1)) InVars {~t5_i~0=v_~t5_i~0_4} OutVars{~t5_i~0=v_~t5_i~0_4, ~t5_st~0=v_~t5_st~0_5} AuxVars[] AssignedVars[~t5_st~0] 1145#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 1146#L601-1 [2765] L601-1-->L606-1: Formula: (and (= v_~T1_E~0_2 1) (= 0 v_~T1_E~0_3)) InVars {~T1_E~0=v_~T1_E~0_3} OutVars{~T1_E~0=v_~T1_E~0_2} AuxVars[] AssignedVars[~T1_E~0] 1149#L606-1 [2407] L606-1-->L611-1: Formula: (and (= 0 v_~T2_E~0_3) (= v_~T2_E~0_2 1)) InVars {~T2_E~0=v_~T2_E~0_3} OutVars{~T2_E~0=v_~T2_E~0_2} AuxVars[] AssignedVars[~T2_E~0] 1051#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 1052#L616-1 [3241] L616-1-->L621-1: Formula: (< v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 930#L621-1 [3243] L621-1-->L626-1: Formula: (< v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 931#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 1016#L631-1 [3247] L631-1-->L636-1: Formula: (< v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 1017#L636-1 [2819] L636-1-->L641-1: Formula: (and (= v_~E_2~0_3 0) (= v_~E_2~0_2 1)) InVars {~E_2~0=v_~E_2~0_3} OutVars{~E_2~0=v_~E_2~0_2} AuxVars[] AssignedVars[~E_2~0] 1191#L641-1 [2474] L641-1-->L646-1: Formula: (and (= v_~E_3~0_3 0) (= v_~E_3~0_2 1)) InVars {~E_3~0=v_~E_3~0_3} OutVars{~E_3~0=v_~E_3~0_2} AuxVars[] AssignedVars[~E_3~0] 1192#L646-1 [2935] L646-1-->L651-1: Formula: (and (= v_~E_4~0_2 1) (= v_~E_4~0_3 0)) InVars {~E_4~0=v_~E_4~0_3} OutVars{~E_4~0=v_~E_4~0_2} AuxVars[] AssignedVars[~E_4~0] 1137#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 1138#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 1348#L294 [2854] L294-->L295: Formula: (= v_~m_pc~0_2 1) InVars {~m_pc~0=v_~m_pc~0_2} OutVars{~m_pc~0=v_~m_pc~0_2} AuxVars[] AssignedVars[] 1261#L295 [2595] L295-->L305: Formula: (and (= v_~E_M~0_5 1) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_4 1)) InVars {~E_M~0=v_~E_M~0_5} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_4, ~E_M~0=v_~E_M~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 1262#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 1367#L745 [3261] L745-->L745-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_5) (= v_~m_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} OutVars{~m_st~0=v_~m_st~0_6, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} AuxVars[] AssignedVars[~m_st~0] 1372#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 1087#L313 [2301] L313-->L314: Formula: (= v_~t1_pc~0_2 1) InVars {~t1_pc~0=v_~t1_pc~0_2} OutVars{~t1_pc~0=v_~t1_pc~0_2} AuxVars[] AssignedVars[] 1043#L314 [2241] L314-->L324: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_4 1) (= v_~E_1~0_5 1)) InVars {~E_1~0=v_~E_1~0_5} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_4, ~E_1~0=v_~E_1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 1045#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 945#L753 [3267] L753-->L753-2: Formula: (and (> 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_5) (= v_~t1_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_5, ~t1_st~0=v_~t1_st~0_6} AuxVars[] AssignedVars[~t1_st~0] 946#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 950#L332 [3269] L332-->L332-2: Formula: (> v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 1114#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 1112#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 1113#L761 [3273] L761-->L761-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_5) (= v_~t2_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5, ~t2_st~0=v_~t2_st~0_6} AuxVars[] AssignedVars[~t2_st~0] 1133#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 1134#L351 [2567] L351-->L352: Formula: (= 1 v_~t3_pc~0_2) InVars {~t3_pc~0=v_~t3_pc~0_2} OutVars{~t3_pc~0=v_~t3_pc~0_2} AuxVars[] AssignedVars[] 1250#L352 [2655] L352-->L362: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_4 1) (= v_~E_3~0_5 1)) InVars {~E_3~0=v_~E_3~0_5} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_4, ~E_3~0=v_~E_3~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 1232#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 1249#L769 [3279] L769-->L769-2: Formula: (and (= v_~t3_st~0_6 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_5)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} OutVars{~t3_st~0=v_~t3_st~0_6, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} AuxVars[] AssignedVars[~t3_st~0] 1253#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 1254#L370 [3281] L370-->L370-2: Formula: (> v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 1337#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 1333#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 1334#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 1347#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 1007#L389 [2193] L389-->L390: Formula: (= 1 v_~t5_pc~0_2) InVars {~t5_pc~0=v_~t5_pc~0_2} OutVars{~t5_pc~0=v_~t5_pc~0_2} AuxVars[] AssignedVars[] 1008#L390 [2343] L390-->L400: Formula: (and (= v_~E_5~0_5 1) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4 1)) InVars {~E_5~0=v_~E_5~0_5} OutVars{~E_5~0=v_~E_5~0_5, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 977#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 1003#L785 [3291] L785-->L785-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_5) (= v_~t5_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} OutVars{~t5_st~0=v_~t5_st~0_6, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} AuxVars[] AssignedVars[~t5_st~0] 1023#L785-2 [3293] L785-2-->L669-1: Formula: (> 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 1025#L669-1 [3295] L669-1-->L674-1: Formula: (> 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 1189#L674-1 [2472] L674-1-->L679-1: Formula: (and (= 1 v_~T2_E~0_6) (= v_~T2_E~0_5 2)) InVars {~T2_E~0=v_~T2_E~0_6} OutVars{~T2_E~0=v_~T2_E~0_5} AuxVars[] AssignedVars[~T2_E~0] 1190#L679-1 [3299] L679-1-->L684-1: Formula: (< v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 1135#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 1136#L689-1 [2782] L689-1-->L694-1: Formula: (and (= v_~T5_E~0_6 1) (= v_~T5_E~0_5 2)) InVars {~T5_E~0=v_~T5_E~0_6} OutVars{~T5_E~0=v_~T5_E~0_5} AuxVars[] AssignedVars[~T5_E~0] 1282#L694-1 [3305] L694-1-->L699-1: Formula: (< v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 1072#L699-1 [3307] L699-1-->L704-1: Formula: (< v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 1073#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 919#L709-1 [3311] L709-1-->L714-1: Formula: (< v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 920#L714-1 [2569] L714-1-->L719-1: Formula: (and (= v_~E_4~0_8 1) (= v_~E_4~0_7 2)) InVars {~E_4~0=v_~E_4~0_8} OutVars{~E_4~0=v_~E_4~0_7} AuxVars[] AssignedVars[~E_4~0] 1010#L719-1 [2198] L719-1-->L930-1: Formula: (and (= v_~E_5~0_8 1) (= v_~E_5~0_7 2)) InVars {~E_5~0=v_~E_5~0_8} OutVars{~E_5~0=v_~E_5~0_7} AuxVars[] AssignedVars[~E_5~0] 1011#L930-1 312.69/160.48 [2019-03-28 12:21:51,684 INFO L796 eck$LassoCheckResult]: Loop: 1011#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 1018#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 1019#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 998#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 1063#L501 [3784] L501-->L601-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 1064#L601-2 [2768] L601-2-->L601-4: Formula: (and (= v_~M_E~0_8 1) (= 0 v_~M_E~0_9)) InVars {~M_E~0=v_~M_E~0_9} OutVars{~M_E~0=v_~M_E~0_8} AuxVars[] AssignedVars[~M_E~0] 1346#L601-4 [2773] L601-4-->L606-3: Formula: (and (= v_~T1_E~0_8 1) (= 0 v_~T1_E~0_9)) InVars {~T1_E~0=v_~T1_E~0_9} OutVars{~T1_E~0=v_~T1_E~0_8} AuxVars[] AssignedVars[~T1_E~0] 1152#L606-3 [2413] L606-3-->L611-3: Formula: (and (= v_~T2_E~0_8 1) (= 0 v_~T2_E~0_9)) InVars {~T2_E~0=v_~T2_E~0_9} OutVars{~T2_E~0=v_~T2_E~0_8} AuxVars[] AssignedVars[~T2_E~0] 1061#L611-3 [2256] L611-3-->L616-3: Formula: (and (= v_~T3_E~0_8 1) (= v_~T3_E~0_9 0)) InVars {~T3_E~0=v_~T3_E~0_9} OutVars{~T3_E~0=v_~T3_E~0_8} AuxVars[] AssignedVars[~T3_E~0] 1062#L616-3 [3338] L616-3-->L621-3: Formula: (< v_~T4_E~0_10 0) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 936#L621-3 [3346] L621-3-->L626-3: Formula: (< 0 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 937#L626-3 [2580] L626-3-->L631-3: Formula: (and (= v_~E_M~0_24 1) (= 0 v_~E_M~0_25)) InVars {~E_M~0=v_~E_M~0_25} OutVars{~E_M~0=v_~E_M~0_24} AuxVars[] AssignedVars[~E_M~0] 992#L631-3 [2180] L631-3-->L636-3: Formula: (and (= v_~E_1~0_24 1) (= 0 v_~E_1~0_25)) InVars {~E_1~0=v_~E_1~0_25} OutVars{~E_1~0=v_~E_1~0_24} AuxVars[] AssignedVars[~E_1~0] 993#L636-3 [3376] L636-3-->L641-3: Formula: (< 0 v_~E_2~0_26) InVars {~E_2~0=v_~E_2~0_26} OutVars{~E_2~0=v_~E_2~0_26} AuxVars[] AssignedVars[] 1183#L641-3 [2455] L641-3-->L646-3: Formula: (and (= 0 v_~E_3~0_25) (= v_~E_3~0_24 1)) InVars {~E_3~0=v_~E_3~0_25} OutVars{~E_3~0=v_~E_3~0_24} AuxVars[] AssignedVars[~E_3~0] 1184#L646-3 [2912] L646-3-->L651-3: Formula: (and (= 0 v_~E_4~0_25) (= v_~E_4~0_24 1)) InVars {~E_4~0=v_~E_4~0_25} OutVars{~E_4~0=v_~E_4~0_24} AuxVars[] AssignedVars[~E_4~0] 1128#L651-3 [3410] L651-3-->L656-3: Formula: (> 0 v_~E_5~0_26) InVars {~E_5~0=v_~E_5~0_26} OutVars{~E_5~0=v_~E_5~0_26} AuxVars[] AssignedVars[] 1129#L656-3 [2767] L656-3-->L294-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_37, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_37, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_22|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_22|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_22|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_37, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_37, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_22|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_22|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_22|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_22|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_37, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_37, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_37} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 1345#L294-21 [2808] L294-21-->L295-7: Formula: (= v_~m_pc~0_21 1) InVars {~m_pc~0=v_~m_pc~0_21} OutVars{~m_pc~0=v_~m_pc~0_21} AuxVars[] AssignedVars[] 1267#L295-7 [2602] L295-7-->L305-7: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_40 1) (= 1 v_~E_M~0_27)) InVars {~E_M~0=v_~E_M~0_27} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_40, ~E_M~0=v_~E_M~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 1268#L305-7 [3806] L305-7-->L745-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 1351#L745-21 [2835] L745-21-->L745-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_42) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} AuxVars[] AssignedVars[] 1352#L745-23 [2838] L745-23-->L313-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_43, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 1046#L313-21 [2243] L313-21-->L314-7: Formula: (= v_~t1_pc~0_21 1) InVars {~t1_pc~0=v_~t1_pc~0_21} OutVars{~t1_pc~0=v_~t1_pc~0_21} AuxVars[] AssignedVars[] 1047#L314-7 [2796] L314-7-->L324-7: Formula: (and (= 1 v_~E_1~0_27) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_46 1)) InVars {~E_1~0=v_~E_1~0_27} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_46, ~E_1~0=v_~E_1~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 1053#L324-7 [3813] L324-7-->L753-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 1083#L753-21 [2292] L753-21-->L753-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} AuxVars[] AssignedVars[] 1084#L753-23 [2297] L753-23-->L332-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_22|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 1086#L332-21 [2470] L332-21-->L333-7: Formula: (= 1 v_~t2_pc~0_21) InVars {~t2_pc~0=v_~t2_pc~0_21} OutVars{~t2_pc~0=v_~t2_pc~0_21} AuxVars[] AssignedVars[] 1166#L333-7 [2431] L333-7-->L343-7: Formula: (and (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_46 1) (= 1 v_~E_2~0_27)) InVars {~E_2~0=v_~E_2~0_27} OutVars{~E_2~0=v_~E_2~0_27, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_46} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 1168#L343-7 [3820] L343-7-->L761-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 1198#L761-21 [3538] L761-21-->L761-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___1~0_41 0) (= v_~t2_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41, ~t2_st~0=v_~t2_st~0_19} AuxVars[] AssignedVars[~t2_st~0] 1199#L761-23 [2493] L761-23-->L351-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_22|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 1200#L351-21 [2679] L351-21-->L352-7: Formula: (= v_~t3_pc~0_21 1) InVars {~t3_pc~0=v_~t3_pc~0_21} OutVars{~t3_pc~0=v_~t3_pc~0_21} AuxVars[] AssignedVars[] 1284#L352-7 [2622] L352-7-->L362-7: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_46 1) (= 1 v_~E_3~0_27)) InVars {~E_3~0=v_~E_3~0_27} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_46, ~E_3~0=v_~E_3~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 1215#L362-7 [3827] L362-7-->L769-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 1216#L769-21 [2534] L769-21-->L769-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} AuxVars[] AssignedVars[] 1222#L769-23 [2537] L769-23-->L370-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_43, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 1225#L370-21 [2927] L370-21-->L371-7: Formula: (= 1 v_~t4_pc~0_21) InVars {~t4_pc~0=v_~t4_pc~0_21} OutVars{~t4_pc~0=v_~t4_pc~0_21} AuxVars[] AssignedVars[] 1361#L371-7 [2863] L371-7-->L381-7: Formula: (and (= 1 v_~E_4~0_27) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_46 1)) InVars {~E_4~0=v_~E_4~0_27} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_46, ~E_4~0=v_~E_4~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 1327#L381-7 [3834] L381-7-->L777-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 1309#L777-21 [2705] L777-21-->L777-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} AuxVars[] AssignedVars[] 1310#L777-23 [2708] L777-23-->L389-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_22|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 948#L389-21 [2132] L389-21-->L390-7: Formula: (= v_~t5_pc~0_21 1) InVars {~t5_pc~0=v_~t5_pc~0_21} OutVars{~t5_pc~0=v_~t5_pc~0_21} AuxVars[] AssignedVars[] 949#L390-7 [2330] L390-7-->L400-7: Formula: (and (= 1 v_~E_5~0_27) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46 1)) InVars {~E_5~0=v_~E_5~0_27} OutVars{~E_5~0=v_~E_5~0_27, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 924#L400-7 [3837] L400-7-->L785-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 964#L785-21 [3654] L785-21-->L785-23: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_41 0) (= v_~t5_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} OutVars{~t5_st~0=v_~t5_st~0_19, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} AuxVars[] AssignedVars[~t5_st~0] 972#L785-23 [2161] L785-23-->L669-3: Formula: (and (= v_~M_E~0_12 1) (= v_~M_E~0_11 2)) InVars {~M_E~0=v_~M_E~0_12} OutVars{~M_E~0=v_~M_E~0_11} AuxVars[] AssignedVars[~M_E~0] 974#L669-3 [2824] L669-3-->L674-3: Formula: (and (= v_~T1_E~0_11 2) (= v_~T1_E~0_12 1)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 1193#L674-3 [2477] L674-3-->L679-3: Formula: (and (= 1 v_~T2_E~0_12) (= v_~T2_E~0_11 2)) InVars {~T2_E~0=v_~T2_E~0_12} OutVars{~T2_E~0=v_~T2_E~0_11} AuxVars[] AssignedVars[~T2_E~0] 1194#L679-3 [3664] L679-3-->L684-3: Formula: (< 1 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 1125#L684-3 [3666] L684-3-->L689-3: Formula: (> v_~T4_E~0_13 1) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 1126#L689-3 [3668] L689-3-->L694-3: Formula: (< 1 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 1148#L694-3 [2405] L694-3-->L699-3: Formula: (and (= 1 v_~E_M~0_30) (= v_~E_M~0_29 2)) InVars {~E_M~0=v_~E_M~0_30} OutVars{~E_M~0=v_~E_M~0_29} AuxVars[] AssignedVars[~E_M~0] 1049#L699-3 [2245] L699-3-->L704-3: Formula: (and (= v_~E_1~0_29 2) (= 1 v_~E_1~0_30)) InVars {~E_1~0=v_~E_1~0_30} OutVars{~E_1~0=v_~E_1~0_29} AuxVars[] AssignedVars[~E_1~0] 1050#L704-3 [2661] L704-3-->L709-3: Formula: (and (= v_~E_2~0_29 2) (= 1 v_~E_2~0_30)) InVars {~E_2~0=v_~E_2~0_30} OutVars{~E_2~0=v_~E_2~0_29} AuxVars[] AssignedVars[~E_2~0] 928#L709-3 [2114] L709-3-->L714-3: Formula: (and (= v_~E_3~0_29 2) (= 1 v_~E_3~0_30)) InVars {~E_3~0=v_~E_3~0_30} OutVars{~E_3~0=v_~E_3~0_29} AuxVars[] AssignedVars[~E_3~0] 929#L714-3 [2573] L714-3-->L719-3: Formula: (and (= v_~E_4~0_29 2) (= 1 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 1014#L719-3 [3680] L719-3-->L724-3: Formula: (> 1 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 1015#L724-3 [2818] L724-3-->L454-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_23} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 1187#L454-1 [2466] L454-1-->L486-1: Formula: (and (= 0 v_~m_st~0_20) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26 1)) InVars {~m_st~0=v_~m_st~0_20} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 1001#L486-1 [3838] L486-1-->L949: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret15, ULTIMATE.start_start_simulation_~tmp~3] 1132#L949 [3688] L949-->L949-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_1) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} AuxVars[] AssignedVars[] 1195#L949-1 [2479] L949-1-->L454-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_1} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 1174#L454-2 [2438] L454-2-->L486-2: Formula: (and (= v_~m_st~0_2 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4 1)) InVars {~m_st~0=v_~m_st~0_2} OutVars{~m_st~0=v_~m_st~0_2, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 1006#L486-2 [3840] L486-2-->L904: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 1103#L904 [2393] L904-->L911: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 1139#L911 [3851] L911-->L930-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_6|, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 1011#L930-1 312.69/160.48 [2019-03-28 12:21:51,684 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.48 [2019-03-28 12:21:51,684 INFO L82 PathProgramCache]: Analyzing trace with hash -1333424472, now seen corresponding path program 1 times 312.69/160.48 [2019-03-28 12:21:51,684 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.48 [2019-03-28 12:21:51,685 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.48 [2019-03-28 12:21:51,686 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:51,686 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:51,686 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:51,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.48 [2019-03-28 12:21:51,718 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.48 [2019-03-28 12:21:51,718 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.48 [2019-03-28 12:21:51,719 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 312.69/160.48 [2019-03-28 12:21:51,719 INFO L799 eck$LassoCheckResult]: stem already infeasible 312.69/160.48 [2019-03-28 12:21:51,719 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.48 [2019-03-28 12:21:51,719 INFO L82 PathProgramCache]: Analyzing trace with hash -1415295597, now seen corresponding path program 1 times 312.69/160.48 [2019-03-28 12:21:51,720 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.48 [2019-03-28 12:21:51,720 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.48 [2019-03-28 12:21:51,721 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:51,721 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:51,721 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:51,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.48 [2019-03-28 12:21:51,753 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.48 [2019-03-28 12:21:51,754 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.48 [2019-03-28 12:21:51,754 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 312.69/160.48 [2019-03-28 12:21:51,754 INFO L811 eck$LassoCheckResult]: loop already infeasible 312.69/160.48 [2019-03-28 12:21:51,754 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 312.69/160.48 [2019-03-28 12:21:51,754 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 312.69/160.48 [2019-03-28 12:21:51,755 INFO L87 Difference]: Start difference. First operand 454 states and 1004 transitions. cyclomatic complexity: 551 Second operand 3 states. 312.69/160.48 [2019-03-28 12:21:52,256 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.48 [2019-03-28 12:21:52,256 INFO L93 Difference]: Finished difference Result 454 states and 1003 transitions. 312.69/160.48 [2019-03-28 12:21:52,257 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 312.69/160.48 [2019-03-28 12:21:52,258 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 454 states and 1003 transitions. 312.69/160.48 [2019-03-28 12:21:52,262 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 387 312.69/160.48 [2019-03-28 12:21:52,266 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 454 states to 454 states and 1003 transitions. 312.69/160.48 [2019-03-28 12:21:52,267 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 454 312.69/160.48 [2019-03-28 12:21:52,267 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 454 312.69/160.48 [2019-03-28 12:21:52,268 INFO L73 IsDeterministic]: Start isDeterministic. Operand 454 states and 1003 transitions. 312.69/160.48 [2019-03-28 12:21:52,270 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.48 [2019-03-28 12:21:52,270 INFO L706 BuchiCegarLoop]: Abstraction has 454 states and 1003 transitions. 312.69/160.48 [2019-03-28 12:21:52,270 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 454 states and 1003 transitions. 312.69/160.48 [2019-03-28 12:21:52,285 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 454 to 454. 312.69/160.48 [2019-03-28 12:21:52,286 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 454 states. 312.69/160.48 [2019-03-28 12:21:52,288 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 454 states to 454 states and 1003 transitions. 312.69/160.48 [2019-03-28 12:21:52,288 INFO L729 BuchiCegarLoop]: Abstraction has 454 states and 1003 transitions. 312.69/160.48 [2019-03-28 12:21:52,288 INFO L609 BuchiCegarLoop]: Abstraction has 454 states and 1003 transitions. 312.69/160.48 [2019-03-28 12:21:52,288 INFO L442 BuchiCegarLoop]: ======== Iteration 3============ 312.69/160.48 [2019-03-28 12:21:52,289 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 454 states and 1003 transitions. 312.69/160.48 [2019-03-28 12:21:52,292 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 387 312.69/160.48 [2019-03-28 12:21:52,292 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.48 [2019-03-28 12:21:52,292 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.48 [2019-03-28 12:21:52,294 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.48 [2019-03-28 12:21:52,294 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.48 [2019-03-28 12:21:52,299 INFO L794 eck$LassoCheckResult]: Stem: 2204#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 2020#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 2021#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 2088#L421-1 [3225] L421-1-->L426-1: Formula: (and (> 1 v_~t2_i~0_4) (= v_~t2_st~0_5 2)) InVars {~t2_i~0=v_~t2_i~0_4} OutVars{~t2_i~0=v_~t2_i~0_4, ~t2_st~0=v_~t2_st~0_5} AuxVars[] AssignedVars[~t2_st~0] 2089#L426-1 [3227] L426-1-->L431-1: Formula: (and (= v_~t3_st~0_5 2) (< v_~t3_i~0_4 1)) InVars {~t3_i~0=v_~t3_i~0_4} OutVars{~t3_st~0=v_~t3_st~0_5, ~t3_i~0=v_~t3_i~0_4} AuxVars[] AssignedVars[~t3_st~0] 2022#L431-1 [3229] L431-1-->L436-1: Formula: (and (< v_~t4_i~0_4 1) (= v_~t4_st~0_5 2)) InVars {~t4_i~0=v_~t4_i~0_4} OutVars{~t4_i~0=v_~t4_i~0_4, ~t4_st~0=v_~t4_st~0_5} AuxVars[] AssignedVars[~t4_st~0] 2023#L436-1 [3231] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_5 2) (> v_~t5_i~0_4 1)) InVars {~t5_i~0=v_~t5_i~0_4} OutVars{~t5_i~0=v_~t5_i~0_4, ~t5_st~0=v_~t5_st~0_5} AuxVars[] AssignedVars[~t5_st~0] 2061#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 2062#L601-1 [2765] L601-1-->L606-1: Formula: (and (= v_~T1_E~0_2 1) (= 0 v_~T1_E~0_3)) InVars {~T1_E~0=v_~T1_E~0_3} OutVars{~T1_E~0=v_~T1_E~0_2} AuxVars[] AssignedVars[~T1_E~0] 2065#L606-1 [2407] L606-1-->L611-1: Formula: (and (= 0 v_~T2_E~0_3) (= v_~T2_E~0_2 1)) InVars {~T2_E~0=v_~T2_E~0_3} OutVars{~T2_E~0=v_~T2_E~0_2} AuxVars[] AssignedVars[~T2_E~0] 1967#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 1968#L616-1 [3241] L616-1-->L621-1: Formula: (< v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 1846#L621-1 [3243] L621-1-->L626-1: Formula: (< v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 1847#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 1932#L631-1 [3247] L631-1-->L636-1: Formula: (< v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 1933#L636-1 [2819] L636-1-->L641-1: Formula: (and (= v_~E_2~0_3 0) (= v_~E_2~0_2 1)) InVars {~E_2~0=v_~E_2~0_3} OutVars{~E_2~0=v_~E_2~0_2} AuxVars[] AssignedVars[~E_2~0] 2107#L641-1 [2474] L641-1-->L646-1: Formula: (and (= v_~E_3~0_3 0) (= v_~E_3~0_2 1)) InVars {~E_3~0=v_~E_3~0_3} OutVars{~E_3~0=v_~E_3~0_2} AuxVars[] AssignedVars[~E_3~0] 2108#L646-1 [2935] L646-1-->L651-1: Formula: (and (= v_~E_4~0_2 1) (= v_~E_4~0_3 0)) InVars {~E_4~0=v_~E_4~0_3} OutVars{~E_4~0=v_~E_4~0_2} AuxVars[] AssignedVars[~E_4~0] 2053#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 2054#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 2264#L294 [2854] L294-->L295: Formula: (= v_~m_pc~0_2 1) InVars {~m_pc~0=v_~m_pc~0_2} OutVars{~m_pc~0=v_~m_pc~0_2} AuxVars[] AssignedVars[] 2177#L295 [2595] L295-->L305: Formula: (and (= v_~E_M~0_5 1) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_4 1)) InVars {~E_M~0=v_~E_M~0_5} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_4, ~E_M~0=v_~E_M~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 2178#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 2283#L745 [3261] L745-->L745-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_5) (= v_~m_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} OutVars{~m_st~0=v_~m_st~0_6, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} AuxVars[] AssignedVars[~m_st~0] 2288#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 2003#L313 [2301] L313-->L314: Formula: (= v_~t1_pc~0_2 1) InVars {~t1_pc~0=v_~t1_pc~0_2} OutVars{~t1_pc~0=v_~t1_pc~0_2} AuxVars[] AssignedVars[] 1959#L314 [2241] L314-->L324: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_4 1) (= v_~E_1~0_5 1)) InVars {~E_1~0=v_~E_1~0_5} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_4, ~E_1~0=v_~E_1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 1961#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 1861#L753 [3267] L753-->L753-2: Formula: (and (> 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_5) (= v_~t1_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_5, ~t1_st~0=v_~t1_st~0_6} AuxVars[] AssignedVars[~t1_st~0] 1862#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 1866#L332 [3269] L332-->L332-2: Formula: (> v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 2030#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 2028#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 2029#L761 [3273] L761-->L761-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_5) (= v_~t2_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5, ~t2_st~0=v_~t2_st~0_6} AuxVars[] AssignedVars[~t2_st~0] 2049#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 2050#L351 [2567] L351-->L352: Formula: (= 1 v_~t3_pc~0_2) InVars {~t3_pc~0=v_~t3_pc~0_2} OutVars{~t3_pc~0=v_~t3_pc~0_2} AuxVars[] AssignedVars[] 2166#L352 [2655] L352-->L362: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_4 1) (= v_~E_3~0_5 1)) InVars {~E_3~0=v_~E_3~0_5} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_4, ~E_3~0=v_~E_3~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 2148#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 2165#L769 [3279] L769-->L769-2: Formula: (and (= v_~t3_st~0_6 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_5)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} OutVars{~t3_st~0=v_~t3_st~0_6, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} AuxVars[] AssignedVars[~t3_st~0] 2169#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 2170#L370 [3281] L370-->L370-2: Formula: (> v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 2253#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 2249#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 2250#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 2263#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 1923#L389 [2193] L389-->L390: Formula: (= 1 v_~t5_pc~0_2) InVars {~t5_pc~0=v_~t5_pc~0_2} OutVars{~t5_pc~0=v_~t5_pc~0_2} AuxVars[] AssignedVars[] 1924#L390 [2343] L390-->L400: Formula: (and (= v_~E_5~0_5 1) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4 1)) InVars {~E_5~0=v_~E_5~0_5} OutVars{~E_5~0=v_~E_5~0_5, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 1893#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 1919#L785 [3291] L785-->L785-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_5) (= v_~t5_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} OutVars{~t5_st~0=v_~t5_st~0_6, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} AuxVars[] AssignedVars[~t5_st~0] 1939#L785-2 [3293] L785-2-->L669-1: Formula: (> 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 1941#L669-1 [3295] L669-1-->L674-1: Formula: (> 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 2105#L674-1 [2472] L674-1-->L679-1: Formula: (and (= 1 v_~T2_E~0_6) (= v_~T2_E~0_5 2)) InVars {~T2_E~0=v_~T2_E~0_6} OutVars{~T2_E~0=v_~T2_E~0_5} AuxVars[] AssignedVars[~T2_E~0] 2106#L679-1 [3299] L679-1-->L684-1: Formula: (< v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 2051#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 2052#L689-1 [2782] L689-1-->L694-1: Formula: (and (= v_~T5_E~0_6 1) (= v_~T5_E~0_5 2)) InVars {~T5_E~0=v_~T5_E~0_6} OutVars{~T5_E~0=v_~T5_E~0_5} AuxVars[] AssignedVars[~T5_E~0] 2198#L694-1 [3305] L694-1-->L699-1: Formula: (< v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 1988#L699-1 [3307] L699-1-->L704-1: Formula: (< v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 1989#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 1835#L709-1 [3311] L709-1-->L714-1: Formula: (< v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 1836#L714-1 [2569] L714-1-->L719-1: Formula: (and (= v_~E_4~0_8 1) (= v_~E_4~0_7 2)) InVars {~E_4~0=v_~E_4~0_8} OutVars{~E_4~0=v_~E_4~0_7} AuxVars[] AssignedVars[~E_4~0] 1926#L719-1 [2198] L719-1-->L930-1: Formula: (and (= v_~E_5~0_8 1) (= v_~E_5~0_7 2)) InVars {~E_5~0=v_~E_5~0_8} OutVars{~E_5~0=v_~E_5~0_7} AuxVars[] AssignedVars[~E_5~0] 1927#L930-1 312.69/160.48 [2019-03-28 12:21:52,301 INFO L796 eck$LassoCheckResult]: Loop: 1927#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 1934#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 1935#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 1914#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 1979#L501 [3784] L501-->L601-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 1980#L601-2 [2768] L601-2-->L601-4: Formula: (and (= v_~M_E~0_8 1) (= 0 v_~M_E~0_9)) InVars {~M_E~0=v_~M_E~0_9} OutVars{~M_E~0=v_~M_E~0_8} AuxVars[] AssignedVars[~M_E~0] 2262#L601-4 [2773] L601-4-->L606-3: Formula: (and (= v_~T1_E~0_8 1) (= 0 v_~T1_E~0_9)) InVars {~T1_E~0=v_~T1_E~0_9} OutVars{~T1_E~0=v_~T1_E~0_8} AuxVars[] AssignedVars[~T1_E~0] 2068#L606-3 [2413] L606-3-->L611-3: Formula: (and (= v_~T2_E~0_8 1) (= 0 v_~T2_E~0_9)) InVars {~T2_E~0=v_~T2_E~0_9} OutVars{~T2_E~0=v_~T2_E~0_8} AuxVars[] AssignedVars[~T2_E~0] 1977#L611-3 [2256] L611-3-->L616-3: Formula: (and (= v_~T3_E~0_8 1) (= v_~T3_E~0_9 0)) InVars {~T3_E~0=v_~T3_E~0_9} OutVars{~T3_E~0=v_~T3_E~0_8} AuxVars[] AssignedVars[~T3_E~0] 1978#L616-3 [3338] L616-3-->L621-3: Formula: (< v_~T4_E~0_10 0) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 1852#L621-3 [3346] L621-3-->L626-3: Formula: (< 0 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 1853#L626-3 [2580] L626-3-->L631-3: Formula: (and (= v_~E_M~0_24 1) (= 0 v_~E_M~0_25)) InVars {~E_M~0=v_~E_M~0_25} OutVars{~E_M~0=v_~E_M~0_24} AuxVars[] AssignedVars[~E_M~0] 1908#L631-3 [2180] L631-3-->L636-3: Formula: (and (= v_~E_1~0_24 1) (= 0 v_~E_1~0_25)) InVars {~E_1~0=v_~E_1~0_25} OutVars{~E_1~0=v_~E_1~0_24} AuxVars[] AssignedVars[~E_1~0] 1909#L636-3 [3376] L636-3-->L641-3: Formula: (< 0 v_~E_2~0_26) InVars {~E_2~0=v_~E_2~0_26} OutVars{~E_2~0=v_~E_2~0_26} AuxVars[] AssignedVars[] 2099#L641-3 [2455] L641-3-->L646-3: Formula: (and (= 0 v_~E_3~0_25) (= v_~E_3~0_24 1)) InVars {~E_3~0=v_~E_3~0_25} OutVars{~E_3~0=v_~E_3~0_24} AuxVars[] AssignedVars[~E_3~0] 2100#L646-3 [2912] L646-3-->L651-3: Formula: (and (= 0 v_~E_4~0_25) (= v_~E_4~0_24 1)) InVars {~E_4~0=v_~E_4~0_25} OutVars{~E_4~0=v_~E_4~0_24} AuxVars[] AssignedVars[~E_4~0] 2044#L651-3 [3410] L651-3-->L656-3: Formula: (> 0 v_~E_5~0_26) InVars {~E_5~0=v_~E_5~0_26} OutVars{~E_5~0=v_~E_5~0_26} AuxVars[] AssignedVars[] 2045#L656-3 [2767] L656-3-->L294-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_37, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_37, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_22|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_22|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_22|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_37, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_37, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_22|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_22|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_22|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_22|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_37, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_37, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_37} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 2261#L294-21 [2808] L294-21-->L295-7: Formula: (= v_~m_pc~0_21 1) InVars {~m_pc~0=v_~m_pc~0_21} OutVars{~m_pc~0=v_~m_pc~0_21} AuxVars[] AssignedVars[] 2183#L295-7 [2602] L295-7-->L305-7: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_40 1) (= 1 v_~E_M~0_27)) InVars {~E_M~0=v_~E_M~0_27} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_40, ~E_M~0=v_~E_M~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 2184#L305-7 [3806] L305-7-->L745-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 2267#L745-21 [2835] L745-21-->L745-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_42) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} AuxVars[] AssignedVars[] 2268#L745-23 [2838] L745-23-->L313-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_43, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 1962#L313-21 [2243] L313-21-->L314-7: Formula: (= v_~t1_pc~0_21 1) InVars {~t1_pc~0=v_~t1_pc~0_21} OutVars{~t1_pc~0=v_~t1_pc~0_21} AuxVars[] AssignedVars[] 1963#L314-7 [2796] L314-7-->L324-7: Formula: (and (= 1 v_~E_1~0_27) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_46 1)) InVars {~E_1~0=v_~E_1~0_27} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_46, ~E_1~0=v_~E_1~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 1969#L324-7 [3813] L324-7-->L753-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 1999#L753-21 [2292] L753-21-->L753-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} AuxVars[] AssignedVars[] 2000#L753-23 [2297] L753-23-->L332-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_22|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 2002#L332-21 [2470] L332-21-->L333-7: Formula: (= 1 v_~t2_pc~0_21) InVars {~t2_pc~0=v_~t2_pc~0_21} OutVars{~t2_pc~0=v_~t2_pc~0_21} AuxVars[] AssignedVars[] 2082#L333-7 [2431] L333-7-->L343-7: Formula: (and (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_46 1) (= 1 v_~E_2~0_27)) InVars {~E_2~0=v_~E_2~0_27} OutVars{~E_2~0=v_~E_2~0_27, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_46} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 2084#L343-7 [3820] L343-7-->L761-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 2114#L761-21 [3538] L761-21-->L761-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___1~0_41 0) (= v_~t2_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41, ~t2_st~0=v_~t2_st~0_19} AuxVars[] AssignedVars[~t2_st~0] 2115#L761-23 [2493] L761-23-->L351-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_22|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 2116#L351-21 [2679] L351-21-->L352-7: Formula: (= v_~t3_pc~0_21 1) InVars {~t3_pc~0=v_~t3_pc~0_21} OutVars{~t3_pc~0=v_~t3_pc~0_21} AuxVars[] AssignedVars[] 2200#L352-7 [2622] L352-7-->L362-7: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_46 1) (= 1 v_~E_3~0_27)) InVars {~E_3~0=v_~E_3~0_27} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_46, ~E_3~0=v_~E_3~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 2131#L362-7 [3827] L362-7-->L769-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 2132#L769-21 [2534] L769-21-->L769-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} AuxVars[] AssignedVars[] 2138#L769-23 [2537] L769-23-->L370-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_43, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 2141#L370-21 [2927] L370-21-->L371-7: Formula: (= 1 v_~t4_pc~0_21) InVars {~t4_pc~0=v_~t4_pc~0_21} OutVars{~t4_pc~0=v_~t4_pc~0_21} AuxVars[] AssignedVars[] 2277#L371-7 [2863] L371-7-->L381-7: Formula: (and (= 1 v_~E_4~0_27) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_46 1)) InVars {~E_4~0=v_~E_4~0_27} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_46, ~E_4~0=v_~E_4~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 2243#L381-7 [3834] L381-7-->L777-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 2225#L777-21 [2705] L777-21-->L777-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} AuxVars[] AssignedVars[] 2226#L777-23 [2708] L777-23-->L389-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_22|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 1864#L389-21 [2132] L389-21-->L390-7: Formula: (= v_~t5_pc~0_21 1) InVars {~t5_pc~0=v_~t5_pc~0_21} OutVars{~t5_pc~0=v_~t5_pc~0_21} AuxVars[] AssignedVars[] 1865#L390-7 [2330] L390-7-->L400-7: Formula: (and (= 1 v_~E_5~0_27) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46 1)) InVars {~E_5~0=v_~E_5~0_27} OutVars{~E_5~0=v_~E_5~0_27, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 1840#L400-7 [3837] L400-7-->L785-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 1880#L785-21 [3654] L785-21-->L785-23: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_41 0) (= v_~t5_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} OutVars{~t5_st~0=v_~t5_st~0_19, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} AuxVars[] AssignedVars[~t5_st~0] 1888#L785-23 [2161] L785-23-->L669-3: Formula: (and (= v_~M_E~0_12 1) (= v_~M_E~0_11 2)) InVars {~M_E~0=v_~M_E~0_12} OutVars{~M_E~0=v_~M_E~0_11} AuxVars[] AssignedVars[~M_E~0] 1890#L669-3 [2824] L669-3-->L674-3: Formula: (and (= v_~T1_E~0_11 2) (= v_~T1_E~0_12 1)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 2109#L674-3 [2477] L674-3-->L679-3: Formula: (and (= 1 v_~T2_E~0_12) (= v_~T2_E~0_11 2)) InVars {~T2_E~0=v_~T2_E~0_12} OutVars{~T2_E~0=v_~T2_E~0_11} AuxVars[] AssignedVars[~T2_E~0] 2110#L679-3 [3664] L679-3-->L684-3: Formula: (< 1 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 2041#L684-3 [3666] L684-3-->L689-3: Formula: (> v_~T4_E~0_13 1) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 2042#L689-3 [3668] L689-3-->L694-3: Formula: (< 1 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 2064#L694-3 [2405] L694-3-->L699-3: Formula: (and (= 1 v_~E_M~0_30) (= v_~E_M~0_29 2)) InVars {~E_M~0=v_~E_M~0_30} OutVars{~E_M~0=v_~E_M~0_29} AuxVars[] AssignedVars[~E_M~0] 1965#L699-3 [2245] L699-3-->L704-3: Formula: (and (= v_~E_1~0_29 2) (= 1 v_~E_1~0_30)) InVars {~E_1~0=v_~E_1~0_30} OutVars{~E_1~0=v_~E_1~0_29} AuxVars[] AssignedVars[~E_1~0] 1966#L704-3 [2661] L704-3-->L709-3: Formula: (and (= v_~E_2~0_29 2) (= 1 v_~E_2~0_30)) InVars {~E_2~0=v_~E_2~0_30} OutVars{~E_2~0=v_~E_2~0_29} AuxVars[] AssignedVars[~E_2~0] 1844#L709-3 [2114] L709-3-->L714-3: Formula: (and (= v_~E_3~0_29 2) (= 1 v_~E_3~0_30)) InVars {~E_3~0=v_~E_3~0_30} OutVars{~E_3~0=v_~E_3~0_29} AuxVars[] AssignedVars[~E_3~0] 1845#L714-3 [2573] L714-3-->L719-3: Formula: (and (= v_~E_4~0_29 2) (= 1 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 1930#L719-3 [3680] L719-3-->L724-3: Formula: (> 1 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 1931#L724-3 [2818] L724-3-->L454-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_23} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 2103#L454-1 [2466] L454-1-->L486-1: Formula: (and (= 0 v_~m_st~0_20) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26 1)) InVars {~m_st~0=v_~m_st~0_20} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 1917#L486-1 [3838] L486-1-->L949: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret15, ULTIMATE.start_start_simulation_~tmp~3] 2048#L949 [3688] L949-->L949-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_1) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} AuxVars[] AssignedVars[] 2111#L949-1 [2479] L949-1-->L454-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_1} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 2090#L454-2 [2438] L454-2-->L486-2: Formula: (and (= v_~m_st~0_2 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4 1)) InVars {~m_st~0=v_~m_st~0_2} OutVars{~m_st~0=v_~m_st~0_2, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 1922#L486-2 [3840] L486-2-->L904: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 2019#L904 [2393] L904-->L911: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 2055#L911 [3851] L911-->L930-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_6|, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 1927#L930-1 312.69/160.48 [2019-03-28 12:21:52,302 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.48 [2019-03-28 12:21:52,302 INFO L82 PathProgramCache]: Analyzing trace with hash 1370213355, now seen corresponding path program 1 times 312.69/160.48 [2019-03-28 12:21:52,302 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.48 [2019-03-28 12:21:52,302 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.48 [2019-03-28 12:21:52,303 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:52,303 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:52,303 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:52,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.48 [2019-03-28 12:21:52,353 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.48 [2019-03-28 12:21:52,354 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.48 [2019-03-28 12:21:52,354 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 312.69/160.48 [2019-03-28 12:21:52,354 INFO L799 eck$LassoCheckResult]: stem already infeasible 312.69/160.48 [2019-03-28 12:21:52,355 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.48 [2019-03-28 12:21:52,355 INFO L82 PathProgramCache]: Analyzing trace with hash -1415295597, now seen corresponding path program 2 times 312.69/160.48 [2019-03-28 12:21:52,355 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.48 [2019-03-28 12:21:52,355 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.48 [2019-03-28 12:21:52,356 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:52,356 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:52,356 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:52,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.48 [2019-03-28 12:21:52,386 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.48 [2019-03-28 12:21:52,386 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.48 [2019-03-28 12:21:52,387 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 312.69/160.48 [2019-03-28 12:21:52,387 INFO L811 eck$LassoCheckResult]: loop already infeasible 312.69/160.48 [2019-03-28 12:21:52,387 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 312.69/160.48 [2019-03-28 12:21:52,387 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 312.69/160.48 [2019-03-28 12:21:52,388 INFO L87 Difference]: Start difference. First operand 454 states and 1003 transitions. cyclomatic complexity: 550 Second operand 3 states. 312.69/160.48 [2019-03-28 12:21:52,917 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.48 [2019-03-28 12:21:52,918 INFO L93 Difference]: Finished difference Result 454 states and 1002 transitions. 312.69/160.48 [2019-03-28 12:21:52,918 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 312.69/160.48 [2019-03-28 12:21:52,919 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 454 states and 1002 transitions. 312.69/160.48 [2019-03-28 12:21:52,922 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 387 312.69/160.48 [2019-03-28 12:21:52,926 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 454 states to 454 states and 1002 transitions. 312.69/160.48 [2019-03-28 12:21:52,926 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 454 312.69/160.48 [2019-03-28 12:21:52,927 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 454 312.69/160.48 [2019-03-28 12:21:52,927 INFO L73 IsDeterministic]: Start isDeterministic. Operand 454 states and 1002 transitions. 312.69/160.48 [2019-03-28 12:21:52,928 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.48 [2019-03-28 12:21:52,928 INFO L706 BuchiCegarLoop]: Abstraction has 454 states and 1002 transitions. 312.69/160.48 [2019-03-28 12:21:52,929 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 454 states and 1002 transitions. 312.69/160.48 [2019-03-28 12:21:52,938 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 454 to 454. 312.69/160.48 [2019-03-28 12:21:52,938 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 454 states. 312.69/160.48 [2019-03-28 12:21:52,939 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 454 states to 454 states and 1002 transitions. 312.69/160.48 [2019-03-28 12:21:52,940 INFO L729 BuchiCegarLoop]: Abstraction has 454 states and 1002 transitions. 312.69/160.48 [2019-03-28 12:21:52,940 INFO L609 BuchiCegarLoop]: Abstraction has 454 states and 1002 transitions. 312.69/160.48 [2019-03-28 12:21:52,940 INFO L442 BuchiCegarLoop]: ======== Iteration 4============ 312.69/160.48 [2019-03-28 12:21:52,940 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 454 states and 1002 transitions. 312.69/160.48 [2019-03-28 12:21:52,943 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 387 312.69/160.48 [2019-03-28 12:21:52,943 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.48 [2019-03-28 12:21:52,943 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.48 [2019-03-28 12:21:52,944 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.48 [2019-03-28 12:21:52,945 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.48 [2019-03-28 12:21:52,946 INFO L794 eck$LassoCheckResult]: Stem: 3120#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 2936#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 2937#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 3004#L421-1 [3224] L421-1-->L426-1: Formula: (and (< 1 v_~t2_i~0_4) (= v_~t2_st~0_5 2)) InVars {~t2_i~0=v_~t2_i~0_4} OutVars{~t2_i~0=v_~t2_i~0_4, ~t2_st~0=v_~t2_st~0_5} AuxVars[] AssignedVars[~t2_st~0] 3005#L426-1 [3227] L426-1-->L431-1: Formula: (and (= v_~t3_st~0_5 2) (< v_~t3_i~0_4 1)) InVars {~t3_i~0=v_~t3_i~0_4} OutVars{~t3_st~0=v_~t3_st~0_5, ~t3_i~0=v_~t3_i~0_4} AuxVars[] AssignedVars[~t3_st~0] 2938#L431-1 [3229] L431-1-->L436-1: Formula: (and (< v_~t4_i~0_4 1) (= v_~t4_st~0_5 2)) InVars {~t4_i~0=v_~t4_i~0_4} OutVars{~t4_i~0=v_~t4_i~0_4, ~t4_st~0=v_~t4_st~0_5} AuxVars[] AssignedVars[~t4_st~0] 2939#L436-1 [3231] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_5 2) (> v_~t5_i~0_4 1)) InVars {~t5_i~0=v_~t5_i~0_4} OutVars{~t5_i~0=v_~t5_i~0_4, ~t5_st~0=v_~t5_st~0_5} AuxVars[] AssignedVars[~t5_st~0] 2977#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 2978#L601-1 [2765] L601-1-->L606-1: Formula: (and (= v_~T1_E~0_2 1) (= 0 v_~T1_E~0_3)) InVars {~T1_E~0=v_~T1_E~0_3} OutVars{~T1_E~0=v_~T1_E~0_2} AuxVars[] AssignedVars[~T1_E~0] 2981#L606-1 [2407] L606-1-->L611-1: Formula: (and (= 0 v_~T2_E~0_3) (= v_~T2_E~0_2 1)) InVars {~T2_E~0=v_~T2_E~0_3} OutVars{~T2_E~0=v_~T2_E~0_2} AuxVars[] AssignedVars[~T2_E~0] 2883#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 2884#L616-1 [3241] L616-1-->L621-1: Formula: (< v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 2762#L621-1 [3243] L621-1-->L626-1: Formula: (< v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 2763#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 2848#L631-1 [3247] L631-1-->L636-1: Formula: (< v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 2849#L636-1 [2819] L636-1-->L641-1: Formula: (and (= v_~E_2~0_3 0) (= v_~E_2~0_2 1)) InVars {~E_2~0=v_~E_2~0_3} OutVars{~E_2~0=v_~E_2~0_2} AuxVars[] AssignedVars[~E_2~0] 3023#L641-1 [2474] L641-1-->L646-1: Formula: (and (= v_~E_3~0_3 0) (= v_~E_3~0_2 1)) InVars {~E_3~0=v_~E_3~0_3} OutVars{~E_3~0=v_~E_3~0_2} AuxVars[] AssignedVars[~E_3~0] 3024#L646-1 [2935] L646-1-->L651-1: Formula: (and (= v_~E_4~0_2 1) (= v_~E_4~0_3 0)) InVars {~E_4~0=v_~E_4~0_3} OutVars{~E_4~0=v_~E_4~0_2} AuxVars[] AssignedVars[~E_4~0] 2969#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 2970#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 3180#L294 [2854] L294-->L295: Formula: (= v_~m_pc~0_2 1) InVars {~m_pc~0=v_~m_pc~0_2} OutVars{~m_pc~0=v_~m_pc~0_2} AuxVars[] AssignedVars[] 3093#L295 [2595] L295-->L305: Formula: (and (= v_~E_M~0_5 1) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_4 1)) InVars {~E_M~0=v_~E_M~0_5} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_4, ~E_M~0=v_~E_M~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 3094#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 3199#L745 [3261] L745-->L745-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_5) (= v_~m_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} OutVars{~m_st~0=v_~m_st~0_6, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} AuxVars[] AssignedVars[~m_st~0] 3204#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 2919#L313 [2301] L313-->L314: Formula: (= v_~t1_pc~0_2 1) InVars {~t1_pc~0=v_~t1_pc~0_2} OutVars{~t1_pc~0=v_~t1_pc~0_2} AuxVars[] AssignedVars[] 2875#L314 [2241] L314-->L324: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_4 1) (= v_~E_1~0_5 1)) InVars {~E_1~0=v_~E_1~0_5} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_4, ~E_1~0=v_~E_1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 2877#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 2777#L753 [3267] L753-->L753-2: Formula: (and (> 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_5) (= v_~t1_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_5, ~t1_st~0=v_~t1_st~0_6} AuxVars[] AssignedVars[~t1_st~0] 2778#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 2782#L332 [3269] L332-->L332-2: Formula: (> v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 2946#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 2944#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 2945#L761 [3273] L761-->L761-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_5) (= v_~t2_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5, ~t2_st~0=v_~t2_st~0_6} AuxVars[] AssignedVars[~t2_st~0] 2965#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 2966#L351 [2567] L351-->L352: Formula: (= 1 v_~t3_pc~0_2) InVars {~t3_pc~0=v_~t3_pc~0_2} OutVars{~t3_pc~0=v_~t3_pc~0_2} AuxVars[] AssignedVars[] 3082#L352 [2655] L352-->L362: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_4 1) (= v_~E_3~0_5 1)) InVars {~E_3~0=v_~E_3~0_5} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_4, ~E_3~0=v_~E_3~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 3064#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 3081#L769 [3279] L769-->L769-2: Formula: (and (= v_~t3_st~0_6 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_5)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} OutVars{~t3_st~0=v_~t3_st~0_6, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} AuxVars[] AssignedVars[~t3_st~0] 3085#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 3086#L370 [3281] L370-->L370-2: Formula: (> v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 3169#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 3165#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 3166#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 3179#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 2839#L389 [2193] L389-->L390: Formula: (= 1 v_~t5_pc~0_2) InVars {~t5_pc~0=v_~t5_pc~0_2} OutVars{~t5_pc~0=v_~t5_pc~0_2} AuxVars[] AssignedVars[] 2840#L390 [2343] L390-->L400: Formula: (and (= v_~E_5~0_5 1) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4 1)) InVars {~E_5~0=v_~E_5~0_5} OutVars{~E_5~0=v_~E_5~0_5, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 2809#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 2835#L785 [3291] L785-->L785-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_5) (= v_~t5_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} OutVars{~t5_st~0=v_~t5_st~0_6, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} AuxVars[] AssignedVars[~t5_st~0] 2855#L785-2 [3293] L785-2-->L669-1: Formula: (> 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 2857#L669-1 [3295] L669-1-->L674-1: Formula: (> 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 3021#L674-1 [2472] L674-1-->L679-1: Formula: (and (= 1 v_~T2_E~0_6) (= v_~T2_E~0_5 2)) InVars {~T2_E~0=v_~T2_E~0_6} OutVars{~T2_E~0=v_~T2_E~0_5} AuxVars[] AssignedVars[~T2_E~0] 3022#L679-1 [3299] L679-1-->L684-1: Formula: (< v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 2967#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 2968#L689-1 [2782] L689-1-->L694-1: Formula: (and (= v_~T5_E~0_6 1) (= v_~T5_E~0_5 2)) InVars {~T5_E~0=v_~T5_E~0_6} OutVars{~T5_E~0=v_~T5_E~0_5} AuxVars[] AssignedVars[~T5_E~0] 3114#L694-1 [3305] L694-1-->L699-1: Formula: (< v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 2904#L699-1 [3307] L699-1-->L704-1: Formula: (< v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 2905#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 2751#L709-1 [3311] L709-1-->L714-1: Formula: (< v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 2752#L714-1 [2569] L714-1-->L719-1: Formula: (and (= v_~E_4~0_8 1) (= v_~E_4~0_7 2)) InVars {~E_4~0=v_~E_4~0_8} OutVars{~E_4~0=v_~E_4~0_7} AuxVars[] AssignedVars[~E_4~0] 2842#L719-1 [2198] L719-1-->L930-1: Formula: (and (= v_~E_5~0_8 1) (= v_~E_5~0_7 2)) InVars {~E_5~0=v_~E_5~0_8} OutVars{~E_5~0=v_~E_5~0_7} AuxVars[] AssignedVars[~E_5~0] 2843#L930-1 312.69/160.48 [2019-03-28 12:21:52,947 INFO L796 eck$LassoCheckResult]: Loop: 2843#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 2850#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 2851#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 2830#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 2895#L501 [3784] L501-->L601-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 2896#L601-2 [2768] L601-2-->L601-4: Formula: (and (= v_~M_E~0_8 1) (= 0 v_~M_E~0_9)) InVars {~M_E~0=v_~M_E~0_9} OutVars{~M_E~0=v_~M_E~0_8} AuxVars[] AssignedVars[~M_E~0] 3178#L601-4 [2773] L601-4-->L606-3: Formula: (and (= v_~T1_E~0_8 1) (= 0 v_~T1_E~0_9)) InVars {~T1_E~0=v_~T1_E~0_9} OutVars{~T1_E~0=v_~T1_E~0_8} AuxVars[] AssignedVars[~T1_E~0] 2984#L606-3 [2413] L606-3-->L611-3: Formula: (and (= v_~T2_E~0_8 1) (= 0 v_~T2_E~0_9)) InVars {~T2_E~0=v_~T2_E~0_9} OutVars{~T2_E~0=v_~T2_E~0_8} AuxVars[] AssignedVars[~T2_E~0] 2893#L611-3 [2256] L611-3-->L616-3: Formula: (and (= v_~T3_E~0_8 1) (= v_~T3_E~0_9 0)) InVars {~T3_E~0=v_~T3_E~0_9} OutVars{~T3_E~0=v_~T3_E~0_8} AuxVars[] AssignedVars[~T3_E~0] 2894#L616-3 [3338] L616-3-->L621-3: Formula: (< v_~T4_E~0_10 0) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 2768#L621-3 [3346] L621-3-->L626-3: Formula: (< 0 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 2769#L626-3 [2580] L626-3-->L631-3: Formula: (and (= v_~E_M~0_24 1) (= 0 v_~E_M~0_25)) InVars {~E_M~0=v_~E_M~0_25} OutVars{~E_M~0=v_~E_M~0_24} AuxVars[] AssignedVars[~E_M~0] 2824#L631-3 [2180] L631-3-->L636-3: Formula: (and (= v_~E_1~0_24 1) (= 0 v_~E_1~0_25)) InVars {~E_1~0=v_~E_1~0_25} OutVars{~E_1~0=v_~E_1~0_24} AuxVars[] AssignedVars[~E_1~0] 2825#L636-3 [3376] L636-3-->L641-3: Formula: (< 0 v_~E_2~0_26) InVars {~E_2~0=v_~E_2~0_26} OutVars{~E_2~0=v_~E_2~0_26} AuxVars[] AssignedVars[] 3015#L641-3 [2455] L641-3-->L646-3: Formula: (and (= 0 v_~E_3~0_25) (= v_~E_3~0_24 1)) InVars {~E_3~0=v_~E_3~0_25} OutVars{~E_3~0=v_~E_3~0_24} AuxVars[] AssignedVars[~E_3~0] 3016#L646-3 [2912] L646-3-->L651-3: Formula: (and (= 0 v_~E_4~0_25) (= v_~E_4~0_24 1)) InVars {~E_4~0=v_~E_4~0_25} OutVars{~E_4~0=v_~E_4~0_24} AuxVars[] AssignedVars[~E_4~0] 2960#L651-3 [3410] L651-3-->L656-3: Formula: (> 0 v_~E_5~0_26) InVars {~E_5~0=v_~E_5~0_26} OutVars{~E_5~0=v_~E_5~0_26} AuxVars[] AssignedVars[] 2961#L656-3 [2767] L656-3-->L294-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_37, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_37, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_22|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_22|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_22|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_37, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_37, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_22|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_22|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_22|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_22|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_37, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_37, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_37} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 3177#L294-21 [2808] L294-21-->L295-7: Formula: (= v_~m_pc~0_21 1) InVars {~m_pc~0=v_~m_pc~0_21} OutVars{~m_pc~0=v_~m_pc~0_21} AuxVars[] AssignedVars[] 3099#L295-7 [2602] L295-7-->L305-7: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_40 1) (= 1 v_~E_M~0_27)) InVars {~E_M~0=v_~E_M~0_27} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_40, ~E_M~0=v_~E_M~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 3100#L305-7 [3806] L305-7-->L745-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 3183#L745-21 [2835] L745-21-->L745-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_42) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} AuxVars[] AssignedVars[] 3184#L745-23 [2838] L745-23-->L313-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_43, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 2878#L313-21 [3468] L313-21-->L313-23: Formula: (> v_~t1_pc~0_22 1) InVars {~t1_pc~0=v_~t1_pc~0_22} OutVars{~t1_pc~0=v_~t1_pc~0_22} AuxVars[] AssignedVars[] 2880#L313-23 [2249] L313-23-->L324-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 2885#L324-7 [3813] L324-7-->L753-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 2915#L753-21 [2292] L753-21-->L753-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} AuxVars[] AssignedVars[] 2916#L753-23 [2297] L753-23-->L332-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_22|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 2918#L332-21 [2470] L332-21-->L333-7: Formula: (= 1 v_~t2_pc~0_21) InVars {~t2_pc~0=v_~t2_pc~0_21} OutVars{~t2_pc~0=v_~t2_pc~0_21} AuxVars[] AssignedVars[] 2998#L333-7 [2431] L333-7-->L343-7: Formula: (and (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_46 1) (= 1 v_~E_2~0_27)) InVars {~E_2~0=v_~E_2~0_27} OutVars{~E_2~0=v_~E_2~0_27, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_46} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 3000#L343-7 [3820] L343-7-->L761-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 3030#L761-21 [3538] L761-21-->L761-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___1~0_41 0) (= v_~t2_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41, ~t2_st~0=v_~t2_st~0_19} AuxVars[] AssignedVars[~t2_st~0] 3031#L761-23 [2493] L761-23-->L351-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_22|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 3032#L351-21 [2679] L351-21-->L352-7: Formula: (= v_~t3_pc~0_21 1) InVars {~t3_pc~0=v_~t3_pc~0_21} OutVars{~t3_pc~0=v_~t3_pc~0_21} AuxVars[] AssignedVars[] 3116#L352-7 [2622] L352-7-->L362-7: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_46 1) (= 1 v_~E_3~0_27)) InVars {~E_3~0=v_~E_3~0_27} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_46, ~E_3~0=v_~E_3~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 3047#L362-7 [3827] L362-7-->L769-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 3048#L769-21 [2534] L769-21-->L769-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} AuxVars[] AssignedVars[] 3054#L769-23 [2537] L769-23-->L370-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_43, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 3057#L370-21 [2927] L370-21-->L371-7: Formula: (= 1 v_~t4_pc~0_21) InVars {~t4_pc~0=v_~t4_pc~0_21} OutVars{~t4_pc~0=v_~t4_pc~0_21} AuxVars[] AssignedVars[] 3193#L371-7 [2863] L371-7-->L381-7: Formula: (and (= 1 v_~E_4~0_27) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_46 1)) InVars {~E_4~0=v_~E_4~0_27} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_46, ~E_4~0=v_~E_4~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 3159#L381-7 [3834] L381-7-->L777-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 3141#L777-21 [2705] L777-21-->L777-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} AuxVars[] AssignedVars[] 3142#L777-23 [2708] L777-23-->L389-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_22|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 2780#L389-21 [3636] L389-21-->L389-23: Formula: (> v_~t5_pc~0_22 1) InVars {~t5_pc~0=v_~t5_pc~0_22} OutVars{~t5_pc~0=v_~t5_pc~0_22} AuxVars[] AssignedVars[] 2755#L389-23 [2111] L389-23-->L400-7: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 2756#L400-7 [3837] L400-7-->L785-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 2796#L785-21 [3654] L785-21-->L785-23: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_41 0) (= v_~t5_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} OutVars{~t5_st~0=v_~t5_st~0_19, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} AuxVars[] AssignedVars[~t5_st~0] 2804#L785-23 [2161] L785-23-->L669-3: Formula: (and (= v_~M_E~0_12 1) (= v_~M_E~0_11 2)) InVars {~M_E~0=v_~M_E~0_12} OutVars{~M_E~0=v_~M_E~0_11} AuxVars[] AssignedVars[~M_E~0] 2806#L669-3 [2824] L669-3-->L674-3: Formula: (and (= v_~T1_E~0_11 2) (= v_~T1_E~0_12 1)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 3025#L674-3 [2477] L674-3-->L679-3: Formula: (and (= 1 v_~T2_E~0_12) (= v_~T2_E~0_11 2)) InVars {~T2_E~0=v_~T2_E~0_12} OutVars{~T2_E~0=v_~T2_E~0_11} AuxVars[] AssignedVars[~T2_E~0] 3026#L679-3 [3664] L679-3-->L684-3: Formula: (< 1 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 2957#L684-3 [3666] L684-3-->L689-3: Formula: (> v_~T4_E~0_13 1) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 2958#L689-3 [3668] L689-3-->L694-3: Formula: (< 1 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 2980#L694-3 [2405] L694-3-->L699-3: Formula: (and (= 1 v_~E_M~0_30) (= v_~E_M~0_29 2)) InVars {~E_M~0=v_~E_M~0_30} OutVars{~E_M~0=v_~E_M~0_29} AuxVars[] AssignedVars[~E_M~0] 2881#L699-3 [2245] L699-3-->L704-3: Formula: (and (= v_~E_1~0_29 2) (= 1 v_~E_1~0_30)) InVars {~E_1~0=v_~E_1~0_30} OutVars{~E_1~0=v_~E_1~0_29} AuxVars[] AssignedVars[~E_1~0] 2882#L704-3 [2661] L704-3-->L709-3: Formula: (and (= v_~E_2~0_29 2) (= 1 v_~E_2~0_30)) InVars {~E_2~0=v_~E_2~0_30} OutVars{~E_2~0=v_~E_2~0_29} AuxVars[] AssignedVars[~E_2~0] 2760#L709-3 [2114] L709-3-->L714-3: Formula: (and (= v_~E_3~0_29 2) (= 1 v_~E_3~0_30)) InVars {~E_3~0=v_~E_3~0_30} OutVars{~E_3~0=v_~E_3~0_29} AuxVars[] AssignedVars[~E_3~0] 2761#L714-3 [2573] L714-3-->L719-3: Formula: (and (= v_~E_4~0_29 2) (= 1 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 2846#L719-3 [3680] L719-3-->L724-3: Formula: (> 1 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 2847#L724-3 [2818] L724-3-->L454-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_23} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 3019#L454-1 [2466] L454-1-->L486-1: Formula: (and (= 0 v_~m_st~0_20) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26 1)) InVars {~m_st~0=v_~m_st~0_20} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 2833#L486-1 [3838] L486-1-->L949: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret15, ULTIMATE.start_start_simulation_~tmp~3] 2964#L949 [3688] L949-->L949-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_1) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} AuxVars[] AssignedVars[] 3027#L949-1 [2479] L949-1-->L454-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_1} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 3006#L454-2 [2438] L454-2-->L486-2: Formula: (and (= v_~m_st~0_2 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4 1)) InVars {~m_st~0=v_~m_st~0_2} OutVars{~m_st~0=v_~m_st~0_2, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 2838#L486-2 [3840] L486-2-->L904: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 2935#L904 [2393] L904-->L911: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 2971#L911 [3851] L911-->L930-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_6|, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 2843#L930-1 312.69/160.48 [2019-03-28 12:21:52,948 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.48 [2019-03-28 12:21:52,948 INFO L82 PathProgramCache]: Analyzing trace with hash -994134836, now seen corresponding path program 1 times 312.69/160.48 [2019-03-28 12:21:52,948 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.48 [2019-03-28 12:21:52,948 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.48 [2019-03-28 12:21:52,949 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:52,950 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:52,950 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:52,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.48 [2019-03-28 12:21:52,986 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.48 [2019-03-28 12:21:52,986 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.48 [2019-03-28 12:21:52,987 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 312.69/160.48 [2019-03-28 12:21:52,987 INFO L799 eck$LassoCheckResult]: stem already infeasible 312.69/160.48 [2019-03-28 12:21:52,987 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.48 [2019-03-28 12:21:52,987 INFO L82 PathProgramCache]: Analyzing trace with hash 506531834, now seen corresponding path program 1 times 312.69/160.48 [2019-03-28 12:21:52,987 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.48 [2019-03-28 12:21:52,988 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.48 [2019-03-28 12:21:52,988 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:52,989 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:52,989 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:52,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.48 [2019-03-28 12:21:53,037 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.48 [2019-03-28 12:21:53,038 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.48 [2019-03-28 12:21:53,038 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 312.69/160.48 [2019-03-28 12:21:53,038 INFO L811 eck$LassoCheckResult]: loop already infeasible 312.69/160.48 [2019-03-28 12:21:53,039 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 312.69/160.48 [2019-03-28 12:21:53,039 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 312.69/160.48 [2019-03-28 12:21:53,039 INFO L87 Difference]: Start difference. First operand 454 states and 1002 transitions. cyclomatic complexity: 549 Second operand 3 states. 312.69/160.48 [2019-03-28 12:21:53,560 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.48 [2019-03-28 12:21:53,560 INFO L93 Difference]: Finished difference Result 454 states and 1001 transitions. 312.69/160.48 [2019-03-28 12:21:53,560 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 312.69/160.48 [2019-03-28 12:21:53,561 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 454 states and 1001 transitions. 312.69/160.48 [2019-03-28 12:21:53,564 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 387 312.69/160.48 [2019-03-28 12:21:53,567 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 454 states to 454 states and 1001 transitions. 312.69/160.48 [2019-03-28 12:21:53,568 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 454 312.69/160.48 [2019-03-28 12:21:53,568 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 454 312.69/160.48 [2019-03-28 12:21:53,568 INFO L73 IsDeterministic]: Start isDeterministic. Operand 454 states and 1001 transitions. 312.69/160.48 [2019-03-28 12:21:53,569 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.48 [2019-03-28 12:21:53,570 INFO L706 BuchiCegarLoop]: Abstraction has 454 states and 1001 transitions. 312.69/160.48 [2019-03-28 12:21:53,570 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 454 states and 1001 transitions. 312.69/160.48 [2019-03-28 12:21:53,577 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 454 to 454. 312.69/160.48 [2019-03-28 12:21:53,578 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 454 states. 312.69/160.48 [2019-03-28 12:21:53,579 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 454 states to 454 states and 1001 transitions. 312.69/160.48 [2019-03-28 12:21:53,579 INFO L729 BuchiCegarLoop]: Abstraction has 454 states and 1001 transitions. 312.69/160.48 [2019-03-28 12:21:53,579 INFO L609 BuchiCegarLoop]: Abstraction has 454 states and 1001 transitions. 312.69/160.48 [2019-03-28 12:21:53,579 INFO L442 BuchiCegarLoop]: ======== Iteration 5============ 312.69/160.48 [2019-03-28 12:21:53,580 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 454 states and 1001 transitions. 312.69/160.48 [2019-03-28 12:21:53,582 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 387 312.69/160.48 [2019-03-28 12:21:53,582 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.48 [2019-03-28 12:21:53,582 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.48 [2019-03-28 12:21:53,584 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.48 [2019-03-28 12:21:53,584 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.48 [2019-03-28 12:21:53,585 INFO L794 eck$LassoCheckResult]: Stem: 4036#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 3852#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 3853#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 3920#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 3921#L426-1 [3227] L426-1-->L431-1: Formula: (and (= v_~t3_st~0_5 2) (< v_~t3_i~0_4 1)) InVars {~t3_i~0=v_~t3_i~0_4} OutVars{~t3_st~0=v_~t3_st~0_5, ~t3_i~0=v_~t3_i~0_4} AuxVars[] AssignedVars[~t3_st~0] 3854#L431-1 [3229] L431-1-->L436-1: Formula: (and (< v_~t4_i~0_4 1) (= v_~t4_st~0_5 2)) InVars {~t4_i~0=v_~t4_i~0_4} OutVars{~t4_i~0=v_~t4_i~0_4, ~t4_st~0=v_~t4_st~0_5} AuxVars[] AssignedVars[~t4_st~0] 3855#L436-1 [3231] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_5 2) (> v_~t5_i~0_4 1)) InVars {~t5_i~0=v_~t5_i~0_4} OutVars{~t5_i~0=v_~t5_i~0_4, ~t5_st~0=v_~t5_st~0_5} AuxVars[] AssignedVars[~t5_st~0] 3893#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 3894#L601-1 [2765] L601-1-->L606-1: Formula: (and (= v_~T1_E~0_2 1) (= 0 v_~T1_E~0_3)) InVars {~T1_E~0=v_~T1_E~0_3} OutVars{~T1_E~0=v_~T1_E~0_2} AuxVars[] AssignedVars[~T1_E~0] 3897#L606-1 [2407] L606-1-->L611-1: Formula: (and (= 0 v_~T2_E~0_3) (= v_~T2_E~0_2 1)) InVars {~T2_E~0=v_~T2_E~0_3} OutVars{~T2_E~0=v_~T2_E~0_2} AuxVars[] AssignedVars[~T2_E~0] 3799#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 3800#L616-1 [3241] L616-1-->L621-1: Formula: (< v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 3678#L621-1 [3243] L621-1-->L626-1: Formula: (< v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 3679#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 3764#L631-1 [3247] L631-1-->L636-1: Formula: (< v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 3765#L636-1 [2819] L636-1-->L641-1: Formula: (and (= v_~E_2~0_3 0) (= v_~E_2~0_2 1)) InVars {~E_2~0=v_~E_2~0_3} OutVars{~E_2~0=v_~E_2~0_2} AuxVars[] AssignedVars[~E_2~0] 3939#L641-1 [2474] L641-1-->L646-1: Formula: (and (= v_~E_3~0_3 0) (= v_~E_3~0_2 1)) InVars {~E_3~0=v_~E_3~0_3} OutVars{~E_3~0=v_~E_3~0_2} AuxVars[] AssignedVars[~E_3~0] 3940#L646-1 [2935] L646-1-->L651-1: Formula: (and (= v_~E_4~0_2 1) (= v_~E_4~0_3 0)) InVars {~E_4~0=v_~E_4~0_3} OutVars{~E_4~0=v_~E_4~0_2} AuxVars[] AssignedVars[~E_4~0] 3885#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 3886#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 4096#L294 [2854] L294-->L295: Formula: (= v_~m_pc~0_2 1) InVars {~m_pc~0=v_~m_pc~0_2} OutVars{~m_pc~0=v_~m_pc~0_2} AuxVars[] AssignedVars[] 4009#L295 [2595] L295-->L305: Formula: (and (= v_~E_M~0_5 1) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_4 1)) InVars {~E_M~0=v_~E_M~0_5} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_4, ~E_M~0=v_~E_M~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 4010#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 4115#L745 [3261] L745-->L745-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_5) (= v_~m_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} OutVars{~m_st~0=v_~m_st~0_6, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} AuxVars[] AssignedVars[~m_st~0] 4120#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 3835#L313 [2301] L313-->L314: Formula: (= v_~t1_pc~0_2 1) InVars {~t1_pc~0=v_~t1_pc~0_2} OutVars{~t1_pc~0=v_~t1_pc~0_2} AuxVars[] AssignedVars[] 3791#L314 [2241] L314-->L324: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_4 1) (= v_~E_1~0_5 1)) InVars {~E_1~0=v_~E_1~0_5} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_4, ~E_1~0=v_~E_1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 3793#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 3693#L753 [3267] L753-->L753-2: Formula: (and (> 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_5) (= v_~t1_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_5, ~t1_st~0=v_~t1_st~0_6} AuxVars[] AssignedVars[~t1_st~0] 3694#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 3698#L332 [3269] L332-->L332-2: Formula: (> v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 3862#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 3860#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 3861#L761 [3273] L761-->L761-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_5) (= v_~t2_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5, ~t2_st~0=v_~t2_st~0_6} AuxVars[] AssignedVars[~t2_st~0] 3881#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 3882#L351 [2567] L351-->L352: Formula: (= 1 v_~t3_pc~0_2) InVars {~t3_pc~0=v_~t3_pc~0_2} OutVars{~t3_pc~0=v_~t3_pc~0_2} AuxVars[] AssignedVars[] 3998#L352 [2655] L352-->L362: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_4 1) (= v_~E_3~0_5 1)) InVars {~E_3~0=v_~E_3~0_5} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_4, ~E_3~0=v_~E_3~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 3980#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 3997#L769 [3279] L769-->L769-2: Formula: (and (= v_~t3_st~0_6 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_5)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} OutVars{~t3_st~0=v_~t3_st~0_6, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} AuxVars[] AssignedVars[~t3_st~0] 4001#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 4002#L370 [3281] L370-->L370-2: Formula: (> v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 4085#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 4081#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 4082#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 4095#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 3755#L389 [2193] L389-->L390: Formula: (= 1 v_~t5_pc~0_2) InVars {~t5_pc~0=v_~t5_pc~0_2} OutVars{~t5_pc~0=v_~t5_pc~0_2} AuxVars[] AssignedVars[] 3756#L390 [2343] L390-->L400: Formula: (and (= v_~E_5~0_5 1) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4 1)) InVars {~E_5~0=v_~E_5~0_5} OutVars{~E_5~0=v_~E_5~0_5, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 3725#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 3751#L785 [3291] L785-->L785-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_5) (= v_~t5_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} OutVars{~t5_st~0=v_~t5_st~0_6, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} AuxVars[] AssignedVars[~t5_st~0] 3771#L785-2 [3293] L785-2-->L669-1: Formula: (> 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 3773#L669-1 [3295] L669-1-->L674-1: Formula: (> 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 3937#L674-1 [2472] L674-1-->L679-1: Formula: (and (= 1 v_~T2_E~0_6) (= v_~T2_E~0_5 2)) InVars {~T2_E~0=v_~T2_E~0_6} OutVars{~T2_E~0=v_~T2_E~0_5} AuxVars[] AssignedVars[~T2_E~0] 3938#L679-1 [3299] L679-1-->L684-1: Formula: (< v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 3883#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 3884#L689-1 [2782] L689-1-->L694-1: Formula: (and (= v_~T5_E~0_6 1) (= v_~T5_E~0_5 2)) InVars {~T5_E~0=v_~T5_E~0_6} OutVars{~T5_E~0=v_~T5_E~0_5} AuxVars[] AssignedVars[~T5_E~0] 4030#L694-1 [3305] L694-1-->L699-1: Formula: (< v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 3820#L699-1 [3307] L699-1-->L704-1: Formula: (< v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 3821#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 3667#L709-1 [3311] L709-1-->L714-1: Formula: (< v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 3668#L714-1 [2569] L714-1-->L719-1: Formula: (and (= v_~E_4~0_8 1) (= v_~E_4~0_7 2)) InVars {~E_4~0=v_~E_4~0_8} OutVars{~E_4~0=v_~E_4~0_7} AuxVars[] AssignedVars[~E_4~0] 3758#L719-1 [2198] L719-1-->L930-1: Formula: (and (= v_~E_5~0_8 1) (= v_~E_5~0_7 2)) InVars {~E_5~0=v_~E_5~0_8} OutVars{~E_5~0=v_~E_5~0_7} AuxVars[] AssignedVars[~E_5~0] 3759#L930-1 312.69/160.48 [2019-03-28 12:21:53,586 INFO L796 eck$LassoCheckResult]: Loop: 3759#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 3766#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 3767#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 3746#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 3811#L501 [3784] L501-->L601-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 3812#L601-2 [2768] L601-2-->L601-4: Formula: (and (= v_~M_E~0_8 1) (= 0 v_~M_E~0_9)) InVars {~M_E~0=v_~M_E~0_9} OutVars{~M_E~0=v_~M_E~0_8} AuxVars[] AssignedVars[~M_E~0] 4094#L601-4 [2773] L601-4-->L606-3: Formula: (and (= v_~T1_E~0_8 1) (= 0 v_~T1_E~0_9)) InVars {~T1_E~0=v_~T1_E~0_9} OutVars{~T1_E~0=v_~T1_E~0_8} AuxVars[] AssignedVars[~T1_E~0] 3900#L606-3 [2413] L606-3-->L611-3: Formula: (and (= v_~T2_E~0_8 1) (= 0 v_~T2_E~0_9)) InVars {~T2_E~0=v_~T2_E~0_9} OutVars{~T2_E~0=v_~T2_E~0_8} AuxVars[] AssignedVars[~T2_E~0] 3809#L611-3 [2256] L611-3-->L616-3: Formula: (and (= v_~T3_E~0_8 1) (= v_~T3_E~0_9 0)) InVars {~T3_E~0=v_~T3_E~0_9} OutVars{~T3_E~0=v_~T3_E~0_8} AuxVars[] AssignedVars[~T3_E~0] 3810#L616-3 [3338] L616-3-->L621-3: Formula: (< v_~T4_E~0_10 0) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 3684#L621-3 [3346] L621-3-->L626-3: Formula: (< 0 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 3685#L626-3 [2580] L626-3-->L631-3: Formula: (and (= v_~E_M~0_24 1) (= 0 v_~E_M~0_25)) InVars {~E_M~0=v_~E_M~0_25} OutVars{~E_M~0=v_~E_M~0_24} AuxVars[] AssignedVars[~E_M~0] 3740#L631-3 [2180] L631-3-->L636-3: Formula: (and (= v_~E_1~0_24 1) (= 0 v_~E_1~0_25)) InVars {~E_1~0=v_~E_1~0_25} OutVars{~E_1~0=v_~E_1~0_24} AuxVars[] AssignedVars[~E_1~0] 3741#L636-3 [3376] L636-3-->L641-3: Formula: (< 0 v_~E_2~0_26) InVars {~E_2~0=v_~E_2~0_26} OutVars{~E_2~0=v_~E_2~0_26} AuxVars[] AssignedVars[] 3931#L641-3 [2455] L641-3-->L646-3: Formula: (and (= 0 v_~E_3~0_25) (= v_~E_3~0_24 1)) InVars {~E_3~0=v_~E_3~0_25} OutVars{~E_3~0=v_~E_3~0_24} AuxVars[] AssignedVars[~E_3~0] 3932#L646-3 [2912] L646-3-->L651-3: Formula: (and (= 0 v_~E_4~0_25) (= v_~E_4~0_24 1)) InVars {~E_4~0=v_~E_4~0_25} OutVars{~E_4~0=v_~E_4~0_24} AuxVars[] AssignedVars[~E_4~0] 3876#L651-3 [3410] L651-3-->L656-3: Formula: (> 0 v_~E_5~0_26) InVars {~E_5~0=v_~E_5~0_26} OutVars{~E_5~0=v_~E_5~0_26} AuxVars[] AssignedVars[] 3877#L656-3 [2767] L656-3-->L294-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_37, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_37, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_22|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_22|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_22|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_37, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_37, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_22|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_22|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_22|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_22|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_37, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_37, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_37} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 4093#L294-21 [3426] L294-21-->L294-23: Formula: (< v_~m_pc~0_22 1) InVars {~m_pc~0=v_~m_pc~0_22} OutVars{~m_pc~0=v_~m_pc~0_22} AuxVars[] AssignedVars[] 4017#L294-23 [2803] L294-23-->L305-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_41 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_41} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 4016#L305-7 [3806] L305-7-->L745-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 4099#L745-21 [2835] L745-21-->L745-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_42) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} AuxVars[] AssignedVars[] 4100#L745-23 [2838] L745-23-->L313-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_43, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 3794#L313-21 [2243] L313-21-->L314-7: Formula: (= v_~t1_pc~0_21 1) InVars {~t1_pc~0=v_~t1_pc~0_21} OutVars{~t1_pc~0=v_~t1_pc~0_21} AuxVars[] AssignedVars[] 3795#L314-7 [2796] L314-7-->L324-7: Formula: (and (= 1 v_~E_1~0_27) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_46 1)) InVars {~E_1~0=v_~E_1~0_27} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_46, ~E_1~0=v_~E_1~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 3801#L324-7 [3813] L324-7-->L753-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 3831#L753-21 [2292] L753-21-->L753-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} AuxVars[] AssignedVars[] 3832#L753-23 [2297] L753-23-->L332-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_22|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 3834#L332-21 [2470] L332-21-->L333-7: Formula: (= 1 v_~t2_pc~0_21) InVars {~t2_pc~0=v_~t2_pc~0_21} OutVars{~t2_pc~0=v_~t2_pc~0_21} AuxVars[] AssignedVars[] 3914#L333-7 [2431] L333-7-->L343-7: Formula: (and (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_46 1) (= 1 v_~E_2~0_27)) InVars {~E_2~0=v_~E_2~0_27} OutVars{~E_2~0=v_~E_2~0_27, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_46} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 3916#L343-7 [3820] L343-7-->L761-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 3946#L761-21 [3538] L761-21-->L761-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___1~0_41 0) (= v_~t2_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41, ~t2_st~0=v_~t2_st~0_19} AuxVars[] AssignedVars[~t2_st~0] 3947#L761-23 [2493] L761-23-->L351-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_22|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 3948#L351-21 [2679] L351-21-->L352-7: Formula: (= v_~t3_pc~0_21 1) InVars {~t3_pc~0=v_~t3_pc~0_21} OutVars{~t3_pc~0=v_~t3_pc~0_21} AuxVars[] AssignedVars[] 4032#L352-7 [2622] L352-7-->L362-7: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_46 1) (= 1 v_~E_3~0_27)) InVars {~E_3~0=v_~E_3~0_27} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_46, ~E_3~0=v_~E_3~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 3963#L362-7 [3827] L362-7-->L769-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 3964#L769-21 [2534] L769-21-->L769-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} AuxVars[] AssignedVars[] 3970#L769-23 [2537] L769-23-->L370-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_43, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 3973#L370-21 [2927] L370-21-->L371-7: Formula: (= 1 v_~t4_pc~0_21) InVars {~t4_pc~0=v_~t4_pc~0_21} OutVars{~t4_pc~0=v_~t4_pc~0_21} AuxVars[] AssignedVars[] 4109#L371-7 [2863] L371-7-->L381-7: Formula: (and (= 1 v_~E_4~0_27) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_46 1)) InVars {~E_4~0=v_~E_4~0_27} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_46, ~E_4~0=v_~E_4~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 4075#L381-7 [3834] L381-7-->L777-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 4057#L777-21 [2705] L777-21-->L777-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} AuxVars[] AssignedVars[] 4058#L777-23 [2708] L777-23-->L389-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_22|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 3696#L389-21 [2132] L389-21-->L390-7: Formula: (= v_~t5_pc~0_21 1) InVars {~t5_pc~0=v_~t5_pc~0_21} OutVars{~t5_pc~0=v_~t5_pc~0_21} AuxVars[] AssignedVars[] 3697#L390-7 [2330] L390-7-->L400-7: Formula: (and (= 1 v_~E_5~0_27) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46 1)) InVars {~E_5~0=v_~E_5~0_27} OutVars{~E_5~0=v_~E_5~0_27, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 3672#L400-7 [3837] L400-7-->L785-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 3712#L785-21 [3654] L785-21-->L785-23: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_41 0) (= v_~t5_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} OutVars{~t5_st~0=v_~t5_st~0_19, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} AuxVars[] AssignedVars[~t5_st~0] 3720#L785-23 [2161] L785-23-->L669-3: Formula: (and (= v_~M_E~0_12 1) (= v_~M_E~0_11 2)) InVars {~M_E~0=v_~M_E~0_12} OutVars{~M_E~0=v_~M_E~0_11} AuxVars[] AssignedVars[~M_E~0] 3722#L669-3 [2824] L669-3-->L674-3: Formula: (and (= v_~T1_E~0_11 2) (= v_~T1_E~0_12 1)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 3941#L674-3 [2477] L674-3-->L679-3: Formula: (and (= 1 v_~T2_E~0_12) (= v_~T2_E~0_11 2)) InVars {~T2_E~0=v_~T2_E~0_12} OutVars{~T2_E~0=v_~T2_E~0_11} AuxVars[] AssignedVars[~T2_E~0] 3942#L679-3 [3664] L679-3-->L684-3: Formula: (< 1 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 3873#L684-3 [3666] L684-3-->L689-3: Formula: (> v_~T4_E~0_13 1) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 3874#L689-3 [3668] L689-3-->L694-3: Formula: (< 1 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 3896#L694-3 [2405] L694-3-->L699-3: Formula: (and (= 1 v_~E_M~0_30) (= v_~E_M~0_29 2)) InVars {~E_M~0=v_~E_M~0_30} OutVars{~E_M~0=v_~E_M~0_29} AuxVars[] AssignedVars[~E_M~0] 3797#L699-3 [2245] L699-3-->L704-3: Formula: (and (= v_~E_1~0_29 2) (= 1 v_~E_1~0_30)) InVars {~E_1~0=v_~E_1~0_30} OutVars{~E_1~0=v_~E_1~0_29} AuxVars[] AssignedVars[~E_1~0] 3798#L704-3 [2661] L704-3-->L709-3: Formula: (and (= v_~E_2~0_29 2) (= 1 v_~E_2~0_30)) InVars {~E_2~0=v_~E_2~0_30} OutVars{~E_2~0=v_~E_2~0_29} AuxVars[] AssignedVars[~E_2~0] 3676#L709-3 [2114] L709-3-->L714-3: Formula: (and (= v_~E_3~0_29 2) (= 1 v_~E_3~0_30)) InVars {~E_3~0=v_~E_3~0_30} OutVars{~E_3~0=v_~E_3~0_29} AuxVars[] AssignedVars[~E_3~0] 3677#L714-3 [2573] L714-3-->L719-3: Formula: (and (= v_~E_4~0_29 2) (= 1 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 3762#L719-3 [3680] L719-3-->L724-3: Formula: (> 1 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 3763#L724-3 [2818] L724-3-->L454-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_23} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 3935#L454-1 [2466] L454-1-->L486-1: Formula: (and (= 0 v_~m_st~0_20) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26 1)) InVars {~m_st~0=v_~m_st~0_20} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 3749#L486-1 [3838] L486-1-->L949: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret15, ULTIMATE.start_start_simulation_~tmp~3] 3880#L949 [3688] L949-->L949-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_1) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} AuxVars[] AssignedVars[] 3943#L949-1 [2479] L949-1-->L454-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_1} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 3922#L454-2 [2438] L454-2-->L486-2: Formula: (and (= v_~m_st~0_2 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4 1)) InVars {~m_st~0=v_~m_st~0_2} OutVars{~m_st~0=v_~m_st~0_2, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 3754#L486-2 [3840] L486-2-->L904: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 3851#L904 [2393] L904-->L911: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 3887#L911 [3851] L911-->L930-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_6|, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 3759#L930-1 312.69/160.48 [2019-03-28 12:21:53,586 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.48 [2019-03-28 12:21:53,586 INFO L82 PathProgramCache]: Analyzing trace with hash -84702880, now seen corresponding path program 1 times 312.69/160.48 [2019-03-28 12:21:53,587 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.48 [2019-03-28 12:21:53,587 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.48 [2019-03-28 12:21:53,588 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:53,588 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:53,588 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:53,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.48 [2019-03-28 12:21:53,614 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.48 [2019-03-28 12:21:53,615 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.48 [2019-03-28 12:21:53,615 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 312.69/160.48 [2019-03-28 12:21:53,615 INFO L799 eck$LassoCheckResult]: stem already infeasible 312.69/160.48 [2019-03-28 12:21:53,615 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.48 [2019-03-28 12:21:53,616 INFO L82 PathProgramCache]: Analyzing trace with hash -1304871118, now seen corresponding path program 1 times 312.69/160.48 [2019-03-28 12:21:53,616 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.48 [2019-03-28 12:21:53,616 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.48 [2019-03-28 12:21:53,617 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:53,617 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:53,617 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:53,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.48 [2019-03-28 12:21:53,650 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.48 [2019-03-28 12:21:53,650 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.48 [2019-03-28 12:21:53,650 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 312.69/160.48 [2019-03-28 12:21:53,650 INFO L811 eck$LassoCheckResult]: loop already infeasible 312.69/160.48 [2019-03-28 12:21:53,651 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 312.69/160.48 [2019-03-28 12:21:53,651 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 312.69/160.48 [2019-03-28 12:21:53,651 INFO L87 Difference]: Start difference. First operand 454 states and 1001 transitions. cyclomatic complexity: 548 Second operand 3 states. 312.69/160.48 [2019-03-28 12:21:54,158 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.48 [2019-03-28 12:21:54,158 INFO L93 Difference]: Finished difference Result 454 states and 1000 transitions. 312.69/160.48 [2019-03-28 12:21:54,159 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 312.69/160.48 [2019-03-28 12:21:54,159 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 454 states and 1000 transitions. 312.69/160.48 [2019-03-28 12:21:54,162 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 387 312.69/160.48 [2019-03-28 12:21:54,165 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 454 states to 454 states and 1000 transitions. 312.69/160.48 [2019-03-28 12:21:54,165 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 454 312.69/160.48 [2019-03-28 12:21:54,166 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 454 312.69/160.48 [2019-03-28 12:21:54,166 INFO L73 IsDeterministic]: Start isDeterministic. Operand 454 states and 1000 transitions. 312.69/160.48 [2019-03-28 12:21:54,167 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.48 [2019-03-28 12:21:54,167 INFO L706 BuchiCegarLoop]: Abstraction has 454 states and 1000 transitions. 312.69/160.48 [2019-03-28 12:21:54,168 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 454 states and 1000 transitions. 312.69/160.48 [2019-03-28 12:21:54,175 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 454 to 454. 312.69/160.48 [2019-03-28 12:21:54,175 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 454 states. 312.69/160.48 [2019-03-28 12:21:54,177 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 454 states to 454 states and 1000 transitions. 312.69/160.48 [2019-03-28 12:21:54,177 INFO L729 BuchiCegarLoop]: Abstraction has 454 states and 1000 transitions. 312.69/160.48 [2019-03-28 12:21:54,177 INFO L609 BuchiCegarLoop]: Abstraction has 454 states and 1000 transitions. 312.69/160.48 [2019-03-28 12:21:54,177 INFO L442 BuchiCegarLoop]: ======== Iteration 6============ 312.69/160.48 [2019-03-28 12:21:54,177 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 454 states and 1000 transitions. 312.69/160.48 [2019-03-28 12:21:54,179 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 387 312.69/160.48 [2019-03-28 12:21:54,179 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.48 [2019-03-28 12:21:54,180 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.48 [2019-03-28 12:21:54,181 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.48 [2019-03-28 12:21:54,181 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.48 [2019-03-28 12:21:54,182 INFO L794 eck$LassoCheckResult]: Stem: 4952#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 4768#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 4769#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 4836#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 4837#L426-1 [3226] L426-1-->L431-1: Formula: (and (= v_~t3_st~0_5 2) (> v_~t3_i~0_4 1)) InVars {~t3_i~0=v_~t3_i~0_4} OutVars{~t3_st~0=v_~t3_st~0_5, ~t3_i~0=v_~t3_i~0_4} AuxVars[] AssignedVars[~t3_st~0] 4770#L431-1 [3229] L431-1-->L436-1: Formula: (and (< v_~t4_i~0_4 1) (= v_~t4_st~0_5 2)) InVars {~t4_i~0=v_~t4_i~0_4} OutVars{~t4_i~0=v_~t4_i~0_4, ~t4_st~0=v_~t4_st~0_5} AuxVars[] AssignedVars[~t4_st~0] 4771#L436-1 [3231] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_5 2) (> v_~t5_i~0_4 1)) InVars {~t5_i~0=v_~t5_i~0_4} OutVars{~t5_i~0=v_~t5_i~0_4, ~t5_st~0=v_~t5_st~0_5} AuxVars[] AssignedVars[~t5_st~0] 4809#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 4810#L601-1 [2765] L601-1-->L606-1: Formula: (and (= v_~T1_E~0_2 1) (= 0 v_~T1_E~0_3)) InVars {~T1_E~0=v_~T1_E~0_3} OutVars{~T1_E~0=v_~T1_E~0_2} AuxVars[] AssignedVars[~T1_E~0] 4813#L606-1 [2407] L606-1-->L611-1: Formula: (and (= 0 v_~T2_E~0_3) (= v_~T2_E~0_2 1)) InVars {~T2_E~0=v_~T2_E~0_3} OutVars{~T2_E~0=v_~T2_E~0_2} AuxVars[] AssignedVars[~T2_E~0] 4715#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 4716#L616-1 [3241] L616-1-->L621-1: Formula: (< v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 4594#L621-1 [3243] L621-1-->L626-1: Formula: (< v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 4595#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 4680#L631-1 [3247] L631-1-->L636-1: Formula: (< v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 4681#L636-1 [2819] L636-1-->L641-1: Formula: (and (= v_~E_2~0_3 0) (= v_~E_2~0_2 1)) InVars {~E_2~0=v_~E_2~0_3} OutVars{~E_2~0=v_~E_2~0_2} AuxVars[] AssignedVars[~E_2~0] 4855#L641-1 [2474] L641-1-->L646-1: Formula: (and (= v_~E_3~0_3 0) (= v_~E_3~0_2 1)) InVars {~E_3~0=v_~E_3~0_3} OutVars{~E_3~0=v_~E_3~0_2} AuxVars[] AssignedVars[~E_3~0] 4856#L646-1 [2935] L646-1-->L651-1: Formula: (and (= v_~E_4~0_2 1) (= v_~E_4~0_3 0)) InVars {~E_4~0=v_~E_4~0_3} OutVars{~E_4~0=v_~E_4~0_2} AuxVars[] AssignedVars[~E_4~0] 4801#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 4802#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 5012#L294 [2854] L294-->L295: Formula: (= v_~m_pc~0_2 1) InVars {~m_pc~0=v_~m_pc~0_2} OutVars{~m_pc~0=v_~m_pc~0_2} AuxVars[] AssignedVars[] 4925#L295 [2595] L295-->L305: Formula: (and (= v_~E_M~0_5 1) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_4 1)) InVars {~E_M~0=v_~E_M~0_5} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_4, ~E_M~0=v_~E_M~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 4926#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 5031#L745 [3261] L745-->L745-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_5) (= v_~m_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} OutVars{~m_st~0=v_~m_st~0_6, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} AuxVars[] AssignedVars[~m_st~0] 5036#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 4751#L313 [2301] L313-->L314: Formula: (= v_~t1_pc~0_2 1) InVars {~t1_pc~0=v_~t1_pc~0_2} OutVars{~t1_pc~0=v_~t1_pc~0_2} AuxVars[] AssignedVars[] 4707#L314 [2241] L314-->L324: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_4 1) (= v_~E_1~0_5 1)) InVars {~E_1~0=v_~E_1~0_5} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_4, ~E_1~0=v_~E_1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 4709#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 4609#L753 [3267] L753-->L753-2: Formula: (and (> 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_5) (= v_~t1_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_5, ~t1_st~0=v_~t1_st~0_6} AuxVars[] AssignedVars[~t1_st~0] 4610#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 4614#L332 [3269] L332-->L332-2: Formula: (> v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 4778#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 4776#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 4777#L761 [3273] L761-->L761-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_5) (= v_~t2_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5, ~t2_st~0=v_~t2_st~0_6} AuxVars[] AssignedVars[~t2_st~0] 4797#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 4798#L351 [2567] L351-->L352: Formula: (= 1 v_~t3_pc~0_2) InVars {~t3_pc~0=v_~t3_pc~0_2} OutVars{~t3_pc~0=v_~t3_pc~0_2} AuxVars[] AssignedVars[] 4914#L352 [2655] L352-->L362: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_4 1) (= v_~E_3~0_5 1)) InVars {~E_3~0=v_~E_3~0_5} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_4, ~E_3~0=v_~E_3~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 4896#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 4913#L769 [3279] L769-->L769-2: Formula: (and (= v_~t3_st~0_6 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_5)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} OutVars{~t3_st~0=v_~t3_st~0_6, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} AuxVars[] AssignedVars[~t3_st~0] 4917#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 4918#L370 [3281] L370-->L370-2: Formula: (> v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 5001#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 4997#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 4998#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 5011#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 4671#L389 [2193] L389-->L390: Formula: (= 1 v_~t5_pc~0_2) InVars {~t5_pc~0=v_~t5_pc~0_2} OutVars{~t5_pc~0=v_~t5_pc~0_2} AuxVars[] AssignedVars[] 4672#L390 [2343] L390-->L400: Formula: (and (= v_~E_5~0_5 1) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4 1)) InVars {~E_5~0=v_~E_5~0_5} OutVars{~E_5~0=v_~E_5~0_5, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 4641#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 4667#L785 [3291] L785-->L785-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_5) (= v_~t5_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} OutVars{~t5_st~0=v_~t5_st~0_6, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} AuxVars[] AssignedVars[~t5_st~0] 4687#L785-2 [3293] L785-2-->L669-1: Formula: (> 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 4689#L669-1 [3295] L669-1-->L674-1: Formula: (> 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 4853#L674-1 [2472] L674-1-->L679-1: Formula: (and (= 1 v_~T2_E~0_6) (= v_~T2_E~0_5 2)) InVars {~T2_E~0=v_~T2_E~0_6} OutVars{~T2_E~0=v_~T2_E~0_5} AuxVars[] AssignedVars[~T2_E~0] 4854#L679-1 [3299] L679-1-->L684-1: Formula: (< v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 4799#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 4800#L689-1 [2782] L689-1-->L694-1: Formula: (and (= v_~T5_E~0_6 1) (= v_~T5_E~0_5 2)) InVars {~T5_E~0=v_~T5_E~0_6} OutVars{~T5_E~0=v_~T5_E~0_5} AuxVars[] AssignedVars[~T5_E~0] 4946#L694-1 [3305] L694-1-->L699-1: Formula: (< v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 4736#L699-1 [3307] L699-1-->L704-1: Formula: (< v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 4737#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 4583#L709-1 [3311] L709-1-->L714-1: Formula: (< v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 4584#L714-1 [2569] L714-1-->L719-1: Formula: (and (= v_~E_4~0_8 1) (= v_~E_4~0_7 2)) InVars {~E_4~0=v_~E_4~0_8} OutVars{~E_4~0=v_~E_4~0_7} AuxVars[] AssignedVars[~E_4~0] 4674#L719-1 [2198] L719-1-->L930-1: Formula: (and (= v_~E_5~0_8 1) (= v_~E_5~0_7 2)) InVars {~E_5~0=v_~E_5~0_8} OutVars{~E_5~0=v_~E_5~0_7} AuxVars[] AssignedVars[~E_5~0] 4675#L930-1 312.69/160.48 [2019-03-28 12:21:54,183 INFO L796 eck$LassoCheckResult]: Loop: 4675#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 4682#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 4683#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 4662#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 4727#L501 [3784] L501-->L601-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 4728#L601-2 [2768] L601-2-->L601-4: Formula: (and (= v_~M_E~0_8 1) (= 0 v_~M_E~0_9)) InVars {~M_E~0=v_~M_E~0_9} OutVars{~M_E~0=v_~M_E~0_8} AuxVars[] AssignedVars[~M_E~0] 5010#L601-4 [2773] L601-4-->L606-3: Formula: (and (= v_~T1_E~0_8 1) (= 0 v_~T1_E~0_9)) InVars {~T1_E~0=v_~T1_E~0_9} OutVars{~T1_E~0=v_~T1_E~0_8} AuxVars[] AssignedVars[~T1_E~0] 4816#L606-3 [2413] L606-3-->L611-3: Formula: (and (= v_~T2_E~0_8 1) (= 0 v_~T2_E~0_9)) InVars {~T2_E~0=v_~T2_E~0_9} OutVars{~T2_E~0=v_~T2_E~0_8} AuxVars[] AssignedVars[~T2_E~0] 4725#L611-3 [2256] L611-3-->L616-3: Formula: (and (= v_~T3_E~0_8 1) (= v_~T3_E~0_9 0)) InVars {~T3_E~0=v_~T3_E~0_9} OutVars{~T3_E~0=v_~T3_E~0_8} AuxVars[] AssignedVars[~T3_E~0] 4726#L616-3 [3338] L616-3-->L621-3: Formula: (< v_~T4_E~0_10 0) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 4600#L621-3 [3346] L621-3-->L626-3: Formula: (< 0 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 4601#L626-3 [2580] L626-3-->L631-3: Formula: (and (= v_~E_M~0_24 1) (= 0 v_~E_M~0_25)) InVars {~E_M~0=v_~E_M~0_25} OutVars{~E_M~0=v_~E_M~0_24} AuxVars[] AssignedVars[~E_M~0] 4656#L631-3 [2180] L631-3-->L636-3: Formula: (and (= v_~E_1~0_24 1) (= 0 v_~E_1~0_25)) InVars {~E_1~0=v_~E_1~0_25} OutVars{~E_1~0=v_~E_1~0_24} AuxVars[] AssignedVars[~E_1~0] 4657#L636-3 [3376] L636-3-->L641-3: Formula: (< 0 v_~E_2~0_26) InVars {~E_2~0=v_~E_2~0_26} OutVars{~E_2~0=v_~E_2~0_26} AuxVars[] AssignedVars[] 4847#L641-3 [2455] L641-3-->L646-3: Formula: (and (= 0 v_~E_3~0_25) (= v_~E_3~0_24 1)) InVars {~E_3~0=v_~E_3~0_25} OutVars{~E_3~0=v_~E_3~0_24} AuxVars[] AssignedVars[~E_3~0] 4848#L646-3 [2912] L646-3-->L651-3: Formula: (and (= 0 v_~E_4~0_25) (= v_~E_4~0_24 1)) InVars {~E_4~0=v_~E_4~0_25} OutVars{~E_4~0=v_~E_4~0_24} AuxVars[] AssignedVars[~E_4~0] 4792#L651-3 [3410] L651-3-->L656-3: Formula: (> 0 v_~E_5~0_26) InVars {~E_5~0=v_~E_5~0_26} OutVars{~E_5~0=v_~E_5~0_26} AuxVars[] AssignedVars[] 4793#L656-3 [2767] L656-3-->L294-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_37, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_37, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_22|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_22|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_22|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_37, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_37, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_22|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_22|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_22|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_22|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_37, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_37, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_37} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 5009#L294-21 [2808] L294-21-->L295-7: Formula: (= v_~m_pc~0_21 1) InVars {~m_pc~0=v_~m_pc~0_21} OutVars{~m_pc~0=v_~m_pc~0_21} AuxVars[] AssignedVars[] 4931#L295-7 [2602] L295-7-->L305-7: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_40 1) (= 1 v_~E_M~0_27)) InVars {~E_M~0=v_~E_M~0_27} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_40, ~E_M~0=v_~E_M~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 4932#L305-7 [3806] L305-7-->L745-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 5015#L745-21 [2835] L745-21-->L745-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_42) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} AuxVars[] AssignedVars[] 5016#L745-23 [2838] L745-23-->L313-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_43, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 4710#L313-21 [2243] L313-21-->L314-7: Formula: (= v_~t1_pc~0_21 1) InVars {~t1_pc~0=v_~t1_pc~0_21} OutVars{~t1_pc~0=v_~t1_pc~0_21} AuxVars[] AssignedVars[] 4711#L314-7 [2796] L314-7-->L324-7: Formula: (and (= 1 v_~E_1~0_27) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_46 1)) InVars {~E_1~0=v_~E_1~0_27} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_46, ~E_1~0=v_~E_1~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 4717#L324-7 [3813] L324-7-->L753-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 4747#L753-21 [2292] L753-21-->L753-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} AuxVars[] AssignedVars[] 4748#L753-23 [2297] L753-23-->L332-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_22|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 4750#L332-21 [2470] L332-21-->L333-7: Formula: (= 1 v_~t2_pc~0_21) InVars {~t2_pc~0=v_~t2_pc~0_21} OutVars{~t2_pc~0=v_~t2_pc~0_21} AuxVars[] AssignedVars[] 4830#L333-7 [2431] L333-7-->L343-7: Formula: (and (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_46 1) (= 1 v_~E_2~0_27)) InVars {~E_2~0=v_~E_2~0_27} OutVars{~E_2~0=v_~E_2~0_27, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_46} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 4832#L343-7 [3820] L343-7-->L761-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 4862#L761-21 [3538] L761-21-->L761-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___1~0_41 0) (= v_~t2_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41, ~t2_st~0=v_~t2_st~0_19} AuxVars[] AssignedVars[~t2_st~0] 4863#L761-23 [2493] L761-23-->L351-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_22|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 4864#L351-21 [2679] L351-21-->L352-7: Formula: (= v_~t3_pc~0_21 1) InVars {~t3_pc~0=v_~t3_pc~0_21} OutVars{~t3_pc~0=v_~t3_pc~0_21} AuxVars[] AssignedVars[] 4948#L352-7 [2622] L352-7-->L362-7: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_46 1) (= 1 v_~E_3~0_27)) InVars {~E_3~0=v_~E_3~0_27} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_46, ~E_3~0=v_~E_3~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 4879#L362-7 [3827] L362-7-->L769-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 4880#L769-21 [2534] L769-21-->L769-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} AuxVars[] AssignedVars[] 4886#L769-23 [2537] L769-23-->L370-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_43, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 4889#L370-21 [2927] L370-21-->L371-7: Formula: (= 1 v_~t4_pc~0_21) InVars {~t4_pc~0=v_~t4_pc~0_21} OutVars{~t4_pc~0=v_~t4_pc~0_21} AuxVars[] AssignedVars[] 5025#L371-7 [2863] L371-7-->L381-7: Formula: (and (= 1 v_~E_4~0_27) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_46 1)) InVars {~E_4~0=v_~E_4~0_27} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_46, ~E_4~0=v_~E_4~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 4991#L381-7 [3834] L381-7-->L777-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 4973#L777-21 [2705] L777-21-->L777-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} AuxVars[] AssignedVars[] 4974#L777-23 [2708] L777-23-->L389-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_22|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 4612#L389-21 [2132] L389-21-->L390-7: Formula: (= v_~t5_pc~0_21 1) InVars {~t5_pc~0=v_~t5_pc~0_21} OutVars{~t5_pc~0=v_~t5_pc~0_21} AuxVars[] AssignedVars[] 4613#L390-7 [2330] L390-7-->L400-7: Formula: (and (= 1 v_~E_5~0_27) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46 1)) InVars {~E_5~0=v_~E_5~0_27} OutVars{~E_5~0=v_~E_5~0_27, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 4588#L400-7 [3837] L400-7-->L785-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 4628#L785-21 [3654] L785-21-->L785-23: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_41 0) (= v_~t5_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} OutVars{~t5_st~0=v_~t5_st~0_19, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} AuxVars[] AssignedVars[~t5_st~0] 4636#L785-23 [2161] L785-23-->L669-3: Formula: (and (= v_~M_E~0_12 1) (= v_~M_E~0_11 2)) InVars {~M_E~0=v_~M_E~0_12} OutVars{~M_E~0=v_~M_E~0_11} AuxVars[] AssignedVars[~M_E~0] 4638#L669-3 [2824] L669-3-->L674-3: Formula: (and (= v_~T1_E~0_11 2) (= v_~T1_E~0_12 1)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 4857#L674-3 [2477] L674-3-->L679-3: Formula: (and (= 1 v_~T2_E~0_12) (= v_~T2_E~0_11 2)) InVars {~T2_E~0=v_~T2_E~0_12} OutVars{~T2_E~0=v_~T2_E~0_11} AuxVars[] AssignedVars[~T2_E~0] 4858#L679-3 [3664] L679-3-->L684-3: Formula: (< 1 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 4789#L684-3 [3666] L684-3-->L689-3: Formula: (> v_~T4_E~0_13 1) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 4790#L689-3 [3668] L689-3-->L694-3: Formula: (< 1 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 4812#L694-3 [2405] L694-3-->L699-3: Formula: (and (= 1 v_~E_M~0_30) (= v_~E_M~0_29 2)) InVars {~E_M~0=v_~E_M~0_30} OutVars{~E_M~0=v_~E_M~0_29} AuxVars[] AssignedVars[~E_M~0] 4713#L699-3 [2245] L699-3-->L704-3: Formula: (and (= v_~E_1~0_29 2) (= 1 v_~E_1~0_30)) InVars {~E_1~0=v_~E_1~0_30} OutVars{~E_1~0=v_~E_1~0_29} AuxVars[] AssignedVars[~E_1~0] 4714#L704-3 [2661] L704-3-->L709-3: Formula: (and (= v_~E_2~0_29 2) (= 1 v_~E_2~0_30)) InVars {~E_2~0=v_~E_2~0_30} OutVars{~E_2~0=v_~E_2~0_29} AuxVars[] AssignedVars[~E_2~0] 4592#L709-3 [2114] L709-3-->L714-3: Formula: (and (= v_~E_3~0_29 2) (= 1 v_~E_3~0_30)) InVars {~E_3~0=v_~E_3~0_30} OutVars{~E_3~0=v_~E_3~0_29} AuxVars[] AssignedVars[~E_3~0] 4593#L714-3 [2573] L714-3-->L719-3: Formula: (and (= v_~E_4~0_29 2) (= 1 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 4678#L719-3 [3680] L719-3-->L724-3: Formula: (> 1 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 4679#L724-3 [2818] L724-3-->L454-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_23} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 4851#L454-1 [2466] L454-1-->L486-1: Formula: (and (= 0 v_~m_st~0_20) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26 1)) InVars {~m_st~0=v_~m_st~0_20} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 4665#L486-1 [3838] L486-1-->L949: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret15, ULTIMATE.start_start_simulation_~tmp~3] 4796#L949 [3688] L949-->L949-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_1) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} AuxVars[] AssignedVars[] 4859#L949-1 [2479] L949-1-->L454-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_1} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 4838#L454-2 [2438] L454-2-->L486-2: Formula: (and (= v_~m_st~0_2 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4 1)) InVars {~m_st~0=v_~m_st~0_2} OutVars{~m_st~0=v_~m_st~0_2, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 4670#L486-2 [3840] L486-2-->L904: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 4767#L904 [2393] L904-->L911: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 4803#L911 [3851] L911-->L930-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_6|, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 4675#L930-1 312.69/160.48 [2019-03-28 12:21:54,184 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.48 [2019-03-28 12:21:54,184 INFO L82 PathProgramCache]: Analyzing trace with hash -715161505, now seen corresponding path program 1 times 312.69/160.48 [2019-03-28 12:21:54,184 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.48 [2019-03-28 12:21:54,184 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.48 [2019-03-28 12:21:54,185 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:54,186 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:54,186 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:54,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.48 [2019-03-28 12:21:54,208 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.48 [2019-03-28 12:21:54,209 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.48 [2019-03-28 12:21:54,209 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 312.69/160.48 [2019-03-28 12:21:54,209 INFO L799 eck$LassoCheckResult]: stem already infeasible 312.69/160.48 [2019-03-28 12:21:54,209 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.48 [2019-03-28 12:21:54,210 INFO L82 PathProgramCache]: Analyzing trace with hash -1415295597, now seen corresponding path program 3 times 312.69/160.48 [2019-03-28 12:21:54,210 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.48 [2019-03-28 12:21:54,210 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.48 [2019-03-28 12:21:54,211 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:54,211 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:54,211 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:54,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.48 [2019-03-28 12:21:54,242 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.48 [2019-03-28 12:21:54,243 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.48 [2019-03-28 12:21:54,243 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 312.69/160.48 [2019-03-28 12:21:54,243 INFO L811 eck$LassoCheckResult]: loop already infeasible 312.69/160.48 [2019-03-28 12:21:54,244 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 312.69/160.48 [2019-03-28 12:21:54,244 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 312.69/160.48 [2019-03-28 12:21:54,244 INFO L87 Difference]: Start difference. First operand 454 states and 1000 transitions. cyclomatic complexity: 547 Second operand 3 states. 312.69/160.48 [2019-03-28 12:21:54,802 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.48 [2019-03-28 12:21:54,802 INFO L93 Difference]: Finished difference Result 454 states and 999 transitions. 312.69/160.48 [2019-03-28 12:21:54,802 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 312.69/160.48 [2019-03-28 12:21:54,802 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 454 states and 999 transitions. 312.69/160.48 [2019-03-28 12:21:54,806 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 387 312.69/160.48 [2019-03-28 12:21:54,809 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 454 states to 454 states and 999 transitions. 312.69/160.48 [2019-03-28 12:21:54,809 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 454 312.69/160.48 [2019-03-28 12:21:54,809 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 454 312.69/160.48 [2019-03-28 12:21:54,809 INFO L73 IsDeterministic]: Start isDeterministic. Operand 454 states and 999 transitions. 312.69/160.48 [2019-03-28 12:21:54,810 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.48 [2019-03-28 12:21:54,811 INFO L706 BuchiCegarLoop]: Abstraction has 454 states and 999 transitions. 312.69/160.48 [2019-03-28 12:21:54,811 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 454 states and 999 transitions. 312.69/160.48 [2019-03-28 12:21:54,818 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 454 to 454. 312.69/160.48 [2019-03-28 12:21:54,818 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 454 states. 312.69/160.48 [2019-03-28 12:21:54,819 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 454 states to 454 states and 999 transitions. 312.69/160.48 [2019-03-28 12:21:54,819 INFO L729 BuchiCegarLoop]: Abstraction has 454 states and 999 transitions. 312.69/160.48 [2019-03-28 12:21:54,820 INFO L609 BuchiCegarLoop]: Abstraction has 454 states and 999 transitions. 312.69/160.48 [2019-03-28 12:21:54,820 INFO L442 BuchiCegarLoop]: ======== Iteration 7============ 312.69/160.48 [2019-03-28 12:21:54,820 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 454 states and 999 transitions. 312.69/160.48 [2019-03-28 12:21:54,822 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 387 312.69/160.48 [2019-03-28 12:21:54,822 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.48 [2019-03-28 12:21:54,822 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.48 [2019-03-28 12:21:54,823 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.48 [2019-03-28 12:21:54,823 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.48 [2019-03-28 12:21:54,824 INFO L794 eck$LassoCheckResult]: Stem: 5868#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 5684#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 5685#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 5754#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 5755#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 5688#L431-1 [3229] L431-1-->L436-1: Formula: (and (< v_~t4_i~0_4 1) (= v_~t4_st~0_5 2)) InVars {~t4_i~0=v_~t4_i~0_4} OutVars{~t4_i~0=v_~t4_i~0_4, ~t4_st~0=v_~t4_st~0_5} AuxVars[] AssignedVars[~t4_st~0] 5689#L436-1 [3231] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_5 2) (> v_~t5_i~0_4 1)) InVars {~t5_i~0=v_~t5_i~0_4} OutVars{~t5_i~0=v_~t5_i~0_4, ~t5_st~0=v_~t5_st~0_5} AuxVars[] AssignedVars[~t5_st~0] 5726#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 5727#L601-1 [2765] L601-1-->L606-1: Formula: (and (= v_~T1_E~0_2 1) (= 0 v_~T1_E~0_3)) InVars {~T1_E~0=v_~T1_E~0_3} OutVars{~T1_E~0=v_~T1_E~0_2} AuxVars[] AssignedVars[~T1_E~0] 5729#L606-1 [2407] L606-1-->L611-1: Formula: (and (= 0 v_~T2_E~0_3) (= v_~T2_E~0_2 1)) InVars {~T2_E~0=v_~T2_E~0_3} OutVars{~T2_E~0=v_~T2_E~0_2} AuxVars[] AssignedVars[~T2_E~0] 5632#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 5633#L616-1 [3241] L616-1-->L621-1: Formula: (< v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 5511#L621-1 [3243] L621-1-->L626-1: Formula: (< v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 5512#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 5596#L631-1 [3247] L631-1-->L636-1: Formula: (< v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 5597#L636-1 [2819] L636-1-->L641-1: Formula: (and (= v_~E_2~0_3 0) (= v_~E_2~0_2 1)) InVars {~E_2~0=v_~E_2~0_3} OutVars{~E_2~0=v_~E_2~0_2} AuxVars[] AssignedVars[~E_2~0] 5771#L641-1 [2474] L641-1-->L646-1: Formula: (and (= v_~E_3~0_3 0) (= v_~E_3~0_2 1)) InVars {~E_3~0=v_~E_3~0_3} OutVars{~E_3~0=v_~E_3~0_2} AuxVars[] AssignedVars[~E_3~0] 5772#L646-1 [2935] L646-1-->L651-1: Formula: (and (= v_~E_4~0_2 1) (= v_~E_4~0_3 0)) InVars {~E_4~0=v_~E_4~0_3} OutVars{~E_4~0=v_~E_4~0_2} AuxVars[] AssignedVars[~E_4~0] 5717#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 5718#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 5928#L294 [2854] L294-->L295: Formula: (= v_~m_pc~0_2 1) InVars {~m_pc~0=v_~m_pc~0_2} OutVars{~m_pc~0=v_~m_pc~0_2} AuxVars[] AssignedVars[] 5841#L295 [2595] L295-->L305: Formula: (and (= v_~E_M~0_5 1) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_4 1)) InVars {~E_M~0=v_~E_M~0_5} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_4, ~E_M~0=v_~E_M~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 5842#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 5947#L745 [3261] L745-->L745-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_5) (= v_~m_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} OutVars{~m_st~0=v_~m_st~0_6, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} AuxVars[] AssignedVars[~m_st~0] 5952#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 5667#L313 [2301] L313-->L314: Formula: (= v_~t1_pc~0_2 1) InVars {~t1_pc~0=v_~t1_pc~0_2} OutVars{~t1_pc~0=v_~t1_pc~0_2} AuxVars[] AssignedVars[] 5623#L314 [2241] L314-->L324: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_4 1) (= v_~E_1~0_5 1)) InVars {~E_1~0=v_~E_1~0_5} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_4, ~E_1~0=v_~E_1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 5625#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 5526#L753 [3267] L753-->L753-2: Formula: (and (> 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_5) (= v_~t1_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_5, ~t1_st~0=v_~t1_st~0_6} AuxVars[] AssignedVars[~t1_st~0] 5527#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 5530#L332 [3269] L332-->L332-2: Formula: (> v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 5694#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 5692#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 5693#L761 [3273] L761-->L761-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_5) (= v_~t2_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5, ~t2_st~0=v_~t2_st~0_6} AuxVars[] AssignedVars[~t2_st~0] 5713#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 5714#L351 [2567] L351-->L352: Formula: (= 1 v_~t3_pc~0_2) InVars {~t3_pc~0=v_~t3_pc~0_2} OutVars{~t3_pc~0=v_~t3_pc~0_2} AuxVars[] AssignedVars[] 5830#L352 [2655] L352-->L362: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_4 1) (= v_~E_3~0_5 1)) InVars {~E_3~0=v_~E_3~0_5} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_4, ~E_3~0=v_~E_3~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 5812#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 5829#L769 [3279] L769-->L769-2: Formula: (and (= v_~t3_st~0_6 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_5)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} OutVars{~t3_st~0=v_~t3_st~0_6, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} AuxVars[] AssignedVars[~t3_st~0] 5833#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 5834#L370 [3281] L370-->L370-2: Formula: (> v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 5917#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 5915#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 5916#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 5927#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 5587#L389 [2193] L389-->L390: Formula: (= 1 v_~t5_pc~0_2) InVars {~t5_pc~0=v_~t5_pc~0_2} OutVars{~t5_pc~0=v_~t5_pc~0_2} AuxVars[] AssignedVars[] 5588#L390 [2343] L390-->L400: Formula: (and (= v_~E_5~0_5 1) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4 1)) InVars {~E_5~0=v_~E_5~0_5} OutVars{~E_5~0=v_~E_5~0_5, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 5559#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 5586#L785 [3291] L785-->L785-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_5) (= v_~t5_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} OutVars{~t5_st~0=v_~t5_st~0_6, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} AuxVars[] AssignedVars[~t5_st~0] 5604#L785-2 [3293] L785-2-->L669-1: Formula: (> 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 5605#L669-1 [3295] L669-1-->L674-1: Formula: (> 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 5769#L674-1 [2472] L674-1-->L679-1: Formula: (and (= 1 v_~T2_E~0_6) (= v_~T2_E~0_5 2)) InVars {~T2_E~0=v_~T2_E~0_6} OutVars{~T2_E~0=v_~T2_E~0_5} AuxVars[] AssignedVars[~T2_E~0] 5770#L679-1 [3299] L679-1-->L684-1: Formula: (< v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 5715#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 5716#L689-1 [2782] L689-1-->L694-1: Formula: (and (= v_~T5_E~0_6 1) (= v_~T5_E~0_5 2)) InVars {~T5_E~0=v_~T5_E~0_6} OutVars{~T5_E~0=v_~T5_E~0_5} AuxVars[] AssignedVars[~T5_E~0] 5862#L694-1 [3305] L694-1-->L699-1: Formula: (< v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 5652#L699-1 [3307] L699-1-->L704-1: Formula: (< v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 5653#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 5499#L709-1 [3311] L709-1-->L714-1: Formula: (< v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 5500#L714-1 [2569] L714-1-->L719-1: Formula: (and (= v_~E_4~0_8 1) (= v_~E_4~0_7 2)) InVars {~E_4~0=v_~E_4~0_8} OutVars{~E_4~0=v_~E_4~0_7} AuxVars[] AssignedVars[~E_4~0] 5591#L719-1 [2198] L719-1-->L930-1: Formula: (and (= v_~E_5~0_8 1) (= v_~E_5~0_7 2)) InVars {~E_5~0=v_~E_5~0_8} OutVars{~E_5~0=v_~E_5~0_7} AuxVars[] AssignedVars[~E_5~0] 5592#L930-1 312.69/160.48 [2019-03-28 12:21:54,826 INFO L796 eck$LassoCheckResult]: Loop: 5592#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 5598#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 5599#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 5578#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 5643#L501 [3784] L501-->L601-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 5644#L601-2 [2768] L601-2-->L601-4: Formula: (and (= v_~M_E~0_8 1) (= 0 v_~M_E~0_9)) InVars {~M_E~0=v_~M_E~0_9} OutVars{~M_E~0=v_~M_E~0_8} AuxVars[] AssignedVars[~M_E~0] 5926#L601-4 [2773] L601-4-->L606-3: Formula: (and (= v_~T1_E~0_8 1) (= 0 v_~T1_E~0_9)) InVars {~T1_E~0=v_~T1_E~0_9} OutVars{~T1_E~0=v_~T1_E~0_8} AuxVars[] AssignedVars[~T1_E~0] 5732#L606-3 [2413] L606-3-->L611-3: Formula: (and (= v_~T2_E~0_8 1) (= 0 v_~T2_E~0_9)) InVars {~T2_E~0=v_~T2_E~0_9} OutVars{~T2_E~0=v_~T2_E~0_8} AuxVars[] AssignedVars[~T2_E~0] 5641#L611-3 [2256] L611-3-->L616-3: Formula: (and (= v_~T3_E~0_8 1) (= v_~T3_E~0_9 0)) InVars {~T3_E~0=v_~T3_E~0_9} OutVars{~T3_E~0=v_~T3_E~0_8} AuxVars[] AssignedVars[~T3_E~0] 5642#L616-3 [3338] L616-3-->L621-3: Formula: (< v_~T4_E~0_10 0) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 5516#L621-3 [3346] L621-3-->L626-3: Formula: (< 0 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 5517#L626-3 [2580] L626-3-->L631-3: Formula: (and (= v_~E_M~0_24 1) (= 0 v_~E_M~0_25)) InVars {~E_M~0=v_~E_M~0_25} OutVars{~E_M~0=v_~E_M~0_24} AuxVars[] AssignedVars[~E_M~0] 5572#L631-3 [2180] L631-3-->L636-3: Formula: (and (= v_~E_1~0_24 1) (= 0 v_~E_1~0_25)) InVars {~E_1~0=v_~E_1~0_25} OutVars{~E_1~0=v_~E_1~0_24} AuxVars[] AssignedVars[~E_1~0] 5573#L636-3 [3376] L636-3-->L641-3: Formula: (< 0 v_~E_2~0_26) InVars {~E_2~0=v_~E_2~0_26} OutVars{~E_2~0=v_~E_2~0_26} AuxVars[] AssignedVars[] 5763#L641-3 [2455] L641-3-->L646-3: Formula: (and (= 0 v_~E_3~0_25) (= v_~E_3~0_24 1)) InVars {~E_3~0=v_~E_3~0_25} OutVars{~E_3~0=v_~E_3~0_24} AuxVars[] AssignedVars[~E_3~0] 5764#L646-3 [2912] L646-3-->L651-3: Formula: (and (= 0 v_~E_4~0_25) (= v_~E_4~0_24 1)) InVars {~E_4~0=v_~E_4~0_25} OutVars{~E_4~0=v_~E_4~0_24} AuxVars[] AssignedVars[~E_4~0] 5708#L651-3 [3410] L651-3-->L656-3: Formula: (> 0 v_~E_5~0_26) InVars {~E_5~0=v_~E_5~0_26} OutVars{~E_5~0=v_~E_5~0_26} AuxVars[] AssignedVars[] 5709#L656-3 [2767] L656-3-->L294-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_37, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_37, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_22|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_22|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_22|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_37, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_37, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_22|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_22|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_22|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_22|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_37, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_37, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_37} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 5925#L294-21 [2808] L294-21-->L295-7: Formula: (= v_~m_pc~0_21 1) InVars {~m_pc~0=v_~m_pc~0_21} OutVars{~m_pc~0=v_~m_pc~0_21} AuxVars[] AssignedVars[] 5847#L295-7 [2602] L295-7-->L305-7: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_40 1) (= 1 v_~E_M~0_27)) InVars {~E_M~0=v_~E_M~0_27} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_40, ~E_M~0=v_~E_M~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 5848#L305-7 [3806] L305-7-->L745-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 5931#L745-21 [2835] L745-21-->L745-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_42) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} AuxVars[] AssignedVars[] 5932#L745-23 [2838] L745-23-->L313-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_43, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 5626#L313-21 [2243] L313-21-->L314-7: Formula: (= v_~t1_pc~0_21 1) InVars {~t1_pc~0=v_~t1_pc~0_21} OutVars{~t1_pc~0=v_~t1_pc~0_21} AuxVars[] AssignedVars[] 5627#L314-7 [2796] L314-7-->L324-7: Formula: (and (= 1 v_~E_1~0_27) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_46 1)) InVars {~E_1~0=v_~E_1~0_27} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_46, ~E_1~0=v_~E_1~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 5631#L324-7 [3813] L324-7-->L753-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 5663#L753-21 [2292] L753-21-->L753-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} AuxVars[] AssignedVars[] 5664#L753-23 [2297] L753-23-->L332-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_22|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 5666#L332-21 [2470] L332-21-->L333-7: Formula: (= 1 v_~t2_pc~0_21) InVars {~t2_pc~0=v_~t2_pc~0_21} OutVars{~t2_pc~0=v_~t2_pc~0_21} AuxVars[] AssignedVars[] 5746#L333-7 [2431] L333-7-->L343-7: Formula: (and (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_46 1) (= 1 v_~E_2~0_27)) InVars {~E_2~0=v_~E_2~0_27} OutVars{~E_2~0=v_~E_2~0_27, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_46} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 5748#L343-7 [3820] L343-7-->L761-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 5778#L761-21 [3538] L761-21-->L761-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___1~0_41 0) (= v_~t2_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41, ~t2_st~0=v_~t2_st~0_19} AuxVars[] AssignedVars[~t2_st~0] 5779#L761-23 [2493] L761-23-->L351-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_22|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 5780#L351-21 [2679] L351-21-->L352-7: Formula: (= v_~t3_pc~0_21 1) InVars {~t3_pc~0=v_~t3_pc~0_21} OutVars{~t3_pc~0=v_~t3_pc~0_21} AuxVars[] AssignedVars[] 5864#L352-7 [2622] L352-7-->L362-7: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_46 1) (= 1 v_~E_3~0_27)) InVars {~E_3~0=v_~E_3~0_27} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_46, ~E_3~0=v_~E_3~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 5795#L362-7 [3827] L362-7-->L769-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 5796#L769-21 [2534] L769-21-->L769-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} AuxVars[] AssignedVars[] 5802#L769-23 [2537] L769-23-->L370-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_43, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 5805#L370-21 [2927] L370-21-->L371-7: Formula: (= 1 v_~t4_pc~0_21) InVars {~t4_pc~0=v_~t4_pc~0_21} OutVars{~t4_pc~0=v_~t4_pc~0_21} AuxVars[] AssignedVars[] 5941#L371-7 [2863] L371-7-->L381-7: Formula: (and (= 1 v_~E_4~0_27) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_46 1)) InVars {~E_4~0=v_~E_4~0_27} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_46, ~E_4~0=v_~E_4~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 5907#L381-7 [3834] L381-7-->L777-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 5889#L777-21 [2705] L777-21-->L777-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} AuxVars[] AssignedVars[] 5890#L777-23 [2708] L777-23-->L389-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_22|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 5528#L389-21 [2132] L389-21-->L390-7: Formula: (= v_~t5_pc~0_21 1) InVars {~t5_pc~0=v_~t5_pc~0_21} OutVars{~t5_pc~0=v_~t5_pc~0_21} AuxVars[] AssignedVars[] 5529#L390-7 [2330] L390-7-->L400-7: Formula: (and (= 1 v_~E_5~0_27) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46 1)) InVars {~E_5~0=v_~E_5~0_27} OutVars{~E_5~0=v_~E_5~0_27, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 5504#L400-7 [3837] L400-7-->L785-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 5544#L785-21 [3654] L785-21-->L785-23: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_41 0) (= v_~t5_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} OutVars{~t5_st~0=v_~t5_st~0_19, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} AuxVars[] AssignedVars[~t5_st~0] 5552#L785-23 [2161] L785-23-->L669-3: Formula: (and (= v_~M_E~0_12 1) (= v_~M_E~0_11 2)) InVars {~M_E~0=v_~M_E~0_12} OutVars{~M_E~0=v_~M_E~0_11} AuxVars[] AssignedVars[~M_E~0] 5554#L669-3 [2824] L669-3-->L674-3: Formula: (and (= v_~T1_E~0_11 2) (= v_~T1_E~0_12 1)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 5773#L674-3 [2477] L674-3-->L679-3: Formula: (and (= 1 v_~T2_E~0_12) (= v_~T2_E~0_11 2)) InVars {~T2_E~0=v_~T2_E~0_12} OutVars{~T2_E~0=v_~T2_E~0_11} AuxVars[] AssignedVars[~T2_E~0] 5774#L679-3 [3664] L679-3-->L684-3: Formula: (< 1 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 5705#L684-3 [3666] L684-3-->L689-3: Formula: (> v_~T4_E~0_13 1) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 5706#L689-3 [3668] L689-3-->L694-3: Formula: (< 1 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 5728#L694-3 [2405] L694-3-->L699-3: Formula: (and (= 1 v_~E_M~0_30) (= v_~E_M~0_29 2)) InVars {~E_M~0=v_~E_M~0_30} OutVars{~E_M~0=v_~E_M~0_29} AuxVars[] AssignedVars[~E_M~0] 5629#L699-3 [2245] L699-3-->L704-3: Formula: (and (= v_~E_1~0_29 2) (= 1 v_~E_1~0_30)) InVars {~E_1~0=v_~E_1~0_30} OutVars{~E_1~0=v_~E_1~0_29} AuxVars[] AssignedVars[~E_1~0] 5630#L704-3 [2661] L704-3-->L709-3: Formula: (and (= v_~E_2~0_29 2) (= 1 v_~E_2~0_30)) InVars {~E_2~0=v_~E_2~0_30} OutVars{~E_2~0=v_~E_2~0_29} AuxVars[] AssignedVars[~E_2~0] 5508#L709-3 [2114] L709-3-->L714-3: Formula: (and (= v_~E_3~0_29 2) (= 1 v_~E_3~0_30)) InVars {~E_3~0=v_~E_3~0_30} OutVars{~E_3~0=v_~E_3~0_29} AuxVars[] AssignedVars[~E_3~0] 5509#L714-3 [2573] L714-3-->L719-3: Formula: (and (= v_~E_4~0_29 2) (= 1 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 5594#L719-3 [3680] L719-3-->L724-3: Formula: (> 1 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 5595#L724-3 [2818] L724-3-->L454-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_23} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 5767#L454-1 [2466] L454-1-->L486-1: Formula: (and (= 0 v_~m_st~0_20) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26 1)) InVars {~m_st~0=v_~m_st~0_20} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 5581#L486-1 [3838] L486-1-->L949: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret15, ULTIMATE.start_start_simulation_~tmp~3] 5712#L949 [3688] L949-->L949-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_1) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} AuxVars[] AssignedVars[] 5775#L949-1 [2479] L949-1-->L454-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_1} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 5752#L454-2 [2438] L454-2-->L486-2: Formula: (and (= v_~m_st~0_2 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4 1)) InVars {~m_st~0=v_~m_st~0_2} OutVars{~m_st~0=v_~m_st~0_2, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 5585#L486-2 [3840] L486-2-->L904: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 5683#L904 [2393] L904-->L911: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 5719#L911 [3851] L911-->L930-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_6|, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 5592#L930-1 312.69/160.48 [2019-03-28 12:21:54,826 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.48 [2019-03-28 12:21:54,826 INFO L82 PathProgramCache]: Analyzing trace with hash 71243262, now seen corresponding path program 1 times 312.69/160.48 [2019-03-28 12:21:54,826 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.48 [2019-03-28 12:21:54,826 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.48 [2019-03-28 12:21:54,827 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:54,827 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:54,828 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:54,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.48 [2019-03-28 12:21:54,847 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.48 [2019-03-28 12:21:54,847 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.48 [2019-03-28 12:21:54,847 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 312.69/160.48 [2019-03-28 12:21:54,848 INFO L799 eck$LassoCheckResult]: stem already infeasible 312.69/160.48 [2019-03-28 12:21:54,848 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.48 [2019-03-28 12:21:54,848 INFO L82 PathProgramCache]: Analyzing trace with hash -1415295597, now seen corresponding path program 4 times 312.69/160.48 [2019-03-28 12:21:54,848 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.48 [2019-03-28 12:21:54,849 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.48 [2019-03-28 12:21:54,849 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:54,849 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:54,850 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:54,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.48 [2019-03-28 12:21:54,876 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.48 [2019-03-28 12:21:54,876 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.48 [2019-03-28 12:21:54,876 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 312.69/160.48 [2019-03-28 12:21:54,876 INFO L811 eck$LassoCheckResult]: loop already infeasible 312.69/160.48 [2019-03-28 12:21:54,877 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 312.69/160.48 [2019-03-28 12:21:54,877 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 312.69/160.48 [2019-03-28 12:21:54,877 INFO L87 Difference]: Start difference. First operand 454 states and 999 transitions. cyclomatic complexity: 546 Second operand 3 states. 312.69/160.48 [2019-03-28 12:21:55,409 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.48 [2019-03-28 12:21:55,409 INFO L93 Difference]: Finished difference Result 454 states and 998 transitions. 312.69/160.48 [2019-03-28 12:21:55,410 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 312.69/160.48 [2019-03-28 12:21:55,410 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 454 states and 998 transitions. 312.69/160.48 [2019-03-28 12:21:55,413 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 387 312.69/160.48 [2019-03-28 12:21:55,416 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 454 states to 454 states and 998 transitions. 312.69/160.48 [2019-03-28 12:21:55,416 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 454 312.69/160.48 [2019-03-28 12:21:55,417 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 454 312.69/160.48 [2019-03-28 12:21:55,417 INFO L73 IsDeterministic]: Start isDeterministic. Operand 454 states and 998 transitions. 312.69/160.48 [2019-03-28 12:21:55,418 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.48 [2019-03-28 12:21:55,418 INFO L706 BuchiCegarLoop]: Abstraction has 454 states and 998 transitions. 312.69/160.48 [2019-03-28 12:21:55,419 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 454 states and 998 transitions. 312.69/160.48 [2019-03-28 12:21:55,425 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 454 to 454. 312.69/160.48 [2019-03-28 12:21:55,425 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 454 states. 312.69/160.48 [2019-03-28 12:21:55,426 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 454 states to 454 states and 998 transitions. 312.69/160.48 [2019-03-28 12:21:55,427 INFO L729 BuchiCegarLoop]: Abstraction has 454 states and 998 transitions. 312.69/160.48 [2019-03-28 12:21:55,427 INFO L609 BuchiCegarLoop]: Abstraction has 454 states and 998 transitions. 312.69/160.48 [2019-03-28 12:21:55,427 INFO L442 BuchiCegarLoop]: ======== Iteration 8============ 312.69/160.48 [2019-03-28 12:21:55,427 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 454 states and 998 transitions. 312.69/160.48 [2019-03-28 12:21:55,429 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 387 312.69/160.48 [2019-03-28 12:21:55,429 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.48 [2019-03-28 12:21:55,429 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.48 [2019-03-28 12:21:55,430 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.48 [2019-03-28 12:21:55,430 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.48 [2019-03-28 12:21:55,431 INFO L794 eck$LassoCheckResult]: Stem: 6784#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 6600#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 6601#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 6670#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 6671#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 6604#L431-1 [3228] L431-1-->L436-1: Formula: (and (= v_~t4_st~0_5 2) (> v_~t4_i~0_4 1)) InVars {~t4_i~0=v_~t4_i~0_4} OutVars{~t4_i~0=v_~t4_i~0_4, ~t4_st~0=v_~t4_st~0_5} AuxVars[] AssignedVars[~t4_st~0] 6605#L436-1 [3231] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_5 2) (> v_~t5_i~0_4 1)) InVars {~t5_i~0=v_~t5_i~0_4} OutVars{~t5_i~0=v_~t5_i~0_4, ~t5_st~0=v_~t5_st~0_5} AuxVars[] AssignedVars[~t5_st~0] 6642#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 6643#L601-1 [2765] L601-1-->L606-1: Formula: (and (= v_~T1_E~0_2 1) (= 0 v_~T1_E~0_3)) InVars {~T1_E~0=v_~T1_E~0_3} OutVars{~T1_E~0=v_~T1_E~0_2} AuxVars[] AssignedVars[~T1_E~0] 6645#L606-1 [2407] L606-1-->L611-1: Formula: (and (= 0 v_~T2_E~0_3) (= v_~T2_E~0_2 1)) InVars {~T2_E~0=v_~T2_E~0_3} OutVars{~T2_E~0=v_~T2_E~0_2} AuxVars[] AssignedVars[~T2_E~0] 6548#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 6549#L616-1 [3241] L616-1-->L621-1: Formula: (< v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 6426#L621-1 [3243] L621-1-->L626-1: Formula: (< v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 6427#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 6512#L631-1 [3247] L631-1-->L636-1: Formula: (< v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 6513#L636-1 [2819] L636-1-->L641-1: Formula: (and (= v_~E_2~0_3 0) (= v_~E_2~0_2 1)) InVars {~E_2~0=v_~E_2~0_3} OutVars{~E_2~0=v_~E_2~0_2} AuxVars[] AssignedVars[~E_2~0] 6687#L641-1 [2474] L641-1-->L646-1: Formula: (and (= v_~E_3~0_3 0) (= v_~E_3~0_2 1)) InVars {~E_3~0=v_~E_3~0_3} OutVars{~E_3~0=v_~E_3~0_2} AuxVars[] AssignedVars[~E_3~0] 6688#L646-1 [2935] L646-1-->L651-1: Formula: (and (= v_~E_4~0_2 1) (= v_~E_4~0_3 0)) InVars {~E_4~0=v_~E_4~0_3} OutVars{~E_4~0=v_~E_4~0_2} AuxVars[] AssignedVars[~E_4~0] 6633#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 6634#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 6844#L294 [2854] L294-->L295: Formula: (= v_~m_pc~0_2 1) InVars {~m_pc~0=v_~m_pc~0_2} OutVars{~m_pc~0=v_~m_pc~0_2} AuxVars[] AssignedVars[] 6757#L295 [2595] L295-->L305: Formula: (and (= v_~E_M~0_5 1) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_4 1)) InVars {~E_M~0=v_~E_M~0_5} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_4, ~E_M~0=v_~E_M~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 6758#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 6863#L745 [3261] L745-->L745-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_5) (= v_~m_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} OutVars{~m_st~0=v_~m_st~0_6, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} AuxVars[] AssignedVars[~m_st~0] 6868#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 6583#L313 [2301] L313-->L314: Formula: (= v_~t1_pc~0_2 1) InVars {~t1_pc~0=v_~t1_pc~0_2} OutVars{~t1_pc~0=v_~t1_pc~0_2} AuxVars[] AssignedVars[] 6539#L314 [2241] L314-->L324: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_4 1) (= v_~E_1~0_5 1)) InVars {~E_1~0=v_~E_1~0_5} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_4, ~E_1~0=v_~E_1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 6541#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 6442#L753 [3267] L753-->L753-2: Formula: (and (> 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_5) (= v_~t1_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_5, ~t1_st~0=v_~t1_st~0_6} AuxVars[] AssignedVars[~t1_st~0] 6443#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 6446#L332 [3269] L332-->L332-2: Formula: (> v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 6610#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 6608#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 6609#L761 [3273] L761-->L761-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_5) (= v_~t2_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5, ~t2_st~0=v_~t2_st~0_6} AuxVars[] AssignedVars[~t2_st~0] 6629#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 6630#L351 [2567] L351-->L352: Formula: (= 1 v_~t3_pc~0_2) InVars {~t3_pc~0=v_~t3_pc~0_2} OutVars{~t3_pc~0=v_~t3_pc~0_2} AuxVars[] AssignedVars[] 6746#L352 [2655] L352-->L362: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_4 1) (= v_~E_3~0_5 1)) InVars {~E_3~0=v_~E_3~0_5} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_4, ~E_3~0=v_~E_3~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 6728#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 6745#L769 [3279] L769-->L769-2: Formula: (and (= v_~t3_st~0_6 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_5)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} OutVars{~t3_st~0=v_~t3_st~0_6, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} AuxVars[] AssignedVars[~t3_st~0] 6749#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 6750#L370 [3281] L370-->L370-2: Formula: (> v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 6833#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 6830#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 6831#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 6843#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 6503#L389 [2193] L389-->L390: Formula: (= 1 v_~t5_pc~0_2) InVars {~t5_pc~0=v_~t5_pc~0_2} OutVars{~t5_pc~0=v_~t5_pc~0_2} AuxVars[] AssignedVars[] 6504#L390 [2343] L390-->L400: Formula: (and (= v_~E_5~0_5 1) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4 1)) InVars {~E_5~0=v_~E_5~0_5} OutVars{~E_5~0=v_~E_5~0_5, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 6475#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 6502#L785 [3291] L785-->L785-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_5) (= v_~t5_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} OutVars{~t5_st~0=v_~t5_st~0_6, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} AuxVars[] AssignedVars[~t5_st~0] 6520#L785-2 [3293] L785-2-->L669-1: Formula: (> 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 6521#L669-1 [3295] L669-1-->L674-1: Formula: (> 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 6685#L674-1 [2472] L674-1-->L679-1: Formula: (and (= 1 v_~T2_E~0_6) (= v_~T2_E~0_5 2)) InVars {~T2_E~0=v_~T2_E~0_6} OutVars{~T2_E~0=v_~T2_E~0_5} AuxVars[] AssignedVars[~T2_E~0] 6686#L679-1 [3299] L679-1-->L684-1: Formula: (< v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 6631#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 6632#L689-1 [2782] L689-1-->L694-1: Formula: (and (= v_~T5_E~0_6 1) (= v_~T5_E~0_5 2)) InVars {~T5_E~0=v_~T5_E~0_6} OutVars{~T5_E~0=v_~T5_E~0_5} AuxVars[] AssignedVars[~T5_E~0] 6778#L694-1 [3305] L694-1-->L699-1: Formula: (< v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 6568#L699-1 [3307] L699-1-->L704-1: Formula: (< v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 6569#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 6415#L709-1 [3311] L709-1-->L714-1: Formula: (< v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 6416#L714-1 [2569] L714-1-->L719-1: Formula: (and (= v_~E_4~0_8 1) (= v_~E_4~0_7 2)) InVars {~E_4~0=v_~E_4~0_8} OutVars{~E_4~0=v_~E_4~0_7} AuxVars[] AssignedVars[~E_4~0] 6507#L719-1 [2198] L719-1-->L930-1: Formula: (and (= v_~E_5~0_8 1) (= v_~E_5~0_7 2)) InVars {~E_5~0=v_~E_5~0_8} OutVars{~E_5~0=v_~E_5~0_7} AuxVars[] AssignedVars[~E_5~0] 6508#L930-1 312.69/160.48 [2019-03-28 12:21:55,433 INFO L796 eck$LassoCheckResult]: Loop: 6508#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 6514#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 6515#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 6494#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 6559#L501 [3784] L501-->L601-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 6560#L601-2 [2768] L601-2-->L601-4: Formula: (and (= v_~M_E~0_8 1) (= 0 v_~M_E~0_9)) InVars {~M_E~0=v_~M_E~0_9} OutVars{~M_E~0=v_~M_E~0_8} AuxVars[] AssignedVars[~M_E~0] 6842#L601-4 [2773] L601-4-->L606-3: Formula: (and (= v_~T1_E~0_8 1) (= 0 v_~T1_E~0_9)) InVars {~T1_E~0=v_~T1_E~0_9} OutVars{~T1_E~0=v_~T1_E~0_8} AuxVars[] AssignedVars[~T1_E~0] 6648#L606-3 [2413] L606-3-->L611-3: Formula: (and (= v_~T2_E~0_8 1) (= 0 v_~T2_E~0_9)) InVars {~T2_E~0=v_~T2_E~0_9} OutVars{~T2_E~0=v_~T2_E~0_8} AuxVars[] AssignedVars[~T2_E~0] 6557#L611-3 [2256] L611-3-->L616-3: Formula: (and (= v_~T3_E~0_8 1) (= v_~T3_E~0_9 0)) InVars {~T3_E~0=v_~T3_E~0_9} OutVars{~T3_E~0=v_~T3_E~0_8} AuxVars[] AssignedVars[~T3_E~0] 6558#L616-3 [3338] L616-3-->L621-3: Formula: (< v_~T4_E~0_10 0) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 6432#L621-3 [3346] L621-3-->L626-3: Formula: (< 0 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 6433#L626-3 [2580] L626-3-->L631-3: Formula: (and (= v_~E_M~0_24 1) (= 0 v_~E_M~0_25)) InVars {~E_M~0=v_~E_M~0_25} OutVars{~E_M~0=v_~E_M~0_24} AuxVars[] AssignedVars[~E_M~0] 6488#L631-3 [2180] L631-3-->L636-3: Formula: (and (= v_~E_1~0_24 1) (= 0 v_~E_1~0_25)) InVars {~E_1~0=v_~E_1~0_25} OutVars{~E_1~0=v_~E_1~0_24} AuxVars[] AssignedVars[~E_1~0] 6489#L636-3 [3376] L636-3-->L641-3: Formula: (< 0 v_~E_2~0_26) InVars {~E_2~0=v_~E_2~0_26} OutVars{~E_2~0=v_~E_2~0_26} AuxVars[] AssignedVars[] 6679#L641-3 [2455] L641-3-->L646-3: Formula: (and (= 0 v_~E_3~0_25) (= v_~E_3~0_24 1)) InVars {~E_3~0=v_~E_3~0_25} OutVars{~E_3~0=v_~E_3~0_24} AuxVars[] AssignedVars[~E_3~0] 6680#L646-3 [2912] L646-3-->L651-3: Formula: (and (= 0 v_~E_4~0_25) (= v_~E_4~0_24 1)) InVars {~E_4~0=v_~E_4~0_25} OutVars{~E_4~0=v_~E_4~0_24} AuxVars[] AssignedVars[~E_4~0] 6624#L651-3 [3410] L651-3-->L656-3: Formula: (> 0 v_~E_5~0_26) InVars {~E_5~0=v_~E_5~0_26} OutVars{~E_5~0=v_~E_5~0_26} AuxVars[] AssignedVars[] 6625#L656-3 [2767] L656-3-->L294-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_37, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_37, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_22|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_22|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_22|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_37, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_37, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_22|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_22|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_22|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_22|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_37, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_37, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_37} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 6841#L294-21 [2808] L294-21-->L295-7: Formula: (= v_~m_pc~0_21 1) InVars {~m_pc~0=v_~m_pc~0_21} OutVars{~m_pc~0=v_~m_pc~0_21} AuxVars[] AssignedVars[] 6763#L295-7 [2602] L295-7-->L305-7: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_40 1) (= 1 v_~E_M~0_27)) InVars {~E_M~0=v_~E_M~0_27} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_40, ~E_M~0=v_~E_M~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 6764#L305-7 [3806] L305-7-->L745-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 6847#L745-21 [2835] L745-21-->L745-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_42) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} AuxVars[] AssignedVars[] 6848#L745-23 [2838] L745-23-->L313-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_43, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 6542#L313-21 [3468] L313-21-->L313-23: Formula: (> v_~t1_pc~0_22 1) InVars {~t1_pc~0=v_~t1_pc~0_22} OutVars{~t1_pc~0=v_~t1_pc~0_22} AuxVars[] AssignedVars[] 6544#L313-23 [2249] L313-23-->L324-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 6547#L324-7 [3813] L324-7-->L753-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 6579#L753-21 [2292] L753-21-->L753-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} AuxVars[] AssignedVars[] 6580#L753-23 [2297] L753-23-->L332-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_22|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 6582#L332-21 [2470] L332-21-->L333-7: Formula: (= 1 v_~t2_pc~0_21) InVars {~t2_pc~0=v_~t2_pc~0_21} OutVars{~t2_pc~0=v_~t2_pc~0_21} AuxVars[] AssignedVars[] 6662#L333-7 [2431] L333-7-->L343-7: Formula: (and (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_46 1) (= 1 v_~E_2~0_27)) InVars {~E_2~0=v_~E_2~0_27} OutVars{~E_2~0=v_~E_2~0_27, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_46} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 6664#L343-7 [3820] L343-7-->L761-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 6694#L761-21 [3538] L761-21-->L761-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___1~0_41 0) (= v_~t2_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41, ~t2_st~0=v_~t2_st~0_19} AuxVars[] AssignedVars[~t2_st~0] 6695#L761-23 [2493] L761-23-->L351-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_22|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 6696#L351-21 [2679] L351-21-->L352-7: Formula: (= v_~t3_pc~0_21 1) InVars {~t3_pc~0=v_~t3_pc~0_21} OutVars{~t3_pc~0=v_~t3_pc~0_21} AuxVars[] AssignedVars[] 6780#L352-7 [2622] L352-7-->L362-7: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_46 1) (= 1 v_~E_3~0_27)) InVars {~E_3~0=v_~E_3~0_27} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_46, ~E_3~0=v_~E_3~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 6711#L362-7 [3827] L362-7-->L769-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 6712#L769-21 [2534] L769-21-->L769-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} AuxVars[] AssignedVars[] 6718#L769-23 [2537] L769-23-->L370-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_43, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 6721#L370-21 [2927] L370-21-->L371-7: Formula: (= 1 v_~t4_pc~0_21) InVars {~t4_pc~0=v_~t4_pc~0_21} OutVars{~t4_pc~0=v_~t4_pc~0_21} AuxVars[] AssignedVars[] 6856#L371-7 [2863] L371-7-->L381-7: Formula: (and (= 1 v_~E_4~0_27) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_46 1)) InVars {~E_4~0=v_~E_4~0_27} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_46, ~E_4~0=v_~E_4~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 6823#L381-7 [3834] L381-7-->L777-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 6805#L777-21 [2705] L777-21-->L777-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} AuxVars[] AssignedVars[] 6806#L777-23 [2708] L777-23-->L389-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_22|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 6444#L389-21 [3636] L389-21-->L389-23: Formula: (> v_~t5_pc~0_22 1) InVars {~t5_pc~0=v_~t5_pc~0_22} OutVars{~t5_pc~0=v_~t5_pc~0_22} AuxVars[] AssignedVars[] 6417#L389-23 [2111] L389-23-->L400-7: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 6418#L400-7 [3837] L400-7-->L785-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 6460#L785-21 [3654] L785-21-->L785-23: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_41 0) (= v_~t5_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} OutVars{~t5_st~0=v_~t5_st~0_19, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} AuxVars[] AssignedVars[~t5_st~0] 6468#L785-23 [2161] L785-23-->L669-3: Formula: (and (= v_~M_E~0_12 1) (= v_~M_E~0_11 2)) InVars {~M_E~0=v_~M_E~0_12} OutVars{~M_E~0=v_~M_E~0_11} AuxVars[] AssignedVars[~M_E~0] 6470#L669-3 [2824] L669-3-->L674-3: Formula: (and (= v_~T1_E~0_11 2) (= v_~T1_E~0_12 1)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 6689#L674-3 [2477] L674-3-->L679-3: Formula: (and (= 1 v_~T2_E~0_12) (= v_~T2_E~0_11 2)) InVars {~T2_E~0=v_~T2_E~0_12} OutVars{~T2_E~0=v_~T2_E~0_11} AuxVars[] AssignedVars[~T2_E~0] 6690#L679-3 [3664] L679-3-->L684-3: Formula: (< 1 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 6621#L684-3 [3666] L684-3-->L689-3: Formula: (> v_~T4_E~0_13 1) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 6622#L689-3 [3668] L689-3-->L694-3: Formula: (< 1 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 6644#L694-3 [2405] L694-3-->L699-3: Formula: (and (= 1 v_~E_M~0_30) (= v_~E_M~0_29 2)) InVars {~E_M~0=v_~E_M~0_30} OutVars{~E_M~0=v_~E_M~0_29} AuxVars[] AssignedVars[~E_M~0] 6545#L699-3 [2245] L699-3-->L704-3: Formula: (and (= v_~E_1~0_29 2) (= 1 v_~E_1~0_30)) InVars {~E_1~0=v_~E_1~0_30} OutVars{~E_1~0=v_~E_1~0_29} AuxVars[] AssignedVars[~E_1~0] 6546#L704-3 [2661] L704-3-->L709-3: Formula: (and (= v_~E_2~0_29 2) (= 1 v_~E_2~0_30)) InVars {~E_2~0=v_~E_2~0_30} OutVars{~E_2~0=v_~E_2~0_29} AuxVars[] AssignedVars[~E_2~0] 6424#L709-3 [2114] L709-3-->L714-3: Formula: (and (= v_~E_3~0_29 2) (= 1 v_~E_3~0_30)) InVars {~E_3~0=v_~E_3~0_30} OutVars{~E_3~0=v_~E_3~0_29} AuxVars[] AssignedVars[~E_3~0] 6425#L714-3 [2573] L714-3-->L719-3: Formula: (and (= v_~E_4~0_29 2) (= 1 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 6510#L719-3 [3680] L719-3-->L724-3: Formula: (> 1 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 6511#L724-3 [2818] L724-3-->L454-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_23} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 6683#L454-1 [2466] L454-1-->L486-1: Formula: (and (= 0 v_~m_st~0_20) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26 1)) InVars {~m_st~0=v_~m_st~0_20} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 6497#L486-1 [3838] L486-1-->L949: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret15, ULTIMATE.start_start_simulation_~tmp~3] 6628#L949 [3688] L949-->L949-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_1) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} AuxVars[] AssignedVars[] 6691#L949-1 [2479] L949-1-->L454-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_1} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 6668#L454-2 [2438] L454-2-->L486-2: Formula: (and (= v_~m_st~0_2 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4 1)) InVars {~m_st~0=v_~m_st~0_2} OutVars{~m_st~0=v_~m_st~0_2, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 6501#L486-2 [3840] L486-2-->L904: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 6599#L904 [2393] L904-->L911: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 6635#L911 [3851] L911-->L930-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_6|, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 6508#L930-1 312.69/160.48 [2019-03-28 12:21:55,433 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.48 [2019-03-28 12:21:55,433 INFO L82 PathProgramCache]: Analyzing trace with hash 50905887, now seen corresponding path program 1 times 312.69/160.48 [2019-03-28 12:21:55,433 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.48 [2019-03-28 12:21:55,433 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.48 [2019-03-28 12:21:55,434 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:55,434 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:55,435 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:55,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.48 [2019-03-28 12:21:55,453 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.48 [2019-03-28 12:21:55,453 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.48 [2019-03-28 12:21:55,453 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 312.69/160.48 [2019-03-28 12:21:55,454 INFO L799 eck$LassoCheckResult]: stem already infeasible 312.69/160.48 [2019-03-28 12:21:55,454 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.48 [2019-03-28 12:21:55,454 INFO L82 PathProgramCache]: Analyzing trace with hash 506531834, now seen corresponding path program 2 times 312.69/160.48 [2019-03-28 12:21:55,454 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.48 [2019-03-28 12:21:55,454 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.48 [2019-03-28 12:21:55,455 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:55,455 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:55,455 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:55,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.48 [2019-03-28 12:21:55,480 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.48 [2019-03-28 12:21:55,481 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.48 [2019-03-28 12:21:55,481 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 312.69/160.48 [2019-03-28 12:21:55,481 INFO L811 eck$LassoCheckResult]: loop already infeasible 312.69/160.48 [2019-03-28 12:21:55,481 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 312.69/160.48 [2019-03-28 12:21:55,481 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 312.69/160.48 [2019-03-28 12:21:55,482 INFO L87 Difference]: Start difference. First operand 454 states and 998 transitions. cyclomatic complexity: 545 Second operand 3 states. 312.69/160.48 [2019-03-28 12:21:55,994 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.48 [2019-03-28 12:21:55,995 INFO L93 Difference]: Finished difference Result 454 states and 997 transitions. 312.69/160.48 [2019-03-28 12:21:55,995 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 312.69/160.48 [2019-03-28 12:21:55,995 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 454 states and 997 transitions. 312.69/160.48 [2019-03-28 12:21:55,998 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 387 312.69/160.48 [2019-03-28 12:21:56,001 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 454 states to 454 states and 997 transitions. 312.69/160.48 [2019-03-28 12:21:56,001 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 454 312.69/160.48 [2019-03-28 12:21:56,002 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 454 312.69/160.48 [2019-03-28 12:21:56,002 INFO L73 IsDeterministic]: Start isDeterministic. Operand 454 states and 997 transitions. 312.69/160.48 [2019-03-28 12:21:56,003 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.48 [2019-03-28 12:21:56,003 INFO L706 BuchiCegarLoop]: Abstraction has 454 states and 997 transitions. 312.69/160.48 [2019-03-28 12:21:56,004 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 454 states and 997 transitions. 312.69/160.48 [2019-03-28 12:21:56,010 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 454 to 454. 312.69/160.48 [2019-03-28 12:21:56,011 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 454 states. 312.69/160.48 [2019-03-28 12:21:56,012 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 454 states to 454 states and 997 transitions. 312.69/160.48 [2019-03-28 12:21:56,012 INFO L729 BuchiCegarLoop]: Abstraction has 454 states and 997 transitions. 312.69/160.48 [2019-03-28 12:21:56,012 INFO L609 BuchiCegarLoop]: Abstraction has 454 states and 997 transitions. 312.69/160.48 [2019-03-28 12:21:56,012 INFO L442 BuchiCegarLoop]: ======== Iteration 9============ 312.69/160.48 [2019-03-28 12:21:56,012 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 454 states and 997 transitions. 312.69/160.48 [2019-03-28 12:21:56,014 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 387 312.69/160.48 [2019-03-28 12:21:56,015 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.48 [2019-03-28 12:21:56,015 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.48 [2019-03-28 12:21:56,016 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.48 [2019-03-28 12:21:56,016 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.48 [2019-03-28 12:21:56,017 INFO L794 eck$LassoCheckResult]: Stem: 7700#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 7516#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 7517#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 7586#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 7587#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 7518#L431-1 [2355] L431-1-->L436-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 7519#L436-1 [3231] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_5 2) (> v_~t5_i~0_4 1)) InVars {~t5_i~0=v_~t5_i~0_4} OutVars{~t5_i~0=v_~t5_i~0_4, ~t5_st~0=v_~t5_st~0_5} AuxVars[] AssignedVars[~t5_st~0] 7558#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 7559#L601-1 [2765] L601-1-->L606-1: Formula: (and (= v_~T1_E~0_2 1) (= 0 v_~T1_E~0_3)) InVars {~T1_E~0=v_~T1_E~0_3} OutVars{~T1_E~0=v_~T1_E~0_2} AuxVars[] AssignedVars[~T1_E~0] 7561#L606-1 [2407] L606-1-->L611-1: Formula: (and (= 0 v_~T2_E~0_3) (= v_~T2_E~0_2 1)) InVars {~T2_E~0=v_~T2_E~0_3} OutVars{~T2_E~0=v_~T2_E~0_2} AuxVars[] AssignedVars[~T2_E~0] 7463#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 7464#L616-1 [3241] L616-1-->L621-1: Formula: (< v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 7342#L621-1 [3243] L621-1-->L626-1: Formula: (< v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 7343#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 7428#L631-1 [3247] L631-1-->L636-1: Formula: (< v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 7429#L636-1 [2819] L636-1-->L641-1: Formula: (and (= v_~E_2~0_3 0) (= v_~E_2~0_2 1)) InVars {~E_2~0=v_~E_2~0_3} OutVars{~E_2~0=v_~E_2~0_2} AuxVars[] AssignedVars[~E_2~0] 7603#L641-1 [2474] L641-1-->L646-1: Formula: (and (= v_~E_3~0_3 0) (= v_~E_3~0_2 1)) InVars {~E_3~0=v_~E_3~0_3} OutVars{~E_3~0=v_~E_3~0_2} AuxVars[] AssignedVars[~E_3~0] 7604#L646-1 [2935] L646-1-->L651-1: Formula: (and (= v_~E_4~0_2 1) (= v_~E_4~0_3 0)) InVars {~E_4~0=v_~E_4~0_3} OutVars{~E_4~0=v_~E_4~0_2} AuxVars[] AssignedVars[~E_4~0] 7549#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 7550#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 7760#L294 [2854] L294-->L295: Formula: (= v_~m_pc~0_2 1) InVars {~m_pc~0=v_~m_pc~0_2} OutVars{~m_pc~0=v_~m_pc~0_2} AuxVars[] AssignedVars[] 7673#L295 [2595] L295-->L305: Formula: (and (= v_~E_M~0_5 1) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_4 1)) InVars {~E_M~0=v_~E_M~0_5} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_4, ~E_M~0=v_~E_M~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 7674#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 7779#L745 [3261] L745-->L745-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_5) (= v_~m_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} OutVars{~m_st~0=v_~m_st~0_6, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} AuxVars[] AssignedVars[~m_st~0] 7784#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 7499#L313 [2301] L313-->L314: Formula: (= v_~t1_pc~0_2 1) InVars {~t1_pc~0=v_~t1_pc~0_2} OutVars{~t1_pc~0=v_~t1_pc~0_2} AuxVars[] AssignedVars[] 7455#L314 [2241] L314-->L324: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_4 1) (= v_~E_1~0_5 1)) InVars {~E_1~0=v_~E_1~0_5} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_4, ~E_1~0=v_~E_1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 7457#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 7358#L753 [3267] L753-->L753-2: Formula: (and (> 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_5) (= v_~t1_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_5, ~t1_st~0=v_~t1_st~0_6} AuxVars[] AssignedVars[~t1_st~0] 7359#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 7362#L332 [3269] L332-->L332-2: Formula: (> v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 7526#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 7524#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 7525#L761 [3273] L761-->L761-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_5) (= v_~t2_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5, ~t2_st~0=v_~t2_st~0_6} AuxVars[] AssignedVars[~t2_st~0] 7545#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 7546#L351 [2567] L351-->L352: Formula: (= 1 v_~t3_pc~0_2) InVars {~t3_pc~0=v_~t3_pc~0_2} OutVars{~t3_pc~0=v_~t3_pc~0_2} AuxVars[] AssignedVars[] 7662#L352 [2655] L352-->L362: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_4 1) (= v_~E_3~0_5 1)) InVars {~E_3~0=v_~E_3~0_5} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_4, ~E_3~0=v_~E_3~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 7644#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 7661#L769 [3279] L769-->L769-2: Formula: (and (= v_~t3_st~0_6 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_5)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} OutVars{~t3_st~0=v_~t3_st~0_6, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} AuxVars[] AssignedVars[~t3_st~0] 7665#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 7666#L370 [3281] L370-->L370-2: Formula: (> v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 7749#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 7746#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 7747#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 7759#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 7419#L389 [2193] L389-->L390: Formula: (= 1 v_~t5_pc~0_2) InVars {~t5_pc~0=v_~t5_pc~0_2} OutVars{~t5_pc~0=v_~t5_pc~0_2} AuxVars[] AssignedVars[] 7420#L390 [2343] L390-->L400: Formula: (and (= v_~E_5~0_5 1) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4 1)) InVars {~E_5~0=v_~E_5~0_5} OutVars{~E_5~0=v_~E_5~0_5, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 7391#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 7418#L785 [3291] L785-->L785-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_5) (= v_~t5_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} OutVars{~t5_st~0=v_~t5_st~0_6, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} AuxVars[] AssignedVars[~t5_st~0] 7436#L785-2 [3293] L785-2-->L669-1: Formula: (> 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 7437#L669-1 [3295] L669-1-->L674-1: Formula: (> 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 7601#L674-1 [2472] L674-1-->L679-1: Formula: (and (= 1 v_~T2_E~0_6) (= v_~T2_E~0_5 2)) InVars {~T2_E~0=v_~T2_E~0_6} OutVars{~T2_E~0=v_~T2_E~0_5} AuxVars[] AssignedVars[~T2_E~0] 7602#L679-1 [3299] L679-1-->L684-1: Formula: (< v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 7547#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 7548#L689-1 [2782] L689-1-->L694-1: Formula: (and (= v_~T5_E~0_6 1) (= v_~T5_E~0_5 2)) InVars {~T5_E~0=v_~T5_E~0_6} OutVars{~T5_E~0=v_~T5_E~0_5} AuxVars[] AssignedVars[~T5_E~0] 7694#L694-1 [3305] L694-1-->L699-1: Formula: (< v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 7484#L699-1 [3307] L699-1-->L704-1: Formula: (< v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 7485#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 7331#L709-1 [3311] L709-1-->L714-1: Formula: (< v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 7332#L714-1 [2569] L714-1-->L719-1: Formula: (and (= v_~E_4~0_8 1) (= v_~E_4~0_7 2)) InVars {~E_4~0=v_~E_4~0_8} OutVars{~E_4~0=v_~E_4~0_7} AuxVars[] AssignedVars[~E_4~0] 7423#L719-1 [2198] L719-1-->L930-1: Formula: (and (= v_~E_5~0_8 1) (= v_~E_5~0_7 2)) InVars {~E_5~0=v_~E_5~0_8} OutVars{~E_5~0=v_~E_5~0_7} AuxVars[] AssignedVars[~E_5~0] 7424#L930-1 312.69/160.48 [2019-03-28 12:21:56,018 INFO L796 eck$LassoCheckResult]: Loop: 7424#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 7430#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 7431#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 7410#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 7475#L501 [3784] L501-->L601-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 7476#L601-2 [2768] L601-2-->L601-4: Formula: (and (= v_~M_E~0_8 1) (= 0 v_~M_E~0_9)) InVars {~M_E~0=v_~M_E~0_9} OutVars{~M_E~0=v_~M_E~0_8} AuxVars[] AssignedVars[~M_E~0] 7758#L601-4 [2773] L601-4-->L606-3: Formula: (and (= v_~T1_E~0_8 1) (= 0 v_~T1_E~0_9)) InVars {~T1_E~0=v_~T1_E~0_9} OutVars{~T1_E~0=v_~T1_E~0_8} AuxVars[] AssignedVars[~T1_E~0] 7564#L606-3 [2413] L606-3-->L611-3: Formula: (and (= v_~T2_E~0_8 1) (= 0 v_~T2_E~0_9)) InVars {~T2_E~0=v_~T2_E~0_9} OutVars{~T2_E~0=v_~T2_E~0_8} AuxVars[] AssignedVars[~T2_E~0] 7473#L611-3 [2256] L611-3-->L616-3: Formula: (and (= v_~T3_E~0_8 1) (= v_~T3_E~0_9 0)) InVars {~T3_E~0=v_~T3_E~0_9} OutVars{~T3_E~0=v_~T3_E~0_8} AuxVars[] AssignedVars[~T3_E~0] 7474#L616-3 [3338] L616-3-->L621-3: Formula: (< v_~T4_E~0_10 0) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 7348#L621-3 [3346] L621-3-->L626-3: Formula: (< 0 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 7349#L626-3 [2580] L626-3-->L631-3: Formula: (and (= v_~E_M~0_24 1) (= 0 v_~E_M~0_25)) InVars {~E_M~0=v_~E_M~0_25} OutVars{~E_M~0=v_~E_M~0_24} AuxVars[] AssignedVars[~E_M~0] 7404#L631-3 [2180] L631-3-->L636-3: Formula: (and (= v_~E_1~0_24 1) (= 0 v_~E_1~0_25)) InVars {~E_1~0=v_~E_1~0_25} OutVars{~E_1~0=v_~E_1~0_24} AuxVars[] AssignedVars[~E_1~0] 7405#L636-3 [3376] L636-3-->L641-3: Formula: (< 0 v_~E_2~0_26) InVars {~E_2~0=v_~E_2~0_26} OutVars{~E_2~0=v_~E_2~0_26} AuxVars[] AssignedVars[] 7595#L641-3 [2455] L641-3-->L646-3: Formula: (and (= 0 v_~E_3~0_25) (= v_~E_3~0_24 1)) InVars {~E_3~0=v_~E_3~0_25} OutVars{~E_3~0=v_~E_3~0_24} AuxVars[] AssignedVars[~E_3~0] 7596#L646-3 [2912] L646-3-->L651-3: Formula: (and (= 0 v_~E_4~0_25) (= v_~E_4~0_24 1)) InVars {~E_4~0=v_~E_4~0_25} OutVars{~E_4~0=v_~E_4~0_24} AuxVars[] AssignedVars[~E_4~0] 7540#L651-3 [3410] L651-3-->L656-3: Formula: (> 0 v_~E_5~0_26) InVars {~E_5~0=v_~E_5~0_26} OutVars{~E_5~0=v_~E_5~0_26} AuxVars[] AssignedVars[] 7541#L656-3 [2767] L656-3-->L294-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_37, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_37, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_22|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_22|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_22|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_37, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_37, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_22|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_22|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_22|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_22|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_37, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_37, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_37} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 7757#L294-21 [3426] L294-21-->L294-23: Formula: (< v_~m_pc~0_22 1) InVars {~m_pc~0=v_~m_pc~0_22} OutVars{~m_pc~0=v_~m_pc~0_22} AuxVars[] AssignedVars[] 7681#L294-23 [2803] L294-23-->L305-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_41 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_41} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 7680#L305-7 [3806] L305-7-->L745-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 7763#L745-21 [2835] L745-21-->L745-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_42) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} AuxVars[] AssignedVars[] 7764#L745-23 [2838] L745-23-->L313-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_43, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 7458#L313-21 [2243] L313-21-->L314-7: Formula: (= v_~t1_pc~0_21 1) InVars {~t1_pc~0=v_~t1_pc~0_21} OutVars{~t1_pc~0=v_~t1_pc~0_21} AuxVars[] AssignedVars[] 7459#L314-7 [2796] L314-7-->L324-7: Formula: (and (= 1 v_~E_1~0_27) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_46 1)) InVars {~E_1~0=v_~E_1~0_27} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_46, ~E_1~0=v_~E_1~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 7465#L324-7 [3813] L324-7-->L753-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 7495#L753-21 [2292] L753-21-->L753-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} AuxVars[] AssignedVars[] 7496#L753-23 [2297] L753-23-->L332-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_22|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 7498#L332-21 [2470] L332-21-->L333-7: Formula: (= 1 v_~t2_pc~0_21) InVars {~t2_pc~0=v_~t2_pc~0_21} OutVars{~t2_pc~0=v_~t2_pc~0_21} AuxVars[] AssignedVars[] 7578#L333-7 [2431] L333-7-->L343-7: Formula: (and (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_46 1) (= 1 v_~E_2~0_27)) InVars {~E_2~0=v_~E_2~0_27} OutVars{~E_2~0=v_~E_2~0_27, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_46} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 7580#L343-7 [3820] L343-7-->L761-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 7610#L761-21 [3538] L761-21-->L761-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___1~0_41 0) (= v_~t2_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41, ~t2_st~0=v_~t2_st~0_19} AuxVars[] AssignedVars[~t2_st~0] 7611#L761-23 [2493] L761-23-->L351-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_22|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 7612#L351-21 [2679] L351-21-->L352-7: Formula: (= v_~t3_pc~0_21 1) InVars {~t3_pc~0=v_~t3_pc~0_21} OutVars{~t3_pc~0=v_~t3_pc~0_21} AuxVars[] AssignedVars[] 7696#L352-7 [2622] L352-7-->L362-7: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_46 1) (= 1 v_~E_3~0_27)) InVars {~E_3~0=v_~E_3~0_27} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_46, ~E_3~0=v_~E_3~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 7627#L362-7 [3827] L362-7-->L769-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 7628#L769-21 [2534] L769-21-->L769-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} AuxVars[] AssignedVars[] 7634#L769-23 [2537] L769-23-->L370-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_43, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 7637#L370-21 [2927] L370-21-->L371-7: Formula: (= 1 v_~t4_pc~0_21) InVars {~t4_pc~0=v_~t4_pc~0_21} OutVars{~t4_pc~0=v_~t4_pc~0_21} AuxVars[] AssignedVars[] 7772#L371-7 [2863] L371-7-->L381-7: Formula: (and (= 1 v_~E_4~0_27) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_46 1)) InVars {~E_4~0=v_~E_4~0_27} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_46, ~E_4~0=v_~E_4~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 7739#L381-7 [3834] L381-7-->L777-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 7721#L777-21 [2705] L777-21-->L777-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} AuxVars[] AssignedVars[] 7722#L777-23 [2708] L777-23-->L389-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_22|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 7360#L389-21 [2132] L389-21-->L390-7: Formula: (= v_~t5_pc~0_21 1) InVars {~t5_pc~0=v_~t5_pc~0_21} OutVars{~t5_pc~0=v_~t5_pc~0_21} AuxVars[] AssignedVars[] 7361#L390-7 [2330] L390-7-->L400-7: Formula: (and (= 1 v_~E_5~0_27) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46 1)) InVars {~E_5~0=v_~E_5~0_27} OutVars{~E_5~0=v_~E_5~0_27, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 7334#L400-7 [3837] L400-7-->L785-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 7376#L785-21 [3654] L785-21-->L785-23: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_41 0) (= v_~t5_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} OutVars{~t5_st~0=v_~t5_st~0_19, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} AuxVars[] AssignedVars[~t5_st~0] 7384#L785-23 [2161] L785-23-->L669-3: Formula: (and (= v_~M_E~0_12 1) (= v_~M_E~0_11 2)) InVars {~M_E~0=v_~M_E~0_12} OutVars{~M_E~0=v_~M_E~0_11} AuxVars[] AssignedVars[~M_E~0] 7386#L669-3 [2824] L669-3-->L674-3: Formula: (and (= v_~T1_E~0_11 2) (= v_~T1_E~0_12 1)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 7605#L674-3 [2477] L674-3-->L679-3: Formula: (and (= 1 v_~T2_E~0_12) (= v_~T2_E~0_11 2)) InVars {~T2_E~0=v_~T2_E~0_12} OutVars{~T2_E~0=v_~T2_E~0_11} AuxVars[] AssignedVars[~T2_E~0] 7606#L679-3 [3664] L679-3-->L684-3: Formula: (< 1 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 7537#L684-3 [3666] L684-3-->L689-3: Formula: (> v_~T4_E~0_13 1) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 7538#L689-3 [3668] L689-3-->L694-3: Formula: (< 1 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 7560#L694-3 [2405] L694-3-->L699-3: Formula: (and (= 1 v_~E_M~0_30) (= v_~E_M~0_29 2)) InVars {~E_M~0=v_~E_M~0_30} OutVars{~E_M~0=v_~E_M~0_29} AuxVars[] AssignedVars[~E_M~0] 7461#L699-3 [2245] L699-3-->L704-3: Formula: (and (= v_~E_1~0_29 2) (= 1 v_~E_1~0_30)) InVars {~E_1~0=v_~E_1~0_30} OutVars{~E_1~0=v_~E_1~0_29} AuxVars[] AssignedVars[~E_1~0] 7462#L704-3 [2661] L704-3-->L709-3: Formula: (and (= v_~E_2~0_29 2) (= 1 v_~E_2~0_30)) InVars {~E_2~0=v_~E_2~0_30} OutVars{~E_2~0=v_~E_2~0_29} AuxVars[] AssignedVars[~E_2~0] 7340#L709-3 [2114] L709-3-->L714-3: Formula: (and (= v_~E_3~0_29 2) (= 1 v_~E_3~0_30)) InVars {~E_3~0=v_~E_3~0_30} OutVars{~E_3~0=v_~E_3~0_29} AuxVars[] AssignedVars[~E_3~0] 7341#L714-3 [2573] L714-3-->L719-3: Formula: (and (= v_~E_4~0_29 2) (= 1 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 7426#L719-3 [3680] L719-3-->L724-3: Formula: (> 1 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 7427#L724-3 [2818] L724-3-->L454-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_23} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 7599#L454-1 [2466] L454-1-->L486-1: Formula: (and (= 0 v_~m_st~0_20) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26 1)) InVars {~m_st~0=v_~m_st~0_20} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 7413#L486-1 [3838] L486-1-->L949: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret15, ULTIMATE.start_start_simulation_~tmp~3] 7544#L949 [3688] L949-->L949-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_1) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} AuxVars[] AssignedVars[] 7607#L949-1 [2479] L949-1-->L454-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_1} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 7584#L454-2 [2438] L454-2-->L486-2: Formula: (and (= v_~m_st~0_2 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4 1)) InVars {~m_st~0=v_~m_st~0_2} OutVars{~m_st~0=v_~m_st~0_2, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 7417#L486-2 [3840] L486-2-->L904: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 7515#L904 [2393] L904-->L911: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 7551#L911 [3851] L911-->L930-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_6|, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 7424#L930-1 312.69/160.48 [2019-03-28 12:21:56,019 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.48 [2019-03-28 12:21:56,019 INFO L82 PathProgramCache]: Analyzing trace with hash -523753304, now seen corresponding path program 1 times 312.69/160.48 [2019-03-28 12:21:56,019 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.48 [2019-03-28 12:21:56,019 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.48 [2019-03-28 12:21:56,020 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:56,020 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:56,020 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:56,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.48 [2019-03-28 12:21:56,052 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.48 [2019-03-28 12:21:56,053 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.48 [2019-03-28 12:21:56,053 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 312.69/160.48 [2019-03-28 12:21:56,053 INFO L799 eck$LassoCheckResult]: stem already infeasible 312.69/160.48 [2019-03-28 12:21:56,053 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.48 [2019-03-28 12:21:56,054 INFO L82 PathProgramCache]: Analyzing trace with hash -1304871118, now seen corresponding path program 2 times 312.69/160.48 [2019-03-28 12:21:56,054 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.48 [2019-03-28 12:21:56,054 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.48 [2019-03-28 12:21:56,055 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:56,055 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:56,055 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:56,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.48 [2019-03-28 12:21:56,086 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.48 [2019-03-28 12:21:56,086 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.48 [2019-03-28 12:21:56,086 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 312.69/160.48 [2019-03-28 12:21:56,087 INFO L811 eck$LassoCheckResult]: loop already infeasible 312.69/160.48 [2019-03-28 12:21:56,087 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 312.69/160.48 [2019-03-28 12:21:56,087 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 312.69/160.48 [2019-03-28 12:21:56,087 INFO L87 Difference]: Start difference. First operand 454 states and 997 transitions. cyclomatic complexity: 544 Second operand 3 states. 312.69/160.48 [2019-03-28 12:21:56,527 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.48 [2019-03-28 12:21:56,527 INFO L93 Difference]: Finished difference Result 454 states and 996 transitions. 312.69/160.48 [2019-03-28 12:21:56,528 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 312.69/160.48 [2019-03-28 12:21:56,528 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 454 states and 996 transitions. 312.69/160.48 [2019-03-28 12:21:56,531 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 387 312.69/160.48 [2019-03-28 12:21:56,534 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 454 states to 454 states and 996 transitions. 312.69/160.48 [2019-03-28 12:21:56,534 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 454 312.69/160.48 [2019-03-28 12:21:56,534 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 454 312.69/160.48 [2019-03-28 12:21:56,534 INFO L73 IsDeterministic]: Start isDeterministic. Operand 454 states and 996 transitions. 312.69/160.48 [2019-03-28 12:21:56,535 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.48 [2019-03-28 12:21:56,535 INFO L706 BuchiCegarLoop]: Abstraction has 454 states and 996 transitions. 312.69/160.48 [2019-03-28 12:21:56,536 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 454 states and 996 transitions. 312.69/160.48 [2019-03-28 12:21:56,542 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 454 to 454. 312.69/160.48 [2019-03-28 12:21:56,542 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 454 states. 312.69/160.48 [2019-03-28 12:21:56,544 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 454 states to 454 states and 996 transitions. 312.69/160.48 [2019-03-28 12:21:56,544 INFO L729 BuchiCegarLoop]: Abstraction has 454 states and 996 transitions. 312.69/160.48 [2019-03-28 12:21:56,544 INFO L609 BuchiCegarLoop]: Abstraction has 454 states and 996 transitions. 312.69/160.48 [2019-03-28 12:21:56,544 INFO L442 BuchiCegarLoop]: ======== Iteration 10============ 312.69/160.48 [2019-03-28 12:21:56,544 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 454 states and 996 transitions. 312.69/160.48 [2019-03-28 12:21:56,546 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 387 312.69/160.48 [2019-03-28 12:21:56,546 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.48 [2019-03-28 12:21:56,546 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.48 [2019-03-28 12:21:56,547 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.48 [2019-03-28 12:21:56,547 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.48 [2019-03-28 12:21:56,548 INFO L794 eck$LassoCheckResult]: Stem: 8616#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 8432#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 8433#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 8500#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 8501#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 8434#L431-1 [2355] L431-1-->L436-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 8435#L436-1 [2735] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 8474#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 8475#L601-1 [2765] L601-1-->L606-1: Formula: (and (= v_~T1_E~0_2 1) (= 0 v_~T1_E~0_3)) InVars {~T1_E~0=v_~T1_E~0_3} OutVars{~T1_E~0=v_~T1_E~0_2} AuxVars[] AssignedVars[~T1_E~0] 8477#L606-1 [2407] L606-1-->L611-1: Formula: (and (= 0 v_~T2_E~0_3) (= v_~T2_E~0_2 1)) InVars {~T2_E~0=v_~T2_E~0_3} OutVars{~T2_E~0=v_~T2_E~0_2} AuxVars[] AssignedVars[~T2_E~0] 8379#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 8380#L616-1 [3241] L616-1-->L621-1: Formula: (< v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 8258#L621-1 [3243] L621-1-->L626-1: Formula: (< v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 8259#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 8344#L631-1 [3247] L631-1-->L636-1: Formula: (< v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 8345#L636-1 [2819] L636-1-->L641-1: Formula: (and (= v_~E_2~0_3 0) (= v_~E_2~0_2 1)) InVars {~E_2~0=v_~E_2~0_3} OutVars{~E_2~0=v_~E_2~0_2} AuxVars[] AssignedVars[~E_2~0] 8519#L641-1 [2474] L641-1-->L646-1: Formula: (and (= v_~E_3~0_3 0) (= v_~E_3~0_2 1)) InVars {~E_3~0=v_~E_3~0_3} OutVars{~E_3~0=v_~E_3~0_2} AuxVars[] AssignedVars[~E_3~0] 8520#L646-1 [2935] L646-1-->L651-1: Formula: (and (= v_~E_4~0_2 1) (= v_~E_4~0_3 0)) InVars {~E_4~0=v_~E_4~0_3} OutVars{~E_4~0=v_~E_4~0_2} AuxVars[] AssignedVars[~E_4~0] 8465#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 8466#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 8676#L294 [2854] L294-->L295: Formula: (= v_~m_pc~0_2 1) InVars {~m_pc~0=v_~m_pc~0_2} OutVars{~m_pc~0=v_~m_pc~0_2} AuxVars[] AssignedVars[] 8589#L295 [2595] L295-->L305: Formula: (and (= v_~E_M~0_5 1) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_4 1)) InVars {~E_M~0=v_~E_M~0_5} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_4, ~E_M~0=v_~E_M~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 8590#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 8695#L745 [3261] L745-->L745-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_5) (= v_~m_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} OutVars{~m_st~0=v_~m_st~0_6, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} AuxVars[] AssignedVars[~m_st~0] 8700#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 8415#L313 [2301] L313-->L314: Formula: (= v_~t1_pc~0_2 1) InVars {~t1_pc~0=v_~t1_pc~0_2} OutVars{~t1_pc~0=v_~t1_pc~0_2} AuxVars[] AssignedVars[] 8371#L314 [2241] L314-->L324: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_4 1) (= v_~E_1~0_5 1)) InVars {~E_1~0=v_~E_1~0_5} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_4, ~E_1~0=v_~E_1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 8373#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 8273#L753 [3267] L753-->L753-2: Formula: (and (> 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_5) (= v_~t1_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_5, ~t1_st~0=v_~t1_st~0_6} AuxVars[] AssignedVars[~t1_st~0] 8274#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 8278#L332 [3269] L332-->L332-2: Formula: (> v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 8442#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 8440#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 8441#L761 [3273] L761-->L761-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_5) (= v_~t2_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5, ~t2_st~0=v_~t2_st~0_6} AuxVars[] AssignedVars[~t2_st~0] 8461#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 8462#L351 [2567] L351-->L352: Formula: (= 1 v_~t3_pc~0_2) InVars {~t3_pc~0=v_~t3_pc~0_2} OutVars{~t3_pc~0=v_~t3_pc~0_2} AuxVars[] AssignedVars[] 8578#L352 [2655] L352-->L362: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_4 1) (= v_~E_3~0_5 1)) InVars {~E_3~0=v_~E_3~0_5} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_4, ~E_3~0=v_~E_3~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 8560#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 8577#L769 [3279] L769-->L769-2: Formula: (and (= v_~t3_st~0_6 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_5)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} OutVars{~t3_st~0=v_~t3_st~0_6, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} AuxVars[] AssignedVars[~t3_st~0] 8581#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 8582#L370 [3281] L370-->L370-2: Formula: (> v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 8665#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 8661#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 8662#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 8675#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 8335#L389 [2193] L389-->L390: Formula: (= 1 v_~t5_pc~0_2) InVars {~t5_pc~0=v_~t5_pc~0_2} OutVars{~t5_pc~0=v_~t5_pc~0_2} AuxVars[] AssignedVars[] 8336#L390 [2343] L390-->L400: Formula: (and (= v_~E_5~0_5 1) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4 1)) InVars {~E_5~0=v_~E_5~0_5} OutVars{~E_5~0=v_~E_5~0_5, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 8305#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 8334#L785 [3291] L785-->L785-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_5) (= v_~t5_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} OutVars{~t5_st~0=v_~t5_st~0_6, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} AuxVars[] AssignedVars[~t5_st~0] 8352#L785-2 [3293] L785-2-->L669-1: Formula: (> 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 8353#L669-1 [3295] L669-1-->L674-1: Formula: (> 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 8517#L674-1 [2472] L674-1-->L679-1: Formula: (and (= 1 v_~T2_E~0_6) (= v_~T2_E~0_5 2)) InVars {~T2_E~0=v_~T2_E~0_6} OutVars{~T2_E~0=v_~T2_E~0_5} AuxVars[] AssignedVars[~T2_E~0] 8518#L679-1 [3299] L679-1-->L684-1: Formula: (< v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 8463#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 8464#L689-1 [2782] L689-1-->L694-1: Formula: (and (= v_~T5_E~0_6 1) (= v_~T5_E~0_5 2)) InVars {~T5_E~0=v_~T5_E~0_6} OutVars{~T5_E~0=v_~T5_E~0_5} AuxVars[] AssignedVars[~T5_E~0] 8610#L694-1 [3305] L694-1-->L699-1: Formula: (< v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 8400#L699-1 [3307] L699-1-->L704-1: Formula: (< v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 8401#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 8247#L709-1 [3311] L709-1-->L714-1: Formula: (< v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 8248#L714-1 [2569] L714-1-->L719-1: Formula: (and (= v_~E_4~0_8 1) (= v_~E_4~0_7 2)) InVars {~E_4~0=v_~E_4~0_8} OutVars{~E_4~0=v_~E_4~0_7} AuxVars[] AssignedVars[~E_4~0] 8338#L719-1 [2198] L719-1-->L930-1: Formula: (and (= v_~E_5~0_8 1) (= v_~E_5~0_7 2)) InVars {~E_5~0=v_~E_5~0_8} OutVars{~E_5~0=v_~E_5~0_7} AuxVars[] AssignedVars[~E_5~0] 8339#L930-1 312.69/160.48 [2019-03-28 12:21:56,550 INFO L796 eck$LassoCheckResult]: Loop: 8339#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 8346#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 8347#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 8326#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 8391#L501 [3784] L501-->L601-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 8392#L601-2 [2768] L601-2-->L601-4: Formula: (and (= v_~M_E~0_8 1) (= 0 v_~M_E~0_9)) InVars {~M_E~0=v_~M_E~0_9} OutVars{~M_E~0=v_~M_E~0_8} AuxVars[] AssignedVars[~M_E~0] 8674#L601-4 [2773] L601-4-->L606-3: Formula: (and (= v_~T1_E~0_8 1) (= 0 v_~T1_E~0_9)) InVars {~T1_E~0=v_~T1_E~0_9} OutVars{~T1_E~0=v_~T1_E~0_8} AuxVars[] AssignedVars[~T1_E~0] 8480#L606-3 [2413] L606-3-->L611-3: Formula: (and (= v_~T2_E~0_8 1) (= 0 v_~T2_E~0_9)) InVars {~T2_E~0=v_~T2_E~0_9} OutVars{~T2_E~0=v_~T2_E~0_8} AuxVars[] AssignedVars[~T2_E~0] 8389#L611-3 [2256] L611-3-->L616-3: Formula: (and (= v_~T3_E~0_8 1) (= v_~T3_E~0_9 0)) InVars {~T3_E~0=v_~T3_E~0_9} OutVars{~T3_E~0=v_~T3_E~0_8} AuxVars[] AssignedVars[~T3_E~0] 8390#L616-3 [3338] L616-3-->L621-3: Formula: (< v_~T4_E~0_10 0) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 8264#L621-3 [3346] L621-3-->L626-3: Formula: (< 0 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 8265#L626-3 [2580] L626-3-->L631-3: Formula: (and (= v_~E_M~0_24 1) (= 0 v_~E_M~0_25)) InVars {~E_M~0=v_~E_M~0_25} OutVars{~E_M~0=v_~E_M~0_24} AuxVars[] AssignedVars[~E_M~0] 8320#L631-3 [2180] L631-3-->L636-3: Formula: (and (= v_~E_1~0_24 1) (= 0 v_~E_1~0_25)) InVars {~E_1~0=v_~E_1~0_25} OutVars{~E_1~0=v_~E_1~0_24} AuxVars[] AssignedVars[~E_1~0] 8321#L636-3 [3376] L636-3-->L641-3: Formula: (< 0 v_~E_2~0_26) InVars {~E_2~0=v_~E_2~0_26} OutVars{~E_2~0=v_~E_2~0_26} AuxVars[] AssignedVars[] 8511#L641-3 [2455] L641-3-->L646-3: Formula: (and (= 0 v_~E_3~0_25) (= v_~E_3~0_24 1)) InVars {~E_3~0=v_~E_3~0_25} OutVars{~E_3~0=v_~E_3~0_24} AuxVars[] AssignedVars[~E_3~0] 8512#L646-3 [2912] L646-3-->L651-3: Formula: (and (= 0 v_~E_4~0_25) (= v_~E_4~0_24 1)) InVars {~E_4~0=v_~E_4~0_25} OutVars{~E_4~0=v_~E_4~0_24} AuxVars[] AssignedVars[~E_4~0] 8456#L651-3 [3410] L651-3-->L656-3: Formula: (> 0 v_~E_5~0_26) InVars {~E_5~0=v_~E_5~0_26} OutVars{~E_5~0=v_~E_5~0_26} AuxVars[] AssignedVars[] 8457#L656-3 [2767] L656-3-->L294-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_37, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_37, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_22|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_22|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_22|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_37, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_37, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_22|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_22|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_22|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_22|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_37, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_37, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_37} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 8673#L294-21 [2808] L294-21-->L295-7: Formula: (= v_~m_pc~0_21 1) InVars {~m_pc~0=v_~m_pc~0_21} OutVars{~m_pc~0=v_~m_pc~0_21} AuxVars[] AssignedVars[] 8595#L295-7 [2602] L295-7-->L305-7: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_40 1) (= 1 v_~E_M~0_27)) InVars {~E_M~0=v_~E_M~0_27} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_40, ~E_M~0=v_~E_M~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 8596#L305-7 [3806] L305-7-->L745-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 8679#L745-21 [2835] L745-21-->L745-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_42) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} AuxVars[] AssignedVars[] 8680#L745-23 [2838] L745-23-->L313-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_43, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 8374#L313-21 [2243] L313-21-->L314-7: Formula: (= v_~t1_pc~0_21 1) InVars {~t1_pc~0=v_~t1_pc~0_21} OutVars{~t1_pc~0=v_~t1_pc~0_21} AuxVars[] AssignedVars[] 8375#L314-7 [2796] L314-7-->L324-7: Formula: (and (= 1 v_~E_1~0_27) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_46 1)) InVars {~E_1~0=v_~E_1~0_27} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_46, ~E_1~0=v_~E_1~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 8381#L324-7 [3813] L324-7-->L753-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 8411#L753-21 [2292] L753-21-->L753-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} AuxVars[] AssignedVars[] 8412#L753-23 [2297] L753-23-->L332-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_22|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 8414#L332-21 [2470] L332-21-->L333-7: Formula: (= 1 v_~t2_pc~0_21) InVars {~t2_pc~0=v_~t2_pc~0_21} OutVars{~t2_pc~0=v_~t2_pc~0_21} AuxVars[] AssignedVars[] 8494#L333-7 [2431] L333-7-->L343-7: Formula: (and (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_46 1) (= 1 v_~E_2~0_27)) InVars {~E_2~0=v_~E_2~0_27} OutVars{~E_2~0=v_~E_2~0_27, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_46} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 8496#L343-7 [3820] L343-7-->L761-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 8526#L761-21 [3538] L761-21-->L761-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___1~0_41 0) (= v_~t2_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41, ~t2_st~0=v_~t2_st~0_19} AuxVars[] AssignedVars[~t2_st~0] 8527#L761-23 [2493] L761-23-->L351-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_22|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 8528#L351-21 [2679] L351-21-->L352-7: Formula: (= v_~t3_pc~0_21 1) InVars {~t3_pc~0=v_~t3_pc~0_21} OutVars{~t3_pc~0=v_~t3_pc~0_21} AuxVars[] AssignedVars[] 8612#L352-7 [2622] L352-7-->L362-7: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_46 1) (= 1 v_~E_3~0_27)) InVars {~E_3~0=v_~E_3~0_27} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_46, ~E_3~0=v_~E_3~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 8543#L362-7 [3827] L362-7-->L769-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 8544#L769-21 [2534] L769-21-->L769-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} AuxVars[] AssignedVars[] 8550#L769-23 [2537] L769-23-->L370-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_43, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 8553#L370-21 [2927] L370-21-->L371-7: Formula: (= 1 v_~t4_pc~0_21) InVars {~t4_pc~0=v_~t4_pc~0_21} OutVars{~t4_pc~0=v_~t4_pc~0_21} AuxVars[] AssignedVars[] 8689#L371-7 [2863] L371-7-->L381-7: Formula: (and (= 1 v_~E_4~0_27) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_46 1)) InVars {~E_4~0=v_~E_4~0_27} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_46, ~E_4~0=v_~E_4~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 8655#L381-7 [3834] L381-7-->L777-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 8637#L777-21 [2705] L777-21-->L777-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} AuxVars[] AssignedVars[] 8638#L777-23 [2708] L777-23-->L389-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_22|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 8276#L389-21 [2132] L389-21-->L390-7: Formula: (= v_~t5_pc~0_21 1) InVars {~t5_pc~0=v_~t5_pc~0_21} OutVars{~t5_pc~0=v_~t5_pc~0_21} AuxVars[] AssignedVars[] 8277#L390-7 [2330] L390-7-->L400-7: Formula: (and (= 1 v_~E_5~0_27) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46 1)) InVars {~E_5~0=v_~E_5~0_27} OutVars{~E_5~0=v_~E_5~0_27, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 8252#L400-7 [3837] L400-7-->L785-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 8292#L785-21 [3654] L785-21-->L785-23: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_41 0) (= v_~t5_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} OutVars{~t5_st~0=v_~t5_st~0_19, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} AuxVars[] AssignedVars[~t5_st~0] 8300#L785-23 [2161] L785-23-->L669-3: Formula: (and (= v_~M_E~0_12 1) (= v_~M_E~0_11 2)) InVars {~M_E~0=v_~M_E~0_12} OutVars{~M_E~0=v_~M_E~0_11} AuxVars[] AssignedVars[~M_E~0] 8302#L669-3 [2824] L669-3-->L674-3: Formula: (and (= v_~T1_E~0_11 2) (= v_~T1_E~0_12 1)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 8521#L674-3 [2477] L674-3-->L679-3: Formula: (and (= 1 v_~T2_E~0_12) (= v_~T2_E~0_11 2)) InVars {~T2_E~0=v_~T2_E~0_12} OutVars{~T2_E~0=v_~T2_E~0_11} AuxVars[] AssignedVars[~T2_E~0] 8522#L679-3 [3664] L679-3-->L684-3: Formula: (< 1 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 8453#L684-3 [3666] L684-3-->L689-3: Formula: (> v_~T4_E~0_13 1) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 8454#L689-3 [3668] L689-3-->L694-3: Formula: (< 1 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 8476#L694-3 [2405] L694-3-->L699-3: Formula: (and (= 1 v_~E_M~0_30) (= v_~E_M~0_29 2)) InVars {~E_M~0=v_~E_M~0_30} OutVars{~E_M~0=v_~E_M~0_29} AuxVars[] AssignedVars[~E_M~0] 8377#L699-3 [2245] L699-3-->L704-3: Formula: (and (= v_~E_1~0_29 2) (= 1 v_~E_1~0_30)) InVars {~E_1~0=v_~E_1~0_30} OutVars{~E_1~0=v_~E_1~0_29} AuxVars[] AssignedVars[~E_1~0] 8378#L704-3 [2661] L704-3-->L709-3: Formula: (and (= v_~E_2~0_29 2) (= 1 v_~E_2~0_30)) InVars {~E_2~0=v_~E_2~0_30} OutVars{~E_2~0=v_~E_2~0_29} AuxVars[] AssignedVars[~E_2~0] 8256#L709-3 [2114] L709-3-->L714-3: Formula: (and (= v_~E_3~0_29 2) (= 1 v_~E_3~0_30)) InVars {~E_3~0=v_~E_3~0_30} OutVars{~E_3~0=v_~E_3~0_29} AuxVars[] AssignedVars[~E_3~0] 8257#L714-3 [2573] L714-3-->L719-3: Formula: (and (= v_~E_4~0_29 2) (= 1 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 8342#L719-3 [3680] L719-3-->L724-3: Formula: (> 1 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 8343#L724-3 [2818] L724-3-->L454-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_23} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 8515#L454-1 [2466] L454-1-->L486-1: Formula: (and (= 0 v_~m_st~0_20) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26 1)) InVars {~m_st~0=v_~m_st~0_20} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 8329#L486-1 [3838] L486-1-->L949: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret15, ULTIMATE.start_start_simulation_~tmp~3] 8460#L949 [3688] L949-->L949-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_1) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} AuxVars[] AssignedVars[] 8523#L949-1 [2479] L949-1-->L454-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_1} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 8502#L454-2 [2438] L454-2-->L486-2: Formula: (and (= v_~m_st~0_2 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4 1)) InVars {~m_st~0=v_~m_st~0_2} OutVars{~m_st~0=v_~m_st~0_2, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 8333#L486-2 [3840] L486-2-->L904: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 8431#L904 [2393] L904-->L911: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 8467#L911 [3851] L911-->L930-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_6|, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 8339#L930-1 312.69/160.48 [2019-03-28 12:21:56,550 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.48 [2019-03-28 12:21:56,550 INFO L82 PathProgramCache]: Analyzing trace with hash -849151304, now seen corresponding path program 1 times 312.69/160.48 [2019-03-28 12:21:56,550 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.48 [2019-03-28 12:21:56,550 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.48 [2019-03-28 12:21:56,551 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:56,551 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:56,551 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:56,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.48 [2019-03-28 12:21:56,579 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.48 [2019-03-28 12:21:56,579 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.48 [2019-03-28 12:21:56,579 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 312.69/160.48 [2019-03-28 12:21:56,580 INFO L799 eck$LassoCheckResult]: stem already infeasible 312.69/160.48 [2019-03-28 12:21:56,580 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.48 [2019-03-28 12:21:56,580 INFO L82 PathProgramCache]: Analyzing trace with hash -1415295597, now seen corresponding path program 5 times 312.69/160.48 [2019-03-28 12:21:56,580 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.48 [2019-03-28 12:21:56,580 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.48 [2019-03-28 12:21:56,581 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:56,581 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:56,581 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.48 [2019-03-28 12:21:56,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.48 [2019-03-28 12:21:56,615 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.48 [2019-03-28 12:21:56,615 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.48 [2019-03-28 12:21:56,615 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 312.69/160.48 [2019-03-28 12:21:56,615 INFO L811 eck$LassoCheckResult]: loop already infeasible 312.69/160.48 [2019-03-28 12:21:56,616 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 312.69/160.48 [2019-03-28 12:21:56,616 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 312.69/160.48 [2019-03-28 12:21:56,616 INFO L87 Difference]: Start difference. First operand 454 states and 996 transitions. cyclomatic complexity: 543 Second operand 3 states. 312.69/160.48 [2019-03-28 12:21:57,117 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.48 [2019-03-28 12:21:57,117 INFO L93 Difference]: Finished difference Result 454 states and 986 transitions. 312.69/160.48 [2019-03-28 12:21:57,118 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 312.69/160.48 [2019-03-28 12:21:57,118 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 454 states and 986 transitions. 312.69/160.48 [2019-03-28 12:21:57,121 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 387 312.69/160.48 [2019-03-28 12:21:57,124 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 454 states to 454 states and 986 transitions. 312.69/160.48 [2019-03-28 12:21:57,124 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 454 312.69/160.48 [2019-03-28 12:21:57,124 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 454 312.69/160.48 [2019-03-28 12:21:57,124 INFO L73 IsDeterministic]: Start isDeterministic. Operand 454 states and 986 transitions. 312.69/160.48 [2019-03-28 12:21:57,125 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.48 [2019-03-28 12:21:57,125 INFO L706 BuchiCegarLoop]: Abstraction has 454 states and 986 transitions. 312.69/160.48 [2019-03-28 12:21:57,126 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 454 states and 986 transitions. 312.69/160.48 [2019-03-28 12:21:57,131 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 454 to 454. 312.69/160.49 [2019-03-28 12:21:57,131 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 454 states. 312.69/160.49 [2019-03-28 12:21:57,132 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 454 states to 454 states and 986 transitions. 312.69/160.49 [2019-03-28 12:21:57,132 INFO L729 BuchiCegarLoop]: Abstraction has 454 states and 986 transitions. 312.69/160.49 [2019-03-28 12:21:57,132 INFO L609 BuchiCegarLoop]: Abstraction has 454 states and 986 transitions. 312.69/160.49 [2019-03-28 12:21:57,132 INFO L442 BuchiCegarLoop]: ======== Iteration 11============ 312.69/160.49 [2019-03-28 12:21:57,133 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 454 states and 986 transitions. 312.69/160.49 [2019-03-28 12:21:57,135 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 387 312.69/160.49 [2019-03-28 12:21:57,135 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.49 [2019-03-28 12:21:57,135 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.49 [2019-03-28 12:21:57,136 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.49 [2019-03-28 12:21:57,136 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.49 [2019-03-28 12:21:57,137 INFO L794 eck$LassoCheckResult]: Stem: 9532#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 9348#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 9349#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 9416#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 9417#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 9350#L431-1 [2355] L431-1-->L436-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 9351#L436-1 [2735] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 9389#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 9390#L601-1 [3235] L601-1-->L606-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 9393#L606-1 [2407] L606-1-->L611-1: Formula: (and (= 0 v_~T2_E~0_3) (= v_~T2_E~0_2 1)) InVars {~T2_E~0=v_~T2_E~0_3} OutVars{~T2_E~0=v_~T2_E~0_2} AuxVars[] AssignedVars[~T2_E~0] 9295#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 9296#L616-1 [3241] L616-1-->L621-1: Formula: (< v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 9174#L621-1 [3243] L621-1-->L626-1: Formula: (< v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 9175#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 9260#L631-1 [3247] L631-1-->L636-1: Formula: (< v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 9261#L636-1 [2819] L636-1-->L641-1: Formula: (and (= v_~E_2~0_3 0) (= v_~E_2~0_2 1)) InVars {~E_2~0=v_~E_2~0_3} OutVars{~E_2~0=v_~E_2~0_2} AuxVars[] AssignedVars[~E_2~0] 9435#L641-1 [2474] L641-1-->L646-1: Formula: (and (= v_~E_3~0_3 0) (= v_~E_3~0_2 1)) InVars {~E_3~0=v_~E_3~0_3} OutVars{~E_3~0=v_~E_3~0_2} AuxVars[] AssignedVars[~E_3~0] 9436#L646-1 [2935] L646-1-->L651-1: Formula: (and (= v_~E_4~0_2 1) (= v_~E_4~0_3 0)) InVars {~E_4~0=v_~E_4~0_3} OutVars{~E_4~0=v_~E_4~0_2} AuxVars[] AssignedVars[~E_4~0] 9381#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 9382#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 9592#L294 [2854] L294-->L295: Formula: (= v_~m_pc~0_2 1) InVars {~m_pc~0=v_~m_pc~0_2} OutVars{~m_pc~0=v_~m_pc~0_2} AuxVars[] AssignedVars[] 9505#L295 [2595] L295-->L305: Formula: (and (= v_~E_M~0_5 1) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_4 1)) InVars {~E_M~0=v_~E_M~0_5} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_4, ~E_M~0=v_~E_M~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 9506#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 9611#L745 [3261] L745-->L745-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_5) (= v_~m_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} OutVars{~m_st~0=v_~m_st~0_6, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} AuxVars[] AssignedVars[~m_st~0] 9616#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 9331#L313 [2301] L313-->L314: Formula: (= v_~t1_pc~0_2 1) InVars {~t1_pc~0=v_~t1_pc~0_2} OutVars{~t1_pc~0=v_~t1_pc~0_2} AuxVars[] AssignedVars[] 9287#L314 [2241] L314-->L324: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_4 1) (= v_~E_1~0_5 1)) InVars {~E_1~0=v_~E_1~0_5} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_4, ~E_1~0=v_~E_1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 9289#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 9189#L753 [3267] L753-->L753-2: Formula: (and (> 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_5) (= v_~t1_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_5, ~t1_st~0=v_~t1_st~0_6} AuxVars[] AssignedVars[~t1_st~0] 9190#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 9194#L332 [3269] L332-->L332-2: Formula: (> v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 9358#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 9356#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 9357#L761 [3273] L761-->L761-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_5) (= v_~t2_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5, ~t2_st~0=v_~t2_st~0_6} AuxVars[] AssignedVars[~t2_st~0] 9377#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 9378#L351 [2567] L351-->L352: Formula: (= 1 v_~t3_pc~0_2) InVars {~t3_pc~0=v_~t3_pc~0_2} OutVars{~t3_pc~0=v_~t3_pc~0_2} AuxVars[] AssignedVars[] 9494#L352 [2655] L352-->L362: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_4 1) (= v_~E_3~0_5 1)) InVars {~E_3~0=v_~E_3~0_5} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_4, ~E_3~0=v_~E_3~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 9476#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 9493#L769 [3279] L769-->L769-2: Formula: (and (= v_~t3_st~0_6 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_5)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} OutVars{~t3_st~0=v_~t3_st~0_6, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} AuxVars[] AssignedVars[~t3_st~0] 9497#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 9498#L370 [3281] L370-->L370-2: Formula: (> v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 9581#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 9577#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 9578#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 9591#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 9251#L389 [2193] L389-->L390: Formula: (= 1 v_~t5_pc~0_2) InVars {~t5_pc~0=v_~t5_pc~0_2} OutVars{~t5_pc~0=v_~t5_pc~0_2} AuxVars[] AssignedVars[] 9252#L390 [2343] L390-->L400: Formula: (and (= v_~E_5~0_5 1) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4 1)) InVars {~E_5~0=v_~E_5~0_5} OutVars{~E_5~0=v_~E_5~0_5, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 9221#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 9247#L785 [3291] L785-->L785-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_5) (= v_~t5_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} OutVars{~t5_st~0=v_~t5_st~0_6, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} AuxVars[] AssignedVars[~t5_st~0] 9267#L785-2 [3293] L785-2-->L669-1: Formula: (> 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 9269#L669-1 [3294] L669-1-->L674-1: Formula: (< 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 9433#L674-1 [2472] L674-1-->L679-1: Formula: (and (= 1 v_~T2_E~0_6) (= v_~T2_E~0_5 2)) InVars {~T2_E~0=v_~T2_E~0_6} OutVars{~T2_E~0=v_~T2_E~0_5} AuxVars[] AssignedVars[~T2_E~0] 9434#L679-1 [3299] L679-1-->L684-1: Formula: (< v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 9379#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 9380#L689-1 [2782] L689-1-->L694-1: Formula: (and (= v_~T5_E~0_6 1) (= v_~T5_E~0_5 2)) InVars {~T5_E~0=v_~T5_E~0_6} OutVars{~T5_E~0=v_~T5_E~0_5} AuxVars[] AssignedVars[~T5_E~0] 9526#L694-1 [3305] L694-1-->L699-1: Formula: (< v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 9316#L699-1 [3307] L699-1-->L704-1: Formula: (< v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 9317#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 9163#L709-1 [3311] L709-1-->L714-1: Formula: (< v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 9164#L714-1 [2569] L714-1-->L719-1: Formula: (and (= v_~E_4~0_8 1) (= v_~E_4~0_7 2)) InVars {~E_4~0=v_~E_4~0_8} OutVars{~E_4~0=v_~E_4~0_7} AuxVars[] AssignedVars[~E_4~0] 9254#L719-1 [2198] L719-1-->L930-1: Formula: (and (= v_~E_5~0_8 1) (= v_~E_5~0_7 2)) InVars {~E_5~0=v_~E_5~0_8} OutVars{~E_5~0=v_~E_5~0_7} AuxVars[] AssignedVars[~E_5~0] 9255#L930-1 312.69/160.49 [2019-03-28 12:21:57,138 INFO L796 eck$LassoCheckResult]: Loop: 9255#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 9262#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 9263#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 9242#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 9307#L501 [3784] L501-->L601-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 9308#L601-2 [2768] L601-2-->L601-4: Formula: (and (= v_~M_E~0_8 1) (= 0 v_~M_E~0_9)) InVars {~M_E~0=v_~M_E~0_9} OutVars{~M_E~0=v_~M_E~0_8} AuxVars[] AssignedVars[~M_E~0] 9590#L601-4 [3322] L601-4-->L606-3: Formula: (> v_~T1_E~0_10 0) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 9396#L606-3 [2413] L606-3-->L611-3: Formula: (and (= v_~T2_E~0_8 1) (= 0 v_~T2_E~0_9)) InVars {~T2_E~0=v_~T2_E~0_9} OutVars{~T2_E~0=v_~T2_E~0_8} AuxVars[] AssignedVars[~T2_E~0] 9305#L611-3 [2256] L611-3-->L616-3: Formula: (and (= v_~T3_E~0_8 1) (= v_~T3_E~0_9 0)) InVars {~T3_E~0=v_~T3_E~0_9} OutVars{~T3_E~0=v_~T3_E~0_8} AuxVars[] AssignedVars[~T3_E~0] 9306#L616-3 [3338] L616-3-->L621-3: Formula: (< v_~T4_E~0_10 0) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 9180#L621-3 [3346] L621-3-->L626-3: Formula: (< 0 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 9181#L626-3 [2580] L626-3-->L631-3: Formula: (and (= v_~E_M~0_24 1) (= 0 v_~E_M~0_25)) InVars {~E_M~0=v_~E_M~0_25} OutVars{~E_M~0=v_~E_M~0_24} AuxVars[] AssignedVars[~E_M~0] 9236#L631-3 [2180] L631-3-->L636-3: Formula: (and (= v_~E_1~0_24 1) (= 0 v_~E_1~0_25)) InVars {~E_1~0=v_~E_1~0_25} OutVars{~E_1~0=v_~E_1~0_24} AuxVars[] AssignedVars[~E_1~0] 9237#L636-3 [3376] L636-3-->L641-3: Formula: (< 0 v_~E_2~0_26) InVars {~E_2~0=v_~E_2~0_26} OutVars{~E_2~0=v_~E_2~0_26} AuxVars[] AssignedVars[] 9427#L641-3 [2455] L641-3-->L646-3: Formula: (and (= 0 v_~E_3~0_25) (= v_~E_3~0_24 1)) InVars {~E_3~0=v_~E_3~0_25} OutVars{~E_3~0=v_~E_3~0_24} AuxVars[] AssignedVars[~E_3~0] 9428#L646-3 [2912] L646-3-->L651-3: Formula: (and (= 0 v_~E_4~0_25) (= v_~E_4~0_24 1)) InVars {~E_4~0=v_~E_4~0_25} OutVars{~E_4~0=v_~E_4~0_24} AuxVars[] AssignedVars[~E_4~0] 9372#L651-3 [3410] L651-3-->L656-3: Formula: (> 0 v_~E_5~0_26) InVars {~E_5~0=v_~E_5~0_26} OutVars{~E_5~0=v_~E_5~0_26} AuxVars[] AssignedVars[] 9373#L656-3 [2767] L656-3-->L294-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_37, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_37, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_22|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_22|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_22|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_37, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_37, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_22|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_22|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_22|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_22|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_37, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_37, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_37} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 9589#L294-21 [2808] L294-21-->L295-7: Formula: (= v_~m_pc~0_21 1) InVars {~m_pc~0=v_~m_pc~0_21} OutVars{~m_pc~0=v_~m_pc~0_21} AuxVars[] AssignedVars[] 9511#L295-7 [2602] L295-7-->L305-7: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_40 1) (= 1 v_~E_M~0_27)) InVars {~E_M~0=v_~E_M~0_27} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_40, ~E_M~0=v_~E_M~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 9512#L305-7 [3806] L305-7-->L745-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 9595#L745-21 [2835] L745-21-->L745-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_42) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} AuxVars[] AssignedVars[] 9596#L745-23 [2838] L745-23-->L313-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_43, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 9290#L313-21 [2243] L313-21-->L314-7: Formula: (= v_~t1_pc~0_21 1) InVars {~t1_pc~0=v_~t1_pc~0_21} OutVars{~t1_pc~0=v_~t1_pc~0_21} AuxVars[] AssignedVars[] 9291#L314-7 [2796] L314-7-->L324-7: Formula: (and (= 1 v_~E_1~0_27) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_46 1)) InVars {~E_1~0=v_~E_1~0_27} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_46, ~E_1~0=v_~E_1~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 9297#L324-7 [3813] L324-7-->L753-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 9327#L753-21 [2292] L753-21-->L753-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} AuxVars[] AssignedVars[] 9328#L753-23 [2297] L753-23-->L332-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_22|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 9330#L332-21 [2470] L332-21-->L333-7: Formula: (= 1 v_~t2_pc~0_21) InVars {~t2_pc~0=v_~t2_pc~0_21} OutVars{~t2_pc~0=v_~t2_pc~0_21} AuxVars[] AssignedVars[] 9410#L333-7 [2431] L333-7-->L343-7: Formula: (and (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_46 1) (= 1 v_~E_2~0_27)) InVars {~E_2~0=v_~E_2~0_27} OutVars{~E_2~0=v_~E_2~0_27, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_46} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 9412#L343-7 [3820] L343-7-->L761-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 9442#L761-21 [3538] L761-21-->L761-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___1~0_41 0) (= v_~t2_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41, ~t2_st~0=v_~t2_st~0_19} AuxVars[] AssignedVars[~t2_st~0] 9443#L761-23 [2493] L761-23-->L351-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_22|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 9444#L351-21 [2679] L351-21-->L352-7: Formula: (= v_~t3_pc~0_21 1) InVars {~t3_pc~0=v_~t3_pc~0_21} OutVars{~t3_pc~0=v_~t3_pc~0_21} AuxVars[] AssignedVars[] 9528#L352-7 [2622] L352-7-->L362-7: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_46 1) (= 1 v_~E_3~0_27)) InVars {~E_3~0=v_~E_3~0_27} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_46, ~E_3~0=v_~E_3~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 9459#L362-7 [3827] L362-7-->L769-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 9460#L769-21 [2534] L769-21-->L769-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} AuxVars[] AssignedVars[] 9466#L769-23 [2537] L769-23-->L370-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_43, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 9469#L370-21 [2927] L370-21-->L371-7: Formula: (= 1 v_~t4_pc~0_21) InVars {~t4_pc~0=v_~t4_pc~0_21} OutVars{~t4_pc~0=v_~t4_pc~0_21} AuxVars[] AssignedVars[] 9605#L371-7 [2863] L371-7-->L381-7: Formula: (and (= 1 v_~E_4~0_27) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_46 1)) InVars {~E_4~0=v_~E_4~0_27} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_46, ~E_4~0=v_~E_4~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 9571#L381-7 [3834] L381-7-->L777-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 9553#L777-21 [2705] L777-21-->L777-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} AuxVars[] AssignedVars[] 9554#L777-23 [2708] L777-23-->L389-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_22|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 9192#L389-21 [2132] L389-21-->L390-7: Formula: (= v_~t5_pc~0_21 1) InVars {~t5_pc~0=v_~t5_pc~0_21} OutVars{~t5_pc~0=v_~t5_pc~0_21} AuxVars[] AssignedVars[] 9193#L390-7 [2330] L390-7-->L400-7: Formula: (and (= 1 v_~E_5~0_27) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46 1)) InVars {~E_5~0=v_~E_5~0_27} OutVars{~E_5~0=v_~E_5~0_27, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 9168#L400-7 [3837] L400-7-->L785-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 9208#L785-21 [3654] L785-21-->L785-23: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_41 0) (= v_~t5_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} OutVars{~t5_st~0=v_~t5_st~0_19, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} AuxVars[] AssignedVars[~t5_st~0] 9216#L785-23 [2161] L785-23-->L669-3: Formula: (and (= v_~M_E~0_12 1) (= v_~M_E~0_11 2)) InVars {~M_E~0=v_~M_E~0_12} OutVars{~M_E~0=v_~M_E~0_11} AuxVars[] AssignedVars[~M_E~0] 9218#L669-3 [3660] L669-3-->L674-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 9437#L674-3 [2477] L674-3-->L679-3: Formula: (and (= 1 v_~T2_E~0_12) (= v_~T2_E~0_11 2)) InVars {~T2_E~0=v_~T2_E~0_12} OutVars{~T2_E~0=v_~T2_E~0_11} AuxVars[] AssignedVars[~T2_E~0] 9438#L679-3 [3664] L679-3-->L684-3: Formula: (< 1 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 9369#L684-3 [3666] L684-3-->L689-3: Formula: (> v_~T4_E~0_13 1) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 9370#L689-3 [3668] L689-3-->L694-3: Formula: (< 1 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 9392#L694-3 [2405] L694-3-->L699-3: Formula: (and (= 1 v_~E_M~0_30) (= v_~E_M~0_29 2)) InVars {~E_M~0=v_~E_M~0_30} OutVars{~E_M~0=v_~E_M~0_29} AuxVars[] AssignedVars[~E_M~0] 9293#L699-3 [2245] L699-3-->L704-3: Formula: (and (= v_~E_1~0_29 2) (= 1 v_~E_1~0_30)) InVars {~E_1~0=v_~E_1~0_30} OutVars{~E_1~0=v_~E_1~0_29} AuxVars[] AssignedVars[~E_1~0] 9294#L704-3 [2661] L704-3-->L709-3: Formula: (and (= v_~E_2~0_29 2) (= 1 v_~E_2~0_30)) InVars {~E_2~0=v_~E_2~0_30} OutVars{~E_2~0=v_~E_2~0_29} AuxVars[] AssignedVars[~E_2~0] 9172#L709-3 [2114] L709-3-->L714-3: Formula: (and (= v_~E_3~0_29 2) (= 1 v_~E_3~0_30)) InVars {~E_3~0=v_~E_3~0_30} OutVars{~E_3~0=v_~E_3~0_29} AuxVars[] AssignedVars[~E_3~0] 9173#L714-3 [2573] L714-3-->L719-3: Formula: (and (= v_~E_4~0_29 2) (= 1 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 9258#L719-3 [3680] L719-3-->L724-3: Formula: (> 1 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 9259#L724-3 [2818] L724-3-->L454-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_23} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 9431#L454-1 [2466] L454-1-->L486-1: Formula: (and (= 0 v_~m_st~0_20) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26 1)) InVars {~m_st~0=v_~m_st~0_20} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 9245#L486-1 [3838] L486-1-->L949: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret15, ULTIMATE.start_start_simulation_~tmp~3] 9376#L949 [3688] L949-->L949-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_1) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} AuxVars[] AssignedVars[] 9439#L949-1 [2479] L949-1-->L454-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_1} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 9418#L454-2 [2438] L454-2-->L486-2: Formula: (and (= v_~m_st~0_2 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4 1)) InVars {~m_st~0=v_~m_st~0_2} OutVars{~m_st~0=v_~m_st~0_2, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 9250#L486-2 [3840] L486-2-->L904: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 9347#L904 [2393] L904-->L911: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 9383#L911 [3851] L911-->L930-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_6|, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 9255#L930-1 312.69/160.49 [2019-03-28 12:21:57,138 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.49 [2019-03-28 12:21:57,139 INFO L82 PathProgramCache]: Analyzing trace with hash -2109723955, now seen corresponding path program 1 times 312.69/160.49 [2019-03-28 12:21:57,139 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.49 [2019-03-28 12:21:57,139 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.49 [2019-03-28 12:21:57,140 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:21:57,140 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:21:57,140 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:21:57,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.49 [2019-03-28 12:21:57,167 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.49 [2019-03-28 12:21:57,167 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.49 [2019-03-28 12:21:57,167 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 312.69/160.49 [2019-03-28 12:21:57,168 INFO L799 eck$LassoCheckResult]: stem already infeasible 312.69/160.49 [2019-03-28 12:21:57,168 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.49 [2019-03-28 12:21:57,168 INFO L82 PathProgramCache]: Analyzing trace with hash 34192330, now seen corresponding path program 1 times 312.69/160.49 [2019-03-28 12:21:57,168 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.49 [2019-03-28 12:21:57,168 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.49 [2019-03-28 12:21:57,169 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:21:57,169 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:21:57,169 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:21:57,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.49 [2019-03-28 12:21:57,207 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.49 [2019-03-28 12:21:57,207 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.49 [2019-03-28 12:21:57,207 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 312.69/160.49 [2019-03-28 12:21:57,208 INFO L811 eck$LassoCheckResult]: loop already infeasible 312.69/160.49 [2019-03-28 12:21:57,208 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 312.69/160.49 [2019-03-28 12:21:57,208 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 312.69/160.49 [2019-03-28 12:21:57,208 INFO L87 Difference]: Start difference. First operand 454 states and 986 transitions. cyclomatic complexity: 533 Second operand 3 states. 312.69/160.49 [2019-03-28 12:21:57,712 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.49 [2019-03-28 12:21:57,713 INFO L93 Difference]: Finished difference Result 454 states and 976 transitions. 312.69/160.49 [2019-03-28 12:21:57,713 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 312.69/160.49 [2019-03-28 12:21:57,713 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 454 states and 976 transitions. 312.69/160.49 [2019-03-28 12:21:57,716 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 387 312.69/160.49 [2019-03-28 12:21:57,719 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 454 states to 454 states and 976 transitions. 312.69/160.49 [2019-03-28 12:21:57,719 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 454 312.69/160.49 [2019-03-28 12:21:57,719 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 454 312.69/160.49 [2019-03-28 12:21:57,719 INFO L73 IsDeterministic]: Start isDeterministic. Operand 454 states and 976 transitions. 312.69/160.49 [2019-03-28 12:21:57,720 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.49 [2019-03-28 12:21:57,720 INFO L706 BuchiCegarLoop]: Abstraction has 454 states and 976 transitions. 312.69/160.49 [2019-03-28 12:21:57,721 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 454 states and 976 transitions. 312.69/160.49 [2019-03-28 12:21:57,726 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 454 to 454. 312.69/160.49 [2019-03-28 12:21:57,726 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 454 states. 312.69/160.49 [2019-03-28 12:21:57,727 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 454 states to 454 states and 976 transitions. 312.69/160.49 [2019-03-28 12:21:57,727 INFO L729 BuchiCegarLoop]: Abstraction has 454 states and 976 transitions. 312.69/160.49 [2019-03-28 12:21:57,727 INFO L609 BuchiCegarLoop]: Abstraction has 454 states and 976 transitions. 312.69/160.49 [2019-03-28 12:21:57,727 INFO L442 BuchiCegarLoop]: ======== Iteration 12============ 312.69/160.49 [2019-03-28 12:21:57,727 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 454 states and 976 transitions. 312.69/160.49 [2019-03-28 12:21:57,729 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 387 312.69/160.49 [2019-03-28 12:21:57,729 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.49 [2019-03-28 12:21:57,730 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.49 [2019-03-28 12:21:57,731 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.49 [2019-03-28 12:21:57,731 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.49 [2019-03-28 12:21:57,732 INFO L794 eck$LassoCheckResult]: Stem: 10448#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 10264#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 10265#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 10332#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 10333#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 10266#L431-1 [2355] L431-1-->L436-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 10267#L436-1 [2735] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 10305#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 10306#L601-1 [3235] L601-1-->L606-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 10309#L606-1 [3236] L606-1-->L611-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 10211#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 10212#L616-1 [3241] L616-1-->L621-1: Formula: (< v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 10090#L621-1 [3243] L621-1-->L626-1: Formula: (< v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 10091#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 10176#L631-1 [3247] L631-1-->L636-1: Formula: (< v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 10177#L636-1 [2819] L636-1-->L641-1: Formula: (and (= v_~E_2~0_3 0) (= v_~E_2~0_2 1)) InVars {~E_2~0=v_~E_2~0_3} OutVars{~E_2~0=v_~E_2~0_2} AuxVars[] AssignedVars[~E_2~0] 10351#L641-1 [2474] L641-1-->L646-1: Formula: (and (= v_~E_3~0_3 0) (= v_~E_3~0_2 1)) InVars {~E_3~0=v_~E_3~0_3} OutVars{~E_3~0=v_~E_3~0_2} AuxVars[] AssignedVars[~E_3~0] 10352#L646-1 [2935] L646-1-->L651-1: Formula: (and (= v_~E_4~0_2 1) (= v_~E_4~0_3 0)) InVars {~E_4~0=v_~E_4~0_3} OutVars{~E_4~0=v_~E_4~0_2} AuxVars[] AssignedVars[~E_4~0] 10297#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 10298#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 10508#L294 [2854] L294-->L295: Formula: (= v_~m_pc~0_2 1) InVars {~m_pc~0=v_~m_pc~0_2} OutVars{~m_pc~0=v_~m_pc~0_2} AuxVars[] AssignedVars[] 10421#L295 [2595] L295-->L305: Formula: (and (= v_~E_M~0_5 1) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_4 1)) InVars {~E_M~0=v_~E_M~0_5} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_4, ~E_M~0=v_~E_M~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 10422#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 10527#L745 [3261] L745-->L745-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_5) (= v_~m_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} OutVars{~m_st~0=v_~m_st~0_6, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} AuxVars[] AssignedVars[~m_st~0] 10532#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 10247#L313 [2301] L313-->L314: Formula: (= v_~t1_pc~0_2 1) InVars {~t1_pc~0=v_~t1_pc~0_2} OutVars{~t1_pc~0=v_~t1_pc~0_2} AuxVars[] AssignedVars[] 10203#L314 [2241] L314-->L324: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_4 1) (= v_~E_1~0_5 1)) InVars {~E_1~0=v_~E_1~0_5} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_4, ~E_1~0=v_~E_1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 10205#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 10105#L753 [3267] L753-->L753-2: Formula: (and (> 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_5) (= v_~t1_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_5, ~t1_st~0=v_~t1_st~0_6} AuxVars[] AssignedVars[~t1_st~0] 10106#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 10110#L332 [3269] L332-->L332-2: Formula: (> v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 10274#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 10272#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 10273#L761 [3273] L761-->L761-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_5) (= v_~t2_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5, ~t2_st~0=v_~t2_st~0_6} AuxVars[] AssignedVars[~t2_st~0] 10293#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 10294#L351 [2567] L351-->L352: Formula: (= 1 v_~t3_pc~0_2) InVars {~t3_pc~0=v_~t3_pc~0_2} OutVars{~t3_pc~0=v_~t3_pc~0_2} AuxVars[] AssignedVars[] 10410#L352 [2655] L352-->L362: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_4 1) (= v_~E_3~0_5 1)) InVars {~E_3~0=v_~E_3~0_5} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_4, ~E_3~0=v_~E_3~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 10392#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 10409#L769 [3279] L769-->L769-2: Formula: (and (= v_~t3_st~0_6 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_5)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} OutVars{~t3_st~0=v_~t3_st~0_6, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} AuxVars[] AssignedVars[~t3_st~0] 10413#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 10414#L370 [3281] L370-->L370-2: Formula: (> v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 10497#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 10493#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 10494#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 10507#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 10167#L389 [2193] L389-->L390: Formula: (= 1 v_~t5_pc~0_2) InVars {~t5_pc~0=v_~t5_pc~0_2} OutVars{~t5_pc~0=v_~t5_pc~0_2} AuxVars[] AssignedVars[] 10168#L390 [2343] L390-->L400: Formula: (and (= v_~E_5~0_5 1) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4 1)) InVars {~E_5~0=v_~E_5~0_5} OutVars{~E_5~0=v_~E_5~0_5, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 10137#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 10163#L785 [3291] L785-->L785-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_5) (= v_~t5_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} OutVars{~t5_st~0=v_~t5_st~0_6, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} AuxVars[] AssignedVars[~t5_st~0] 10183#L785-2 [3293] L785-2-->L669-1: Formula: (> 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 10185#L669-1 [3294] L669-1-->L674-1: Formula: (< 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 10349#L674-1 [3296] L674-1-->L679-1: Formula: (< 1 v_~T2_E~0_7) InVars {~T2_E~0=v_~T2_E~0_7} OutVars{~T2_E~0=v_~T2_E~0_7} AuxVars[] AssignedVars[] 10350#L679-1 [3299] L679-1-->L684-1: Formula: (< v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 10295#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 10296#L689-1 [2782] L689-1-->L694-1: Formula: (and (= v_~T5_E~0_6 1) (= v_~T5_E~0_5 2)) InVars {~T5_E~0=v_~T5_E~0_6} OutVars{~T5_E~0=v_~T5_E~0_5} AuxVars[] AssignedVars[~T5_E~0] 10442#L694-1 [3305] L694-1-->L699-1: Formula: (< v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 10232#L699-1 [3307] L699-1-->L704-1: Formula: (< v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 10233#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 10079#L709-1 [3311] L709-1-->L714-1: Formula: (< v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 10080#L714-1 [2569] L714-1-->L719-1: Formula: (and (= v_~E_4~0_8 1) (= v_~E_4~0_7 2)) InVars {~E_4~0=v_~E_4~0_8} OutVars{~E_4~0=v_~E_4~0_7} AuxVars[] AssignedVars[~E_4~0] 10170#L719-1 [2198] L719-1-->L930-1: Formula: (and (= v_~E_5~0_8 1) (= v_~E_5~0_7 2)) InVars {~E_5~0=v_~E_5~0_8} OutVars{~E_5~0=v_~E_5~0_7} AuxVars[] AssignedVars[~E_5~0] 10171#L930-1 312.69/160.49 [2019-03-28 12:21:57,733 INFO L796 eck$LassoCheckResult]: Loop: 10171#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 10178#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 10179#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 10158#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 10223#L501 [3784] L501-->L601-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 10224#L601-2 [2768] L601-2-->L601-4: Formula: (and (= v_~M_E~0_8 1) (= 0 v_~M_E~0_9)) InVars {~M_E~0=v_~M_E~0_9} OutVars{~M_E~0=v_~M_E~0_8} AuxVars[] AssignedVars[~M_E~0] 10506#L601-4 [3322] L601-4-->L606-3: Formula: (> v_~T1_E~0_10 0) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 10312#L606-3 [3326] L606-3-->L611-3: Formula: (< 0 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 10221#L611-3 [2256] L611-3-->L616-3: Formula: (and (= v_~T3_E~0_8 1) (= v_~T3_E~0_9 0)) InVars {~T3_E~0=v_~T3_E~0_9} OutVars{~T3_E~0=v_~T3_E~0_8} AuxVars[] AssignedVars[~T3_E~0] 10222#L616-3 [3338] L616-3-->L621-3: Formula: (< v_~T4_E~0_10 0) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 10096#L621-3 [3346] L621-3-->L626-3: Formula: (< 0 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 10097#L626-3 [2580] L626-3-->L631-3: Formula: (and (= v_~E_M~0_24 1) (= 0 v_~E_M~0_25)) InVars {~E_M~0=v_~E_M~0_25} OutVars{~E_M~0=v_~E_M~0_24} AuxVars[] AssignedVars[~E_M~0] 10152#L631-3 [2180] L631-3-->L636-3: Formula: (and (= v_~E_1~0_24 1) (= 0 v_~E_1~0_25)) InVars {~E_1~0=v_~E_1~0_25} OutVars{~E_1~0=v_~E_1~0_24} AuxVars[] AssignedVars[~E_1~0] 10153#L636-3 [3376] L636-3-->L641-3: Formula: (< 0 v_~E_2~0_26) InVars {~E_2~0=v_~E_2~0_26} OutVars{~E_2~0=v_~E_2~0_26} AuxVars[] AssignedVars[] 10343#L641-3 [2455] L641-3-->L646-3: Formula: (and (= 0 v_~E_3~0_25) (= v_~E_3~0_24 1)) InVars {~E_3~0=v_~E_3~0_25} OutVars{~E_3~0=v_~E_3~0_24} AuxVars[] AssignedVars[~E_3~0] 10344#L646-3 [2912] L646-3-->L651-3: Formula: (and (= 0 v_~E_4~0_25) (= v_~E_4~0_24 1)) InVars {~E_4~0=v_~E_4~0_25} OutVars{~E_4~0=v_~E_4~0_24} AuxVars[] AssignedVars[~E_4~0] 10288#L651-3 [3410] L651-3-->L656-3: Formula: (> 0 v_~E_5~0_26) InVars {~E_5~0=v_~E_5~0_26} OutVars{~E_5~0=v_~E_5~0_26} AuxVars[] AssignedVars[] 10289#L656-3 [2767] L656-3-->L294-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_37, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_37, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_22|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_22|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_22|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_37, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_37, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_22|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_22|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_22|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_22|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_37, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_37, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_37} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 10505#L294-21 [2808] L294-21-->L295-7: Formula: (= v_~m_pc~0_21 1) InVars {~m_pc~0=v_~m_pc~0_21} OutVars{~m_pc~0=v_~m_pc~0_21} AuxVars[] AssignedVars[] 10427#L295-7 [2602] L295-7-->L305-7: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_40 1) (= 1 v_~E_M~0_27)) InVars {~E_M~0=v_~E_M~0_27} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_40, ~E_M~0=v_~E_M~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 10428#L305-7 [3806] L305-7-->L745-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 10511#L745-21 [2835] L745-21-->L745-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_42) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} AuxVars[] AssignedVars[] 10512#L745-23 [2838] L745-23-->L313-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_43, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 10206#L313-21 [3468] L313-21-->L313-23: Formula: (> v_~t1_pc~0_22 1) InVars {~t1_pc~0=v_~t1_pc~0_22} OutVars{~t1_pc~0=v_~t1_pc~0_22} AuxVars[] AssignedVars[] 10208#L313-23 [2249] L313-23-->L324-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 10213#L324-7 [3813] L324-7-->L753-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 10243#L753-21 [2292] L753-21-->L753-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} AuxVars[] AssignedVars[] 10244#L753-23 [2297] L753-23-->L332-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_22|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 10246#L332-21 [2470] L332-21-->L333-7: Formula: (= 1 v_~t2_pc~0_21) InVars {~t2_pc~0=v_~t2_pc~0_21} OutVars{~t2_pc~0=v_~t2_pc~0_21} AuxVars[] AssignedVars[] 10326#L333-7 [2431] L333-7-->L343-7: Formula: (and (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_46 1) (= 1 v_~E_2~0_27)) InVars {~E_2~0=v_~E_2~0_27} OutVars{~E_2~0=v_~E_2~0_27, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_46} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 10328#L343-7 [3820] L343-7-->L761-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 10358#L761-21 [3538] L761-21-->L761-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___1~0_41 0) (= v_~t2_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41, ~t2_st~0=v_~t2_st~0_19} AuxVars[] AssignedVars[~t2_st~0] 10359#L761-23 [2493] L761-23-->L351-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_22|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 10360#L351-21 [2679] L351-21-->L352-7: Formula: (= v_~t3_pc~0_21 1) InVars {~t3_pc~0=v_~t3_pc~0_21} OutVars{~t3_pc~0=v_~t3_pc~0_21} AuxVars[] AssignedVars[] 10444#L352-7 [2622] L352-7-->L362-7: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_46 1) (= 1 v_~E_3~0_27)) InVars {~E_3~0=v_~E_3~0_27} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_46, ~E_3~0=v_~E_3~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 10375#L362-7 [3827] L362-7-->L769-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 10376#L769-21 [2534] L769-21-->L769-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} AuxVars[] AssignedVars[] 10382#L769-23 [2537] L769-23-->L370-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_43, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 10385#L370-21 [2927] L370-21-->L371-7: Formula: (= 1 v_~t4_pc~0_21) InVars {~t4_pc~0=v_~t4_pc~0_21} OutVars{~t4_pc~0=v_~t4_pc~0_21} AuxVars[] AssignedVars[] 10521#L371-7 [2863] L371-7-->L381-7: Formula: (and (= 1 v_~E_4~0_27) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_46 1)) InVars {~E_4~0=v_~E_4~0_27} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_46, ~E_4~0=v_~E_4~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 10487#L381-7 [3834] L381-7-->L777-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 10469#L777-21 [2705] L777-21-->L777-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} AuxVars[] AssignedVars[] 10470#L777-23 [2708] L777-23-->L389-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_22|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 10108#L389-21 [3636] L389-21-->L389-23: Formula: (> v_~t5_pc~0_22 1) InVars {~t5_pc~0=v_~t5_pc~0_22} OutVars{~t5_pc~0=v_~t5_pc~0_22} AuxVars[] AssignedVars[] 10083#L389-23 [2111] L389-23-->L400-7: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 10084#L400-7 [3837] L400-7-->L785-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 10124#L785-21 [3654] L785-21-->L785-23: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_41 0) (= v_~t5_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} OutVars{~t5_st~0=v_~t5_st~0_19, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} AuxVars[] AssignedVars[~t5_st~0] 10132#L785-23 [2161] L785-23-->L669-3: Formula: (and (= v_~M_E~0_12 1) (= v_~M_E~0_11 2)) InVars {~M_E~0=v_~M_E~0_12} OutVars{~M_E~0=v_~M_E~0_11} AuxVars[] AssignedVars[~M_E~0] 10134#L669-3 [3660] L669-3-->L674-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 10353#L674-3 [3662] L674-3-->L679-3: Formula: (< 1 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 10354#L679-3 [3664] L679-3-->L684-3: Formula: (< 1 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 10285#L684-3 [3666] L684-3-->L689-3: Formula: (> v_~T4_E~0_13 1) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 10286#L689-3 [3668] L689-3-->L694-3: Formula: (< 1 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 10308#L694-3 [2405] L694-3-->L699-3: Formula: (and (= 1 v_~E_M~0_30) (= v_~E_M~0_29 2)) InVars {~E_M~0=v_~E_M~0_30} OutVars{~E_M~0=v_~E_M~0_29} AuxVars[] AssignedVars[~E_M~0] 10209#L699-3 [2245] L699-3-->L704-3: Formula: (and (= v_~E_1~0_29 2) (= 1 v_~E_1~0_30)) InVars {~E_1~0=v_~E_1~0_30} OutVars{~E_1~0=v_~E_1~0_29} AuxVars[] AssignedVars[~E_1~0] 10210#L704-3 [2661] L704-3-->L709-3: Formula: (and (= v_~E_2~0_29 2) (= 1 v_~E_2~0_30)) InVars {~E_2~0=v_~E_2~0_30} OutVars{~E_2~0=v_~E_2~0_29} AuxVars[] AssignedVars[~E_2~0] 10088#L709-3 [2114] L709-3-->L714-3: Formula: (and (= v_~E_3~0_29 2) (= 1 v_~E_3~0_30)) InVars {~E_3~0=v_~E_3~0_30} OutVars{~E_3~0=v_~E_3~0_29} AuxVars[] AssignedVars[~E_3~0] 10089#L714-3 [2573] L714-3-->L719-3: Formula: (and (= v_~E_4~0_29 2) (= 1 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 10174#L719-3 [3680] L719-3-->L724-3: Formula: (> 1 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 10175#L724-3 [2818] L724-3-->L454-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_23} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 10347#L454-1 [2466] L454-1-->L486-1: Formula: (and (= 0 v_~m_st~0_20) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26 1)) InVars {~m_st~0=v_~m_st~0_20} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 10161#L486-1 [3838] L486-1-->L949: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret15, ULTIMATE.start_start_simulation_~tmp~3] 10292#L949 [3688] L949-->L949-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_1) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} AuxVars[] AssignedVars[] 10355#L949-1 [2479] L949-1-->L454-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_1} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 10334#L454-2 [2438] L454-2-->L486-2: Formula: (and (= v_~m_st~0_2 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4 1)) InVars {~m_st~0=v_~m_st~0_2} OutVars{~m_st~0=v_~m_st~0_2, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 10166#L486-2 [3840] L486-2-->L904: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 10263#L904 [2393] L904-->L911: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 10299#L911 [3851] L911-->L930-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_6|, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 10171#L930-1 312.69/160.49 [2019-03-28 12:21:57,733 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.49 [2019-03-28 12:21:57,733 INFO L82 PathProgramCache]: Analyzing trace with hash 1158687800, now seen corresponding path program 1 times 312.69/160.49 [2019-03-28 12:21:57,734 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.49 [2019-03-28 12:21:57,734 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.49 [2019-03-28 12:21:57,735 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:21:57,735 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:21:57,735 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:21:57,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.49 [2019-03-28 12:21:57,754 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.49 [2019-03-28 12:21:57,755 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.49 [2019-03-28 12:21:57,755 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 312.69/160.49 [2019-03-28 12:21:57,755 INFO L799 eck$LassoCheckResult]: stem already infeasible 312.69/160.49 [2019-03-28 12:21:57,755 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.49 [2019-03-28 12:21:57,755 INFO L82 PathProgramCache]: Analyzing trace with hash 1942382755, now seen corresponding path program 1 times 312.69/160.49 [2019-03-28 12:21:57,755 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.49 [2019-03-28 12:21:57,756 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.49 [2019-03-28 12:21:57,756 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:21:57,756 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:21:57,757 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:21:57,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.49 [2019-03-28 12:21:57,780 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.49 [2019-03-28 12:21:57,780 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.49 [2019-03-28 12:21:57,780 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 312.69/160.49 [2019-03-28 12:21:57,780 INFO L811 eck$LassoCheckResult]: loop already infeasible 312.69/160.49 [2019-03-28 12:21:57,781 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 312.69/160.49 [2019-03-28 12:21:57,781 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 312.69/160.49 [2019-03-28 12:21:57,781 INFO L87 Difference]: Start difference. First operand 454 states and 976 transitions. cyclomatic complexity: 523 Second operand 3 states. 312.69/160.49 [2019-03-28 12:21:58,281 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.49 [2019-03-28 12:21:58,282 INFO L93 Difference]: Finished difference Result 454 states and 966 transitions. 312.69/160.49 [2019-03-28 12:21:58,282 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 312.69/160.49 [2019-03-28 12:21:58,283 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 454 states and 966 transitions. 312.69/160.49 [2019-03-28 12:21:58,285 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 387 312.69/160.49 [2019-03-28 12:21:58,288 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 454 states to 454 states and 966 transitions. 312.69/160.49 [2019-03-28 12:21:58,289 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 454 312.69/160.49 [2019-03-28 12:21:58,289 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 454 312.69/160.49 [2019-03-28 12:21:58,289 INFO L73 IsDeterministic]: Start isDeterministic. Operand 454 states and 966 transitions. 312.69/160.49 [2019-03-28 12:21:58,290 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.49 [2019-03-28 12:21:58,290 INFO L706 BuchiCegarLoop]: Abstraction has 454 states and 966 transitions. 312.69/160.49 [2019-03-28 12:21:58,291 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 454 states and 966 transitions. 312.69/160.49 [2019-03-28 12:21:58,295 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 454 to 454. 312.69/160.49 [2019-03-28 12:21:58,296 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 454 states. 312.69/160.49 [2019-03-28 12:21:58,297 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 454 states to 454 states and 966 transitions. 312.69/160.49 [2019-03-28 12:21:58,297 INFO L729 BuchiCegarLoop]: Abstraction has 454 states and 966 transitions. 312.69/160.49 [2019-03-28 12:21:58,297 INFO L609 BuchiCegarLoop]: Abstraction has 454 states and 966 transitions. 312.69/160.49 [2019-03-28 12:21:58,297 INFO L442 BuchiCegarLoop]: ======== Iteration 13============ 312.69/160.49 [2019-03-28 12:21:58,297 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 454 states and 966 transitions. 312.69/160.49 [2019-03-28 12:21:58,299 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 387 312.69/160.49 [2019-03-28 12:21:58,299 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.49 [2019-03-28 12:21:58,300 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.49 [2019-03-28 12:21:58,301 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.49 [2019-03-28 12:21:58,301 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.49 [2019-03-28 12:21:58,302 INFO L794 eck$LassoCheckResult]: Stem: 11364#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 11180#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 11181#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 11248#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 11249#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 11182#L431-1 [2355] L431-1-->L436-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 11183#L436-1 [2735] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 11221#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 11222#L601-1 [3235] L601-1-->L606-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 11225#L606-1 [3236] L606-1-->L611-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 11127#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 11128#L616-1 [3240] L616-1-->L621-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 11006#L621-1 [3243] L621-1-->L626-1: Formula: (< v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 11007#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 11092#L631-1 [3247] L631-1-->L636-1: Formula: (< v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 11093#L636-1 [2819] L636-1-->L641-1: Formula: (and (= v_~E_2~0_3 0) (= v_~E_2~0_2 1)) InVars {~E_2~0=v_~E_2~0_3} OutVars{~E_2~0=v_~E_2~0_2} AuxVars[] AssignedVars[~E_2~0] 11267#L641-1 [2474] L641-1-->L646-1: Formula: (and (= v_~E_3~0_3 0) (= v_~E_3~0_2 1)) InVars {~E_3~0=v_~E_3~0_3} OutVars{~E_3~0=v_~E_3~0_2} AuxVars[] AssignedVars[~E_3~0] 11268#L646-1 [2935] L646-1-->L651-1: Formula: (and (= v_~E_4~0_2 1) (= v_~E_4~0_3 0)) InVars {~E_4~0=v_~E_4~0_3} OutVars{~E_4~0=v_~E_4~0_2} AuxVars[] AssignedVars[~E_4~0] 11213#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 11214#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 11424#L294 [2854] L294-->L295: Formula: (= v_~m_pc~0_2 1) InVars {~m_pc~0=v_~m_pc~0_2} OutVars{~m_pc~0=v_~m_pc~0_2} AuxVars[] AssignedVars[] 11337#L295 [2595] L295-->L305: Formula: (and (= v_~E_M~0_5 1) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_4 1)) InVars {~E_M~0=v_~E_M~0_5} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_4, ~E_M~0=v_~E_M~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 11338#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 11443#L745 [3261] L745-->L745-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_5) (= v_~m_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} OutVars{~m_st~0=v_~m_st~0_6, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} AuxVars[] AssignedVars[~m_st~0] 11448#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 11163#L313 [2301] L313-->L314: Formula: (= v_~t1_pc~0_2 1) InVars {~t1_pc~0=v_~t1_pc~0_2} OutVars{~t1_pc~0=v_~t1_pc~0_2} AuxVars[] AssignedVars[] 11119#L314 [2241] L314-->L324: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_4 1) (= v_~E_1~0_5 1)) InVars {~E_1~0=v_~E_1~0_5} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_4, ~E_1~0=v_~E_1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 11121#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 11021#L753 [3267] L753-->L753-2: Formula: (and (> 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_5) (= v_~t1_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_5, ~t1_st~0=v_~t1_st~0_6} AuxVars[] AssignedVars[~t1_st~0] 11022#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 11026#L332 [3269] L332-->L332-2: Formula: (> v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 11190#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 11188#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 11189#L761 [3273] L761-->L761-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_5) (= v_~t2_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5, ~t2_st~0=v_~t2_st~0_6} AuxVars[] AssignedVars[~t2_st~0] 11209#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 11210#L351 [2567] L351-->L352: Formula: (= 1 v_~t3_pc~0_2) InVars {~t3_pc~0=v_~t3_pc~0_2} OutVars{~t3_pc~0=v_~t3_pc~0_2} AuxVars[] AssignedVars[] 11326#L352 [2655] L352-->L362: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_4 1) (= v_~E_3~0_5 1)) InVars {~E_3~0=v_~E_3~0_5} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_4, ~E_3~0=v_~E_3~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 11308#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 11325#L769 [3279] L769-->L769-2: Formula: (and (= v_~t3_st~0_6 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_5)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} OutVars{~t3_st~0=v_~t3_st~0_6, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} AuxVars[] AssignedVars[~t3_st~0] 11329#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 11330#L370 [3281] L370-->L370-2: Formula: (> v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 11413#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 11409#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 11410#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 11423#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 11083#L389 [2193] L389-->L390: Formula: (= 1 v_~t5_pc~0_2) InVars {~t5_pc~0=v_~t5_pc~0_2} OutVars{~t5_pc~0=v_~t5_pc~0_2} AuxVars[] AssignedVars[] 11084#L390 [2343] L390-->L400: Formula: (and (= v_~E_5~0_5 1) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4 1)) InVars {~E_5~0=v_~E_5~0_5} OutVars{~E_5~0=v_~E_5~0_5, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 11053#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 11079#L785 [3291] L785-->L785-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_5) (= v_~t5_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} OutVars{~t5_st~0=v_~t5_st~0_6, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} AuxVars[] AssignedVars[~t5_st~0] 11099#L785-2 [3293] L785-2-->L669-1: Formula: (> 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 11101#L669-1 [3294] L669-1-->L674-1: Formula: (< 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 11265#L674-1 [3296] L674-1-->L679-1: Formula: (< 1 v_~T2_E~0_7) InVars {~T2_E~0=v_~T2_E~0_7} OutVars{~T2_E~0=v_~T2_E~0_7} AuxVars[] AssignedVars[] 11266#L679-1 [3299] L679-1-->L684-1: Formula: (< v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 11211#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 11212#L689-1 [2782] L689-1-->L694-1: Formula: (and (= v_~T5_E~0_6 1) (= v_~T5_E~0_5 2)) InVars {~T5_E~0=v_~T5_E~0_6} OutVars{~T5_E~0=v_~T5_E~0_5} AuxVars[] AssignedVars[~T5_E~0] 11358#L694-1 [3305] L694-1-->L699-1: Formula: (< v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 11148#L699-1 [3307] L699-1-->L704-1: Formula: (< v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 11149#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 10995#L709-1 [3311] L709-1-->L714-1: Formula: (< v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 10996#L714-1 [2569] L714-1-->L719-1: Formula: (and (= v_~E_4~0_8 1) (= v_~E_4~0_7 2)) InVars {~E_4~0=v_~E_4~0_8} OutVars{~E_4~0=v_~E_4~0_7} AuxVars[] AssignedVars[~E_4~0] 11086#L719-1 [2198] L719-1-->L930-1: Formula: (and (= v_~E_5~0_8 1) (= v_~E_5~0_7 2)) InVars {~E_5~0=v_~E_5~0_8} OutVars{~E_5~0=v_~E_5~0_7} AuxVars[] AssignedVars[~E_5~0] 11087#L930-1 312.69/160.49 [2019-03-28 12:21:58,303 INFO L796 eck$LassoCheckResult]: Loop: 11087#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 11094#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 11095#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 11074#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 11139#L501 [3784] L501-->L601-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 11140#L601-2 [2768] L601-2-->L601-4: Formula: (and (= v_~M_E~0_8 1) (= 0 v_~M_E~0_9)) InVars {~M_E~0=v_~M_E~0_9} OutVars{~M_E~0=v_~M_E~0_8} AuxVars[] AssignedVars[~M_E~0] 11422#L601-4 [3322] L601-4-->L606-3: Formula: (> v_~T1_E~0_10 0) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 11228#L606-3 [3326] L606-3-->L611-3: Formula: (< 0 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 11137#L611-3 [2256] L611-3-->L616-3: Formula: (and (= v_~T3_E~0_8 1) (= v_~T3_E~0_9 0)) InVars {~T3_E~0=v_~T3_E~0_9} OutVars{~T3_E~0=v_~T3_E~0_8} AuxVars[] AssignedVars[~T3_E~0] 11138#L616-3 [3339] L616-3-->L621-3: Formula: (> v_~T4_E~0_10 0) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 11012#L621-3 [3346] L621-3-->L626-3: Formula: (< 0 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 11013#L626-3 [2580] L626-3-->L631-3: Formula: (and (= v_~E_M~0_24 1) (= 0 v_~E_M~0_25)) InVars {~E_M~0=v_~E_M~0_25} OutVars{~E_M~0=v_~E_M~0_24} AuxVars[] AssignedVars[~E_M~0] 11068#L631-3 [2180] L631-3-->L636-3: Formula: (and (= v_~E_1~0_24 1) (= 0 v_~E_1~0_25)) InVars {~E_1~0=v_~E_1~0_25} OutVars{~E_1~0=v_~E_1~0_24} AuxVars[] AssignedVars[~E_1~0] 11069#L636-3 [3376] L636-3-->L641-3: Formula: (< 0 v_~E_2~0_26) InVars {~E_2~0=v_~E_2~0_26} OutVars{~E_2~0=v_~E_2~0_26} AuxVars[] AssignedVars[] 11259#L641-3 [2455] L641-3-->L646-3: Formula: (and (= 0 v_~E_3~0_25) (= v_~E_3~0_24 1)) InVars {~E_3~0=v_~E_3~0_25} OutVars{~E_3~0=v_~E_3~0_24} AuxVars[] AssignedVars[~E_3~0] 11260#L646-3 [2912] L646-3-->L651-3: Formula: (and (= 0 v_~E_4~0_25) (= v_~E_4~0_24 1)) InVars {~E_4~0=v_~E_4~0_25} OutVars{~E_4~0=v_~E_4~0_24} AuxVars[] AssignedVars[~E_4~0] 11204#L651-3 [3410] L651-3-->L656-3: Formula: (> 0 v_~E_5~0_26) InVars {~E_5~0=v_~E_5~0_26} OutVars{~E_5~0=v_~E_5~0_26} AuxVars[] AssignedVars[] 11205#L656-3 [2767] L656-3-->L294-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_37, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_37, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_22|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_22|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_22|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_37, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_37, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_22|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_22|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_22|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_22|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_37, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_37, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_37} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 11421#L294-21 [3426] L294-21-->L294-23: Formula: (< v_~m_pc~0_22 1) InVars {~m_pc~0=v_~m_pc~0_22} OutVars{~m_pc~0=v_~m_pc~0_22} AuxVars[] AssignedVars[] 11345#L294-23 [2803] L294-23-->L305-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_41 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_41} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 11344#L305-7 [3806] L305-7-->L745-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 11427#L745-21 [2835] L745-21-->L745-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_42) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} AuxVars[] AssignedVars[] 11428#L745-23 [2838] L745-23-->L313-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_43, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 11122#L313-21 [2243] L313-21-->L314-7: Formula: (= v_~t1_pc~0_21 1) InVars {~t1_pc~0=v_~t1_pc~0_21} OutVars{~t1_pc~0=v_~t1_pc~0_21} AuxVars[] AssignedVars[] 11123#L314-7 [2796] L314-7-->L324-7: Formula: (and (= 1 v_~E_1~0_27) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_46 1)) InVars {~E_1~0=v_~E_1~0_27} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_46, ~E_1~0=v_~E_1~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 11129#L324-7 [3813] L324-7-->L753-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 11159#L753-21 [2292] L753-21-->L753-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} AuxVars[] AssignedVars[] 11160#L753-23 [2297] L753-23-->L332-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_22|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 11162#L332-21 [2470] L332-21-->L333-7: Formula: (= 1 v_~t2_pc~0_21) InVars {~t2_pc~0=v_~t2_pc~0_21} OutVars{~t2_pc~0=v_~t2_pc~0_21} AuxVars[] AssignedVars[] 11242#L333-7 [2431] L333-7-->L343-7: Formula: (and (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_46 1) (= 1 v_~E_2~0_27)) InVars {~E_2~0=v_~E_2~0_27} OutVars{~E_2~0=v_~E_2~0_27, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_46} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 11244#L343-7 [3820] L343-7-->L761-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 11274#L761-21 [3538] L761-21-->L761-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___1~0_41 0) (= v_~t2_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41, ~t2_st~0=v_~t2_st~0_19} AuxVars[] AssignedVars[~t2_st~0] 11275#L761-23 [2493] L761-23-->L351-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_22|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 11276#L351-21 [2679] L351-21-->L352-7: Formula: (= v_~t3_pc~0_21 1) InVars {~t3_pc~0=v_~t3_pc~0_21} OutVars{~t3_pc~0=v_~t3_pc~0_21} AuxVars[] AssignedVars[] 11360#L352-7 [2622] L352-7-->L362-7: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_46 1) (= 1 v_~E_3~0_27)) InVars {~E_3~0=v_~E_3~0_27} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_46, ~E_3~0=v_~E_3~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 11291#L362-7 [3827] L362-7-->L769-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 11292#L769-21 [2534] L769-21-->L769-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} AuxVars[] AssignedVars[] 11298#L769-23 [2537] L769-23-->L370-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_43, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 11301#L370-21 [2927] L370-21-->L371-7: Formula: (= 1 v_~t4_pc~0_21) InVars {~t4_pc~0=v_~t4_pc~0_21} OutVars{~t4_pc~0=v_~t4_pc~0_21} AuxVars[] AssignedVars[] 11437#L371-7 [2863] L371-7-->L381-7: Formula: (and (= 1 v_~E_4~0_27) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_46 1)) InVars {~E_4~0=v_~E_4~0_27} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_46, ~E_4~0=v_~E_4~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 11403#L381-7 [3834] L381-7-->L777-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 11385#L777-21 [2705] L777-21-->L777-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} AuxVars[] AssignedVars[] 11386#L777-23 [2708] L777-23-->L389-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_22|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 11024#L389-21 [2132] L389-21-->L390-7: Formula: (= v_~t5_pc~0_21 1) InVars {~t5_pc~0=v_~t5_pc~0_21} OutVars{~t5_pc~0=v_~t5_pc~0_21} AuxVars[] AssignedVars[] 11025#L390-7 [2330] L390-7-->L400-7: Formula: (and (= 1 v_~E_5~0_27) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46 1)) InVars {~E_5~0=v_~E_5~0_27} OutVars{~E_5~0=v_~E_5~0_27, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 11000#L400-7 [3837] L400-7-->L785-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 11040#L785-21 [3654] L785-21-->L785-23: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_41 0) (= v_~t5_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} OutVars{~t5_st~0=v_~t5_st~0_19, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} AuxVars[] AssignedVars[~t5_st~0] 11048#L785-23 [2161] L785-23-->L669-3: Formula: (and (= v_~M_E~0_12 1) (= v_~M_E~0_11 2)) InVars {~M_E~0=v_~M_E~0_12} OutVars{~M_E~0=v_~M_E~0_11} AuxVars[] AssignedVars[~M_E~0] 11050#L669-3 [3660] L669-3-->L674-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 11269#L674-3 [3662] L674-3-->L679-3: Formula: (< 1 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 11270#L679-3 [3664] L679-3-->L684-3: Formula: (< 1 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 11201#L684-3 [3666] L684-3-->L689-3: Formula: (> v_~T4_E~0_13 1) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 11202#L689-3 [3668] L689-3-->L694-3: Formula: (< 1 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 11224#L694-3 [2405] L694-3-->L699-3: Formula: (and (= 1 v_~E_M~0_30) (= v_~E_M~0_29 2)) InVars {~E_M~0=v_~E_M~0_30} OutVars{~E_M~0=v_~E_M~0_29} AuxVars[] AssignedVars[~E_M~0] 11125#L699-3 [2245] L699-3-->L704-3: Formula: (and (= v_~E_1~0_29 2) (= 1 v_~E_1~0_30)) InVars {~E_1~0=v_~E_1~0_30} OutVars{~E_1~0=v_~E_1~0_29} AuxVars[] AssignedVars[~E_1~0] 11126#L704-3 [2661] L704-3-->L709-3: Formula: (and (= v_~E_2~0_29 2) (= 1 v_~E_2~0_30)) InVars {~E_2~0=v_~E_2~0_30} OutVars{~E_2~0=v_~E_2~0_29} AuxVars[] AssignedVars[~E_2~0] 11004#L709-3 [2114] L709-3-->L714-3: Formula: (and (= v_~E_3~0_29 2) (= 1 v_~E_3~0_30)) InVars {~E_3~0=v_~E_3~0_30} OutVars{~E_3~0=v_~E_3~0_29} AuxVars[] AssignedVars[~E_3~0] 11005#L714-3 [2573] L714-3-->L719-3: Formula: (and (= v_~E_4~0_29 2) (= 1 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 11090#L719-3 [3680] L719-3-->L724-3: Formula: (> 1 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 11091#L724-3 [2818] L724-3-->L454-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_23} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 11263#L454-1 [2466] L454-1-->L486-1: Formula: (and (= 0 v_~m_st~0_20) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26 1)) InVars {~m_st~0=v_~m_st~0_20} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 11077#L486-1 [3838] L486-1-->L949: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret15, ULTIMATE.start_start_simulation_~tmp~3] 11208#L949 [3688] L949-->L949-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_1) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} AuxVars[] AssignedVars[] 11271#L949-1 [2479] L949-1-->L454-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_1} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 11250#L454-2 [2438] L454-2-->L486-2: Formula: (and (= v_~m_st~0_2 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4 1)) InVars {~m_st~0=v_~m_st~0_2} OutVars{~m_st~0=v_~m_st~0_2, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 11082#L486-2 [3840] L486-2-->L904: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 11179#L904 [2393] L904-->L911: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 11215#L911 [3851] L911-->L930-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_6|, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 11087#L930-1 312.69/160.49 [2019-03-28 12:21:58,305 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.49 [2019-03-28 12:21:58,305 INFO L82 PathProgramCache]: Analyzing trace with hash 1399227929, now seen corresponding path program 1 times 312.69/160.49 [2019-03-28 12:21:58,305 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.49 [2019-03-28 12:21:58,305 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.49 [2019-03-28 12:21:58,306 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:21:58,307 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:21:58,307 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:21:58,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.49 [2019-03-28 12:21:58,328 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.49 [2019-03-28 12:21:58,328 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.49 [2019-03-28 12:21:58,329 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 312.69/160.49 [2019-03-28 12:21:58,329 INFO L799 eck$LassoCheckResult]: stem already infeasible 312.69/160.49 [2019-03-28 12:21:58,329 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.49 [2019-03-28 12:21:58,329 INFO L82 PathProgramCache]: Analyzing trace with hash 411329692, now seen corresponding path program 1 times 312.69/160.49 [2019-03-28 12:21:58,329 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.49 [2019-03-28 12:21:58,330 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.49 [2019-03-28 12:21:58,330 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:21:58,330 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:21:58,331 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:21:58,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.49 [2019-03-28 12:21:58,354 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.49 [2019-03-28 12:21:58,354 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.49 [2019-03-28 12:21:58,354 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 312.69/160.49 [2019-03-28 12:21:58,355 INFO L811 eck$LassoCheckResult]: loop already infeasible 312.69/160.49 [2019-03-28 12:21:58,355 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 312.69/160.49 [2019-03-28 12:21:58,355 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 312.69/160.49 [2019-03-28 12:21:58,355 INFO L87 Difference]: Start difference. First operand 454 states and 966 transitions. cyclomatic complexity: 513 Second operand 3 states. 312.69/160.49 [2019-03-28 12:21:58,943 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.49 [2019-03-28 12:21:58,943 INFO L93 Difference]: Finished difference Result 454 states and 956 transitions. 312.69/160.49 [2019-03-28 12:21:58,943 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 312.69/160.49 [2019-03-28 12:21:58,944 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 454 states and 956 transitions. 312.69/160.49 [2019-03-28 12:21:58,947 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 387 312.69/160.49 [2019-03-28 12:21:58,949 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 454 states to 454 states and 956 transitions. 312.69/160.49 [2019-03-28 12:21:58,949 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 454 312.69/160.49 [2019-03-28 12:21:58,950 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 454 312.69/160.49 [2019-03-28 12:21:58,950 INFO L73 IsDeterministic]: Start isDeterministic. Operand 454 states and 956 transitions. 312.69/160.49 [2019-03-28 12:21:58,951 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.49 [2019-03-28 12:21:58,951 INFO L706 BuchiCegarLoop]: Abstraction has 454 states and 956 transitions. 312.69/160.49 [2019-03-28 12:21:58,951 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 454 states and 956 transitions. 312.69/160.49 [2019-03-28 12:21:58,956 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 454 to 454. 312.69/160.49 [2019-03-28 12:21:58,956 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 454 states. 312.69/160.49 [2019-03-28 12:21:58,957 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 454 states to 454 states and 956 transitions. 312.69/160.49 [2019-03-28 12:21:58,957 INFO L729 BuchiCegarLoop]: Abstraction has 454 states and 956 transitions. 312.69/160.49 [2019-03-28 12:21:58,958 INFO L609 BuchiCegarLoop]: Abstraction has 454 states and 956 transitions. 312.69/160.49 [2019-03-28 12:21:58,958 INFO L442 BuchiCegarLoop]: ======== Iteration 14============ 312.69/160.49 [2019-03-28 12:21:58,958 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 454 states and 956 transitions. 312.69/160.49 [2019-03-28 12:21:58,960 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 387 312.69/160.49 [2019-03-28 12:21:58,960 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.49 [2019-03-28 12:21:58,960 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.49 [2019-03-28 12:21:58,961 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.49 [2019-03-28 12:21:58,961 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.49 [2019-03-28 12:21:58,962 INFO L794 eck$LassoCheckResult]: Stem: 12280#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 12096#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 12097#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 12164#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 12165#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 12098#L431-1 [2355] L431-1-->L436-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 12099#L436-1 [2735] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 12137#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 12138#L601-1 [3235] L601-1-->L606-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 12141#L606-1 [3236] L606-1-->L611-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 12043#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 12044#L616-1 [3240] L616-1-->L621-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 11922#L621-1 [3242] L621-1-->L626-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 11923#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 12008#L631-1 [3247] L631-1-->L636-1: Formula: (< v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 12009#L636-1 [2819] L636-1-->L641-1: Formula: (and (= v_~E_2~0_3 0) (= v_~E_2~0_2 1)) InVars {~E_2~0=v_~E_2~0_3} OutVars{~E_2~0=v_~E_2~0_2} AuxVars[] AssignedVars[~E_2~0] 12183#L641-1 [2474] L641-1-->L646-1: Formula: (and (= v_~E_3~0_3 0) (= v_~E_3~0_2 1)) InVars {~E_3~0=v_~E_3~0_3} OutVars{~E_3~0=v_~E_3~0_2} AuxVars[] AssignedVars[~E_3~0] 12184#L646-1 [2935] L646-1-->L651-1: Formula: (and (= v_~E_4~0_2 1) (= v_~E_4~0_3 0)) InVars {~E_4~0=v_~E_4~0_3} OutVars{~E_4~0=v_~E_4~0_2} AuxVars[] AssignedVars[~E_4~0] 12129#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 12130#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 12340#L294 [2854] L294-->L295: Formula: (= v_~m_pc~0_2 1) InVars {~m_pc~0=v_~m_pc~0_2} OutVars{~m_pc~0=v_~m_pc~0_2} AuxVars[] AssignedVars[] 12253#L295 [2595] L295-->L305: Formula: (and (= v_~E_M~0_5 1) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_4 1)) InVars {~E_M~0=v_~E_M~0_5} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_4, ~E_M~0=v_~E_M~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 12254#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 12359#L745 [3261] L745-->L745-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_5) (= v_~m_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} OutVars{~m_st~0=v_~m_st~0_6, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} AuxVars[] AssignedVars[~m_st~0] 12364#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 12079#L313 [2301] L313-->L314: Formula: (= v_~t1_pc~0_2 1) InVars {~t1_pc~0=v_~t1_pc~0_2} OutVars{~t1_pc~0=v_~t1_pc~0_2} AuxVars[] AssignedVars[] 12035#L314 [2241] L314-->L324: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_4 1) (= v_~E_1~0_5 1)) InVars {~E_1~0=v_~E_1~0_5} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_4, ~E_1~0=v_~E_1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 12037#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 11937#L753 [3267] L753-->L753-2: Formula: (and (> 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_5) (= v_~t1_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_5, ~t1_st~0=v_~t1_st~0_6} AuxVars[] AssignedVars[~t1_st~0] 11938#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 11942#L332 [3269] L332-->L332-2: Formula: (> v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 12106#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 12104#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 12105#L761 [3273] L761-->L761-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_5) (= v_~t2_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5, ~t2_st~0=v_~t2_st~0_6} AuxVars[] AssignedVars[~t2_st~0] 12125#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 12126#L351 [2567] L351-->L352: Formula: (= 1 v_~t3_pc~0_2) InVars {~t3_pc~0=v_~t3_pc~0_2} OutVars{~t3_pc~0=v_~t3_pc~0_2} AuxVars[] AssignedVars[] 12242#L352 [2655] L352-->L362: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_4 1) (= v_~E_3~0_5 1)) InVars {~E_3~0=v_~E_3~0_5} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_4, ~E_3~0=v_~E_3~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 12224#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 12241#L769 [3279] L769-->L769-2: Formula: (and (= v_~t3_st~0_6 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_5)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} OutVars{~t3_st~0=v_~t3_st~0_6, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} AuxVars[] AssignedVars[~t3_st~0] 12245#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 12246#L370 [3281] L370-->L370-2: Formula: (> v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 12329#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 12325#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 12326#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 12339#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 11999#L389 [2193] L389-->L390: Formula: (= 1 v_~t5_pc~0_2) InVars {~t5_pc~0=v_~t5_pc~0_2} OutVars{~t5_pc~0=v_~t5_pc~0_2} AuxVars[] AssignedVars[] 12000#L390 [2343] L390-->L400: Formula: (and (= v_~E_5~0_5 1) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4 1)) InVars {~E_5~0=v_~E_5~0_5} OutVars{~E_5~0=v_~E_5~0_5, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 11969#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 11995#L785 [3291] L785-->L785-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_5) (= v_~t5_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} OutVars{~t5_st~0=v_~t5_st~0_6, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} AuxVars[] AssignedVars[~t5_st~0] 12015#L785-2 [3293] L785-2-->L669-1: Formula: (> 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 12017#L669-1 [3294] L669-1-->L674-1: Formula: (< 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 12181#L674-1 [3296] L674-1-->L679-1: Formula: (< 1 v_~T2_E~0_7) InVars {~T2_E~0=v_~T2_E~0_7} OutVars{~T2_E~0=v_~T2_E~0_7} AuxVars[] AssignedVars[] 12182#L679-1 [3299] L679-1-->L684-1: Formula: (< v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 12127#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 12128#L689-1 [3302] L689-1-->L694-1: Formula: (> v_~T5_E~0_7 1) InVars {~T5_E~0=v_~T5_E~0_7} OutVars{~T5_E~0=v_~T5_E~0_7} AuxVars[] AssignedVars[] 12274#L694-1 [3305] L694-1-->L699-1: Formula: (< v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 12064#L699-1 [3307] L699-1-->L704-1: Formula: (< v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 12065#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 11911#L709-1 [3311] L709-1-->L714-1: Formula: (< v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 11912#L714-1 [2569] L714-1-->L719-1: Formula: (and (= v_~E_4~0_8 1) (= v_~E_4~0_7 2)) InVars {~E_4~0=v_~E_4~0_8} OutVars{~E_4~0=v_~E_4~0_7} AuxVars[] AssignedVars[~E_4~0] 12002#L719-1 [2198] L719-1-->L930-1: Formula: (and (= v_~E_5~0_8 1) (= v_~E_5~0_7 2)) InVars {~E_5~0=v_~E_5~0_8} OutVars{~E_5~0=v_~E_5~0_7} AuxVars[] AssignedVars[~E_5~0] 12003#L930-1 312.69/160.49 [2019-03-28 12:21:58,963 INFO L796 eck$LassoCheckResult]: Loop: 12003#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 12010#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 12011#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 11990#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 12055#L501 [3784] L501-->L601-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 12056#L601-2 [2768] L601-2-->L601-4: Formula: (and (= v_~M_E~0_8 1) (= 0 v_~M_E~0_9)) InVars {~M_E~0=v_~M_E~0_9} OutVars{~M_E~0=v_~M_E~0_8} AuxVars[] AssignedVars[~M_E~0] 12338#L601-4 [3322] L601-4-->L606-3: Formula: (> v_~T1_E~0_10 0) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 12144#L606-3 [3326] L606-3-->L611-3: Formula: (< 0 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 12053#L611-3 [2256] L611-3-->L616-3: Formula: (and (= v_~T3_E~0_8 1) (= v_~T3_E~0_9 0)) InVars {~T3_E~0=v_~T3_E~0_9} OutVars{~T3_E~0=v_~T3_E~0_8} AuxVars[] AssignedVars[~T3_E~0] 12054#L616-3 [3339] L616-3-->L621-3: Formula: (> v_~T4_E~0_10 0) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 11928#L621-3 [3346] L621-3-->L626-3: Formula: (< 0 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 11929#L626-3 [2580] L626-3-->L631-3: Formula: (and (= v_~E_M~0_24 1) (= 0 v_~E_M~0_25)) InVars {~E_M~0=v_~E_M~0_25} OutVars{~E_M~0=v_~E_M~0_24} AuxVars[] AssignedVars[~E_M~0] 11984#L631-3 [2180] L631-3-->L636-3: Formula: (and (= v_~E_1~0_24 1) (= 0 v_~E_1~0_25)) InVars {~E_1~0=v_~E_1~0_25} OutVars{~E_1~0=v_~E_1~0_24} AuxVars[] AssignedVars[~E_1~0] 11985#L636-3 [3376] L636-3-->L641-3: Formula: (< 0 v_~E_2~0_26) InVars {~E_2~0=v_~E_2~0_26} OutVars{~E_2~0=v_~E_2~0_26} AuxVars[] AssignedVars[] 12175#L641-3 [2455] L641-3-->L646-3: Formula: (and (= 0 v_~E_3~0_25) (= v_~E_3~0_24 1)) InVars {~E_3~0=v_~E_3~0_25} OutVars{~E_3~0=v_~E_3~0_24} AuxVars[] AssignedVars[~E_3~0] 12176#L646-3 [2912] L646-3-->L651-3: Formula: (and (= 0 v_~E_4~0_25) (= v_~E_4~0_24 1)) InVars {~E_4~0=v_~E_4~0_25} OutVars{~E_4~0=v_~E_4~0_24} AuxVars[] AssignedVars[~E_4~0] 12120#L651-3 [3410] L651-3-->L656-3: Formula: (> 0 v_~E_5~0_26) InVars {~E_5~0=v_~E_5~0_26} OutVars{~E_5~0=v_~E_5~0_26} AuxVars[] AssignedVars[] 12121#L656-3 [2767] L656-3-->L294-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_37, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_37, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_22|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_22|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_22|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_37, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_37, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_22|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_22|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_22|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_22|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_37, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_37, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_37} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 12337#L294-21 [2808] L294-21-->L295-7: Formula: (= v_~m_pc~0_21 1) InVars {~m_pc~0=v_~m_pc~0_21} OutVars{~m_pc~0=v_~m_pc~0_21} AuxVars[] AssignedVars[] 12259#L295-7 [2602] L295-7-->L305-7: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_40 1) (= 1 v_~E_M~0_27)) InVars {~E_M~0=v_~E_M~0_27} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_40, ~E_M~0=v_~E_M~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 12260#L305-7 [3806] L305-7-->L745-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 12343#L745-21 [2835] L745-21-->L745-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_42) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} AuxVars[] AssignedVars[] 12344#L745-23 [2838] L745-23-->L313-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_43, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 12038#L313-21 [2243] L313-21-->L314-7: Formula: (= v_~t1_pc~0_21 1) InVars {~t1_pc~0=v_~t1_pc~0_21} OutVars{~t1_pc~0=v_~t1_pc~0_21} AuxVars[] AssignedVars[] 12039#L314-7 [2796] L314-7-->L324-7: Formula: (and (= 1 v_~E_1~0_27) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_46 1)) InVars {~E_1~0=v_~E_1~0_27} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_46, ~E_1~0=v_~E_1~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 12045#L324-7 [3813] L324-7-->L753-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 12075#L753-21 [2292] L753-21-->L753-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} AuxVars[] AssignedVars[] 12076#L753-23 [2297] L753-23-->L332-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_22|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 12078#L332-21 [2470] L332-21-->L333-7: Formula: (= 1 v_~t2_pc~0_21) InVars {~t2_pc~0=v_~t2_pc~0_21} OutVars{~t2_pc~0=v_~t2_pc~0_21} AuxVars[] AssignedVars[] 12158#L333-7 [2431] L333-7-->L343-7: Formula: (and (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_46 1) (= 1 v_~E_2~0_27)) InVars {~E_2~0=v_~E_2~0_27} OutVars{~E_2~0=v_~E_2~0_27, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_46} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 12160#L343-7 [3820] L343-7-->L761-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 12190#L761-21 [3538] L761-21-->L761-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___1~0_41 0) (= v_~t2_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41, ~t2_st~0=v_~t2_st~0_19} AuxVars[] AssignedVars[~t2_st~0] 12191#L761-23 [2493] L761-23-->L351-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_22|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 12192#L351-21 [2679] L351-21-->L352-7: Formula: (= v_~t3_pc~0_21 1) InVars {~t3_pc~0=v_~t3_pc~0_21} OutVars{~t3_pc~0=v_~t3_pc~0_21} AuxVars[] AssignedVars[] 12276#L352-7 [2622] L352-7-->L362-7: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_46 1) (= 1 v_~E_3~0_27)) InVars {~E_3~0=v_~E_3~0_27} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_46, ~E_3~0=v_~E_3~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 12207#L362-7 [3827] L362-7-->L769-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 12208#L769-21 [2534] L769-21-->L769-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} AuxVars[] AssignedVars[] 12214#L769-23 [2537] L769-23-->L370-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_43, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 12217#L370-21 [2927] L370-21-->L371-7: Formula: (= 1 v_~t4_pc~0_21) InVars {~t4_pc~0=v_~t4_pc~0_21} OutVars{~t4_pc~0=v_~t4_pc~0_21} AuxVars[] AssignedVars[] 12353#L371-7 [2863] L371-7-->L381-7: Formula: (and (= 1 v_~E_4~0_27) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_46 1)) InVars {~E_4~0=v_~E_4~0_27} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_46, ~E_4~0=v_~E_4~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 12319#L381-7 [3834] L381-7-->L777-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 12301#L777-21 [2705] L777-21-->L777-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} AuxVars[] AssignedVars[] 12302#L777-23 [2708] L777-23-->L389-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_22|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 11940#L389-21 [2132] L389-21-->L390-7: Formula: (= v_~t5_pc~0_21 1) InVars {~t5_pc~0=v_~t5_pc~0_21} OutVars{~t5_pc~0=v_~t5_pc~0_21} AuxVars[] AssignedVars[] 11941#L390-7 [2330] L390-7-->L400-7: Formula: (and (= 1 v_~E_5~0_27) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46 1)) InVars {~E_5~0=v_~E_5~0_27} OutVars{~E_5~0=v_~E_5~0_27, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 11916#L400-7 [3837] L400-7-->L785-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 11956#L785-21 [3654] L785-21-->L785-23: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_41 0) (= v_~t5_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} OutVars{~t5_st~0=v_~t5_st~0_19, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} AuxVars[] AssignedVars[~t5_st~0] 11964#L785-23 [2161] L785-23-->L669-3: Formula: (and (= v_~M_E~0_12 1) (= v_~M_E~0_11 2)) InVars {~M_E~0=v_~M_E~0_12} OutVars{~M_E~0=v_~M_E~0_11} AuxVars[] AssignedVars[~M_E~0] 11966#L669-3 [3660] L669-3-->L674-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 12185#L674-3 [3662] L674-3-->L679-3: Formula: (< 1 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 12186#L679-3 [3664] L679-3-->L684-3: Formula: (< 1 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 12117#L684-3 [3666] L684-3-->L689-3: Formula: (> v_~T4_E~0_13 1) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 12118#L689-3 [3668] L689-3-->L694-3: Formula: (< 1 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 12140#L694-3 [2405] L694-3-->L699-3: Formula: (and (= 1 v_~E_M~0_30) (= v_~E_M~0_29 2)) InVars {~E_M~0=v_~E_M~0_30} OutVars{~E_M~0=v_~E_M~0_29} AuxVars[] AssignedVars[~E_M~0] 12041#L699-3 [2245] L699-3-->L704-3: Formula: (and (= v_~E_1~0_29 2) (= 1 v_~E_1~0_30)) InVars {~E_1~0=v_~E_1~0_30} OutVars{~E_1~0=v_~E_1~0_29} AuxVars[] AssignedVars[~E_1~0] 12042#L704-3 [2661] L704-3-->L709-3: Formula: (and (= v_~E_2~0_29 2) (= 1 v_~E_2~0_30)) InVars {~E_2~0=v_~E_2~0_30} OutVars{~E_2~0=v_~E_2~0_29} AuxVars[] AssignedVars[~E_2~0] 11920#L709-3 [2114] L709-3-->L714-3: Formula: (and (= v_~E_3~0_29 2) (= 1 v_~E_3~0_30)) InVars {~E_3~0=v_~E_3~0_30} OutVars{~E_3~0=v_~E_3~0_29} AuxVars[] AssignedVars[~E_3~0] 11921#L714-3 [2573] L714-3-->L719-3: Formula: (and (= v_~E_4~0_29 2) (= 1 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 12006#L719-3 [3680] L719-3-->L724-3: Formula: (> 1 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 12007#L724-3 [2818] L724-3-->L454-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_23} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 12179#L454-1 [2466] L454-1-->L486-1: Formula: (and (= 0 v_~m_st~0_20) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26 1)) InVars {~m_st~0=v_~m_st~0_20} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 11993#L486-1 [3838] L486-1-->L949: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret15, ULTIMATE.start_start_simulation_~tmp~3] 12124#L949 [3688] L949-->L949-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_1) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} AuxVars[] AssignedVars[] 12187#L949-1 [2479] L949-1-->L454-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_1} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 12166#L454-2 [2438] L454-2-->L486-2: Formula: (and (= v_~m_st~0_2 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4 1)) InVars {~m_st~0=v_~m_st~0_2} OutVars{~m_st~0=v_~m_st~0_2, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 11998#L486-2 [3840] L486-2-->L904: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 12095#L904 [2393] L904-->L911: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 12131#L911 [3851] L911-->L930-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_6|, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 12003#L930-1 312.69/160.49 [2019-03-28 12:21:58,964 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.49 [2019-03-28 12:21:58,964 INFO L82 PathProgramCache]: Analyzing trace with hash -947566560, now seen corresponding path program 1 times 312.69/160.49 [2019-03-28 12:21:58,964 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.49 [2019-03-28 12:21:58,964 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.49 [2019-03-28 12:21:58,965 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:21:58,965 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:21:58,965 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:21:58,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.49 [2019-03-28 12:21:58,990 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.49 [2019-03-28 12:21:58,990 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.49 [2019-03-28 12:21:58,990 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 312.69/160.49 [2019-03-28 12:21:58,991 INFO L799 eck$LassoCheckResult]: stem already infeasible 312.69/160.49 [2019-03-28 12:21:58,991 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.49 [2019-03-28 12:21:58,991 INFO L82 PathProgramCache]: Analyzing trace with hash 300905213, now seen corresponding path program 1 times 312.69/160.49 [2019-03-28 12:21:58,991 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.49 [2019-03-28 12:21:58,991 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.49 [2019-03-28 12:21:58,992 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:21:58,992 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:21:58,992 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:21:58,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.49 [2019-03-28 12:21:59,019 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.49 [2019-03-28 12:21:59,019 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.49 [2019-03-28 12:21:59,020 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 312.69/160.49 [2019-03-28 12:21:59,020 INFO L811 eck$LassoCheckResult]: loop already infeasible 312.69/160.49 [2019-03-28 12:21:59,020 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 312.69/160.49 [2019-03-28 12:21:59,020 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 312.69/160.49 [2019-03-28 12:21:59,020 INFO L87 Difference]: Start difference. First operand 454 states and 956 transitions. cyclomatic complexity: 503 Second operand 3 states. 312.69/160.49 [2019-03-28 12:21:59,703 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.49 [2019-03-28 12:21:59,703 INFO L93 Difference]: Finished difference Result 482 states and 984 transitions. 312.69/160.49 [2019-03-28 12:21:59,703 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 312.69/160.49 [2019-03-28 12:21:59,704 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 482 states and 984 transitions. 312.69/160.49 [2019-03-28 12:21:59,706 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 415 312.69/160.49 [2019-03-28 12:21:59,709 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 482 states to 482 states and 984 transitions. 312.69/160.49 [2019-03-28 12:21:59,709 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 482 312.69/160.49 [2019-03-28 12:21:59,710 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 482 312.69/160.49 [2019-03-28 12:21:59,710 INFO L73 IsDeterministic]: Start isDeterministic. Operand 482 states and 984 transitions. 312.69/160.49 [2019-03-28 12:21:59,711 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.49 [2019-03-28 12:21:59,711 INFO L706 BuchiCegarLoop]: Abstraction has 482 states and 984 transitions. 312.69/160.49 [2019-03-28 12:21:59,711 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 482 states and 984 transitions. 312.69/160.49 [2019-03-28 12:21:59,717 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 482 to 454. 312.69/160.49 [2019-03-28 12:21:59,717 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 454 states. 312.69/160.49 [2019-03-28 12:21:59,718 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 454 states to 454 states and 930 transitions. 312.69/160.49 [2019-03-28 12:21:59,718 INFO L729 BuchiCegarLoop]: Abstraction has 454 states and 930 transitions. 312.69/160.49 [2019-03-28 12:21:59,718 INFO L609 BuchiCegarLoop]: Abstraction has 454 states and 930 transitions. 312.69/160.49 [2019-03-28 12:21:59,718 INFO L442 BuchiCegarLoop]: ======== Iteration 15============ 312.69/160.49 [2019-03-28 12:21:59,719 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 454 states and 930 transitions. 312.69/160.49 [2019-03-28 12:21:59,720 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 387 312.69/160.49 [2019-03-28 12:21:59,721 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.49 [2019-03-28 12:21:59,721 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.49 [2019-03-28 12:21:59,722 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.49 [2019-03-28 12:21:59,722 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.49 [2019-03-28 12:21:59,723 INFO L794 eck$LassoCheckResult]: Stem: 13224#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 13040#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 13041#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 13108#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 13109#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 13042#L431-1 [2355] L431-1-->L436-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 13043#L436-1 [2735] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 13081#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 13082#L601-1 [3235] L601-1-->L606-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 13085#L606-1 [3236] L606-1-->L611-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 12982#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 12983#L616-1 [3240] L616-1-->L621-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 12866#L621-1 [3242] L621-1-->L626-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 12867#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 12952#L631-1 [3246] L631-1-->L636-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 12953#L636-1 [2819] L636-1-->L641-1: Formula: (and (= v_~E_2~0_3 0) (= v_~E_2~0_2 1)) InVars {~E_2~0=v_~E_2~0_3} OutVars{~E_2~0=v_~E_2~0_2} AuxVars[] AssignedVars[~E_2~0] 13127#L641-1 [2474] L641-1-->L646-1: Formula: (and (= v_~E_3~0_3 0) (= v_~E_3~0_2 1)) InVars {~E_3~0=v_~E_3~0_3} OutVars{~E_3~0=v_~E_3~0_2} AuxVars[] AssignedVars[~E_3~0] 13128#L646-1 [2935] L646-1-->L651-1: Formula: (and (= v_~E_4~0_2 1) (= v_~E_4~0_3 0)) InVars {~E_4~0=v_~E_4~0_3} OutVars{~E_4~0=v_~E_4~0_2} AuxVars[] AssignedVars[~E_4~0] 13073#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 13074#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 13284#L294 [2854] L294-->L295: Formula: (= v_~m_pc~0_2 1) InVars {~m_pc~0=v_~m_pc~0_2} OutVars{~m_pc~0=v_~m_pc~0_2} AuxVars[] AssignedVars[] 13197#L295 [2595] L295-->L305: Formula: (and (= v_~E_M~0_5 1) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_4 1)) InVars {~E_M~0=v_~E_M~0_5} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_4, ~E_M~0=v_~E_M~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 13198#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 13303#L745 [3261] L745-->L745-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_5) (= v_~m_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} OutVars{~m_st~0=v_~m_st~0_6, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} AuxVars[] AssignedVars[~m_st~0] 13308#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 13023#L313 [3263] L313-->L313-2: Formula: (> v_~t1_pc~0_3 1) InVars {~t1_pc~0=v_~t1_pc~0_3} OutVars{~t1_pc~0=v_~t1_pc~0_3} AuxVars[] AssignedVars[] 12976#L313-2 [2314] L313-2-->L324: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 13022#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 12881#L753 [3267] L753-->L753-2: Formula: (and (> 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_5) (= v_~t1_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_5, ~t1_st~0=v_~t1_st~0_6} AuxVars[] AssignedVars[~t1_st~0] 12882#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 12886#L332 [3269] L332-->L332-2: Formula: (> v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 13050#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 13048#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 13049#L761 [3273] L761-->L761-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_5) (= v_~t2_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5, ~t2_st~0=v_~t2_st~0_6} AuxVars[] AssignedVars[~t2_st~0] 13069#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 13070#L351 [2567] L351-->L352: Formula: (= 1 v_~t3_pc~0_2) InVars {~t3_pc~0=v_~t3_pc~0_2} OutVars{~t3_pc~0=v_~t3_pc~0_2} AuxVars[] AssignedVars[] 13186#L352 [2655] L352-->L362: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_4 1) (= v_~E_3~0_5 1)) InVars {~E_3~0=v_~E_3~0_5} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_4, ~E_3~0=v_~E_3~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 13168#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 13185#L769 [3279] L769-->L769-2: Formula: (and (= v_~t3_st~0_6 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_5)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} OutVars{~t3_st~0=v_~t3_st~0_6, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} AuxVars[] AssignedVars[~t3_st~0] 13189#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 13190#L370 [3281] L370-->L370-2: Formula: (> v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 13273#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 13269#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 13270#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 13283#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 12943#L389 [2193] L389-->L390: Formula: (= 1 v_~t5_pc~0_2) InVars {~t5_pc~0=v_~t5_pc~0_2} OutVars{~t5_pc~0=v_~t5_pc~0_2} AuxVars[] AssignedVars[] 12944#L390 [2343] L390-->L400: Formula: (and (= v_~E_5~0_5 1) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4 1)) InVars {~E_5~0=v_~E_5~0_5} OutVars{~E_5~0=v_~E_5~0_5, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 12913#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 12939#L785 [3291] L785-->L785-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_5) (= v_~t5_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} OutVars{~t5_st~0=v_~t5_st~0_6, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} AuxVars[] AssignedVars[~t5_st~0] 12959#L785-2 [3293] L785-2-->L669-1: Formula: (> 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 12961#L669-1 [3294] L669-1-->L674-1: Formula: (< 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 13125#L674-1 [3296] L674-1-->L679-1: Formula: (< 1 v_~T2_E~0_7) InVars {~T2_E~0=v_~T2_E~0_7} OutVars{~T2_E~0=v_~T2_E~0_7} AuxVars[] AssignedVars[] 13126#L679-1 [3299] L679-1-->L684-1: Formula: (< v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 13071#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 13072#L689-1 [3302] L689-1-->L694-1: Formula: (> v_~T5_E~0_7 1) InVars {~T5_E~0=v_~T5_E~0_7} OutVars{~T5_E~0=v_~T5_E~0_7} AuxVars[] AssignedVars[] 13218#L694-1 [3305] L694-1-->L699-1: Formula: (< v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 13004#L699-1 [3306] L699-1-->L704-1: Formula: (> v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 13005#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 12855#L709-1 [3311] L709-1-->L714-1: Formula: (< v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 12856#L714-1 [2569] L714-1-->L719-1: Formula: (and (= v_~E_4~0_8 1) (= v_~E_4~0_7 2)) InVars {~E_4~0=v_~E_4~0_8} OutVars{~E_4~0=v_~E_4~0_7} AuxVars[] AssignedVars[~E_4~0] 12946#L719-1 [2198] L719-1-->L930-1: Formula: (and (= v_~E_5~0_8 1) (= v_~E_5~0_7 2)) InVars {~E_5~0=v_~E_5~0_8} OutVars{~E_5~0=v_~E_5~0_7} AuxVars[] AssignedVars[~E_5~0] 12947#L930-1 312.69/160.49 [2019-03-28 12:21:59,724 INFO L796 eck$LassoCheckResult]: Loop: 12947#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 12954#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 12955#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 12934#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 12994#L501 [3784] L501-->L601-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 12995#L601-2 [2768] L601-2-->L601-4: Formula: (and (= v_~M_E~0_8 1) (= 0 v_~M_E~0_9)) InVars {~M_E~0=v_~M_E~0_9} OutVars{~M_E~0=v_~M_E~0_8} AuxVars[] AssignedVars[~M_E~0] 13282#L601-4 [3322] L601-4-->L606-3: Formula: (> v_~T1_E~0_10 0) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 13088#L606-3 [3326] L606-3-->L611-3: Formula: (< 0 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 12992#L611-3 [2256] L611-3-->L616-3: Formula: (and (= v_~T3_E~0_8 1) (= v_~T3_E~0_9 0)) InVars {~T3_E~0=v_~T3_E~0_9} OutVars{~T3_E~0=v_~T3_E~0_8} AuxVars[] AssignedVars[~T3_E~0] 12993#L616-3 [3339] L616-3-->L621-3: Formula: (> v_~T4_E~0_10 0) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 12872#L621-3 [3346] L621-3-->L626-3: Formula: (< 0 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 12873#L626-3 [2580] L626-3-->L631-3: Formula: (and (= v_~E_M~0_24 1) (= 0 v_~E_M~0_25)) InVars {~E_M~0=v_~E_M~0_25} OutVars{~E_M~0=v_~E_M~0_24} AuxVars[] AssignedVars[~E_M~0] 12928#L631-3 [3365] L631-3-->L636-3: Formula: (< 0 v_~E_1~0_26) InVars {~E_1~0=v_~E_1~0_26} OutVars{~E_1~0=v_~E_1~0_26} AuxVars[] AssignedVars[] 12929#L636-3 [3376] L636-3-->L641-3: Formula: (< 0 v_~E_2~0_26) InVars {~E_2~0=v_~E_2~0_26} OutVars{~E_2~0=v_~E_2~0_26} AuxVars[] AssignedVars[] 13119#L641-3 [2455] L641-3-->L646-3: Formula: (and (= 0 v_~E_3~0_25) (= v_~E_3~0_24 1)) InVars {~E_3~0=v_~E_3~0_25} OutVars{~E_3~0=v_~E_3~0_24} AuxVars[] AssignedVars[~E_3~0] 13120#L646-3 [2912] L646-3-->L651-3: Formula: (and (= 0 v_~E_4~0_25) (= v_~E_4~0_24 1)) InVars {~E_4~0=v_~E_4~0_25} OutVars{~E_4~0=v_~E_4~0_24} AuxVars[] AssignedVars[~E_4~0] 13064#L651-3 [3410] L651-3-->L656-3: Formula: (> 0 v_~E_5~0_26) InVars {~E_5~0=v_~E_5~0_26} OutVars{~E_5~0=v_~E_5~0_26} AuxVars[] AssignedVars[] 13065#L656-3 [2767] L656-3-->L294-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_37, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_37, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_22|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_22|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_22|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_37, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_37, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_22|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_22|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_22|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_22|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_37, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_37, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_37} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 13281#L294-21 [2808] L294-21-->L295-7: Formula: (= v_~m_pc~0_21 1) InVars {~m_pc~0=v_~m_pc~0_21} OutVars{~m_pc~0=v_~m_pc~0_21} AuxVars[] AssignedVars[] 13203#L295-7 [2602] L295-7-->L305-7: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_40 1) (= 1 v_~E_M~0_27)) InVars {~E_M~0=v_~E_M~0_27} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_40, ~E_M~0=v_~E_M~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 13204#L305-7 [3806] L305-7-->L745-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 13287#L745-21 [2835] L745-21-->L745-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_42) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} AuxVars[] AssignedVars[] 13288#L745-23 [2838] L745-23-->L313-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_43, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 12977#L313-21 [3468] L313-21-->L313-23: Formula: (> v_~t1_pc~0_22 1) InVars {~t1_pc~0=v_~t1_pc~0_22} OutVars{~t1_pc~0=v_~t1_pc~0_22} AuxVars[] AssignedVars[] 12979#L313-23 [2249] L313-23-->L324-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 12984#L324-7 [3813] L324-7-->L753-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 13017#L753-21 [2292] L753-21-->L753-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} AuxVars[] AssignedVars[] 13018#L753-23 [2297] L753-23-->L332-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_22|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 13021#L332-21 [2470] L332-21-->L333-7: Formula: (= 1 v_~t2_pc~0_21) InVars {~t2_pc~0=v_~t2_pc~0_21} OutVars{~t2_pc~0=v_~t2_pc~0_21} AuxVars[] AssignedVars[] 13102#L333-7 [2431] L333-7-->L343-7: Formula: (and (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_46 1) (= 1 v_~E_2~0_27)) InVars {~E_2~0=v_~E_2~0_27} OutVars{~E_2~0=v_~E_2~0_27, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_46} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 13104#L343-7 [3820] L343-7-->L761-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 13134#L761-21 [3538] L761-21-->L761-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___1~0_41 0) (= v_~t2_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41, ~t2_st~0=v_~t2_st~0_19} AuxVars[] AssignedVars[~t2_st~0] 13135#L761-23 [2493] L761-23-->L351-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_22|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 13136#L351-21 [2679] L351-21-->L352-7: Formula: (= v_~t3_pc~0_21 1) InVars {~t3_pc~0=v_~t3_pc~0_21} OutVars{~t3_pc~0=v_~t3_pc~0_21} AuxVars[] AssignedVars[] 13220#L352-7 [2622] L352-7-->L362-7: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_46 1) (= 1 v_~E_3~0_27)) InVars {~E_3~0=v_~E_3~0_27} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_46, ~E_3~0=v_~E_3~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 13151#L362-7 [3827] L362-7-->L769-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 13152#L769-21 [2534] L769-21-->L769-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} AuxVars[] AssignedVars[] 13158#L769-23 [2537] L769-23-->L370-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_43, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 13161#L370-21 [2927] L370-21-->L371-7: Formula: (= 1 v_~t4_pc~0_21) InVars {~t4_pc~0=v_~t4_pc~0_21} OutVars{~t4_pc~0=v_~t4_pc~0_21} AuxVars[] AssignedVars[] 13297#L371-7 [2863] L371-7-->L381-7: Formula: (and (= 1 v_~E_4~0_27) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_46 1)) InVars {~E_4~0=v_~E_4~0_27} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_46, ~E_4~0=v_~E_4~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 13263#L381-7 [3834] L381-7-->L777-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 13245#L777-21 [2705] L777-21-->L777-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} AuxVars[] AssignedVars[] 13246#L777-23 [2708] L777-23-->L389-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_22|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 12884#L389-21 [2132] L389-21-->L390-7: Formula: (= v_~t5_pc~0_21 1) InVars {~t5_pc~0=v_~t5_pc~0_21} OutVars{~t5_pc~0=v_~t5_pc~0_21} AuxVars[] AssignedVars[] 12885#L390-7 [2330] L390-7-->L400-7: Formula: (and (= 1 v_~E_5~0_27) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46 1)) InVars {~E_5~0=v_~E_5~0_27} OutVars{~E_5~0=v_~E_5~0_27, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 12860#L400-7 [3837] L400-7-->L785-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 12900#L785-21 [3654] L785-21-->L785-23: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_41 0) (= v_~t5_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} OutVars{~t5_st~0=v_~t5_st~0_19, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} AuxVars[] AssignedVars[~t5_st~0] 12908#L785-23 [2161] L785-23-->L669-3: Formula: (and (= v_~M_E~0_12 1) (= v_~M_E~0_11 2)) InVars {~M_E~0=v_~M_E~0_12} OutVars{~M_E~0=v_~M_E~0_11} AuxVars[] AssignedVars[~M_E~0] 12910#L669-3 [3660] L669-3-->L674-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 13129#L674-3 [3662] L674-3-->L679-3: Formula: (< 1 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 13130#L679-3 [3664] L679-3-->L684-3: Formula: (< 1 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 13061#L684-3 [3666] L684-3-->L689-3: Formula: (> v_~T4_E~0_13 1) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 13062#L689-3 [3668] L689-3-->L694-3: Formula: (< 1 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 13084#L694-3 [2405] L694-3-->L699-3: Formula: (and (= 1 v_~E_M~0_30) (= v_~E_M~0_29 2)) InVars {~E_M~0=v_~E_M~0_30} OutVars{~E_M~0=v_~E_M~0_29} AuxVars[] AssignedVars[~E_M~0] 12980#L699-3 [3673] L699-3-->L704-3: Formula: (< 1 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 12981#L704-3 [2661] L704-3-->L709-3: Formula: (and (= v_~E_2~0_29 2) (= 1 v_~E_2~0_30)) InVars {~E_2~0=v_~E_2~0_30} OutVars{~E_2~0=v_~E_2~0_29} AuxVars[] AssignedVars[~E_2~0] 12864#L709-3 [2114] L709-3-->L714-3: Formula: (and (= v_~E_3~0_29 2) (= 1 v_~E_3~0_30)) InVars {~E_3~0=v_~E_3~0_30} OutVars{~E_3~0=v_~E_3~0_29} AuxVars[] AssignedVars[~E_3~0] 12865#L714-3 [2573] L714-3-->L719-3: Formula: (and (= v_~E_4~0_29 2) (= 1 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 12950#L719-3 [3680] L719-3-->L724-3: Formula: (> 1 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 12951#L724-3 [2818] L724-3-->L454-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_23} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 13123#L454-1 [2466] L454-1-->L486-1: Formula: (and (= 0 v_~m_st~0_20) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26 1)) InVars {~m_st~0=v_~m_st~0_20} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 12937#L486-1 [3838] L486-1-->L949: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret15, ULTIMATE.start_start_simulation_~tmp~3] 13068#L949 [3688] L949-->L949-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_1) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} AuxVars[] AssignedVars[] 13131#L949-1 [2479] L949-1-->L454-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_1} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 13110#L454-2 [2438] L454-2-->L486-2: Formula: (and (= v_~m_st~0_2 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4 1)) InVars {~m_st~0=v_~m_st~0_2} OutVars{~m_st~0=v_~m_st~0_2, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 12942#L486-2 [3840] L486-2-->L904: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 13039#L904 [2393] L904-->L911: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 13075#L911 [3851] L911-->L930-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_6|, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 12947#L930-1 312.69/160.49 [2019-03-28 12:21:59,724 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.49 [2019-03-28 12:21:59,725 INFO L82 PathProgramCache]: Analyzing trace with hash 2069728613, now seen corresponding path program 1 times 312.69/160.49 [2019-03-28 12:21:59,725 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.49 [2019-03-28 12:21:59,725 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.49 [2019-03-28 12:21:59,726 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:21:59,726 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:21:59,726 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:21:59,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.49 [2019-03-28 12:21:59,750 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.49 [2019-03-28 12:21:59,751 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.49 [2019-03-28 12:21:59,751 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 312.69/160.49 [2019-03-28 12:21:59,751 INFO L799 eck$LassoCheckResult]: stem already infeasible 312.69/160.49 [2019-03-28 12:21:59,752 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.49 [2019-03-28 12:21:59,752 INFO L82 PathProgramCache]: Analyzing trace with hash 61558132, now seen corresponding path program 1 times 312.69/160.49 [2019-03-28 12:21:59,752 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.49 [2019-03-28 12:21:59,752 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.49 [2019-03-28 12:21:59,753 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:21:59,753 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:21:59,753 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:21:59,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.49 [2019-03-28 12:21:59,775 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.49 [2019-03-28 12:21:59,776 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.49 [2019-03-28 12:21:59,776 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 312.69/160.49 [2019-03-28 12:21:59,776 INFO L811 eck$LassoCheckResult]: loop already infeasible 312.69/160.49 [2019-03-28 12:21:59,777 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 312.69/160.49 [2019-03-28 12:21:59,777 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 312.69/160.49 [2019-03-28 12:21:59,777 INFO L87 Difference]: Start difference. First operand 454 states and 930 transitions. cyclomatic complexity: 477 Second operand 3 states. 312.69/160.49 [2019-03-28 12:22:00,441 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.49 [2019-03-28 12:22:00,442 INFO L93 Difference]: Finished difference Result 476 states and 946 transitions. 312.69/160.49 [2019-03-28 12:22:00,442 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 312.69/160.49 [2019-03-28 12:22:00,442 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 476 states and 946 transitions. 312.69/160.49 [2019-03-28 12:22:00,445 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 409 312.69/160.49 [2019-03-28 12:22:00,448 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 476 states to 476 states and 946 transitions. 312.69/160.49 [2019-03-28 12:22:00,448 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 476 312.69/160.49 [2019-03-28 12:22:00,448 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 476 312.69/160.49 [2019-03-28 12:22:00,448 INFO L73 IsDeterministic]: Start isDeterministic. Operand 476 states and 946 transitions. 312.69/160.49 [2019-03-28 12:22:00,449 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.49 [2019-03-28 12:22:00,449 INFO L706 BuchiCegarLoop]: Abstraction has 476 states and 946 transitions. 312.69/160.49 [2019-03-28 12:22:00,450 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 476 states and 946 transitions. 312.69/160.49 [2019-03-28 12:22:00,455 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 476 to 454. 312.69/160.49 [2019-03-28 12:22:00,456 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 454 states. 312.69/160.49 [2019-03-28 12:22:00,457 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 454 states to 454 states and 904 transitions. 312.69/160.49 [2019-03-28 12:22:00,457 INFO L729 BuchiCegarLoop]: Abstraction has 454 states and 904 transitions. 312.69/160.49 [2019-03-28 12:22:00,457 INFO L609 BuchiCegarLoop]: Abstraction has 454 states and 904 transitions. 312.69/160.49 [2019-03-28 12:22:00,457 INFO L442 BuchiCegarLoop]: ======== Iteration 16============ 312.69/160.49 [2019-03-28 12:22:00,457 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 454 states and 904 transitions. 312.69/160.49 [2019-03-28 12:22:00,459 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 387 312.69/160.49 [2019-03-28 12:22:00,459 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.49 [2019-03-28 12:22:00,459 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.49 [2019-03-28 12:22:00,460 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.49 [2019-03-28 12:22:00,461 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.49 [2019-03-28 12:22:00,462 INFO L794 eck$LassoCheckResult]: Stem: 14162#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 13978#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 13979#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 14041#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 14042#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 13980#L431-1 [2355] L431-1-->L436-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 13981#L436-1 [2735] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 14019#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 14020#L601-1 [3235] L601-1-->L606-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 14023#L606-1 [3236] L606-1-->L611-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 13920#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 13921#L616-1 [3240] L616-1-->L621-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 13804#L621-1 [3242] L621-1-->L626-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 13805#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 13890#L631-1 [3246] L631-1-->L636-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 13891#L636-1 [3248] L636-1-->L641-1: Formula: (> v_~E_2~0_4 0) InVars {~E_2~0=v_~E_2~0_4} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[] 14061#L641-1 [2474] L641-1-->L646-1: Formula: (and (= v_~E_3~0_3 0) (= v_~E_3~0_2 1)) InVars {~E_3~0=v_~E_3~0_3} OutVars{~E_3~0=v_~E_3~0_2} AuxVars[] AssignedVars[~E_3~0] 14062#L646-1 [2935] L646-1-->L651-1: Formula: (and (= v_~E_4~0_2 1) (= v_~E_4~0_3 0)) InVars {~E_4~0=v_~E_4~0_3} OutVars{~E_4~0=v_~E_4~0_2} AuxVars[] AssignedVars[~E_4~0] 14011#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 14012#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 14222#L294 [2854] L294-->L295: Formula: (= v_~m_pc~0_2 1) InVars {~m_pc~0=v_~m_pc~0_2} OutVars{~m_pc~0=v_~m_pc~0_2} AuxVars[] AssignedVars[] 14135#L295 [2595] L295-->L305: Formula: (and (= v_~E_M~0_5 1) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_4 1)) InVars {~E_M~0=v_~E_M~0_5} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_4, ~E_M~0=v_~E_M~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 14136#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 14241#L745 [3261] L745-->L745-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_5) (= v_~m_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} OutVars{~m_st~0=v_~m_st~0_6, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} AuxVars[] AssignedVars[~m_st~0] 14246#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 13961#L313 [3263] L313-->L313-2: Formula: (> v_~t1_pc~0_3 1) InVars {~t1_pc~0=v_~t1_pc~0_3} OutVars{~t1_pc~0=v_~t1_pc~0_3} AuxVars[] AssignedVars[] 13914#L313-2 [2314] L313-2-->L324: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 13960#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 13819#L753 [3267] L753-->L753-2: Formula: (and (> 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_5) (= v_~t1_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_5, ~t1_st~0=v_~t1_st~0_6} AuxVars[] AssignedVars[~t1_st~0] 13820#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 13824#L332 [3269] L332-->L332-2: Formula: (> v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 13988#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 13986#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 13987#L761 [3273] L761-->L761-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_5) (= v_~t2_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5, ~t2_st~0=v_~t2_st~0_6} AuxVars[] AssignedVars[~t2_st~0] 14007#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 14008#L351 [2567] L351-->L352: Formula: (= 1 v_~t3_pc~0_2) InVars {~t3_pc~0=v_~t3_pc~0_2} OutVars{~t3_pc~0=v_~t3_pc~0_2} AuxVars[] AssignedVars[] 14124#L352 [2655] L352-->L362: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_4 1) (= v_~E_3~0_5 1)) InVars {~E_3~0=v_~E_3~0_5} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_4, ~E_3~0=v_~E_3~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 14106#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 14123#L769 [3279] L769-->L769-2: Formula: (and (= v_~t3_st~0_6 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_5)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} OutVars{~t3_st~0=v_~t3_st~0_6, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} AuxVars[] AssignedVars[~t3_st~0] 14127#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 14128#L370 [3281] L370-->L370-2: Formula: (> v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 14211#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 14207#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 14208#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 14221#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 13881#L389 [2193] L389-->L390: Formula: (= 1 v_~t5_pc~0_2) InVars {~t5_pc~0=v_~t5_pc~0_2} OutVars{~t5_pc~0=v_~t5_pc~0_2} AuxVars[] AssignedVars[] 13882#L390 [2343] L390-->L400: Formula: (and (= v_~E_5~0_5 1) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4 1)) InVars {~E_5~0=v_~E_5~0_5} OutVars{~E_5~0=v_~E_5~0_5, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 13851#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 13877#L785 [3291] L785-->L785-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_5) (= v_~t5_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} OutVars{~t5_st~0=v_~t5_st~0_6, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} AuxVars[] AssignedVars[~t5_st~0] 13897#L785-2 [3293] L785-2-->L669-1: Formula: (> 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 13899#L669-1 [3294] L669-1-->L674-1: Formula: (< 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 14059#L674-1 [3296] L674-1-->L679-1: Formula: (< 1 v_~T2_E~0_7) InVars {~T2_E~0=v_~T2_E~0_7} OutVars{~T2_E~0=v_~T2_E~0_7} AuxVars[] AssignedVars[] 14060#L679-1 [3299] L679-1-->L684-1: Formula: (< v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 14009#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 14010#L689-1 [3302] L689-1-->L694-1: Formula: (> v_~T5_E~0_7 1) InVars {~T5_E~0=v_~T5_E~0_7} OutVars{~T5_E~0=v_~T5_E~0_7} AuxVars[] AssignedVars[] 14156#L694-1 [3305] L694-1-->L699-1: Formula: (< v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 13942#L699-1 [3306] L699-1-->L704-1: Formula: (> v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 13943#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 13793#L709-1 [3311] L709-1-->L714-1: Formula: (< v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 13794#L714-1 [2569] L714-1-->L719-1: Formula: (and (= v_~E_4~0_8 1) (= v_~E_4~0_7 2)) InVars {~E_4~0=v_~E_4~0_8} OutVars{~E_4~0=v_~E_4~0_7} AuxVars[] AssignedVars[~E_4~0] 13884#L719-1 [2198] L719-1-->L930-1: Formula: (and (= v_~E_5~0_8 1) (= v_~E_5~0_7 2)) InVars {~E_5~0=v_~E_5~0_8} OutVars{~E_5~0=v_~E_5~0_7} AuxVars[] AssignedVars[~E_5~0] 13885#L930-1 312.69/160.49 [2019-03-28 12:22:00,463 INFO L796 eck$LassoCheckResult]: Loop: 13885#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 13892#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 13893#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 13872#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 13932#L501 [3784] L501-->L601-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 13933#L601-2 [2768] L601-2-->L601-4: Formula: (and (= v_~M_E~0_8 1) (= 0 v_~M_E~0_9)) InVars {~M_E~0=v_~M_E~0_9} OutVars{~M_E~0=v_~M_E~0_8} AuxVars[] AssignedVars[~M_E~0] 14220#L601-4 [3322] L601-4-->L606-3: Formula: (> v_~T1_E~0_10 0) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 14026#L606-3 [3326] L606-3-->L611-3: Formula: (< 0 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 13930#L611-3 [2256] L611-3-->L616-3: Formula: (and (= v_~T3_E~0_8 1) (= v_~T3_E~0_9 0)) InVars {~T3_E~0=v_~T3_E~0_9} OutVars{~T3_E~0=v_~T3_E~0_8} AuxVars[] AssignedVars[~T3_E~0] 13931#L616-3 [3339] L616-3-->L621-3: Formula: (> v_~T4_E~0_10 0) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 13810#L621-3 [3346] L621-3-->L626-3: Formula: (< 0 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 13811#L626-3 [2580] L626-3-->L631-3: Formula: (and (= v_~E_M~0_24 1) (= 0 v_~E_M~0_25)) InVars {~E_M~0=v_~E_M~0_25} OutVars{~E_M~0=v_~E_M~0_24} AuxVars[] AssignedVars[~E_M~0] 13866#L631-3 [3365] L631-3-->L636-3: Formula: (< 0 v_~E_1~0_26) InVars {~E_1~0=v_~E_1~0_26} OutVars{~E_1~0=v_~E_1~0_26} AuxVars[] AssignedVars[] 13867#L636-3 [3376] L636-3-->L641-3: Formula: (< 0 v_~E_2~0_26) InVars {~E_2~0=v_~E_2~0_26} OutVars{~E_2~0=v_~E_2~0_26} AuxVars[] AssignedVars[] 14051#L641-3 [2455] L641-3-->L646-3: Formula: (and (= 0 v_~E_3~0_25) (= v_~E_3~0_24 1)) InVars {~E_3~0=v_~E_3~0_25} OutVars{~E_3~0=v_~E_3~0_24} AuxVars[] AssignedVars[~E_3~0] 14052#L646-3 [2912] L646-3-->L651-3: Formula: (and (= 0 v_~E_4~0_25) (= v_~E_4~0_24 1)) InVars {~E_4~0=v_~E_4~0_25} OutVars{~E_4~0=v_~E_4~0_24} AuxVars[] AssignedVars[~E_4~0] 14002#L651-3 [3410] L651-3-->L656-3: Formula: (> 0 v_~E_5~0_26) InVars {~E_5~0=v_~E_5~0_26} OutVars{~E_5~0=v_~E_5~0_26} AuxVars[] AssignedVars[] 14003#L656-3 [2767] L656-3-->L294-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_37, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_37, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_22|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_22|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_22|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_37, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_37, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_22|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_22|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_22|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_22|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_37, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_37, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_37} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 14219#L294-21 [2808] L294-21-->L295-7: Formula: (= v_~m_pc~0_21 1) InVars {~m_pc~0=v_~m_pc~0_21} OutVars{~m_pc~0=v_~m_pc~0_21} AuxVars[] AssignedVars[] 14141#L295-7 [2602] L295-7-->L305-7: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_40 1) (= 1 v_~E_M~0_27)) InVars {~E_M~0=v_~E_M~0_27} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_40, ~E_M~0=v_~E_M~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 14142#L305-7 [3806] L305-7-->L745-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 14225#L745-21 [2835] L745-21-->L745-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_42) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} AuxVars[] AssignedVars[] 14226#L745-23 [2838] L745-23-->L313-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_43, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 13915#L313-21 [3468] L313-21-->L313-23: Formula: (> v_~t1_pc~0_22 1) InVars {~t1_pc~0=v_~t1_pc~0_22} OutVars{~t1_pc~0=v_~t1_pc~0_22} AuxVars[] AssignedVars[] 13917#L313-23 [2249] L313-23-->L324-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 13922#L324-7 [3813] L324-7-->L753-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 13955#L753-21 [2292] L753-21-->L753-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} AuxVars[] AssignedVars[] 13956#L753-23 [2297] L753-23-->L332-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_22|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 13959#L332-21 [3510] L332-21-->L332-23: Formula: (> 1 v_~t2_pc~0_22) InVars {~t2_pc~0=v_~t2_pc~0_22} OutVars{~t2_pc~0=v_~t2_pc~0_22} AuxVars[] AssignedVars[] 14038#L332-23 [2476] L332-23-->L343-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 14063#L343-7 [3820] L343-7-->L761-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 14071#L761-21 [3538] L761-21-->L761-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___1~0_41 0) (= v_~t2_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41, ~t2_st~0=v_~t2_st~0_19} AuxVars[] AssignedVars[~t2_st~0] 14072#L761-23 [2493] L761-23-->L351-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_22|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 14073#L351-21 [2679] L351-21-->L352-7: Formula: (= v_~t3_pc~0_21 1) InVars {~t3_pc~0=v_~t3_pc~0_21} OutVars{~t3_pc~0=v_~t3_pc~0_21} AuxVars[] AssignedVars[] 14158#L352-7 [2622] L352-7-->L362-7: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_46 1) (= 1 v_~E_3~0_27)) InVars {~E_3~0=v_~E_3~0_27} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_46, ~E_3~0=v_~E_3~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 14089#L362-7 [3827] L362-7-->L769-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 14090#L769-21 [2534] L769-21-->L769-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} AuxVars[] AssignedVars[] 14096#L769-23 [2537] L769-23-->L370-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_43, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 14099#L370-21 [2927] L370-21-->L371-7: Formula: (= 1 v_~t4_pc~0_21) InVars {~t4_pc~0=v_~t4_pc~0_21} OutVars{~t4_pc~0=v_~t4_pc~0_21} AuxVars[] AssignedVars[] 14235#L371-7 [2863] L371-7-->L381-7: Formula: (and (= 1 v_~E_4~0_27) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_46 1)) InVars {~E_4~0=v_~E_4~0_27} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_46, ~E_4~0=v_~E_4~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 14201#L381-7 [3834] L381-7-->L777-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 14183#L777-21 [2705] L777-21-->L777-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} AuxVars[] AssignedVars[] 14184#L777-23 [2708] L777-23-->L389-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_22|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 13822#L389-21 [3636] L389-21-->L389-23: Formula: (> v_~t5_pc~0_22 1) InVars {~t5_pc~0=v_~t5_pc~0_22} OutVars{~t5_pc~0=v_~t5_pc~0_22} AuxVars[] AssignedVars[] 13797#L389-23 [2111] L389-23-->L400-7: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 13798#L400-7 [3837] L400-7-->L785-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 13838#L785-21 [3654] L785-21-->L785-23: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_41 0) (= v_~t5_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} OutVars{~t5_st~0=v_~t5_st~0_19, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} AuxVars[] AssignedVars[~t5_st~0] 13846#L785-23 [2161] L785-23-->L669-3: Formula: (and (= v_~M_E~0_12 1) (= v_~M_E~0_11 2)) InVars {~M_E~0=v_~M_E~0_12} OutVars{~M_E~0=v_~M_E~0_11} AuxVars[] AssignedVars[~M_E~0] 13848#L669-3 [3660] L669-3-->L674-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 14064#L674-3 [3662] L674-3-->L679-3: Formula: (< 1 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 14065#L679-3 [3664] L679-3-->L684-3: Formula: (< 1 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 13999#L684-3 [3666] L684-3-->L689-3: Formula: (> v_~T4_E~0_13 1) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 14000#L689-3 [3668] L689-3-->L694-3: Formula: (< 1 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 14022#L694-3 [2405] L694-3-->L699-3: Formula: (and (= 1 v_~E_M~0_30) (= v_~E_M~0_29 2)) InVars {~E_M~0=v_~E_M~0_30} OutVars{~E_M~0=v_~E_M~0_29} AuxVars[] AssignedVars[~E_M~0] 13918#L699-3 [3673] L699-3-->L704-3: Formula: (< 1 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 13919#L704-3 [3675] L704-3-->L709-3: Formula: (< 1 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 13802#L709-3 [2114] L709-3-->L714-3: Formula: (and (= v_~E_3~0_29 2) (= 1 v_~E_3~0_30)) InVars {~E_3~0=v_~E_3~0_30} OutVars{~E_3~0=v_~E_3~0_29} AuxVars[] AssignedVars[~E_3~0] 13803#L714-3 [2573] L714-3-->L719-3: Formula: (and (= v_~E_4~0_29 2) (= 1 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 13888#L719-3 [3680] L719-3-->L724-3: Formula: (> 1 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 13889#L724-3 [2818] L724-3-->L454-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_23} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 14056#L454-1 [2466] L454-1-->L486-1: Formula: (and (= 0 v_~m_st~0_20) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26 1)) InVars {~m_st~0=v_~m_st~0_20} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 13875#L486-1 [3838] L486-1-->L949: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret15, ULTIMATE.start_start_simulation_~tmp~3] 14006#L949 [3688] L949-->L949-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_1) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} AuxVars[] AssignedVars[] 14066#L949-1 [2479] L949-1-->L454-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_1} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 14043#L454-2 [2438] L454-2-->L486-2: Formula: (and (= v_~m_st~0_2 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4 1)) InVars {~m_st~0=v_~m_st~0_2} OutVars{~m_st~0=v_~m_st~0_2, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 13880#L486-2 [3840] L486-2-->L904: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 13977#L904 [2393] L904-->L911: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 14013#L911 [3851] L911-->L930-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_6|, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 13885#L930-1 312.69/160.49 [2019-03-28 12:22:00,463 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.49 [2019-03-28 12:22:00,463 INFO L82 PathProgramCache]: Analyzing trace with hash 1219879128, now seen corresponding path program 1 times 312.69/160.49 [2019-03-28 12:22:00,463 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.49 [2019-03-28 12:22:00,464 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.49 [2019-03-28 12:22:00,464 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:00,465 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:00,465 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:00,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.49 [2019-03-28 12:22:00,488 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.49 [2019-03-28 12:22:00,488 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.49 [2019-03-28 12:22:00,488 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 312.69/160.49 [2019-03-28 12:22:00,489 INFO L799 eck$LassoCheckResult]: stem already infeasible 312.69/160.49 [2019-03-28 12:22:00,489 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.49 [2019-03-28 12:22:00,489 INFO L82 PathProgramCache]: Analyzing trace with hash 65289698, now seen corresponding path program 1 times 312.69/160.49 [2019-03-28 12:22:00,489 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.49 [2019-03-28 12:22:00,489 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.49 [2019-03-28 12:22:00,490 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:00,490 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:00,491 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:00,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.49 [2019-03-28 12:22:00,513 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.49 [2019-03-28 12:22:00,513 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.49 [2019-03-28 12:22:00,513 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 312.69/160.49 [2019-03-28 12:22:00,514 INFO L811 eck$LassoCheckResult]: loop already infeasible 312.69/160.49 [2019-03-28 12:22:00,514 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 312.69/160.49 [2019-03-28 12:22:00,514 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 312.69/160.49 [2019-03-28 12:22:00,514 INFO L87 Difference]: Start difference. First operand 454 states and 904 transitions. cyclomatic complexity: 451 Second operand 3 states. 312.69/160.49 [2019-03-28 12:22:01,009 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.49 [2019-03-28 12:22:01,009 INFO L93 Difference]: Finished difference Result 470 states and 908 transitions. 312.69/160.49 [2019-03-28 12:22:01,009 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 312.69/160.49 [2019-03-28 12:22:01,010 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 470 states and 908 transitions. 312.69/160.49 [2019-03-28 12:22:01,013 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 403 312.69/160.49 [2019-03-28 12:22:01,015 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 470 states to 470 states and 908 transitions. 312.69/160.49 [2019-03-28 12:22:01,016 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 470 312.69/160.49 [2019-03-28 12:22:01,016 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 470 312.69/160.49 [2019-03-28 12:22:01,016 INFO L73 IsDeterministic]: Start isDeterministic. Operand 470 states and 908 transitions. 312.69/160.49 [2019-03-28 12:22:01,017 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.49 [2019-03-28 12:22:01,017 INFO L706 BuchiCegarLoop]: Abstraction has 470 states and 908 transitions. 312.69/160.49 [2019-03-28 12:22:01,018 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 470 states and 908 transitions. 312.69/160.49 [2019-03-28 12:22:01,023 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 470 to 454. 312.69/160.49 [2019-03-28 12:22:01,024 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 454 states. 312.69/160.49 [2019-03-28 12:22:01,025 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 454 states to 454 states and 878 transitions. 312.69/160.49 [2019-03-28 12:22:01,025 INFO L729 BuchiCegarLoop]: Abstraction has 454 states and 878 transitions. 312.69/160.49 [2019-03-28 12:22:01,025 INFO L609 BuchiCegarLoop]: Abstraction has 454 states and 878 transitions. 312.69/160.49 [2019-03-28 12:22:01,025 INFO L442 BuchiCegarLoop]: ======== Iteration 17============ 312.69/160.49 [2019-03-28 12:22:01,025 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 454 states and 878 transitions. 312.69/160.49 [2019-03-28 12:22:01,027 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 387 312.69/160.49 [2019-03-28 12:22:01,027 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.49 [2019-03-28 12:22:01,028 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.49 [2019-03-28 12:22:01,028 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.49 [2019-03-28 12:22:01,029 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.49 [2019-03-28 12:22:01,030 INFO L794 eck$LassoCheckResult]: Stem: 15094#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 14910#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 14911#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 14975#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 14976#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 14914#L431-1 [2355] L431-1-->L436-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 14915#L436-1 [2735] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 14952#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 14953#L601-1 [3235] L601-1-->L606-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 14955#L606-1 [3236] L606-1-->L611-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 14853#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 14854#L616-1 [3240] L616-1-->L621-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 14737#L621-1 [3242] L621-1-->L626-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 14738#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 14822#L631-1 [3246] L631-1-->L636-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 14823#L636-1 [3248] L636-1-->L641-1: Formula: (> v_~E_2~0_4 0) InVars {~E_2~0=v_~E_2~0_4} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[] 14993#L641-1 [3251] L641-1-->L646-1: Formula: (> v_~E_3~0_4 0) InVars {~E_3~0=v_~E_3~0_4} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[] 14994#L646-1 [2935] L646-1-->L651-1: Formula: (and (= v_~E_4~0_2 1) (= v_~E_4~0_3 0)) InVars {~E_4~0=v_~E_4~0_3} OutVars{~E_4~0=v_~E_4~0_2} AuxVars[] AssignedVars[~E_4~0] 14943#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 14944#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 15154#L294 [2854] L294-->L295: Formula: (= v_~m_pc~0_2 1) InVars {~m_pc~0=v_~m_pc~0_2} OutVars{~m_pc~0=v_~m_pc~0_2} AuxVars[] AssignedVars[] 15067#L295 [2595] L295-->L305: Formula: (and (= v_~E_M~0_5 1) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_4 1)) InVars {~E_M~0=v_~E_M~0_5} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_4, ~E_M~0=v_~E_M~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 15068#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 15173#L745 [3261] L745-->L745-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_5) (= v_~m_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} OutVars{~m_st~0=v_~m_st~0_6, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} AuxVars[] AssignedVars[~m_st~0] 15178#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 14893#L313 [3263] L313-->L313-2: Formula: (> v_~t1_pc~0_3 1) InVars {~t1_pc~0=v_~t1_pc~0_3} OutVars{~t1_pc~0=v_~t1_pc~0_3} AuxVars[] AssignedVars[] 14846#L313-2 [2314] L313-2-->L324: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 14892#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 14752#L753 [3267] L753-->L753-2: Formula: (and (> 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_5) (= v_~t1_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_5, ~t1_st~0=v_~t1_st~0_6} AuxVars[] AssignedVars[~t1_st~0] 14753#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 14756#L332 [3269] L332-->L332-2: Formula: (> v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 14920#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 14918#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 14919#L761 [3273] L761-->L761-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_5) (= v_~t2_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5, ~t2_st~0=v_~t2_st~0_6} AuxVars[] AssignedVars[~t2_st~0] 14939#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 14940#L351 [3275] L351-->L351-2: Formula: (< 1 v_~t3_pc~0_3) InVars {~t3_pc~0=v_~t3_pc~0_3} OutVars{~t3_pc~0=v_~t3_pc~0_3} AuxVars[] AssignedVars[] 15037#L351-2 [2543] L351-2-->L362: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 15038#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 15055#L769 [3279] L769-->L769-2: Formula: (and (= v_~t3_st~0_6 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_5)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} OutVars{~t3_st~0=v_~t3_st~0_6, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} AuxVars[] AssignedVars[~t3_st~0] 15059#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 15060#L370 [3281] L370-->L370-2: Formula: (> v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 15143#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 15141#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 15142#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 15153#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 14813#L389 [2193] L389-->L390: Formula: (= 1 v_~t5_pc~0_2) InVars {~t5_pc~0=v_~t5_pc~0_2} OutVars{~t5_pc~0=v_~t5_pc~0_2} AuxVars[] AssignedVars[] 14814#L390 [2343] L390-->L400: Formula: (and (= v_~E_5~0_5 1) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4 1)) InVars {~E_5~0=v_~E_5~0_5} OutVars{~E_5~0=v_~E_5~0_5, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 14785#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 14812#L785 [3291] L785-->L785-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_5) (= v_~t5_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} OutVars{~t5_st~0=v_~t5_st~0_6, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} AuxVars[] AssignedVars[~t5_st~0] 14830#L785-2 [3293] L785-2-->L669-1: Formula: (> 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 14831#L669-1 [3294] L669-1-->L674-1: Formula: (< 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 14991#L674-1 [3296] L674-1-->L679-1: Formula: (< 1 v_~T2_E~0_7) InVars {~T2_E~0=v_~T2_E~0_7} OutVars{~T2_E~0=v_~T2_E~0_7} AuxVars[] AssignedVars[] 14992#L679-1 [3299] L679-1-->L684-1: Formula: (< v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 14941#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 14942#L689-1 [3302] L689-1-->L694-1: Formula: (> v_~T5_E~0_7 1) InVars {~T5_E~0=v_~T5_E~0_7} OutVars{~T5_E~0=v_~T5_E~0_7} AuxVars[] AssignedVars[] 15088#L694-1 [3305] L694-1-->L699-1: Formula: (< v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 14874#L699-1 [3306] L699-1-->L704-1: Formula: (> v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 14875#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 14725#L709-1 [3310] L709-1-->L714-1: Formula: (> v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 14726#L714-1 [2569] L714-1-->L719-1: Formula: (and (= v_~E_4~0_8 1) (= v_~E_4~0_7 2)) InVars {~E_4~0=v_~E_4~0_8} OutVars{~E_4~0=v_~E_4~0_7} AuxVars[] AssignedVars[~E_4~0] 14817#L719-1 [2198] L719-1-->L930-1: Formula: (and (= v_~E_5~0_8 1) (= v_~E_5~0_7 2)) InVars {~E_5~0=v_~E_5~0_8} OutVars{~E_5~0=v_~E_5~0_7} AuxVars[] AssignedVars[~E_5~0] 14818#L930-1 312.69/160.49 [2019-03-28 12:22:01,031 INFO L796 eck$LassoCheckResult]: Loop: 14818#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 14824#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 14825#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 14804#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 14864#L501 [3784] L501-->L601-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 14865#L601-2 [2768] L601-2-->L601-4: Formula: (and (= v_~M_E~0_8 1) (= 0 v_~M_E~0_9)) InVars {~M_E~0=v_~M_E~0_9} OutVars{~M_E~0=v_~M_E~0_8} AuxVars[] AssignedVars[~M_E~0] 15152#L601-4 [3322] L601-4-->L606-3: Formula: (> v_~T1_E~0_10 0) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 14958#L606-3 [3326] L606-3-->L611-3: Formula: (< 0 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 14862#L611-3 [2256] L611-3-->L616-3: Formula: (and (= v_~T3_E~0_8 1) (= v_~T3_E~0_9 0)) InVars {~T3_E~0=v_~T3_E~0_9} OutVars{~T3_E~0=v_~T3_E~0_8} AuxVars[] AssignedVars[~T3_E~0] 14863#L616-3 [3339] L616-3-->L621-3: Formula: (> v_~T4_E~0_10 0) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 14742#L621-3 [3346] L621-3-->L626-3: Formula: (< 0 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 14743#L626-3 [2580] L626-3-->L631-3: Formula: (and (= v_~E_M~0_24 1) (= 0 v_~E_M~0_25)) InVars {~E_M~0=v_~E_M~0_25} OutVars{~E_M~0=v_~E_M~0_24} AuxVars[] AssignedVars[~E_M~0] 14798#L631-3 [3365] L631-3-->L636-3: Formula: (< 0 v_~E_1~0_26) InVars {~E_1~0=v_~E_1~0_26} OutVars{~E_1~0=v_~E_1~0_26} AuxVars[] AssignedVars[] 14799#L636-3 [3376] L636-3-->L641-3: Formula: (< 0 v_~E_2~0_26) InVars {~E_2~0=v_~E_2~0_26} OutVars{~E_2~0=v_~E_2~0_26} AuxVars[] AssignedVars[] 14983#L641-3 [3388] L641-3-->L646-3: Formula: (< 0 v_~E_3~0_26) InVars {~E_3~0=v_~E_3~0_26} OutVars{~E_3~0=v_~E_3~0_26} AuxVars[] AssignedVars[] 14984#L646-3 [2912] L646-3-->L651-3: Formula: (and (= 0 v_~E_4~0_25) (= v_~E_4~0_24 1)) InVars {~E_4~0=v_~E_4~0_25} OutVars{~E_4~0=v_~E_4~0_24} AuxVars[] AssignedVars[~E_4~0] 14934#L651-3 [3410] L651-3-->L656-3: Formula: (> 0 v_~E_5~0_26) InVars {~E_5~0=v_~E_5~0_26} OutVars{~E_5~0=v_~E_5~0_26} AuxVars[] AssignedVars[] 14935#L656-3 [2767] L656-3-->L294-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_37, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_37, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_22|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_22|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_22|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_37, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_37, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_22|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_22|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_22|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_22|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_37, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_37, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_37} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 15151#L294-21 [2808] L294-21-->L295-7: Formula: (= v_~m_pc~0_21 1) InVars {~m_pc~0=v_~m_pc~0_21} OutVars{~m_pc~0=v_~m_pc~0_21} AuxVars[] AssignedVars[] 15073#L295-7 [2602] L295-7-->L305-7: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_40 1) (= 1 v_~E_M~0_27)) InVars {~E_M~0=v_~E_M~0_27} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_40, ~E_M~0=v_~E_M~0_27} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 15074#L305-7 [3806] L305-7-->L745-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 15157#L745-21 [2835] L745-21-->L745-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_42) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} AuxVars[] AssignedVars[] 15158#L745-23 [2838] L745-23-->L313-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_43, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 14847#L313-21 [3468] L313-21-->L313-23: Formula: (> v_~t1_pc~0_22 1) InVars {~t1_pc~0=v_~t1_pc~0_22} OutVars{~t1_pc~0=v_~t1_pc~0_22} AuxVars[] AssignedVars[] 14849#L313-23 [2249] L313-23-->L324-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 14852#L324-7 [3813] L324-7-->L753-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 14887#L753-21 [2292] L753-21-->L753-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} AuxVars[] AssignedVars[] 14888#L753-23 [2297] L753-23-->L332-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_22|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 14891#L332-21 [3510] L332-21-->L332-23: Formula: (> 1 v_~t2_pc~0_22) InVars {~t2_pc~0=v_~t2_pc~0_22} OutVars{~t2_pc~0=v_~t2_pc~0_22} AuxVars[] AssignedVars[] 14970#L332-23 [2476] L332-23-->L343-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 14995#L343-7 [3820] L343-7-->L761-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 15003#L761-21 [3538] L761-21-->L761-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___1~0_41 0) (= v_~t2_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41, ~t2_st~0=v_~t2_st~0_19} AuxVars[] AssignedVars[~t2_st~0] 15004#L761-23 [2493] L761-23-->L351-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_22|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 15005#L351-21 [3552] L351-21-->L351-23: Formula: (< v_~t3_pc~0_22 1) InVars {~t3_pc~0=v_~t3_pc~0_22} OutVars{~t3_pc~0=v_~t3_pc~0_22} AuxVars[] AssignedVars[] 15091#L351-23 [2660] L351-23-->L362-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 15021#L362-7 [3827] L362-7-->L769-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 15022#L769-21 [2534] L769-21-->L769-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} AuxVars[] AssignedVars[] 15028#L769-23 [2537] L769-23-->L370-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_43, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 15031#L370-21 [3594] L370-21-->L370-23: Formula: (< 1 v_~t4_pc~0_22) InVars {~t4_pc~0=v_~t4_pc~0_22} OutVars{~t4_pc~0=v_~t4_pc~0_22} AuxVars[] AssignedVars[] 15168#L370-23 [2934] L370-23-->L381-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 15133#L381-7 [3834] L381-7-->L777-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 15115#L777-21 [2705] L777-21-->L777-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} AuxVars[] AssignedVars[] 15116#L777-23 [2708] L777-23-->L389-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_22|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 14754#L389-21 [2132] L389-21-->L390-7: Formula: (= v_~t5_pc~0_21 1) InVars {~t5_pc~0=v_~t5_pc~0_21} OutVars{~t5_pc~0=v_~t5_pc~0_21} AuxVars[] AssignedVars[] 14755#L390-7 [2330] L390-7-->L400-7: Formula: (and (= 1 v_~E_5~0_27) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46 1)) InVars {~E_5~0=v_~E_5~0_27} OutVars{~E_5~0=v_~E_5~0_27, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 14730#L400-7 [3837] L400-7-->L785-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 14770#L785-21 [3654] L785-21-->L785-23: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_41 0) (= v_~t5_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} OutVars{~t5_st~0=v_~t5_st~0_19, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} AuxVars[] AssignedVars[~t5_st~0] 14778#L785-23 [2161] L785-23-->L669-3: Formula: (and (= v_~M_E~0_12 1) (= v_~M_E~0_11 2)) InVars {~M_E~0=v_~M_E~0_12} OutVars{~M_E~0=v_~M_E~0_11} AuxVars[] AssignedVars[~M_E~0] 14780#L669-3 [3660] L669-3-->L674-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 14996#L674-3 [3662] L674-3-->L679-3: Formula: (< 1 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 14997#L679-3 [3664] L679-3-->L684-3: Formula: (< 1 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 14931#L684-3 [3666] L684-3-->L689-3: Formula: (> v_~T4_E~0_13 1) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 14932#L689-3 [3668] L689-3-->L694-3: Formula: (< 1 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 14954#L694-3 [2405] L694-3-->L699-3: Formula: (and (= 1 v_~E_M~0_30) (= v_~E_M~0_29 2)) InVars {~E_M~0=v_~E_M~0_30} OutVars{~E_M~0=v_~E_M~0_29} AuxVars[] AssignedVars[~E_M~0] 14850#L699-3 [3673] L699-3-->L704-3: Formula: (< 1 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 14851#L704-3 [3675] L704-3-->L709-3: Formula: (< 1 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 14734#L709-3 [3677] L709-3-->L714-3: Formula: (< 1 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 14735#L714-3 [2573] L714-3-->L719-3: Formula: (and (= v_~E_4~0_29 2) (= 1 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 14820#L719-3 [3680] L719-3-->L724-3: Formula: (> 1 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 14821#L724-3 [2818] L724-3-->L454-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_23} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 14988#L454-1 [2466] L454-1-->L486-1: Formula: (and (= 0 v_~m_st~0_20) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26 1)) InVars {~m_st~0=v_~m_st~0_20} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 14807#L486-1 [3838] L486-1-->L949: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret15, ULTIMATE.start_start_simulation_~tmp~3] 14938#L949 [3688] L949-->L949-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_1) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} AuxVars[] AssignedVars[] 14998#L949-1 [2479] L949-1-->L454-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_1} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 14973#L454-2 [2438] L454-2-->L486-2: Formula: (and (= v_~m_st~0_2 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4 1)) InVars {~m_st~0=v_~m_st~0_2} OutVars{~m_st~0=v_~m_st~0_2, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 14811#L486-2 [3840] L486-2-->L904: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 14909#L904 [2393] L904-->L911: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 14945#L911 [3851] L911-->L930-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_6|, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 14818#L930-1 312.69/160.49 [2019-03-28 12:22:01,031 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.49 [2019-03-28 12:22:01,031 INFO L82 PathProgramCache]: Analyzing trace with hash -494114836, now seen corresponding path program 1 times 312.69/160.49 [2019-03-28 12:22:01,031 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.49 [2019-03-28 12:22:01,032 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.49 [2019-03-28 12:22:01,032 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:01,033 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:01,033 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:01,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.49 [2019-03-28 12:22:01,053 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.49 [2019-03-28 12:22:01,053 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.49 [2019-03-28 12:22:01,053 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 312.69/160.49 [2019-03-28 12:22:01,053 INFO L799 eck$LassoCheckResult]: stem already infeasible 312.69/160.49 [2019-03-28 12:22:01,054 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.49 [2019-03-28 12:22:01,054 INFO L82 PathProgramCache]: Analyzing trace with hash 539935254, now seen corresponding path program 1 times 312.69/160.49 [2019-03-28 12:22:01,054 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.49 [2019-03-28 12:22:01,054 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.49 [2019-03-28 12:22:01,055 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:01,055 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:01,055 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:01,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.49 [2019-03-28 12:22:01,077 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.49 [2019-03-28 12:22:01,078 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.49 [2019-03-28 12:22:01,078 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 312.69/160.49 [2019-03-28 12:22:01,078 INFO L811 eck$LassoCheckResult]: loop already infeasible 312.69/160.49 [2019-03-28 12:22:01,078 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 312.69/160.49 [2019-03-28 12:22:01,078 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 312.69/160.49 [2019-03-28 12:22:01,079 INFO L87 Difference]: Start difference. First operand 454 states and 878 transitions. cyclomatic complexity: 425 Second operand 3 states. 312.69/160.49 [2019-03-28 12:22:01,566 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.49 [2019-03-28 12:22:01,566 INFO L93 Difference]: Finished difference Result 464 states and 870 transitions. 312.69/160.49 [2019-03-28 12:22:01,567 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 312.69/160.49 [2019-03-28 12:22:01,567 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 464 states and 870 transitions. 312.69/160.49 [2019-03-28 12:22:01,570 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 397 312.69/160.49 [2019-03-28 12:22:01,572 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 464 states to 464 states and 870 transitions. 312.69/160.49 [2019-03-28 12:22:01,573 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 464 312.69/160.49 [2019-03-28 12:22:01,573 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 464 312.69/160.49 [2019-03-28 12:22:01,573 INFO L73 IsDeterministic]: Start isDeterministic. Operand 464 states and 870 transitions. 312.69/160.49 [2019-03-28 12:22:01,574 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.49 [2019-03-28 12:22:01,574 INFO L706 BuchiCegarLoop]: Abstraction has 464 states and 870 transitions. 312.69/160.49 [2019-03-28 12:22:01,575 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 464 states and 870 transitions. 312.69/160.49 [2019-03-28 12:22:01,579 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 464 to 454. 312.69/160.49 [2019-03-28 12:22:01,580 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 454 states. 312.69/160.49 [2019-03-28 12:22:01,581 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 454 states to 454 states and 852 transitions. 312.69/160.49 [2019-03-28 12:22:01,581 INFO L729 BuchiCegarLoop]: Abstraction has 454 states and 852 transitions. 312.69/160.49 [2019-03-28 12:22:01,581 INFO L609 BuchiCegarLoop]: Abstraction has 454 states and 852 transitions. 312.69/160.49 [2019-03-28 12:22:01,581 INFO L442 BuchiCegarLoop]: ======== Iteration 18============ 312.69/160.49 [2019-03-28 12:22:01,581 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 454 states and 852 transitions. 312.69/160.49 [2019-03-28 12:22:01,583 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 387 312.69/160.49 [2019-03-28 12:22:01,583 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.49 [2019-03-28 12:22:01,583 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.49 [2019-03-28 12:22:01,584 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.49 [2019-03-28 12:22:01,584 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.49 [2019-03-28 12:22:01,585 INFO L794 eck$LassoCheckResult]: Stem: 16020#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 15836#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 15837#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 15901#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 15902#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 15840#L431-1 [2355] L431-1-->L436-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 15841#L436-1 [2735] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 15878#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 15879#L601-1 [3235] L601-1-->L606-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 15881#L606-1 [3236] L606-1-->L611-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 15779#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 15780#L616-1 [3240] L616-1-->L621-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 15663#L621-1 [3242] L621-1-->L626-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 15664#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 15748#L631-1 [3246] L631-1-->L636-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 15749#L636-1 [3248] L636-1-->L641-1: Formula: (> v_~E_2~0_4 0) InVars {~E_2~0=v_~E_2~0_4} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[] 15919#L641-1 [3251] L641-1-->L646-1: Formula: (> v_~E_3~0_4 0) InVars {~E_3~0=v_~E_3~0_4} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[] 15920#L646-1 [3253] L646-1-->L651-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 15869#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 15870#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 16080#L294 [2854] L294-->L295: Formula: (= v_~m_pc~0_2 1) InVars {~m_pc~0=v_~m_pc~0_2} OutVars{~m_pc~0=v_~m_pc~0_2} AuxVars[] AssignedVars[] 15993#L295 [2595] L295-->L305: Formula: (and (= v_~E_M~0_5 1) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_4 1)) InVars {~E_M~0=v_~E_M~0_5} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_4, ~E_M~0=v_~E_M~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 15994#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 16099#L745 [3261] L745-->L745-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_5) (= v_~m_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} OutVars{~m_st~0=v_~m_st~0_6, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} AuxVars[] AssignedVars[~m_st~0] 16104#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 15819#L313 [3263] L313-->L313-2: Formula: (> v_~t1_pc~0_3 1) InVars {~t1_pc~0=v_~t1_pc~0_3} OutVars{~t1_pc~0=v_~t1_pc~0_3} AuxVars[] AssignedVars[] 15772#L313-2 [2314] L313-2-->L324: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 15818#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 15678#L753 [3267] L753-->L753-2: Formula: (and (> 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_5) (= v_~t1_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_5, ~t1_st~0=v_~t1_st~0_6} AuxVars[] AssignedVars[~t1_st~0] 15679#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 15682#L332 [3269] L332-->L332-2: Formula: (> v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 15846#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 15844#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 15845#L761 [3273] L761-->L761-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_5) (= v_~t2_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5, ~t2_st~0=v_~t2_st~0_6} AuxVars[] AssignedVars[~t2_st~0] 15865#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 15866#L351 [3275] L351-->L351-2: Formula: (< 1 v_~t3_pc~0_3) InVars {~t3_pc~0=v_~t3_pc~0_3} OutVars{~t3_pc~0=v_~t3_pc~0_3} AuxVars[] AssignedVars[] 15963#L351-2 [2543] L351-2-->L362: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 15964#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 15981#L769 [3279] L769-->L769-2: Formula: (and (= v_~t3_st~0_6 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_5)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} OutVars{~t3_st~0=v_~t3_st~0_6, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} AuxVars[] AssignedVars[~t3_st~0] 15985#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 15986#L370 [3281] L370-->L370-2: Formula: (> v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 16069#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 16066#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 16067#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 16079#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 15739#L389 [2193] L389-->L390: Formula: (= 1 v_~t5_pc~0_2) InVars {~t5_pc~0=v_~t5_pc~0_2} OutVars{~t5_pc~0=v_~t5_pc~0_2} AuxVars[] AssignedVars[] 15740#L390 [2343] L390-->L400: Formula: (and (= v_~E_5~0_5 1) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4 1)) InVars {~E_5~0=v_~E_5~0_5} OutVars{~E_5~0=v_~E_5~0_5, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 15711#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 15738#L785 [3291] L785-->L785-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_5) (= v_~t5_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} OutVars{~t5_st~0=v_~t5_st~0_6, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} AuxVars[] AssignedVars[~t5_st~0] 15756#L785-2 [3293] L785-2-->L669-1: Formula: (> 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 15757#L669-1 [3294] L669-1-->L674-1: Formula: (< 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 15917#L674-1 [3296] L674-1-->L679-1: Formula: (< 1 v_~T2_E~0_7) InVars {~T2_E~0=v_~T2_E~0_7} OutVars{~T2_E~0=v_~T2_E~0_7} AuxVars[] AssignedVars[] 15918#L679-1 [3299] L679-1-->L684-1: Formula: (< v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 15867#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 15868#L689-1 [3302] L689-1-->L694-1: Formula: (> v_~T5_E~0_7 1) InVars {~T5_E~0=v_~T5_E~0_7} OutVars{~T5_E~0=v_~T5_E~0_7} AuxVars[] AssignedVars[] 16014#L694-1 [3305] L694-1-->L699-1: Formula: (< v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 15800#L699-1 [3306] L699-1-->L704-1: Formula: (> v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 15801#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 15651#L709-1 [3310] L709-1-->L714-1: Formula: (> v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 15652#L714-1 [3313] L714-1-->L719-1: Formula: (> v_~E_4~0_9 1) InVars {~E_4~0=v_~E_4~0_9} OutVars{~E_4~0=v_~E_4~0_9} AuxVars[] AssignedVars[] 15743#L719-1 [2198] L719-1-->L930-1: Formula: (and (= v_~E_5~0_8 1) (= v_~E_5~0_7 2)) InVars {~E_5~0=v_~E_5~0_8} OutVars{~E_5~0=v_~E_5~0_7} AuxVars[] AssignedVars[~E_5~0] 15744#L930-1 312.69/160.49 [2019-03-28 12:22:01,586 INFO L796 eck$LassoCheckResult]: Loop: 15744#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 15750#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 15751#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 15730#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 15790#L501 [3784] L501-->L601-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 15791#L601-2 [2768] L601-2-->L601-4: Formula: (and (= v_~M_E~0_8 1) (= 0 v_~M_E~0_9)) InVars {~M_E~0=v_~M_E~0_9} OutVars{~M_E~0=v_~M_E~0_8} AuxVars[] AssignedVars[~M_E~0] 16078#L601-4 [3322] L601-4-->L606-3: Formula: (> v_~T1_E~0_10 0) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 15884#L606-3 [3326] L606-3-->L611-3: Formula: (< 0 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 15788#L611-3 [2256] L611-3-->L616-3: Formula: (and (= v_~T3_E~0_8 1) (= v_~T3_E~0_9 0)) InVars {~T3_E~0=v_~T3_E~0_9} OutVars{~T3_E~0=v_~T3_E~0_8} AuxVars[] AssignedVars[~T3_E~0] 15789#L616-3 [3339] L616-3-->L621-3: Formula: (> v_~T4_E~0_10 0) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 15668#L621-3 [3346] L621-3-->L626-3: Formula: (< 0 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 15669#L626-3 [2580] L626-3-->L631-3: Formula: (and (= v_~E_M~0_24 1) (= 0 v_~E_M~0_25)) InVars {~E_M~0=v_~E_M~0_25} OutVars{~E_M~0=v_~E_M~0_24} AuxVars[] AssignedVars[~E_M~0] 15724#L631-3 [3365] L631-3-->L636-3: Formula: (< 0 v_~E_1~0_26) InVars {~E_1~0=v_~E_1~0_26} OutVars{~E_1~0=v_~E_1~0_26} AuxVars[] AssignedVars[] 15725#L636-3 [3376] L636-3-->L641-3: Formula: (< 0 v_~E_2~0_26) InVars {~E_2~0=v_~E_2~0_26} OutVars{~E_2~0=v_~E_2~0_26} AuxVars[] AssignedVars[] 15909#L641-3 [3388] L641-3-->L646-3: Formula: (< 0 v_~E_3~0_26) InVars {~E_3~0=v_~E_3~0_26} OutVars{~E_3~0=v_~E_3~0_26} AuxVars[] AssignedVars[] 15910#L646-3 [3401] L646-3-->L651-3: Formula: (< 0 v_~E_4~0_26) InVars {~E_4~0=v_~E_4~0_26} OutVars{~E_4~0=v_~E_4~0_26} AuxVars[] AssignedVars[] 15860#L651-3 [3410] L651-3-->L656-3: Formula: (> 0 v_~E_5~0_26) InVars {~E_5~0=v_~E_5~0_26} OutVars{~E_5~0=v_~E_5~0_26} AuxVars[] AssignedVars[] 15861#L656-3 [2767] L656-3-->L294-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_37, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_37, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_22|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_22|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_22|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_37, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_37, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_22|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_22|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_22|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_22|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_37, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_37, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_37} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 16077#L294-21 [3426] L294-21-->L294-23: Formula: (< v_~m_pc~0_22 1) InVars {~m_pc~0=v_~m_pc~0_22} OutVars{~m_pc~0=v_~m_pc~0_22} AuxVars[] AssignedVars[] 16001#L294-23 [2803] L294-23-->L305-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_41 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_41} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 16000#L305-7 [3806] L305-7-->L745-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 16083#L745-21 [2835] L745-21-->L745-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_42) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} AuxVars[] AssignedVars[] 16084#L745-23 [2838] L745-23-->L313-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_43, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 15773#L313-21 [3468] L313-21-->L313-23: Formula: (> v_~t1_pc~0_22 1) InVars {~t1_pc~0=v_~t1_pc~0_22} OutVars{~t1_pc~0=v_~t1_pc~0_22} AuxVars[] AssignedVars[] 15775#L313-23 [2249] L313-23-->L324-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 15778#L324-7 [3813] L324-7-->L753-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 15813#L753-21 [2292] L753-21-->L753-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} AuxVars[] AssignedVars[] 15814#L753-23 [2297] L753-23-->L332-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_22|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 15817#L332-21 [3510] L332-21-->L332-23: Formula: (> 1 v_~t2_pc~0_22) InVars {~t2_pc~0=v_~t2_pc~0_22} OutVars{~t2_pc~0=v_~t2_pc~0_22} AuxVars[] AssignedVars[] 15896#L332-23 [2476] L332-23-->L343-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 15921#L343-7 [3820] L343-7-->L761-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 15929#L761-21 [3538] L761-21-->L761-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___1~0_41 0) (= v_~t2_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41, ~t2_st~0=v_~t2_st~0_19} AuxVars[] AssignedVars[~t2_st~0] 15930#L761-23 [2493] L761-23-->L351-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_22|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 15931#L351-21 [3552] L351-21-->L351-23: Formula: (< v_~t3_pc~0_22 1) InVars {~t3_pc~0=v_~t3_pc~0_22} OutVars{~t3_pc~0=v_~t3_pc~0_22} AuxVars[] AssignedVars[] 16017#L351-23 [2660] L351-23-->L362-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 15947#L362-7 [3827] L362-7-->L769-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 15948#L769-21 [2534] L769-21-->L769-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} AuxVars[] AssignedVars[] 15954#L769-23 [2537] L769-23-->L370-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_43, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 15957#L370-21 [3594] L370-21-->L370-23: Formula: (< 1 v_~t4_pc~0_22) InVars {~t4_pc~0=v_~t4_pc~0_22} OutVars{~t4_pc~0=v_~t4_pc~0_22} AuxVars[] AssignedVars[] 16093#L370-23 [2934] L370-23-->L381-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 16059#L381-7 [3834] L381-7-->L777-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 16041#L777-21 [2705] L777-21-->L777-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} AuxVars[] AssignedVars[] 16042#L777-23 [2708] L777-23-->L389-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_22|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 15680#L389-21 [2132] L389-21-->L390-7: Formula: (= v_~t5_pc~0_21 1) InVars {~t5_pc~0=v_~t5_pc~0_21} OutVars{~t5_pc~0=v_~t5_pc~0_21} AuxVars[] AssignedVars[] 15681#L390-7 [2330] L390-7-->L400-7: Formula: (and (= 1 v_~E_5~0_27) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46 1)) InVars {~E_5~0=v_~E_5~0_27} OutVars{~E_5~0=v_~E_5~0_27, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 15654#L400-7 [3837] L400-7-->L785-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 15696#L785-21 [3654] L785-21-->L785-23: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_41 0) (= v_~t5_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} OutVars{~t5_st~0=v_~t5_st~0_19, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} AuxVars[] AssignedVars[~t5_st~0] 15704#L785-23 [2161] L785-23-->L669-3: Formula: (and (= v_~M_E~0_12 1) (= v_~M_E~0_11 2)) InVars {~M_E~0=v_~M_E~0_12} OutVars{~M_E~0=v_~M_E~0_11} AuxVars[] AssignedVars[~M_E~0] 15706#L669-3 [3660] L669-3-->L674-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 15922#L674-3 [3662] L674-3-->L679-3: Formula: (< 1 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 15923#L679-3 [3664] L679-3-->L684-3: Formula: (< 1 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 15857#L684-3 [3666] L684-3-->L689-3: Formula: (> v_~T4_E~0_13 1) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 15858#L689-3 [3668] L689-3-->L694-3: Formula: (< 1 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 15880#L694-3 [2405] L694-3-->L699-3: Formula: (and (= 1 v_~E_M~0_30) (= v_~E_M~0_29 2)) InVars {~E_M~0=v_~E_M~0_30} OutVars{~E_M~0=v_~E_M~0_29} AuxVars[] AssignedVars[~E_M~0] 15776#L699-3 [3673] L699-3-->L704-3: Formula: (< 1 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 15777#L704-3 [3675] L704-3-->L709-3: Formula: (< 1 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 15660#L709-3 [3677] L709-3-->L714-3: Formula: (< 1 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 15661#L714-3 [3678] L714-3-->L719-3: Formula: (< 1 v_~E_4~0_31) InVars {~E_4~0=v_~E_4~0_31} OutVars{~E_4~0=v_~E_4~0_31} AuxVars[] AssignedVars[] 15746#L719-3 [3680] L719-3-->L724-3: Formula: (> 1 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 15747#L724-3 [2818] L724-3-->L454-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_23} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 15914#L454-1 [2466] L454-1-->L486-1: Formula: (and (= 0 v_~m_st~0_20) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26 1)) InVars {~m_st~0=v_~m_st~0_20} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 15733#L486-1 [3838] L486-1-->L949: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret15, ULTIMATE.start_start_simulation_~tmp~3] 15864#L949 [3688] L949-->L949-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_1) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} AuxVars[] AssignedVars[] 15924#L949-1 [2479] L949-1-->L454-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_1} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 15899#L454-2 [2438] L454-2-->L486-2: Formula: (and (= v_~m_st~0_2 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4 1)) InVars {~m_st~0=v_~m_st~0_2} OutVars{~m_st~0=v_~m_st~0_2, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 15737#L486-2 [3840] L486-2-->L904: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 15835#L904 [2393] L904-->L911: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 15871#L911 [3851] L911-->L930-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_6|, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 15744#L930-1 312.69/160.49 [2019-03-28 12:22:01,586 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.49 [2019-03-28 12:22:01,587 INFO L82 PathProgramCache]: Analyzing trace with hash 70755846, now seen corresponding path program 1 times 312.69/160.49 [2019-03-28 12:22:01,587 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.49 [2019-03-28 12:22:01,587 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.49 [2019-03-28 12:22:01,588 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:01,588 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:01,588 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:01,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.49 [2019-03-28 12:22:01,623 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.49 [2019-03-28 12:22:01,624 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.49 [2019-03-28 12:22:01,624 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 312.69/160.49 [2019-03-28 12:22:01,624 INFO L799 eck$LassoCheckResult]: stem already infeasible 312.69/160.49 [2019-03-28 12:22:01,624 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.49 [2019-03-28 12:22:01,624 INFO L82 PathProgramCache]: Analyzing trace with hash -1693952465, now seen corresponding path program 1 times 312.69/160.49 [2019-03-28 12:22:01,625 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.49 [2019-03-28 12:22:01,625 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.49 [2019-03-28 12:22:01,625 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:01,626 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:01,626 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:01,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.49 [2019-03-28 12:22:01,651 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.49 [2019-03-28 12:22:01,651 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.49 [2019-03-28 12:22:01,651 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 312.69/160.49 [2019-03-28 12:22:01,651 INFO L811 eck$LassoCheckResult]: loop already infeasible 312.69/160.49 [2019-03-28 12:22:01,652 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 312.69/160.49 [2019-03-28 12:22:01,652 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 312.69/160.49 [2019-03-28 12:22:01,652 INFO L87 Difference]: Start difference. First operand 454 states and 852 transitions. cyclomatic complexity: 399 Second operand 3 states. 312.69/160.49 [2019-03-28 12:22:02,391 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.49 [2019-03-28 12:22:02,392 INFO L93 Difference]: Finished difference Result 827 states and 1532 transitions. 312.69/160.49 [2019-03-28 12:22:02,392 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 312.69/160.49 [2019-03-28 12:22:02,393 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 827 states and 1532 transitions. 312.69/160.49 [2019-03-28 12:22:02,396 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 761 312.69/160.49 [2019-03-28 12:22:02,401 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 827 states to 827 states and 1532 transitions. 312.69/160.49 [2019-03-28 12:22:02,401 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 827 312.69/160.49 [2019-03-28 12:22:02,401 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 827 312.69/160.49 [2019-03-28 12:22:02,402 INFO L73 IsDeterministic]: Start isDeterministic. Operand 827 states and 1532 transitions. 312.69/160.49 [2019-03-28 12:22:02,402 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.49 [2019-03-28 12:22:02,403 INFO L706 BuchiCegarLoop]: Abstraction has 827 states and 1532 transitions. 312.69/160.49 [2019-03-28 12:22:02,403 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 827 states and 1532 transitions. 312.69/160.49 [2019-03-28 12:22:02,414 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 827 to 793. 312.69/160.49 [2019-03-28 12:22:02,415 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 793 states. 312.69/160.49 [2019-03-28 12:22:02,417 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 793 states to 793 states and 1472 transitions. 312.69/160.49 [2019-03-28 12:22:02,417 INFO L729 BuchiCegarLoop]: Abstraction has 793 states and 1472 transitions. 312.69/160.49 [2019-03-28 12:22:02,417 INFO L609 BuchiCegarLoop]: Abstraction has 793 states and 1472 transitions. 312.69/160.49 [2019-03-28 12:22:02,417 INFO L442 BuchiCegarLoop]: ======== Iteration 19============ 312.69/160.49 [2019-03-28 12:22:02,417 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 793 states and 1472 transitions. 312.69/160.49 [2019-03-28 12:22:02,419 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 312.69/160.49 [2019-03-28 12:22:02,419 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.49 [2019-03-28 12:22:02,419 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.49 [2019-03-28 12:22:02,420 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.49 [2019-03-28 12:22:02,420 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.49 [2019-03-28 12:22:02,421 INFO L794 eck$LassoCheckResult]: Stem: 17313#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 17129#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 17130#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 17196#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 17197#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 17133#L431-1 [2355] L431-1-->L436-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 17134#L436-1 [2735] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 17172#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 17173#L601-1 [3235] L601-1-->L606-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 17175#L606-1 [3236] L606-1-->L611-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 17069#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 17070#L616-1 [3240] L616-1-->L621-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 16952#L621-1 [3242] L621-1-->L626-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 16953#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 17037#L631-1 [3246] L631-1-->L636-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 17038#L636-1 [3248] L636-1-->L641-1: Formula: (> v_~E_2~0_4 0) InVars {~E_2~0=v_~E_2~0_4} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[] 17214#L641-1 [3251] L641-1-->L646-1: Formula: (> v_~E_3~0_4 0) InVars {~E_3~0=v_~E_3~0_4} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[] 17215#L646-1 [3253] L646-1-->L651-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 17163#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 17164#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 17374#L294 [3256] L294-->L294-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 17397#L294-2 [2905] L294-2-->L305: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 17407#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 17408#L745 [3261] L745-->L745-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_5) (= v_~m_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} OutVars{~m_st~0=v_~m_st~0_6, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} AuxVars[] AssignedVars[~m_st~0] 17414#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 17111#L313 [3263] L313-->L313-2: Formula: (> v_~t1_pc~0_3 1) InVars {~t1_pc~0=v_~t1_pc~0_3} OutVars{~t1_pc~0=v_~t1_pc~0_3} AuxVars[] AssignedVars[] 17062#L313-2 [2314] L313-2-->L324: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 17110#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 16967#L753 [3267] L753-->L753-2: Formula: (and (> 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_5) (= v_~t1_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_5, ~t1_st~0=v_~t1_st~0_6} AuxVars[] AssignedVars[~t1_st~0] 16968#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 16971#L332 [3269] L332-->L332-2: Formula: (> v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 17139#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 17137#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 17138#L761 [3273] L761-->L761-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_5) (= v_~t2_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5, ~t2_st~0=v_~t2_st~0_6} AuxVars[] AssignedVars[~t2_st~0] 17159#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 17160#L351 [3275] L351-->L351-2: Formula: (< 1 v_~t3_pc~0_3) InVars {~t3_pc~0=v_~t3_pc~0_3} OutVars{~t3_pc~0=v_~t3_pc~0_3} AuxVars[] AssignedVars[] 17259#L351-2 [2543] L351-2-->L362: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 17260#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 17277#L769 [3279] L769-->L769-2: Formula: (and (= v_~t3_st~0_6 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_5)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} OutVars{~t3_st~0=v_~t3_st~0_6, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} AuxVars[] AssignedVars[~t3_st~0] 17281#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 17282#L370 [3281] L370-->L370-2: Formula: (> v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 17363#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 17361#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 17362#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 17373#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 17028#L389 [2193] L389-->L390: Formula: (= 1 v_~t5_pc~0_2) InVars {~t5_pc~0=v_~t5_pc~0_2} OutVars{~t5_pc~0=v_~t5_pc~0_2} AuxVars[] AssignedVars[] 17029#L390 [2343] L390-->L400: Formula: (and (= v_~E_5~0_5 1) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4 1)) InVars {~E_5~0=v_~E_5~0_5} OutVars{~E_5~0=v_~E_5~0_5, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 17000#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 17027#L785 [3291] L785-->L785-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_5) (= v_~t5_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} OutVars{~t5_st~0=v_~t5_st~0_6, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} AuxVars[] AssignedVars[~t5_st~0] 17045#L785-2 [3293] L785-2-->L669-1: Formula: (> 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 17046#L669-1 [3294] L669-1-->L674-1: Formula: (< 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 17212#L674-1 [3296] L674-1-->L679-1: Formula: (< 1 v_~T2_E~0_7) InVars {~T2_E~0=v_~T2_E~0_7} OutVars{~T2_E~0=v_~T2_E~0_7} AuxVars[] AssignedVars[] 17213#L679-1 [3299] L679-1-->L684-1: Formula: (< v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 17161#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 17162#L689-1 [3302] L689-1-->L694-1: Formula: (> v_~T5_E~0_7 1) InVars {~T5_E~0=v_~T5_E~0_7} OutVars{~T5_E~0=v_~T5_E~0_7} AuxVars[] AssignedVars[] 17307#L694-1 [3305] L694-1-->L699-1: Formula: (< v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 17090#L699-1 [3306] L699-1-->L704-1: Formula: (> v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 17091#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 16940#L709-1 [3310] L709-1-->L714-1: Formula: (> v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 16941#L714-1 [3313] L714-1-->L719-1: Formula: (> v_~E_4~0_9 1) InVars {~E_4~0=v_~E_4~0_9} OutVars{~E_4~0=v_~E_4~0_9} AuxVars[] AssignedVars[] 17032#L719-1 [2198] L719-1-->L930-1: Formula: (and (= v_~E_5~0_8 1) (= v_~E_5~0_7 2)) InVars {~E_5~0=v_~E_5~0_8} OutVars{~E_5~0=v_~E_5~0_7} AuxVars[] AssignedVars[~E_5~0] 17033#L930-1 312.69/160.49 [2019-03-28 12:22:02,423 INFO L796 eck$LassoCheckResult]: Loop: 17033#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 17177#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 17614#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 17156#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 17080#L501 [3784] L501-->L601-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 17081#L601-2 [2768] L601-2-->L601-4: Formula: (and (= v_~M_E~0_8 1) (= 0 v_~M_E~0_9)) InVars {~M_E~0=v_~M_E~0_9} OutVars{~M_E~0=v_~M_E~0_8} AuxVars[] AssignedVars[~M_E~0] 17372#L601-4 [3322] L601-4-->L606-3: Formula: (> v_~T1_E~0_10 0) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 17179#L606-3 [3326] L606-3-->L611-3: Formula: (< 0 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 17078#L611-3 [2256] L611-3-->L616-3: Formula: (and (= v_~T3_E~0_8 1) (= v_~T3_E~0_9 0)) InVars {~T3_E~0=v_~T3_E~0_9} OutVars{~T3_E~0=v_~T3_E~0_8} AuxVars[] AssignedVars[~T3_E~0] 17079#L616-3 [3339] L616-3-->L621-3: Formula: (> v_~T4_E~0_10 0) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 16957#L621-3 [3346] L621-3-->L626-3: Formula: (< 0 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 16958#L626-3 [2580] L626-3-->L631-3: Formula: (and (= v_~E_M~0_24 1) (= 0 v_~E_M~0_25)) InVars {~E_M~0=v_~E_M~0_25} OutVars{~E_M~0=v_~E_M~0_24} AuxVars[] AssignedVars[~E_M~0] 17013#L631-3 [3365] L631-3-->L636-3: Formula: (< 0 v_~E_1~0_26) InVars {~E_1~0=v_~E_1~0_26} OutVars{~E_1~0=v_~E_1~0_26} AuxVars[] AssignedVars[] 17014#L636-3 [3376] L636-3-->L641-3: Formula: (< 0 v_~E_2~0_26) InVars {~E_2~0=v_~E_2~0_26} OutVars{~E_2~0=v_~E_2~0_26} AuxVars[] AssignedVars[] 17204#L641-3 [3388] L641-3-->L646-3: Formula: (< 0 v_~E_3~0_26) InVars {~E_3~0=v_~E_3~0_26} OutVars{~E_3~0=v_~E_3~0_26} AuxVars[] AssignedVars[] 17205#L646-3 [3401] L646-3-->L651-3: Formula: (< 0 v_~E_4~0_26) InVars {~E_4~0=v_~E_4~0_26} OutVars{~E_4~0=v_~E_4~0_26} AuxVars[] AssignedVars[] 17153#L651-3 [3410] L651-3-->L656-3: Formula: (> 0 v_~E_5~0_26) InVars {~E_5~0=v_~E_5~0_26} OutVars{~E_5~0=v_~E_5~0_26} AuxVars[] AssignedVars[] 17154#L656-3 [2767] L656-3-->L294-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_37, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_37, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_22|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_22|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_22|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_37, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_37, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_22|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_22|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_22|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_22|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_37, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_37, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_37} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 17371#L294-21 [3426] L294-21-->L294-23: Formula: (< v_~m_pc~0_22 1) InVars {~m_pc~0=v_~m_pc~0_22} OutVars{~m_pc~0=v_~m_pc~0_22} AuxVars[] AssignedVars[] 17376#L294-23 [2803] L294-23-->L305-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_41 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_41} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 17732#L305-7 [3806] L305-7-->L745-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 17730#L745-21 [2835] L745-21-->L745-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_42) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} AuxVars[] AssignedVars[] 17728#L745-23 [2838] L745-23-->L313-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_43, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 17726#L313-21 [3468] L313-21-->L313-23: Formula: (> v_~t1_pc~0_22 1) InVars {~t1_pc~0=v_~t1_pc~0_22} OutVars{~t1_pc~0=v_~t1_pc~0_22} AuxVars[] AssignedVars[] 17724#L313-23 [2249] L313-23-->L324-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 17723#L324-7 [3813] L324-7-->L753-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 17722#L753-21 [2292] L753-21-->L753-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} AuxVars[] AssignedVars[] 17721#L753-23 [2297] L753-23-->L332-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_22|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 17719#L332-21 [3510] L332-21-->L332-23: Formula: (> 1 v_~t2_pc~0_22) InVars {~t2_pc~0=v_~t2_pc~0_22} OutVars{~t2_pc~0=v_~t2_pc~0_22} AuxVars[] AssignedVars[] 17718#L332-23 [2476] L332-23-->L343-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 17717#L343-7 [3820] L343-7-->L761-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 17716#L761-21 [3538] L761-21-->L761-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___1~0_41 0) (= v_~t2_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41, ~t2_st~0=v_~t2_st~0_19} AuxVars[] AssignedVars[~t2_st~0] 17715#L761-23 [2493] L761-23-->L351-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_22|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 17713#L351-21 [3552] L351-21-->L351-23: Formula: (< v_~t3_pc~0_22 1) InVars {~t3_pc~0=v_~t3_pc~0_22} OutVars{~t3_pc~0=v_~t3_pc~0_22} AuxVars[] AssignedVars[] 17712#L351-23 [2660] L351-23-->L362-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 17711#L362-7 [3827] L362-7-->L769-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 17710#L769-21 [2534] L769-21-->L769-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} AuxVars[] AssignedVars[] 17709#L769-23 [2537] L769-23-->L370-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_43, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 17708#L370-21 [3594] L370-21-->L370-23: Formula: (< 1 v_~t4_pc~0_22) InVars {~t4_pc~0=v_~t4_pc~0_22} OutVars{~t4_pc~0=v_~t4_pc~0_22} AuxVars[] AssignedVars[] 17706#L370-23 [2934] L370-23-->L381-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 17705#L381-7 [3834] L381-7-->L777-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 17704#L777-21 [2705] L777-21-->L777-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} AuxVars[] AssignedVars[] 17703#L777-23 [2708] L777-23-->L389-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_22|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 17702#L389-21 [2132] L389-21-->L390-7: Formula: (= v_~t5_pc~0_21 1) InVars {~t5_pc~0=v_~t5_pc~0_21} OutVars{~t5_pc~0=v_~t5_pc~0_21} AuxVars[] AssignedVars[] 17700#L390-7 [2330] L390-7-->L400-7: Formula: (and (= 1 v_~E_5~0_27) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46 1)) InVars {~E_5~0=v_~E_5~0_27} OutVars{~E_5~0=v_~E_5~0_27, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 17699#L400-7 [3837] L400-7-->L785-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 17698#L785-21 [3654] L785-21-->L785-23: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_41 0) (= v_~t5_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} OutVars{~t5_st~0=v_~t5_st~0_19, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} AuxVars[] AssignedVars[~t5_st~0] 17697#L785-23 [2161] L785-23-->L669-3: Formula: (and (= v_~M_E~0_12 1) (= v_~M_E~0_11 2)) InVars {~M_E~0=v_~M_E~0_12} OutVars{~M_E~0=v_~M_E~0_11} AuxVars[] AssignedVars[~M_E~0] 17696#L669-3 [3660] L669-3-->L674-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 17217#L674-3 [3662] L674-3-->L679-3: Formula: (< 1 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 17218#L679-3 [3664] L679-3-->L684-3: Formula: (< 1 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 17150#L684-3 [3666] L684-3-->L689-3: Formula: (> v_~T4_E~0_13 1) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 17151#L689-3 [3668] L689-3-->L694-3: Formula: (< 1 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 17174#L694-3 [2405] L694-3-->L699-3: Formula: (and (= 1 v_~E_M~0_30) (= v_~E_M~0_29 2)) InVars {~E_M~0=v_~E_M~0_30} OutVars{~E_M~0=v_~E_M~0_29} AuxVars[] AssignedVars[~E_M~0] 17066#L699-3 [3673] L699-3-->L704-3: Formula: (< 1 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 17067#L704-3 [3675] L704-3-->L709-3: Formula: (< 1 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 16949#L709-3 [3677] L709-3-->L714-3: Formula: (< 1 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 16950#L714-3 [3678] L714-3-->L719-3: Formula: (< 1 v_~E_4~0_31) InVars {~E_4~0=v_~E_4~0_31} OutVars{~E_4~0=v_~E_4~0_31} AuxVars[] AssignedVars[] 17035#L719-3 [3680] L719-3-->L724-3: Formula: (> 1 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 17036#L724-3 [2818] L724-3-->L454-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_23} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 17209#L454-1 [2466] L454-1-->L486-1: Formula: (and (= 0 v_~m_st~0_20) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26 1)) InVars {~m_st~0=v_~m_st~0_20} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 17022#L486-1 [3838] L486-1-->L949: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret15, ULTIMATE.start_start_simulation_~tmp~3] 17158#L949 [3688] L949-->L949-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_1) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} AuxVars[] AssignedVars[] 17232#L949-1 [2479] L949-1-->L454-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_1} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 17626#L454-2 [2438] L454-2-->L486-2: Formula: (and (= v_~m_st~0_2 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4 1)) InVars {~m_st~0=v_~m_st~0_2} OutVars{~m_st~0=v_~m_st~0_2, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 17620#L486-2 [3840] L486-2-->L904: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 17618#L904 [2393] L904-->L911: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 17616#L911 [3851] L911-->L930-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_6|, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 17033#L930-1 312.69/160.49 [2019-03-28 12:22:02,423 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.49 [2019-03-28 12:22:02,423 INFO L82 PathProgramCache]: Analyzing trace with hash 1442634658, now seen corresponding path program 1 times 312.69/160.49 [2019-03-28 12:22:02,423 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.49 [2019-03-28 12:22:02,423 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.49 [2019-03-28 12:22:02,424 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:02,425 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:02,425 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:02,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.49 [2019-03-28 12:22:02,449 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.49 [2019-03-28 12:22:02,449 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.49 [2019-03-28 12:22:02,449 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 312.69/160.49 [2019-03-28 12:22:02,449 INFO L799 eck$LassoCheckResult]: stem already infeasible 312.69/160.49 [2019-03-28 12:22:02,450 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.49 [2019-03-28 12:22:02,450 INFO L82 PathProgramCache]: Analyzing trace with hash -1693952465, now seen corresponding path program 2 times 312.69/160.49 [2019-03-28 12:22:02,450 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.49 [2019-03-28 12:22:02,450 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.49 [2019-03-28 12:22:02,451 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:02,451 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:02,451 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:02,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.49 [2019-03-28 12:22:02,472 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.49 [2019-03-28 12:22:02,472 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.49 [2019-03-28 12:22:02,472 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 312.69/160.49 [2019-03-28 12:22:02,473 INFO L811 eck$LassoCheckResult]: loop already infeasible 312.69/160.49 [2019-03-28 12:22:02,473 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. 312.69/160.49 [2019-03-28 12:22:02,473 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 312.69/160.49 [2019-03-28 12:22:02,473 INFO L87 Difference]: Start difference. First operand 793 states and 1472 transitions. cyclomatic complexity: 680 Second operand 4 states. 312.69/160.49 [2019-03-28 12:22:03,837 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.49 [2019-03-28 12:22:03,837 INFO L93 Difference]: Finished difference Result 1507 states and 2792 transitions. 312.69/160.49 [2019-03-28 12:22:03,838 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. 312.69/160.49 [2019-03-28 12:22:03,838 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1507 states and 2792 transitions. 312.69/160.49 [2019-03-28 12:22:03,844 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1441 312.69/160.49 [2019-03-28 12:22:03,852 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1507 states to 1507 states and 2792 transitions. 312.69/160.49 [2019-03-28 12:22:03,852 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1507 312.69/160.49 [2019-03-28 12:22:03,853 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1507 312.69/160.49 [2019-03-28 12:22:03,853 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1507 states and 2792 transitions. 312.69/160.49 [2019-03-28 12:22:03,854 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.49 [2019-03-28 12:22:03,854 INFO L706 BuchiCegarLoop]: Abstraction has 1507 states and 2792 transitions. 312.69/160.49 [2019-03-28 12:22:03,856 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1507 states and 2792 transitions. 312.69/160.49 [2019-03-28 12:22:03,868 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1507 to 809. 312.69/160.49 [2019-03-28 12:22:03,868 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 809 states. 312.69/160.49 [2019-03-28 12:22:03,870 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 809 states to 809 states and 1488 transitions. 312.69/160.49 [2019-03-28 12:22:03,870 INFO L729 BuchiCegarLoop]: Abstraction has 809 states and 1488 transitions. 312.69/160.49 [2019-03-28 12:22:03,871 INFO L609 BuchiCegarLoop]: Abstraction has 809 states and 1488 transitions. 312.69/160.49 [2019-03-28 12:22:03,871 INFO L442 BuchiCegarLoop]: ======== Iteration 20============ 312.69/160.49 [2019-03-28 12:22:03,871 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 809 states and 1488 transitions. 312.69/160.49 [2019-03-28 12:22:03,873 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 743 312.69/160.49 [2019-03-28 12:22:03,873 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.49 [2019-03-28 12:22:03,873 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.49 [2019-03-28 12:22:03,874 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.49 [2019-03-28 12:22:03,874 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.49 [2019-03-28 12:22:03,875 INFO L794 eck$LassoCheckResult]: Stem: 19626#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 19438#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 19439#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 19503#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 19504#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 19440#L431-1 [2355] L431-1-->L436-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 19441#L436-1 [2735] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 19480#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 19481#L601-1 [3235] L601-1-->L606-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 19483#L606-1 [3236] L606-1-->L611-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 19379#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 19380#L616-1 [3240] L616-1-->L621-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 19263#L621-1 [3242] L621-1-->L626-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 19264#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 19348#L631-1 [3246] L631-1-->L636-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 19349#L636-1 [3248] L636-1-->L641-1: Formula: (> v_~E_2~0_4 0) InVars {~E_2~0=v_~E_2~0_4} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[] 19522#L641-1 [3251] L641-1-->L646-1: Formula: (> v_~E_3~0_4 0) InVars {~E_3~0=v_~E_3~0_4} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[] 19523#L646-1 [3253] L646-1-->L651-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 19471#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 19472#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 19689#L294 [3256] L294-->L294-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 19712#L294-2 [2905] L294-2-->L305: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 19728#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 19729#L745 [2925] L745-->L745-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_6) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} AuxVars[] AssignedVars[] 19736#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 19420#L313 [3263] L313-->L313-2: Formula: (> v_~t1_pc~0_3 1) InVars {~t1_pc~0=v_~t1_pc~0_3} OutVars{~t1_pc~0=v_~t1_pc~0_3} AuxVars[] AssignedVars[] 19372#L313-2 [2314] L313-2-->L324: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 19419#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 19278#L753 [3267] L753-->L753-2: Formula: (and (> 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_5) (= v_~t1_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_5, ~t1_st~0=v_~t1_st~0_6} AuxVars[] AssignedVars[~t1_st~0] 19279#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 19282#L332 [3269] L332-->L332-2: Formula: (> v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 19448#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 19446#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 19447#L761 [3273] L761-->L761-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_5) (= v_~t2_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5, ~t2_st~0=v_~t2_st~0_6} AuxVars[] AssignedVars[~t2_st~0] 19467#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 19468#L351 [3275] L351-->L351-2: Formula: (< 1 v_~t3_pc~0_3) InVars {~t3_pc~0=v_~t3_pc~0_3} OutVars{~t3_pc~0=v_~t3_pc~0_3} AuxVars[] AssignedVars[] 19571#L351-2 [2543] L351-2-->L362: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 19572#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 19590#L769 [3279] L769-->L769-2: Formula: (and (= v_~t3_st~0_6 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_5)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} OutVars{~t3_st~0=v_~t3_st~0_6, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} AuxVars[] AssignedVars[~t3_st~0] 19594#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 19595#L370 [3281] L370-->L370-2: Formula: (> v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 19677#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 19675#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 19676#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 19688#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 19339#L389 [2193] L389-->L390: Formula: (= 1 v_~t5_pc~0_2) InVars {~t5_pc~0=v_~t5_pc~0_2} OutVars{~t5_pc~0=v_~t5_pc~0_2} AuxVars[] AssignedVars[] 19340#L390 [2343] L390-->L400: Formula: (and (= v_~E_5~0_5 1) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4 1)) InVars {~E_5~0=v_~E_5~0_5} OutVars{~E_5~0=v_~E_5~0_5, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 19311#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 19338#L785 [3291] L785-->L785-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_5) (= v_~t5_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} OutVars{~t5_st~0=v_~t5_st~0_6, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} AuxVars[] AssignedVars[~t5_st~0] 19356#L785-2 [3293] L785-2-->L669-1: Formula: (> 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 19357#L669-1 [3294] L669-1-->L674-1: Formula: (< 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 19520#L674-1 [3296] L674-1-->L679-1: Formula: (< 1 v_~T2_E~0_7) InVars {~T2_E~0=v_~T2_E~0_7} OutVars{~T2_E~0=v_~T2_E~0_7} AuxVars[] AssignedVars[] 19521#L679-1 [3299] L679-1-->L684-1: Formula: (< v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 19469#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 19470#L689-1 [3302] L689-1-->L694-1: Formula: (> v_~T5_E~0_7 1) InVars {~T5_E~0=v_~T5_E~0_7} OutVars{~T5_E~0=v_~T5_E~0_7} AuxVars[] AssignedVars[] 19620#L694-1 [3305] L694-1-->L699-1: Formula: (< v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 19400#L699-1 [3306] L699-1-->L704-1: Formula: (> v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 19401#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 19251#L709-1 [3310] L709-1-->L714-1: Formula: (> v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 19252#L714-1 [3313] L714-1-->L719-1: Formula: (> v_~E_4~0_9 1) InVars {~E_4~0=v_~E_4~0_9} OutVars{~E_4~0=v_~E_4~0_9} AuxVars[] AssignedVars[] 19343#L719-1 [2198] L719-1-->L930-1: Formula: (and (= v_~E_5~0_8 1) (= v_~E_5~0_7 2)) InVars {~E_5~0=v_~E_5~0_8} OutVars{~E_5~0=v_~E_5~0_7} AuxVars[] AssignedVars[~E_5~0] 19344#L930-1 312.69/160.49 [2019-03-28 12:22:03,876 INFO L796 eck$LassoCheckResult]: Loop: 19344#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 19773#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 19772#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 19766#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 19764#L501 [3784] L501-->L601-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 19765#L601-2 [2768] L601-2-->L601-4: Formula: (and (= v_~M_E~0_8 1) (= 0 v_~M_E~0_9)) InVars {~M_E~0=v_~M_E~0_9} OutVars{~M_E~0=v_~M_E~0_8} AuxVars[] AssignedVars[~M_E~0] 20054#L601-4 [3322] L601-4-->L606-3: Formula: (> v_~T1_E~0_10 0) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 20053#L606-3 [3326] L606-3-->L611-3: Formula: (< 0 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 20052#L611-3 [2256] L611-3-->L616-3: Formula: (and (= v_~T3_E~0_8 1) (= v_~T3_E~0_9 0)) InVars {~T3_E~0=v_~T3_E~0_9} OutVars{~T3_E~0=v_~T3_E~0_8} AuxVars[] AssignedVars[~T3_E~0] 20051#L616-3 [3339] L616-3-->L621-3: Formula: (> v_~T4_E~0_10 0) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 20050#L621-3 [3346] L621-3-->L626-3: Formula: (< 0 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 20049#L626-3 [2580] L626-3-->L631-3: Formula: (and (= v_~E_M~0_24 1) (= 0 v_~E_M~0_25)) InVars {~E_M~0=v_~E_M~0_25} OutVars{~E_M~0=v_~E_M~0_24} AuxVars[] AssignedVars[~E_M~0] 20048#L631-3 [3365] L631-3-->L636-3: Formula: (< 0 v_~E_1~0_26) InVars {~E_1~0=v_~E_1~0_26} OutVars{~E_1~0=v_~E_1~0_26} AuxVars[] AssignedVars[] 20047#L636-3 [3376] L636-3-->L641-3: Formula: (< 0 v_~E_2~0_26) InVars {~E_2~0=v_~E_2~0_26} OutVars{~E_2~0=v_~E_2~0_26} AuxVars[] AssignedVars[] 20046#L641-3 [3388] L641-3-->L646-3: Formula: (< 0 v_~E_3~0_26) InVars {~E_3~0=v_~E_3~0_26} OutVars{~E_3~0=v_~E_3~0_26} AuxVars[] AssignedVars[] 20045#L646-3 [3401] L646-3-->L651-3: Formula: (< 0 v_~E_4~0_26) InVars {~E_4~0=v_~E_4~0_26} OutVars{~E_4~0=v_~E_4~0_26} AuxVars[] AssignedVars[] 20044#L651-3 [3410] L651-3-->L656-3: Formula: (> 0 v_~E_5~0_26) InVars {~E_5~0=v_~E_5~0_26} OutVars{~E_5~0=v_~E_5~0_26} AuxVars[] AssignedVars[] 19685#L656-3 [2767] L656-3-->L294-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_37, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_37, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_22|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_22|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_22|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_37, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_37, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_22|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_22|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_22|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_22|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_37, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_37, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_37} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 19686#L294-21 [3426] L294-21-->L294-23: Formula: (< v_~m_pc~0_22 1) InVars {~m_pc~0=v_~m_pc~0_22} OutVars{~m_pc~0=v_~m_pc~0_22} AuxVars[] AssignedVars[] 19692#L294-23 [2803] L294-23-->L305-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_41 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_41} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 20037#L305-7 [3806] L305-7-->L745-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 20035#L745-21 [2835] L745-21-->L745-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_42) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} AuxVars[] AssignedVars[] 20033#L745-23 [2838] L745-23-->L313-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_43, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 20031#L313-21 [3468] L313-21-->L313-23: Formula: (> v_~t1_pc~0_22 1) InVars {~t1_pc~0=v_~t1_pc~0_22} OutVars{~t1_pc~0=v_~t1_pc~0_22} AuxVars[] AssignedVars[] 20027#L313-23 [2249] L313-23-->L324-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 20025#L324-7 [3813] L324-7-->L753-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 20023#L753-21 [2292] L753-21-->L753-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} AuxVars[] AssignedVars[] 20021#L753-23 [2297] L753-23-->L332-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_22|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 20018#L332-21 [3510] L332-21-->L332-23: Formula: (> 1 v_~t2_pc~0_22) InVars {~t2_pc~0=v_~t2_pc~0_22} OutVars{~t2_pc~0=v_~t2_pc~0_22} AuxVars[] AssignedVars[] 20017#L332-23 [2476] L332-23-->L343-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 20016#L343-7 [3820] L343-7-->L761-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 20014#L761-21 [3538] L761-21-->L761-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___1~0_41 0) (= v_~t2_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41, ~t2_st~0=v_~t2_st~0_19} AuxVars[] AssignedVars[~t2_st~0] 20012#L761-23 [2493] L761-23-->L351-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_22|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 20009#L351-21 [3552] L351-21-->L351-23: Formula: (< v_~t3_pc~0_22 1) InVars {~t3_pc~0=v_~t3_pc~0_22} OutVars{~t3_pc~0=v_~t3_pc~0_22} AuxVars[] AssignedVars[] 20008#L351-23 [2660] L351-23-->L362-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 20003#L362-7 [3827] L362-7-->L769-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 19999#L769-21 [2534] L769-21-->L769-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} AuxVars[] AssignedVars[] 19995#L769-23 [2537] L769-23-->L370-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_43, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 19990#L370-21 [3594] L370-21-->L370-23: Formula: (< 1 v_~t4_pc~0_22) InVars {~t4_pc~0=v_~t4_pc~0_22} OutVars{~t4_pc~0=v_~t4_pc~0_22} AuxVars[] AssignedVars[] 19983#L370-23 [2934] L370-23-->L381-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 19976#L381-7 [3834] L381-7-->L777-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 19970#L777-21 [2705] L777-21-->L777-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} AuxVars[] AssignedVars[] 19965#L777-23 [2708] L777-23-->L389-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_22|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 19960#L389-21 [2132] L389-21-->L390-7: Formula: (= v_~t5_pc~0_21 1) InVars {~t5_pc~0=v_~t5_pc~0_21} OutVars{~t5_pc~0=v_~t5_pc~0_21} AuxVars[] AssignedVars[] 19953#L390-7 [2330] L390-7-->L400-7: Formula: (and (= 1 v_~E_5~0_27) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46 1)) InVars {~E_5~0=v_~E_5~0_27} OutVars{~E_5~0=v_~E_5~0_27, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 19948#L400-7 [3837] L400-7-->L785-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 19940#L785-21 [3654] L785-21-->L785-23: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_41 0) (= v_~t5_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} OutVars{~t5_st~0=v_~t5_st~0_19, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} AuxVars[] AssignedVars[~t5_st~0] 19935#L785-23 [2161] L785-23-->L669-3: Formula: (and (= v_~M_E~0_12 1) (= v_~M_E~0_11 2)) InVars {~M_E~0=v_~M_E~0_12} OutVars{~M_E~0=v_~M_E~0_11} AuxVars[] AssignedVars[~M_E~0] 19930#L669-3 [3660] L669-3-->L674-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 19924#L674-3 [3662] L674-3-->L679-3: Formula: (< 1 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 19918#L679-3 [3664] L679-3-->L684-3: Formula: (< 1 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 19912#L684-3 [3666] L684-3-->L689-3: Formula: (> v_~T4_E~0_13 1) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 19815#L689-3 [3668] L689-3-->L694-3: Formula: (< 1 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 19812#L694-3 [2405] L694-3-->L699-3: Formula: (and (= 1 v_~E_M~0_30) (= v_~E_M~0_29 2)) InVars {~E_M~0=v_~E_M~0_30} OutVars{~E_M~0=v_~E_M~0_29} AuxVars[] AssignedVars[~E_M~0] 19810#L699-3 [3673] L699-3-->L704-3: Formula: (< 1 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 19808#L704-3 [3675] L704-3-->L709-3: Formula: (< 1 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 19806#L709-3 [3677] L709-3-->L714-3: Formula: (< 1 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 19804#L714-3 [3678] L714-3-->L719-3: Formula: (< 1 v_~E_4~0_31) InVars {~E_4~0=v_~E_4~0_31} OutVars{~E_4~0=v_~E_4~0_31} AuxVars[] AssignedVars[] 19801#L719-3 [3680] L719-3-->L724-3: Formula: (> 1 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 19799#L724-3 [2818] L724-3-->L454-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_23} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 19753#L454-1 [2466] L454-1-->L486-1: Formula: (and (= 0 v_~m_st~0_20) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26 1)) InVars {~m_st~0=v_~m_st~0_20} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 19743#L486-1 [3838] L486-1-->L949: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret15, ULTIMATE.start_start_simulation_~tmp~3] 19541#L949 [3688] L949-->L949-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_1) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} AuxVars[] AssignedVars[] 19542#L949-1 [2479] L949-1-->L454-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_1} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 19790#L454-2 [2438] L454-2-->L486-2: Formula: (and (= v_~m_st~0_2 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4 1)) InVars {~m_st~0=v_~m_st~0_2} OutVars{~m_st~0=v_~m_st~0_2, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 19784#L486-2 [3840] L486-2-->L904: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 19782#L904 [2393] L904-->L911: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 19780#L911 [3851] L911-->L930-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_6|, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 19344#L930-1 312.69/160.49 [2019-03-28 12:22:03,877 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.49 [2019-03-28 12:22:03,877 INFO L82 PathProgramCache]: Analyzing trace with hash -1718662414, now seen corresponding path program 1 times 312.69/160.49 [2019-03-28 12:22:03,877 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.49 [2019-03-28 12:22:03,877 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.49 [2019-03-28 12:22:03,878 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:03,878 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:03,878 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:03,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.49 [2019-03-28 12:22:03,898 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.49 [2019-03-28 12:22:03,898 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.49 [2019-03-28 12:22:03,899 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 312.69/160.49 [2019-03-28 12:22:03,899 INFO L799 eck$LassoCheckResult]: stem already infeasible 312.69/160.49 [2019-03-28 12:22:03,899 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.49 [2019-03-28 12:22:03,899 INFO L82 PathProgramCache]: Analyzing trace with hash -1693952465, now seen corresponding path program 3 times 312.69/160.49 [2019-03-28 12:22:03,899 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.49 [2019-03-28 12:22:03,900 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.49 [2019-03-28 12:22:03,900 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:03,900 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:03,901 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:03,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.49 [2019-03-28 12:22:03,922 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.49 [2019-03-28 12:22:03,922 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.49 [2019-03-28 12:22:03,922 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 312.69/160.49 [2019-03-28 12:22:03,923 INFO L811 eck$LassoCheckResult]: loop already infeasible 312.69/160.49 [2019-03-28 12:22:03,923 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 312.69/160.49 [2019-03-28 12:22:03,923 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 312.69/160.49 [2019-03-28 12:22:03,923 INFO L87 Difference]: Start difference. First operand 809 states and 1488 transitions. cyclomatic complexity: 680 Second operand 3 states. 312.69/160.49 [2019-03-28 12:22:04,632 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.49 [2019-03-28 12:22:04,632 INFO L93 Difference]: Finished difference Result 1521 states and 2789 transitions. 312.69/160.49 [2019-03-28 12:22:04,632 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 312.69/160.49 [2019-03-28 12:22:04,633 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1521 states and 2789 transitions. 312.69/160.49 [2019-03-28 12:22:04,638 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1456 312.69/160.49 [2019-03-28 12:22:04,646 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1521 states to 1521 states and 2789 transitions. 312.69/160.49 [2019-03-28 12:22:04,646 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1521 312.69/160.49 [2019-03-28 12:22:04,647 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1521 312.69/160.49 [2019-03-28 12:22:04,647 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1521 states and 2789 transitions. 312.69/160.49 [2019-03-28 12:22:04,648 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.49 [2019-03-28 12:22:04,649 INFO L706 BuchiCegarLoop]: Abstraction has 1521 states and 2789 transitions. 312.69/160.49 [2019-03-28 12:22:04,650 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1521 states and 2789 transitions. 312.69/160.49 [2019-03-28 12:22:04,673 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1521 to 1463. 312.69/160.49 [2019-03-28 12:22:04,674 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1463 states. 312.69/160.49 [2019-03-28 12:22:04,677 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1463 states to 1463 states and 2687 transitions. 312.69/160.49 [2019-03-28 12:22:04,677 INFO L729 BuchiCegarLoop]: Abstraction has 1463 states and 2687 transitions. 312.69/160.49 [2019-03-28 12:22:04,677 INFO L609 BuchiCegarLoop]: Abstraction has 1463 states and 2687 transitions. 312.69/160.49 [2019-03-28 12:22:04,677 INFO L442 BuchiCegarLoop]: ======== Iteration 21============ 312.69/160.49 [2019-03-28 12:22:04,677 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1463 states and 2687 transitions. 312.69/160.49 [2019-03-28 12:22:04,681 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1398 312.69/160.49 [2019-03-28 12:22:04,681 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.49 [2019-03-28 12:22:04,681 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.49 [2019-03-28 12:22:04,682 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.49 [2019-03-28 12:22:04,682 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.49 [2019-03-28 12:22:04,683 INFO L794 eck$LassoCheckResult]: Stem: 21971#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 21786#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 21787#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 21851#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 21852#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 21790#L431-1 [2355] L431-1-->L436-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 21791#L436-1 [2735] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 21828#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 21829#L601-1 [3235] L601-1-->L606-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 21831#L606-1 [3236] L606-1-->L611-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 21722#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 21723#L616-1 [3240] L616-1-->L621-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 21600#L621-1 [3242] L621-1-->L626-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 21601#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 21692#L631-1 [3246] L631-1-->L636-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 21693#L636-1 [3248] L636-1-->L641-1: Formula: (> v_~E_2~0_4 0) InVars {~E_2~0=v_~E_2~0_4} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[] 21870#L641-1 [3251] L641-1-->L646-1: Formula: (> v_~E_3~0_4 0) InVars {~E_3~0=v_~E_3~0_4} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[] 21871#L646-1 [3253] L646-1-->L651-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 21819#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 21820#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 22031#L294 [3256] L294-->L294-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 22061#L294-2 [2905] L294-2-->L305: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 22075#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 22076#L745 [2925] L745-->L745-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_6) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} AuxVars[] AssignedVars[] 22084#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 21766#L313 [3262] L313-->L313-2: Formula: (< v_~t1_pc~0_3 1) InVars {~t1_pc~0=v_~t1_pc~0_3} OutVars{~t1_pc~0=v_~t1_pc~0_3} AuxVars[] AssignedVars[] 21767#L313-2 [2314] L313-2-->L324: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 21765#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 21616#L753 [3267] L753-->L753-2: Formula: (and (> 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_5) (= v_~t1_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_5, ~t1_st~0=v_~t1_st~0_6} AuxVars[] AssignedVars[~t1_st~0] 21617#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 21620#L332 [3269] L332-->L332-2: Formula: (> v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 21796#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 21794#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 21795#L761 [3273] L761-->L761-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_5) (= v_~t2_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5, ~t2_st~0=v_~t2_st~0_6} AuxVars[] AssignedVars[~t2_st~0] 21815#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 21816#L351 [3275] L351-->L351-2: Formula: (< 1 v_~t3_pc~0_3) InVars {~t3_pc~0=v_~t3_pc~0_3} OutVars{~t3_pc~0=v_~t3_pc~0_3} AuxVars[] AssignedVars[] 21915#L351-2 [2543] L351-2-->L362: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 21916#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 21934#L769 [3279] L769-->L769-2: Formula: (and (= v_~t3_st~0_6 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_5)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} OutVars{~t3_st~0=v_~t3_st~0_6, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} AuxVars[] AssignedVars[~t3_st~0] 21939#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 21940#L370 [3281] L370-->L370-2: Formula: (> v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 22020#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 22018#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 22019#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 22030#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 21683#L389 [2193] L389-->L390: Formula: (= 1 v_~t5_pc~0_2) InVars {~t5_pc~0=v_~t5_pc~0_2} OutVars{~t5_pc~0=v_~t5_pc~0_2} AuxVars[] AssignedVars[] 21684#L390 [2343] L390-->L400: Formula: (and (= v_~E_5~0_5 1) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4 1)) InVars {~E_5~0=v_~E_5~0_5} OutVars{~E_5~0=v_~E_5~0_5, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 21650#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 21681#L785 [3291] L785-->L785-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_5) (= v_~t5_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} OutVars{~t5_st~0=v_~t5_st~0_6, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} AuxVars[] AssignedVars[~t5_st~0] 21700#L785-2 [3293] L785-2-->L669-1: Formula: (> 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 21701#L669-1 [3294] L669-1-->L674-1: Formula: (< 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 21868#L674-1 [3296] L674-1-->L679-1: Formula: (< 1 v_~T2_E~0_7) InVars {~T2_E~0=v_~T2_E~0_7} OutVars{~T2_E~0=v_~T2_E~0_7} AuxVars[] AssignedVars[] 21869#L679-1 [3299] L679-1-->L684-1: Formula: (< v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 21817#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 21818#L689-1 [3302] L689-1-->L694-1: Formula: (> v_~T5_E~0_7 1) InVars {~T5_E~0=v_~T5_E~0_7} OutVars{~T5_E~0=v_~T5_E~0_7} AuxVars[] AssignedVars[] 21965#L694-1 [3305] L694-1-->L699-1: Formula: (< v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 21743#L699-1 [3306] L699-1-->L704-1: Formula: (> v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 21744#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 21589#L709-1 [3310] L709-1-->L714-1: Formula: (> v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 21590#L714-1 [3313] L714-1-->L719-1: Formula: (> v_~E_4~0_9 1) InVars {~E_4~0=v_~E_4~0_9} OutVars{~E_4~0=v_~E_4~0_9} AuxVars[] AssignedVars[] 21687#L719-1 [2198] L719-1-->L930-1: Formula: (and (= v_~E_5~0_8 1) (= v_~E_5~0_7 2)) InVars {~E_5~0=v_~E_5~0_8} OutVars{~E_5~0=v_~E_5~0_7} AuxVars[] AssignedVars[~E_5~0] 21688#L930-1 312.69/160.49 [2019-03-28 12:22:04,684 INFO L796 eck$LassoCheckResult]: Loop: 21688#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 21694#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 21695#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 21672#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 21733#L501 [3784] L501-->L601-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 21734#L601-2 [2768] L601-2-->L601-4: Formula: (and (= v_~M_E~0_8 1) (= 0 v_~M_E~0_9)) InVars {~M_E~0=v_~M_E~0_9} OutVars{~M_E~0=v_~M_E~0_8} AuxVars[] AssignedVars[~M_E~0] 22029#L601-4 [3322] L601-4-->L606-3: Formula: (> v_~T1_E~0_10 0) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 21834#L606-3 [3326] L606-3-->L611-3: Formula: (< 0 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 21731#L611-3 [2256] L611-3-->L616-3: Formula: (and (= v_~T3_E~0_8 1) (= v_~T3_E~0_9 0)) InVars {~T3_E~0=v_~T3_E~0_9} OutVars{~T3_E~0=v_~T3_E~0_8} AuxVars[] AssignedVars[~T3_E~0] 21732#L616-3 [3339] L616-3-->L621-3: Formula: (> v_~T4_E~0_10 0) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 21606#L621-3 [3346] L621-3-->L626-3: Formula: (< 0 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 21607#L626-3 [2580] L626-3-->L631-3: Formula: (and (= v_~E_M~0_24 1) (= 0 v_~E_M~0_25)) InVars {~E_M~0=v_~E_M~0_25} OutVars{~E_M~0=v_~E_M~0_24} AuxVars[] AssignedVars[~E_M~0] 21665#L631-3 [3365] L631-3-->L636-3: Formula: (< 0 v_~E_1~0_26) InVars {~E_1~0=v_~E_1~0_26} OutVars{~E_1~0=v_~E_1~0_26} AuxVars[] AssignedVars[] 21666#L636-3 [3376] L636-3-->L641-3: Formula: (< 0 v_~E_2~0_26) InVars {~E_2~0=v_~E_2~0_26} OutVars{~E_2~0=v_~E_2~0_26} AuxVars[] AssignedVars[] 21859#L641-3 [3388] L641-3-->L646-3: Formula: (< 0 v_~E_3~0_26) InVars {~E_3~0=v_~E_3~0_26} OutVars{~E_3~0=v_~E_3~0_26} AuxVars[] AssignedVars[] 21860#L646-3 [3401] L646-3-->L651-3: Formula: (< 0 v_~E_4~0_26) InVars {~E_4~0=v_~E_4~0_26} OutVars{~E_4~0=v_~E_4~0_26} AuxVars[] AssignedVars[] 21810#L651-3 [3410] L651-3-->L656-3: Formula: (> 0 v_~E_5~0_26) InVars {~E_5~0=v_~E_5~0_26} OutVars{~E_5~0=v_~E_5~0_26} AuxVars[] AssignedVars[] 21811#L656-3 [2767] L656-3-->L294-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_37, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_37, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_22|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_22|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_22|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_37, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_37, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_22|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_22|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_22|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_22|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_37, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_37, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_37} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 22028#L294-21 [3426] L294-21-->L294-23: Formula: (< v_~m_pc~0_22 1) InVars {~m_pc~0=v_~m_pc~0_22} OutVars{~m_pc~0=v_~m_pc~0_22} AuxVars[] AssignedVars[] 22038#L294-23 [2803] L294-23-->L305-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_41 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_41} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 22039#L305-7 [3806] L305-7-->L745-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 22050#L745-21 [2835] L745-21-->L745-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_42) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} AuxVars[] AssignedVars[] 22051#L745-23 [2838] L745-23-->L313-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_43, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 21716#L313-21 [3469] L313-21-->L313-23: Formula: (< v_~t1_pc~0_22 1) InVars {~t1_pc~0=v_~t1_pc~0_22} OutVars{~t1_pc~0=v_~t1_pc~0_22} AuxVars[] AssignedVars[] 21717#L313-23 [2249] L313-23-->L324-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 22770#L324-7 [3813] L324-7-->L753-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 22769#L753-21 [2292] L753-21-->L753-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} AuxVars[] AssignedVars[] 22768#L753-23 [2297] L753-23-->L332-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_22|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 22766#L332-21 [3510] L332-21-->L332-23: Formula: (> 1 v_~t2_pc~0_22) InVars {~t2_pc~0=v_~t2_pc~0_22} OutVars{~t2_pc~0=v_~t2_pc~0_22} AuxVars[] AssignedVars[] 22765#L332-23 [2476] L332-23-->L343-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 22764#L343-7 [3820] L343-7-->L761-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 22763#L761-21 [3538] L761-21-->L761-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___1~0_41 0) (= v_~t2_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41, ~t2_st~0=v_~t2_st~0_19} AuxVars[] AssignedVars[~t2_st~0] 22762#L761-23 [2493] L761-23-->L351-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_22|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 22760#L351-21 [3552] L351-21-->L351-23: Formula: (< v_~t3_pc~0_22 1) InVars {~t3_pc~0=v_~t3_pc~0_22} OutVars{~t3_pc~0=v_~t3_pc~0_22} AuxVars[] AssignedVars[] 22759#L351-23 [2660] L351-23-->L362-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 22758#L362-7 [3827] L362-7-->L769-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 22757#L769-21 [2534] L769-21-->L769-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} AuxVars[] AssignedVars[] 22756#L769-23 [2537] L769-23-->L370-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_43, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 22755#L370-21 [3594] L370-21-->L370-23: Formula: (< 1 v_~t4_pc~0_22) InVars {~t4_pc~0=v_~t4_pc~0_22} OutVars{~t4_pc~0=v_~t4_pc~0_22} AuxVars[] AssignedVars[] 22753#L370-23 [2934] L370-23-->L381-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 22752#L381-7 [3834] L381-7-->L777-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 22751#L777-21 [2705] L777-21-->L777-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} AuxVars[] AssignedVars[] 22750#L777-23 [2708] L777-23-->L389-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_22|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 22749#L389-21 [2132] L389-21-->L390-7: Formula: (= v_~t5_pc~0_21 1) InVars {~t5_pc~0=v_~t5_pc~0_21} OutVars{~t5_pc~0=v_~t5_pc~0_21} AuxVars[] AssignedVars[] 22747#L390-7 [2330] L390-7-->L400-7: Formula: (and (= 1 v_~E_5~0_27) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46 1)) InVars {~E_5~0=v_~E_5~0_27} OutVars{~E_5~0=v_~E_5~0_27, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 22746#L400-7 [3837] L400-7-->L785-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 22745#L785-21 [3654] L785-21-->L785-23: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_41 0) (= v_~t5_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} OutVars{~t5_st~0=v_~t5_st~0_19, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} AuxVars[] AssignedVars[~t5_st~0] 22744#L785-23 [2161] L785-23-->L669-3: Formula: (and (= v_~M_E~0_12 1) (= v_~M_E~0_11 2)) InVars {~M_E~0=v_~M_E~0_12} OutVars{~M_E~0=v_~M_E~0_11} AuxVars[] AssignedVars[~M_E~0] 22743#L669-3 [3660] L669-3-->L674-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 22742#L674-3 [3662] L674-3-->L679-3: Formula: (< 1 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 22741#L679-3 [3664] L679-3-->L684-3: Formula: (< 1 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 22740#L684-3 [3666] L684-3-->L689-3: Formula: (> v_~T4_E~0_13 1) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 22739#L689-3 [3668] L689-3-->L694-3: Formula: (< 1 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 22738#L694-3 [2405] L694-3-->L699-3: Formula: (and (= 1 v_~E_M~0_30) (= v_~E_M~0_29 2)) InVars {~E_M~0=v_~E_M~0_30} OutVars{~E_M~0=v_~E_M~0_29} AuxVars[] AssignedVars[~E_M~0] 22737#L699-3 [3673] L699-3-->L704-3: Formula: (< 1 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 22736#L704-3 [3675] L704-3-->L709-3: Formula: (< 1 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 22735#L709-3 [3677] L709-3-->L714-3: Formula: (< 1 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 22734#L714-3 [3678] L714-3-->L719-3: Formula: (< 1 v_~E_4~0_31) InVars {~E_4~0=v_~E_4~0_31} OutVars{~E_4~0=v_~E_4~0_31} AuxVars[] AssignedVars[] 22733#L719-3 [3680] L719-3-->L724-3: Formula: (> 1 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 22732#L724-3 [2818] L724-3-->L454-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_23} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 22726#L454-1 [2466] L454-1-->L486-1: Formula: (and (= 0 v_~m_st~0_20) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26 1)) InVars {~m_st~0=v_~m_st~0_20} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 22725#L486-1 [3838] L486-1-->L949: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret15, ULTIMATE.start_start_simulation_~tmp~3] 22724#L949 [3688] L949-->L949-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_1) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} AuxVars[] AssignedVars[] 21875#L949-1 [2479] L949-1-->L454-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_1} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 21849#L454-2 [2438] L454-2-->L486-2: Formula: (and (= v_~m_st~0_2 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4 1)) InVars {~m_st~0=v_~m_st~0_2} OutVars{~m_st~0=v_~m_st~0_2, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 21680#L486-2 [3840] L486-2-->L904: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 21785#L904 [2393] L904-->L911: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 21821#L911 [3851] L911-->L930-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_6|, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 21688#L930-1 312.69/160.49 [2019-03-28 12:22:04,685 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.49 [2019-03-28 12:22:04,685 INFO L82 PathProgramCache]: Analyzing trace with hash 626004627, now seen corresponding path program 1 times 312.69/160.49 [2019-03-28 12:22:04,685 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.49 [2019-03-28 12:22:04,685 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.49 [2019-03-28 12:22:04,686 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:04,686 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:04,686 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:04,691 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.49 [2019-03-28 12:22:04,746 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.49 [2019-03-28 12:22:04,746 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.49 [2019-03-28 12:22:04,746 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 312.69/160.49 [2019-03-28 12:22:04,746 INFO L799 eck$LassoCheckResult]: stem already infeasible 312.69/160.49 [2019-03-28 12:22:04,747 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.49 [2019-03-28 12:22:04,747 INFO L82 PathProgramCache]: Analyzing trace with hash 900274352, now seen corresponding path program 1 times 312.69/160.49 [2019-03-28 12:22:04,747 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.49 [2019-03-28 12:22:04,747 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.49 [2019-03-28 12:22:04,748 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:04,748 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:04,748 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:04,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.49 [2019-03-28 12:22:04,772 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.49 [2019-03-28 12:22:04,772 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.49 [2019-03-28 12:22:04,772 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 312.69/160.49 [2019-03-28 12:22:04,773 INFO L811 eck$LassoCheckResult]: loop already infeasible 312.69/160.49 [2019-03-28 12:22:04,773 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. 312.69/160.49 [2019-03-28 12:22:04,773 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 312.69/160.49 [2019-03-28 12:22:04,773 INFO L87 Difference]: Start difference. First operand 1463 states and 2687 transitions. cyclomatic complexity: 1225 Second operand 6 states. 312.69/160.49 [2019-03-28 12:22:05,504 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.49 [2019-03-28 12:22:05,504 INFO L93 Difference]: Finished difference Result 1463 states and 2614 transitions. 312.69/160.49 [2019-03-28 12:22:05,505 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. 312.69/160.49 [2019-03-28 12:22:05,505 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1463 states and 2614 transitions. 312.69/160.49 [2019-03-28 12:22:05,511 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1398 312.69/160.49 [2019-03-28 12:22:05,519 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1463 states to 1463 states and 2614 transitions. 312.69/160.49 [2019-03-28 12:22:05,519 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1463 312.69/160.49 [2019-03-28 12:22:05,520 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1463 312.69/160.49 [2019-03-28 12:22:05,520 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1463 states and 2614 transitions. 312.69/160.49 [2019-03-28 12:22:05,522 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.49 [2019-03-28 12:22:05,522 INFO L706 BuchiCegarLoop]: Abstraction has 1463 states and 2614 transitions. 312.69/160.49 [2019-03-28 12:22:05,523 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1463 states and 2614 transitions. 312.69/160.49 [2019-03-28 12:22:05,541 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1463 to 1463. 312.69/160.49 [2019-03-28 12:22:05,542 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1463 states. 312.69/160.49 [2019-03-28 12:22:05,545 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1463 states to 1463 states and 2614 transitions. 312.69/160.49 [2019-03-28 12:22:05,545 INFO L729 BuchiCegarLoop]: Abstraction has 1463 states and 2614 transitions. 312.69/160.49 [2019-03-28 12:22:05,545 INFO L609 BuchiCegarLoop]: Abstraction has 1463 states and 2614 transitions. 312.69/160.49 [2019-03-28 12:22:05,545 INFO L442 BuchiCegarLoop]: ======== Iteration 22============ 312.69/160.49 [2019-03-28 12:22:05,545 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1463 states and 2614 transitions. 312.69/160.49 [2019-03-28 12:22:05,549 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1398 312.69/160.49 [2019-03-28 12:22:05,549 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.49 [2019-03-28 12:22:05,549 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.49 [2019-03-28 12:22:05,551 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.49 [2019-03-28 12:22:05,551 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.49 [2019-03-28 12:22:05,552 INFO L794 eck$LassoCheckResult]: Stem: 24921#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 24733#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 24734#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 24797#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 24798#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 24735#L431-1 [2355] L431-1-->L436-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 24736#L436-1 [2735] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 24775#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 24776#L601-1 [3235] L601-1-->L606-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 24779#L606-1 [3236] L606-1-->L611-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 24664#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 24665#L616-1 [3240] L616-1-->L621-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 24546#L621-1 [3242] L621-1-->L626-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 24547#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 24636#L631-1 [3246] L631-1-->L636-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 24637#L636-1 [3248] L636-1-->L641-1: Formula: (> v_~E_2~0_4 0) InVars {~E_2~0=v_~E_2~0_4} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[] 24817#L641-1 [3251] L641-1-->L646-1: Formula: (> v_~E_3~0_4 0) InVars {~E_3~0=v_~E_3~0_4} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[] 24818#L646-1 [3253] L646-1-->L651-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 24767#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 24768#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 24993#L294 [3256] L294-->L294-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 25026#L294-2 [2905] L294-2-->L305: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 25040#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 25041#L745 [2925] L745-->L745-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_6) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} AuxVars[] AssignedVars[] 25048#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 24711#L313 [3262] L313-->L313-2: Formula: (< v_~t1_pc~0_3 1) InVars {~t1_pc~0=v_~t1_pc~0_3} OutVars{~t1_pc~0=v_~t1_pc~0_3} AuxVars[] AssignedVars[] 24712#L313-2 [2314] L313-2-->L324: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 24710#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 24562#L753 [3266] L753-->L753-2: Formula: (and (= v_~t1_st~0_6 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_5)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_5, ~t1_st~0=v_~t1_st~0_6} AuxVars[] AssignedVars[~t1_st~0] 24563#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 24567#L332 [3269] L332-->L332-2: Formula: (> v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 24743#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 24741#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 24742#L761 [3273] L761-->L761-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_5) (= v_~t2_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5, ~t2_st~0=v_~t2_st~0_6} AuxVars[] AssignedVars[~t2_st~0] 24763#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 24764#L351 [3275] L351-->L351-2: Formula: (< 1 v_~t3_pc~0_3) InVars {~t3_pc~0=v_~t3_pc~0_3} OutVars{~t3_pc~0=v_~t3_pc~0_3} AuxVars[] AssignedVars[] 24863#L351-2 [2543] L351-2-->L362: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 24864#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 24882#L769 [3279] L769-->L769-2: Formula: (and (= v_~t3_st~0_6 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_5)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} OutVars{~t3_st~0=v_~t3_st~0_6, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} AuxVars[] AssignedVars[~t3_st~0] 24889#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 24890#L370 [3281] L370-->L370-2: Formula: (> v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 24980#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 24976#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 24977#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 24992#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 24627#L389 [2193] L389-->L390: Formula: (= 1 v_~t5_pc~0_2) InVars {~t5_pc~0=v_~t5_pc~0_2} OutVars{~t5_pc~0=v_~t5_pc~0_2} AuxVars[] AssignedVars[] 24628#L390 [2343] L390-->L400: Formula: (and (= v_~E_5~0_5 1) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4 1)) InVars {~E_5~0=v_~E_5~0_5} OutVars{~E_5~0=v_~E_5~0_5, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 24596#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 24623#L785 [3291] L785-->L785-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_5) (= v_~t5_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} OutVars{~t5_st~0=v_~t5_st~0_6, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} AuxVars[] AssignedVars[~t5_st~0] 24643#L785-2 [3293] L785-2-->L669-1: Formula: (> 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 24645#L669-1 [3294] L669-1-->L674-1: Formula: (< 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 24815#L674-1 [3296] L674-1-->L679-1: Formula: (< 1 v_~T2_E~0_7) InVars {~T2_E~0=v_~T2_E~0_7} OutVars{~T2_E~0=v_~T2_E~0_7} AuxVars[] AssignedVars[] 24816#L679-1 [3299] L679-1-->L684-1: Formula: (< v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 24765#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 24766#L689-1 [3302] L689-1-->L694-1: Formula: (> v_~T5_E~0_7 1) InVars {~T5_E~0=v_~T5_E~0_7} OutVars{~T5_E~0=v_~T5_E~0_7} AuxVars[] AssignedVars[] 24915#L694-1 [3305] L694-1-->L699-1: Formula: (< v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 24687#L699-1 [3306] L699-1-->L704-1: Formula: (> v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 24688#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 24535#L709-1 [3310] L709-1-->L714-1: Formula: (> v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 24536#L714-1 [3313] L714-1-->L719-1: Formula: (> v_~E_4~0_9 1) InVars {~E_4~0=v_~E_4~0_9} OutVars{~E_4~0=v_~E_4~0_9} AuxVars[] AssignedVars[] 24630#L719-1 [2198] L719-1-->L930-1: Formula: (and (= v_~E_5~0_8 1) (= v_~E_5~0_7 2)) InVars {~E_5~0=v_~E_5~0_8} OutVars{~E_5~0=v_~E_5~0_7} AuxVars[] AssignedVars[~E_5~0] 24631#L930-1 312.69/160.49 [2019-03-28 12:22:05,553 INFO L796 eck$LassoCheckResult]: Loop: 24631#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 25667#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 25665#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 25659#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 24676#L501 [3784] L501-->L601-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 24677#L601-2 [2768] L601-2-->L601-4: Formula: (and (= v_~M_E~0_8 1) (= 0 v_~M_E~0_9)) InVars {~M_E~0=v_~M_E~0_9} OutVars{~M_E~0=v_~M_E~0_8} AuxVars[] AssignedVars[~M_E~0] 24991#L601-4 [3322] L601-4-->L606-3: Formula: (> v_~T1_E~0_10 0) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 24782#L606-3 [3326] L606-3-->L611-3: Formula: (< 0 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 24674#L611-3 [2256] L611-3-->L616-3: Formula: (and (= v_~T3_E~0_8 1) (= v_~T3_E~0_9 0)) InVars {~T3_E~0=v_~T3_E~0_9} OutVars{~T3_E~0=v_~T3_E~0_8} AuxVars[] AssignedVars[~T3_E~0] 24675#L616-3 [3339] L616-3-->L621-3: Formula: (> v_~T4_E~0_10 0) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 24553#L621-3 [3346] L621-3-->L626-3: Formula: (< 0 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 24554#L626-3 [2580] L626-3-->L631-3: Formula: (and (= v_~E_M~0_24 1) (= 0 v_~E_M~0_25)) InVars {~E_M~0=v_~E_M~0_25} OutVars{~E_M~0=v_~E_M~0_24} AuxVars[] AssignedVars[~E_M~0] 24612#L631-3 [3365] L631-3-->L636-3: Formula: (< 0 v_~E_1~0_26) InVars {~E_1~0=v_~E_1~0_26} OutVars{~E_1~0=v_~E_1~0_26} AuxVars[] AssignedVars[] 24613#L636-3 [3376] L636-3-->L641-3: Formula: (< 0 v_~E_2~0_26) InVars {~E_2~0=v_~E_2~0_26} OutVars{~E_2~0=v_~E_2~0_26} AuxVars[] AssignedVars[] 24807#L641-3 [3388] L641-3-->L646-3: Formula: (< 0 v_~E_3~0_26) InVars {~E_3~0=v_~E_3~0_26} OutVars{~E_3~0=v_~E_3~0_26} AuxVars[] AssignedVars[] 24808#L646-3 [3401] L646-3-->L651-3: Formula: (< 0 v_~E_4~0_26) InVars {~E_4~0=v_~E_4~0_26} OutVars{~E_4~0=v_~E_4~0_26} AuxVars[] AssignedVars[] 24757#L651-3 [3410] L651-3-->L656-3: Formula: (> 0 v_~E_5~0_26) InVars {~E_5~0=v_~E_5~0_26} OutVars{~E_5~0=v_~E_5~0_26} AuxVars[] AssignedVars[] 24758#L656-3 [2767] L656-3-->L294-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_37, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_37, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_22|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_22|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_22|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_37, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_37, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_22|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_22|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_22|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_22|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_37, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_37, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_37} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 24990#L294-21 [3426] L294-21-->L294-23: Formula: (< v_~m_pc~0_22 1) InVars {~m_pc~0=v_~m_pc~0_22} OutVars{~m_pc~0=v_~m_pc~0_22} AuxVars[] AssignedVars[] 25000#L294-23 [2803] L294-23-->L305-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_41 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_41} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 25001#L305-7 [3806] L305-7-->L745-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 25014#L745-21 [2835] L745-21-->L745-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_42) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} AuxVars[] AssignedVars[] 25015#L745-23 [2838] L745-23-->L313-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_43, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 24660#L313-21 [3469] L313-21-->L313-23: Formula: (< v_~t1_pc~0_22 1) InVars {~t1_pc~0=v_~t1_pc~0_22} OutVars{~t1_pc~0=v_~t1_pc~0_22} AuxVars[] AssignedVars[] 24661#L313-23 [2249] L313-23-->L324-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 24666#L324-7 [3813] L324-7-->L753-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 24704#L753-21 [2292] L753-21-->L753-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} AuxVars[] AssignedVars[] 24705#L753-23 [2297] L753-23-->L332-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_22|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 24709#L332-21 [3510] L332-21-->L332-23: Formula: (> 1 v_~t2_pc~0_22) InVars {~t2_pc~0=v_~t2_pc~0_22} OutVars{~t2_pc~0=v_~t2_pc~0_22} AuxVars[] AssignedVars[] 24794#L332-23 [2476] L332-23-->L343-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 24819#L343-7 [3820] L343-7-->L761-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 24827#L761-21 [3538] L761-21-->L761-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___1~0_41 0) (= v_~t2_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41, ~t2_st~0=v_~t2_st~0_19} AuxVars[] AssignedVars[~t2_st~0] 24828#L761-23 [2493] L761-23-->L351-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_22|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 24829#L351-21 [3552] L351-21-->L351-23: Formula: (< v_~t3_pc~0_22 1) InVars {~t3_pc~0=v_~t3_pc~0_22} OutVars{~t3_pc~0=v_~t3_pc~0_22} AuxVars[] AssignedVars[] 24918#L351-23 [2660] L351-23-->L362-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 24847#L362-7 [3827] L362-7-->L769-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 24848#L769-21 [2534] L769-21-->L769-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} AuxVars[] AssignedVars[] 24854#L769-23 [2537] L769-23-->L370-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_43, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 24857#L370-21 [3594] L370-21-->L370-23: Formula: (< 1 v_~t4_pc~0_22) InVars {~t4_pc~0=v_~t4_pc~0_22} OutVars{~t4_pc~0=v_~t4_pc~0_22} AuxVars[] AssignedVars[] 25033#L370-23 [2934] L370-23-->L381-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 24970#L381-7 [3834] L381-7-->L777-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 24948#L777-21 [2705] L777-21-->L777-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} AuxVars[] AssignedVars[] 24949#L777-23 [2708] L777-23-->L389-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_22|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 24565#L389-21 [2132] L389-21-->L390-7: Formula: (= v_~t5_pc~0_21 1) InVars {~t5_pc~0=v_~t5_pc~0_21} OutVars{~t5_pc~0=v_~t5_pc~0_21} AuxVars[] AssignedVars[] 24566#L390-7 [2330] L390-7-->L400-7: Formula: (and (= 1 v_~E_5~0_27) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46 1)) InVars {~E_5~0=v_~E_5~0_27} OutVars{~E_5~0=v_~E_5~0_27, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 24540#L400-7 [3837] L400-7-->L785-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 24581#L785-21 [3654] L785-21-->L785-23: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_41 0) (= v_~t5_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} OutVars{~t5_st~0=v_~t5_st~0_19, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} AuxVars[] AssignedVars[~t5_st~0] 24590#L785-23 [2161] L785-23-->L669-3: Formula: (and (= v_~M_E~0_12 1) (= v_~M_E~0_11 2)) InVars {~M_E~0=v_~M_E~0_12} OutVars{~M_E~0=v_~M_E~0_11} AuxVars[] AssignedVars[~M_E~0] 24592#L669-3 [3660] L669-3-->L674-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 24820#L674-3 [3662] L674-3-->L679-3: Formula: (< 1 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 24821#L679-3 [3664] L679-3-->L684-3: Formula: (< 1 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 24754#L684-3 [3666] L684-3-->L689-3: Formula: (> v_~T4_E~0_13 1) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 24755#L689-3 [3668] L689-3-->L694-3: Formula: (< 1 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 24778#L694-3 [2405] L694-3-->L699-3: Formula: (and (= 1 v_~E_M~0_30) (= v_~E_M~0_29 2)) InVars {~E_M~0=v_~E_M~0_30} OutVars{~E_M~0=v_~E_M~0_29} AuxVars[] AssignedVars[~E_M~0] 24662#L699-3 [3673] L699-3-->L704-3: Formula: (< 1 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 24663#L704-3 [3675] L704-3-->L709-3: Formula: (< 1 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 24544#L709-3 [3677] L709-3-->L714-3: Formula: (< 1 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 24545#L714-3 [3678] L714-3-->L719-3: Formula: (< 1 v_~E_4~0_31) InVars {~E_4~0=v_~E_4~0_31} OutVars{~E_4~0=v_~E_4~0_31} AuxVars[] AssignedVars[] 24634#L719-3 [3680] L719-3-->L724-3: Formula: (> 1 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 24635#L724-3 [2818] L724-3-->L454-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_23} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 24812#L454-1 [2466] L454-1-->L486-1: Formula: (and (= 0 v_~m_st~0_20) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26 1)) InVars {~m_st~0=v_~m_st~0_20} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 24621#L486-1 [3838] L486-1-->L949: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret15, ULTIMATE.start_start_simulation_~tmp~3] 24762#L949 [3688] L949-->L949-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_1) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} AuxVars[] AssignedVars[] 24822#L949-1 [2479] L949-1-->L454-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_1} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 24799#L454-2 [2438] L454-2-->L486-2: Formula: (and (= v_~m_st~0_2 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4 1)) InVars {~m_st~0=v_~m_st~0_2} OutVars{~m_st~0=v_~m_st~0_2, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 24626#L486-2 [3840] L486-2-->L904: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 25679#L904 [2393] L904-->L911: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 25674#L911 [3851] L911-->L930-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_6|, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 24631#L930-1 312.69/160.49 [2019-03-28 12:22:05,554 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.49 [2019-03-28 12:22:05,554 INFO L82 PathProgramCache]: Analyzing trace with hash -1485285742, now seen corresponding path program 1 times 312.69/160.49 [2019-03-28 12:22:05,554 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.49 [2019-03-28 12:22:05,554 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.49 [2019-03-28 12:22:05,555 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:05,555 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:05,555 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:05,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.49 [2019-03-28 12:22:05,610 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.49 [2019-03-28 12:22:05,610 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.49 [2019-03-28 12:22:05,610 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 312.69/160.49 [2019-03-28 12:22:05,611 INFO L799 eck$LassoCheckResult]: stem already infeasible 312.69/160.49 [2019-03-28 12:22:05,611 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.49 [2019-03-28 12:22:05,611 INFO L82 PathProgramCache]: Analyzing trace with hash 900274352, now seen corresponding path program 2 times 312.69/160.49 [2019-03-28 12:22:05,611 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.49 [2019-03-28 12:22:05,611 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.49 [2019-03-28 12:22:05,612 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:05,612 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:05,613 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:05,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.49 [2019-03-28 12:22:05,634 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.49 [2019-03-28 12:22:05,634 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.49 [2019-03-28 12:22:05,634 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 312.69/160.49 [2019-03-28 12:22:05,635 INFO L811 eck$LassoCheckResult]: loop already infeasible 312.69/160.49 [2019-03-28 12:22:05,635 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. 312.69/160.49 [2019-03-28 12:22:05,635 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 312.69/160.49 [2019-03-28 12:22:05,636 INFO L87 Difference]: Start difference. First operand 1463 states and 2614 transitions. cyclomatic complexity: 1152 Second operand 6 states. 312.69/160.49 [2019-03-28 12:22:07,379 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.49 [2019-03-28 12:22:07,380 INFO L93 Difference]: Finished difference Result 3392 states and 6176 transitions. 312.69/160.49 [2019-03-28 12:22:07,380 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. 312.69/160.49 [2019-03-28 12:22:07,380 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3392 states and 6176 transitions. 312.69/160.49 [2019-03-28 12:22:07,393 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3327 312.69/160.49 [2019-03-28 12:22:07,413 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3392 states to 3392 states and 6176 transitions. 312.69/160.49 [2019-03-28 12:22:07,413 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3392 312.69/160.49 [2019-03-28 12:22:07,415 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3392 312.69/160.49 [2019-03-28 12:22:07,415 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3392 states and 6176 transitions. 312.69/160.49 [2019-03-28 12:22:07,419 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.49 [2019-03-28 12:22:07,419 INFO L706 BuchiCegarLoop]: Abstraction has 3392 states and 6176 transitions. 312.69/160.49 [2019-03-28 12:22:07,420 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3392 states and 6176 transitions. 312.69/160.49 [2019-03-28 12:22:07,440 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3392 to 1465. 312.69/160.49 [2019-03-28 12:22:07,441 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1465 states. 312.69/160.49 [2019-03-28 12:22:07,443 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1465 states to 1465 states and 2588 transitions. 312.69/160.49 [2019-03-28 12:22:07,444 INFO L729 BuchiCegarLoop]: Abstraction has 1465 states and 2588 transitions. 312.69/160.49 [2019-03-28 12:22:07,444 INFO L609 BuchiCegarLoop]: Abstraction has 1465 states and 2588 transitions. 312.69/160.49 [2019-03-28 12:22:07,444 INFO L442 BuchiCegarLoop]: ======== Iteration 23============ 312.69/160.49 [2019-03-28 12:22:07,444 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1465 states and 2588 transitions. 312.69/160.49 [2019-03-28 12:22:07,447 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1400 312.69/160.49 [2019-03-28 12:22:07,448 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.49 [2019-03-28 12:22:07,448 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.49 [2019-03-28 12:22:07,449 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.49 [2019-03-28 12:22:07,449 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.49 [2019-03-28 12:22:07,450 INFO L794 eck$LassoCheckResult]: Stem: 29804#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 29618#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 29619#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 29681#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 29682#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 29620#L431-1 [2355] L431-1-->L436-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 29621#L436-1 [2735] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 29659#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 29660#L601-1 [3235] L601-1-->L606-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 29663#L606-1 [3236] L606-1-->L611-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 29547#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 29548#L616-1 [3240] L616-1-->L621-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 29431#L621-1 [3242] L621-1-->L626-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 29432#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 29519#L631-1 [3246] L631-1-->L636-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 29520#L636-1 [3248] L636-1-->L641-1: Formula: (> v_~E_2~0_4 0) InVars {~E_2~0=v_~E_2~0_4} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[] 29702#L641-1 [3251] L641-1-->L646-1: Formula: (> v_~E_3~0_4 0) InVars {~E_3~0=v_~E_3~0_4} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[] 29703#L646-1 [3253] L646-1-->L651-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 29651#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 29652#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 29868#L294 [3256] L294-->L294-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 29902#L294-2 [2905] L294-2-->L305: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 29920#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 29921#L745 [2925] L745-->L745-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_6) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} AuxVars[] AssignedVars[] 29933#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 29598#L313 [3262] L313-->L313-2: Formula: (< v_~t1_pc~0_3 1) InVars {~t1_pc~0=v_~t1_pc~0_3} OutVars{~t1_pc~0=v_~t1_pc~0_3} AuxVars[] AssignedVars[] 29599#L313-2 [2314] L313-2-->L324: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 29597#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 29447#L753 [2130] L753-->L753-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} AuxVars[] AssignedVars[] 29448#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 29452#L332 [3269] L332-->L332-2: Formula: (> v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 29628#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 29626#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 29627#L761 [3273] L761-->L761-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_5) (= v_~t2_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5, ~t2_st~0=v_~t2_st~0_6} AuxVars[] AssignedVars[~t2_st~0] 29647#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 29648#L351 [3275] L351-->L351-2: Formula: (< 1 v_~t3_pc~0_3) InVars {~t3_pc~0=v_~t3_pc~0_3} OutVars{~t3_pc~0=v_~t3_pc~0_3} AuxVars[] AssignedVars[] 29750#L351-2 [2543] L351-2-->L362: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 29751#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 29768#L769 [3279] L769-->L769-2: Formula: (and (= v_~t3_st~0_6 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_5)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} OutVars{~t3_st~0=v_~t3_st~0_6, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} AuxVars[] AssignedVars[~t3_st~0] 29772#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 29773#L370 [3281] L370-->L370-2: Formula: (> v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 29856#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 29852#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 29853#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 29867#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 29510#L389 [2193] L389-->L390: Formula: (= 1 v_~t5_pc~0_2) InVars {~t5_pc~0=v_~t5_pc~0_2} OutVars{~t5_pc~0=v_~t5_pc~0_2} AuxVars[] AssignedVars[] 29511#L390 [2343] L390-->L400: Formula: (and (= v_~E_5~0_5 1) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4 1)) InVars {~E_5~0=v_~E_5~0_5} OutVars{~E_5~0=v_~E_5~0_5, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 29480#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 29506#L785 [3291] L785-->L785-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_5) (= v_~t5_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} OutVars{~t5_st~0=v_~t5_st~0_6, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} AuxVars[] AssignedVars[~t5_st~0] 29526#L785-2 [3293] L785-2-->L669-1: Formula: (> 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 29529#L669-1 [3294] L669-1-->L674-1: Formula: (< 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 29700#L674-1 [3296] L674-1-->L679-1: Formula: (< 1 v_~T2_E~0_7) InVars {~T2_E~0=v_~T2_E~0_7} OutVars{~T2_E~0=v_~T2_E~0_7} AuxVars[] AssignedVars[] 29701#L679-1 [3299] L679-1-->L684-1: Formula: (< v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 29649#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 29650#L689-1 [3302] L689-1-->L694-1: Formula: (> v_~T5_E~0_7 1) InVars {~T5_E~0=v_~T5_E~0_7} OutVars{~T5_E~0=v_~T5_E~0_7} AuxVars[] AssignedVars[] 29798#L694-1 [3305] L694-1-->L699-1: Formula: (< v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 29570#L699-1 [3306] L699-1-->L704-1: Formula: (> v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 29571#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 29420#L709-1 [3310] L709-1-->L714-1: Formula: (> v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 29421#L714-1 [3313] L714-1-->L719-1: Formula: (> v_~E_4~0_9 1) InVars {~E_4~0=v_~E_4~0_9} OutVars{~E_4~0=v_~E_4~0_9} AuxVars[] AssignedVars[] 29513#L719-1 [2198] L719-1-->L930-1: Formula: (and (= v_~E_5~0_8 1) (= v_~E_5~0_7 2)) InVars {~E_5~0=v_~E_5~0_8} OutVars{~E_5~0=v_~E_5~0_7} AuxVars[] AssignedVars[~E_5~0] 29514#L930-1 312.69/160.49 [2019-03-28 12:22:07,451 INFO L796 eck$LassoCheckResult]: Loop: 29514#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 30096#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 30093#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 30086#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 30083#L501 [3784] L501-->L601-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 30084#L601-2 [2768] L601-2-->L601-4: Formula: (and (= v_~M_E~0_8 1) (= 0 v_~M_E~0_9)) InVars {~M_E~0=v_~M_E~0_9} OutVars{~M_E~0=v_~M_E~0_8} AuxVars[] AssignedVars[~M_E~0] 30564#L601-4 [3322] L601-4-->L606-3: Formula: (> v_~T1_E~0_10 0) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 30563#L606-3 [3326] L606-3-->L611-3: Formula: (< 0 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 30562#L611-3 [2256] L611-3-->L616-3: Formula: (and (= v_~T3_E~0_8 1) (= v_~T3_E~0_9 0)) InVars {~T3_E~0=v_~T3_E~0_9} OutVars{~T3_E~0=v_~T3_E~0_8} AuxVars[] AssignedVars[~T3_E~0] 30561#L616-3 [3339] L616-3-->L621-3: Formula: (> v_~T4_E~0_10 0) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 30560#L621-3 [3346] L621-3-->L626-3: Formula: (< 0 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 30559#L626-3 [2580] L626-3-->L631-3: Formula: (and (= v_~E_M~0_24 1) (= 0 v_~E_M~0_25)) InVars {~E_M~0=v_~E_M~0_25} OutVars{~E_M~0=v_~E_M~0_24} AuxVars[] AssignedVars[~E_M~0] 30558#L631-3 [3365] L631-3-->L636-3: Formula: (< 0 v_~E_1~0_26) InVars {~E_1~0=v_~E_1~0_26} OutVars{~E_1~0=v_~E_1~0_26} AuxVars[] AssignedVars[] 30557#L636-3 [3376] L636-3-->L641-3: Formula: (< 0 v_~E_2~0_26) InVars {~E_2~0=v_~E_2~0_26} OutVars{~E_2~0=v_~E_2~0_26} AuxVars[] AssignedVars[] 30556#L641-3 [3388] L641-3-->L646-3: Formula: (< 0 v_~E_3~0_26) InVars {~E_3~0=v_~E_3~0_26} OutVars{~E_3~0=v_~E_3~0_26} AuxVars[] AssignedVars[] 30555#L646-3 [3401] L646-3-->L651-3: Formula: (< 0 v_~E_4~0_26) InVars {~E_4~0=v_~E_4~0_26} OutVars{~E_4~0=v_~E_4~0_26} AuxVars[] AssignedVars[] 30554#L651-3 [3410] L651-3-->L656-3: Formula: (> 0 v_~E_5~0_26) InVars {~E_5~0=v_~E_5~0_26} OutVars{~E_5~0=v_~E_5~0_26} AuxVars[] AssignedVars[] 30553#L656-3 [2767] L656-3-->L294-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_37, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_37, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_22|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_22|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_22|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_37, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_37, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_22|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_22|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_22|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_22|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_37, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_37, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_37} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 30521#L294-21 [3426] L294-21-->L294-23: Formula: (< v_~m_pc~0_22 1) InVars {~m_pc~0=v_~m_pc~0_22} OutVars{~m_pc~0=v_~m_pc~0_22} AuxVars[] AssignedVars[] 30520#L294-23 [2803] L294-23-->L305-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_41 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_41} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 30519#L305-7 [3806] L305-7-->L745-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 30518#L745-21 [2835] L745-21-->L745-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_42) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} AuxVars[] AssignedVars[] 30517#L745-23 [2838] L745-23-->L313-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_43, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 30516#L313-21 [3469] L313-21-->L313-23: Formula: (< v_~t1_pc~0_22 1) InVars {~t1_pc~0=v_~t1_pc~0_22} OutVars{~t1_pc~0=v_~t1_pc~0_22} AuxVars[] AssignedVars[] 30229#L313-23 [2249] L313-23-->L324-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 30515#L324-7 [3813] L324-7-->L753-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 30513#L753-21 [2292] L753-21-->L753-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} AuxVars[] AssignedVars[] 30511#L753-23 [2297] L753-23-->L332-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_22|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 30508#L332-21 [3510] L332-21-->L332-23: Formula: (> 1 v_~t2_pc~0_22) InVars {~t2_pc~0=v_~t2_pc~0_22} OutVars{~t2_pc~0=v_~t2_pc~0_22} AuxVars[] AssignedVars[] 30506#L332-23 [2476] L332-23-->L343-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 30504#L343-7 [3820] L343-7-->L761-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 30503#L761-21 [3538] L761-21-->L761-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___1~0_41 0) (= v_~t2_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41, ~t2_st~0=v_~t2_st~0_19} AuxVars[] AssignedVars[~t2_st~0] 30502#L761-23 [2493] L761-23-->L351-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_22|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 30500#L351-21 [3552] L351-21-->L351-23: Formula: (< v_~t3_pc~0_22 1) InVars {~t3_pc~0=v_~t3_pc~0_22} OutVars{~t3_pc~0=v_~t3_pc~0_22} AuxVars[] AssignedVars[] 30499#L351-23 [2660] L351-23-->L362-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 30498#L362-7 [3827] L362-7-->L769-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 30497#L769-21 [2534] L769-21-->L769-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} AuxVars[] AssignedVars[] 30495#L769-23 [2537] L769-23-->L370-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_43, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 30493#L370-21 [3594] L370-21-->L370-23: Formula: (< 1 v_~t4_pc~0_22) InVars {~t4_pc~0=v_~t4_pc~0_22} OutVars{~t4_pc~0=v_~t4_pc~0_22} AuxVars[] AssignedVars[] 30490#L370-23 [2934] L370-23-->L381-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 30488#L381-7 [3834] L381-7-->L777-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 30487#L777-21 [2705] L777-21-->L777-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} AuxVars[] AssignedVars[] 30485#L777-23 [2708] L777-23-->L389-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_22|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 30483#L389-21 [2132] L389-21-->L390-7: Formula: (= v_~t5_pc~0_21 1) InVars {~t5_pc~0=v_~t5_pc~0_21} OutVars{~t5_pc~0=v_~t5_pc~0_21} AuxVars[] AssignedVars[] 30480#L390-7 [2330] L390-7-->L400-7: Formula: (and (= 1 v_~E_5~0_27) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46 1)) InVars {~E_5~0=v_~E_5~0_27} OutVars{~E_5~0=v_~E_5~0_27, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 30479#L400-7 [3837] L400-7-->L785-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 30476#L785-21 [3654] L785-21-->L785-23: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_41 0) (= v_~t5_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} OutVars{~t5_st~0=v_~t5_st~0_19, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} AuxVars[] AssignedVars[~t5_st~0] 30474#L785-23 [2161] L785-23-->L669-3: Formula: (and (= v_~M_E~0_12 1) (= v_~M_E~0_11 2)) InVars {~M_E~0=v_~M_E~0_12} OutVars{~M_E~0=v_~M_E~0_11} AuxVars[] AssignedVars[~M_E~0] 30472#L669-3 [3660] L669-3-->L674-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 30470#L674-3 [3662] L674-3-->L679-3: Formula: (< 1 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 30468#L679-3 [3664] L679-3-->L684-3: Formula: (< 1 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 30467#L684-3 [3666] L684-3-->L689-3: Formula: (> v_~T4_E~0_13 1) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 30466#L689-3 [3668] L689-3-->L694-3: Formula: (< 1 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 30465#L694-3 [2405] L694-3-->L699-3: Formula: (and (= 1 v_~E_M~0_30) (= v_~E_M~0_29 2)) InVars {~E_M~0=v_~E_M~0_30} OutVars{~E_M~0=v_~E_M~0_29} AuxVars[] AssignedVars[~E_M~0] 30464#L699-3 [3673] L699-3-->L704-3: Formula: (< 1 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 30462#L704-3 [3675] L704-3-->L709-3: Formula: (< 1 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 30460#L709-3 [3677] L709-3-->L714-3: Formula: (< 1 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 30458#L714-3 [3678] L714-3-->L719-3: Formula: (< 1 v_~E_4~0_31) InVars {~E_4~0=v_~E_4~0_31} OutVars{~E_4~0=v_~E_4~0_31} AuxVars[] AssignedVars[] 30456#L719-3 [3680] L719-3-->L724-3: Formula: (> 1 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 30454#L724-3 [2818] L724-3-->L454-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_23} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 30343#L454-1 [2466] L454-1-->L486-1: Formula: (and (= 0 v_~m_st~0_20) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26 1)) InVars {~m_st~0=v_~m_st~0_20} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 30339#L486-1 [3838] L486-1-->L949: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret15, ULTIMATE.start_start_simulation_~tmp~3] 30336#L949 [3688] L949-->L949-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_1) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} AuxVars[] AssignedVars[] 30337#L949-1 [2479] L949-1-->L454-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_1} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 30356#L454-2 [2438] L454-2-->L486-2: Formula: (and (= v_~m_st~0_2 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4 1)) InVars {~m_st~0=v_~m_st~0_2} OutVars{~m_st~0=v_~m_st~0_2, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 30352#L486-2 [3840] L486-2-->L904: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 30351#L904 [2393] L904-->L911: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 30350#L911 [3851] L911-->L930-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_6|, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 29514#L930-1 312.69/160.49 [2019-03-28 12:22:07,451 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.49 [2019-03-28 12:22:07,451 INFO L82 PathProgramCache]: Analyzing trace with hash 975573538, now seen corresponding path program 1 times 312.69/160.49 [2019-03-28 12:22:07,451 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.49 [2019-03-28 12:22:07,452 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.49 [2019-03-28 12:22:07,452 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:07,453 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:07,453 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:07,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.49 [2019-03-28 12:22:07,475 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.49 [2019-03-28 12:22:07,475 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.49 [2019-03-28 12:22:07,475 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 312.69/160.49 [2019-03-28 12:22:07,476 INFO L799 eck$LassoCheckResult]: stem already infeasible 312.69/160.49 [2019-03-28 12:22:07,476 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.49 [2019-03-28 12:22:07,476 INFO L82 PathProgramCache]: Analyzing trace with hash 900274352, now seen corresponding path program 3 times 312.69/160.49 [2019-03-28 12:22:07,476 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.49 [2019-03-28 12:22:07,476 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.49 [2019-03-28 12:22:07,477 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:07,477 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:07,477 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:07,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.49 [2019-03-28 12:22:07,500 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.49 [2019-03-28 12:22:07,500 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.49 [2019-03-28 12:22:07,500 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 312.69/160.49 [2019-03-28 12:22:07,500 INFO L811 eck$LassoCheckResult]: loop already infeasible 312.69/160.49 [2019-03-28 12:22:07,501 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 312.69/160.49 [2019-03-28 12:22:07,501 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 312.69/160.49 [2019-03-28 12:22:07,501 INFO L87 Difference]: Start difference. First operand 1465 states and 2588 transitions. cyclomatic complexity: 1124 Second operand 3 states. 312.69/160.49 [2019-03-28 12:22:08,230 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.49 [2019-03-28 12:22:08,230 INFO L93 Difference]: Finished difference Result 2784 states and 4905 transitions. 312.69/160.49 [2019-03-28 12:22:08,230 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 312.69/160.49 [2019-03-28 12:22:08,231 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2784 states and 4905 transitions. 312.69/160.49 [2019-03-28 12:22:08,240 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2720 312.69/160.49 [2019-03-28 12:22:08,251 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2784 states to 2784 states and 4905 transitions. 312.69/160.49 [2019-03-28 12:22:08,252 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2784 312.69/160.49 [2019-03-28 12:22:08,253 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2784 312.69/160.49 [2019-03-28 12:22:08,253 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2784 states and 4905 transitions. 312.69/160.49 [2019-03-28 12:22:08,256 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.49 [2019-03-28 12:22:08,256 INFO L706 BuchiCegarLoop]: Abstraction has 2784 states and 4905 transitions. 312.69/160.49 [2019-03-28 12:22:08,257 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2784 states and 4905 transitions. 312.69/160.49 [2019-03-28 12:22:08,281 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2784 to 2692. 312.69/160.49 [2019-03-28 12:22:08,282 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2692 states. 312.69/160.49 [2019-03-28 12:22:08,286 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2692 states to 2692 states and 4741 transitions. 312.69/160.49 [2019-03-28 12:22:08,286 INFO L729 BuchiCegarLoop]: Abstraction has 2692 states and 4741 transitions. 312.69/160.49 [2019-03-28 12:22:08,287 INFO L609 BuchiCegarLoop]: Abstraction has 2692 states and 4741 transitions. 312.69/160.49 [2019-03-28 12:22:08,287 INFO L442 BuchiCegarLoop]: ======== Iteration 24============ 312.69/160.49 [2019-03-28 12:22:08,287 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2692 states and 4741 transitions. 312.69/160.49 [2019-03-28 12:22:08,293 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2628 312.69/160.49 [2019-03-28 12:22:08,293 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.49 [2019-03-28 12:22:08,293 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.49 [2019-03-28 12:22:08,294 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.49 [2019-03-28 12:22:08,295 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.49 [2019-03-28 12:22:08,296 INFO L794 eck$LassoCheckResult]: Stem: 34074#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 33872#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 33873#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 33939#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 33940#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 33876#L431-1 [2355] L431-1-->L436-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 33877#L436-1 [2735] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 33915#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 33916#L601-1 [3235] L601-1-->L606-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 33918#L606-1 [3236] L606-1-->L611-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 33805#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 33806#L616-1 [3240] L616-1-->L621-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 33688#L621-1 [3242] L621-1-->L626-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 33689#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 33776#L631-1 [3246] L631-1-->L636-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 33777#L636-1 [3248] L636-1-->L641-1: Formula: (> v_~E_2~0_4 0) InVars {~E_2~0=v_~E_2~0_4} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[] 33962#L641-1 [3251] L641-1-->L646-1: Formula: (> v_~E_3~0_4 0) InVars {~E_3~0=v_~E_3~0_4} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[] 33963#L646-1 [3253] L646-1-->L651-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 33906#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 33907#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 34145#L294 [3256] L294-->L294-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 34183#L294-2 [2905] L294-2-->L305: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 34197#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 34198#L745 [2925] L745-->L745-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_6) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} AuxVars[] AssignedVars[] 34206#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 33851#L313 [3262] L313-->L313-2: Formula: (< v_~t1_pc~0_3 1) InVars {~t1_pc~0=v_~t1_pc~0_3} OutVars{~t1_pc~0=v_~t1_pc~0_3} AuxVars[] AssignedVars[] 33852#L313-2 [2314] L313-2-->L324: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 33850#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 33704#L753 [2130] L753-->L753-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} AuxVars[] AssignedVars[] 33705#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 33708#L332 [3268] L332-->L332-2: Formula: (< v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 33882#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 33880#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 33881#L761 [3273] L761-->L761-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_5) (= v_~t2_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5, ~t2_st~0=v_~t2_st~0_6} AuxVars[] AssignedVars[~t2_st~0] 33901#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 33902#L351 [3275] L351-->L351-2: Formula: (< 1 v_~t3_pc~0_3) InVars {~t3_pc~0=v_~t3_pc~0_3} OutVars{~t3_pc~0=v_~t3_pc~0_3} AuxVars[] AssignedVars[] 34017#L351-2 [2543] L351-2-->L362: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 34018#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 34035#L769 [3279] L769-->L769-2: Formula: (and (= v_~t3_st~0_6 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_5)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} OutVars{~t3_st~0=v_~t3_st~0_6, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} AuxVars[] AssignedVars[~t3_st~0] 34042#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 34043#L370 [3281] L370-->L370-2: Formula: (> v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 34132#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 34129#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 34130#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 34144#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 33767#L389 [2193] L389-->L390: Formula: (= 1 v_~t5_pc~0_2) InVars {~t5_pc~0=v_~t5_pc~0_2} OutVars{~t5_pc~0=v_~t5_pc~0_2} AuxVars[] AssignedVars[] 33768#L390 [2343] L390-->L400: Formula: (and (= v_~E_5~0_5 1) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4 1)) InVars {~E_5~0=v_~E_5~0_5} OutVars{~E_5~0=v_~E_5~0_5, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 33738#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 33766#L785 [3291] L785-->L785-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_5) (= v_~t5_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} OutVars{~t5_st~0=v_~t5_st~0_6, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} AuxVars[] AssignedVars[~t5_st~0] 33784#L785-2 [3293] L785-2-->L669-1: Formula: (> 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 33785#L669-1 [3294] L669-1-->L674-1: Formula: (< 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 33960#L674-1 [3296] L674-1-->L679-1: Formula: (< 1 v_~T2_E~0_7) InVars {~T2_E~0=v_~T2_E~0_7} OutVars{~T2_E~0=v_~T2_E~0_7} AuxVars[] AssignedVars[] 33961#L679-1 [3299] L679-1-->L684-1: Formula: (< v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 33904#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 33905#L689-1 [3302] L689-1-->L694-1: Formula: (> v_~T5_E~0_7 1) InVars {~T5_E~0=v_~T5_E~0_7} OutVars{~T5_E~0=v_~T5_E~0_7} AuxVars[] AssignedVars[] 34068#L694-1 [3305] L694-1-->L699-1: Formula: (< v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 33827#L699-1 [3306] L699-1-->L704-1: Formula: (> v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 33828#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 33677#L709-1 [3310] L709-1-->L714-1: Formula: (> v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 33678#L714-1 [3313] L714-1-->L719-1: Formula: (> v_~E_4~0_9 1) InVars {~E_4~0=v_~E_4~0_9} OutVars{~E_4~0=v_~E_4~0_9} AuxVars[] AssignedVars[] 33770#L719-1 [2198] L719-1-->L930-1: Formula: (and (= v_~E_5~0_8 1) (= v_~E_5~0_7 2)) InVars {~E_5~0=v_~E_5~0_8} OutVars{~E_5~0=v_~E_5~0_7} AuxVars[] AssignedVars[~E_5~0] 33771#L930-1 312.69/160.49 [2019-03-28 12:22:08,297 INFO L796 eck$LassoCheckResult]: Loop: 33771#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 35653#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 35473#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 35466#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 35464#L501 [3784] L501-->L601-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 34142#L601-2 [2768] L601-2-->L601-4: Formula: (and (= v_~M_E~0_8 1) (= 0 v_~M_E~0_9)) InVars {~M_E~0=v_~M_E~0_9} OutVars{~M_E~0=v_~M_E~0_8} AuxVars[] AssignedVars[~M_E~0] 34143#L601-4 [3322] L601-4-->L606-3: Formula: (> v_~T1_E~0_10 0) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 33921#L606-3 [3326] L606-3-->L611-3: Formula: (< 0 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 33922#L611-3 [2256] L611-3-->L616-3: Formula: (and (= v_~T3_E~0_8 1) (= v_~T3_E~0_9 0)) InVars {~T3_E~0=v_~T3_E~0_9} OutVars{~T3_E~0=v_~T3_E~0_8} AuxVars[] AssignedVars[~T3_E~0] 34089#L616-3 [3339] L616-3-->L621-3: Formula: (> v_~T4_E~0_10 0) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 34090#L621-3 [3346] L621-3-->L626-3: Formula: (< 0 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 34041#L626-3 [2580] L626-3-->L631-3: Formula: (and (= v_~E_M~0_24 1) (= 0 v_~E_M~0_25)) InVars {~E_M~0=v_~E_M~0_25} OutVars{~E_M~0=v_~E_M~0_24} AuxVars[] AssignedVars[~E_M~0] 33752#L631-3 [3365] L631-3-->L636-3: Formula: (< 0 v_~E_1~0_26) InVars {~E_1~0=v_~E_1~0_26} OutVars{~E_1~0=v_~E_1~0_26} AuxVars[] AssignedVars[] 33753#L636-3 [3376] L636-3-->L641-3: Formula: (< 0 v_~E_2~0_26) InVars {~E_2~0=v_~E_2~0_26} OutVars{~E_2~0=v_~E_2~0_26} AuxVars[] AssignedVars[] 33949#L641-3 [3388] L641-3-->L646-3: Formula: (< 0 v_~E_3~0_26) InVars {~E_3~0=v_~E_3~0_26} OutVars{~E_3~0=v_~E_3~0_26} AuxVars[] AssignedVars[] 33950#L646-3 [3401] L646-3-->L651-3: Formula: (< 0 v_~E_4~0_26) InVars {~E_4~0=v_~E_4~0_26} OutVars{~E_4~0=v_~E_4~0_26} AuxVars[] AssignedVars[] 36327#L651-3 [3410] L651-3-->L656-3: Formula: (> 0 v_~E_5~0_26) InVars {~E_5~0=v_~E_5~0_26} OutVars{~E_5~0=v_~E_5~0_26} AuxVars[] AssignedVars[] 36326#L656-3 [2767] L656-3-->L294-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_37, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_37, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_22|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_22|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_22|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_37, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_37, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_22|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_22|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_22|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_22|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_37, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_37, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_37} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 34155#L294-21 [3426] L294-21-->L294-23: Formula: (< v_~m_pc~0_22 1) InVars {~m_pc~0=v_~m_pc~0_22} OutVars{~m_pc~0=v_~m_pc~0_22} AuxVars[] AssignedVars[] 34151#L294-23 [2803] L294-23-->L305-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_41 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_41} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 34152#L305-7 [3806] L305-7-->L745-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 34169#L745-21 [2835] L745-21-->L745-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_42) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} AuxVars[] AssignedVars[] 34170#L745-23 [2838] L745-23-->L313-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_43, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 33800#L313-21 [3469] L313-21-->L313-23: Formula: (< v_~t1_pc~0_22 1) InVars {~t1_pc~0=v_~t1_pc~0_22} OutVars{~t1_pc~0=v_~t1_pc~0_22} AuxVars[] AssignedVars[] 33801#L313-23 [2249] L313-23-->L324-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 33804#L324-7 [3813] L324-7-->L753-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 33842#L753-21 [2292] L753-21-->L753-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} AuxVars[] AssignedVars[] 33845#L753-23 [2297] L753-23-->L332-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_22|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 33849#L332-21 [3510] L332-21-->L332-23: Formula: (> 1 v_~t2_pc~0_22) InVars {~t2_pc~0=v_~t2_pc~0_22} OutVars{~t2_pc~0=v_~t2_pc~0_22} AuxVars[] AssignedVars[] 33959#L332-23 [2476] L332-23-->L343-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 33964#L343-7 [3820] L343-7-->L761-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 36108#L761-21 [3538] L761-21-->L761-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___1~0_41 0) (= v_~t2_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41, ~t2_st~0=v_~t2_st~0_19} AuxVars[] AssignedVars[~t2_st~0] 36107#L761-23 [2493] L761-23-->L351-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_22|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 36099#L351-21 [3552] L351-21-->L351-23: Formula: (< v_~t3_pc~0_22 1) InVars {~t3_pc~0=v_~t3_pc~0_22} OutVars{~t3_pc~0=v_~t3_pc~0_22} AuxVars[] AssignedVars[] 36097#L351-23 [2660] L351-23-->L362-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 36096#L362-7 [3827] L362-7-->L769-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 36095#L769-21 [2534] L769-21-->L769-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} AuxVars[] AssignedVars[] 36094#L769-23 [2537] L769-23-->L370-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_43, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 35906#L370-21 [3594] L370-21-->L370-23: Formula: (< 1 v_~t4_pc~0_22) InVars {~t4_pc~0=v_~t4_pc~0_22} OutVars{~t4_pc~0=v_~t4_pc~0_22} AuxVars[] AssignedVars[] 35903#L370-23 [2934] L370-23-->L381-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 35901#L381-7 [3834] L381-7-->L777-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 35899#L777-21 [2705] L777-21-->L777-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} AuxVars[] AssignedVars[] 35897#L777-23 [2708] L777-23-->L389-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_22|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 35896#L389-21 [2132] L389-21-->L390-7: Formula: (= v_~t5_pc~0_21 1) InVars {~t5_pc~0=v_~t5_pc~0_21} OutVars{~t5_pc~0=v_~t5_pc~0_21} AuxVars[] AssignedVars[] 35893#L390-7 [2330] L390-7-->L400-7: Formula: (and (= 1 v_~E_5~0_27) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46 1)) InVars {~E_5~0=v_~E_5~0_27} OutVars{~E_5~0=v_~E_5~0_27, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 35891#L400-7 [3837] L400-7-->L785-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 35889#L785-21 [3654] L785-21-->L785-23: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_41 0) (= v_~t5_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} OutVars{~t5_st~0=v_~t5_st~0_19, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} AuxVars[] AssignedVars[~t5_st~0] 35888#L785-23 [2161] L785-23-->L669-3: Formula: (and (= v_~M_E~0_12 1) (= v_~M_E~0_11 2)) InVars {~M_E~0=v_~M_E~0_12} OutVars{~M_E~0=v_~M_E~0_11} AuxVars[] AssignedVars[~M_E~0] 35885#L669-3 [3660] L669-3-->L674-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 35883#L674-3 [3662] L674-3-->L679-3: Formula: (< 1 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 35881#L679-3 [3664] L679-3-->L684-3: Formula: (< 1 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 35879#L684-3 [3666] L684-3-->L689-3: Formula: (> v_~T4_E~0_13 1) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 35877#L689-3 [3668] L689-3-->L694-3: Formula: (< 1 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 35850#L694-3 [2405] L694-3-->L699-3: Formula: (and (= 1 v_~E_M~0_30) (= v_~E_M~0_29 2)) InVars {~E_M~0=v_~E_M~0_30} OutVars{~E_M~0=v_~E_M~0_29} AuxVars[] AssignedVars[~E_M~0] 35841#L699-3 [3673] L699-3-->L704-3: Formula: (< 1 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 35837#L704-3 [3675] L704-3-->L709-3: Formula: (< 1 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 35835#L709-3 [3677] L709-3-->L714-3: Formula: (< 1 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 35833#L714-3 [3678] L714-3-->L719-3: Formula: (< 1 v_~E_4~0_31) InVars {~E_4~0=v_~E_4~0_31} OutVars{~E_4~0=v_~E_4~0_31} AuxVars[] AssignedVars[] 35831#L719-3 [3680] L719-3-->L724-3: Formula: (> 1 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 35829#L724-3 [2818] L724-3-->L454-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_23} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 35752#L454-1 [2466] L454-1-->L486-1: Formula: (and (= 0 v_~m_st~0_20) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26 1)) InVars {~m_st~0=v_~m_st~0_20} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 35747#L486-1 [3838] L486-1-->L949: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret15, ULTIMATE.start_start_simulation_~tmp~3] 35741#L949 [3688] L949-->L949-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_1) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} AuxVars[] AssignedVars[] 35737#L949-1 [2479] L949-1-->L454-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_1} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 35686#L454-2 [2438] L454-2-->L486-2: Formula: (and (= v_~m_st~0_2 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4 1)) InVars {~m_st~0=v_~m_st~0_2} OutVars{~m_st~0=v_~m_st~0_2, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 35674#L486-2 [3840] L486-2-->L904: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 35666#L904 [2393] L904-->L911: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 35658#L911 [3851] L911-->L930-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_6|, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 33771#L930-1 312.69/160.49 [2019-03-28 12:22:08,297 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.49 [2019-03-28 12:22:08,297 INFO L82 PathProgramCache]: Analyzing trace with hash 624773601, now seen corresponding path program 1 times 312.69/160.49 [2019-03-28 12:22:08,297 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.49 [2019-03-28 12:22:08,297 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.49 [2019-03-28 12:22:08,298 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:08,298 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:08,298 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:08,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.49 [2019-03-28 12:22:08,367 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.49 [2019-03-28 12:22:08,367 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.49 [2019-03-28 12:22:08,368 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 312.69/160.49 [2019-03-28 12:22:08,368 INFO L799 eck$LassoCheckResult]: stem already infeasible 312.69/160.49 [2019-03-28 12:22:08,368 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.49 [2019-03-28 12:22:08,368 INFO L82 PathProgramCache]: Analyzing trace with hash 900274352, now seen corresponding path program 4 times 312.69/160.49 [2019-03-28 12:22:08,369 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.49 [2019-03-28 12:22:08,369 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.49 [2019-03-28 12:22:08,369 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:08,370 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:08,370 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.49 [2019-03-28 12:22:08,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.49 [2019-03-28 12:22:08,395 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.49 [2019-03-28 12:22:08,396 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.49 [2019-03-28 12:22:08,396 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 312.69/160.49 [2019-03-28 12:22:08,396 INFO L811 eck$LassoCheckResult]: loop already infeasible 312.69/160.49 [2019-03-28 12:22:08,396 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. 312.69/160.49 [2019-03-28 12:22:08,397 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 312.69/160.49 [2019-03-28 12:22:08,397 INFO L87 Difference]: Start difference. First operand 2692 states and 4741 transitions. cyclomatic complexity: 2050 Second operand 6 states. 312.69/160.49 [2019-03-28 12:22:10,065 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.49 [2019-03-28 12:22:10,066 INFO L93 Difference]: Finished difference Result 6175 states and 10901 transitions. 312.69/160.49 [2019-03-28 12:22:10,066 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. 312.69/160.49 [2019-03-28 12:22:10,066 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6175 states and 10901 transitions. 312.69/160.49 [2019-03-28 12:22:10,089 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 6111 312.69/160.49 [2019-03-28 12:22:10,113 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6175 states to 6175 states and 10901 transitions. 312.69/160.49 [2019-03-28 12:22:10,113 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6175 312.69/160.49 [2019-03-28 12:22:10,117 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6175 312.69/160.49 [2019-03-28 12:22:10,117 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6175 states and 10901 transitions. 312.69/160.49 [2019-03-28 12:22:10,123 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.49 [2019-03-28 12:22:10,123 INFO L706 BuchiCegarLoop]: Abstraction has 6175 states and 10901 transitions. 312.69/160.49 [2019-03-28 12:22:10,126 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6175 states and 10901 transitions. 312.69/160.49 [2019-03-28 12:22:10,164 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6175 to 2696. 312.69/160.49 [2019-03-28 12:22:10,165 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2696 states. 312.69/160.49 [2019-03-28 12:22:10,169 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2696 states to 2696 states and 4696 transitions. 312.69/160.49 [2019-03-28 12:22:10,170 INFO L729 BuchiCegarLoop]: Abstraction has 2696 states and 4696 transitions. 312.69/160.49 [2019-03-28 12:22:10,170 INFO L609 BuchiCegarLoop]: Abstraction has 2696 states and 4696 transitions. 312.69/160.49 [2019-03-28 12:22:10,170 INFO L442 BuchiCegarLoop]: ======== Iteration 25============ 312.69/160.49 [2019-03-28 12:22:10,170 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2696 states and 4696 transitions. 312.69/160.49 [2019-03-28 12:22:10,176 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2632 312.69/160.49 [2019-03-28 12:22:10,177 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.49 [2019-03-28 12:22:10,177 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.49 [2019-03-28 12:22:10,178 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.49 [2019-03-28 12:22:10,178 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.49 [2019-03-28 12:22:10,179 INFO L794 eck$LassoCheckResult]: Stem: 42971#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 42772#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 42773#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 42835#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 42836#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 42774#L431-1 [2355] L431-1-->L436-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 42775#L436-1 [2735] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 42813#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 42814#L601-1 [3235] L601-1-->L606-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 42817#L606-1 [3236] L606-1-->L611-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 42699#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 42700#L616-1 [3240] L616-1-->L621-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 42585#L621-1 [3242] L621-1-->L626-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 42586#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 42672#L631-1 [3246] L631-1-->L636-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 42673#L636-1 [3248] L636-1-->L641-1: Formula: (> v_~E_2~0_4 0) InVars {~E_2~0=v_~E_2~0_4} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[] 42860#L641-1 [3251] L641-1-->L646-1: Formula: (> v_~E_3~0_4 0) InVars {~E_3~0=v_~E_3~0_4} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[] 42861#L646-1 [3253] L646-1-->L651-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 42805#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 42806#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 43034#L294 [3256] L294-->L294-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 43066#L294-2 [2905] L294-2-->L305: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 43084#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 43085#L745 [2925] L745-->L745-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_6) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} AuxVars[] AssignedVars[] 43094#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 42749#L313 [3262] L313-->L313-2: Formula: (< v_~t1_pc~0_3 1) InVars {~t1_pc~0=v_~t1_pc~0_3} OutVars{~t1_pc~0=v_~t1_pc~0_3} AuxVars[] AssignedVars[] 42750#L313-2 [2314] L313-2-->L324: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 42748#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 42601#L753 [2130] L753-->L753-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} AuxVars[] AssignedVars[] 42602#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 42606#L332 [3268] L332-->L332-2: Formula: (< v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 42782#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 42780#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 42781#L761 [3272] L761-->L761-2: Formula: (and (> 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_5) (= v_~t2_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_5, ~t2_st~0=v_~t2_st~0_6} AuxVars[] AssignedVars[~t2_st~0] 42801#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 42802#L351 [3275] L351-->L351-2: Formula: (< 1 v_~t3_pc~0_3) InVars {~t3_pc~0=v_~t3_pc~0_3} OutVars{~t3_pc~0=v_~t3_pc~0_3} AuxVars[] AssignedVars[] 42918#L351-2 [2543] L351-2-->L362: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 42919#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 42935#L769 [3279] L769-->L769-2: Formula: (and (= v_~t3_st~0_6 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_5)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} OutVars{~t3_st~0=v_~t3_st~0_6, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} AuxVars[] AssignedVars[~t3_st~0] 42939#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 42940#L370 [3281] L370-->L370-2: Formula: (> v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 43021#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 43017#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 43018#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 43033#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 42663#L389 [2193] L389-->L390: Formula: (= 1 v_~t5_pc~0_2) InVars {~t5_pc~0=v_~t5_pc~0_2} OutVars{~t5_pc~0=v_~t5_pc~0_2} AuxVars[] AssignedVars[] 42664#L390 [2343] L390-->L400: Formula: (and (= v_~E_5~0_5 1) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4 1)) InVars {~E_5~0=v_~E_5~0_5} OutVars{~E_5~0=v_~E_5~0_5, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 42633#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 42659#L785 [3291] L785-->L785-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_5) (= v_~t5_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} OutVars{~t5_st~0=v_~t5_st~0_6, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} AuxVars[] AssignedVars[~t5_st~0] 42679#L785-2 [3293] L785-2-->L669-1: Formula: (> 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 42681#L669-1 [3294] L669-1-->L674-1: Formula: (< 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 42858#L674-1 [3296] L674-1-->L679-1: Formula: (< 1 v_~T2_E~0_7) InVars {~T2_E~0=v_~T2_E~0_7} OutVars{~T2_E~0=v_~T2_E~0_7} AuxVars[] AssignedVars[] 42859#L679-1 [3299] L679-1-->L684-1: Formula: (< v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 42803#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 42804#L689-1 [3302] L689-1-->L694-1: Formula: (> v_~T5_E~0_7 1) InVars {~T5_E~0=v_~T5_E~0_7} OutVars{~T5_E~0=v_~T5_E~0_7} AuxVars[] AssignedVars[] 42965#L694-1 [3305] L694-1-->L699-1: Formula: (< v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 42724#L699-1 [3306] L699-1-->L704-1: Formula: (> v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 42725#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 42574#L709-1 [3310] L709-1-->L714-1: Formula: (> v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 42575#L714-1 [3313] L714-1-->L719-1: Formula: (> v_~E_4~0_9 1) InVars {~E_4~0=v_~E_4~0_9} OutVars{~E_4~0=v_~E_4~0_9} AuxVars[] AssignedVars[] 42666#L719-1 [2198] L719-1-->L930-1: Formula: (and (= v_~E_5~0_8 1) (= v_~E_5~0_7 2)) InVars {~E_5~0=v_~E_5~0_8} OutVars{~E_5~0=v_~E_5~0_7} AuxVars[] AssignedVars[~E_5~0] 42667#L930-1 312.69/160.49 [2019-03-28 12:22:10,180 INFO L796 eck$LassoCheckResult]: Loop: 42667#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 43439#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 43435#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 43428#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 43424#L501 [3784] L501-->L601-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 43425#L601-2 [2768] L601-2-->L601-4: Formula: (and (= v_~M_E~0_8 1) (= 0 v_~M_E~0_9)) InVars {~M_E~0=v_~M_E~0_9} OutVars{~M_E~0=v_~M_E~0_8} AuxVars[] AssignedVars[~M_E~0] 44095#L601-4 [3322] L601-4-->L606-3: Formula: (> v_~T1_E~0_10 0) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 44094#L606-3 [3326] L606-3-->L611-3: Formula: (< 0 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 44093#L611-3 [2256] L611-3-->L616-3: Formula: (and (= v_~T3_E~0_8 1) (= v_~T3_E~0_9 0)) InVars {~T3_E~0=v_~T3_E~0_9} OutVars{~T3_E~0=v_~T3_E~0_8} AuxVars[] AssignedVars[~T3_E~0] 44092#L616-3 [3339] L616-3-->L621-3: Formula: (> v_~T4_E~0_10 0) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 44091#L621-3 [3346] L621-3-->L626-3: Formula: (< 0 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 44090#L626-3 [2580] L626-3-->L631-3: Formula: (and (= v_~E_M~0_24 1) (= 0 v_~E_M~0_25)) InVars {~E_M~0=v_~E_M~0_25} OutVars{~E_M~0=v_~E_M~0_24} AuxVars[] AssignedVars[~E_M~0] 44089#L631-3 [3365] L631-3-->L636-3: Formula: (< 0 v_~E_1~0_26) InVars {~E_1~0=v_~E_1~0_26} OutVars{~E_1~0=v_~E_1~0_26} AuxVars[] AssignedVars[] 44058#L636-3 [3376] L636-3-->L641-3: Formula: (< 0 v_~E_2~0_26) InVars {~E_2~0=v_~E_2~0_26} OutVars{~E_2~0=v_~E_2~0_26} AuxVars[] AssignedVars[] 44056#L641-3 [3388] L641-3-->L646-3: Formula: (< 0 v_~E_3~0_26) InVars {~E_3~0=v_~E_3~0_26} OutVars{~E_3~0=v_~E_3~0_26} AuxVars[] AssignedVars[] 44053#L646-3 [3401] L646-3-->L651-3: Formula: (< 0 v_~E_4~0_26) InVars {~E_4~0=v_~E_4~0_26} OutVars{~E_4~0=v_~E_4~0_26} AuxVars[] AssignedVars[] 44049#L651-3 [3410] L651-3-->L656-3: Formula: (> 0 v_~E_5~0_26) InVars {~E_5~0=v_~E_5~0_26} OutVars{~E_5~0=v_~E_5~0_26} AuxVars[] AssignedVars[] 44045#L656-3 [2767] L656-3-->L294-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_37, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_37, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_22|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_22|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_22|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_37, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_37, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_22|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_22|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_22|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_22|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_37, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_37, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_37} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 44040#L294-21 [3426] L294-21-->L294-23: Formula: (< v_~m_pc~0_22 1) InVars {~m_pc~0=v_~m_pc~0_22} OutVars{~m_pc~0=v_~m_pc~0_22} AuxVars[] AssignedVars[] 44031#L294-23 [2803] L294-23-->L305-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_41 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_41} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 44026#L305-7 [3806] L305-7-->L745-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 44020#L745-21 [2835] L745-21-->L745-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_42) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} AuxVars[] AssignedVars[] 44011#L745-23 [2838] L745-23-->L313-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_43, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 43821#L313-21 [3469] L313-21-->L313-23: Formula: (< v_~t1_pc~0_22 1) InVars {~t1_pc~0=v_~t1_pc~0_22} OutVars{~t1_pc~0=v_~t1_pc~0_22} AuxVars[] AssignedVars[] 43819#L313-23 [2249] L313-23-->L324-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 43817#L324-7 [3813] L324-7-->L753-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 43815#L753-21 [2292] L753-21-->L753-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} AuxVars[] AssignedVars[] 43813#L753-23 [2297] L753-23-->L332-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_22|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 43680#L332-21 [3510] L332-21-->L332-23: Formula: (> 1 v_~t2_pc~0_22) InVars {~t2_pc~0=v_~t2_pc~0_22} OutVars{~t2_pc~0=v_~t2_pc~0_22} AuxVars[] AssignedVars[] 43679#L332-23 [2476] L332-23-->L343-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 43678#L343-7 [3820] L343-7-->L761-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 43677#L761-21 [3538] L761-21-->L761-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___1~0_41 0) (= v_~t2_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_41, ~t2_st~0=v_~t2_st~0_19} AuxVars[] AssignedVars[~t2_st~0] 43676#L761-23 [2493] L761-23-->L351-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_22|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 43674#L351-21 [3552] L351-21-->L351-23: Formula: (< v_~t3_pc~0_22 1) InVars {~t3_pc~0=v_~t3_pc~0_22} OutVars{~t3_pc~0=v_~t3_pc~0_22} AuxVars[] AssignedVars[] 43673#L351-23 [2660] L351-23-->L362-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 43672#L362-7 [3827] L362-7-->L769-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 43671#L769-21 [2534] L769-21-->L769-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} AuxVars[] AssignedVars[] 43670#L769-23 [2537] L769-23-->L370-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_43, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 43669#L370-21 [3594] L370-21-->L370-23: Formula: (< 1 v_~t4_pc~0_22) InVars {~t4_pc~0=v_~t4_pc~0_22} OutVars{~t4_pc~0=v_~t4_pc~0_22} AuxVars[] AssignedVars[] 43667#L370-23 [2934] L370-23-->L381-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 43666#L381-7 [3834] L381-7-->L777-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 43665#L777-21 [2705] L777-21-->L777-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} AuxVars[] AssignedVars[] 43664#L777-23 [2708] L777-23-->L389-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_22|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 43663#L389-21 [2132] L389-21-->L390-7: Formula: (= v_~t5_pc~0_21 1) InVars {~t5_pc~0=v_~t5_pc~0_21} OutVars{~t5_pc~0=v_~t5_pc~0_21} AuxVars[] AssignedVars[] 43661#L390-7 [2330] L390-7-->L400-7: Formula: (and (= 1 v_~E_5~0_27) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46 1)) InVars {~E_5~0=v_~E_5~0_27} OutVars{~E_5~0=v_~E_5~0_27, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 43660#L400-7 [3837] L400-7-->L785-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 43659#L785-21 [3654] L785-21-->L785-23: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_41 0) (= v_~t5_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} OutVars{~t5_st~0=v_~t5_st~0_19, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} AuxVars[] AssignedVars[~t5_st~0] 43658#L785-23 [2161] L785-23-->L669-3: Formula: (and (= v_~M_E~0_12 1) (= v_~M_E~0_11 2)) InVars {~M_E~0=v_~M_E~0_12} OutVars{~M_E~0=v_~M_E~0_11} AuxVars[] AssignedVars[~M_E~0] 43657#L669-3 [3660] L669-3-->L674-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 43656#L674-3 [3662] L674-3-->L679-3: Formula: (< 1 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 43655#L679-3 [3664] L679-3-->L684-3: Formula: (< 1 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 43654#L684-3 [3666] L684-3-->L689-3: Formula: (> v_~T4_E~0_13 1) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 43653#L689-3 [3668] L689-3-->L694-3: Formula: (< 1 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 43652#L694-3 [2405] L694-3-->L699-3: Formula: (and (= 1 v_~E_M~0_30) (= v_~E_M~0_29 2)) InVars {~E_M~0=v_~E_M~0_30} OutVars{~E_M~0=v_~E_M~0_29} AuxVars[] AssignedVars[~E_M~0] 43651#L699-3 [3673] L699-3-->L704-3: Formula: (< 1 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 43650#L704-3 [3675] L704-3-->L709-3: Formula: (< 1 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 43649#L709-3 [3677] L709-3-->L714-3: Formula: (< 1 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 43648#L714-3 [3678] L714-3-->L719-3: Formula: (< 1 v_~E_4~0_31) InVars {~E_4~0=v_~E_4~0_31} OutVars{~E_4~0=v_~E_4~0_31} AuxVars[] AssignedVars[] 43647#L719-3 [3680] L719-3-->L724-3: Formula: (> 1 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 43646#L724-3 [2818] L724-3-->L454-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_23} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 43608#L454-1 [2466] L454-1-->L486-1: Formula: (and (= 0 v_~m_st~0_20) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26 1)) InVars {~m_st~0=v_~m_st~0_20} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 43606#L486-1 [3838] L486-1-->L949: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret15, ULTIMATE.start_start_simulation_~tmp~3] 43603#L949 [3688] L949-->L949-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_1) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} AuxVars[] AssignedVars[] 43601#L949-1 [2479] L949-1-->L454-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_1} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 43464#L454-2 [2438] L454-2-->L486-2: Formula: (and (= v_~m_st~0_2 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4 1)) InVars {~m_st~0=v_~m_st~0_2} OutVars{~m_st~0=v_~m_st~0_2, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 43459#L486-2 [3840] L486-2-->L904: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 43457#L904 [2393] L904-->L911: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 43453#L911 [3851] L911-->L930-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_6|, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 42667#L930-1 312.69/160.50 [2019-03-28 12:22:10,180 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.50 [2019-03-28 12:22:10,181 INFO L82 PathProgramCache]: Analyzing trace with hash 879510146, now seen corresponding path program 1 times 312.69/160.50 [2019-03-28 12:22:10,181 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.50 [2019-03-28 12:22:10,181 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.50 [2019-03-28 12:22:10,182 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:10,182 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:10,182 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:10,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.50 [2019-03-28 12:22:10,220 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.50 [2019-03-28 12:22:10,220 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.50 [2019-03-28 12:22:10,220 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 312.69/160.50 [2019-03-28 12:22:10,220 INFO L799 eck$LassoCheckResult]: stem already infeasible 312.69/160.50 [2019-03-28 12:22:10,221 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.50 [2019-03-28 12:22:10,221 INFO L82 PathProgramCache]: Analyzing trace with hash 900274352, now seen corresponding path program 5 times 312.69/160.50 [2019-03-28 12:22:10,221 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.50 [2019-03-28 12:22:10,221 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.50 [2019-03-28 12:22:10,222 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:10,222 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:10,222 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:10,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.50 [2019-03-28 12:22:10,246 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.50 [2019-03-28 12:22:10,247 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.50 [2019-03-28 12:22:10,247 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 312.69/160.50 [2019-03-28 12:22:10,247 INFO L811 eck$LassoCheckResult]: loop already infeasible 312.69/160.50 [2019-03-28 12:22:10,248 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. 312.69/160.50 [2019-03-28 12:22:10,248 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 312.69/160.50 [2019-03-28 12:22:10,248 INFO L87 Difference]: Start difference. First operand 2696 states and 4696 transitions. cyclomatic complexity: 2001 Second operand 6 states. 312.69/160.50 [2019-03-28 12:22:10,867 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.50 [2019-03-28 12:22:10,867 INFO L93 Difference]: Finished difference Result 2696 states and 4641 transitions. 312.69/160.50 [2019-03-28 12:22:10,868 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. 312.69/160.50 [2019-03-28 12:22:10,868 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2696 states and 4641 transitions. 312.69/160.50 [2019-03-28 12:22:10,876 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2632 312.69/160.50 [2019-03-28 12:22:10,883 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2696 states to 2696 states and 4641 transitions. 312.69/160.50 [2019-03-28 12:22:10,883 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2696 312.69/160.50 [2019-03-28 12:22:10,885 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2696 312.69/160.50 [2019-03-28 12:22:10,885 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2696 states and 4641 transitions. 312.69/160.50 [2019-03-28 12:22:10,887 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.50 [2019-03-28 12:22:10,888 INFO L706 BuchiCegarLoop]: Abstraction has 2696 states and 4641 transitions. 312.69/160.50 [2019-03-28 12:22:10,889 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2696 states and 4641 transitions. 312.69/160.50 [2019-03-28 12:22:10,913 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2696 to 2696. 312.69/160.50 [2019-03-28 12:22:10,913 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2696 states. 312.69/160.50 [2019-03-28 12:22:10,917 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2696 states to 2696 states and 4641 transitions. 312.69/160.50 [2019-03-28 12:22:10,918 INFO L729 BuchiCegarLoop]: Abstraction has 2696 states and 4641 transitions. 312.69/160.50 [2019-03-28 12:22:10,918 INFO L609 BuchiCegarLoop]: Abstraction has 2696 states and 4641 transitions. 312.69/160.50 [2019-03-28 12:22:10,918 INFO L442 BuchiCegarLoop]: ======== Iteration 26============ 312.69/160.50 [2019-03-28 12:22:10,918 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2696 states and 4641 transitions. 312.69/160.50 [2019-03-28 12:22:10,924 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2632 312.69/160.50 [2019-03-28 12:22:10,924 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.50 [2019-03-28 12:22:10,924 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.50 [2019-03-28 12:22:10,926 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.50 [2019-03-28 12:22:10,926 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.50 [2019-03-28 12:22:10,927 INFO L794 eck$LassoCheckResult]: Stem: 48385#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 48185#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 48186#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 48249#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 48250#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 48187#L431-1 [2355] L431-1-->L436-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 48188#L436-1 [2735] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 48226#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 48227#L601-1 [3235] L601-1-->L606-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 48230#L606-1 [3236] L606-1-->L611-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 48115#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 48116#L616-1 [3240] L616-1-->L621-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 47997#L621-1 [3242] L621-1-->L626-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 47998#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 48086#L631-1 [3246] L631-1-->L636-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 48087#L636-1 [3248] L636-1-->L641-1: Formula: (> v_~E_2~0_4 0) InVars {~E_2~0=v_~E_2~0_4} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[] 48275#L641-1 [3251] L641-1-->L646-1: Formula: (> v_~E_3~0_4 0) InVars {~E_3~0=v_~E_3~0_4} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[] 48276#L646-1 [3253] L646-1-->L651-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 48218#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 48219#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 48451#L294 [3256] L294-->L294-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 48489#L294-2 [2905] L294-2-->L305: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 48504#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 48505#L745 [2925] L745-->L745-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_6) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} AuxVars[] AssignedVars[] 48513#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 48166#L313 [3262] L313-->L313-2: Formula: (< v_~t1_pc~0_3 1) InVars {~t1_pc~0=v_~t1_pc~0_3} OutVars{~t1_pc~0=v_~t1_pc~0_3} AuxVars[] AssignedVars[] 48167#L313-2 [2314] L313-2-->L324: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 48165#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 48012#L753 [2130] L753-->L753-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} AuxVars[] AssignedVars[] 48013#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 48017#L332 [3268] L332-->L332-2: Formula: (< v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 48195#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 48193#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 48194#L761 [2384] L761-->L761-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} AuxVars[] AssignedVars[] 48214#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 48215#L351 [3275] L351-->L351-2: Formula: (< 1 v_~t3_pc~0_3) InVars {~t3_pc~0=v_~t3_pc~0_3} OutVars{~t3_pc~0=v_~t3_pc~0_3} AuxVars[] AssignedVars[] 48331#L351-2 [2543] L351-2-->L362: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 48332#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 48349#L769 [3279] L769-->L769-2: Formula: (and (= v_~t3_st~0_6 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_5)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} OutVars{~t3_st~0=v_~t3_st~0_6, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} AuxVars[] AssignedVars[~t3_st~0] 48353#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 48354#L370 [3281] L370-->L370-2: Formula: (> v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 48438#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 48434#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 48435#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 48450#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 48077#L389 [2193] L389-->L390: Formula: (= 1 v_~t5_pc~0_2) InVars {~t5_pc~0=v_~t5_pc~0_2} OutVars{~t5_pc~0=v_~t5_pc~0_2} AuxVars[] AssignedVars[] 48078#L390 [2343] L390-->L400: Formula: (and (= v_~E_5~0_5 1) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4 1)) InVars {~E_5~0=v_~E_5~0_5} OutVars{~E_5~0=v_~E_5~0_5, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 48045#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 48073#L785 [3291] L785-->L785-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_5) (= v_~t5_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} OutVars{~t5_st~0=v_~t5_st~0_6, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} AuxVars[] AssignedVars[~t5_st~0] 48094#L785-2 [3293] L785-2-->L669-1: Formula: (> 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 48096#L669-1 [3294] L669-1-->L674-1: Formula: (< 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 48273#L674-1 [3296] L674-1-->L679-1: Formula: (< 1 v_~T2_E~0_7) InVars {~T2_E~0=v_~T2_E~0_7} OutVars{~T2_E~0=v_~T2_E~0_7} AuxVars[] AssignedVars[] 48274#L679-1 [3299] L679-1-->L684-1: Formula: (< v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 48216#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 48217#L689-1 [3302] L689-1-->L694-1: Formula: (> v_~T5_E~0_7 1) InVars {~T5_E~0=v_~T5_E~0_7} OutVars{~T5_E~0=v_~T5_E~0_7} AuxVars[] AssignedVars[] 48379#L694-1 [3305] L694-1-->L699-1: Formula: (< v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 48140#L699-1 [3306] L699-1-->L704-1: Formula: (> v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 48141#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 47986#L709-1 [3310] L709-1-->L714-1: Formula: (> v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 47987#L714-1 [3313] L714-1-->L719-1: Formula: (> v_~E_4~0_9 1) InVars {~E_4~0=v_~E_4~0_9} OutVars{~E_4~0=v_~E_4~0_9} AuxVars[] AssignedVars[] 48080#L719-1 [2198] L719-1-->L930-1: Formula: (and (= v_~E_5~0_8 1) (= v_~E_5~0_7 2)) InVars {~E_5~0=v_~E_5~0_8} OutVars{~E_5~0=v_~E_5~0_7} AuxVars[] AssignedVars[~E_5~0] 48081#L930-1 312.69/160.50 [2019-03-28 12:22:10,928 INFO L796 eck$LassoCheckResult]: Loop: 48081#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 49258#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 49256#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 49249#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 49247#L501 [3784] L501-->L601-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 48448#L601-2 [2768] L601-2-->L601-4: Formula: (and (= v_~M_E~0_8 1) (= 0 v_~M_E~0_9)) InVars {~M_E~0=v_~M_E~0_9} OutVars{~M_E~0=v_~M_E~0_8} AuxVars[] AssignedVars[~M_E~0] 48449#L601-4 [3322] L601-4-->L606-3: Formula: (> v_~T1_E~0_10 0) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 48234#L606-3 [3326] L606-3-->L611-3: Formula: (< 0 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 48127#L611-3 [2256] L611-3-->L616-3: Formula: (and (= v_~T3_E~0_8 1) (= v_~T3_E~0_9 0)) InVars {~T3_E~0=v_~T3_E~0_9} OutVars{~T3_E~0=v_~T3_E~0_8} AuxVars[] AssignedVars[~T3_E~0] 48128#L616-3 [3339] L616-3-->L621-3: Formula: (> v_~T4_E~0_10 0) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 48003#L621-3 [3346] L621-3-->L626-3: Formula: (< 0 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 48004#L626-3 [2580] L626-3-->L631-3: Formula: (and (= v_~E_M~0_24 1) (= 0 v_~E_M~0_25)) InVars {~E_M~0=v_~E_M~0_25} OutVars{~E_M~0=v_~E_M~0_24} AuxVars[] AssignedVars[~E_M~0] 48062#L631-3 [3365] L631-3-->L636-3: Formula: (< 0 v_~E_1~0_26) InVars {~E_1~0=v_~E_1~0_26} OutVars{~E_1~0=v_~E_1~0_26} AuxVars[] AssignedVars[] 48063#L636-3 [3376] L636-3-->L641-3: Formula: (< 0 v_~E_2~0_26) InVars {~E_2~0=v_~E_2~0_26} OutVars{~E_2~0=v_~E_2~0_26} AuxVars[] AssignedVars[] 48261#L641-3 [3388] L641-3-->L646-3: Formula: (< 0 v_~E_3~0_26) InVars {~E_3~0=v_~E_3~0_26} OutVars{~E_3~0=v_~E_3~0_26} AuxVars[] AssignedVars[] 48262#L646-3 [3401] L646-3-->L651-3: Formula: (< 0 v_~E_4~0_26) InVars {~E_4~0=v_~E_4~0_26} OutVars{~E_4~0=v_~E_4~0_26} AuxVars[] AssignedVars[] 48208#L651-3 [3410] L651-3-->L656-3: Formula: (> 0 v_~E_5~0_26) InVars {~E_5~0=v_~E_5~0_26} OutVars{~E_5~0=v_~E_5~0_26} AuxVars[] AssignedVars[] 48209#L656-3 [2767] L656-3-->L294-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_37, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_37, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_22|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_22|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_22|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_37, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_37, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_22|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_22|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_22|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_22|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_37, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_37, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_37} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 48447#L294-21 [3426] L294-21-->L294-23: Formula: (< v_~m_pc~0_22 1) InVars {~m_pc~0=v_~m_pc~0_22} OutVars{~m_pc~0=v_~m_pc~0_22} AuxVars[] AssignedVars[] 48459#L294-23 [2803] L294-23-->L305-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_41 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_41} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 48460#L305-7 [3806] L305-7-->L745-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 48475#L745-21 [2835] L745-21-->L745-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_42) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} AuxVars[] AssignedVars[] 48476#L745-23 [2838] L745-23-->L313-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_43, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 48111#L313-21 [3469] L313-21-->L313-23: Formula: (< v_~t1_pc~0_22 1) InVars {~t1_pc~0=v_~t1_pc~0_22} OutVars{~t1_pc~0=v_~t1_pc~0_22} AuxVars[] AssignedVars[] 48112#L313-23 [2249] L313-23-->L324-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 50264#L324-7 [3813] L324-7-->L753-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 50262#L753-21 [2292] L753-21-->L753-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} AuxVars[] AssignedVars[] 50261#L753-23 [2297] L753-23-->L332-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_22|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 48271#L332-21 [3510] L332-21-->L332-23: Formula: (> 1 v_~t2_pc~0_22) InVars {~t2_pc~0=v_~t2_pc~0_22} OutVars{~t2_pc~0=v_~t2_pc~0_22} AuxVars[] AssignedVars[] 48272#L332-23 [2476] L332-23-->L343-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 48277#L343-7 [3820] L343-7-->L761-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 48288#L761-21 [2490] L761-21-->L761-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_42} AuxVars[] AssignedVars[] 48289#L761-23 [2493] L761-23-->L351-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_22|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 48291#L351-21 [3552] L351-21-->L351-23: Formula: (< v_~t3_pc~0_22 1) InVars {~t3_pc~0=v_~t3_pc~0_22} OutVars{~t3_pc~0=v_~t3_pc~0_22} AuxVars[] AssignedVars[] 48382#L351-23 [2660] L351-23-->L362-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 48315#L362-7 [3827] L362-7-->L769-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 48316#L769-21 [2534] L769-21-->L769-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} AuxVars[] AssignedVars[] 48322#L769-23 [2537] L769-23-->L370-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_43, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 48325#L370-21 [3594] L370-21-->L370-23: Formula: (< 1 v_~t4_pc~0_22) InVars {~t4_pc~0=v_~t4_pc~0_22} OutVars{~t4_pc~0=v_~t4_pc~0_22} AuxVars[] AssignedVars[] 48495#L370-23 [2934] L370-23-->L381-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 48428#L381-7 [3834] L381-7-->L777-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 48409#L777-21 [2705] L777-21-->L777-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} AuxVars[] AssignedVars[] 48410#L777-23 [2708] L777-23-->L389-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_22|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 48015#L389-21 [2132] L389-21-->L390-7: Formula: (= v_~t5_pc~0_21 1) InVars {~t5_pc~0=v_~t5_pc~0_21} OutVars{~t5_pc~0=v_~t5_pc~0_21} AuxVars[] AssignedVars[] 48016#L390-7 [2330] L390-7-->L400-7: Formula: (and (= 1 v_~E_5~0_27) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46 1)) InVars {~E_5~0=v_~E_5~0_27} OutVars{~E_5~0=v_~E_5~0_27, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 47991#L400-7 [3837] L400-7-->L785-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 48031#L785-21 [3654] L785-21-->L785-23: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_41 0) (= v_~t5_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} OutVars{~t5_st~0=v_~t5_st~0_19, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} AuxVars[] AssignedVars[~t5_st~0] 48036#L785-23 [2161] L785-23-->L669-3: Formula: (and (= v_~M_E~0_12 1) (= v_~M_E~0_11 2)) InVars {~M_E~0=v_~M_E~0_12} OutVars{~M_E~0=v_~M_E~0_11} AuxVars[] AssignedVars[~M_E~0] 48040#L669-3 [3660] L669-3-->L674-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 48278#L674-3 [3662] L674-3-->L679-3: Formula: (< 1 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 48279#L679-3 [3664] L679-3-->L684-3: Formula: (< 1 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 48205#L684-3 [3666] L684-3-->L689-3: Formula: (> v_~T4_E~0_13 1) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 48206#L689-3 [3668] L689-3-->L694-3: Formula: (< 1 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 48229#L694-3 [2405] L694-3-->L699-3: Formula: (and (= 1 v_~E_M~0_30) (= v_~E_M~0_29 2)) InVars {~E_M~0=v_~E_M~0_30} OutVars{~E_M~0=v_~E_M~0_29} AuxVars[] AssignedVars[~E_M~0] 48113#L699-3 [3673] L699-3-->L704-3: Formula: (< 1 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 48114#L704-3 [3675] L704-3-->L709-3: Formula: (< 1 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 47995#L709-3 [3677] L709-3-->L714-3: Formula: (< 1 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 47996#L714-3 [3678] L714-3-->L719-3: Formula: (< 1 v_~E_4~0_31) InVars {~E_4~0=v_~E_4~0_31} OutVars{~E_4~0=v_~E_4~0_31} AuxVars[] AssignedVars[] 48084#L719-3 [3680] L719-3-->L724-3: Formula: (> 1 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 48085#L724-3 [2818] L724-3-->L454-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_23} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 48268#L454-1 [2466] L454-1-->L486-1: Formula: (and (= 0 v_~m_st~0_20) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26 1)) InVars {~m_st~0=v_~m_st~0_20} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 48071#L486-1 [3838] L486-1-->L949: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret15, ULTIMATE.start_start_simulation_~tmp~3] 48213#L949 [3688] L949-->L949-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_1) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} AuxVars[] AssignedVars[] 48300#L949-1 [2479] L949-1-->L454-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_1} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 49279#L454-2 [2438] L454-2-->L486-2: Formula: (and (= v_~m_st~0_2 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4 1)) InVars {~m_st~0=v_~m_st~0_2} OutVars{~m_st~0=v_~m_st~0_2, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 49273#L486-2 [3840] L486-2-->L904: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 49271#L904 [2393] L904-->L911: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 49269#L911 [3851] L911-->L930-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_6|, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 48081#L930-1 312.69/160.50 [2019-03-28 12:22:10,929 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.50 [2019-03-28 12:22:10,929 INFO L82 PathProgramCache]: Analyzing trace with hash -547704582, now seen corresponding path program 1 times 312.69/160.50 [2019-03-28 12:22:10,929 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.50 [2019-03-28 12:22:10,929 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.50 [2019-03-28 12:22:10,930 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:10,930 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:10,930 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:10,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.50 [2019-03-28 12:22:10,957 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.50 [2019-03-28 12:22:10,958 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.50 [2019-03-28 12:22:10,958 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 312.69/160.50 [2019-03-28 12:22:10,958 INFO L799 eck$LassoCheckResult]: stem already infeasible 312.69/160.50 [2019-03-28 12:22:10,958 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.50 [2019-03-28 12:22:10,958 INFO L82 PathProgramCache]: Analyzing trace with hash -1096859496, now seen corresponding path program 1 times 312.69/160.50 [2019-03-28 12:22:10,959 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.50 [2019-03-28 12:22:10,959 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.50 [2019-03-28 12:22:10,959 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:10,960 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:10,960 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:10,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.50 [2019-03-28 12:22:10,980 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.50 [2019-03-28 12:22:10,981 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.50 [2019-03-28 12:22:10,981 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 312.69/160.50 [2019-03-28 12:22:10,981 INFO L811 eck$LassoCheckResult]: loop already infeasible 312.69/160.50 [2019-03-28 12:22:10,981 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 312.69/160.50 [2019-03-28 12:22:10,981 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 312.69/160.50 [2019-03-28 12:22:10,982 INFO L87 Difference]: Start difference. First operand 2696 states and 4641 transitions. cyclomatic complexity: 1946 Second operand 3 states. 312.69/160.50 [2019-03-28 12:22:11,723 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.50 [2019-03-28 12:22:11,724 INFO L93 Difference]: Finished difference Result 5127 states and 8810 transitions. 312.69/160.50 [2019-03-28 12:22:11,724 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 312.69/160.50 [2019-03-28 12:22:11,724 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5127 states and 8810 transitions. 312.69/160.50 [2019-03-28 12:22:11,740 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5064 312.69/160.50 [2019-03-28 12:22:11,755 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5127 states to 5127 states and 8810 transitions. 312.69/160.50 [2019-03-28 12:22:11,755 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5127 312.69/160.50 [2019-03-28 12:22:11,758 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5127 312.69/160.50 [2019-03-28 12:22:11,758 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5127 states and 8810 transitions. 312.69/160.50 [2019-03-28 12:22:11,763 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.50 [2019-03-28 12:22:11,763 INFO L706 BuchiCegarLoop]: Abstraction has 5127 states and 8810 transitions. 312.69/160.50 [2019-03-28 12:22:11,766 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5127 states and 8810 transitions. 312.69/160.50 [2019-03-28 12:22:11,813 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5127 to 4991. 312.69/160.50 [2019-03-28 12:22:11,814 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4991 states. 312.69/160.50 [2019-03-28 12:22:11,822 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4991 states to 4991 states and 8562 transitions. 312.69/160.50 [2019-03-28 12:22:11,822 INFO L729 BuchiCegarLoop]: Abstraction has 4991 states and 8562 transitions. 312.69/160.50 [2019-03-28 12:22:11,823 INFO L609 BuchiCegarLoop]: Abstraction has 4991 states and 8562 transitions. 312.69/160.50 [2019-03-28 12:22:11,823 INFO L442 BuchiCegarLoop]: ======== Iteration 27============ 312.69/160.50 [2019-03-28 12:22:11,823 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4991 states and 8562 transitions. 312.69/160.50 [2019-03-28 12:22:11,838 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4928 312.69/160.50 [2019-03-28 12:22:11,839 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.50 [2019-03-28 12:22:11,839 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.50 [2019-03-28 12:22:11,840 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.50 [2019-03-28 12:22:11,840 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.50 [2019-03-28 12:22:11,841 INFO L794 eck$LassoCheckResult]: Stem: 56211#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 56015#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 56016#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 56078#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 56079#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 56017#L431-1 [2355] L431-1-->L436-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 56018#L436-1 [2735] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 56056#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 56057#L601-1 [3235] L601-1-->L606-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 56060#L606-1 [3236] L606-1-->L611-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 55944#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 55945#L616-1 [3240] L616-1-->L621-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 55828#L621-1 [3242] L621-1-->L626-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 55829#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 55917#L631-1 [3246] L631-1-->L636-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 55918#L636-1 [3248] L636-1-->L641-1: Formula: (> v_~E_2~0_4 0) InVars {~E_2~0=v_~E_2~0_4} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[] 56102#L641-1 [3251] L641-1-->L646-1: Formula: (> v_~E_3~0_4 0) InVars {~E_3~0=v_~E_3~0_4} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[] 56103#L646-1 [3253] L646-1-->L651-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 56048#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 56049#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 56291#L294 [3256] L294-->L294-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 56327#L294-2 [2905] L294-2-->L305: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 56343#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 56344#L745 [2925] L745-->L745-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_6) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} AuxVars[] AssignedVars[] 56352#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 55995#L313 [3262] L313-->L313-2: Formula: (< v_~t1_pc~0_3 1) InVars {~t1_pc~0=v_~t1_pc~0_3} OutVars{~t1_pc~0=v_~t1_pc~0_3} AuxVars[] AssignedVars[] 55996#L313-2 [2314] L313-2-->L324: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 55994#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 55843#L753 [2130] L753-->L753-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} AuxVars[] AssignedVars[] 55844#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 55849#L332 [3268] L332-->L332-2: Formula: (< v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 56025#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 56023#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 56024#L761 [2384] L761-->L761-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} AuxVars[] AssignedVars[] 56044#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 56045#L351 [3274] L351-->L351-2: Formula: (> 1 v_~t3_pc~0_3) InVars {~t3_pc~0=v_~t3_pc~0_3} OutVars{~t3_pc~0=v_~t3_pc~0_3} AuxVars[] AssignedVars[] 56153#L351-2 [2543] L351-2-->L362: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 56154#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 56172#L769 [3279] L769-->L769-2: Formula: (and (= v_~t3_st~0_6 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_5)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} OutVars{~t3_st~0=v_~t3_st~0_6, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} AuxVars[] AssignedVars[~t3_st~0] 56177#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 56178#L370 [3281] L370-->L370-2: Formula: (> v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 56277#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 56272#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 56273#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 56290#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 55906#L389 [2193] L389-->L390: Formula: (= 1 v_~t5_pc~0_2) InVars {~t5_pc~0=v_~t5_pc~0_2} OutVars{~t5_pc~0=v_~t5_pc~0_2} AuxVars[] AssignedVars[] 55907#L390 [2343] L390-->L400: Formula: (and (= v_~E_5~0_5 1) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4 1)) InVars {~E_5~0=v_~E_5~0_5} OutVars{~E_5~0=v_~E_5~0_5, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 55876#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 55902#L785 [3291] L785-->L785-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_5) (= v_~t5_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} OutVars{~t5_st~0=v_~t5_st~0_6, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} AuxVars[] AssignedVars[~t5_st~0] 55924#L785-2 [3293] L785-2-->L669-1: Formula: (> 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 55926#L669-1 [3294] L669-1-->L674-1: Formula: (< 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 56100#L674-1 [3296] L674-1-->L679-1: Formula: (< 1 v_~T2_E~0_7) InVars {~T2_E~0=v_~T2_E~0_7} OutVars{~T2_E~0=v_~T2_E~0_7} AuxVars[] AssignedVars[] 56101#L679-1 [3299] L679-1-->L684-1: Formula: (< v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 56046#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 56047#L689-1 [3302] L689-1-->L694-1: Formula: (> v_~T5_E~0_7 1) InVars {~T5_E~0=v_~T5_E~0_7} OutVars{~T5_E~0=v_~T5_E~0_7} AuxVars[] AssignedVars[] 56203#L694-1 [3305] L694-1-->L699-1: Formula: (< v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 55970#L699-1 [3306] L699-1-->L704-1: Formula: (> v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 55971#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 55817#L709-1 [3310] L709-1-->L714-1: Formula: (> v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 55818#L714-1 [3313] L714-1-->L719-1: Formula: (> v_~E_4~0_9 1) InVars {~E_4~0=v_~E_4~0_9} OutVars{~E_4~0=v_~E_4~0_9} AuxVars[] AssignedVars[] 55910#L719-1 [2198] L719-1-->L930-1: Formula: (and (= v_~E_5~0_8 1) (= v_~E_5~0_7 2)) InVars {~E_5~0=v_~E_5~0_8} OutVars{~E_5~0=v_~E_5~0_7} AuxVars[] AssignedVars[~E_5~0] 55911#L930-1 312.69/160.50 [2019-03-28 12:22:11,842 INFO L796 eck$LassoCheckResult]: Loop: 55911#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 59653#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 59605#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 59594#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 59584#L501 [3784] L501-->L601-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 59585#L601-2 [2768] L601-2-->L601-4: Formula: (and (= v_~M_E~0_8 1) (= 0 v_~M_E~0_9)) InVars {~M_E~0=v_~M_E~0_9} OutVars{~M_E~0=v_~M_E~0_8} AuxVars[] AssignedVars[~M_E~0] 60500#L601-4 [3322] L601-4-->L606-3: Formula: (> v_~T1_E~0_10 0) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 60498#L606-3 [3326] L606-3-->L611-3: Formula: (< 0 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 60496#L611-3 [2256] L611-3-->L616-3: Formula: (and (= v_~T3_E~0_8 1) (= v_~T3_E~0_9 0)) InVars {~T3_E~0=v_~T3_E~0_9} OutVars{~T3_E~0=v_~T3_E~0_8} AuxVars[] AssignedVars[~T3_E~0] 60494#L616-3 [3339] L616-3-->L621-3: Formula: (> v_~T4_E~0_10 0) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 60491#L621-3 [3346] L621-3-->L626-3: Formula: (< 0 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 60489#L626-3 [2580] L626-3-->L631-3: Formula: (and (= v_~E_M~0_24 1) (= 0 v_~E_M~0_25)) InVars {~E_M~0=v_~E_M~0_25} OutVars{~E_M~0=v_~E_M~0_24} AuxVars[] AssignedVars[~E_M~0] 60487#L631-3 [3365] L631-3-->L636-3: Formula: (< 0 v_~E_1~0_26) InVars {~E_1~0=v_~E_1~0_26} OutVars{~E_1~0=v_~E_1~0_26} AuxVars[] AssignedVars[] 60485#L636-3 [3376] L636-3-->L641-3: Formula: (< 0 v_~E_2~0_26) InVars {~E_2~0=v_~E_2~0_26} OutVars{~E_2~0=v_~E_2~0_26} AuxVars[] AssignedVars[] 60483#L641-3 [3388] L641-3-->L646-3: Formula: (< 0 v_~E_3~0_26) InVars {~E_3~0=v_~E_3~0_26} OutVars{~E_3~0=v_~E_3~0_26} AuxVars[] AssignedVars[] 60480#L646-3 [3401] L646-3-->L651-3: Formula: (< 0 v_~E_4~0_26) InVars {~E_4~0=v_~E_4~0_26} OutVars{~E_4~0=v_~E_4~0_26} AuxVars[] AssignedVars[] 60478#L651-3 [3410] L651-3-->L656-3: Formula: (> 0 v_~E_5~0_26) InVars {~E_5~0=v_~E_5~0_26} OutVars{~E_5~0=v_~E_5~0_26} AuxVars[] AssignedVars[] 60476#L656-3 [2767] L656-3-->L294-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_37, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_37, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_22|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_22|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_22|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_37, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_37, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_22|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_22|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_22|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_22|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_37, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_37, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_37} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 60475#L294-21 [3426] L294-21-->L294-23: Formula: (< v_~m_pc~0_22 1) InVars {~m_pc~0=v_~m_pc~0_22} OutVars{~m_pc~0=v_~m_pc~0_22} AuxVars[] AssignedVars[] 60223#L294-23 [2803] L294-23-->L305-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_41 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_41} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 60470#L305-7 [3806] L305-7-->L745-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 60469#L745-21 [2835] L745-21-->L745-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_42) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} AuxVars[] AssignedVars[] 60468#L745-23 [2838] L745-23-->L313-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_43, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 59897#L313-21 [3469] L313-21-->L313-23: Formula: (< v_~t1_pc~0_22 1) InVars {~t1_pc~0=v_~t1_pc~0_22} OutVars{~t1_pc~0=v_~t1_pc~0_22} AuxVars[] AssignedVars[] 59895#L313-23 [2249] L313-23-->L324-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 59893#L324-7 [3813] L324-7-->L753-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 59891#L753-21 [2292] L753-21-->L753-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} AuxVars[] AssignedVars[] 59889#L753-23 [2297] L753-23-->L332-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_22|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 59887#L332-21 [3510] L332-21-->L332-23: Formula: (> 1 v_~t2_pc~0_22) InVars {~t2_pc~0=v_~t2_pc~0_22} OutVars{~t2_pc~0=v_~t2_pc~0_22} AuxVars[] AssignedVars[] 59401#L332-23 [2476] L332-23-->L343-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 59884#L343-7 [3820] L343-7-->L761-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 59882#L761-21 [2490] L761-21-->L761-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_42} AuxVars[] AssignedVars[] 59880#L761-23 [2493] L761-23-->L351-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_22|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 59878#L351-21 [3552] L351-21-->L351-23: Formula: (< v_~t3_pc~0_22 1) InVars {~t3_pc~0=v_~t3_pc~0_22} OutVars{~t3_pc~0=v_~t3_pc~0_22} AuxVars[] AssignedVars[] 58576#L351-23 [2660] L351-23-->L362-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 59866#L362-7 [3827] L362-7-->L769-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 59862#L769-21 [2534] L769-21-->L769-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} AuxVars[] AssignedVars[] 59858#L769-23 [2537] L769-23-->L370-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_43, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 59855#L370-21 [3594] L370-21-->L370-23: Formula: (< 1 v_~t4_pc~0_22) InVars {~t4_pc~0=v_~t4_pc~0_22} OutVars{~t4_pc~0=v_~t4_pc~0_22} AuxVars[] AssignedVars[] 59853#L370-23 [2934] L370-23-->L381-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 59851#L381-7 [3834] L381-7-->L777-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 59849#L777-21 [2705] L777-21-->L777-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} AuxVars[] AssignedVars[] 59847#L777-23 [2708] L777-23-->L389-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_22|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 59844#L389-21 [2132] L389-21-->L390-7: Formula: (= v_~t5_pc~0_21 1) InVars {~t5_pc~0=v_~t5_pc~0_21} OutVars{~t5_pc~0=v_~t5_pc~0_21} AuxVars[] AssignedVars[] 59841#L390-7 [2330] L390-7-->L400-7: Formula: (and (= 1 v_~E_5~0_27) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46 1)) InVars {~E_5~0=v_~E_5~0_27} OutVars{~E_5~0=v_~E_5~0_27, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 59839#L400-7 [3837] L400-7-->L785-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 59837#L785-21 [3654] L785-21-->L785-23: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_41 0) (= v_~t5_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} OutVars{~t5_st~0=v_~t5_st~0_19, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} AuxVars[] AssignedVars[~t5_st~0] 59835#L785-23 [2161] L785-23-->L669-3: Formula: (and (= v_~M_E~0_12 1) (= v_~M_E~0_11 2)) InVars {~M_E~0=v_~M_E~0_12} OutVars{~M_E~0=v_~M_E~0_11} AuxVars[] AssignedVars[~M_E~0] 59833#L669-3 [3660] L669-3-->L674-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 59829#L674-3 [3662] L674-3-->L679-3: Formula: (< 1 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 59826#L679-3 [3664] L679-3-->L684-3: Formula: (< 1 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 59823#L684-3 [3666] L684-3-->L689-3: Formula: (> v_~T4_E~0_13 1) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 59820#L689-3 [3668] L689-3-->L694-3: Formula: (< 1 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 59817#L694-3 [2405] L694-3-->L699-3: Formula: (and (= 1 v_~E_M~0_30) (= v_~E_M~0_29 2)) InVars {~E_M~0=v_~E_M~0_30} OutVars{~E_M~0=v_~E_M~0_29} AuxVars[] AssignedVars[~E_M~0] 59812#L699-3 [3673] L699-3-->L704-3: Formula: (< 1 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 59809#L704-3 [3675] L704-3-->L709-3: Formula: (< 1 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 59806#L709-3 [3677] L709-3-->L714-3: Formula: (< 1 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 59803#L714-3 [3678] L714-3-->L719-3: Formula: (< 1 v_~E_4~0_31) InVars {~E_4~0=v_~E_4~0_31} OutVars{~E_4~0=v_~E_4~0_31} AuxVars[] AssignedVars[] 59800#L719-3 [3680] L719-3-->L724-3: Formula: (> 1 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 59797#L724-3 [2818] L724-3-->L454-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_23} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 59790#L454-1 [2466] L454-1-->L486-1: Formula: (and (= 0 v_~m_st~0_20) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26 1)) InVars {~m_st~0=v_~m_st~0_20} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 59787#L486-1 [3838] L486-1-->L949: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret15, ULTIMATE.start_start_simulation_~tmp~3] 59781#L949 [3688] L949-->L949-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_1) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} AuxVars[] AssignedVars[] 59776#L949-1 [2479] L949-1-->L454-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_1} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 59721#L454-2 [2438] L454-2-->L486-2: Formula: (and (= v_~m_st~0_2 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4 1)) InVars {~m_st~0=v_~m_st~0_2} OutVars{~m_st~0=v_~m_st~0_2, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 59711#L486-2 [3840] L486-2-->L904: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 59674#L904 [2393] L904-->L911: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 59663#L911 [3851] L911-->L930-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_6|, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 55911#L930-1 312.69/160.50 [2019-03-28 12:22:11,843 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.50 [2019-03-28 12:22:11,843 INFO L82 PathProgramCache]: Analyzing trace with hash -578724389, now seen corresponding path program 1 times 312.69/160.50 [2019-03-28 12:22:11,843 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.50 [2019-03-28 12:22:11,843 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.50 [2019-03-28 12:22:11,844 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:11,844 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:11,844 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:11,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.50 [2019-03-28 12:22:11,887 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.50 [2019-03-28 12:22:11,887 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.50 [2019-03-28 12:22:11,887 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 312.69/160.50 [2019-03-28 12:22:11,888 INFO L799 eck$LassoCheckResult]: stem already infeasible 312.69/160.50 [2019-03-28 12:22:11,888 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.50 [2019-03-28 12:22:11,888 INFO L82 PathProgramCache]: Analyzing trace with hash -1096859496, now seen corresponding path program 2 times 312.69/160.50 [2019-03-28 12:22:11,888 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.50 [2019-03-28 12:22:11,888 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.50 [2019-03-28 12:22:11,889 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:11,889 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:11,889 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:11,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.50 [2019-03-28 12:22:11,909 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.50 [2019-03-28 12:22:11,910 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.50 [2019-03-28 12:22:11,910 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 312.69/160.50 [2019-03-28 12:22:11,910 INFO L811 eck$LassoCheckResult]: loop already infeasible 312.69/160.50 [2019-03-28 12:22:11,910 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. 312.69/160.50 [2019-03-28 12:22:11,910 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 312.69/160.50 [2019-03-28 12:22:11,911 INFO L87 Difference]: Start difference. First operand 4991 states and 8562 transitions. cyclomatic complexity: 3572 Second operand 6 states. 312.69/160.50 [2019-03-28 12:22:13,549 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.50 [2019-03-28 12:22:13,549 INFO L93 Difference]: Finished difference Result 11789 states and 20195 transitions. 312.69/160.50 [2019-03-28 12:22:13,549 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. 312.69/160.50 [2019-03-28 12:22:13,550 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11789 states and 20195 transitions. 312.69/160.50 [2019-03-28 12:22:13,593 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 11726 312.69/160.50 [2019-03-28 12:22:13,623 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11789 states to 11789 states and 20195 transitions. 312.69/160.50 [2019-03-28 12:22:13,623 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11789 312.69/160.50 [2019-03-28 12:22:13,633 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11789 312.69/160.50 [2019-03-28 12:22:13,633 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11789 states and 20195 transitions. 312.69/160.50 [2019-03-28 12:22:13,642 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.50 [2019-03-28 12:22:13,643 INFO L706 BuchiCegarLoop]: Abstraction has 11789 states and 20195 transitions. 312.69/160.50 [2019-03-28 12:22:13,649 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11789 states and 20195 transitions. 312.69/160.50 [2019-03-28 12:22:13,717 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11789 to 4999. 312.69/160.50 [2019-03-28 12:22:13,718 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4999 states. 312.69/160.50 [2019-03-28 12:22:13,727 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4999 states to 4999 states and 8481 transitions. 312.69/160.50 [2019-03-28 12:22:13,727 INFO L729 BuchiCegarLoop]: Abstraction has 4999 states and 8481 transitions. 312.69/160.50 [2019-03-28 12:22:13,727 INFO L609 BuchiCegarLoop]: Abstraction has 4999 states and 8481 transitions. 312.69/160.50 [2019-03-28 12:22:13,727 INFO L442 BuchiCegarLoop]: ======== Iteration 28============ 312.69/160.50 [2019-03-28 12:22:13,727 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4999 states and 8481 transitions. 312.69/160.50 [2019-03-28 12:22:13,742 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4936 312.69/160.50 [2019-03-28 12:22:13,742 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.50 [2019-03-28 12:22:13,742 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.50 [2019-03-28 12:22:13,744 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.50 [2019-03-28 12:22:13,744 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.50 [2019-03-28 12:22:13,745 INFO L794 eck$LassoCheckResult]: Stem: 73064#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 72846#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 72847#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 72917#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 72918#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 72850#L431-1 [2355] L431-1-->L436-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 72851#L436-1 [2735] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 72893#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 72894#L601-1 [3235] L601-1-->L606-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 72896#L606-1 [3236] L606-1-->L611-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 72774#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 72775#L616-1 [3240] L616-1-->L621-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 72640#L621-1 [3242] L621-1-->L626-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 72641#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 72745#L631-1 [3246] L631-1-->L636-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 72746#L636-1 [3248] L636-1-->L641-1: Formula: (> v_~E_2~0_4 0) InVars {~E_2~0=v_~E_2~0_4} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[] 72941#L641-1 [3251] L641-1-->L646-1: Formula: (> v_~E_3~0_4 0) InVars {~E_3~0=v_~E_3~0_4} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[] 72942#L646-1 [3253] L646-1-->L651-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 72883#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 72884#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 73182#L294 [3256] L294-->L294-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 73225#L294-2 [2905] L294-2-->L305: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 73240#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 73241#L745 [2925] L745-->L745-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_6) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} AuxVars[] AssignedVars[] 73254#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 72821#L313 [3262] L313-->L313-2: Formula: (< v_~t1_pc~0_3 1) InVars {~t1_pc~0=v_~t1_pc~0_3} OutVars{~t1_pc~0=v_~t1_pc~0_3} AuxVars[] AssignedVars[] 72822#L313-2 [2314] L313-2-->L324: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 72820#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 72657#L753 [2130] L753-->L753-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} AuxVars[] AssignedVars[] 72658#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 72661#L332 [3268] L332-->L332-2: Formula: (< v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 72856#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 72854#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 72855#L761 [2384] L761-->L761-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} AuxVars[] AssignedVars[] 72877#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 72878#L351 [3274] L351-->L351-2: Formula: (> 1 v_~t3_pc~0_3) InVars {~t3_pc~0=v_~t3_pc~0_3} OutVars{~t3_pc~0=v_~t3_pc~0_3} AuxVars[] AssignedVars[] 72998#L351-2 [2543] L351-2-->L362: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 72999#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 73023#L769 [3278] L769-->L769-2: Formula: (and (> 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_5) (= v_~t3_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} OutVars{~t3_st~0=v_~t3_st~0_6, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_5} AuxVars[] AssignedVars[~t3_st~0] 73030#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 73031#L370 [3281] L370-->L370-2: Formula: (> v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 73157#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 73155#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 73156#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 73179#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 72733#L389 [2193] L389-->L390: Formula: (= 1 v_~t5_pc~0_2) InVars {~t5_pc~0=v_~t5_pc~0_2} OutVars{~t5_pc~0=v_~t5_pc~0_2} AuxVars[] AssignedVars[] 72734#L390 [2343] L390-->L400: Formula: (and (= v_~E_5~0_5 1) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4 1)) InVars {~E_5~0=v_~E_5~0_5} OutVars{~E_5~0=v_~E_5~0_5, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 72695#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 72730#L785 [3291] L785-->L785-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_5) (= v_~t5_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} OutVars{~t5_st~0=v_~t5_st~0_6, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} AuxVars[] AssignedVars[~t5_st~0] 72754#L785-2 [3293] L785-2-->L669-1: Formula: (> 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 72755#L669-1 [3294] L669-1-->L674-1: Formula: (< 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 72939#L674-1 [3296] L674-1-->L679-1: Formula: (< 1 v_~T2_E~0_7) InVars {~T2_E~0=v_~T2_E~0_7} OutVars{~T2_E~0=v_~T2_E~0_7} AuxVars[] AssignedVars[] 72940#L679-1 [3299] L679-1-->L684-1: Formula: (< v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 72881#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 72882#L689-1 [3302] L689-1-->L694-1: Formula: (> v_~T5_E~0_7 1) InVars {~T5_E~0=v_~T5_E~0_7} OutVars{~T5_E~0=v_~T5_E~0_7} AuxVars[] AssignedVars[] 73056#L694-1 [3305] L694-1-->L699-1: Formula: (< v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 72796#L699-1 [3306] L699-1-->L704-1: Formula: (> v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 72797#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 72627#L709-1 [3310] L709-1-->L714-1: Formula: (> v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 72628#L714-1 [3313] L714-1-->L719-1: Formula: (> v_~E_4~0_9 1) InVars {~E_4~0=v_~E_4~0_9} OutVars{~E_4~0=v_~E_4~0_9} AuxVars[] AssignedVars[] 72739#L719-1 [2198] L719-1-->L930-1: Formula: (and (= v_~E_5~0_8 1) (= v_~E_5~0_7 2)) InVars {~E_5~0=v_~E_5~0_8} OutVars{~E_5~0=v_~E_5~0_7} AuxVars[] AssignedVars[~E_5~0] 72740#L930-1 312.69/160.50 [2019-03-28 12:22:13,746 INFO L796 eck$LassoCheckResult]: Loop: 72740#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 73817#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 73814#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 73806#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 73802#L501 [3784] L501-->L601-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 73803#L601-2 [2768] L601-2-->L601-4: Formula: (and (= v_~M_E~0_8 1) (= 0 v_~M_E~0_9)) InVars {~M_E~0=v_~M_E~0_9} OutVars{~M_E~0=v_~M_E~0_8} AuxVars[] AssignedVars[~M_E~0] 76915#L601-4 [3322] L601-4-->L606-3: Formula: (> v_~T1_E~0_10 0) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 76914#L606-3 [3326] L606-3-->L611-3: Formula: (< 0 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 76913#L611-3 [2256] L611-3-->L616-3: Formula: (and (= v_~T3_E~0_8 1) (= v_~T3_E~0_9 0)) InVars {~T3_E~0=v_~T3_E~0_9} OutVars{~T3_E~0=v_~T3_E~0_8} AuxVars[] AssignedVars[~T3_E~0] 76912#L616-3 [3339] L616-3-->L621-3: Formula: (> v_~T4_E~0_10 0) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 76911#L621-3 [3346] L621-3-->L626-3: Formula: (< 0 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 76910#L626-3 [2580] L626-3-->L631-3: Formula: (and (= v_~E_M~0_24 1) (= 0 v_~E_M~0_25)) InVars {~E_M~0=v_~E_M~0_25} OutVars{~E_M~0=v_~E_M~0_24} AuxVars[] AssignedVars[~E_M~0] 76909#L631-3 [3365] L631-3-->L636-3: Formula: (< 0 v_~E_1~0_26) InVars {~E_1~0=v_~E_1~0_26} OutVars{~E_1~0=v_~E_1~0_26} AuxVars[] AssignedVars[] 76908#L636-3 [3376] L636-3-->L641-3: Formula: (< 0 v_~E_2~0_26) InVars {~E_2~0=v_~E_2~0_26} OutVars{~E_2~0=v_~E_2~0_26} AuxVars[] AssignedVars[] 76907#L641-3 [3388] L641-3-->L646-3: Formula: (< 0 v_~E_3~0_26) InVars {~E_3~0=v_~E_3~0_26} OutVars{~E_3~0=v_~E_3~0_26} AuxVars[] AssignedVars[] 76906#L646-3 [3401] L646-3-->L651-3: Formula: (< 0 v_~E_4~0_26) InVars {~E_4~0=v_~E_4~0_26} OutVars{~E_4~0=v_~E_4~0_26} AuxVars[] AssignedVars[] 76905#L651-3 [3410] L651-3-->L656-3: Formula: (> 0 v_~E_5~0_26) InVars {~E_5~0=v_~E_5~0_26} OutVars{~E_5~0=v_~E_5~0_26} AuxVars[] AssignedVars[] 76903#L656-3 [2767] L656-3-->L294-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_37, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_37, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_22|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_22|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_22|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_37, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_37, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_22|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_22|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_22|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_22|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_37, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_37, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_37} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 76900#L294-21 [3426] L294-21-->L294-23: Formula: (< v_~m_pc~0_22 1) InVars {~m_pc~0=v_~m_pc~0_22} OutVars{~m_pc~0=v_~m_pc~0_22} AuxVars[] AssignedVars[] 76133#L294-23 [2803] L294-23-->L305-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_41 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_41} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 76134#L305-7 [3806] L305-7-->L745-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 76129#L745-21 [2835] L745-21-->L745-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_42) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} AuxVars[] AssignedVars[] 76130#L745-23 [2838] L745-23-->L313-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_43, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 76126#L313-21 [3469] L313-21-->L313-23: Formula: (< v_~t1_pc~0_22 1) InVars {~t1_pc~0=v_~t1_pc~0_22} OutVars{~t1_pc~0=v_~t1_pc~0_22} AuxVars[] AssignedVars[] 73693#L313-23 [2249] L313-23-->L324-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 76123#L324-7 [3813] L324-7-->L753-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 76124#L753-21 [2292] L753-21-->L753-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} AuxVars[] AssignedVars[] 76119#L753-23 [2297] L753-23-->L332-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_22|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 76120#L332-21 [3510] L332-21-->L332-23: Formula: (> 1 v_~t2_pc~0_22) InVars {~t2_pc~0=v_~t2_pc~0_22} OutVars{~t2_pc~0=v_~t2_pc~0_22} AuxVars[] AssignedVars[] 74712#L332-23 [2476] L332-23-->L343-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 76899#L343-7 [3820] L343-7-->L761-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 76898#L761-21 [2490] L761-21-->L761-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_42} AuxVars[] AssignedVars[] 76897#L761-23 [2493] L761-23-->L351-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_22|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 73974#L351-21 [3552] L351-21-->L351-23: Formula: (< v_~t3_pc~0_22 1) InVars {~t3_pc~0=v_~t3_pc~0_22} OutVars{~t3_pc~0=v_~t3_pc~0_22} AuxVars[] AssignedVars[] 73972#L351-23 [2660] L351-23-->L362-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 73970#L362-7 [3827] L362-7-->L769-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 73968#L769-21 [2534] L769-21-->L769-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} AuxVars[] AssignedVars[] 73967#L769-23 [2537] L769-23-->L370-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_43, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 73966#L370-21 [3594] L370-21-->L370-23: Formula: (< 1 v_~t4_pc~0_22) InVars {~t4_pc~0=v_~t4_pc~0_22} OutVars{~t4_pc~0=v_~t4_pc~0_22} AuxVars[] AssignedVars[] 73964#L370-23 [2934] L370-23-->L381-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 73963#L381-7 [3834] L381-7-->L777-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 73961#L777-21 [2705] L777-21-->L777-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} AuxVars[] AssignedVars[] 73959#L777-23 [2708] L777-23-->L389-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_22|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 73957#L389-21 [3636] L389-21-->L389-23: Formula: (> v_~t5_pc~0_22 1) InVars {~t5_pc~0=v_~t5_pc~0_22} OutVars{~t5_pc~0=v_~t5_pc~0_22} AuxVars[] AssignedVars[] 73955#L389-23 [2111] L389-23-->L400-7: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 73952#L400-7 [3837] L400-7-->L785-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 73951#L785-21 [3654] L785-21-->L785-23: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_41 0) (= v_~t5_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} OutVars{~t5_st~0=v_~t5_st~0_19, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} AuxVars[] AssignedVars[~t5_st~0] 73948#L785-23 [2161] L785-23-->L669-3: Formula: (and (= v_~M_E~0_12 1) (= v_~M_E~0_11 2)) InVars {~M_E~0=v_~M_E~0_12} OutVars{~M_E~0=v_~M_E~0_11} AuxVars[] AssignedVars[~M_E~0] 73946#L669-3 [3660] L669-3-->L674-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 73944#L674-3 [3662] L674-3-->L679-3: Formula: (< 1 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 73942#L679-3 [3664] L679-3-->L684-3: Formula: (< 1 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 73940#L684-3 [3666] L684-3-->L689-3: Formula: (> v_~T4_E~0_13 1) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 73938#L689-3 [3668] L689-3-->L694-3: Formula: (< 1 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 73935#L694-3 [2405] L694-3-->L699-3: Formula: (and (= 1 v_~E_M~0_30) (= v_~E_M~0_29 2)) InVars {~E_M~0=v_~E_M~0_30} OutVars{~E_M~0=v_~E_M~0_29} AuxVars[] AssignedVars[~E_M~0] 73933#L699-3 [3673] L699-3-->L704-3: Formula: (< 1 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 73931#L704-3 [3675] L704-3-->L709-3: Formula: (< 1 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 73929#L709-3 [3677] L709-3-->L714-3: Formula: (< 1 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 73927#L714-3 [3678] L714-3-->L719-3: Formula: (< 1 v_~E_4~0_31) InVars {~E_4~0=v_~E_4~0_31} OutVars{~E_4~0=v_~E_4~0_31} AuxVars[] AssignedVars[] 73925#L719-3 [3680] L719-3-->L724-3: Formula: (> 1 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 73923#L724-3 [2818] L724-3-->L454-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_23} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 73911#L454-1 [2466] L454-1-->L486-1: Formula: (and (= 0 v_~m_st~0_20) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26 1)) InVars {~m_st~0=v_~m_st~0_20} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 73909#L486-1 [3838] L486-1-->L949: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret15, ULTIMATE.start_start_simulation_~tmp~3] 73907#L949 [3688] L949-->L949-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_1) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} AuxVars[] AssignedVars[] 73903#L949-1 [2479] L949-1-->L454-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_1} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 73845#L454-2 [2438] L454-2-->L486-2: Formula: (and (= v_~m_st~0_2 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4 1)) InVars {~m_st~0=v_~m_st~0_2} OutVars{~m_st~0=v_~m_st~0_2, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 73840#L486-2 [3840] L486-2-->L904: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 73838#L904 [2393] L904-->L911: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 73827#L911 [3851] L911-->L930-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_6|, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 72740#L930-1 312.69/160.50 [2019-03-28 12:22:13,746 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.50 [2019-03-28 12:22:13,746 INFO L82 PathProgramCache]: Analyzing trace with hash -1823488870, now seen corresponding path program 1 times 312.69/160.50 [2019-03-28 12:22:13,746 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.50 [2019-03-28 12:22:13,747 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.50 [2019-03-28 12:22:13,747 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:13,747 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:13,748 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:13,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.50 [2019-03-28 12:22:13,783 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.50 [2019-03-28 12:22:13,783 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.50 [2019-03-28 12:22:13,783 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 312.69/160.50 [2019-03-28 12:22:13,784 INFO L799 eck$LassoCheckResult]: stem already infeasible 312.69/160.50 [2019-03-28 12:22:13,784 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.50 [2019-03-28 12:22:13,784 INFO L82 PathProgramCache]: Analyzing trace with hash -988910157, now seen corresponding path program 1 times 312.69/160.50 [2019-03-28 12:22:13,784 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.50 [2019-03-28 12:22:13,784 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.50 [2019-03-28 12:22:13,785 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:13,785 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:13,785 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:13,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.50 [2019-03-28 12:22:13,806 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.50 [2019-03-28 12:22:13,807 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.50 [2019-03-28 12:22:13,807 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 312.69/160.50 [2019-03-28 12:22:13,807 INFO L811 eck$LassoCheckResult]: loop already infeasible 312.69/160.50 [2019-03-28 12:22:13,808 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. 312.69/160.50 [2019-03-28 12:22:13,808 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 312.69/160.50 [2019-03-28 12:22:13,808 INFO L87 Difference]: Start difference. First operand 4999 states and 8481 transitions. cyclomatic complexity: 3483 Second operand 6 states. 312.69/160.50 [2019-03-28 12:22:14,496 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.50 [2019-03-28 12:22:14,496 INFO L93 Difference]: Finished difference Result 4999 states and 8380 transitions. 312.69/160.50 [2019-03-28 12:22:14,497 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. 312.69/160.50 [2019-03-28 12:22:14,497 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4999 states and 8380 transitions. 312.69/160.50 [2019-03-28 12:22:14,513 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4936 312.69/160.50 [2019-03-28 12:22:14,525 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4999 states to 4999 states and 8380 transitions. 312.69/160.50 [2019-03-28 12:22:14,525 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4999 312.69/160.50 [2019-03-28 12:22:14,528 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4999 312.69/160.50 [2019-03-28 12:22:14,529 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4999 states and 8380 transitions. 312.69/160.50 [2019-03-28 12:22:14,532 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.50 [2019-03-28 12:22:14,532 INFO L706 BuchiCegarLoop]: Abstraction has 4999 states and 8380 transitions. 312.69/160.50 [2019-03-28 12:22:14,535 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4999 states and 8380 transitions. 312.69/160.50 [2019-03-28 12:22:14,578 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4999 to 4999. 312.69/160.50 [2019-03-28 12:22:14,578 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4999 states. 312.69/160.50 [2019-03-28 12:22:14,587 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4999 states to 4999 states and 8380 transitions. 312.69/160.50 [2019-03-28 12:22:14,587 INFO L729 BuchiCegarLoop]: Abstraction has 4999 states and 8380 transitions. 312.69/160.50 [2019-03-28 12:22:14,587 INFO L609 BuchiCegarLoop]: Abstraction has 4999 states and 8380 transitions. 312.69/160.50 [2019-03-28 12:22:14,587 INFO L442 BuchiCegarLoop]: ======== Iteration 29============ 312.69/160.50 [2019-03-28 12:22:14,588 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4999 states and 8380 transitions. 312.69/160.50 [2019-03-28 12:22:14,602 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4936 312.69/160.50 [2019-03-28 12:22:14,602 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.50 [2019-03-28 12:22:14,602 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.50 [2019-03-28 12:22:14,604 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.50 [2019-03-28 12:22:14,604 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.50 [2019-03-28 12:22:14,605 INFO L794 eck$LassoCheckResult]: Stem: 83045#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 82842#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 82843#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 82909#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 82910#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 82844#L431-1 [2355] L431-1-->L436-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 82845#L436-1 [2735] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 82884#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 82885#L601-1 [3235] L601-1-->L606-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 82887#L606-1 [3236] L606-1-->L611-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 82771#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 82772#L616-1 [3240] L616-1-->L621-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 82656#L621-1 [3242] L621-1-->L626-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 82657#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 82743#L631-1 [3246] L631-1-->L636-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 82744#L636-1 [3248] L636-1-->L641-1: Formula: (> v_~E_2~0_4 0) InVars {~E_2~0=v_~E_2~0_4} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[] 82935#L641-1 [3251] L641-1-->L646-1: Formula: (> v_~E_3~0_4 0) InVars {~E_3~0=v_~E_3~0_4} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[] 82936#L646-1 [3253] L646-1-->L651-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 82875#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 82876#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 83123#L294 [3256] L294-->L294-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 83161#L294-2 [2905] L294-2-->L305: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 83176#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 83177#L745 [2925] L745-->L745-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_6) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} AuxVars[] AssignedVars[] 83184#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 82822#L313 [3262] L313-->L313-2: Formula: (< v_~t1_pc~0_3 1) InVars {~t1_pc~0=v_~t1_pc~0_3} OutVars{~t1_pc~0=v_~t1_pc~0_3} AuxVars[] AssignedVars[] 82823#L313-2 [2314] L313-2-->L324: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 82821#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 82671#L753 [2130] L753-->L753-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} AuxVars[] AssignedVars[] 82672#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 82676#L332 [3268] L332-->L332-2: Formula: (< v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 82852#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 82850#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 82851#L761 [2384] L761-->L761-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} AuxVars[] AssignedVars[] 82871#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 82872#L351 [3274] L351-->L351-2: Formula: (> 1 v_~t3_pc~0_3) InVars {~t3_pc~0=v_~t3_pc~0_3} OutVars{~t3_pc~0=v_~t3_pc~0_3} AuxVars[] AssignedVars[] 82989#L351-2 [2543] L351-2-->L362: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 82990#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 83008#L769 [2585] L769-->L769-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} AuxVars[] AssignedVars[] 83012#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 83013#L370 [3281] L370-->L370-2: Formula: (> v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 83108#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 83104#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 83105#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 83122#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 82734#L389 [2193] L389-->L390: Formula: (= 1 v_~t5_pc~0_2) InVars {~t5_pc~0=v_~t5_pc~0_2} OutVars{~t5_pc~0=v_~t5_pc~0_2} AuxVars[] AssignedVars[] 82735#L390 [2343] L390-->L400: Formula: (and (= v_~E_5~0_5 1) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4 1)) InVars {~E_5~0=v_~E_5~0_5} OutVars{~E_5~0=v_~E_5~0_5, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 82704#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 82733#L785 [3291] L785-->L785-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_5) (= v_~t5_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} OutVars{~t5_st~0=v_~t5_st~0_6, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} AuxVars[] AssignedVars[~t5_st~0] 82751#L785-2 [3293] L785-2-->L669-1: Formula: (> 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 82752#L669-1 [3294] L669-1-->L674-1: Formula: (< 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 82933#L674-1 [3296] L674-1-->L679-1: Formula: (< 1 v_~T2_E~0_7) InVars {~T2_E~0=v_~T2_E~0_7} OutVars{~T2_E~0=v_~T2_E~0_7} AuxVars[] AssignedVars[] 82934#L679-1 [3299] L679-1-->L684-1: Formula: (< v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 82873#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 82874#L689-1 [3302] L689-1-->L694-1: Formula: (> v_~T5_E~0_7 1) InVars {~T5_E~0=v_~T5_E~0_7} OutVars{~T5_E~0=v_~T5_E~0_7} AuxVars[] AssignedVars[] 83038#L694-1 [3305] L694-1-->L699-1: Formula: (< v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 82794#L699-1 [3306] L699-1-->L704-1: Formula: (> v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 82795#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 82645#L709-1 [3310] L709-1-->L714-1: Formula: (> v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 82646#L714-1 [3313] L714-1-->L719-1: Formula: (> v_~E_4~0_9 1) InVars {~E_4~0=v_~E_4~0_9} OutVars{~E_4~0=v_~E_4~0_9} AuxVars[] AssignedVars[] 82737#L719-1 [2198] L719-1-->L930-1: Formula: (and (= v_~E_5~0_8 1) (= v_~E_5~0_7 2)) InVars {~E_5~0=v_~E_5~0_8} OutVars{~E_5~0=v_~E_5~0_7} AuxVars[] AssignedVars[~E_5~0] 82738#L930-1 312.69/160.50 [2019-03-28 12:22:14,606 INFO L796 eck$LassoCheckResult]: Loop: 82738#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 84120#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 84117#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 84110#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 84107#L501 [3784] L501-->L601-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 84108#L601-2 [2768] L601-2-->L601-4: Formula: (and (= v_~M_E~0_8 1) (= 0 v_~M_E~0_9)) InVars {~M_E~0=v_~M_E~0_9} OutVars{~M_E~0=v_~M_E~0_8} AuxVars[] AssignedVars[~M_E~0] 87641#L601-4 [3322] L601-4-->L606-3: Formula: (> v_~T1_E~0_10 0) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 87640#L606-3 [3326] L606-3-->L611-3: Formula: (< 0 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 87639#L611-3 [2256] L611-3-->L616-3: Formula: (and (= v_~T3_E~0_8 1) (= v_~T3_E~0_9 0)) InVars {~T3_E~0=v_~T3_E~0_9} OutVars{~T3_E~0=v_~T3_E~0_8} AuxVars[] AssignedVars[~T3_E~0] 87638#L616-3 [3339] L616-3-->L621-3: Formula: (> v_~T4_E~0_10 0) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 82662#L621-3 [3346] L621-3-->L626-3: Formula: (< 0 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 82663#L626-3 [2580] L626-3-->L631-3: Formula: (and (= v_~E_M~0_24 1) (= 0 v_~E_M~0_25)) InVars {~E_M~0=v_~E_M~0_25} OutVars{~E_M~0=v_~E_M~0_24} AuxVars[] AssignedVars[~E_M~0] 83011#L631-3 [3365] L631-3-->L636-3: Formula: (< 0 v_~E_1~0_26) InVars {~E_1~0=v_~E_1~0_26} OutVars{~E_1~0=v_~E_1~0_26} AuxVars[] AssignedVars[] 83134#L636-3 [3376] L636-3-->L641-3: Formula: (< 0 v_~E_2~0_26) InVars {~E_2~0=v_~E_2~0_26} OutVars{~E_2~0=v_~E_2~0_26} AuxVars[] AssignedVars[] 82920#L641-3 [3388] L641-3-->L646-3: Formula: (< 0 v_~E_3~0_26) InVars {~E_3~0=v_~E_3~0_26} OutVars{~E_3~0=v_~E_3~0_26} AuxVars[] AssignedVars[] 82921#L646-3 [3401] L646-3-->L651-3: Formula: (< 0 v_~E_4~0_26) InVars {~E_4~0=v_~E_4~0_26} OutVars{~E_4~0=v_~E_4~0_26} AuxVars[] AssignedVars[] 82865#L651-3 [3410] L651-3-->L656-3: Formula: (> 0 v_~E_5~0_26) InVars {~E_5~0=v_~E_5~0_26} OutVars{~E_5~0=v_~E_5~0_26} AuxVars[] AssignedVars[] 82866#L656-3 [2767] L656-3-->L294-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_37, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_37, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_22|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_22|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_22|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_37, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_37, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_22|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_22|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_22|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_22|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_37, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_37, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_37} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 83135#L294-21 [3426] L294-21-->L294-23: Formula: (< v_~m_pc~0_22 1) InVars {~m_pc~0=v_~m_pc~0_22} OutVars{~m_pc~0=v_~m_pc~0_22} AuxVars[] AssignedVars[] 83131#L294-23 [2803] L294-23-->L305-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_41 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_41} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 83132#L305-7 [3806] L305-7-->L745-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 83147#L745-21 [2835] L745-21-->L745-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_42) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} AuxVars[] AssignedVars[] 83148#L745-23 [2838] L745-23-->L313-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_43, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 87630#L313-21 [3469] L313-21-->L313-23: Formula: (< v_~t1_pc~0_22 1) InVars {~t1_pc~0=v_~t1_pc~0_22} OutVars{~t1_pc~0=v_~t1_pc~0_22} AuxVars[] AssignedVars[] 82773#L313-23 [2249] L313-23-->L324-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 82774#L324-7 [3813] L324-7-->L753-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 82813#L753-21 [2292] L753-21-->L753-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} AuxVars[] AssignedVars[] 82819#L753-23 [2297] L753-23-->L332-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_22|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 82820#L332-21 [3510] L332-21-->L332-23: Formula: (> 1 v_~t2_pc~0_22) InVars {~t2_pc~0=v_~t2_pc~0_22} OutVars{~t2_pc~0=v_~t2_pc~0_22} AuxVars[] AssignedVars[] 86399#L332-23 [2476] L332-23-->L343-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 86398#L343-7 [3820] L343-7-->L761-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 86397#L761-21 [2490] L761-21-->L761-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_42} AuxVars[] AssignedVars[] 86396#L761-23 [2493] L761-23-->L351-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_22|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 84496#L351-21 [3552] L351-21-->L351-23: Formula: (< v_~t3_pc~0_22 1) InVars {~t3_pc~0=v_~t3_pc~0_22} OutVars{~t3_pc~0=v_~t3_pc~0_22} AuxVars[] AssignedVars[] 84494#L351-23 [2660] L351-23-->L362-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 84492#L362-7 [3827] L362-7-->L769-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 84489#L769-21 [2534] L769-21-->L769-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} AuxVars[] AssignedVars[] 84487#L769-23 [2537] L769-23-->L370-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_43, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 84485#L370-21 [3594] L370-21-->L370-23: Formula: (< 1 v_~t4_pc~0_22) InVars {~t4_pc~0=v_~t4_pc~0_22} OutVars{~t4_pc~0=v_~t4_pc~0_22} AuxVars[] AssignedVars[] 84482#L370-23 [2934] L370-23-->L381-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 84480#L381-7 [3834] L381-7-->L777-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 84478#L777-21 [2705] L777-21-->L777-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} AuxVars[] AssignedVars[] 84476#L777-23 [2708] L777-23-->L389-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_22|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 84474#L389-21 [2132] L389-21-->L390-7: Formula: (= v_~t5_pc~0_21 1) InVars {~t5_pc~0=v_~t5_pc~0_21} OutVars{~t5_pc~0=v_~t5_pc~0_21} AuxVars[] AssignedVars[] 84471#L390-7 [2330] L390-7-->L400-7: Formula: (and (= 1 v_~E_5~0_27) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46 1)) InVars {~E_5~0=v_~E_5~0_27} OutVars{~E_5~0=v_~E_5~0_27, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_46} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 84469#L400-7 [3837] L400-7-->L785-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 84468#L785-21 [3654] L785-21-->L785-23: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_41 0) (= v_~t5_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} OutVars{~t5_st~0=v_~t5_st~0_19, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} AuxVars[] AssignedVars[~t5_st~0] 84465#L785-23 [2161] L785-23-->L669-3: Formula: (and (= v_~M_E~0_12 1) (= v_~M_E~0_11 2)) InVars {~M_E~0=v_~M_E~0_12} OutVars{~M_E~0=v_~M_E~0_11} AuxVars[] AssignedVars[~M_E~0] 84463#L669-3 [3660] L669-3-->L674-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 84461#L674-3 [3662] L674-3-->L679-3: Formula: (< 1 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 84459#L679-3 [3664] L679-3-->L684-3: Formula: (< 1 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 84457#L684-3 [3666] L684-3-->L689-3: Formula: (> v_~T4_E~0_13 1) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 84455#L689-3 [3668] L689-3-->L694-3: Formula: (< 1 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 84452#L694-3 [2405] L694-3-->L699-3: Formula: (and (= 1 v_~E_M~0_30) (= v_~E_M~0_29 2)) InVars {~E_M~0=v_~E_M~0_30} OutVars{~E_M~0=v_~E_M~0_29} AuxVars[] AssignedVars[~E_M~0] 84450#L699-3 [3673] L699-3-->L704-3: Formula: (< 1 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 84448#L704-3 [3675] L704-3-->L709-3: Formula: (< 1 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 84446#L709-3 [3677] L709-3-->L714-3: Formula: (< 1 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 84444#L714-3 [3678] L714-3-->L719-3: Formula: (< 1 v_~E_4~0_31) InVars {~E_4~0=v_~E_4~0_31} OutVars{~E_4~0=v_~E_4~0_31} AuxVars[] AssignedVars[] 84442#L719-3 [3680] L719-3-->L724-3: Formula: (> 1 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 84440#L724-3 [2818] L724-3-->L454-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_23} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 84428#L454-1 [2466] L454-1-->L486-1: Formula: (and (= 0 v_~m_st~0_20) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26 1)) InVars {~m_st~0=v_~m_st~0_20} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 84426#L486-1 [3838] L486-1-->L949: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret15, ULTIMATE.start_start_simulation_~tmp~3] 84424#L949 [3688] L949-->L949-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_1) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} AuxVars[] AssignedVars[] 84422#L949-1 [2479] L949-1-->L454-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_1} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 84419#L454-2 [2438] L454-2-->L486-2: Formula: (and (= v_~m_st~0_2 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4 1)) InVars {~m_st~0=v_~m_st~0_2} OutVars{~m_st~0=v_~m_st~0_2, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 84415#L486-2 [3840] L486-2-->L904: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 84414#L904 [2393] L904-->L911: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 84412#L911 [3851] L911-->L930-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_6|, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 82738#L930-1 312.69/160.50 [2019-03-28 12:22:14,606 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.50 [2019-03-28 12:22:14,606 INFO L82 PathProgramCache]: Analyzing trace with hash -1156847707, now seen corresponding path program 1 times 312.69/160.50 [2019-03-28 12:22:14,606 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.50 [2019-03-28 12:22:14,607 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.50 [2019-03-28 12:22:14,607 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:14,608 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:14,608 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:14,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.50 [2019-03-28 12:22:14,629 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.50 [2019-03-28 12:22:14,629 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.50 [2019-03-28 12:22:14,629 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 312.69/160.50 [2019-03-28 12:22:14,630 INFO L799 eck$LassoCheckResult]: stem already infeasible 312.69/160.50 [2019-03-28 12:22:14,630 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.50 [2019-03-28 12:22:14,630 INFO L82 PathProgramCache]: Analyzing trace with hash -1096859496, now seen corresponding path program 3 times 312.69/160.50 [2019-03-28 12:22:14,630 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.50 [2019-03-28 12:22:14,630 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.50 [2019-03-28 12:22:14,631 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:14,631 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:14,631 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:14,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.50 [2019-03-28 12:22:14,651 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.50 [2019-03-28 12:22:14,651 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.50 [2019-03-28 12:22:14,652 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 312.69/160.50 [2019-03-28 12:22:14,652 INFO L811 eck$LassoCheckResult]: loop already infeasible 312.69/160.50 [2019-03-28 12:22:14,652 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 312.69/160.50 [2019-03-28 12:22:14,652 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 312.69/160.50 [2019-03-28 12:22:14,652 INFO L87 Difference]: Start difference. First operand 4999 states and 8380 transitions. cyclomatic complexity: 3382 Second operand 3 states. 312.69/160.50 [2019-03-28 12:22:15,397 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.50 [2019-03-28 12:22:15,397 INFO L93 Difference]: Finished difference Result 9454 states and 15841 transitions. 312.69/160.50 [2019-03-28 12:22:15,398 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 312.69/160.50 [2019-03-28 12:22:15,398 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9454 states and 15841 transitions. 312.69/160.50 [2019-03-28 12:22:15,433 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 9392 312.69/160.50 [2019-03-28 12:22:15,455 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9454 states to 9454 states and 15841 transitions. 312.69/160.50 [2019-03-28 12:22:15,456 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9454 312.69/160.50 [2019-03-28 12:22:15,464 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9454 312.69/160.50 [2019-03-28 12:22:15,464 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9454 states and 15841 transitions. 312.69/160.50 [2019-03-28 12:22:15,472 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.50 [2019-03-28 12:22:15,472 INFO L706 BuchiCegarLoop]: Abstraction has 9454 states and 15841 transitions. 312.69/160.50 [2019-03-28 12:22:15,476 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9454 states and 15841 transitions. 312.69/160.50 [2019-03-28 12:22:15,554 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9454 to 9278. 312.69/160.50 [2019-03-28 12:22:15,555 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9278 states. 312.69/160.50 [2019-03-28 12:22:15,572 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9278 states to 9278 states and 15537 transitions. 312.69/160.50 [2019-03-28 12:22:15,572 INFO L729 BuchiCegarLoop]: Abstraction has 9278 states and 15537 transitions. 312.69/160.50 [2019-03-28 12:22:15,572 INFO L609 BuchiCegarLoop]: Abstraction has 9278 states and 15537 transitions. 312.69/160.50 [2019-03-28 12:22:15,572 INFO L442 BuchiCegarLoop]: ======== Iteration 30============ 312.69/160.50 [2019-03-28 12:22:15,573 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9278 states and 15537 transitions. 312.69/160.50 [2019-03-28 12:22:15,601 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 9216 312.69/160.50 [2019-03-28 12:22:15,602 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.50 [2019-03-28 12:22:15,602 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.50 [2019-03-28 12:22:15,604 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.50 [2019-03-28 12:22:15,604 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.50 [2019-03-28 12:22:15,605 INFO L794 eck$LassoCheckResult]: Stem: 97513#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 97309#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 97310#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 97374#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 97375#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 97311#L431-1 [2355] L431-1-->L436-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 97312#L436-1 [2735] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 97351#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 97352#L601-1 [3235] L601-1-->L606-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 97355#L606-1 [3236] L606-1-->L611-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 97233#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 97234#L616-1 [3240] L616-1-->L621-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 97117#L621-1 [3242] L621-1-->L626-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 97118#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 97205#L631-1 [3246] L631-1-->L636-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 97206#L636-1 [3248] L636-1-->L641-1: Formula: (> v_~E_2~0_4 0) InVars {~E_2~0=v_~E_2~0_4} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[] 97401#L641-1 [3251] L641-1-->L646-1: Formula: (> v_~E_3~0_4 0) InVars {~E_3~0=v_~E_3~0_4} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[] 97402#L646-1 [3253] L646-1-->L651-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 97343#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 97344#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 97585#L294 [3256] L294-->L294-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 97625#L294-2 [2905] L294-2-->L305: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 97642#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 97643#L745 [2925] L745-->L745-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_6) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} AuxVars[] AssignedVars[] 97656#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 97288#L313 [3262] L313-->L313-2: Formula: (< v_~t1_pc~0_3 1) InVars {~t1_pc~0=v_~t1_pc~0_3} OutVars{~t1_pc~0=v_~t1_pc~0_3} AuxVars[] AssignedVars[] 97289#L313-2 [2314] L313-2-->L324: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 97287#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 97132#L753 [2130] L753-->L753-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} AuxVars[] AssignedVars[] 97133#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 97138#L332 [3268] L332-->L332-2: Formula: (< v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 97319#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 97317#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 97318#L761 [2384] L761-->L761-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} AuxVars[] AssignedVars[] 97338#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 97339#L351 [3274] L351-->L351-2: Formula: (> 1 v_~t3_pc~0_3) InVars {~t3_pc~0=v_~t3_pc~0_3} OutVars{~t3_pc~0=v_~t3_pc~0_3} AuxVars[] AssignedVars[] 97456#L351-2 [2543] L351-2-->L362: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 97457#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 97476#L769 [2585] L769-->L769-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} AuxVars[] AssignedVars[] 97479#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 97480#L370 [3280] L370-->L370-2: Formula: (< v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 97574#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 97570#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 97571#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 97584#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 97196#L389 [2193] L389-->L390: Formula: (= 1 v_~t5_pc~0_2) InVars {~t5_pc~0=v_~t5_pc~0_2} OutVars{~t5_pc~0=v_~t5_pc~0_2} AuxVars[] AssignedVars[] 97197#L390 [2343] L390-->L400: Formula: (and (= v_~E_5~0_5 1) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4 1)) InVars {~E_5~0=v_~E_5~0_5} OutVars{~E_5~0=v_~E_5~0_5, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_4} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 97165#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 97192#L785 [3291] L785-->L785-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_5) (= v_~t5_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} OutVars{~t5_st~0=v_~t5_st~0_6, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} AuxVars[] AssignedVars[~t5_st~0] 97212#L785-2 [3293] L785-2-->L669-1: Formula: (> 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 97214#L669-1 [3294] L669-1-->L674-1: Formula: (< 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 97399#L674-1 [3296] L674-1-->L679-1: Formula: (< 1 v_~T2_E~0_7) InVars {~T2_E~0=v_~T2_E~0_7} OutVars{~T2_E~0=v_~T2_E~0_7} AuxVars[] AssignedVars[] 97400#L679-1 [3299] L679-1-->L684-1: Formula: (< v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 97341#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 97342#L689-1 [3302] L689-1-->L694-1: Formula: (> v_~T5_E~0_7 1) InVars {~T5_E~0=v_~T5_E~0_7} OutVars{~T5_E~0=v_~T5_E~0_7} AuxVars[] AssignedVars[] 97505#L694-1 [3305] L694-1-->L699-1: Formula: (< v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 97260#L699-1 [3306] L699-1-->L704-1: Formula: (> v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 97261#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 97106#L709-1 [3310] L709-1-->L714-1: Formula: (> v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 97107#L714-1 [3313] L714-1-->L719-1: Formula: (> v_~E_4~0_9 1) InVars {~E_4~0=v_~E_4~0_9} OutVars{~E_4~0=v_~E_4~0_9} AuxVars[] AssignedVars[] 97199#L719-1 [2198] L719-1-->L930-1: Formula: (and (= v_~E_5~0_8 1) (= v_~E_5~0_7 2)) InVars {~E_5~0=v_~E_5~0_8} OutVars{~E_5~0=v_~E_5~0_7} AuxVars[] AssignedVars[~E_5~0] 97200#L930-1 312.69/160.50 [2019-03-28 12:22:15,606 INFO L796 eck$LassoCheckResult]: Loop: 97200#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 102181#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 102180#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 102173#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 102170#L501 [3784] L501-->L601-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 102171#L601-2 [2768] L601-2-->L601-4: Formula: (and (= v_~M_E~0_8 1) (= 0 v_~M_E~0_9)) InVars {~M_E~0=v_~M_E~0_9} OutVars{~M_E~0=v_~M_E~0_8} AuxVars[] AssignedVars[~M_E~0] 106268#L601-4 [3322] L601-4-->L606-3: Formula: (> v_~T1_E~0_10 0) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 106267#L606-3 [3326] L606-3-->L611-3: Formula: (< 0 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 106266#L611-3 [2256] L611-3-->L616-3: Formula: (and (= v_~T3_E~0_8 1) (= v_~T3_E~0_9 0)) InVars {~T3_E~0=v_~T3_E~0_9} OutVars{~T3_E~0=v_~T3_E~0_8} AuxVars[] AssignedVars[~T3_E~0] 106117#L616-3 [3339] L616-3-->L621-3: Formula: (> v_~T4_E~0_10 0) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 106116#L621-3 [3346] L621-3-->L626-3: Formula: (< 0 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 106115#L626-3 [2580] L626-3-->L631-3: Formula: (and (= v_~E_M~0_24 1) (= 0 v_~E_M~0_25)) InVars {~E_M~0=v_~E_M~0_25} OutVars{~E_M~0=v_~E_M~0_24} AuxVars[] AssignedVars[~E_M~0] 106007#L631-3 [3365] L631-3-->L636-3: Formula: (< 0 v_~E_1~0_26) InVars {~E_1~0=v_~E_1~0_26} OutVars{~E_1~0=v_~E_1~0_26} AuxVars[] AssignedVars[] 106003#L636-3 [3376] L636-3-->L641-3: Formula: (< 0 v_~E_2~0_26) InVars {~E_2~0=v_~E_2~0_26} OutVars{~E_2~0=v_~E_2~0_26} AuxVars[] AssignedVars[] 105999#L641-3 [3388] L641-3-->L646-3: Formula: (< 0 v_~E_3~0_26) InVars {~E_3~0=v_~E_3~0_26} OutVars{~E_3~0=v_~E_3~0_26} AuxVars[] AssignedVars[] 105996#L646-3 [3401] L646-3-->L651-3: Formula: (< 0 v_~E_4~0_26) InVars {~E_4~0=v_~E_4~0_26} OutVars{~E_4~0=v_~E_4~0_26} AuxVars[] AssignedVars[] 105992#L651-3 [3410] L651-3-->L656-3: Formula: (> 0 v_~E_5~0_26) InVars {~E_5~0=v_~E_5~0_26} OutVars{~E_5~0=v_~E_5~0_26} AuxVars[] AssignedVars[] 105989#L656-3 [2767] L656-3-->L294-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_37, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_37, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_22|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_22|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_22|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_37, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_37, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_22|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_22|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_22|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_22|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_37, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_37, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_37} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 105493#L294-21 [3426] L294-21-->L294-23: Formula: (< v_~m_pc~0_22 1) InVars {~m_pc~0=v_~m_pc~0_22} OutVars{~m_pc~0=v_~m_pc~0_22} AuxVars[] AssignedVars[] 105491#L294-23 [2803] L294-23-->L305-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_41 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_41} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 105488#L305-7 [3806] L305-7-->L745-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 105486#L745-21 [2835] L745-21-->L745-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_42) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} AuxVars[] AssignedVars[] 105484#L745-23 [2838] L745-23-->L313-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_43, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 105482#L313-21 [3469] L313-21-->L313-23: Formula: (< v_~t1_pc~0_22 1) InVars {~t1_pc~0=v_~t1_pc~0_22} OutVars{~t1_pc~0=v_~t1_pc~0_22} AuxVars[] AssignedVars[] 105079#L313-23 [2249] L313-23-->L324-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 105479#L324-7 [3813] L324-7-->L753-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 105476#L753-21 [2292] L753-21-->L753-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} AuxVars[] AssignedVars[] 105474#L753-23 [2297] L753-23-->L332-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_22|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 105472#L332-21 [3510] L332-21-->L332-23: Formula: (> 1 v_~t2_pc~0_22) InVars {~t2_pc~0=v_~t2_pc~0_22} OutVars{~t2_pc~0=v_~t2_pc~0_22} AuxVars[] AssignedVars[] 105471#L332-23 [2476] L332-23-->L343-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 105470#L343-7 [3820] L343-7-->L761-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 103323#L761-21 [2490] L761-21-->L761-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_42} AuxVars[] AssignedVars[] 103324#L761-23 [2493] L761-23-->L351-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_22|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 102282#L351-21 [3552] L351-21-->L351-23: Formula: (< v_~t3_pc~0_22 1) InVars {~t3_pc~0=v_~t3_pc~0_22} OutVars{~t3_pc~0=v_~t3_pc~0_22} AuxVars[] AssignedVars[] 102281#L351-23 [2660] L351-23-->L362-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 102280#L362-7 [3827] L362-7-->L769-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 102279#L769-21 [2534] L769-21-->L769-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} AuxVars[] AssignedVars[] 102278#L769-23 [2537] L769-23-->L370-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_43, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 102277#L370-21 [3595] L370-21-->L370-23: Formula: (> 1 v_~t4_pc~0_22) InVars {~t4_pc~0=v_~t4_pc~0_22} OutVars{~t4_pc~0=v_~t4_pc~0_22} AuxVars[] AssignedVars[] 100613#L370-23 [2934] L370-23-->L381-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 102276#L381-7 [3834] L381-7-->L777-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 102275#L777-21 [2705] L777-21-->L777-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} AuxVars[] AssignedVars[] 102273#L777-23 [2708] L777-23-->L389-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_22|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 102271#L389-21 [3636] L389-21-->L389-23: Formula: (> v_~t5_pc~0_22 1) InVars {~t5_pc~0=v_~t5_pc~0_22} OutVars{~t5_pc~0=v_~t5_pc~0_22} AuxVars[] AssignedVars[] 102269#L389-23 [2111] L389-23-->L400-7: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 102266#L400-7 [3837] L400-7-->L785-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 102264#L785-21 [3654] L785-21-->L785-23: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_41 0) (= v_~t5_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} OutVars{~t5_st~0=v_~t5_st~0_19, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} AuxVars[] AssignedVars[~t5_st~0] 102262#L785-23 [2161] L785-23-->L669-3: Formula: (and (= v_~M_E~0_12 1) (= v_~M_E~0_11 2)) InVars {~M_E~0=v_~M_E~0_12} OutVars{~M_E~0=v_~M_E~0_11} AuxVars[] AssignedVars[~M_E~0] 102261#L669-3 [3660] L669-3-->L674-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 102259#L674-3 [3662] L674-3-->L679-3: Formula: (< 1 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 102257#L679-3 [3664] L679-3-->L684-3: Formula: (< 1 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 102255#L684-3 [3666] L684-3-->L689-3: Formula: (> v_~T4_E~0_13 1) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 102253#L689-3 [3668] L689-3-->L694-3: Formula: (< 1 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 102250#L694-3 [2405] L694-3-->L699-3: Formula: (and (= 1 v_~E_M~0_30) (= v_~E_M~0_29 2)) InVars {~E_M~0=v_~E_M~0_30} OutVars{~E_M~0=v_~E_M~0_29} AuxVars[] AssignedVars[~E_M~0] 102248#L699-3 [3673] L699-3-->L704-3: Formula: (< 1 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 102246#L704-3 [3675] L704-3-->L709-3: Formula: (< 1 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 102244#L709-3 [3677] L709-3-->L714-3: Formula: (< 1 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 102242#L714-3 [3678] L714-3-->L719-3: Formula: (< 1 v_~E_4~0_31) InVars {~E_4~0=v_~E_4~0_31} OutVars{~E_4~0=v_~E_4~0_31} AuxVars[] AssignedVars[] 102240#L719-3 [3680] L719-3-->L724-3: Formula: (> 1 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 102238#L724-3 [2818] L724-3-->L454-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_23} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 102226#L454-1 [2466] L454-1-->L486-1: Formula: (and (= 0 v_~m_st~0_20) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26 1)) InVars {~m_st~0=v_~m_st~0_20} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 102224#L486-1 [3838] L486-1-->L949: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret15, ULTIMATE.start_start_simulation_~tmp~3] 102223#L949 [3688] L949-->L949-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_1) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} AuxVars[] AssignedVars[] 102221#L949-1 [2479] L949-1-->L454-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_1} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 102218#L454-2 [2438] L454-2-->L486-2: Formula: (and (= v_~m_st~0_2 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4 1)) InVars {~m_st~0=v_~m_st~0_2} OutVars{~m_st~0=v_~m_st~0_2, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 102213#L486-2 [3840] L486-2-->L904: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 102211#L904 [2393] L904-->L911: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 102209#L911 [3851] L911-->L930-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_6|, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 97200#L930-1 312.69/160.50 [2019-03-28 12:22:15,607 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.50 [2019-03-28 12:22:15,607 INFO L82 PathProgramCache]: Analyzing trace with hash -1368198620, now seen corresponding path program 1 times 312.69/160.50 [2019-03-28 12:22:15,607 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.50 [2019-03-28 12:22:15,607 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.50 [2019-03-28 12:22:15,608 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:15,608 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:15,608 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:15,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.50 [2019-03-28 12:22:15,630 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.50 [2019-03-28 12:22:15,630 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.50 [2019-03-28 12:22:15,630 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 312.69/160.50 [2019-03-28 12:22:15,630 INFO L799 eck$LassoCheckResult]: stem already infeasible 312.69/160.50 [2019-03-28 12:22:15,631 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.50 [2019-03-28 12:22:15,631 INFO L82 PathProgramCache]: Analyzing trace with hash -977594030, now seen corresponding path program 1 times 312.69/160.50 [2019-03-28 12:22:15,631 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.50 [2019-03-28 12:22:15,631 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.50 [2019-03-28 12:22:15,632 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:15,632 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:15,632 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:15,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.50 [2019-03-28 12:22:15,656 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.50 [2019-03-28 12:22:15,656 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.50 [2019-03-28 12:22:15,657 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 312.69/160.50 [2019-03-28 12:22:15,657 INFO L811 eck$LassoCheckResult]: loop already infeasible 312.69/160.50 [2019-03-28 12:22:15,657 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 312.69/160.50 [2019-03-28 12:22:15,657 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 312.69/160.50 [2019-03-28 12:22:15,657 INFO L87 Difference]: Start difference. First operand 9278 states and 15537 transitions. cyclomatic complexity: 6260 Second operand 3 states. 312.69/160.50 [2019-03-28 12:22:16,283 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.50 [2019-03-28 12:22:16,284 INFO L93 Difference]: Finished difference Result 17373 states and 28788 transitions. 312.69/160.50 [2019-03-28 12:22:16,284 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 312.69/160.50 [2019-03-28 12:22:16,284 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17373 states and 28788 transitions. 312.69/160.50 [2019-03-28 12:22:16,356 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 17312 312.69/160.50 [2019-03-28 12:22:16,399 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17373 states to 17373 states and 28788 transitions. 312.69/160.50 [2019-03-28 12:22:16,399 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17373 312.69/160.50 [2019-03-28 12:22:16,412 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17373 312.69/160.50 [2019-03-28 12:22:16,412 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17373 states and 28788 transitions. 312.69/160.50 [2019-03-28 12:22:16,425 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.50 [2019-03-28 12:22:16,425 INFO L706 BuchiCegarLoop]: Abstraction has 17373 states and 28788 transitions. 312.69/160.50 [2019-03-28 12:22:16,432 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17373 states and 28788 transitions. 312.69/160.50 [2019-03-28 12:22:16,583 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17373 to 17213. 312.69/160.50 [2019-03-28 12:22:16,583 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17213 states. 312.69/160.50 [2019-03-28 12:22:16,621 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17213 states to 17213 states and 28564 transitions. 312.69/160.50 [2019-03-28 12:22:16,621 INFO L729 BuchiCegarLoop]: Abstraction has 17213 states and 28564 transitions. 312.69/160.50 [2019-03-28 12:22:16,621 INFO L609 BuchiCegarLoop]: Abstraction has 17213 states and 28564 transitions. 312.69/160.50 [2019-03-28 12:22:16,621 INFO L442 BuchiCegarLoop]: ======== Iteration 31============ 312.69/160.50 [2019-03-28 12:22:16,622 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17213 states and 28564 transitions. 312.69/160.50 [2019-03-28 12:22:16,747 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 17152 312.69/160.50 [2019-03-28 12:22:16,747 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.50 [2019-03-28 12:22:16,747 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.50 [2019-03-28 12:22:16,751 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.50 [2019-03-28 12:22:16,751 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.50 [2019-03-28 12:22:16,752 INFO L794 eck$LassoCheckResult]: Stem: 124185#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 123982#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 123983#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 124047#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 124048#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 123984#L431-1 [2355] L431-1-->L436-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 123985#L436-1 [2735] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 124023#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 124024#L601-1 [3235] L601-1-->L606-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 124027#L606-1 [3236] L606-1-->L611-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 123889#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 123890#L616-1 [3240] L616-1-->L621-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 123775#L621-1 [3242] L621-1-->L626-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 123776#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 123861#L631-1 [3246] L631-1-->L636-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 123862#L636-1 [3248] L636-1-->L641-1: Formula: (> v_~E_2~0_4 0) InVars {~E_2~0=v_~E_2~0_4} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[] 124075#L641-1 [3251] L641-1-->L646-1: Formula: (> v_~E_3~0_4 0) InVars {~E_3~0=v_~E_3~0_4} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[] 124076#L646-1 [3253] L646-1-->L651-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 124015#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 124016#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 124269#L294 [3256] L294-->L294-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 124308#L294-2 [2905] L294-2-->L305: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 124328#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 124329#L745 [2925] L745-->L745-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_6) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} AuxVars[] AssignedVars[] 124343#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 123942#L313 [3262] L313-->L313-2: Formula: (< v_~t1_pc~0_3 1) InVars {~t1_pc~0=v_~t1_pc~0_3} OutVars{~t1_pc~0=v_~t1_pc~0_3} AuxVars[] AssignedVars[] 123943#L313-2 [2314] L313-2-->L324: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 123940#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 123791#L753 [2130] L753-->L753-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} AuxVars[] AssignedVars[] 123792#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 123796#L332 [3268] L332-->L332-2: Formula: (< v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 123992#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 123990#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 123991#L761 [2384] L761-->L761-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} AuxVars[] AssignedVars[] 124011#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 124012#L351 [3274] L351-->L351-2: Formula: (> 1 v_~t3_pc~0_3) InVars {~t3_pc~0=v_~t3_pc~0_3} OutVars{~t3_pc~0=v_~t3_pc~0_3} AuxVars[] AssignedVars[] 124129#L351-2 [2543] L351-2-->L362: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 124130#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 124147#L769 [2585] L769-->L769-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} AuxVars[] AssignedVars[] 124151#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 124152#L370 [3280] L370-->L370-2: Formula: (< v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 124252#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 124248#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 124249#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 124268#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 123853#L389 [3286] L389-->L389-2: Formula: (> 1 v_~t5_pc~0_3) InVars {~t5_pc~0=v_~t5_pc~0_3} OutVars{~t5_pc~0=v_~t5_pc~0_3} AuxVars[] AssignedVars[] 123821#L389-2 [2164] L389-2-->L400: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 123822#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 123849#L785 [3291] L785-->L785-2: Formula: (and (< 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_5) (= v_~t5_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} OutVars{~t5_st~0=v_~t5_st~0_6, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} AuxVars[] AssignedVars[~t5_st~0] 123868#L785-2 [3293] L785-2-->L669-1: Formula: (> 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 123870#L669-1 [3294] L669-1-->L674-1: Formula: (< 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 124073#L674-1 [3296] L674-1-->L679-1: Formula: (< 1 v_~T2_E~0_7) InVars {~T2_E~0=v_~T2_E~0_7} OutVars{~T2_E~0=v_~T2_E~0_7} AuxVars[] AssignedVars[] 124074#L679-1 [3299] L679-1-->L684-1: Formula: (< v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 124013#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 124014#L689-1 [3302] L689-1-->L694-1: Formula: (> v_~T5_E~0_7 1) InVars {~T5_E~0=v_~T5_E~0_7} OutVars{~T5_E~0=v_~T5_E~0_7} AuxVars[] AssignedVars[] 124177#L694-1 [3305] L694-1-->L699-1: Formula: (< v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 123912#L699-1 [3306] L699-1-->L704-1: Formula: (> v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 123913#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 123765#L709-1 [3310] L709-1-->L714-1: Formula: (> v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 123766#L714-1 [3313] L714-1-->L719-1: Formula: (> v_~E_4~0_9 1) InVars {~E_4~0=v_~E_4~0_9} OutVars{~E_4~0=v_~E_4~0_9} AuxVars[] AssignedVars[] 123855#L719-1 [2198] L719-1-->L930-1: Formula: (and (= v_~E_5~0_8 1) (= v_~E_5~0_7 2)) InVars {~E_5~0=v_~E_5~0_8} OutVars{~E_5~0=v_~E_5~0_7} AuxVars[] AssignedVars[~E_5~0] 123856#L930-1 312.69/160.50 [2019-03-28 12:22:16,753 INFO L796 eck$LassoCheckResult]: Loop: 123856#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 132674#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 132717#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 132710#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 132703#L501 [3784] L501-->L601-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 132704#L601-2 [2768] L601-2-->L601-4: Formula: (and (= v_~M_E~0_8 1) (= 0 v_~M_E~0_9)) InVars {~M_E~0=v_~M_E~0_9} OutVars{~M_E~0=v_~M_E~0_8} AuxVars[] AssignedVars[~M_E~0] 140516#L601-4 [3322] L601-4-->L606-3: Formula: (> v_~T1_E~0_10 0) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 140515#L606-3 [3326] L606-3-->L611-3: Formula: (< 0 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 140514#L611-3 [2256] L611-3-->L616-3: Formula: (and (= v_~T3_E~0_8 1) (= v_~T3_E~0_9 0)) InVars {~T3_E~0=v_~T3_E~0_9} OutVars{~T3_E~0=v_~T3_E~0_8} AuxVars[] AssignedVars[~T3_E~0] 140513#L616-3 [3339] L616-3-->L621-3: Formula: (> v_~T4_E~0_10 0) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 140512#L621-3 [3346] L621-3-->L626-3: Formula: (< 0 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 140511#L626-3 [2580] L626-3-->L631-3: Formula: (and (= v_~E_M~0_24 1) (= 0 v_~E_M~0_25)) InVars {~E_M~0=v_~E_M~0_25} OutVars{~E_M~0=v_~E_M~0_24} AuxVars[] AssignedVars[~E_M~0] 140509#L631-3 [3365] L631-3-->L636-3: Formula: (< 0 v_~E_1~0_26) InVars {~E_1~0=v_~E_1~0_26} OutVars{~E_1~0=v_~E_1~0_26} AuxVars[] AssignedVars[] 140508#L636-3 [3376] L636-3-->L641-3: Formula: (< 0 v_~E_2~0_26) InVars {~E_2~0=v_~E_2~0_26} OutVars{~E_2~0=v_~E_2~0_26} AuxVars[] AssignedVars[] 140507#L641-3 [3388] L641-3-->L646-3: Formula: (< 0 v_~E_3~0_26) InVars {~E_3~0=v_~E_3~0_26} OutVars{~E_3~0=v_~E_3~0_26} AuxVars[] AssignedVars[] 140504#L646-3 [3401] L646-3-->L651-3: Formula: (< 0 v_~E_4~0_26) InVars {~E_4~0=v_~E_4~0_26} OutVars{~E_4~0=v_~E_4~0_26} AuxVars[] AssignedVars[] 140502#L651-3 [3410] L651-3-->L656-3: Formula: (> 0 v_~E_5~0_26) InVars {~E_5~0=v_~E_5~0_26} OutVars{~E_5~0=v_~E_5~0_26} AuxVars[] AssignedVars[] 139699#L656-3 [2767] L656-3-->L294-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_37, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_37, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_22|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_22|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_22|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_37, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_37, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_22|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_22|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_22|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_22|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_37, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_37, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_37} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 138617#L294-21 [3426] L294-21-->L294-23: Formula: (< v_~m_pc~0_22 1) InVars {~m_pc~0=v_~m_pc~0_22} OutVars{~m_pc~0=v_~m_pc~0_22} AuxVars[] AssignedVars[] 138614#L294-23 [2803] L294-23-->L305-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_41 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_41} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 138612#L305-7 [3806] L305-7-->L745-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 138609#L745-21 [2835] L745-21-->L745-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_42) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} AuxVars[] AssignedVars[] 138607#L745-23 [2838] L745-23-->L313-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_43, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 138585#L313-21 [3469] L313-21-->L313-23: Formula: (< v_~t1_pc~0_22 1) InVars {~t1_pc~0=v_~t1_pc~0_22} OutVars{~t1_pc~0=v_~t1_pc~0_22} AuxVars[] AssignedVars[] 138583#L313-23 [2249] L313-23-->L324-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 138578#L324-7 [3813] L324-7-->L753-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 138572#L753-21 [2292] L753-21-->L753-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} AuxVars[] AssignedVars[] 138567#L753-23 [2297] L753-23-->L332-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_22|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 138497#L332-21 [3510] L332-21-->L332-23: Formula: (> 1 v_~t2_pc~0_22) InVars {~t2_pc~0=v_~t2_pc~0_22} OutVars{~t2_pc~0=v_~t2_pc~0_22} AuxVars[] AssignedVars[] 138491#L332-23 [2476] L332-23-->L343-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 138485#L343-7 [3820] L343-7-->L761-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 138478#L761-21 [2490] L761-21-->L761-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_42} AuxVars[] AssignedVars[] 138472#L761-23 [2493] L761-23-->L351-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_22|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 132798#L351-21 [3552] L351-21-->L351-23: Formula: (< v_~t3_pc~0_22 1) InVars {~t3_pc~0=v_~t3_pc~0_22} OutVars{~t3_pc~0=v_~t3_pc~0_22} AuxVars[] AssignedVars[] 132797#L351-23 [2660] L351-23-->L362-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 132796#L362-7 [3827] L362-7-->L769-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 132795#L769-21 [2534] L769-21-->L769-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} AuxVars[] AssignedVars[] 132793#L769-23 [2537] L769-23-->L370-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_43, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 132791#L370-21 [3595] L370-21-->L370-23: Formula: (> 1 v_~t4_pc~0_22) InVars {~t4_pc~0=v_~t4_pc~0_22} OutVars{~t4_pc~0=v_~t4_pc~0_22} AuxVars[] AssignedVars[] 132789#L370-23 [2934] L370-23-->L381-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 132787#L381-7 [3834] L381-7-->L777-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 132785#L777-21 [2705] L777-21-->L777-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} AuxVars[] AssignedVars[] 132783#L777-23 [2708] L777-23-->L389-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_22|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 132781#L389-21 [3637] L389-21-->L389-23: Formula: (< v_~t5_pc~0_22 1) InVars {~t5_pc~0=v_~t5_pc~0_22} OutVars{~t5_pc~0=v_~t5_pc~0_22} AuxVars[] AssignedVars[] 127353#L389-23 [2111] L389-23-->L400-7: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 132778#L400-7 [3837] L400-7-->L785-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 132777#L785-21 [3654] L785-21-->L785-23: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_41 0) (= v_~t5_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} OutVars{~t5_st~0=v_~t5_st~0_19, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} AuxVars[] AssignedVars[~t5_st~0] 132775#L785-23 [2161] L785-23-->L669-3: Formula: (and (= v_~M_E~0_12 1) (= v_~M_E~0_11 2)) InVars {~M_E~0=v_~M_E~0_12} OutVars{~M_E~0=v_~M_E~0_11} AuxVars[] AssignedVars[~M_E~0] 132773#L669-3 [3660] L669-3-->L674-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 132771#L674-3 [3662] L674-3-->L679-3: Formula: (< 1 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 132769#L679-3 [3664] L679-3-->L684-3: Formula: (< 1 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 132767#L684-3 [3666] L684-3-->L689-3: Formula: (> v_~T4_E~0_13 1) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 132765#L689-3 [3668] L689-3-->L694-3: Formula: (< 1 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 132763#L694-3 [2405] L694-3-->L699-3: Formula: (and (= 1 v_~E_M~0_30) (= v_~E_M~0_29 2)) InVars {~E_M~0=v_~E_M~0_30} OutVars{~E_M~0=v_~E_M~0_29} AuxVars[] AssignedVars[~E_M~0] 132761#L699-3 [3673] L699-3-->L704-3: Formula: (< 1 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 132759#L704-3 [3675] L704-3-->L709-3: Formula: (< 1 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 132757#L709-3 [3677] L709-3-->L714-3: Formula: (< 1 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 132755#L714-3 [3678] L714-3-->L719-3: Formula: (< 1 v_~E_4~0_31) InVars {~E_4~0=v_~E_4~0_31} OutVars{~E_4~0=v_~E_4~0_31} AuxVars[] AssignedVars[] 132753#L719-3 [3680] L719-3-->L724-3: Formula: (> 1 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 132751#L724-3 [2818] L724-3-->L454-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_23} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 132744#L454-1 [2466] L454-1-->L486-1: Formula: (and (= 0 v_~m_st~0_20) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26 1)) InVars {~m_st~0=v_~m_st~0_20} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 132742#L486-1 [3838] L486-1-->L949: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret15, ULTIMATE.start_start_simulation_~tmp~3] 132739#L949 [3688] L949-->L949-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_1) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} AuxVars[] AssignedVars[] 132736#L949-1 [2479] L949-1-->L454-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_1} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 132729#L454-2 [2438] L454-2-->L486-2: Formula: (and (= v_~m_st~0_2 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4 1)) InVars {~m_st~0=v_~m_st~0_2} OutVars{~m_st~0=v_~m_st~0_2, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 132724#L486-2 [3840] L486-2-->L904: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 132722#L904 [2393] L904-->L911: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 132720#L911 [3851] L911-->L930-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_6|, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 123856#L930-1 312.69/160.50 [2019-03-28 12:22:16,753 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.50 [2019-03-28 12:22:16,754 INFO L82 PathProgramCache]: Analyzing trace with hash -305139764, now seen corresponding path program 1 times 312.69/160.50 [2019-03-28 12:22:16,754 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.50 [2019-03-28 12:22:16,754 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.50 [2019-03-28 12:22:16,755 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:16,755 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:16,755 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:16,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.50 [2019-03-28 12:22:16,794 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.50 [2019-03-28 12:22:16,795 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.50 [2019-03-28 12:22:16,795 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 312.69/160.50 [2019-03-28 12:22:16,795 INFO L799 eck$LassoCheckResult]: stem already infeasible 312.69/160.50 [2019-03-28 12:22:16,795 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.50 [2019-03-28 12:22:16,795 INFO L82 PathProgramCache]: Analyzing trace with hash 1240163923, now seen corresponding path program 1 times 312.69/160.50 [2019-03-28 12:22:16,796 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.50 [2019-03-28 12:22:16,796 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.50 [2019-03-28 12:22:16,796 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:16,797 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:16,797 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:16,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.50 [2019-03-28 12:22:16,816 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.50 [2019-03-28 12:22:16,816 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.50 [2019-03-28 12:22:16,816 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 312.69/160.50 [2019-03-28 12:22:16,816 INFO L811 eck$LassoCheckResult]: loop already infeasible 312.69/160.50 [2019-03-28 12:22:16,817 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. 312.69/160.50 [2019-03-28 12:22:16,817 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 312.69/160.50 [2019-03-28 12:22:16,817 INFO L87 Difference]: Start difference. First operand 17213 states and 28564 transitions. cyclomatic complexity: 11352 Second operand 6 states. 312.69/160.50 [2019-03-28 12:22:18,735 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.50 [2019-03-28 12:22:18,735 INFO L93 Difference]: Finished difference Result 57389 states and 97099 transitions. 312.69/160.50 [2019-03-28 12:22:18,736 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. 312.69/160.50 [2019-03-28 12:22:18,736 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 57389 states and 97099 transitions. 312.69/160.50 [2019-03-28 12:22:19,009 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 57328 312.69/160.50 [2019-03-28 12:22:19,180 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 57389 states to 57389 states and 97099 transitions. 312.69/160.50 [2019-03-28 12:22:19,180 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 57389 312.69/160.50 [2019-03-28 12:22:19,227 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 57389 312.69/160.50 [2019-03-28 12:22:19,227 INFO L73 IsDeterministic]: Start isDeterministic. Operand 57389 states and 97099 transitions. 312.69/160.50 [2019-03-28 12:22:19,269 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.50 [2019-03-28 12:22:19,269 INFO L706 BuchiCegarLoop]: Abstraction has 57389 states and 97099 transitions. 312.69/160.50 [2019-03-28 12:22:19,298 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57389 states and 97099 transitions. 312.69/160.50 [2019-03-28 12:22:19,758 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57389 to 17565. 312.69/160.50 [2019-03-28 12:22:19,758 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17565 states. 312.69/160.50 [2019-03-28 12:22:19,790 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17565 states to 17565 states and 28947 transitions. 312.69/160.50 [2019-03-28 12:22:19,790 INFO L729 BuchiCegarLoop]: Abstraction has 17565 states and 28947 transitions. 312.69/160.50 [2019-03-28 12:22:19,790 INFO L609 BuchiCegarLoop]: Abstraction has 17565 states and 28947 transitions. 312.69/160.50 [2019-03-28 12:22:19,790 INFO L442 BuchiCegarLoop]: ======== Iteration 32============ 312.69/160.50 [2019-03-28 12:22:19,790 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17565 states and 28947 transitions. 312.69/160.50 [2019-03-28 12:22:19,847 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 17504 312.69/160.50 [2019-03-28 12:22:19,847 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.50 [2019-03-28 12:22:19,847 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.50 [2019-03-28 12:22:19,851 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.50 [2019-03-28 12:22:19,852 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.50 [2019-03-28 12:22:19,853 INFO L794 eck$LassoCheckResult]: Stem: 198810#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 198611#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 198612#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 198674#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 198675#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 198613#L431-1 [2355] L431-1-->L436-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 198614#L436-1 [2735] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 198652#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 198653#L601-1 [3235] L601-1-->L606-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 198656#L606-1 [3236] L606-1-->L611-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 198537#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 198538#L616-1 [3240] L616-1-->L621-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 198407#L621-1 [3242] L621-1-->L626-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 198408#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 198508#L631-1 [3246] L631-1-->L636-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 198509#L636-1 [3248] L636-1-->L641-1: Formula: (> v_~E_2~0_4 0) InVars {~E_2~0=v_~E_2~0_4} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[] 198699#L641-1 [3251] L641-1-->L646-1: Formula: (> v_~E_3~0_4 0) InVars {~E_3~0=v_~E_3~0_4} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[] 198700#L646-1 [3253] L646-1-->L651-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 198644#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 198645#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 198893#L294 [3256] L294-->L294-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 198929#L294-2 [2905] L294-2-->L305: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 198954#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 198955#L745 [2925] L745-->L745-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_6) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} AuxVars[] AssignedVars[] 198973#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 198587#L313 [3262] L313-->L313-2: Formula: (< v_~t1_pc~0_3 1) InVars {~t1_pc~0=v_~t1_pc~0_3} OutVars{~t1_pc~0=v_~t1_pc~0_3} AuxVars[] AssignedVars[] 198588#L313-2 [2314] L313-2-->L324: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 198585#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 198423#L753 [2130] L753-->L753-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} AuxVars[] AssignedVars[] 198424#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 198428#L332 [3268] L332-->L332-2: Formula: (< v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 198621#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 198619#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 198620#L761 [2384] L761-->L761-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} AuxVars[] AssignedVars[] 198640#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 198641#L351 [3274] L351-->L351-2: Formula: (> 1 v_~t3_pc~0_3) InVars {~t3_pc~0=v_~t3_pc~0_3} OutVars{~t3_pc~0=v_~t3_pc~0_3} AuxVars[] AssignedVars[] 198755#L351-2 [2543] L351-2-->L362: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 198756#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 198773#L769 [2585] L769-->L769-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} AuxVars[] AssignedVars[] 198776#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 198777#L370 [3280] L370-->L370-2: Formula: (< v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 198876#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 198872#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 198873#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 198891#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 198497#L389 [3286] L389-->L389-2: Formula: (> 1 v_~t5_pc~0_3) InVars {~t5_pc~0=v_~t5_pc~0_3} OutVars{~t5_pc~0=v_~t5_pc~0_3} AuxVars[] AssignedVars[] 198461#L389-2 [2164] L389-2-->L400: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 198462#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 198493#L785 [3290] L785-->L785-2: Formula: (and (> 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_5) (= v_~t5_st~0_6 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} OutVars{~t5_st~0=v_~t5_st~0_6, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_5} AuxVars[] AssignedVars[~t5_st~0] 198516#L785-2 [3293] L785-2-->L669-1: Formula: (> 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 198519#L669-1 [3294] L669-1-->L674-1: Formula: (< 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 198697#L674-1 [3296] L674-1-->L679-1: Formula: (< 1 v_~T2_E~0_7) InVars {~T2_E~0=v_~T2_E~0_7} OutVars{~T2_E~0=v_~T2_E~0_7} AuxVars[] AssignedVars[] 198698#L679-1 [3299] L679-1-->L684-1: Formula: (< v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 198642#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 198643#L689-1 [3302] L689-1-->L694-1: Formula: (> v_~T5_E~0_7 1) InVars {~T5_E~0=v_~T5_E~0_7} OutVars{~T5_E~0=v_~T5_E~0_7} AuxVars[] AssignedVars[] 198802#L694-1 [3305] L694-1-->L699-1: Formula: (< v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 198561#L699-1 [3306] L699-1-->L704-1: Formula: (> v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 198562#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 198397#L709-1 [3310] L709-1-->L714-1: Formula: (> v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 198398#L714-1 [3313] L714-1-->L719-1: Formula: (> v_~E_4~0_9 1) InVars {~E_4~0=v_~E_4~0_9} OutVars{~E_4~0=v_~E_4~0_9} AuxVars[] AssignedVars[] 198501#L719-1 [2198] L719-1-->L930-1: Formula: (and (= v_~E_5~0_8 1) (= v_~E_5~0_7 2)) InVars {~E_5~0=v_~E_5~0_8} OutVars{~E_5~0=v_~E_5~0_7} AuxVars[] AssignedVars[~E_5~0] 198502#L930-1 312.69/160.50 [2019-03-28 12:22:19,854 INFO L796 eck$LassoCheckResult]: Loop: 198502#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 200027#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 199995#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 199989#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 199986#L501 [3784] L501-->L601-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 199987#L601-2 [2768] L601-2-->L601-4: Formula: (and (= v_~M_E~0_8 1) (= 0 v_~M_E~0_9)) InVars {~M_E~0=v_~M_E~0_9} OutVars{~M_E~0=v_~M_E~0_8} AuxVars[] AssignedVars[~M_E~0] 209632#L601-4 [3322] L601-4-->L606-3: Formula: (> v_~T1_E~0_10 0) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 209631#L606-3 [3326] L606-3-->L611-3: Formula: (< 0 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 209630#L611-3 [2256] L611-3-->L616-3: Formula: (and (= v_~T3_E~0_8 1) (= v_~T3_E~0_9 0)) InVars {~T3_E~0=v_~T3_E~0_9} OutVars{~T3_E~0=v_~T3_E~0_8} AuxVars[] AssignedVars[~T3_E~0] 209629#L616-3 [3339] L616-3-->L621-3: Formula: (> v_~T4_E~0_10 0) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 209628#L621-3 [3346] L621-3-->L626-3: Formula: (< 0 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 209627#L626-3 [2580] L626-3-->L631-3: Formula: (and (= v_~E_M~0_24 1) (= 0 v_~E_M~0_25)) InVars {~E_M~0=v_~E_M~0_25} OutVars{~E_M~0=v_~E_M~0_24} AuxVars[] AssignedVars[~E_M~0] 209626#L631-3 [3365] L631-3-->L636-3: Formula: (< 0 v_~E_1~0_26) InVars {~E_1~0=v_~E_1~0_26} OutVars{~E_1~0=v_~E_1~0_26} AuxVars[] AssignedVars[] 209625#L636-3 [3376] L636-3-->L641-3: Formula: (< 0 v_~E_2~0_26) InVars {~E_2~0=v_~E_2~0_26} OutVars{~E_2~0=v_~E_2~0_26} AuxVars[] AssignedVars[] 209624#L641-3 [3388] L641-3-->L646-3: Formula: (< 0 v_~E_3~0_26) InVars {~E_3~0=v_~E_3~0_26} OutVars{~E_3~0=v_~E_3~0_26} AuxVars[] AssignedVars[] 209623#L646-3 [3401] L646-3-->L651-3: Formula: (< 0 v_~E_4~0_26) InVars {~E_4~0=v_~E_4~0_26} OutVars{~E_4~0=v_~E_4~0_26} AuxVars[] AssignedVars[] 209622#L651-3 [3410] L651-3-->L656-3: Formula: (> 0 v_~E_5~0_26) InVars {~E_5~0=v_~E_5~0_26} OutVars{~E_5~0=v_~E_5~0_26} AuxVars[] AssignedVars[] 209621#L656-3 [2767] L656-3-->L294-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_37, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_37, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_22|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_22|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_22|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_37, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_37, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_22|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_22|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_22|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_22|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_37, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_37, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_37} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 209619#L294-21 [3426] L294-21-->L294-23: Formula: (< v_~m_pc~0_22 1) InVars {~m_pc~0=v_~m_pc~0_22} OutVars{~m_pc~0=v_~m_pc~0_22} AuxVars[] AssignedVars[] 209615#L294-23 [2803] L294-23-->L305-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_41 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_41} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 209614#L305-7 [3806] L305-7-->L745-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 209613#L745-21 [2835] L745-21-->L745-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_42) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} AuxVars[] AssignedVars[] 209612#L745-23 [2838] L745-23-->L313-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_43, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 209611#L313-21 [3469] L313-21-->L313-23: Formula: (< v_~t1_pc~0_22 1) InVars {~t1_pc~0=v_~t1_pc~0_22} OutVars{~t1_pc~0=v_~t1_pc~0_22} AuxVars[] AssignedVars[] 207721#L313-23 [2249] L313-23-->L324-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 209610#L324-7 [3813] L324-7-->L753-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 209609#L753-21 [2292] L753-21-->L753-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} AuxVars[] AssignedVars[] 209608#L753-23 [2297] L753-23-->L332-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_22|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 209607#L332-21 [3510] L332-21-->L332-23: Formula: (> 1 v_~t2_pc~0_22) InVars {~t2_pc~0=v_~t2_pc~0_22} OutVars{~t2_pc~0=v_~t2_pc~0_22} AuxVars[] AssignedVars[] 207555#L332-23 [2476] L332-23-->L343-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 209606#L343-7 [3820] L343-7-->L761-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 209605#L761-21 [2490] L761-21-->L761-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_42} AuxVars[] AssignedVars[] 209604#L761-23 [2493] L761-23-->L351-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_22|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 209603#L351-21 [3552] L351-21-->L351-23: Formula: (< v_~t3_pc~0_22 1) InVars {~t3_pc~0=v_~t3_pc~0_22} OutVars{~t3_pc~0=v_~t3_pc~0_22} AuxVars[] AssignedVars[] 207350#L351-23 [2660] L351-23-->L362-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 209602#L362-7 [3827] L362-7-->L769-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 209601#L769-21 [2534] L769-21-->L769-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} AuxVars[] AssignedVars[] 209600#L769-23 [2537] L769-23-->L370-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_43, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 209599#L370-21 [3595] L370-21-->L370-23: Formula: (> 1 v_~t4_pc~0_22) InVars {~t4_pc~0=v_~t4_pc~0_22} OutVars{~t4_pc~0=v_~t4_pc~0_22} AuxVars[] AssignedVars[] 208251#L370-23 [2934] L370-23-->L381-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 209598#L381-7 [3834] L381-7-->L777-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 209597#L777-21 [2705] L777-21-->L777-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} AuxVars[] AssignedVars[] 209596#L777-23 [2708] L777-23-->L389-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_22|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 200123#L389-21 [3637] L389-21-->L389-23: Formula: (< v_~t5_pc~0_22 1) InVars {~t5_pc~0=v_~t5_pc~0_22} OutVars{~t5_pc~0=v_~t5_pc~0_22} AuxVars[] AssignedVars[] 200120#L389-23 [2111] L389-23-->L400-7: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 200118#L400-7 [3837] L400-7-->L785-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 200117#L785-21 [3655] L785-21-->L785-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___4~0_41 0) (= v_~t5_st~0_19 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} OutVars{~t5_st~0=v_~t5_st~0_19, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_41} AuxVars[] AssignedVars[~t5_st~0] 200116#L785-23 [2161] L785-23-->L669-3: Formula: (and (= v_~M_E~0_12 1) (= v_~M_E~0_11 2)) InVars {~M_E~0=v_~M_E~0_12} OutVars{~M_E~0=v_~M_E~0_11} AuxVars[] AssignedVars[~M_E~0] 200114#L669-3 [3660] L669-3-->L674-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 200112#L674-3 [3662] L674-3-->L679-3: Formula: (< 1 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 200110#L679-3 [3664] L679-3-->L684-3: Formula: (< 1 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 200108#L684-3 [3666] L684-3-->L689-3: Formula: (> v_~T4_E~0_13 1) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 200106#L689-3 [3668] L689-3-->L694-3: Formula: (< 1 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 200104#L694-3 [2405] L694-3-->L699-3: Formula: (and (= 1 v_~E_M~0_30) (= v_~E_M~0_29 2)) InVars {~E_M~0=v_~E_M~0_30} OutVars{~E_M~0=v_~E_M~0_29} AuxVars[] AssignedVars[~E_M~0] 200102#L699-3 [3673] L699-3-->L704-3: Formula: (< 1 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 200100#L704-3 [3675] L704-3-->L709-3: Formula: (< 1 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 200098#L709-3 [3677] L709-3-->L714-3: Formula: (< 1 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 200096#L714-3 [3678] L714-3-->L719-3: Formula: (< 1 v_~E_4~0_31) InVars {~E_4~0=v_~E_4~0_31} OutVars{~E_4~0=v_~E_4~0_31} AuxVars[] AssignedVars[] 200094#L719-3 [3680] L719-3-->L724-3: Formula: (> 1 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 200092#L724-3 [2818] L724-3-->L454-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_23} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 200066#L454-1 [2466] L454-1-->L486-1: Formula: (and (= 0 v_~m_st~0_20) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26 1)) InVars {~m_st~0=v_~m_st~0_20} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 200057#L486-1 [3838] L486-1-->L949: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret15, ULTIMATE.start_start_simulation_~tmp~3] 200050#L949 [3688] L949-->L949-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_1) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} AuxVars[] AssignedVars[] 200047#L949-1 [2479] L949-1-->L454-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_1} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 200042#L454-2 [2438] L454-2-->L486-2: Formula: (and (= v_~m_st~0_2 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4 1)) InVars {~m_st~0=v_~m_st~0_2} OutVars{~m_st~0=v_~m_st~0_2, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 200038#L486-2 [3840] L486-2-->L904: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 200037#L904 [2393] L904-->L911: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 200033#L911 [3851] L911-->L930-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_6|, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 198502#L930-1 312.69/160.50 [2019-03-28 12:22:19,854 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.50 [2019-03-28 12:22:19,854 INFO L82 PathProgramCache]: Analyzing trace with hash -11736757, now seen corresponding path program 1 times 312.69/160.50 [2019-03-28 12:22:19,854 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.50 [2019-03-28 12:22:19,854 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.50 [2019-03-28 12:22:19,855 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:19,855 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:19,856 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:19,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.50 [2019-03-28 12:22:19,900 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.50 [2019-03-28 12:22:19,901 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.50 [2019-03-28 12:22:19,901 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 312.69/160.50 [2019-03-28 12:22:19,901 INFO L799 eck$LassoCheckResult]: stem already infeasible 312.69/160.50 [2019-03-28 12:22:19,901 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.50 [2019-03-28 12:22:19,902 INFO L82 PathProgramCache]: Analyzing trace with hash -797892366, now seen corresponding path program 1 times 312.69/160.50 [2019-03-28 12:22:19,902 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.50 [2019-03-28 12:22:19,902 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.50 [2019-03-28 12:22:19,903 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:19,903 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:19,903 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:19,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.50 [2019-03-28 12:22:19,923 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.50 [2019-03-28 12:22:19,923 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.50 [2019-03-28 12:22:19,923 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 312.69/160.50 [2019-03-28 12:22:19,924 INFO L811 eck$LassoCheckResult]: loop already infeasible 312.69/160.50 [2019-03-28 12:22:19,924 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. 312.69/160.50 [2019-03-28 12:22:19,924 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 312.69/160.50 [2019-03-28 12:22:19,924 INFO L87 Difference]: Start difference. First operand 17565 states and 28947 transitions. cyclomatic complexity: 11383 Second operand 6 states. 312.69/160.50 [2019-03-28 12:22:20,589 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.50 [2019-03-28 12:22:20,589 INFO L93 Difference]: Finished difference Result 17565 states and 28450 transitions. 312.69/160.50 [2019-03-28 12:22:20,589 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. 312.69/160.50 [2019-03-28 12:22:20,590 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17565 states and 28450 transitions. 312.69/160.50 [2019-03-28 12:22:20,661 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 17504 312.69/160.50 [2019-03-28 12:22:20,703 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17565 states to 17565 states and 28450 transitions. 312.69/160.50 [2019-03-28 12:22:20,704 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17565 312.69/160.50 [2019-03-28 12:22:20,716 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17565 312.69/160.50 [2019-03-28 12:22:20,716 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17565 states and 28450 transitions. 312.69/160.50 [2019-03-28 12:22:20,728 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.50 [2019-03-28 12:22:20,728 INFO L706 BuchiCegarLoop]: Abstraction has 17565 states and 28450 transitions. 312.69/160.50 [2019-03-28 12:22:20,736 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17565 states and 28450 transitions. 312.69/160.50 [2019-03-28 12:22:20,867 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17565 to 17565. 312.69/160.50 [2019-03-28 12:22:20,867 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17565 states. 312.69/160.50 [2019-03-28 12:22:20,898 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17565 states to 17565 states and 28450 transitions. 312.69/160.50 [2019-03-28 12:22:20,899 INFO L729 BuchiCegarLoop]: Abstraction has 17565 states and 28450 transitions. 312.69/160.50 [2019-03-28 12:22:20,899 INFO L609 BuchiCegarLoop]: Abstraction has 17565 states and 28450 transitions. 312.69/160.50 [2019-03-28 12:22:20,899 INFO L442 BuchiCegarLoop]: ======== Iteration 33============ 312.69/160.50 [2019-03-28 12:22:20,899 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17565 states and 28450 transitions. 312.69/160.50 [2019-03-28 12:22:20,955 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 17504 312.69/160.50 [2019-03-28 12:22:20,955 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.50 [2019-03-28 12:22:20,955 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.50 [2019-03-28 12:22:20,960 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.50 [2019-03-28 12:22:20,960 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.50 [2019-03-28 12:22:20,961 INFO L794 eck$LassoCheckResult]: Stem: 233969#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 233761#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 233762#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 233830#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 233831#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 233763#L431-1 [2355] L431-1-->L436-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 233764#L436-1 [2735] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 233805#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 233806#L601-1 [3235] L601-1-->L606-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 233808#L606-1 [3236] L606-1-->L611-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 233674#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 233675#L616-1 [3240] L616-1-->L621-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 233557#L621-1 [3242] L621-1-->L626-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 233558#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 233646#L631-1 [3246] L631-1-->L636-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 233647#L636-1 [3248] L636-1-->L641-1: Formula: (> v_~E_2~0_4 0) InVars {~E_2~0=v_~E_2~0_4} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[] 233855#L641-1 [3251] L641-1-->L646-1: Formula: (> v_~E_3~0_4 0) InVars {~E_3~0=v_~E_3~0_4} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[] 233856#L646-1 [3253] L646-1-->L651-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 233795#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 233796#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 234063#L294 [3256] L294-->L294-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 234111#L294-2 [2905] L294-2-->L305: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 234127#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 234128#L745 [2925] L745-->L745-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_6) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} AuxVars[] AssignedVars[] 234146#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 233731#L313 [3262] L313-->L313-2: Formula: (< v_~t1_pc~0_3 1) InVars {~t1_pc~0=v_~t1_pc~0_3} OutVars{~t1_pc~0=v_~t1_pc~0_3} AuxVars[] AssignedVars[] 233732#L313-2 [2314] L313-2-->L324: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 233730#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 233574#L753 [2130] L753-->L753-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} AuxVars[] AssignedVars[] 233575#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 233578#L332 [3268] L332-->L332-2: Formula: (< v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 233771#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 233769#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 233770#L761 [2384] L761-->L761-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} AuxVars[] AssignedVars[] 233791#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 233792#L351 [3274] L351-->L351-2: Formula: (> 1 v_~t3_pc~0_3) InVars {~t3_pc~0=v_~t3_pc~0_3} OutVars{~t3_pc~0=v_~t3_pc~0_3} AuxVars[] AssignedVars[] 233912#L351-2 [2543] L351-2-->L362: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 233913#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 233929#L769 [2585] L769-->L769-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} AuxVars[] AssignedVars[] 233936#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 233937#L370 [3280] L370-->L370-2: Formula: (< v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 234043#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 234040#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 234041#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 234062#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 233636#L389 [3286] L389-->L389-2: Formula: (> 1 v_~t5_pc~0_3) InVars {~t5_pc~0=v_~t5_pc~0_3} OutVars{~t5_pc~0=v_~t5_pc~0_3} AuxVars[] AssignedVars[] 233606#L389-2 [2164] L389-2-->L400: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 233607#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 233634#L785 [2215] L785-->L785-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_6} AuxVars[] AssignedVars[] 233654#L785-2 [3293] L785-2-->L669-1: Formula: (> 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 233655#L669-1 [3294] L669-1-->L674-1: Formula: (< 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 233853#L674-1 [3296] L674-1-->L679-1: Formula: (< 1 v_~T2_E~0_7) InVars {~T2_E~0=v_~T2_E~0_7} OutVars{~T2_E~0=v_~T2_E~0_7} AuxVars[] AssignedVars[] 233854#L679-1 [3299] L679-1-->L684-1: Formula: (< v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 233793#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 233794#L689-1 [3302] L689-1-->L694-1: Formula: (> v_~T5_E~0_7 1) InVars {~T5_E~0=v_~T5_E~0_7} OutVars{~T5_E~0=v_~T5_E~0_7} AuxVars[] AssignedVars[] 233962#L694-1 [3305] L694-1-->L699-1: Formula: (< v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 233699#L699-1 [3306] L699-1-->L704-1: Formula: (> v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 233700#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 233547#L709-1 [3310] L709-1-->L714-1: Formula: (> v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 233548#L714-1 [3313] L714-1-->L719-1: Formula: (> v_~E_4~0_9 1) InVars {~E_4~0=v_~E_4~0_9} OutVars{~E_4~0=v_~E_4~0_9} AuxVars[] AssignedVars[] 233639#L719-1 [2198] L719-1-->L930-1: Formula: (and (= v_~E_5~0_8 1) (= v_~E_5~0_7 2)) InVars {~E_5~0=v_~E_5~0_8} OutVars{~E_5~0=v_~E_5~0_7} AuxVars[] AssignedVars[~E_5~0] 233640#L930-1 312.69/160.50 [2019-03-28 12:22:20,962 INFO L796 eck$LassoCheckResult]: Loop: 233640#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 239348#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 239347#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 239341#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 239339#L501 [3784] L501-->L601-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 239340#L601-2 [2768] L601-2-->L601-4: Formula: (and (= v_~M_E~0_8 1) (= 0 v_~M_E~0_9)) InVars {~M_E~0=v_~M_E~0_9} OutVars{~M_E~0=v_~M_E~0_8} AuxVars[] AssignedVars[~M_E~0] 234061#L601-4 [3322] L601-4-->L606-3: Formula: (> v_~T1_E~0_10 0) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 233812#L606-3 [3326] L606-3-->L611-3: Formula: (< 0 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 233813#L611-3 [2256] L611-3-->L616-3: Formula: (and (= v_~T3_E~0_8 1) (= v_~T3_E~0_9 0)) InVars {~T3_E~0=v_~T3_E~0_9} OutVars{~T3_E~0=v_~T3_E~0_8} AuxVars[] AssignedVars[~T3_E~0] 250907#L616-3 [3339] L616-3-->L621-3: Formula: (> v_~T4_E~0_10 0) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 250721#L621-3 [3346] L621-3-->L626-3: Formula: (< 0 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 250720#L626-3 [2580] L626-3-->L631-3: Formula: (and (= v_~E_M~0_24 1) (= 0 v_~E_M~0_25)) InVars {~E_M~0=v_~E_M~0_25} OutVars{~E_M~0=v_~E_M~0_24} AuxVars[] AssignedVars[~E_M~0] 250719#L631-3 [3365] L631-3-->L636-3: Formula: (< 0 v_~E_1~0_26) InVars {~E_1~0=v_~E_1~0_26} OutVars{~E_1~0=v_~E_1~0_26} AuxVars[] AssignedVars[] 250718#L636-3 [3376] L636-3-->L641-3: Formula: (< 0 v_~E_2~0_26) InVars {~E_2~0=v_~E_2~0_26} OutVars{~E_2~0=v_~E_2~0_26} AuxVars[] AssignedVars[] 250716#L641-3 [3388] L641-3-->L646-3: Formula: (< 0 v_~E_3~0_26) InVars {~E_3~0=v_~E_3~0_26} OutVars{~E_3~0=v_~E_3~0_26} AuxVars[] AssignedVars[] 250717#L646-3 [3401] L646-3-->L651-3: Formula: (< 0 v_~E_4~0_26) InVars {~E_4~0=v_~E_4~0_26} OutVars{~E_4~0=v_~E_4~0_26} AuxVars[] AssignedVars[] 251104#L651-3 [3410] L651-3-->L656-3: Formula: (> 0 v_~E_5~0_26) InVars {~E_5~0=v_~E_5~0_26} OutVars{~E_5~0=v_~E_5~0_26} AuxVars[] AssignedVars[] 251103#L656-3 [2767] L656-3-->L294-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_37, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_37, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_22|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_22|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_22|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_37, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_37, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_22|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_22|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_22|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_22|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_37, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_37, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_37} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 250707#L294-21 [3426] L294-21-->L294-23: Formula: (< v_~m_pc~0_22 1) InVars {~m_pc~0=v_~m_pc~0_22} OutVars{~m_pc~0=v_~m_pc~0_22} AuxVars[] AssignedVars[] 250705#L294-23 [2803] L294-23-->L305-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_41 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_41} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 250704#L305-7 [3806] L305-7-->L745-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 250702#L745-21 [2835] L745-21-->L745-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_42) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} AuxVars[] AssignedVars[] 250700#L745-23 [2838] L745-23-->L313-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_43, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 250698#L313-21 [3469] L313-21-->L313-23: Formula: (< v_~t1_pc~0_22 1) InVars {~t1_pc~0=v_~t1_pc~0_22} OutVars{~t1_pc~0=v_~t1_pc~0_22} AuxVars[] AssignedVars[] 249268#L313-23 [2249] L313-23-->L324-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 250697#L324-7 [3813] L324-7-->L753-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 250696#L753-21 [2292] L753-21-->L753-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} AuxVars[] AssignedVars[] 250695#L753-23 [2297] L753-23-->L332-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_22|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 250694#L332-21 [3510] L332-21-->L332-23: Formula: (> 1 v_~t2_pc~0_22) InVars {~t2_pc~0=v_~t2_pc~0_22} OutVars{~t2_pc~0=v_~t2_pc~0_22} AuxVars[] AssignedVars[] 248255#L332-23 [2476] L332-23-->L343-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 250692#L343-7 [3820] L343-7-->L761-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 250690#L761-21 [2490] L761-21-->L761-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_42} AuxVars[] AssignedVars[] 249494#L761-23 [2493] L761-23-->L351-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_22|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 248192#L351-21 [3552] L351-21-->L351-23: Formula: (< v_~t3_pc~0_22 1) InVars {~t3_pc~0=v_~t3_pc~0_22} OutVars{~t3_pc~0=v_~t3_pc~0_22} AuxVars[] AssignedVars[] 248191#L351-23 [2660] L351-23-->L362-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 248189#L362-7 [3827] L362-7-->L769-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 248187#L769-21 [2534] L769-21-->L769-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} AuxVars[] AssignedVars[] 248185#L769-23 [2537] L769-23-->L370-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_43, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 248184#L370-21 [3595] L370-21-->L370-23: Formula: (> 1 v_~t4_pc~0_22) InVars {~t4_pc~0=v_~t4_pc~0_22} OutVars{~t4_pc~0=v_~t4_pc~0_22} AuxVars[] AssignedVars[] 248121#L370-23 [2934] L370-23-->L381-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 248180#L381-7 [3834] L381-7-->L777-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 248178#L777-21 [2705] L777-21-->L777-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} AuxVars[] AssignedVars[] 248176#L777-23 [2708] L777-23-->L389-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_22|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 239402#L389-21 [3637] L389-21-->L389-23: Formula: (< v_~t5_pc~0_22 1) InVars {~t5_pc~0=v_~t5_pc~0_22} OutVars{~t5_pc~0=v_~t5_pc~0_22} AuxVars[] AssignedVars[] 239401#L389-23 [2111] L389-23-->L400-7: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 239400#L400-7 [3837] L400-7-->L785-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 239399#L785-21 [2159] L785-21-->L785-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_42} AuxVars[] AssignedVars[] 239398#L785-23 [2161] L785-23-->L669-3: Formula: (and (= v_~M_E~0_12 1) (= v_~M_E~0_11 2)) InVars {~M_E~0=v_~M_E~0_12} OutVars{~M_E~0=v_~M_E~0_11} AuxVars[] AssignedVars[~M_E~0] 239397#L669-3 [3660] L669-3-->L674-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 239396#L674-3 [3662] L674-3-->L679-3: Formula: (< 1 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 239395#L679-3 [3664] L679-3-->L684-3: Formula: (< 1 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 239394#L684-3 [3666] L684-3-->L689-3: Formula: (> v_~T4_E~0_13 1) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 239392#L689-3 [3668] L689-3-->L694-3: Formula: (< 1 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 239390#L694-3 [2405] L694-3-->L699-3: Formula: (and (= 1 v_~E_M~0_30) (= v_~E_M~0_29 2)) InVars {~E_M~0=v_~E_M~0_30} OutVars{~E_M~0=v_~E_M~0_29} AuxVars[] AssignedVars[~E_M~0] 239388#L699-3 [3673] L699-3-->L704-3: Formula: (< 1 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 239386#L704-3 [3675] L704-3-->L709-3: Formula: (< 1 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 239384#L709-3 [3677] L709-3-->L714-3: Formula: (< 1 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 239382#L714-3 [3678] L714-3-->L719-3: Formula: (< 1 v_~E_4~0_31) InVars {~E_4~0=v_~E_4~0_31} OutVars{~E_4~0=v_~E_4~0_31} AuxVars[] AssignedVars[] 239380#L719-3 [3680] L719-3-->L724-3: Formula: (> 1 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 239378#L724-3 [2818] L724-3-->L454-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_23} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 239366#L454-1 [2466] L454-1-->L486-1: Formula: (and (= 0 v_~m_st~0_20) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26 1)) InVars {~m_st~0=v_~m_st~0_20} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 239364#L486-1 [3838] L486-1-->L949: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret15, ULTIMATE.start_start_simulation_~tmp~3] 239362#L949 [3688] L949-->L949-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_1) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} AuxVars[] AssignedVars[] 239360#L949-1 [2479] L949-1-->L454-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_1} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 239357#L454-2 [2438] L454-2-->L486-2: Formula: (and (= v_~m_st~0_2 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4 1)) InVars {~m_st~0=v_~m_st~0_2} OutVars{~m_st~0=v_~m_st~0_2, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 239353#L486-2 [3840] L486-2-->L904: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 239352#L904 [2393] L904-->L911: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 239351#L911 [3851] L911-->L930-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_6|, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 233640#L930-1 312.69/160.50 [2019-03-28 12:22:20,962 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.50 [2019-03-28 12:22:20,962 INFO L82 PathProgramCache]: Analyzing trace with hash 1863883160, now seen corresponding path program 1 times 312.69/160.50 [2019-03-28 12:22:20,962 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.50 [2019-03-28 12:22:20,962 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.50 [2019-03-28 12:22:20,963 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:20,964 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:20,964 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:20,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.50 [2019-03-28 12:22:20,994 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.50 [2019-03-28 12:22:20,994 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.50 [2019-03-28 12:22:20,994 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 312.69/160.50 [2019-03-28 12:22:20,994 INFO L799 eck$LassoCheckResult]: stem already infeasible 312.69/160.50 [2019-03-28 12:22:20,995 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.50 [2019-03-28 12:22:20,995 INFO L82 PathProgramCache]: Analyzing trace with hash -1292464182, now seen corresponding path program 1 times 312.69/160.50 [2019-03-28 12:22:20,995 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.50 [2019-03-28 12:22:20,995 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.50 [2019-03-28 12:22:20,996 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:20,996 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:20,996 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:20,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.50 [2019-03-28 12:22:21,021 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.50 [2019-03-28 12:22:21,021 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.50 [2019-03-28 12:22:21,022 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 312.69/160.50 [2019-03-28 12:22:21,022 INFO L811 eck$LassoCheckResult]: loop already infeasible 312.69/160.50 [2019-03-28 12:22:21,022 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. 312.69/160.50 [2019-03-28 12:22:21,022 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 312.69/160.50 [2019-03-28 12:22:21,023 INFO L87 Difference]: Start difference. First operand 17565 states and 28450 transitions. cyclomatic complexity: 10886 Second operand 4 states. 312.69/160.50 [2019-03-28 12:22:21,411 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.50 [2019-03-28 12:22:21,412 INFO L93 Difference]: Finished difference Result 17565 states and 28126 transitions. 312.69/160.50 [2019-03-28 12:22:21,412 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. 312.69/160.50 [2019-03-28 12:22:21,412 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17565 states and 28126 transitions. 312.69/160.50 [2019-03-28 12:22:21,484 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 17504 312.69/160.50 [2019-03-28 12:22:21,528 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17565 states to 17565 states and 28126 transitions. 312.69/160.50 [2019-03-28 12:22:21,528 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17565 312.69/160.50 [2019-03-28 12:22:21,540 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17565 312.69/160.50 [2019-03-28 12:22:21,540 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17565 states and 28126 transitions. 312.69/160.50 [2019-03-28 12:22:21,552 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.50 [2019-03-28 12:22:21,552 INFO L706 BuchiCegarLoop]: Abstraction has 17565 states and 28126 transitions. 312.69/160.50 [2019-03-28 12:22:21,560 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17565 states and 28126 transitions. 312.69/160.50 [2019-03-28 12:22:21,683 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17565 to 17565. 312.69/160.50 [2019-03-28 12:22:21,683 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17565 states. 312.69/160.50 [2019-03-28 12:22:21,715 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17565 states to 17565 states and 28126 transitions. 312.69/160.50 [2019-03-28 12:22:21,715 INFO L729 BuchiCegarLoop]: Abstraction has 17565 states and 28126 transitions. 312.69/160.50 [2019-03-28 12:22:21,715 INFO L609 BuchiCegarLoop]: Abstraction has 17565 states and 28126 transitions. 312.69/160.50 [2019-03-28 12:22:21,716 INFO L442 BuchiCegarLoop]: ======== Iteration 34============ 312.69/160.50 [2019-03-28 12:22:21,716 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17565 states and 28126 transitions. 312.69/160.50 [2019-03-28 12:22:21,774 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 17504 312.69/160.50 [2019-03-28 12:22:21,774 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.50 [2019-03-28 12:22:21,774 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.50 [2019-03-28 12:22:21,778 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.50 [2019-03-28 12:22:21,779 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.50 [2019-03-28 12:22:21,780 INFO L794 eck$LassoCheckResult]: Stem: 269092#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 268889#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 268890#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 268954#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 268955#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 268893#L431-1 [2355] L431-1-->L436-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 268894#L436-1 [2735] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 268930#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 268931#L601-1 [3235] L601-1-->L606-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 268933#L606-1 [3236] L606-1-->L611-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 268807#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 268808#L616-1 [3240] L616-1-->L621-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 268696#L621-1 [3242] L621-1-->L626-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 268697#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 268778#L631-1 [3246] L631-1-->L636-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 268779#L636-1 [3248] L636-1-->L641-1: Formula: (> v_~E_2~0_4 0) InVars {~E_2~0=v_~E_2~0_4} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[] 268978#L641-1 [3251] L641-1-->L646-1: Formula: (> v_~E_3~0_4 0) InVars {~E_3~0=v_~E_3~0_4} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[] 268979#L646-1 [3253] L646-1-->L651-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 268921#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 268922#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 269179#L294 [3256] L294-->L294-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 269218#L294-2 [2905] L294-2-->L305: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 269235#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 269236#L745 [2925] L745-->L745-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_6) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} AuxVars[] AssignedVars[] 269249#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 268857#L313 [3262] L313-->L313-2: Formula: (< v_~t1_pc~0_3 1) InVars {~t1_pc~0=v_~t1_pc~0_3} OutVars{~t1_pc~0=v_~t1_pc~0_3} AuxVars[] AssignedVars[] 268858#L313-2 [2314] L313-2-->L324: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 268856#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 268712#L753 [2130] L753-->L753-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} AuxVars[] AssignedVars[] 268713#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 268715#L332 [3268] L332-->L332-2: Formula: (< v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 268899#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 268897#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 268898#L761 [2384] L761-->L761-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} AuxVars[] AssignedVars[] 268917#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 268918#L351 [3274] L351-->L351-2: Formula: (> 1 v_~t3_pc~0_3) InVars {~t3_pc~0=v_~t3_pc~0_3} OutVars{~t3_pc~0=v_~t3_pc~0_3} AuxVars[] AssignedVars[] 269034#L351-2 [2543] L351-2-->L362: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 269035#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 269054#L769 [2585] L769-->L769-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} AuxVars[] AssignedVars[] 269058#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 269059#L370 [3280] L370-->L370-2: Formula: (< v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 269162#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 269159#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 269160#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 269178#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 268770#L389 [3286] L389-->L389-2: Formula: (> 1 v_~t5_pc~0_3) InVars {~t5_pc~0=v_~t5_pc~0_3} OutVars{~t5_pc~0=v_~t5_pc~0_3} AuxVars[] AssignedVars[] 268742#L389-2 [2164] L389-2-->L400: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 268743#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 268769#L785 [2215] L785-->L785-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_6} AuxVars[] AssignedVars[] 268786#L785-2 [3292] L785-2-->L669-1: Formula: (< 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 268787#L669-1 [3294] L669-1-->L674-1: Formula: (< 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 268976#L674-1 [3296] L674-1-->L679-1: Formula: (< 1 v_~T2_E~0_7) InVars {~T2_E~0=v_~T2_E~0_7} OutVars{~T2_E~0=v_~T2_E~0_7} AuxVars[] AssignedVars[] 268977#L679-1 [3299] L679-1-->L684-1: Formula: (< v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 268919#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 268920#L689-1 [3302] L689-1-->L694-1: Formula: (> v_~T5_E~0_7 1) InVars {~T5_E~0=v_~T5_E~0_7} OutVars{~T5_E~0=v_~T5_E~0_7} AuxVars[] AssignedVars[] 269084#L694-1 [3305] L694-1-->L699-1: Formula: (< v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 268827#L699-1 [3306] L699-1-->L704-1: Formula: (> v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 268828#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 268686#L709-1 [3310] L709-1-->L714-1: Formula: (> v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 268687#L714-1 [3313] L714-1-->L719-1: Formula: (> v_~E_4~0_9 1) InVars {~E_4~0=v_~E_4~0_9} OutVars{~E_4~0=v_~E_4~0_9} AuxVars[] AssignedVars[] 268772#L719-1 [2198] L719-1-->L930-1: Formula: (and (= v_~E_5~0_8 1) (= v_~E_5~0_7 2)) InVars {~E_5~0=v_~E_5~0_8} OutVars{~E_5~0=v_~E_5~0_7} AuxVars[] AssignedVars[~E_5~0] 268773#L930-1 312.69/160.50 [2019-03-28 12:22:21,781 INFO L796 eck$LassoCheckResult]: Loop: 268773#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 273417#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 273415#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 273407#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 273405#L501 [3784] L501-->L601-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 273406#L601-2 [3318] L601-2-->L601-4: Formula: (> v_~M_E~0_10 0) InVars {~M_E~0=v_~M_E~0_10} OutVars{~M_E~0=v_~M_E~0_10} AuxVars[] AssignedVars[] 285802#L601-4 [3322] L601-4-->L606-3: Formula: (> v_~T1_E~0_10 0) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 285800#L606-3 [3326] L606-3-->L611-3: Formula: (< 0 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 285798#L611-3 [2256] L611-3-->L616-3: Formula: (and (= v_~T3_E~0_8 1) (= v_~T3_E~0_9 0)) InVars {~T3_E~0=v_~T3_E~0_9} OutVars{~T3_E~0=v_~T3_E~0_8} AuxVars[] AssignedVars[~T3_E~0] 285796#L616-3 [3339] L616-3-->L621-3: Formula: (> v_~T4_E~0_10 0) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 285794#L621-3 [3346] L621-3-->L626-3: Formula: (< 0 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 285792#L626-3 [2580] L626-3-->L631-3: Formula: (and (= v_~E_M~0_24 1) (= 0 v_~E_M~0_25)) InVars {~E_M~0=v_~E_M~0_25} OutVars{~E_M~0=v_~E_M~0_24} AuxVars[] AssignedVars[~E_M~0] 285790#L631-3 [3365] L631-3-->L636-3: Formula: (< 0 v_~E_1~0_26) InVars {~E_1~0=v_~E_1~0_26} OutVars{~E_1~0=v_~E_1~0_26} AuxVars[] AssignedVars[] 285788#L636-3 [3376] L636-3-->L641-3: Formula: (< 0 v_~E_2~0_26) InVars {~E_2~0=v_~E_2~0_26} OutVars{~E_2~0=v_~E_2~0_26} AuxVars[] AssignedVars[] 285786#L641-3 [3388] L641-3-->L646-3: Formula: (< 0 v_~E_3~0_26) InVars {~E_3~0=v_~E_3~0_26} OutVars{~E_3~0=v_~E_3~0_26} AuxVars[] AssignedVars[] 285784#L646-3 [3401] L646-3-->L651-3: Formula: (< 0 v_~E_4~0_26) InVars {~E_4~0=v_~E_4~0_26} OutVars{~E_4~0=v_~E_4~0_26} AuxVars[] AssignedVars[] 285783#L651-3 [3410] L651-3-->L656-3: Formula: (> 0 v_~E_5~0_26) InVars {~E_5~0=v_~E_5~0_26} OutVars{~E_5~0=v_~E_5~0_26} AuxVars[] AssignedVars[] 285781#L656-3 [2767] L656-3-->L294-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_37, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_37, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_22|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_22|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_22|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_37, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_37, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_22|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_22|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_22|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_22|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_37, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_37, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_37} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 284202#L294-21 [3426] L294-21-->L294-23: Formula: (< v_~m_pc~0_22 1) InVars {~m_pc~0=v_~m_pc~0_22} OutVars{~m_pc~0=v_~m_pc~0_22} AuxVars[] AssignedVars[] 284200#L294-23 [2803] L294-23-->L305-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_41 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_41} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 284198#L305-7 [3806] L305-7-->L745-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 284196#L745-21 [2835] L745-21-->L745-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_42) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} AuxVars[] AssignedVars[] 284161#L745-23 [2838] L745-23-->L313-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_43, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 283976#L313-21 [3469] L313-21-->L313-23: Formula: (< v_~t1_pc~0_22 1) InVars {~t1_pc~0=v_~t1_pc~0_22} OutVars{~t1_pc~0=v_~t1_pc~0_22} AuxVars[] AssignedVars[] 283974#L313-23 [2249] L313-23-->L324-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 283971#L324-7 [3813] L324-7-->L753-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 283969#L753-21 [2292] L753-21-->L753-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} AuxVars[] AssignedVars[] 283967#L753-23 [2297] L753-23-->L332-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_22|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 283965#L332-21 [3510] L332-21-->L332-23: Formula: (> 1 v_~t2_pc~0_22) InVars {~t2_pc~0=v_~t2_pc~0_22} OutVars{~t2_pc~0=v_~t2_pc~0_22} AuxVars[] AssignedVars[] 283136#L332-23 [2476] L332-23-->L343-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 283963#L343-7 [3820] L343-7-->L761-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 283960#L761-21 [2490] L761-21-->L761-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_42} AuxVars[] AssignedVars[] 283958#L761-23 [2493] L761-23-->L351-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_22|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 282199#L351-21 [3552] L351-21-->L351-23: Formula: (< v_~t3_pc~0_22 1) InVars {~t3_pc~0=v_~t3_pc~0_22} OutVars{~t3_pc~0=v_~t3_pc~0_22} AuxVars[] AssignedVars[] 282197#L351-23 [2660] L351-23-->L362-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 282195#L362-7 [3827] L362-7-->L769-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 282193#L769-21 [2534] L769-21-->L769-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} AuxVars[] AssignedVars[] 282192#L769-23 [2537] L769-23-->L370-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_43, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 273508#L370-21 [3595] L370-21-->L370-23: Formula: (> 1 v_~t4_pc~0_22) InVars {~t4_pc~0=v_~t4_pc~0_22} OutVars{~t4_pc~0=v_~t4_pc~0_22} AuxVars[] AssignedVars[] 273504#L370-23 [2934] L370-23-->L381-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 273503#L381-7 [3834] L381-7-->L777-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 273498#L777-21 [2705] L777-21-->L777-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} AuxVars[] AssignedVars[] 273496#L777-23 [2708] L777-23-->L389-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_22|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 273489#L389-21 [3637] L389-21-->L389-23: Formula: (< v_~t5_pc~0_22 1) InVars {~t5_pc~0=v_~t5_pc~0_22} OutVars{~t5_pc~0=v_~t5_pc~0_22} AuxVars[] AssignedVars[] 272800#L389-23 [2111] L389-23-->L400-7: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 273485#L400-7 [3837] L400-7-->L785-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 273484#L785-21 [2159] L785-21-->L785-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_42} AuxVars[] AssignedVars[] 273482#L785-23 [3658] L785-23-->L669-3: Formula: (> v_~M_E~0_13 1) InVars {~M_E~0=v_~M_E~0_13} OutVars{~M_E~0=v_~M_E~0_13} AuxVars[] AssignedVars[] 273480#L669-3 [3660] L669-3-->L674-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 273478#L674-3 [3662] L674-3-->L679-3: Formula: (< 1 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 273476#L679-3 [3664] L679-3-->L684-3: Formula: (< 1 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 273474#L684-3 [3666] L684-3-->L689-3: Formula: (> v_~T4_E~0_13 1) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 273472#L689-3 [3668] L689-3-->L694-3: Formula: (< 1 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 273471#L694-3 [2405] L694-3-->L699-3: Formula: (and (= 1 v_~E_M~0_30) (= v_~E_M~0_29 2)) InVars {~E_M~0=v_~E_M~0_30} OutVars{~E_M~0=v_~E_M~0_29} AuxVars[] AssignedVars[~E_M~0] 273469#L699-3 [3673] L699-3-->L704-3: Formula: (< 1 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 273467#L704-3 [3675] L704-3-->L709-3: Formula: (< 1 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 273465#L709-3 [3677] L709-3-->L714-3: Formula: (< 1 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 273463#L714-3 [3678] L714-3-->L719-3: Formula: (< 1 v_~E_4~0_31) InVars {~E_4~0=v_~E_4~0_31} OutVars{~E_4~0=v_~E_4~0_31} AuxVars[] AssignedVars[] 273461#L719-3 [3680] L719-3-->L724-3: Formula: (> 1 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 273459#L724-3 [2818] L724-3-->L454-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_23} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 273447#L454-1 [2466] L454-1-->L486-1: Formula: (and (= 0 v_~m_st~0_20) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26 1)) InVars {~m_st~0=v_~m_st~0_20} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 273445#L486-1 [3838] L486-1-->L949: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret15, ULTIMATE.start_start_simulation_~tmp~3] 273443#L949 [3688] L949-->L949-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_1) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} AuxVars[] AssignedVars[] 273441#L949-1 [2479] L949-1-->L454-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_1} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 273436#L454-2 [2438] L454-2-->L486-2: Formula: (and (= v_~m_st~0_2 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4 1)) InVars {~m_st~0=v_~m_st~0_2} OutVars{~m_st~0=v_~m_st~0_2, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 273431#L486-2 [3840] L486-2-->L904: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 273430#L904 [2393] L904-->L911: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 273425#L911 [3851] L911-->L930-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_6|, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 268773#L930-1 312.69/160.50 [2019-03-28 12:22:21,781 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.50 [2019-03-28 12:22:21,781 INFO L82 PathProgramCache]: Analyzing trace with hash 1734800441, now seen corresponding path program 1 times 312.69/160.50 [2019-03-28 12:22:21,781 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.50 [2019-03-28 12:22:21,781 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.50 [2019-03-28 12:22:21,782 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:21,782 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:21,782 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:21,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.50 [2019-03-28 12:22:21,817 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.50 [2019-03-28 12:22:21,817 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.50 [2019-03-28 12:22:21,817 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 312.69/160.50 [2019-03-28 12:22:21,818 INFO L799 eck$LassoCheckResult]: stem already infeasible 312.69/160.50 [2019-03-28 12:22:21,818 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.50 [2019-03-28 12:22:21,818 INFO L82 PathProgramCache]: Analyzing trace with hash -1547676983, now seen corresponding path program 1 times 312.69/160.50 [2019-03-28 12:22:21,818 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.50 [2019-03-28 12:22:21,818 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.50 [2019-03-28 12:22:21,819 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:21,819 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:21,819 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:21,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.50 [2019-03-28 12:22:21,843 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.50 [2019-03-28 12:22:21,843 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.50 [2019-03-28 12:22:21,843 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 312.69/160.50 [2019-03-28 12:22:21,843 INFO L811 eck$LassoCheckResult]: loop already infeasible 312.69/160.50 [2019-03-28 12:22:21,844 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. 312.69/160.50 [2019-03-28 12:22:21,844 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 312.69/160.50 [2019-03-28 12:22:21,844 INFO L87 Difference]: Start difference. First operand 17565 states and 28126 transitions. cyclomatic complexity: 10562 Second operand 4 states. 312.69/160.50 [2019-03-28 12:22:22,403 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.50 [2019-03-28 12:22:22,403 INFO L93 Difference]: Finished difference Result 17565 states and 27738 transitions. 312.69/160.50 [2019-03-28 12:22:22,403 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 312.69/160.50 [2019-03-28 12:22:22,404 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17565 states and 27738 transitions. 312.69/160.50 [2019-03-28 12:22:22,472 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 17504 312.69/160.50 [2019-03-28 12:22:22,513 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17565 states to 17565 states and 27738 transitions. 312.69/160.50 [2019-03-28 12:22:22,513 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17565 312.69/160.50 [2019-03-28 12:22:22,525 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17565 312.69/160.50 [2019-03-28 12:22:22,526 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17565 states and 27738 transitions. 312.69/160.50 [2019-03-28 12:22:22,537 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.50 [2019-03-28 12:22:22,538 INFO L706 BuchiCegarLoop]: Abstraction has 17565 states and 27738 transitions. 312.69/160.50 [2019-03-28 12:22:22,544 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17565 states and 27738 transitions. 312.69/160.50 [2019-03-28 12:22:22,666 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17565 to 17565. 312.69/160.50 [2019-03-28 12:22:22,666 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17565 states. 312.69/160.50 [2019-03-28 12:22:22,698 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17565 states to 17565 states and 27738 transitions. 312.69/160.50 [2019-03-28 12:22:22,698 INFO L729 BuchiCegarLoop]: Abstraction has 17565 states and 27738 transitions. 312.69/160.50 [2019-03-28 12:22:22,698 INFO L609 BuchiCegarLoop]: Abstraction has 17565 states and 27738 transitions. 312.69/160.50 [2019-03-28 12:22:22,698 INFO L442 BuchiCegarLoop]: ======== Iteration 35============ 312.69/160.50 [2019-03-28 12:22:22,698 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17565 states and 27738 transitions. 312.69/160.50 [2019-03-28 12:22:22,756 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 17504 312.69/160.50 [2019-03-28 12:22:22,756 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.50 [2019-03-28 12:22:22,756 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.50 [2019-03-28 12:22:22,760 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.50 [2019-03-28 12:22:22,760 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.50 [2019-03-28 12:22:22,761 INFO L794 eck$LassoCheckResult]: Stem: 304234#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 304033#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 304034#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 304099#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 304100#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 304037#L431-1 [2355] L431-1-->L436-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 304038#L436-1 [2735] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 304076#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 304077#L601-1 [3235] L601-1-->L606-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 304079#L606-1 [3236] L606-1-->L611-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 303948#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 303949#L616-1 [3240] L616-1-->L621-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 303835#L621-1 [3242] L621-1-->L626-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 303836#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 303918#L631-1 [3246] L631-1-->L636-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 303919#L636-1 [3248] L636-1-->L641-1: Formula: (> v_~E_2~0_4 0) InVars {~E_2~0=v_~E_2~0_4} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[] 304124#L641-1 [3251] L641-1-->L646-1: Formula: (> v_~E_3~0_4 0) InVars {~E_3~0=v_~E_3~0_4} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[] 304125#L646-1 [3253] L646-1-->L651-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 304067#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 304068#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 304319#L294 [3256] L294-->L294-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 304360#L294-2 [2905] L294-2-->L305: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 304376#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 304377#L745 [2925] L745-->L745-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_6) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} AuxVars[] AssignedVars[] 304389#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 304001#L313 [3262] L313-->L313-2: Formula: (< v_~t1_pc~0_3 1) InVars {~t1_pc~0=v_~t1_pc~0_3} OutVars{~t1_pc~0=v_~t1_pc~0_3} AuxVars[] AssignedVars[] 304002#L313-2 [2314] L313-2-->L324: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 304000#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 303852#L753 [2130] L753-->L753-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} AuxVars[] AssignedVars[] 303853#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 303855#L332 [3268] L332-->L332-2: Formula: (< v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 304043#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 304041#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 304042#L761 [2384] L761-->L761-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} AuxVars[] AssignedVars[] 304062#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 304063#L351 [3274] L351-->L351-2: Formula: (> 1 v_~t3_pc~0_3) InVars {~t3_pc~0=v_~t3_pc~0_3} OutVars{~t3_pc~0=v_~t3_pc~0_3} AuxVars[] AssignedVars[] 304180#L351-2 [2543] L351-2-->L362: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 304181#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 304197#L769 [2585] L769-->L769-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} AuxVars[] AssignedVars[] 304200#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 304201#L370 [3280] L370-->L370-2: Formula: (< v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 304303#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 304301#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 304302#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 304318#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 303910#L389 [3286] L389-->L389-2: Formula: (> 1 v_~t5_pc~0_3) InVars {~t5_pc~0=v_~t5_pc~0_3} OutVars{~t5_pc~0=v_~t5_pc~0_3} AuxVars[] AssignedVars[] 303882#L389-2 [2164] L389-2-->L400: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 303883#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 303909#L785 [2215] L785-->L785-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_6} AuxVars[] AssignedVars[] 303926#L785-2 [3292] L785-2-->L669-1: Formula: (< 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 303927#L669-1 [3294] L669-1-->L674-1: Formula: (< 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 304122#L674-1 [3296] L674-1-->L679-1: Formula: (< 1 v_~T2_E~0_7) InVars {~T2_E~0=v_~T2_E~0_7} OutVars{~T2_E~0=v_~T2_E~0_7} AuxVars[] AssignedVars[] 304123#L679-1 [3298] L679-1-->L684-1: Formula: (> v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 304065#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 304066#L689-1 [3302] L689-1-->L694-1: Formula: (> v_~T5_E~0_7 1) InVars {~T5_E~0=v_~T5_E~0_7} OutVars{~T5_E~0=v_~T5_E~0_7} AuxVars[] AssignedVars[] 304226#L694-1 [3305] L694-1-->L699-1: Formula: (< v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 303971#L699-1 [3306] L699-1-->L704-1: Formula: (> v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 303972#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 303825#L709-1 [3310] L709-1-->L714-1: Formula: (> v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 303826#L714-1 [3313] L714-1-->L719-1: Formula: (> v_~E_4~0_9 1) InVars {~E_4~0=v_~E_4~0_9} OutVars{~E_4~0=v_~E_4~0_9} AuxVars[] AssignedVars[] 303912#L719-1 [2198] L719-1-->L930-1: Formula: (and (= v_~E_5~0_8 1) (= v_~E_5~0_7 2)) InVars {~E_5~0=v_~E_5~0_8} OutVars{~E_5~0=v_~E_5~0_7} AuxVars[] AssignedVars[~E_5~0] 303913#L930-1 312.69/160.50 [2019-03-28 12:22:22,762 INFO L796 eck$LassoCheckResult]: Loop: 303913#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 308086#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 308085#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 308079#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 308078#L501 [3784] L501-->L601-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 304315#L601-2 [3318] L601-2-->L601-4: Formula: (> v_~M_E~0_10 0) InVars {~M_E~0=v_~M_E~0_10} OutVars{~M_E~0=v_~M_E~0_10} AuxVars[] AssignedVars[] 304316#L601-4 [3322] L601-4-->L606-3: Formula: (> v_~T1_E~0_10 0) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 304082#L606-3 [3326] L606-3-->L611-3: Formula: (< 0 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 303957#L611-3 [3333] L611-3-->L616-3: Formula: (< 0 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 303958#L616-3 [3339] L616-3-->L621-3: Formula: (> v_~T4_E~0_10 0) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 303842#L621-3 [3346] L621-3-->L626-3: Formula: (< 0 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 303843#L626-3 [2580] L626-3-->L631-3: Formula: (and (= v_~E_M~0_24 1) (= 0 v_~E_M~0_25)) InVars {~E_M~0=v_~E_M~0_25} OutVars{~E_M~0=v_~E_M~0_24} AuxVars[] AssignedVars[~E_M~0] 303895#L631-3 [3365] L631-3-->L636-3: Formula: (< 0 v_~E_1~0_26) InVars {~E_1~0=v_~E_1~0_26} OutVars{~E_1~0=v_~E_1~0_26} AuxVars[] AssignedVars[] 303896#L636-3 [3376] L636-3-->L641-3: Formula: (< 0 v_~E_2~0_26) InVars {~E_2~0=v_~E_2~0_26} OutVars{~E_2~0=v_~E_2~0_26} AuxVars[] AssignedVars[] 304109#L641-3 [3388] L641-3-->L646-3: Formula: (< 0 v_~E_3~0_26) InVars {~E_3~0=v_~E_3~0_26} OutVars{~E_3~0=v_~E_3~0_26} AuxVars[] AssignedVars[] 304110#L646-3 [3401] L646-3-->L651-3: Formula: (< 0 v_~E_4~0_26) InVars {~E_4~0=v_~E_4~0_26} OutVars{~E_4~0=v_~E_4~0_26} AuxVars[] AssignedVars[] 304057#L651-3 [3410] L651-3-->L656-3: Formula: (> 0 v_~E_5~0_26) InVars {~E_5~0=v_~E_5~0_26} OutVars{~E_5~0=v_~E_5~0_26} AuxVars[] AssignedVars[] 304058#L656-3 [2767] L656-3-->L294-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_37, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_37, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_22|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_22|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_22|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_37, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_37, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_22|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_22|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_22|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_22|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_37, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_37, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_37} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 304314#L294-21 [3426] L294-21-->L294-23: Formula: (< v_~m_pc~0_22 1) InVars {~m_pc~0=v_~m_pc~0_22} OutVars{~m_pc~0=v_~m_pc~0_22} AuxVars[] AssignedVars[] 321330#L294-23 [2803] L294-23-->L305-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_41 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_41} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 321328#L305-7 [3806] L305-7-->L745-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 320934#L745-21 [2835] L745-21-->L745-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_42) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} AuxVars[] AssignedVars[] 320933#L745-23 [2838] L745-23-->L313-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_43, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 318711#L313-21 [3469] L313-21-->L313-23: Formula: (< v_~t1_pc~0_22 1) InVars {~t1_pc~0=v_~t1_pc~0_22} OutVars{~t1_pc~0=v_~t1_pc~0_22} AuxVars[] AssignedVars[] 318709#L313-23 [2249] L313-23-->L324-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 318707#L324-7 [3813] L324-7-->L753-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 318659#L753-21 [2292] L753-21-->L753-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} AuxVars[] AssignedVars[] 318654#L753-23 [2297] L753-23-->L332-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_22|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 318641#L332-21 [3510] L332-21-->L332-23: Formula: (> 1 v_~t2_pc~0_22) InVars {~t2_pc~0=v_~t2_pc~0_22} OutVars{~t2_pc~0=v_~t2_pc~0_22} AuxVars[] AssignedVars[] 318639#L332-23 [2476] L332-23-->L343-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 318638#L343-7 [3820] L343-7-->L761-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 318637#L761-21 [2490] L761-21-->L761-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_42} AuxVars[] AssignedVars[] 318636#L761-23 [2493] L761-23-->L351-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_22|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 318239#L351-21 [3552] L351-21-->L351-23: Formula: (< v_~t3_pc~0_22 1) InVars {~t3_pc~0=v_~t3_pc~0_22} OutVars{~t3_pc~0=v_~t3_pc~0_22} AuxVars[] AssignedVars[] 318237#L351-23 [2660] L351-23-->L362-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 318235#L362-7 [3827] L362-7-->L769-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 318067#L769-21 [2534] L769-21-->L769-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} AuxVars[] AssignedVars[] 318066#L769-23 [2537] L769-23-->L370-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_43, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 318065#L370-21 [3595] L370-21-->L370-23: Formula: (> 1 v_~t4_pc~0_22) InVars {~t4_pc~0=v_~t4_pc~0_22} OutVars{~t4_pc~0=v_~t4_pc~0_22} AuxVars[] AssignedVars[] 315312#L370-23 [2934] L370-23-->L381-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 318062#L381-7 [3834] L381-7-->L777-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 318060#L777-21 [2705] L777-21-->L777-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} AuxVars[] AssignedVars[] 318058#L777-23 [2708] L777-23-->L389-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_22|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 308150#L389-21 [3637] L389-21-->L389-23: Formula: (< v_~t5_pc~0_22 1) InVars {~t5_pc~0=v_~t5_pc~0_22} OutVars{~t5_pc~0=v_~t5_pc~0_22} AuxVars[] AssignedVars[] 308148#L389-23 [2111] L389-23-->L400-7: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 308146#L400-7 [3837] L400-7-->L785-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 308144#L785-21 [2159] L785-21-->L785-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_42} AuxVars[] AssignedVars[] 308142#L785-23 [3658] L785-23-->L669-3: Formula: (> v_~M_E~0_13 1) InVars {~M_E~0=v_~M_E~0_13} OutVars{~M_E~0=v_~M_E~0_13} AuxVars[] AssignedVars[] 308139#L669-3 [3660] L669-3-->L674-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 308136#L674-3 [3662] L674-3-->L679-3: Formula: (< 1 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 308134#L679-3 [3664] L679-3-->L684-3: Formula: (< 1 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 308131#L684-3 [3666] L684-3-->L689-3: Formula: (> v_~T4_E~0_13 1) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 308129#L689-3 [3668] L689-3-->L694-3: Formula: (< 1 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 308127#L694-3 [2405] L694-3-->L699-3: Formula: (and (= 1 v_~E_M~0_30) (= v_~E_M~0_29 2)) InVars {~E_M~0=v_~E_M~0_30} OutVars{~E_M~0=v_~E_M~0_29} AuxVars[] AssignedVars[~E_M~0] 308125#L699-3 [3673] L699-3-->L704-3: Formula: (< 1 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 308123#L704-3 [3675] L704-3-->L709-3: Formula: (< 1 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 308121#L709-3 [3677] L709-3-->L714-3: Formula: (< 1 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 308119#L714-3 [3678] L714-3-->L719-3: Formula: (< 1 v_~E_4~0_31) InVars {~E_4~0=v_~E_4~0_31} OutVars{~E_4~0=v_~E_4~0_31} AuxVars[] AssignedVars[] 308117#L719-3 [3680] L719-3-->L724-3: Formula: (> 1 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 308115#L724-3 [2818] L724-3-->L454-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_23} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 308103#L454-1 [2466] L454-1-->L486-1: Formula: (and (= 0 v_~m_st~0_20) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26 1)) InVars {~m_st~0=v_~m_st~0_20} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 308101#L486-1 [3838] L486-1-->L949: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret15, ULTIMATE.start_start_simulation_~tmp~3] 308100#L949 [3688] L949-->L949-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_1) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} AuxVars[] AssignedVars[] 308098#L949-1 [2479] L949-1-->L454-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_1} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 308095#L454-2 [2438] L454-2-->L486-2: Formula: (and (= v_~m_st~0_2 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4 1)) InVars {~m_st~0=v_~m_st~0_2} OutVars{~m_st~0=v_~m_st~0_2, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 308091#L486-2 [3840] L486-2-->L904: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 308090#L904 [2393] L904-->L911: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 308089#L911 [3851] L911-->L930-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_6|, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 303913#L930-1 312.69/160.50 [2019-03-28 12:22:22,762 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.50 [2019-03-28 12:22:22,763 INFO L82 PathProgramCache]: Analyzing trace with hash -752712392, now seen corresponding path program 1 times 312.69/160.50 [2019-03-28 12:22:22,763 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.50 [2019-03-28 12:22:22,763 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.50 [2019-03-28 12:22:22,763 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:22,764 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:22,764 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:22,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.50 [2019-03-28 12:22:22,803 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.50 [2019-03-28 12:22:22,804 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.50 [2019-03-28 12:22:22,804 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 312.69/160.50 [2019-03-28 12:22:22,804 INFO L799 eck$LassoCheckResult]: stem already infeasible 312.69/160.50 [2019-03-28 12:22:22,804 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.50 [2019-03-28 12:22:22,805 INFO L82 PathProgramCache]: Analyzing trace with hash -239670924, now seen corresponding path program 1 times 312.69/160.50 [2019-03-28 12:22:22,805 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.50 [2019-03-28 12:22:22,805 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.50 [2019-03-28 12:22:22,805 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:22,806 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:22,806 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:22,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.50 [2019-03-28 12:22:22,825 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.50 [2019-03-28 12:22:22,825 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.50 [2019-03-28 12:22:22,826 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 312.69/160.50 [2019-03-28 12:22:22,826 INFO L811 eck$LassoCheckResult]: loop already infeasible 312.69/160.50 [2019-03-28 12:22:22,826 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. 312.69/160.50 [2019-03-28 12:22:22,826 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 312.69/160.50 [2019-03-28 12:22:22,826 INFO L87 Difference]: Start difference. First operand 17565 states and 27738 transitions. cyclomatic complexity: 10174 Second operand 4 states. 312.69/160.50 [2019-03-28 12:22:23,219 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.50 [2019-03-28 12:22:23,219 INFO L93 Difference]: Finished difference Result 17789 states and 27254 transitions. 312.69/160.50 [2019-03-28 12:22:23,219 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. 312.69/160.50 [2019-03-28 12:22:23,220 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17789 states and 27254 transitions. 312.69/160.50 [2019-03-28 12:22:23,290 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 17728 312.69/160.50 [2019-03-28 12:22:23,331 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17789 states to 17789 states and 27254 transitions. 312.69/160.50 [2019-03-28 12:22:23,331 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17789 312.69/160.50 [2019-03-28 12:22:23,343 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17789 312.69/160.50 [2019-03-28 12:22:23,343 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17789 states and 27254 transitions. 312.69/160.50 [2019-03-28 12:22:23,355 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.50 [2019-03-28 12:22:23,355 INFO L706 BuchiCegarLoop]: Abstraction has 17789 states and 27254 transitions. 312.69/160.50 [2019-03-28 12:22:23,362 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17789 states and 27254 transitions. 312.69/160.50 [2019-03-28 12:22:23,481 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17789 to 17245. 312.69/160.50 [2019-03-28 12:22:23,482 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17245 states. 312.69/160.50 [2019-03-28 12:22:23,512 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17245 states to 17245 states and 26534 transitions. 312.69/160.50 [2019-03-28 12:22:23,512 INFO L729 BuchiCegarLoop]: Abstraction has 17245 states and 26534 transitions. 312.69/160.50 [2019-03-28 12:22:23,513 INFO L609 BuchiCegarLoop]: Abstraction has 17245 states and 26534 transitions. 312.69/160.50 [2019-03-28 12:22:23,513 INFO L442 BuchiCegarLoop]: ======== Iteration 36============ 312.69/160.50 [2019-03-28 12:22:23,513 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17245 states and 26534 transitions. 312.69/160.50 [2019-03-28 12:22:23,567 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 17184 312.69/160.50 [2019-03-28 12:22:23,567 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.50 [2019-03-28 12:22:23,567 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.50 [2019-03-28 12:22:23,574 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.50 [2019-03-28 12:22:23,574 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.50 [2019-03-28 12:22:23,575 INFO L794 eck$LassoCheckResult]: Stem: 339615#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 339412#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 339413#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 339482#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 339483#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 339416#L431-1 [2355] L431-1-->L436-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 339417#L436-1 [2735] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 339456#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 339457#L601-1 [3235] L601-1-->L606-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 339459#L606-1 [3236] L606-1-->L611-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 339325#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 339326#L616-1 [3240] L616-1-->L621-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 339198#L621-1 [3242] L621-1-->L626-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 339199#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 339293#L631-1 [3246] L631-1-->L636-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 339294#L636-1 [3248] L636-1-->L641-1: Formula: (> v_~E_2~0_4 0) InVars {~E_2~0=v_~E_2~0_4} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[] 339505#L641-1 [3251] L641-1-->L646-1: Formula: (> v_~E_3~0_4 0) InVars {~E_3~0=v_~E_3~0_4} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[] 339506#L646-1 [3253] L646-1-->L651-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 339447#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 339448#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 339714#L294 [3256] L294-->L294-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 339756#L294-2 [2905] L294-2-->L305: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 339775#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 339776#L745 [2925] L745-->L745-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_6) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} AuxVars[] AssignedVars[] 339790#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 339377#L313 [3262] L313-->L313-2: Formula: (< v_~t1_pc~0_3 1) InVars {~t1_pc~0=v_~t1_pc~0_3} OutVars{~t1_pc~0=v_~t1_pc~0_3} AuxVars[] AssignedVars[] 339378#L313-2 [2314] L313-2-->L324: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 339376#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 339216#L753 [2130] L753-->L753-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} AuxVars[] AssignedVars[] 339217#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 339220#L332 [3268] L332-->L332-2: Formula: (< v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 339422#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 339420#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 339421#L761 [2384] L761-->L761-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} AuxVars[] AssignedVars[] 339443#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 339444#L351 [3274] L351-->L351-2: Formula: (> 1 v_~t3_pc~0_3) InVars {~t3_pc~0=v_~t3_pc~0_3} OutVars{~t3_pc~0=v_~t3_pc~0_3} AuxVars[] AssignedVars[] 339568#L351-2 [2543] L351-2-->L362: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 339569#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 339586#L769 [2585] L769-->L769-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} AuxVars[] AssignedVars[] 339589#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 339590#L370 [3280] L370-->L370-2: Formula: (< v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 339693#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 339691#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 339692#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 339713#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 339283#L389 [3286] L389-->L389-2: Formula: (> 1 v_~t5_pc~0_3) InVars {~t5_pc~0=v_~t5_pc~0_3} OutVars{~t5_pc~0=v_~t5_pc~0_3} AuxVars[] AssignedVars[] 339251#L389-2 [2164] L389-2-->L400: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 339252#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 339281#L785 [2215] L785-->L785-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_6} AuxVars[] AssignedVars[] 339303#L785-2 [3292] L785-2-->L669-1: Formula: (< 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 339304#L669-1 [3294] L669-1-->L674-1: Formula: (< 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 339503#L674-1 [3296] L674-1-->L679-1: Formula: (< 1 v_~T2_E~0_7) InVars {~T2_E~0=v_~T2_E~0_7} OutVars{~T2_E~0=v_~T2_E~0_7} AuxVars[] AssignedVars[] 339504#L679-1 [3298] L679-1-->L684-1: Formula: (> v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 339445#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 339446#L689-1 [3302] L689-1-->L694-1: Formula: (> v_~T5_E~0_7 1) InVars {~T5_E~0=v_~T5_E~0_7} OutVars{~T5_E~0=v_~T5_E~0_7} AuxVars[] AssignedVars[] 339608#L694-1 [3304] L694-1-->L699-1: Formula: (> v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 339347#L699-1 [3306] L699-1-->L704-1: Formula: (> v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 339348#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 339188#L709-1 [3310] L709-1-->L714-1: Formula: (> v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 339189#L714-1 [3313] L714-1-->L719-1: Formula: (> v_~E_4~0_9 1) InVars {~E_4~0=v_~E_4~0_9} OutVars{~E_4~0=v_~E_4~0_9} AuxVars[] AssignedVars[] 339288#L719-1 [2198] L719-1-->L930-1: Formula: (and (= v_~E_5~0_8 1) (= v_~E_5~0_7 2)) InVars {~E_5~0=v_~E_5~0_8} OutVars{~E_5~0=v_~E_5~0_7} AuxVars[] AssignedVars[~E_5~0] 339289#L930-1 312.69/160.50 [2019-03-28 12:22:23,576 INFO L796 eck$LassoCheckResult]: Loop: 339289#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 342141#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 342176#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 342170#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 342168#L501 [3784] L501-->L601-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 342169#L601-2 [3318] L601-2-->L601-4: Formula: (> v_~M_E~0_10 0) InVars {~M_E~0=v_~M_E~0_10} OutVars{~M_E~0=v_~M_E~0_10} AuxVars[] AssignedVars[] 356062#L601-4 [3322] L601-4-->L606-3: Formula: (> v_~T1_E~0_10 0) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 356060#L606-3 [3326] L606-3-->L611-3: Formula: (< 0 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 356059#L611-3 [3333] L611-3-->L616-3: Formula: (< 0 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 356057#L616-3 [3339] L616-3-->L621-3: Formula: (> v_~T4_E~0_10 0) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 356055#L621-3 [3346] L621-3-->L626-3: Formula: (< 0 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 356053#L626-3 [3354] L626-3-->L631-3: Formula: (< 0 v_~E_M~0_26) InVars {~E_M~0=v_~E_M~0_26} OutVars{~E_M~0=v_~E_M~0_26} AuxVars[] AssignedVars[] 356051#L631-3 [3365] L631-3-->L636-3: Formula: (< 0 v_~E_1~0_26) InVars {~E_1~0=v_~E_1~0_26} OutVars{~E_1~0=v_~E_1~0_26} AuxVars[] AssignedVars[] 356043#L636-3 [3376] L636-3-->L641-3: Formula: (< 0 v_~E_2~0_26) InVars {~E_2~0=v_~E_2~0_26} OutVars{~E_2~0=v_~E_2~0_26} AuxVars[] AssignedVars[] 356041#L641-3 [3388] L641-3-->L646-3: Formula: (< 0 v_~E_3~0_26) InVars {~E_3~0=v_~E_3~0_26} OutVars{~E_3~0=v_~E_3~0_26} AuxVars[] AssignedVars[] 356040#L646-3 [3401] L646-3-->L651-3: Formula: (< 0 v_~E_4~0_26) InVars {~E_4~0=v_~E_4~0_26} OutVars{~E_4~0=v_~E_4~0_26} AuxVars[] AssignedVars[] 356034#L651-3 [3410] L651-3-->L656-3: Formula: (> 0 v_~E_5~0_26) InVars {~E_5~0=v_~E_5~0_26} OutVars{~E_5~0=v_~E_5~0_26} AuxVars[] AssignedVars[] 356024#L656-3 [2767] L656-3-->L294-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_37, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_37, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_22|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_22|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_22|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_37, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_37, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_22|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_22|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_22|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_22|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_37, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_37, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_37} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 356023#L294-21 [3426] L294-21-->L294-23: Formula: (< v_~m_pc~0_22 1) InVars {~m_pc~0=v_~m_pc~0_22} OutVars{~m_pc~0=v_~m_pc~0_22} AuxVars[] AssignedVars[] 355882#L294-23 [2803] L294-23-->L305-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_41 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_41} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 356021#L305-7 [3806] L305-7-->L745-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 356019#L745-21 [2835] L745-21-->L745-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_42) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} AuxVars[] AssignedVars[] 356016#L745-23 [2838] L745-23-->L313-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_43, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 352860#L313-21 [3469] L313-21-->L313-23: Formula: (< v_~t1_pc~0_22 1) InVars {~t1_pc~0=v_~t1_pc~0_22} OutVars{~t1_pc~0=v_~t1_pc~0_22} AuxVars[] AssignedVars[] 352858#L313-23 [2249] L313-23-->L324-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 352856#L324-7 [3813] L324-7-->L753-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 352854#L753-21 [2292] L753-21-->L753-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} AuxVars[] AssignedVars[] 352853#L753-23 [2297] L753-23-->L332-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_22|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 352715#L332-21 [3510] L332-21-->L332-23: Formula: (> 1 v_~t2_pc~0_22) InVars {~t2_pc~0=v_~t2_pc~0_22} OutVars{~t2_pc~0=v_~t2_pc~0_22} AuxVars[] AssignedVars[] 352712#L332-23 [2476] L332-23-->L343-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 352710#L343-7 [3820] L343-7-->L761-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 352708#L761-21 [2490] L761-21-->L761-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_42} AuxVars[] AssignedVars[] 352706#L761-23 [2493] L761-23-->L351-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_22|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 352704#L351-21 [3552] L351-21-->L351-23: Formula: (< v_~t3_pc~0_22 1) InVars {~t3_pc~0=v_~t3_pc~0_22} OutVars{~t3_pc~0=v_~t3_pc~0_22} AuxVars[] AssignedVars[] 352511#L351-23 [2660] L351-23-->L362-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 352702#L362-7 [3827] L362-7-->L769-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 352700#L769-21 [2534] L769-21-->L769-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} AuxVars[] AssignedVars[] 351249#L769-23 [2537] L769-23-->L370-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_43, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 342238#L370-21 [3595] L370-21-->L370-23: Formula: (> 1 v_~t4_pc~0_22) InVars {~t4_pc~0=v_~t4_pc~0_22} OutVars{~t4_pc~0=v_~t4_pc~0_22} AuxVars[] AssignedVars[] 342236#L370-23 [2934] L370-23-->L381-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 342235#L381-7 [3834] L381-7-->L777-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 342234#L777-21 [2705] L777-21-->L777-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} AuxVars[] AssignedVars[] 342233#L777-23 [2708] L777-23-->L389-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_22|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 342232#L389-21 [3637] L389-21-->L389-23: Formula: (< v_~t5_pc~0_22 1) InVars {~t5_pc~0=v_~t5_pc~0_22} OutVars{~t5_pc~0=v_~t5_pc~0_22} AuxVars[] AssignedVars[] 342079#L389-23 [2111] L389-23-->L400-7: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 342231#L400-7 [3837] L400-7-->L785-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 342230#L785-21 [2159] L785-21-->L785-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_42} AuxVars[] AssignedVars[] 342228#L785-23 [3658] L785-23-->L669-3: Formula: (> v_~M_E~0_13 1) InVars {~M_E~0=v_~M_E~0_13} OutVars{~M_E~0=v_~M_E~0_13} AuxVars[] AssignedVars[] 342226#L669-3 [3660] L669-3-->L674-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 342224#L674-3 [3662] L674-3-->L679-3: Formula: (< 1 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 342222#L679-3 [3664] L679-3-->L684-3: Formula: (< 1 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 342220#L684-3 [3666] L684-3-->L689-3: Formula: (> v_~T4_E~0_13 1) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 342218#L689-3 [3668] L689-3-->L694-3: Formula: (< 1 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 342217#L694-3 [3670] L694-3-->L699-3: Formula: (< 1 v_~E_M~0_31) InVars {~E_M~0=v_~E_M~0_31} OutVars{~E_M~0=v_~E_M~0_31} AuxVars[] AssignedVars[] 342215#L699-3 [3673] L699-3-->L704-3: Formula: (< 1 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 342213#L704-3 [3675] L704-3-->L709-3: Formula: (< 1 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 342211#L709-3 [3677] L709-3-->L714-3: Formula: (< 1 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 342209#L714-3 [3678] L714-3-->L719-3: Formula: (< 1 v_~E_4~0_31) InVars {~E_4~0=v_~E_4~0_31} OutVars{~E_4~0=v_~E_4~0_31} AuxVars[] AssignedVars[] 342207#L719-3 [3680] L719-3-->L724-3: Formula: (> 1 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 342205#L724-3 [2818] L724-3-->L454-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_23} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 342193#L454-1 [2466] L454-1-->L486-1: Formula: (and (= 0 v_~m_st~0_20) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26 1)) InVars {~m_st~0=v_~m_st~0_20} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 342191#L486-1 [3838] L486-1-->L949: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret15, ULTIMATE.start_start_simulation_~tmp~3] 342189#L949 [3688] L949-->L949-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_1) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} AuxVars[] AssignedVars[] 342187#L949-1 [2479] L949-1-->L454-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_1} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 342183#L454-2 [2438] L454-2-->L486-2: Formula: (and (= v_~m_st~0_2 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4 1)) InVars {~m_st~0=v_~m_st~0_2} OutVars{~m_st~0=v_~m_st~0_2, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 342179#L486-2 [3840] L486-2-->L904: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 342178#L904 [2393] L904-->L911: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 342177#L911 [3851] L911-->L930-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_6|, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 339289#L930-1 312.69/160.50 [2019-03-28 12:22:23,576 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.50 [2019-03-28 12:22:23,576 INFO L82 PathProgramCache]: Analyzing trace with hash -781341543, now seen corresponding path program 1 times 312.69/160.50 [2019-03-28 12:22:23,577 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.50 [2019-03-28 12:22:23,577 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.50 [2019-03-28 12:22:23,577 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:23,578 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:23,578 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:23,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.50 [2019-03-28 12:22:23,606 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.50 [2019-03-28 12:22:23,606 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.50 [2019-03-28 12:22:23,606 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 312.69/160.50 [2019-03-28 12:22:23,607 INFO L799 eck$LassoCheckResult]: stem already infeasible 312.69/160.50 [2019-03-28 12:22:23,607 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.50 [2019-03-28 12:22:23,607 INFO L82 PathProgramCache]: Analyzing trace with hash -1803407957, now seen corresponding path program 1 times 312.69/160.50 [2019-03-28 12:22:23,607 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.50 [2019-03-28 12:22:23,607 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.50 [2019-03-28 12:22:23,608 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:23,608 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:23,608 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:23,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.50 [2019-03-28 12:22:23,626 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.50 [2019-03-28 12:22:23,627 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.50 [2019-03-28 12:22:23,627 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 312.69/160.50 [2019-03-28 12:22:23,627 INFO L811 eck$LassoCheckResult]: loop already infeasible 312.69/160.50 [2019-03-28 12:22:23,628 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 312.69/160.50 [2019-03-28 12:22:23,628 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 312.69/160.50 [2019-03-28 12:22:23,628 INFO L87 Difference]: Start difference. First operand 17245 states and 26534 transitions. cyclomatic complexity: 9290 Second operand 3 states. 312.69/160.50 [2019-03-28 12:22:23,965 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.50 [2019-03-28 12:22:23,966 INFO L93 Difference]: Finished difference Result 16989 states and 25410 transitions. 312.69/160.50 [2019-03-28 12:22:23,966 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 312.69/160.50 [2019-03-28 12:22:23,966 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16989 states and 25410 transitions. 312.69/160.50 [2019-03-28 12:22:24,035 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 16928 312.69/160.50 [2019-03-28 12:22:24,075 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16989 states to 16989 states and 25410 transitions. 312.69/160.50 [2019-03-28 12:22:24,075 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16989 312.69/160.50 [2019-03-28 12:22:24,086 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16989 312.69/160.50 [2019-03-28 12:22:24,086 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16989 states and 25410 transitions. 312.69/160.50 [2019-03-28 12:22:24,098 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.50 [2019-03-28 12:22:24,098 INFO L706 BuchiCegarLoop]: Abstraction has 16989 states and 25410 transitions. 312.69/160.50 [2019-03-28 12:22:24,105 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16989 states and 25410 transitions. 312.69/160.50 [2019-03-28 12:22:24,221 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16989 to 16925. 312.69/160.50 [2019-03-28 12:22:24,221 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16925 states. 312.69/160.50 [2019-03-28 12:22:24,253 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16925 states to 16925 states and 25346 transitions. 312.69/160.50 [2019-03-28 12:22:24,253 INFO L729 BuchiCegarLoop]: Abstraction has 16925 states and 25346 transitions. 312.69/160.50 [2019-03-28 12:22:24,253 INFO L609 BuchiCegarLoop]: Abstraction has 16925 states and 25346 transitions. 312.69/160.50 [2019-03-28 12:22:24,253 INFO L442 BuchiCegarLoop]: ======== Iteration 37============ 312.69/160.50 [2019-03-28 12:22:24,254 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16925 states and 25346 transitions. 312.69/160.50 [2019-03-28 12:22:24,440 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 16864 312.69/160.50 [2019-03-28 12:22:24,441 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.50 [2019-03-28 12:22:24,441 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.50 [2019-03-28 12:22:24,445 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.50 [2019-03-28 12:22:24,445 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.50 [2019-03-28 12:22:24,446 INFO L794 eck$LassoCheckResult]: Stem: 373828#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 373632#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 373633#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 373699#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 373700#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 373636#L431-1 [2355] L431-1-->L436-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 373637#L436-1 [2735] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 373674#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 373675#L601-1 [3235] L601-1-->L606-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 373678#L606-1 [3236] L606-1-->L611-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 373554#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 373555#L616-1 [3240] L616-1-->L621-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 373440#L621-1 [3242] L621-1-->L626-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 373441#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 373525#L631-1 [3246] L631-1-->L636-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 373526#L636-1 [3248] L636-1-->L641-1: Formula: (> v_~E_2~0_4 0) InVars {~E_2~0=v_~E_2~0_4} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[] 373723#L641-1 [3251] L641-1-->L646-1: Formula: (> v_~E_3~0_4 0) InVars {~E_3~0=v_~E_3~0_4} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[] 373724#L646-1 [3253] L646-1-->L651-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 373665#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 373666#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 373913#L294 [3256] L294-->L294-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 373957#L294-2 [2905] L294-2-->L305: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 373979#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 373980#L745 [2925] L745-->L745-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_6) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} AuxVars[] AssignedVars[] 373994#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 373604#L313 [3262] L313-->L313-2: Formula: (< v_~t1_pc~0_3 1) InVars {~t1_pc~0=v_~t1_pc~0_3} OutVars{~t1_pc~0=v_~t1_pc~0_3} AuxVars[] AssignedVars[] 373605#L313-2 [2314] L313-2-->L324: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 373603#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 373457#L753 [2130] L753-->L753-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} AuxVars[] AssignedVars[] 373458#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 373461#L332 [3268] L332-->L332-2: Formula: (< v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 373642#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 373640#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 373641#L761 [2384] L761-->L761-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} AuxVars[] AssignedVars[] 373661#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 373662#L351 [3274] L351-->L351-2: Formula: (> 1 v_~t3_pc~0_3) InVars {~t3_pc~0=v_~t3_pc~0_3} OutVars{~t3_pc~0=v_~t3_pc~0_3} AuxVars[] AssignedVars[] 373779#L351-2 [2543] L351-2-->L362: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 373780#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 373798#L769 [2585] L769-->L769-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} AuxVars[] AssignedVars[] 373802#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 373803#L370 [3280] L370-->L370-2: Formula: (< v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 373895#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 373893#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 373894#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 373912#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 373517#L389 [3286] L389-->L389-2: Formula: (> 1 v_~t5_pc~0_3) InVars {~t5_pc~0=v_~t5_pc~0_3} OutVars{~t5_pc~0=v_~t5_pc~0_3} AuxVars[] AssignedVars[] 373488#L389-2 [2164] L389-2-->L400: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 373489#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 373516#L785 [2215] L785-->L785-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_6} AuxVars[] AssignedVars[] 373533#L785-2 [3292] L785-2-->L669-1: Formula: (< 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 373534#L669-1 [3294] L669-1-->L674-1: Formula: (< 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 373721#L674-1 [3296] L674-1-->L679-1: Formula: (< 1 v_~T2_E~0_7) InVars {~T2_E~0=v_~T2_E~0_7} OutVars{~T2_E~0=v_~T2_E~0_7} AuxVars[] AssignedVars[] 373722#L679-1 [3298] L679-1-->L684-1: Formula: (> v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 373663#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 373664#L689-1 [3302] L689-1-->L694-1: Formula: (> v_~T5_E~0_7 1) InVars {~T5_E~0=v_~T5_E~0_7} OutVars{~T5_E~0=v_~T5_E~0_7} AuxVars[] AssignedVars[] 373821#L694-1 [3304] L694-1-->L699-1: Formula: (> v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 373577#L699-1 [3306] L699-1-->L704-1: Formula: (> v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 373578#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 373430#L709-1 [3310] L709-1-->L714-1: Formula: (> v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 373431#L714-1 [3313] L714-1-->L719-1: Formula: (> v_~E_4~0_9 1) InVars {~E_4~0=v_~E_4~0_9} OutVars{~E_4~0=v_~E_4~0_9} AuxVars[] AssignedVars[] 373520#L719-1 [3314] L719-1-->L930-1: Formula: (> v_~E_5~0_9 1) InVars {~E_5~0=v_~E_5~0_9} OutVars{~E_5~0=v_~E_5~0_9} AuxVars[] AssignedVars[] 373521#L930-1 312.69/160.50 [2019-03-28 12:22:24,447 INFO L796 eck$LassoCheckResult]: Loop: 373521#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 379159#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 379157#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 379150#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 379148#L501 [3784] L501-->L601-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 373909#L601-2 [3318] L601-2-->L601-4: Formula: (> v_~M_E~0_10 0) InVars {~M_E~0=v_~M_E~0_10} OutVars{~M_E~0=v_~M_E~0_10} AuxVars[] AssignedVars[] 373910#L601-4 [3322] L601-4-->L606-3: Formula: (> v_~T1_E~0_10 0) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 373681#L606-3 [3326] L606-3-->L611-3: Formula: (< 0 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 373682#L611-3 [3333] L611-3-->L616-3: Formula: (< 0 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 390327#L616-3 [3339] L616-3-->L621-3: Formula: (> v_~T4_E~0_10 0) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 373447#L621-3 [3346] L621-3-->L626-3: Formula: (< 0 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 373448#L626-3 [3354] L626-3-->L631-3: Formula: (< 0 v_~E_M~0_26) InVars {~E_M~0=v_~E_M~0_26} OutVars{~E_M~0=v_~E_M~0_26} AuxVars[] AssignedVars[] 373502#L631-3 [3365] L631-3-->L636-3: Formula: (< 0 v_~E_1~0_26) InVars {~E_1~0=v_~E_1~0_26} OutVars{~E_1~0=v_~E_1~0_26} AuxVars[] AssignedVars[] 373503#L636-3 [3376] L636-3-->L641-3: Formula: (< 0 v_~E_2~0_26) InVars {~E_2~0=v_~E_2~0_26} OutVars{~E_2~0=v_~E_2~0_26} AuxVars[] AssignedVars[] 373710#L641-3 [3388] L641-3-->L646-3: Formula: (< 0 v_~E_3~0_26) InVars {~E_3~0=v_~E_3~0_26} OutVars{~E_3~0=v_~E_3~0_26} AuxVars[] AssignedVars[] 373711#L646-3 [3401] L646-3-->L651-3: Formula: (< 0 v_~E_4~0_26) InVars {~E_4~0=v_~E_4~0_26} OutVars{~E_4~0=v_~E_4~0_26} AuxVars[] AssignedVars[] 373655#L651-3 [3411] L651-3-->L656-3: Formula: (< 0 v_~E_5~0_26) InVars {~E_5~0=v_~E_5~0_26} OutVars{~E_5~0=v_~E_5~0_26} AuxVars[] AssignedVars[] 373656#L656-3 [2767] L656-3-->L294-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_37, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_37, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_22|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_22|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_22|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_37, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_37, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_22|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_22|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_22|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_22|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_37, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_37, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_37} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 390159#L294-21 [3426] L294-21-->L294-23: Formula: (< v_~m_pc~0_22 1) InVars {~m_pc~0=v_~m_pc~0_22} OutVars{~m_pc~0=v_~m_pc~0_22} AuxVars[] AssignedVars[] 390158#L294-23 [2803] L294-23-->L305-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_41 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_41} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 390156#L305-7 [3806] L305-7-->L745-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 390154#L745-21 [2835] L745-21-->L745-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_42) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} AuxVars[] AssignedVars[] 390153#L745-23 [2838] L745-23-->L313-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_43, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 390152#L313-21 [3469] L313-21-->L313-23: Formula: (< v_~t1_pc~0_22 1) InVars {~t1_pc~0=v_~t1_pc~0_22} OutVars{~t1_pc~0=v_~t1_pc~0_22} AuxVars[] AssignedVars[] 389857#L313-23 [2249] L313-23-->L324-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 390151#L324-7 [3813] L324-7-->L753-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 390149#L753-21 [2292] L753-21-->L753-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} AuxVars[] AssignedVars[] 390148#L753-23 [2297] L753-23-->L332-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_22|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 390147#L332-21 [3510] L332-21-->L332-23: Formula: (> 1 v_~t2_pc~0_22) InVars {~t2_pc~0=v_~t2_pc~0_22} OutVars{~t2_pc~0=v_~t2_pc~0_22} AuxVars[] AssignedVars[] 373725#L332-23 [2476] L332-23-->L343-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 373726#L343-7 [3820] L343-7-->L761-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 373738#L761-21 [2490] L761-21-->L761-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_42} AuxVars[] AssignedVars[] 373739#L761-23 [2493] L761-23-->L351-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_22|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 373740#L351-21 [3552] L351-21-->L351-23: Formula: (< v_~t3_pc~0_22 1) InVars {~t3_pc~0=v_~t3_pc~0_22} OutVars{~t3_pc~0=v_~t3_pc~0_22} AuxVars[] AssignedVars[] 373845#L351-23 [2660] L351-23-->L362-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 373762#L362-7 [3827] L362-7-->L769-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 373763#L769-21 [2534] L769-21-->L769-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} AuxVars[] AssignedVars[] 373770#L769-23 [2537] L769-23-->L370-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_43, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 373773#L370-21 [3595] L370-21-->L370-23: Formula: (> 1 v_~t4_pc~0_22) InVars {~t4_pc~0=v_~t4_pc~0_22} OutVars{~t4_pc~0=v_~t4_pc~0_22} AuxVars[] AssignedVars[] 387254#L370-23 [2934] L370-23-->L381-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 387253#L381-7 [3834] L381-7-->L777-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 387251#L777-21 [2705] L777-21-->L777-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} AuxVars[] AssignedVars[] 387249#L777-23 [2708] L777-23-->L389-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_22|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 379232#L389-21 [3637] L389-21-->L389-23: Formula: (< v_~t5_pc~0_22 1) InVars {~t5_pc~0=v_~t5_pc~0_22} OutVars{~t5_pc~0=v_~t5_pc~0_22} AuxVars[] AssignedVars[] 379231#L389-23 [2111] L389-23-->L400-7: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 379224#L400-7 [3837] L400-7-->L785-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 379222#L785-21 [2159] L785-21-->L785-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_42} AuxVars[] AssignedVars[] 379221#L785-23 [3658] L785-23-->L669-3: Formula: (> v_~M_E~0_13 1) InVars {~M_E~0=v_~M_E~0_13} OutVars{~M_E~0=v_~M_E~0_13} AuxVars[] AssignedVars[] 379220#L669-3 [3660] L669-3-->L674-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 379219#L674-3 [3662] L674-3-->L679-3: Formula: (< 1 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 379218#L679-3 [3664] L679-3-->L684-3: Formula: (< 1 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 379217#L684-3 [3666] L684-3-->L689-3: Formula: (> v_~T4_E~0_13 1) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 379216#L689-3 [3668] L689-3-->L694-3: Formula: (< 1 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 379214#L694-3 [3670] L694-3-->L699-3: Formula: (< 1 v_~E_M~0_31) InVars {~E_M~0=v_~E_M~0_31} OutVars{~E_M~0=v_~E_M~0_31} AuxVars[] AssignedVars[] 379212#L699-3 [3673] L699-3-->L704-3: Formula: (< 1 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 379210#L704-3 [3675] L704-3-->L709-3: Formula: (< 1 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 379208#L709-3 [3677] L709-3-->L714-3: Formula: (< 1 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 379206#L714-3 [3678] L714-3-->L719-3: Formula: (< 1 v_~E_4~0_31) InVars {~E_4~0=v_~E_4~0_31} OutVars{~E_4~0=v_~E_4~0_31} AuxVars[] AssignedVars[] 379204#L719-3 [3681] L719-3-->L724-3: Formula: (< 1 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 379202#L724-3 [2818] L724-3-->L454-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_23} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 379190#L454-1 [2466] L454-1-->L486-1: Formula: (and (= 0 v_~m_st~0_20) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26 1)) InVars {~m_st~0=v_~m_st~0_20} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 379188#L486-1 [3838] L486-1-->L949: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret15, ULTIMATE.start_start_simulation_~tmp~3] 379184#L949 [3688] L949-->L949-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_1) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} AuxVars[] AssignedVars[] 379183#L949-1 [2479] L949-1-->L454-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_1} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 379180#L454-2 [2438] L454-2-->L486-2: Formula: (and (= v_~m_st~0_2 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4 1)) InVars {~m_st~0=v_~m_st~0_2} OutVars{~m_st~0=v_~m_st~0_2, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 379176#L486-2 [3840] L486-2-->L904: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 379174#L904 [2393] L904-->L911: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 379172#L911 [3851] L911-->L930-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_6|, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 373521#L930-1 312.69/160.50 [2019-03-28 12:22:24,447 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.50 [2019-03-28 12:22:24,447 INFO L82 PathProgramCache]: Analyzing trace with hash -781340427, now seen corresponding path program 1 times 312.69/160.50 [2019-03-28 12:22:24,447 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.50 [2019-03-28 12:22:24,447 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.50 [2019-03-28 12:22:24,448 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:24,448 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:24,448 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:24,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.50 [2019-03-28 12:22:24,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.50 [2019-03-28 12:22:24,497 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.50 [2019-03-28 12:22:24,497 INFO L82 PathProgramCache]: Analyzing trace with hash -1230751447, now seen corresponding path program 1 times 312.69/160.50 [2019-03-28 12:22:24,497 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.50 [2019-03-28 12:22:24,497 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.50 [2019-03-28 12:22:24,498 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:24,498 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:24,498 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:24,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.50 [2019-03-28 12:22:24,526 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.50 [2019-03-28 12:22:24,527 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.50 [2019-03-28 12:22:24,527 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 312.69/160.50 [2019-03-28 12:22:24,527 INFO L811 eck$LassoCheckResult]: loop already infeasible 312.69/160.50 [2019-03-28 12:22:24,527 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. 312.69/160.50 [2019-03-28 12:22:24,527 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 312.69/160.50 [2019-03-28 12:22:24,528 INFO L87 Difference]: Start difference. First operand 16925 states and 25346 transitions. cyclomatic complexity: 8422 Second operand 4 states. 312.69/160.50 [2019-03-28 12:22:25,224 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.50 [2019-03-28 12:22:25,224 INFO L93 Difference]: Finished difference Result 29565 states and 44290 transitions. 312.69/160.50 [2019-03-28 12:22:25,224 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. 312.69/160.50 [2019-03-28 12:22:25,225 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 29565 states and 44290 transitions. 312.69/160.50 [2019-03-28 12:22:25,355 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 29504 312.69/160.50 [2019-03-28 12:22:25,438 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 29565 states to 29565 states and 44290 transitions. 312.69/160.50 [2019-03-28 12:22:25,438 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29565 312.69/160.50 [2019-03-28 12:22:25,460 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29565 312.69/160.50 [2019-03-28 12:22:25,460 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29565 states and 44290 transitions. 312.69/160.50 [2019-03-28 12:22:25,481 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.50 [2019-03-28 12:22:25,482 INFO L706 BuchiCegarLoop]: Abstraction has 29565 states and 44290 transitions. 312.69/160.50 [2019-03-28 12:22:25,496 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29565 states and 44290 transitions. 312.69/160.50 [2019-03-28 12:22:25,668 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29565 to 17053. 312.69/160.50 [2019-03-28 12:22:25,669 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17053 states. 312.69/160.50 [2019-03-28 12:22:25,709 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17053 states to 17053 states and 25538 transitions. 312.69/160.50 [2019-03-28 12:22:25,709 INFO L729 BuchiCegarLoop]: Abstraction has 17053 states and 25538 transitions. 312.69/160.50 [2019-03-28 12:22:25,709 INFO L609 BuchiCegarLoop]: Abstraction has 17053 states and 25538 transitions. 312.69/160.50 [2019-03-28 12:22:25,709 INFO L442 BuchiCegarLoop]: ======== Iteration 38============ 312.69/160.50 [2019-03-28 12:22:25,710 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17053 states and 25538 transitions. 312.69/160.50 [2019-03-28 12:22:25,763 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 16992 312.69/160.50 [2019-03-28 12:22:25,763 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.50 [2019-03-28 12:22:25,764 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.50 [2019-03-28 12:22:25,768 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.50 [2019-03-28 12:22:25,768 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.50 [2019-03-28 12:22:25,769 INFO L794 eck$LassoCheckResult]: Stem: 420345#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 420141#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 420142#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 420211#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 420212#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 420145#L431-1 [2355] L431-1-->L436-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 420146#L436-1 [2735] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 420183#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 420184#L601-1 [3235] L601-1-->L606-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 420187#L606-1 [3236] L606-1-->L611-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 420059#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 420060#L616-1 [3240] L616-1-->L621-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 419940#L621-1 [3242] L621-1-->L626-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 419941#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 420031#L631-1 [3246] L631-1-->L636-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 420032#L636-1 [3248] L636-1-->L641-1: Formula: (> v_~E_2~0_4 0) InVars {~E_2~0=v_~E_2~0_4} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[] 420235#L641-1 [3251] L641-1-->L646-1: Formula: (> v_~E_3~0_4 0) InVars {~E_3~0=v_~E_3~0_4} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[] 420236#L646-1 [3253] L646-1-->L651-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 420174#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 420175#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 420443#L294 [3256] L294-->L294-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 420490#L294-2 [2905] L294-2-->L305: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 420509#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 420510#L745 [2925] L745-->L745-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_6) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} AuxVars[] AssignedVars[] 420525#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 420111#L313 [3262] L313-->L313-2: Formula: (< v_~t1_pc~0_3 1) InVars {~t1_pc~0=v_~t1_pc~0_3} OutVars{~t1_pc~0=v_~t1_pc~0_3} AuxVars[] AssignedVars[] 420112#L313-2 [2314] L313-2-->L324: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 420110#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 419957#L753 [2130] L753-->L753-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} AuxVars[] AssignedVars[] 419958#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 419961#L332 [3268] L332-->L332-2: Formula: (< v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 420151#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 420149#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 420150#L761 [2384] L761-->L761-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} AuxVars[] AssignedVars[] 420170#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 420171#L351 [3274] L351-->L351-2: Formula: (> 1 v_~t3_pc~0_3) InVars {~t3_pc~0=v_~t3_pc~0_3} OutVars{~t3_pc~0=v_~t3_pc~0_3} AuxVars[] AssignedVars[] 420293#L351-2 [2543] L351-2-->L362: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 420294#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 420312#L769 [2585] L769-->L769-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} AuxVars[] AssignedVars[] 420319#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 420320#L370 [3280] L370-->L370-2: Formula: (< v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 420426#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 420424#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 420425#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 420442#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 420023#L389 [3286] L389-->L389-2: Formula: (> 1 v_~t5_pc~0_3) InVars {~t5_pc~0=v_~t5_pc~0_3} OutVars{~t5_pc~0=v_~t5_pc~0_3} AuxVars[] AssignedVars[] 419992#L389-2 [2164] L389-2-->L400: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 419993#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 420022#L785 [2215] L785-->L785-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_6} AuxVars[] AssignedVars[] 420039#L785-2 [3292] L785-2-->L669-1: Formula: (< 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 420040#L669-1 [3294] L669-1-->L674-1: Formula: (< 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 420233#L674-1 [3296] L674-1-->L679-1: Formula: (< 1 v_~T2_E~0_7) InVars {~T2_E~0=v_~T2_E~0_7} OutVars{~T2_E~0=v_~T2_E~0_7} AuxVars[] AssignedVars[] 420234#L679-1 [3298] L679-1-->L684-1: Formula: (> v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 420172#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 420173#L689-1 [3302] L689-1-->L694-1: Formula: (> v_~T5_E~0_7 1) InVars {~T5_E~0=v_~T5_E~0_7} OutVars{~T5_E~0=v_~T5_E~0_7} AuxVars[] AssignedVars[] 420338#L694-1 [3304] L694-1-->L699-1: Formula: (> v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 420080#L699-1 [3306] L699-1-->L704-1: Formula: (> v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 420081#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 419929#L709-1 [3310] L709-1-->L714-1: Formula: (> v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 419930#L714-1 [3313] L714-1-->L719-1: Formula: (> v_~E_4~0_9 1) InVars {~E_4~0=v_~E_4~0_9} OutVars{~E_4~0=v_~E_4~0_9} AuxVars[] AssignedVars[] 420026#L719-1 [3314] L719-1-->L930-1: Formula: (> v_~E_5~0_9 1) InVars {~E_5~0=v_~E_5~0_9} OutVars{~E_5~0=v_~E_5~0_9} AuxVars[] AssignedVars[] 420027#L930-1 312.69/160.50 [2019-03-28 12:22:25,770 INFO L796 eck$LassoCheckResult]: Loop: 420027#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 420033#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 420034#L454 [3316] L454-->L458: Formula: (> v_~m_st~0_8 0) InVars {~m_st~0=v_~m_st~0_8} OutVars{~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[] 420227#L458 [3320] L458-->L462: Formula: (< v_~t1_st~0_8 0) InVars {~t1_st~0=v_~t1_st~0_8} OutVars{~t1_st~0=v_~t1_st~0_8} AuxVars[] AssignedVars[] 420358#L462 [3324] L462-->L466: Formula: (< v_~t2_st~0_8 0) InVars {~t2_st~0=v_~t2_st~0_8} OutVars{~t2_st~0=v_~t2_st~0_8} AuxVars[] AssignedVars[] 420011#L466 [3330] L466-->L470: Formula: (> 0 v_~t3_st~0_8) InVars {~t3_st~0=v_~t3_st~0_8} OutVars{~t3_st~0=v_~t3_st~0_8} AuxVars[] AssignedVars[] 420012#L470 [3336] L470-->L474: Formula: (< v_~t4_st~0_8 0) InVars {~t4_st~0=v_~t4_st~0_8} OutVars{~t4_st~0=v_~t4_st~0_8} AuxVars[] AssignedVars[] 420194#L474 [3344] L474-->L486: Formula: (and (> 0 v_~t5_st~0_8) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_21 0)) InVars {~t5_st~0=v_~t5_st~0_8} OutVars{~t5_st~0=v_~t5_st~0_8, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_21} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 420195#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 424864#L501 [3784] L501-->L601-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 435361#L601-2 [3318] L601-2-->L601-4: Formula: (> v_~M_E~0_10 0) InVars {~M_E~0=v_~M_E~0_10} OutVars{~M_E~0=v_~M_E~0_10} AuxVars[] AssignedVars[] 435355#L601-4 [3322] L601-4-->L606-3: Formula: (> v_~T1_E~0_10 0) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 435356#L606-3 [3326] L606-3-->L611-3: Formula: (< 0 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 420068#L611-3 [3333] L611-3-->L616-3: Formula: (< 0 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 420069#L616-3 [3339] L616-3-->L621-3: Formula: (> v_~T4_E~0_10 0) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 419946#L621-3 [3346] L621-3-->L626-3: Formula: (< 0 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 419947#L626-3 [3354] L626-3-->L631-3: Formula: (< 0 v_~E_M~0_26) InVars {~E_M~0=v_~E_M~0_26} OutVars{~E_M~0=v_~E_M~0_26} AuxVars[] AssignedVars[] 436351#L631-3 [3365] L631-3-->L636-3: Formula: (< 0 v_~E_1~0_26) InVars {~E_1~0=v_~E_1~0_26} OutVars{~E_1~0=v_~E_1~0_26} AuxVars[] AssignedVars[] 420453#L636-3 [3376] L636-3-->L641-3: Formula: (< 0 v_~E_2~0_26) InVars {~E_2~0=v_~E_2~0_26} OutVars{~E_2~0=v_~E_2~0_26} AuxVars[] AssignedVars[] 420454#L641-3 [3388] L641-3-->L646-3: Formula: (< 0 v_~E_3~0_26) InVars {~E_3~0=v_~E_3~0_26} OutVars{~E_3~0=v_~E_3~0_26} AuxVars[] AssignedVars[] 420520#L646-3 [3401] L646-3-->L651-3: Formula: (< 0 v_~E_4~0_26) InVars {~E_4~0=v_~E_4~0_26} OutVars{~E_4~0=v_~E_4~0_26} AuxVars[] AssignedVars[] 420521#L651-3 [3411] L651-3-->L656-3: Formula: (< 0 v_~E_5~0_26) InVars {~E_5~0=v_~E_5~0_26} OutVars{~E_5~0=v_~E_5~0_26} AuxVars[] AssignedVars[] 420436#L656-3 [2767] L656-3-->L294-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_37, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_37, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_22|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_22|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_22|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_37, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_37, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_22|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_22|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_22|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_22|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_37, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_37, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_37} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 420437#L294-21 [3426] L294-21-->L294-23: Formula: (< v_~m_pc~0_22 1) InVars {~m_pc~0=v_~m_pc~0_22} OutVars{~m_pc~0=v_~m_pc~0_22} AuxVars[] AssignedVars[] 420456#L294-23 [2803] L294-23-->L305-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_41 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_41} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 434506#L305-7 [3806] L305-7-->L745-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 434493#L745-21 [2835] L745-21-->L745-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_42) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} AuxVars[] AssignedVars[] 434494#L745-23 [2838] L745-23-->L313-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_43, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 420054#L313-21 [3469] L313-21-->L313-23: Formula: (< v_~t1_pc~0_22 1) InVars {~t1_pc~0=v_~t1_pc~0_22} OutVars{~t1_pc~0=v_~t1_pc~0_22} AuxVars[] AssignedVars[] 420055#L313-23 [2249] L313-23-->L324-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 420058#L324-7 [3813] L324-7-->L753-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 420101#L753-21 [2292] L753-21-->L753-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} AuxVars[] AssignedVars[] 420102#L753-23 [2297] L753-23-->L332-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_22|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 436143#L332-21 [3510] L332-21-->L332-23: Formula: (> 1 v_~t2_pc~0_22) InVars {~t2_pc~0=v_~t2_pc~0_22} OutVars{~t2_pc~0=v_~t2_pc~0_22} AuxVars[] AssignedVars[] 433582#L332-23 [2476] L332-23-->L343-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 436142#L343-7 [3820] L343-7-->L761-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 436141#L761-21 [2490] L761-21-->L761-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_42} AuxVars[] AssignedVars[] 436140#L761-23 [2493] L761-23-->L351-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_22|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 436139#L351-21 [3552] L351-21-->L351-23: Formula: (< v_~t3_pc~0_22 1) InVars {~t3_pc~0=v_~t3_pc~0_22} OutVars{~t3_pc~0=v_~t3_pc~0_22} AuxVars[] AssignedVars[] 427326#L351-23 [2660] L351-23-->L362-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 436138#L362-7 [3827] L362-7-->L769-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 436137#L769-21 [2534] L769-21-->L769-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} AuxVars[] AssignedVars[] 436136#L769-23 [2537] L769-23-->L370-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_43, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 420528#L370-21 [3595] L370-21-->L370-23: Formula: (> 1 v_~t4_pc~0_22) InVars {~t4_pc~0=v_~t4_pc~0_22} OutVars{~t4_pc~0=v_~t4_pc~0_22} AuxVars[] AssignedVars[] 420529#L370-23 [2934] L370-23-->L381-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 420530#L381-7 [3834] L381-7-->L777-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 420385#L777-21 [2705] L777-21-->L777-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} AuxVars[] AssignedVars[] 420386#L777-23 [2708] L777-23-->L389-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_22|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 419959#L389-21 [3637] L389-21-->L389-23: Formula: (< v_~t5_pc~0_22 1) InVars {~t5_pc~0=v_~t5_pc~0_22} OutVars{~t5_pc~0=v_~t5_pc~0_22} AuxVars[] AssignedVars[] 419960#L389-23 [2111] L389-23-->L400-7: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 436584#L400-7 [3837] L400-7-->L785-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 436583#L785-21 [2159] L785-21-->L785-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_42} AuxVars[] AssignedVars[] 436582#L785-23 [3658] L785-23-->L669-3: Formula: (> v_~M_E~0_13 1) InVars {~M_E~0=v_~M_E~0_13} OutVars{~M_E~0=v_~M_E~0_13} AuxVars[] AssignedVars[] 436581#L669-3 [3660] L669-3-->L674-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 436580#L674-3 [3662] L674-3-->L679-3: Formula: (< 1 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 436579#L679-3 [3664] L679-3-->L684-3: Formula: (< 1 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 436578#L684-3 [3666] L684-3-->L689-3: Formula: (> v_~T4_E~0_13 1) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 436577#L689-3 [3668] L689-3-->L694-3: Formula: (< 1 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 436576#L694-3 [3670] L694-3-->L699-3: Formula: (< 1 v_~E_M~0_31) InVars {~E_M~0=v_~E_M~0_31} OutVars{~E_M~0=v_~E_M~0_31} AuxVars[] AssignedVars[] 436575#L699-3 [3673] L699-3-->L704-3: Formula: (< 1 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 436574#L704-3 [3675] L704-3-->L709-3: Formula: (< 1 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 436573#L709-3 [3677] L709-3-->L714-3: Formula: (< 1 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 436572#L714-3 [3678] L714-3-->L719-3: Formula: (< 1 v_~E_4~0_31) InVars {~E_4~0=v_~E_4~0_31} OutVars{~E_4~0=v_~E_4~0_31} AuxVars[] AssignedVars[] 436571#L719-3 [3681] L719-3-->L724-3: Formula: (< 1 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 436570#L724-3 [2818] L724-3-->L454-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_23} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 436564#L454-1 [2466] L454-1-->L486-1: Formula: (and (= 0 v_~m_st~0_20) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26 1)) InVars {~m_st~0=v_~m_st~0_20} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 436562#L486-1 [3838] L486-1-->L949: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret15, ULTIMATE.start_start_simulation_~tmp~3] 436558#L949 [3688] L949-->L949-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_1) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} AuxVars[] AssignedVars[] 436534#L949-1 [2479] L949-1-->L454-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_1} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 436531#L454-2 [2438] L454-2-->L486-2: Formula: (and (= v_~m_st~0_2 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4 1)) InVars {~m_st~0=v_~m_st~0_2} OutVars{~m_st~0=v_~m_st~0_2, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 436011#L486-2 [3840] L486-2-->L904: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 436010#L904 [2393] L904-->L911: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 436009#L911 [3851] L911-->L930-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_6|, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 420027#L930-1 312.69/160.50 [2019-03-28 12:22:25,770 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.50 [2019-03-28 12:22:25,770 INFO L82 PathProgramCache]: Analyzing trace with hash -781340427, now seen corresponding path program 2 times 312.69/160.50 [2019-03-28 12:22:25,770 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.50 [2019-03-28 12:22:25,770 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.50 [2019-03-28 12:22:25,771 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:25,771 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:25,771 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:25,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.50 [2019-03-28 12:22:25,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.50 [2019-03-28 12:22:25,791 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.50 [2019-03-28 12:22:25,791 INFO L82 PathProgramCache]: Analyzing trace with hash 1220798290, now seen corresponding path program 1 times 312.69/160.50 [2019-03-28 12:22:25,791 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.50 [2019-03-28 12:22:25,791 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.50 [2019-03-28 12:22:25,792 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:25,792 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:25,792 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:25,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.50 [2019-03-28 12:22:25,815 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.50 [2019-03-28 12:22:25,815 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.50 [2019-03-28 12:22:25,815 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 312.69/160.50 [2019-03-28 12:22:25,816 INFO L811 eck$LassoCheckResult]: loop already infeasible 312.69/160.50 [2019-03-28 12:22:25,816 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 312.69/160.50 [2019-03-28 12:22:25,816 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 312.69/160.50 [2019-03-28 12:22:25,816 INFO L87 Difference]: Start difference. First operand 17053 states and 25538 transitions. cyclomatic complexity: 8486 Second operand 3 states. 312.69/160.50 [2019-03-28 12:22:26,422 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.50 [2019-03-28 12:22:26,422 INFO L93 Difference]: Finished difference Result 32493 states and 48162 transitions. 312.69/160.50 [2019-03-28 12:22:26,423 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 312.69/160.50 [2019-03-28 12:22:26,423 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 32493 states and 48162 transitions. 312.69/160.50 [2019-03-28 12:22:26,564 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 32432 312.69/160.50 [2019-03-28 12:22:26,654 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 32493 states to 32493 states and 48162 transitions. 312.69/160.50 [2019-03-28 12:22:26,654 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 32493 312.69/160.50 [2019-03-28 12:22:26,678 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 32493 312.69/160.50 [2019-03-28 12:22:26,678 INFO L73 IsDeterministic]: Start isDeterministic. Operand 32493 states and 48162 transitions. 312.69/160.50 [2019-03-28 12:22:26,700 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.50 [2019-03-28 12:22:26,700 INFO L706 BuchiCegarLoop]: Abstraction has 32493 states and 48162 transitions. 312.69/160.50 [2019-03-28 12:22:26,714 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32493 states and 48162 transitions. 312.69/160.50 [2019-03-28 12:22:26,958 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32493 to 32493. 312.69/160.50 [2019-03-28 12:22:26,958 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 32493 states. 312.69/160.50 [2019-03-28 12:22:27,018 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32493 states to 32493 states and 48162 transitions. 312.69/160.50 [2019-03-28 12:22:27,018 INFO L729 BuchiCegarLoop]: Abstraction has 32493 states and 48162 transitions. 312.69/160.50 [2019-03-28 12:22:27,018 INFO L609 BuchiCegarLoop]: Abstraction has 32493 states and 48162 transitions. 312.69/160.50 [2019-03-28 12:22:27,019 INFO L442 BuchiCegarLoop]: ======== Iteration 39============ 312.69/160.50 [2019-03-28 12:22:27,019 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 32493 states and 48162 transitions. 312.69/160.50 [2019-03-28 12:22:27,135 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 32432 312.69/160.50 [2019-03-28 12:22:27,136 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.50 [2019-03-28 12:22:27,136 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.50 [2019-03-28 12:22:27,140 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.50 [2019-03-28 12:22:27,140 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.50 [2019-03-28 12:22:27,141 INFO L794 eck$LassoCheckResult]: Stem: 469879#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 469684#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 469685#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 469754#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 469755#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 469688#L431-1 [2355] L431-1-->L436-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 469689#L436-1 [2735] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 469729#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 469730#L601-1 [3235] L601-1-->L606-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 469732#L606-1 [3236] L606-1-->L611-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 469599#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 469600#L616-1 [3240] L616-1-->L621-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 469491#L621-1 [3242] L621-1-->L626-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 469492#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 469571#L631-1 [3246] L631-1-->L636-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 469572#L636-1 [3248] L636-1-->L641-1: Formula: (> v_~E_2~0_4 0) InVars {~E_2~0=v_~E_2~0_4} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[] 469779#L641-1 [3251] L641-1-->L646-1: Formula: (> v_~E_3~0_4 0) InVars {~E_3~0=v_~E_3~0_4} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[] 469780#L646-1 [3253] L646-1-->L651-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 469720#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 469721#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 469957#L294 [3256] L294-->L294-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 470001#L294-2 [2905] L294-2-->L305: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 470019#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 470020#L745 [2925] L745-->L745-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_6) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} AuxVars[] AssignedVars[] 470034#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 469651#L313 [3262] L313-->L313-2: Formula: (< v_~t1_pc~0_3 1) InVars {~t1_pc~0=v_~t1_pc~0_3} OutVars{~t1_pc~0=v_~t1_pc~0_3} AuxVars[] AssignedVars[] 469652#L313-2 [2314] L313-2-->L324: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 469650#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 469506#L753 [2130] L753-->L753-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} AuxVars[] AssignedVars[] 469507#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 469510#L332 [3268] L332-->L332-2: Formula: (< v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 469694#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 469692#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 469693#L761 [2384] L761-->L761-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} AuxVars[] AssignedVars[] 469715#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 469716#L351 [3274] L351-->L351-2: Formula: (> 1 v_~t3_pc~0_3) InVars {~t3_pc~0=v_~t3_pc~0_3} OutVars{~t3_pc~0=v_~t3_pc~0_3} AuxVars[] AssignedVars[] 469831#L351-2 [2543] L351-2-->L362: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 469832#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 469848#L769 [2585] L769-->L769-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} AuxVars[] AssignedVars[] 469852#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 469853#L370 [3280] L370-->L370-2: Formula: (< v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 469942#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 469940#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 469941#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 469956#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 469563#L389 [3286] L389-->L389-2: Formula: (> 1 v_~t5_pc~0_3) InVars {~t5_pc~0=v_~t5_pc~0_3} OutVars{~t5_pc~0=v_~t5_pc~0_3} AuxVars[] AssignedVars[] 469536#L389-2 [2164] L389-2-->L400: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 469537#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 469562#L785 [2215] L785-->L785-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_6} AuxVars[] AssignedVars[] 469579#L785-2 [3292] L785-2-->L669-1: Formula: (< 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 469580#L669-1 [3294] L669-1-->L674-1: Formula: (< 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 469777#L674-1 [3296] L674-1-->L679-1: Formula: (< 1 v_~T2_E~0_7) InVars {~T2_E~0=v_~T2_E~0_7} OutVars{~T2_E~0=v_~T2_E~0_7} AuxVars[] AssignedVars[] 469778#L679-1 [3298] L679-1-->L684-1: Formula: (> v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 469718#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 469719#L689-1 [3302] L689-1-->L694-1: Formula: (> v_~T5_E~0_7 1) InVars {~T5_E~0=v_~T5_E~0_7} OutVars{~T5_E~0=v_~T5_E~0_7} AuxVars[] AssignedVars[] 469871#L694-1 [3304] L694-1-->L699-1: Formula: (> v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 469620#L699-1 [3306] L699-1-->L704-1: Formula: (> v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 469621#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 469481#L709-1 [3310] L709-1-->L714-1: Formula: (> v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 469482#L714-1 [3313] L714-1-->L719-1: Formula: (> v_~E_4~0_9 1) InVars {~E_4~0=v_~E_4~0_9} OutVars{~E_4~0=v_~E_4~0_9} AuxVars[] AssignedVars[] 469565#L719-1 [3314] L719-1-->L930-1: Formula: (> v_~E_5~0_9 1) InVars {~E_5~0=v_~E_5~0_9} OutVars{~E_5~0=v_~E_5~0_9} AuxVars[] AssignedVars[] 469566#L930-1 312.69/160.50 [2019-03-28 12:22:27,143 INFO L796 eck$LassoCheckResult]: Loop: 469566#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 474320#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 486328#L454 [3317] L454-->L458: Formula: (< v_~m_st~0_8 0) InVars {~m_st~0=v_~m_st~0_8} OutVars{~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[] 486325#L458 [3320] L458-->L462: Formula: (< v_~t1_st~0_8 0) InVars {~t1_st~0=v_~t1_st~0_8} OutVars{~t1_st~0=v_~t1_st~0_8} AuxVars[] AssignedVars[] 486326#L462 [3324] L462-->L466: Formula: (< v_~t2_st~0_8 0) InVars {~t2_st~0=v_~t2_st~0_8} OutVars{~t2_st~0=v_~t2_st~0_8} AuxVars[] AssignedVars[] 486327#L466 [3330] L466-->L470: Formula: (> 0 v_~t3_st~0_8) InVars {~t3_st~0=v_~t3_st~0_8} OutVars{~t3_st~0=v_~t3_st~0_8} AuxVars[] AssignedVars[] 486324#L470 [3336] L470-->L474: Formula: (< v_~t4_st~0_8 0) InVars {~t4_st~0=v_~t4_st~0_8} OutVars{~t4_st~0=v_~t4_st~0_8} AuxVars[] AssignedVars[] 486322#L474 [3344] L474-->L486: Formula: (and (> 0 v_~t5_st~0_8) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_21 0)) InVars {~t5_st~0=v_~t5_st~0_8} OutVars{~t5_st~0=v_~t5_st~0_8, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_21} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 486323#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 493836#L501 [3784] L501-->L601-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 493833#L601-2 [3318] L601-2-->L601-4: Formula: (> v_~M_E~0_10 0) InVars {~M_E~0=v_~M_E~0_10} OutVars{~M_E~0=v_~M_E~0_10} AuxVars[] AssignedVars[] 493830#L601-4 [3322] L601-4-->L606-3: Formula: (> v_~T1_E~0_10 0) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 493788#L606-3 [3326] L606-3-->L611-3: Formula: (< 0 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 493773#L611-3 [3333] L611-3-->L616-3: Formula: (< 0 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 493770#L616-3 [3339] L616-3-->L621-3: Formula: (> v_~T4_E~0_10 0) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 493763#L621-3 [3346] L621-3-->L626-3: Formula: (< 0 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 493758#L626-3 [3354] L626-3-->L631-3: Formula: (< 0 v_~E_M~0_26) InVars {~E_M~0=v_~E_M~0_26} OutVars{~E_M~0=v_~E_M~0_26} AuxVars[] AssignedVars[] 493753#L631-3 [3365] L631-3-->L636-3: Formula: (< 0 v_~E_1~0_26) InVars {~E_1~0=v_~E_1~0_26} OutVars{~E_1~0=v_~E_1~0_26} AuxVars[] AssignedVars[] 493749#L636-3 [3376] L636-3-->L641-3: Formula: (< 0 v_~E_2~0_26) InVars {~E_2~0=v_~E_2~0_26} OutVars{~E_2~0=v_~E_2~0_26} AuxVars[] AssignedVars[] 493744#L641-3 [3388] L641-3-->L646-3: Formula: (< 0 v_~E_3~0_26) InVars {~E_3~0=v_~E_3~0_26} OutVars{~E_3~0=v_~E_3~0_26} AuxVars[] AssignedVars[] 493736#L646-3 [3401] L646-3-->L651-3: Formula: (< 0 v_~E_4~0_26) InVars {~E_4~0=v_~E_4~0_26} OutVars{~E_4~0=v_~E_4~0_26} AuxVars[] AssignedVars[] 493732#L651-3 [3411] L651-3-->L656-3: Formula: (< 0 v_~E_5~0_26) InVars {~E_5~0=v_~E_5~0_26} OutVars{~E_5~0=v_~E_5~0_26} AuxVars[] AssignedVars[] 493728#L656-3 [2767] L656-3-->L294-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_37, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_37, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_22|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_22|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_22|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_37, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_37, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_22|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_22|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_22|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_22|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_37, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_37, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_37} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 493725#L294-21 [3426] L294-21-->L294-23: Formula: (< v_~m_pc~0_22 1) InVars {~m_pc~0=v_~m_pc~0_22} OutVars{~m_pc~0=v_~m_pc~0_22} AuxVars[] AssignedVars[] 493163#L294-23 [2803] L294-23-->L305-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_41 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_41} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 493719#L305-7 [3806] L305-7-->L745-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 493716#L745-21 [2835] L745-21-->L745-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_42) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_42} AuxVars[] AssignedVars[] 493712#L745-23 [2838] L745-23-->L313-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_43, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 493652#L313-21 [3469] L313-21-->L313-23: Formula: (< v_~t1_pc~0_22 1) InVars {~t1_pc~0=v_~t1_pc~0_22} OutVars{~t1_pc~0=v_~t1_pc~0_22} AuxVars[] AssignedVars[] 493651#L313-23 [2249] L313-23-->L324-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 493350#L324-7 [3813] L324-7-->L753-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 493330#L753-21 [2292] L753-21-->L753-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_42} AuxVars[] AssignedVars[] 493331#L753-23 [2297] L753-23-->L332-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_22|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 492585#L332-21 [3510] L332-21-->L332-23: Formula: (> 1 v_~t2_pc~0_22) InVars {~t2_pc~0=v_~t2_pc~0_22} OutVars{~t2_pc~0=v_~t2_pc~0_22} AuxVars[] AssignedVars[] 492583#L332-23 [2476] L332-23-->L343-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 492580#L343-7 [3820] L343-7-->L761-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 492577#L761-21 [2490] L761-21-->L761-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_42} AuxVars[] AssignedVars[] 492574#L761-23 [2493] L761-23-->L351-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_22|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 492571#L351-21 [3552] L351-21-->L351-23: Formula: (< v_~t3_pc~0_22 1) InVars {~t3_pc~0=v_~t3_pc~0_22} OutVars{~t3_pc~0=v_~t3_pc~0_22} AuxVars[] AssignedVars[] 486471#L351-23 [2660] L351-23-->L362-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 486472#L362-7 [3827] L362-7-->L769-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 486463#L769-21 [2534] L769-21-->L769-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_42} AuxVars[] AssignedVars[] 486464#L769-23 [2537] L769-23-->L370-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_43, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_22|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 486445#L370-21 [3595] L370-21-->L370-23: Formula: (> 1 v_~t4_pc~0_22) InVars {~t4_pc~0=v_~t4_pc~0_22} OutVars{~t4_pc~0=v_~t4_pc~0_22} AuxVars[] AssignedVars[] 486443#L370-23 [2934] L370-23-->L381-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 486441#L381-7 [3834] L381-7-->L777-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 486439#L777-21 [2705] L777-21-->L777-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_42} AuxVars[] AssignedVars[] 486437#L777-23 [2708] L777-23-->L389-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_22|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_43} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 486434#L389-21 [3637] L389-21-->L389-23: Formula: (< v_~t5_pc~0_22 1) InVars {~t5_pc~0=v_~t5_pc~0_22} OutVars{~t5_pc~0=v_~t5_pc~0_22} AuxVars[] AssignedVars[] 474316#L389-23 [2111] L389-23-->L400-7: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_47 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_47} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 486429#L400-7 [3837] L400-7-->L785-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 486426#L785-21 [2159] L785-21-->L785-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_42 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_42} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_42} AuxVars[] AssignedVars[] 486423#L785-23 [3658] L785-23-->L669-3: Formula: (> v_~M_E~0_13 1) InVars {~M_E~0=v_~M_E~0_13} OutVars{~M_E~0=v_~M_E~0_13} AuxVars[] AssignedVars[] 486420#L669-3 [3660] L669-3-->L674-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 486418#L674-3 [3662] L674-3-->L679-3: Formula: (< 1 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 486415#L679-3 [3664] L679-3-->L684-3: Formula: (< 1 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 486410#L684-3 [3666] L684-3-->L689-3: Formula: (> v_~T4_E~0_13 1) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 486407#L689-3 [3668] L689-3-->L694-3: Formula: (< 1 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 486404#L694-3 [3670] L694-3-->L699-3: Formula: (< 1 v_~E_M~0_31) InVars {~E_M~0=v_~E_M~0_31} OutVars{~E_M~0=v_~E_M~0_31} AuxVars[] AssignedVars[] 486401#L699-3 [3673] L699-3-->L704-3: Formula: (< 1 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 486398#L704-3 [3675] L704-3-->L709-3: Formula: (< 1 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 486393#L709-3 [3677] L709-3-->L714-3: Formula: (< 1 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 486390#L714-3 [3678] L714-3-->L719-3: Formula: (< 1 v_~E_4~0_31) InVars {~E_4~0=v_~E_4~0_31} OutVars{~E_4~0=v_~E_4~0_31} AuxVars[] AssignedVars[] 486385#L719-3 [3681] L719-3-->L724-3: Formula: (< 1 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 486381#L724-3 [2818] L724-3-->L454-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_23} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 486370#L454-1 [2466] L454-1-->L486-1: Formula: (and (= 0 v_~m_st~0_20) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26 1)) InVars {~m_st~0=v_~m_st~0_20} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_26} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 486364#L486-1 [3838] L486-1-->L949: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_36} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret15, ULTIMATE.start_start_simulation_~tmp~3] 486359#L949 [3688] L949-->L949-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_1) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_1} AuxVars[] AssignedVars[] 486355#L949-1 [2479] L949-1-->L454-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_1} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 486348#L454-2 [2438] L454-2-->L486-2: Formula: (and (= v_~m_st~0_2 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4 1)) InVars {~m_st~0=v_~m_st~0_2} OutVars{~m_st~0=v_~m_st~0_2, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 486340#L486-2 [3840] L486-2-->L904: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} OutVars{ULTIMATE.start_stop_simulation_#t~ret14=|v_ULTIMATE.start_stop_simulation_#t~ret14_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_37} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret14, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 486335#L904 [2393] L904-->L911: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 486329#L911 [3851] L911-->L930-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_6|, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 469566#L930-1 312.69/160.50 [2019-03-28 12:22:27,143 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.50 [2019-03-28 12:22:27,143 INFO L82 PathProgramCache]: Analyzing trace with hash -781340427, now seen corresponding path program 3 times 312.69/160.50 [2019-03-28 12:22:27,143 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.50 [2019-03-28 12:22:27,143 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.50 [2019-03-28 12:22:27,144 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:27,144 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:27,144 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:27,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.50 [2019-03-28 12:22:27,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.50 [2019-03-28 12:22:27,163 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.50 [2019-03-28 12:22:27,164 INFO L82 PathProgramCache]: Analyzing trace with hash 737122963, now seen corresponding path program 1 times 312.69/160.50 [2019-03-28 12:22:27,164 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.50 [2019-03-28 12:22:27,164 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.50 [2019-03-28 12:22:27,164 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:27,165 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:27,165 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.50 [2019-03-28 12:22:27,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.50 [2019-03-28 12:22:27,199 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.50 [2019-03-28 12:22:27,199 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.50 [2019-03-28 12:22:27,199 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 312.69/160.50 [2019-03-28 12:22:27,199 INFO L811 eck$LassoCheckResult]: loop already infeasible 312.69/160.50 [2019-03-28 12:22:27,200 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 312.69/160.50 [2019-03-28 12:22:27,200 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 312.69/160.50 [2019-03-28 12:22:27,201 INFO L87 Difference]: Start difference. First operand 32493 states and 48162 transitions. cyclomatic complexity: 15671 Second operand 3 states. 312.69/160.50 [2019-03-28 12:22:28,358 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.50 [2019-03-28 12:22:28,358 INFO L93 Difference]: Finished difference Result 39711 states and 58873 transitions. 312.69/160.50 [2019-03-28 12:22:28,358 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 312.69/160.50 [2019-03-28 12:22:28,359 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 39711 states and 58873 transitions. 312.69/160.50 [2019-03-28 12:22:28,519 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 39635 312.69/160.50 [2019-03-28 12:22:28,624 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 39711 states to 39711 states and 58873 transitions. 312.69/160.50 [2019-03-28 12:22:28,624 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 39711 312.69/160.50 [2019-03-28 12:22:28,652 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 39711 312.69/160.50 [2019-03-28 12:22:28,652 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39711 states and 58873 transitions. 312.69/160.50 [2019-03-28 12:22:28,678 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.50 [2019-03-28 12:22:28,678 INFO L706 BuchiCegarLoop]: Abstraction has 39711 states and 58873 transitions. 312.69/160.50 [2019-03-28 12:22:28,695 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39711 states and 58873 transitions. 312.69/160.50 [2019-03-28 12:22:28,983 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39711 to 39711. 312.69/160.50 [2019-03-28 12:22:28,983 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39711 states. 312.69/160.50 [2019-03-28 12:22:29,054 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39711 states to 39711 states and 58873 transitions. 312.69/160.50 [2019-03-28 12:22:29,054 INFO L729 BuchiCegarLoop]: Abstraction has 39711 states and 58873 transitions. 312.69/160.50 [2019-03-28 12:22:29,054 INFO L609 BuchiCegarLoop]: Abstraction has 39711 states and 58873 transitions. 312.69/160.50 [2019-03-28 12:22:29,054 INFO L442 BuchiCegarLoop]: ======== Iteration 40============ 312.69/160.50 [2019-03-28 12:22:29,054 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39711 states and 58873 transitions. 312.69/160.50 [2019-03-28 12:22:29,186 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 39635 312.69/160.50 [2019-03-28 12:22:29,186 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.50 [2019-03-28 12:22:29,186 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.50 [2019-03-28 12:22:29,187 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.50 [2019-03-28 12:22:29,187 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.50 [2019-03-28 12:22:29,188 INFO L794 eck$LassoCheckResult]: Stem: 542091#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 541896#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 541897#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 541963#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 541964#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 541900#L431-1 [2355] L431-1-->L436-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 541901#L436-1 [2735] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 541939#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 541940#L601-1 [3235] L601-1-->L606-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 541942#L606-1 [3236] L606-1-->L611-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 541814#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 541815#L616-1 [3240] L616-1-->L621-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 541701#L621-1 [3242] L621-1-->L626-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 541702#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 541785#L631-1 [3246] L631-1-->L636-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 541786#L636-1 [3248] L636-1-->L641-1: Formula: (> v_~E_2~0_4 0) InVars {~E_2~0=v_~E_2~0_4} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[] 541991#L641-1 [3251] L641-1-->L646-1: Formula: (> v_~E_3~0_4 0) InVars {~E_3~0=v_~E_3~0_4} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[] 541992#L646-1 [3253] L646-1-->L651-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 541930#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 541931#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 542171#L294 [3256] L294-->L294-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 542206#L294-2 [2905] L294-2-->L305: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 542224#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 542225#L745 [2925] L745-->L745-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_6) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} AuxVars[] AssignedVars[] 542237#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 541864#L313 [3262] L313-->L313-2: Formula: (< v_~t1_pc~0_3 1) InVars {~t1_pc~0=v_~t1_pc~0_3} OutVars{~t1_pc~0=v_~t1_pc~0_3} AuxVars[] AssignedVars[] 541865#L313-2 [2314] L313-2-->L324: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 541863#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 541718#L753 [2130] L753-->L753-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} AuxVars[] AssignedVars[] 541719#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 541721#L332 [3268] L332-->L332-2: Formula: (< v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 541906#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 541904#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 541905#L761 [2384] L761-->L761-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} AuxVars[] AssignedVars[] 541926#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 541927#L351 [3274] L351-->L351-2: Formula: (> 1 v_~t3_pc~0_3) InVars {~t3_pc~0=v_~t3_pc~0_3} OutVars{~t3_pc~0=v_~t3_pc~0_3} AuxVars[] AssignedVars[] 542041#L351-2 [2543] L351-2-->L362: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 542042#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 542059#L769 [2585] L769-->L769-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} AuxVars[] AssignedVars[] 542064#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 542065#L370 [3280] L370-->L370-2: Formula: (< v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 542157#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 542155#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 542156#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 542169#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 541777#L389 [3286] L389-->L389-2: Formula: (> 1 v_~t5_pc~0_3) InVars {~t5_pc~0=v_~t5_pc~0_3} OutVars{~t5_pc~0=v_~t5_pc~0_3} AuxVars[] AssignedVars[] 541747#L389-2 [2164] L389-2-->L400: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 541748#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 541776#L785 [2215] L785-->L785-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_6} AuxVars[] AssignedVars[] 541793#L785-2 [3292] L785-2-->L669-1: Formula: (< 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 541794#L669-1 [3294] L669-1-->L674-1: Formula: (< 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 541989#L674-1 [3296] L674-1-->L679-1: Formula: (< 1 v_~T2_E~0_7) InVars {~T2_E~0=v_~T2_E~0_7} OutVars{~T2_E~0=v_~T2_E~0_7} AuxVars[] AssignedVars[] 541990#L679-1 [3298] L679-1-->L684-1: Formula: (> v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 541928#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 541929#L689-1 [3302] L689-1-->L694-1: Formula: (> v_~T5_E~0_7 1) InVars {~T5_E~0=v_~T5_E~0_7} OutVars{~T5_E~0=v_~T5_E~0_7} AuxVars[] AssignedVars[] 542083#L694-1 [3304] L694-1-->L699-1: Formula: (> v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 541835#L699-1 [3306] L699-1-->L704-1: Formula: (> v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 541836#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 541691#L709-1 [3310] L709-1-->L714-1: Formula: (> v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 541692#L714-1 [3313] L714-1-->L719-1: Formula: (> v_~E_4~0_9 1) InVars {~E_4~0=v_~E_4~0_9} OutVars{~E_4~0=v_~E_4~0_9} AuxVars[] AssignedVars[] 541779#L719-1 [3314] L719-1-->L930-1: Formula: (> v_~E_5~0_9 1) InVars {~E_5~0=v_~E_5~0_9} OutVars{~E_5~0=v_~E_5~0_9} AuxVars[] AssignedVars[] 541780#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 544699#L576 312.69/160.51 [2019-03-28 12:22:29,188 INFO L796 eck$LassoCheckResult]: Loop: 544699#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 544695#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 544694#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 544692#L501 [3328] L501-->L501-1: Formula: (> v_ULTIMATE.start_eval_~tmp~0_4 0) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} OutVars{ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} AuxVars[] AssignedVars[] 544688#L501-1 [2236] L501-1-->L509: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_2 |v_ULTIMATE.start_eval_#t~nondet2_3|) (= v_~m_st~0_9 0)) InVars {~m_st~0=v_~m_st~0_9, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_3|} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_2|, ~m_st~0=v_~m_st~0_9, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_1~0] 544685#L509 [2460] L509-->L506: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} AuxVars[] AssignedVars[] 544682#L506 [3342] L506-->L520: Formula: (> 0 v_~t1_st~0_14) InVars {~t1_st~0=v_~t1_st~0_14} OutVars{~t1_st~0=v_~t1_st~0_14} AuxVars[] AssignedVars[] 544679#L520 [3352] L520-->L534: Formula: (< v_~t2_st~0_15 0) InVars {~t2_st~0=v_~t2_st~0_15} OutVars{~t2_st~0=v_~t2_st~0_15} AuxVars[] AssignedVars[] 544456#L534 [3362] L534-->L548: Formula: (< 0 v_~t3_st~0_16) InVars {~t3_st~0=v_~t3_st~0_16} OutVars{~t3_st~0=v_~t3_st~0_16} AuxVars[] AssignedVars[] 544673#L548 [3374] L548-->L562: Formula: (> 0 v_~t4_st~0_17) InVars {~t4_st~0=v_~t4_st~0_17} OutVars{~t4_st~0=v_~t4_st~0_17} AuxVars[] AssignedVars[] 544671#L562 [3386] L562-->L576: Formula: (< v_~t5_st~0_18 0) InVars {~t5_st~0=v_~t5_st~0_18} OutVars{~t5_st~0=v_~t5_st~0_18} AuxVars[] AssignedVars[] 544699#L576 312.69/160.51 [2019-03-28 12:22:29,188 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.51 [2019-03-28 12:22:29,188 INFO L82 PathProgramCache]: Analyzing trace with hash 1548254319, now seen corresponding path program 1 times 312.69/160.51 [2019-03-28 12:22:29,188 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.51 [2019-03-28 12:22:29,189 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.51 [2019-03-28 12:22:29,189 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:29,189 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:29,190 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:29,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:22:29,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:22:29,207 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.51 [2019-03-28 12:22:29,207 INFO L82 PathProgramCache]: Analyzing trace with hash 1966145263, now seen corresponding path program 1 times 312.69/160.51 [2019-03-28 12:22:29,207 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.51 [2019-03-28 12:22:29,207 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.51 [2019-03-28 12:22:29,208 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:29,208 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:29,208 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:29,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:22:29,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:22:29,213 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.51 [2019-03-28 12:22:29,214 INFO L82 PathProgramCache]: Analyzing trace with hash 1985483201, now seen corresponding path program 1 times 312.69/160.51 [2019-03-28 12:22:29,214 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.51 [2019-03-28 12:22:29,214 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.51 [2019-03-28 12:22:29,215 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:29,215 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:29,215 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:29,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.51 [2019-03-28 12:22:29,237 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.51 [2019-03-28 12:22:29,237 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.51 [2019-03-28 12:22:29,237 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 312.69/160.51 [2019-03-28 12:22:29,299 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 312.69/160.51 [2019-03-28 12:22:29,299 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 312.69/160.51 [2019-03-28 12:22:29,299 INFO L87 Difference]: Start difference. First operand 39711 states and 58873 transitions. cyclomatic complexity: 19166 Second operand 3 states. 312.69/160.51 [2019-03-28 12:22:29,736 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.51 [2019-03-28 12:22:29,737 INFO L93 Difference]: Finished difference Result 39711 states and 58298 transitions. 312.69/160.51 [2019-03-28 12:22:29,737 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 312.69/160.51 [2019-03-28 12:22:29,737 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 39711 states and 58298 transitions. 312.69/160.51 [2019-03-28 12:22:29,906 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 39635 312.69/160.51 [2019-03-28 12:22:30,016 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 39711 states to 39711 states and 58298 transitions. 312.69/160.51 [2019-03-28 12:22:30,016 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 39711 312.69/160.51 [2019-03-28 12:22:30,047 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 39711 312.69/160.51 [2019-03-28 12:22:30,047 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39711 states and 58298 transitions. 312.69/160.51 [2019-03-28 12:22:30,076 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.51 [2019-03-28 12:22:30,076 INFO L706 BuchiCegarLoop]: Abstraction has 39711 states and 58298 transitions. 312.69/160.51 [2019-03-28 12:22:30,096 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39711 states and 58298 transitions. 312.69/160.51 [2019-03-28 12:22:30,650 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39711 to 39711. 312.69/160.51 [2019-03-28 12:22:30,650 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39711 states. 312.69/160.51 [2019-03-28 12:22:30,723 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39711 states to 39711 states and 58298 transitions. 312.69/160.51 [2019-03-28 12:22:30,724 INFO L729 BuchiCegarLoop]: Abstraction has 39711 states and 58298 transitions. 312.69/160.51 [2019-03-28 12:22:30,735 INFO L609 BuchiCegarLoop]: Abstraction has 39711 states and 58298 transitions. 312.69/160.51 [2019-03-28 12:22:30,735 INFO L442 BuchiCegarLoop]: ======== Iteration 41============ 312.69/160.51 [2019-03-28 12:22:30,735 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39711 states and 58298 transitions. 312.69/160.51 [2019-03-28 12:22:30,866 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 39635 312.69/160.51 [2019-03-28 12:22:30,867 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.51 [2019-03-28 12:22:30,867 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.51 [2019-03-28 12:22:30,867 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.51 [2019-03-28 12:22:30,868 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.51 [2019-03-28 12:22:30,869 INFO L794 eck$LassoCheckResult]: Stem: 621535#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 621318#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 621319#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 621391#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 621392#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 621322#L431-1 [2355] L431-1-->L436-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 621323#L436-1 [2735] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 621366#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 621367#L601-1 [3235] L601-1-->L606-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 621369#L606-1 [3236] L606-1-->L611-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 621243#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 621244#L616-1 [3240] L616-1-->L621-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 621131#L621-1 [3242] L621-1-->L626-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 621132#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 621214#L631-1 [3246] L631-1-->L636-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 621215#L636-1 [3248] L636-1-->L641-1: Formula: (> v_~E_2~0_4 0) InVars {~E_2~0=v_~E_2~0_4} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[] 621417#L641-1 [3251] L641-1-->L646-1: Formula: (> v_~E_3~0_4 0) InVars {~E_3~0=v_~E_3~0_4} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[] 621418#L646-1 [3253] L646-1-->L651-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 621357#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 621358#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 621614#L294 [3256] L294-->L294-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 621655#L294-2 [2905] L294-2-->L305: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 621676#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 621677#L745 [2925] L745-->L745-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_6) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} AuxVars[] AssignedVars[] 621688#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 621291#L313 [3262] L313-->L313-2: Formula: (< v_~t1_pc~0_3 1) InVars {~t1_pc~0=v_~t1_pc~0_3} OutVars{~t1_pc~0=v_~t1_pc~0_3} AuxVars[] AssignedVars[] 621292#L313-2 [2314] L313-2-->L324: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 621290#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 621148#L753 [2130] L753-->L753-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} AuxVars[] AssignedVars[] 621149#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 621151#L332 [3268] L332-->L332-2: Formula: (< v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 621328#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 621326#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 621327#L761 [2384] L761-->L761-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} AuxVars[] AssignedVars[] 621351#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 621352#L351 [3274] L351-->L351-2: Formula: (> 1 v_~t3_pc~0_3) InVars {~t3_pc~0=v_~t3_pc~0_3} OutVars{~t3_pc~0=v_~t3_pc~0_3} AuxVars[] AssignedVars[] 621478#L351-2 [2543] L351-2-->L362: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 621479#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 621501#L769 [2585] L769-->L769-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} AuxVars[] AssignedVars[] 621507#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 621508#L370 [3280] L370-->L370-2: Formula: (< v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 621599#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 621597#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 621598#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 621613#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 621206#L389 [3286] L389-->L389-2: Formula: (> 1 v_~t5_pc~0_3) InVars {~t5_pc~0=v_~t5_pc~0_3} OutVars{~t5_pc~0=v_~t5_pc~0_3} AuxVars[] AssignedVars[] 621178#L389-2 [2164] L389-2-->L400: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 621179#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 621205#L785 [2215] L785-->L785-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_6} AuxVars[] AssignedVars[] 621222#L785-2 [3292] L785-2-->L669-1: Formula: (< 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 621223#L669-1 [3294] L669-1-->L674-1: Formula: (< 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 621415#L674-1 [3296] L674-1-->L679-1: Formula: (< 1 v_~T2_E~0_7) InVars {~T2_E~0=v_~T2_E~0_7} OutVars{~T2_E~0=v_~T2_E~0_7} AuxVars[] AssignedVars[] 621416#L679-1 [3298] L679-1-->L684-1: Formula: (> v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 621355#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 621356#L689-1 [3302] L689-1-->L694-1: Formula: (> v_~T5_E~0_7 1) InVars {~T5_E~0=v_~T5_E~0_7} OutVars{~T5_E~0=v_~T5_E~0_7} AuxVars[] AssignedVars[] 621526#L694-1 [3304] L694-1-->L699-1: Formula: (> v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 621262#L699-1 [3306] L699-1-->L704-1: Formula: (> v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 621263#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 621121#L709-1 [3310] L709-1-->L714-1: Formula: (> v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 621122#L714-1 [3313] L714-1-->L719-1: Formula: (> v_~E_4~0_9 1) InVars {~E_4~0=v_~E_4~0_9} OutVars{~E_4~0=v_~E_4~0_9} AuxVars[] AssignedVars[] 621209#L719-1 [3314] L719-1-->L930-1: Formula: (> v_~E_5~0_9 1) InVars {~E_5~0=v_~E_5~0_9} OutVars{~E_5~0=v_~E_5~0_9} AuxVars[] AssignedVars[] 621210#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 622727#L576 312.69/160.51 [2019-03-28 12:22:30,869 INFO L796 eck$LassoCheckResult]: Loop: 622727#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 622723#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 622721#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 622719#L501 [3328] L501-->L501-1: Formula: (> v_ULTIMATE.start_eval_~tmp~0_4 0) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} OutVars{ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} AuxVars[] AssignedVars[] 622715#L501-1 [2236] L501-1-->L509: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_2 |v_ULTIMATE.start_eval_#t~nondet2_3|) (= v_~m_st~0_9 0)) InVars {~m_st~0=v_~m_st~0_9, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_3|} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_2|, ~m_st~0=v_~m_st~0_9, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_1~0] 622712#L509 [2460] L509-->L506: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} AuxVars[] AssignedVars[] 622710#L506 [3343] L506-->L520: Formula: (< 0 v_~t1_st~0_14) InVars {~t1_st~0=v_~t1_st~0_14} OutVars{~t1_st~0=v_~t1_st~0_14} AuxVars[] AssignedVars[] 622708#L520 [3352] L520-->L534: Formula: (< v_~t2_st~0_15 0) InVars {~t2_st~0=v_~t2_st~0_15} OutVars{~t2_st~0=v_~t2_st~0_15} AuxVars[] AssignedVars[] 622737#L534 [3362] L534-->L548: Formula: (< 0 v_~t3_st~0_16) InVars {~t3_st~0=v_~t3_st~0_16} OutVars{~t3_st~0=v_~t3_st~0_16} AuxVars[] AssignedVars[] 622736#L548 [3374] L548-->L562: Formula: (> 0 v_~t4_st~0_17) InVars {~t4_st~0=v_~t4_st~0_17} OutVars{~t4_st~0=v_~t4_st~0_17} AuxVars[] AssignedVars[] 622731#L562 [3386] L562-->L576: Formula: (< v_~t5_st~0_18 0) InVars {~t5_st~0=v_~t5_st~0_18} OutVars{~t5_st~0=v_~t5_st~0_18} AuxVars[] AssignedVars[] 622727#L576 312.69/160.51 [2019-03-28 12:22:30,869 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.51 [2019-03-28 12:22:30,869 INFO L82 PathProgramCache]: Analyzing trace with hash 1548254319, now seen corresponding path program 2 times 312.69/160.51 [2019-03-28 12:22:30,869 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.51 [2019-03-28 12:22:30,870 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.51 [2019-03-28 12:22:30,870 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:30,870 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:30,870 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:30,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:22:30,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:22:30,890 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.51 [2019-03-28 12:22:30,890 INFO L82 PathProgramCache]: Analyzing trace with hash 1967068784, now seen corresponding path program 1 times 312.69/160.51 [2019-03-28 12:22:30,890 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.51 [2019-03-28 12:22:30,890 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.51 [2019-03-28 12:22:30,891 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:30,891 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:30,891 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:30,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:22:30,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:22:30,896 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.51 [2019-03-28 12:22:30,896 INFO L82 PathProgramCache]: Analyzing trace with hash 1986406722, now seen corresponding path program 1 times 312.69/160.51 [2019-03-28 12:22:30,897 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.51 [2019-03-28 12:22:30,897 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.51 [2019-03-28 12:22:30,897 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:30,897 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:30,897 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:30,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.51 [2019-03-28 12:22:30,920 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.51 [2019-03-28 12:22:30,921 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.51 [2019-03-28 12:22:30,921 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 312.69/160.51 [2019-03-28 12:22:30,985 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 312.69/160.51 [2019-03-28 12:22:30,986 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 312.69/160.51 [2019-03-28 12:22:30,986 INFO L87 Difference]: Start difference. First operand 39711 states and 58298 transitions. cyclomatic complexity: 18591 Second operand 3 states. 312.69/160.51 [2019-03-28 12:22:31,690 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.51 [2019-03-28 12:22:31,690 INFO L93 Difference]: Finished difference Result 65965 states and 96341 transitions. 312.69/160.51 [2019-03-28 12:22:31,691 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 312.69/160.51 [2019-03-28 12:22:31,691 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 65965 states and 96341 transitions. 312.69/160.51 [2019-03-28 12:22:31,988 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 65817 312.69/160.51 [2019-03-28 12:22:32,179 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 65965 states to 65965 states and 96341 transitions. 312.69/160.51 [2019-03-28 12:22:32,180 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 65965 312.69/160.51 [2019-03-28 12:22:32,230 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 65965 312.69/160.51 [2019-03-28 12:22:32,231 INFO L73 IsDeterministic]: Start isDeterministic. Operand 65965 states and 96341 transitions. 312.69/160.51 [2019-03-28 12:22:32,278 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.51 [2019-03-28 12:22:32,278 INFO L706 BuchiCegarLoop]: Abstraction has 65965 states and 96341 transitions. 312.69/160.51 [2019-03-28 12:22:32,311 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65965 states and 96341 transitions. 312.69/160.51 [2019-03-28 12:22:32,820 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65965 to 65965. 312.69/160.51 [2019-03-28 12:22:32,820 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 65965 states. 312.69/160.51 [2019-03-28 12:22:32,943 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65965 states to 65965 states and 96341 transitions. 312.69/160.51 [2019-03-28 12:22:32,944 INFO L729 BuchiCegarLoop]: Abstraction has 65965 states and 96341 transitions. 312.69/160.51 [2019-03-28 12:22:32,944 INFO L609 BuchiCegarLoop]: Abstraction has 65965 states and 96341 transitions. 312.69/160.51 [2019-03-28 12:22:32,944 INFO L442 BuchiCegarLoop]: ======== Iteration 42============ 312.69/160.51 [2019-03-28 12:22:32,944 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 65965 states and 96341 transitions. 312.69/160.51 [2019-03-28 12:22:33,179 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 65817 312.69/160.51 [2019-03-28 12:22:33,180 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.51 [2019-03-28 12:22:33,180 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.51 [2019-03-28 12:22:33,180 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.51 [2019-03-28 12:22:33,180 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.51 [2019-03-28 12:22:33,181 INFO L794 eck$LassoCheckResult]: Stem: 727209#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 727007#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 727008#L416-1 [3223] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_5 2) (< 1 v_~t1_i~0_4)) InVars {~t1_i~0=v_~t1_i~0_4} OutVars{~t1_st~0=v_~t1_st~0_5, ~t1_i~0=v_~t1_i~0_4} AuxVars[] AssignedVars[~t1_st~0] 727307#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 729086#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 729085#L431-1 [2355] L431-1-->L436-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 729084#L436-1 [2735] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 729083#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 729082#L601-1 [3235] L601-1-->L606-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 729081#L606-1 [3236] L606-1-->L611-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 729080#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 729079#L616-1 [3240] L616-1-->L621-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 729078#L621-1 [3242] L621-1-->L626-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 729077#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 729076#L631-1 [3246] L631-1-->L636-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 729075#L636-1 [3248] L636-1-->L641-1: Formula: (> v_~E_2~0_4 0) InVars {~E_2~0=v_~E_2~0_4} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[] 729074#L641-1 [3251] L641-1-->L646-1: Formula: (> v_~E_3~0_4 0) InVars {~E_3~0=v_~E_3~0_4} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[] 729073#L646-1 [3253] L646-1-->L651-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 729072#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 729071#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 729070#L294 [3256] L294-->L294-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 729069#L294-2 [2905] L294-2-->L305: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 729068#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 729067#L745 [2925] L745-->L745-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_6) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} AuxVars[] AssignedVars[] 729066#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 729065#L313 [3262] L313-->L313-2: Formula: (< v_~t1_pc~0_3 1) InVars {~t1_pc~0=v_~t1_pc~0_3} OutVars{~t1_pc~0=v_~t1_pc~0_3} AuxVars[] AssignedVars[] 729064#L313-2 [2314] L313-2-->L324: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 729063#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 729062#L753 [2130] L753-->L753-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} AuxVars[] AssignedVars[] 729061#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 729060#L332 [3268] L332-->L332-2: Formula: (< v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 729059#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 729058#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 729057#L761 [2384] L761-->L761-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} AuxVars[] AssignedVars[] 729056#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 729055#L351 [3274] L351-->L351-2: Formula: (> 1 v_~t3_pc~0_3) InVars {~t3_pc~0=v_~t3_pc~0_3} OutVars{~t3_pc~0=v_~t3_pc~0_3} AuxVars[] AssignedVars[] 729054#L351-2 [2543] L351-2-->L362: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 729053#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 729052#L769 [2585] L769-->L769-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} AuxVars[] AssignedVars[] 729051#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 729050#L370 [3280] L370-->L370-2: Formula: (< v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 729049#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 729048#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 729047#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 729046#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 729045#L389 [3286] L389-->L389-2: Formula: (> 1 v_~t5_pc~0_3) InVars {~t5_pc~0=v_~t5_pc~0_3} OutVars{~t5_pc~0=v_~t5_pc~0_3} AuxVars[] AssignedVars[] 729044#L389-2 [2164] L389-2-->L400: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 729043#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 729042#L785 [2215] L785-->L785-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_6} AuxVars[] AssignedVars[] 729041#L785-2 [3292] L785-2-->L669-1: Formula: (< 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 729040#L669-1 [3294] L669-1-->L674-1: Formula: (< 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 729039#L674-1 [3296] L674-1-->L679-1: Formula: (< 1 v_~T2_E~0_7) InVars {~T2_E~0=v_~T2_E~0_7} OutVars{~T2_E~0=v_~T2_E~0_7} AuxVars[] AssignedVars[] 729038#L679-1 [3298] L679-1-->L684-1: Formula: (> v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 727041#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 727042#L689-1 [3302] L689-1-->L694-1: Formula: (> v_~T5_E~0_7 1) InVars {~T5_E~0=v_~T5_E~0_7} OutVars{~T5_E~0=v_~T5_E~0_7} AuxVars[] AssignedVars[] 727201#L694-1 [3304] L694-1-->L699-1: Formula: (> v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 727202#L699-1 [3306] L699-1-->L704-1: Formula: (> v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 729030#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 729028#L709-1 [3310] L709-1-->L714-1: Formula: (> v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 727178#L714-1 [3313] L714-1-->L719-1: Formula: (> v_~E_4~0_9 1) InVars {~E_4~0=v_~E_4~0_9} OutVars{~E_4~0=v_~E_4~0_9} AuxVars[] AssignedVars[] 726896#L719-1 [3314] L719-1-->L930-1: Formula: (> v_~E_5~0_9 1) InVars {~E_5~0=v_~E_5~0_9} OutVars{~E_5~0=v_~E_5~0_9} AuxVars[] AssignedVars[] 726897#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 728960#L576 312.69/160.51 [2019-03-28 12:22:33,182 INFO L796 eck$LassoCheckResult]: Loop: 728960#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 728961#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 728994#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 728991#L501 [3328] L501-->L501-1: Formula: (> v_ULTIMATE.start_eval_~tmp~0_4 0) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} OutVars{ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} AuxVars[] AssignedVars[] 728987#L501-1 [2236] L501-1-->L509: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_2 |v_ULTIMATE.start_eval_#t~nondet2_3|) (= v_~m_st~0_9 0)) InVars {~m_st~0=v_~m_st~0_9, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_3|} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_2|, ~m_st~0=v_~m_st~0_9, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_1~0] 728984#L509 [2460] L509-->L506: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} AuxVars[] AssignedVars[] 728981#L506 [3343] L506-->L520: Formula: (< 0 v_~t1_st~0_14) InVars {~t1_st~0=v_~t1_st~0_14} OutVars{~t1_st~0=v_~t1_st~0_14} AuxVars[] AssignedVars[] 728982#L520 [3352] L520-->L534: Formula: (< v_~t2_st~0_15 0) InVars {~t2_st~0=v_~t2_st~0_15} OutVars{~t2_st~0=v_~t2_st~0_15} AuxVars[] AssignedVars[] 729024#L534 [3362] L534-->L548: Formula: (< 0 v_~t3_st~0_16) InVars {~t3_st~0=v_~t3_st~0_16} OutVars{~t3_st~0=v_~t3_st~0_16} AuxVars[] AssignedVars[] 729022#L548 [3374] L548-->L562: Formula: (> 0 v_~t4_st~0_17) InVars {~t4_st~0=v_~t4_st~0_17} OutVars{~t4_st~0=v_~t4_st~0_17} AuxVars[] AssignedVars[] 728963#L562 [3386] L562-->L576: Formula: (< v_~t5_st~0_18 0) InVars {~t5_st~0=v_~t5_st~0_18} OutVars{~t5_st~0=v_~t5_st~0_18} AuxVars[] AssignedVars[] 728960#L576 312.69/160.51 [2019-03-28 12:22:33,182 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.51 [2019-03-28 12:22:33,182 INFO L82 PathProgramCache]: Analyzing trace with hash 174311763, now seen corresponding path program 1 times 312.69/160.51 [2019-03-28 12:22:33,182 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.51 [2019-03-28 12:22:33,182 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.51 [2019-03-28 12:22:33,183 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:33,183 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:33,183 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:33,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.51 [2019-03-28 12:22:33,194 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.51 [2019-03-28 12:22:33,194 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.51 [2019-03-28 12:22:33,194 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 312.69/160.51 [2019-03-28 12:22:33,195 INFO L799 eck$LassoCheckResult]: stem already infeasible 312.69/160.51 [2019-03-28 12:22:33,195 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.51 [2019-03-28 12:22:33,195 INFO L82 PathProgramCache]: Analyzing trace with hash 1967068784, now seen corresponding path program 2 times 312.69/160.51 [2019-03-28 12:22:33,195 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.51 [2019-03-28 12:22:33,195 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.51 [2019-03-28 12:22:33,196 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:33,196 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:33,196 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:33,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:22:33,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:22:33,250 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 312.69/160.51 [2019-03-28 12:22:33,250 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 312.69/160.51 [2019-03-28 12:22:33,250 INFO L87 Difference]: Start difference. First operand 65965 states and 96341 transitions. cyclomatic complexity: 30381 Second operand 3 states. 312.69/160.51 [2019-03-28 12:22:33,972 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.51 [2019-03-28 12:22:33,973 INFO L93 Difference]: Finished difference Result 65965 states and 96340 transitions. 312.69/160.51 [2019-03-28 12:22:33,973 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 312.69/160.51 [2019-03-28 12:22:33,973 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 65965 states and 96340 transitions. 312.69/160.51 [2019-03-28 12:22:34,243 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 65817 312.69/160.51 [2019-03-28 12:22:34,413 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 65965 states to 65965 states and 96340 transitions. 312.69/160.51 [2019-03-28 12:22:34,413 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 65965 312.69/160.51 [2019-03-28 12:22:34,455 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 65965 312.69/160.51 [2019-03-28 12:22:34,455 INFO L73 IsDeterministic]: Start isDeterministic. Operand 65965 states and 96340 transitions. 312.69/160.51 [2019-03-28 12:22:34,496 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.51 [2019-03-28 12:22:34,496 INFO L706 BuchiCegarLoop]: Abstraction has 65965 states and 96340 transitions. 312.69/160.51 [2019-03-28 12:22:34,526 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65965 states and 96340 transitions. 312.69/160.51 [2019-03-28 12:22:35,031 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65965 to 65965. 312.69/160.51 [2019-03-28 12:22:35,032 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 65965 states. 312.69/160.51 [2019-03-28 12:22:35,157 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65965 states to 65965 states and 96340 transitions. 312.69/160.51 [2019-03-28 12:22:35,157 INFO L729 BuchiCegarLoop]: Abstraction has 65965 states and 96340 transitions. 312.69/160.51 [2019-03-28 12:22:35,157 INFO L609 BuchiCegarLoop]: Abstraction has 65965 states and 96340 transitions. 312.69/160.51 [2019-03-28 12:22:35,157 INFO L442 BuchiCegarLoop]: ======== Iteration 43============ 312.69/160.51 [2019-03-28 12:22:35,157 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 65965 states and 96340 transitions. 312.69/160.51 [2019-03-28 12:22:35,394 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 65817 312.69/160.51 [2019-03-28 12:22:35,394 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.51 [2019-03-28 12:22:35,394 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.51 [2019-03-28 12:22:35,394 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.51 [2019-03-28 12:22:35,395 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.51 [2019-03-28 12:22:35,396 INFO L794 eck$LassoCheckResult]: Stem: 859157#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 858944#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 858945#L416-1 [3222] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_5 2) (> 1 v_~t1_i~0_4)) InVars {~t1_i~0=v_~t1_i~0_4} OutVars{~t1_st~0=v_~t1_st~0_5, ~t1_i~0=v_~t1_i~0_4} AuxVars[] AssignedVars[~t1_st~0] 859267#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 862163#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 862162#L431-1 [2355] L431-1-->L436-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 862161#L436-1 [2735] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 862160#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 862159#L601-1 [3235] L601-1-->L606-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 862158#L606-1 [3236] L606-1-->L611-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 862157#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 862156#L616-1 [3240] L616-1-->L621-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 862155#L621-1 [3242] L621-1-->L626-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 862154#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 862153#L631-1 [3246] L631-1-->L636-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 862152#L636-1 [3248] L636-1-->L641-1: Formula: (> v_~E_2~0_4 0) InVars {~E_2~0=v_~E_2~0_4} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[] 862151#L641-1 [3251] L641-1-->L646-1: Formula: (> v_~E_3~0_4 0) InVars {~E_3~0=v_~E_3~0_4} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[] 862150#L646-1 [3253] L646-1-->L651-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 862149#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 862148#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 862147#L294 [3256] L294-->L294-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 862146#L294-2 [2905] L294-2-->L305: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 862145#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 862144#L745 [2925] L745-->L745-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_6) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} AuxVars[] AssignedVars[] 862143#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 862142#L313 [3262] L313-->L313-2: Formula: (< v_~t1_pc~0_3 1) InVars {~t1_pc~0=v_~t1_pc~0_3} OutVars{~t1_pc~0=v_~t1_pc~0_3} AuxVars[] AssignedVars[] 862141#L313-2 [2314] L313-2-->L324: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 862140#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 862139#L753 [2130] L753-->L753-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} AuxVars[] AssignedVars[] 862138#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 862137#L332 [3268] L332-->L332-2: Formula: (< v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 862136#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 862135#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 862134#L761 [2384] L761-->L761-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} AuxVars[] AssignedVars[] 862133#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 862132#L351 [3274] L351-->L351-2: Formula: (> 1 v_~t3_pc~0_3) InVars {~t3_pc~0=v_~t3_pc~0_3} OutVars{~t3_pc~0=v_~t3_pc~0_3} AuxVars[] AssignedVars[] 862131#L351-2 [2543] L351-2-->L362: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 862130#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 862129#L769 [2585] L769-->L769-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} AuxVars[] AssignedVars[] 862128#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 862127#L370 [3280] L370-->L370-2: Formula: (< v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 862126#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 862125#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 862124#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 862123#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 862122#L389 [3286] L389-->L389-2: Formula: (> 1 v_~t5_pc~0_3) InVars {~t5_pc~0=v_~t5_pc~0_3} OutVars{~t5_pc~0=v_~t5_pc~0_3} AuxVars[] AssignedVars[] 862121#L389-2 [2164] L389-2-->L400: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 862120#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 862119#L785 [2215] L785-->L785-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_6} AuxVars[] AssignedVars[] 862118#L785-2 [3292] L785-2-->L669-1: Formula: (< 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 862117#L669-1 [3294] L669-1-->L674-1: Formula: (< 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 862116#L674-1 [3296] L674-1-->L679-1: Formula: (< 1 v_~T2_E~0_7) InVars {~T2_E~0=v_~T2_E~0_7} OutVars{~T2_E~0=v_~T2_E~0_7} AuxVars[] AssignedVars[] 862115#L679-1 [3298] L679-1-->L684-1: Formula: (> v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 862114#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 862113#L689-1 [3302] L689-1-->L694-1: Formula: (> v_~T5_E~0_7 1) InVars {~T5_E~0=v_~T5_E~0_7} OutVars{~T5_E~0=v_~T5_E~0_7} AuxVars[] AssignedVars[] 859147#L694-1 [3304] L694-1-->L699-1: Formula: (> v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 859148#L699-1 [3306] L699-1-->L704-1: Formula: (> v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 862096#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 858741#L709-1 [3310] L709-1-->L714-1: Formula: (> v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 858742#L714-1 [3313] L714-1-->L719-1: Formula: (> v_~E_4~0_9 1) InVars {~E_4~0=v_~E_4~0_9} OutVars{~E_4~0=v_~E_4~0_9} AuxVars[] AssignedVars[] 861649#L719-1 [3314] L719-1-->L930-1: Formula: (> v_~E_5~0_9 1) InVars {~E_5~0=v_~E_5~0_9} OutVars{~E_5~0=v_~E_5~0_9} AuxVars[] AssignedVars[] 861646#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 861615#L576 312.69/160.51 [2019-03-28 12:22:35,396 INFO L796 eck$LassoCheckResult]: Loop: 861615#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 861616#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 861607#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 861608#L501 [3328] L501-->L501-1: Formula: (> v_ULTIMATE.start_eval_~tmp~0_4 0) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} OutVars{ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} AuxVars[] AssignedVars[] 861599#L501-1 [2236] L501-1-->L509: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_2 |v_ULTIMATE.start_eval_#t~nondet2_3|) (= v_~m_st~0_9 0)) InVars {~m_st~0=v_~m_st~0_9, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_3|} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_2|, ~m_st~0=v_~m_st~0_9, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_1~0] 861602#L509 [2460] L509-->L506: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} AuxVars[] AssignedVars[] 861640#L506 [3343] L506-->L520: Formula: (< 0 v_~t1_st~0_14) InVars {~t1_st~0=v_~t1_st~0_14} OutVars{~t1_st~0=v_~t1_st~0_14} AuxVars[] AssignedVars[] 861637#L520 [3352] L520-->L534: Formula: (< v_~t2_st~0_15 0) InVars {~t2_st~0=v_~t2_st~0_15} OutVars{~t2_st~0=v_~t2_st~0_15} AuxVars[] AssignedVars[] 861631#L534 [3362] L534-->L548: Formula: (< 0 v_~t3_st~0_16) InVars {~t3_st~0=v_~t3_st~0_16} OutVars{~t3_st~0=v_~t3_st~0_16} AuxVars[] AssignedVars[] 861629#L548 [3374] L548-->L562: Formula: (> 0 v_~t4_st~0_17) InVars {~t4_st~0=v_~t4_st~0_17} OutVars{~t4_st~0=v_~t4_st~0_17} AuxVars[] AssignedVars[] 861627#L562 [3386] L562-->L576: Formula: (< v_~t5_st~0_18 0) InVars {~t5_st~0=v_~t5_st~0_18} OutVars{~t5_st~0=v_~t5_st~0_18} AuxVars[] AssignedVars[] 861615#L576 312.69/160.51 [2019-03-28 12:22:35,396 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.51 [2019-03-28 12:22:35,396 INFO L82 PathProgramCache]: Analyzing trace with hash 73399796, now seen corresponding path program 1 times 312.69/160.51 [2019-03-28 12:22:35,396 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.51 [2019-03-28 12:22:35,397 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.51 [2019-03-28 12:22:35,397 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:35,397 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:35,397 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:35,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.51 [2019-03-28 12:22:35,408 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.51 [2019-03-28 12:22:35,408 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.51 [2019-03-28 12:22:35,408 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 312.69/160.51 [2019-03-28 12:22:35,409 INFO L799 eck$LassoCheckResult]: stem already infeasible 312.69/160.51 [2019-03-28 12:22:35,409 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.51 [2019-03-28 12:22:35,409 INFO L82 PathProgramCache]: Analyzing trace with hash 1967068784, now seen corresponding path program 3 times 312.69/160.51 [2019-03-28 12:22:35,409 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.51 [2019-03-28 12:22:35,409 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.51 [2019-03-28 12:22:35,410 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:35,410 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:35,410 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:35,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:22:35,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:22:35,466 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 312.69/160.51 [2019-03-28 12:22:35,466 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 312.69/160.51 [2019-03-28 12:22:35,466 INFO L87 Difference]: Start difference. First operand 65965 states and 96340 transitions. cyclomatic complexity: 30380 Second operand 3 states. 312.69/160.51 [2019-03-28 12:22:35,920 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.51 [2019-03-28 12:22:35,920 INFO L93 Difference]: Finished difference Result 65878 states and 96220 transitions. 312.69/160.51 [2019-03-28 12:22:35,933 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 312.69/160.51 [2019-03-28 12:22:35,933 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 65878 states and 96220 transitions. 312.69/160.51 [2019-03-28 12:22:36,228 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 65802 312.69/160.51 [2019-03-28 12:22:36,420 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 65878 states to 65878 states and 96220 transitions. 312.69/160.51 [2019-03-28 12:22:36,420 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 65878 312.69/160.51 [2019-03-28 12:22:36,470 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 65878 312.69/160.51 [2019-03-28 12:22:36,471 INFO L73 IsDeterministic]: Start isDeterministic. Operand 65878 states and 96220 transitions. 312.69/160.51 [2019-03-28 12:22:36,517 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.51 [2019-03-28 12:22:36,517 INFO L706 BuchiCegarLoop]: Abstraction has 65878 states and 96220 transitions. 312.69/160.51 [2019-03-28 12:22:36,550 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65878 states and 96220 transitions. 312.69/160.51 [2019-03-28 12:22:38,522 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65878 to 65878. 312.69/160.51 [2019-03-28 12:22:38,522 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 65878 states. 312.69/160.51 [2019-03-28 12:22:38,645 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65878 states to 65878 states and 96220 transitions. 312.69/160.51 [2019-03-28 12:22:38,645 INFO L729 BuchiCegarLoop]: Abstraction has 65878 states and 96220 transitions. 312.69/160.51 [2019-03-28 12:22:38,645 INFO L609 BuchiCegarLoop]: Abstraction has 65878 states and 96220 transitions. 312.69/160.51 [2019-03-28 12:22:38,646 INFO L442 BuchiCegarLoop]: ======== Iteration 44============ 312.69/160.51 [2019-03-28 12:22:38,646 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 65878 states and 96220 transitions. 312.69/160.51 [2019-03-28 12:22:38,881 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 65802 312.69/160.51 [2019-03-28 12:22:38,881 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.51 [2019-03-28 12:22:38,881 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.51 [2019-03-28 12:22:38,882 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.51 [2019-03-28 12:22:38,882 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.51 [2019-03-28 12:22:38,883 INFO L794 eck$LassoCheckResult]: Stem: 991004#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 990796#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 990797#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 990866#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 990867#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 990798#L431-1 [2355] L431-1-->L436-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 990799#L436-1 [2735] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 990841#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 990842#L601-1 [3235] L601-1-->L606-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 990845#L606-1 [3236] L606-1-->L611-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 990713#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 990714#L616-1 [3240] L616-1-->L621-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 990600#L621-1 [3242] L621-1-->L626-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 990601#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 990686#L631-1 [3246] L631-1-->L636-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 990687#L636-1 [3248] L636-1-->L641-1: Formula: (> v_~E_2~0_4 0) InVars {~E_2~0=v_~E_2~0_4} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[] 990895#L641-1 [3251] L641-1-->L646-1: Formula: (> v_~E_3~0_4 0) InVars {~E_3~0=v_~E_3~0_4} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[] 990896#L646-1 [3253] L646-1-->L651-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 990832#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 990833#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 991087#L294 [3256] L294-->L294-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 991126#L294-2 [2905] L294-2-->L305: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 991142#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 991143#L745 [2925] L745-->L745-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_6) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} AuxVars[] AssignedVars[] 991158#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 990764#L313 [3262] L313-->L313-2: Formula: (< v_~t1_pc~0_3 1) InVars {~t1_pc~0=v_~t1_pc~0_3} OutVars{~t1_pc~0=v_~t1_pc~0_3} AuxVars[] AssignedVars[] 990765#L313-2 [2314] L313-2-->L324: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 990762#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 990615#L753 [2130] L753-->L753-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} AuxVars[] AssignedVars[] 990616#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 990620#L332 [3268] L332-->L332-2: Formula: (< v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 990806#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 990804#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 990805#L761 [2384] L761-->L761-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} AuxVars[] AssignedVars[] 990828#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 990829#L351 [3274] L351-->L351-2: Formula: (> 1 v_~t3_pc~0_3) InVars {~t3_pc~0=v_~t3_pc~0_3} OutVars{~t3_pc~0=v_~t3_pc~0_3} AuxVars[] AssignedVars[] 990956#L351-2 [2543] L351-2-->L362: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 990957#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 990974#L769 [2585] L769-->L769-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} AuxVars[] AssignedVars[] 990977#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 990978#L370 [3280] L370-->L370-2: Formula: (< v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 991069#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 991065#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 991066#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 991086#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 990677#L389 [3286] L389-->L389-2: Formula: (> 1 v_~t5_pc~0_3) InVars {~t5_pc~0=v_~t5_pc~0_3} OutVars{~t5_pc~0=v_~t5_pc~0_3} AuxVars[] AssignedVars[] 990644#L389-2 [2164] L389-2-->L400: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 990645#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 990673#L785 [2215] L785-->L785-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_6} AuxVars[] AssignedVars[] 990693#L785-2 [3292] L785-2-->L669-1: Formula: (< 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 990695#L669-1 [3294] L669-1-->L674-1: Formula: (< 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 990893#L674-1 [3296] L674-1-->L679-1: Formula: (< 1 v_~T2_E~0_7) InVars {~T2_E~0=v_~T2_E~0_7} OutVars{~T2_E~0=v_~T2_E~0_7} AuxVars[] AssignedVars[] 990894#L679-1 [3298] L679-1-->L684-1: Formula: (> v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 990830#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 990831#L689-1 [3302] L689-1-->L694-1: Formula: (> v_~T5_E~0_7 1) InVars {~T5_E~0=v_~T5_E~0_7} OutVars{~T5_E~0=v_~T5_E~0_7} AuxVars[] AssignedVars[] 990996#L694-1 [3304] L694-1-->L699-1: Formula: (> v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 990734#L699-1 [3306] L699-1-->L704-1: Formula: (> v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 990735#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 990590#L709-1 [3310] L709-1-->L714-1: Formula: (> v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 990591#L714-1 [3313] L714-1-->L719-1: Formula: (> v_~E_4~0_9 1) InVars {~E_4~0=v_~E_4~0_9} OutVars{~E_4~0=v_~E_4~0_9} AuxVars[] AssignedVars[] 990679#L719-1 [3314] L719-1-->L930-1: Formula: (> v_~E_5~0_9 1) InVars {~E_5~0=v_~E_5~0_9} OutVars{~E_5~0=v_~E_5~0_9} AuxVars[] AssignedVars[] 990680#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 998690#L576 312.69/160.51 [2019-03-28 12:22:38,883 INFO L796 eck$LassoCheckResult]: Loop: 998690#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 998686#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 998684#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 998682#L501 [3328] L501-->L501-1: Formula: (> v_ULTIMATE.start_eval_~tmp~0_4 0) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} OutVars{ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} AuxVars[] AssignedVars[] 998678#L501-1 [2236] L501-1-->L509: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_2 |v_ULTIMATE.start_eval_#t~nondet2_3|) (= v_~m_st~0_9 0)) InVars {~m_st~0=v_~m_st~0_9, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_3|} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_2|, ~m_st~0=v_~m_st~0_9, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_1~0] 998675#L509 [2460] L509-->L506: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} AuxVars[] AssignedVars[] 998674#L506 [2670] L506-->L523: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_2 |v_ULTIMATE.start_eval_#t~nondet3_3|) (= 0 v_~t1_st~0_10)) InVars {ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_3|, ~t1_st~0=v_~t1_st~0_10} OutVars{ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_2|, ~t1_st~0=v_~t1_st~0_10, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_~tmp_ndt_2~0] 998671#L523 [2255] L523-->L520: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} AuxVars[] AssignedVars[] 998672#L520 [3352] L520-->L534: Formula: (< v_~t2_st~0_15 0) InVars {~t2_st~0=v_~t2_st~0_15} OutVars{~t2_st~0=v_~t2_st~0_15} AuxVars[] AssignedVars[] 998698#L534 [3362] L534-->L548: Formula: (< 0 v_~t3_st~0_16) InVars {~t3_st~0=v_~t3_st~0_16} OutVars{~t3_st~0=v_~t3_st~0_16} AuxVars[] AssignedVars[] 998697#L548 [3374] L548-->L562: Formula: (> 0 v_~t4_st~0_17) InVars {~t4_st~0=v_~t4_st~0_17} OutVars{~t4_st~0=v_~t4_st~0_17} AuxVars[] AssignedVars[] 998692#L562 [3386] L562-->L576: Formula: (< v_~t5_st~0_18 0) InVars {~t5_st~0=v_~t5_st~0_18} OutVars{~t5_st~0=v_~t5_st~0_18} AuxVars[] AssignedVars[] 998690#L576 312.69/160.51 [2019-03-28 12:22:38,883 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.51 [2019-03-28 12:22:38,884 INFO L82 PathProgramCache]: Analyzing trace with hash 1548254319, now seen corresponding path program 3 times 312.69/160.51 [2019-03-28 12:22:38,884 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.51 [2019-03-28 12:22:38,884 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.51 [2019-03-28 12:22:38,885 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:38,885 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:38,885 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:38,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:22:38,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:22:38,899 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.51 [2019-03-28 12:22:38,900 INFO L82 PathProgramCache]: Analyzing trace with hash 2043599052, now seen corresponding path program 1 times 312.69/160.51 [2019-03-28 12:22:38,900 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.51 [2019-03-28 12:22:38,900 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.51 [2019-03-28 12:22:38,901 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:38,901 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:38,901 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:38,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:22:38,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:22:38,905 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.51 [2019-03-28 12:22:38,906 INFO L82 PathProgramCache]: Analyzing trace with hash -1651892166, now seen corresponding path program 1 times 312.69/160.51 [2019-03-28 12:22:38,906 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.51 [2019-03-28 12:22:38,906 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.51 [2019-03-28 12:22:38,906 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:38,906 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:38,907 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:38,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.51 [2019-03-28 12:22:38,927 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.51 [2019-03-28 12:22:38,928 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.51 [2019-03-28 12:22:38,928 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 312.69/160.51 [2019-03-28 12:22:38,990 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 312.69/160.51 [2019-03-28 12:22:38,990 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 312.69/160.51 [2019-03-28 12:22:38,990 INFO L87 Difference]: Start difference. First operand 65878 states and 96220 transitions. cyclomatic complexity: 30346 Second operand 3 states. 312.69/160.51 [2019-03-28 12:22:39,420 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.51 [2019-03-28 12:22:39,420 INFO L93 Difference]: Finished difference Result 65878 states and 95455 transitions. 312.69/160.51 [2019-03-28 12:22:39,421 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 312.69/160.51 [2019-03-28 12:22:39,421 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 65878 states and 95455 transitions. 312.69/160.51 [2019-03-28 12:22:39,700 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 65802 312.69/160.51 [2019-03-28 12:22:39,879 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 65878 states to 65878 states and 95455 transitions. 312.69/160.51 [2019-03-28 12:22:39,879 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 65878 312.69/160.51 [2019-03-28 12:22:39,925 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 65878 312.69/160.51 [2019-03-28 12:22:39,925 INFO L73 IsDeterministic]: Start isDeterministic. Operand 65878 states and 95455 transitions. 312.69/160.51 [2019-03-28 12:22:39,969 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.51 [2019-03-28 12:22:39,969 INFO L706 BuchiCegarLoop]: Abstraction has 65878 states and 95455 transitions. 312.69/160.51 [2019-03-28 12:22:40,000 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65878 states and 95455 transitions. 312.69/160.51 [2019-03-28 12:22:40,510 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65878 to 65878. 312.69/160.51 [2019-03-28 12:22:40,510 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 65878 states. 312.69/160.51 [2019-03-28 12:22:40,633 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65878 states to 65878 states and 95455 transitions. 312.69/160.51 [2019-03-28 12:22:40,633 INFO L729 BuchiCegarLoop]: Abstraction has 65878 states and 95455 transitions. 312.69/160.51 [2019-03-28 12:22:40,633 INFO L609 BuchiCegarLoop]: Abstraction has 65878 states and 95455 transitions. 312.69/160.51 [2019-03-28 12:22:40,634 INFO L442 BuchiCegarLoop]: ======== Iteration 45============ 312.69/160.51 [2019-03-28 12:22:40,634 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 65878 states and 95455 transitions. 312.69/160.51 [2019-03-28 12:22:40,866 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 65802 312.69/160.51 [2019-03-28 12:22:40,866 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.51 [2019-03-28 12:22:40,866 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.51 [2019-03-28 12:22:40,867 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.51 [2019-03-28 12:22:40,867 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.51 [2019-03-28 12:22:40,868 INFO L794 eck$LassoCheckResult]: Stem: 1122762#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 1122560#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 1122561#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 1122628#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 1122629#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 1122562#L431-1 [2355] L431-1-->L436-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 1122563#L436-1 [2735] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 1122604#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 1122605#L601-1 [3235] L601-1-->L606-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 1122608#L606-1 [3236] L606-1-->L611-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 1122478#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 1122479#L616-1 [3240] L616-1-->L621-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 1122364#L621-1 [3242] L621-1-->L626-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 1122365#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 1122451#L631-1 [3246] L631-1-->L636-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 1122452#L636-1 [3248] L636-1-->L641-1: Formula: (> v_~E_2~0_4 0) InVars {~E_2~0=v_~E_2~0_4} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[] 1122658#L641-1 [3251] L641-1-->L646-1: Formula: (> v_~E_3~0_4 0) InVars {~E_3~0=v_~E_3~0_4} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[] 1122659#L646-1 [3253] L646-1-->L651-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 1122596#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 1122597#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 1122838#L294 [3256] L294-->L294-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 1122872#L294-2 [2905] L294-2-->L305: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 1122891#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 1122892#L745 [2925] L745-->L745-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_6) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} AuxVars[] AssignedVars[] 1122904#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 1122531#L313 [3262] L313-->L313-2: Formula: (< v_~t1_pc~0_3 1) InVars {~t1_pc~0=v_~t1_pc~0_3} OutVars{~t1_pc~0=v_~t1_pc~0_3} AuxVars[] AssignedVars[] 1122532#L313-2 [2314] L313-2-->L324: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 1122529#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 1122379#L753 [2130] L753-->L753-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} AuxVars[] AssignedVars[] 1122380#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 1122384#L332 [3268] L332-->L332-2: Formula: (< v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 1122570#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 1122568#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 1122569#L761 [2384] L761-->L761-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} AuxVars[] AssignedVars[] 1122591#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 1122592#L351 [3274] L351-->L351-2: Formula: (> 1 v_~t3_pc~0_3) InVars {~t3_pc~0=v_~t3_pc~0_3} OutVars{~t3_pc~0=v_~t3_pc~0_3} AuxVars[] AssignedVars[] 1122714#L351-2 [2543] L351-2-->L362: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 1122715#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 1122732#L769 [2585] L769-->L769-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} AuxVars[] AssignedVars[] 1122735#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 1122736#L370 [3280] L370-->L370-2: Formula: (< v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 1122822#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 1122818#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 1122819#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 1122837#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 1122439#L389 [3286] L389-->L389-2: Formula: (> 1 v_~t5_pc~0_3) InVars {~t5_pc~0=v_~t5_pc~0_3} OutVars{~t5_pc~0=v_~t5_pc~0_3} AuxVars[] AssignedVars[] 1122408#L389-2 [2164] L389-2-->L400: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 1122409#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 1122435#L785 [2215] L785-->L785-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_6} AuxVars[] AssignedVars[] 1122458#L785-2 [3292] L785-2-->L669-1: Formula: (< 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 1122460#L669-1 [3294] L669-1-->L674-1: Formula: (< 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 1122656#L674-1 [3296] L674-1-->L679-1: Formula: (< 1 v_~T2_E~0_7) InVars {~T2_E~0=v_~T2_E~0_7} OutVars{~T2_E~0=v_~T2_E~0_7} AuxVars[] AssignedVars[] 1122657#L679-1 [3298] L679-1-->L684-1: Formula: (> v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 1122594#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 1122595#L689-1 [3302] L689-1-->L694-1: Formula: (> v_~T5_E~0_7 1) InVars {~T5_E~0=v_~T5_E~0_7} OutVars{~T5_E~0=v_~T5_E~0_7} AuxVars[] AssignedVars[] 1122754#L694-1 [3304] L694-1-->L699-1: Formula: (> v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 1122503#L699-1 [3306] L699-1-->L704-1: Formula: (> v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 1122504#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 1122354#L709-1 [3310] L709-1-->L714-1: Formula: (> v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 1122355#L714-1 [3313] L714-1-->L719-1: Formula: (> v_~E_4~0_9 1) InVars {~E_4~0=v_~E_4~0_9} OutVars{~E_4~0=v_~E_4~0_9} AuxVars[] AssignedVars[] 1122444#L719-1 [3314] L719-1-->L930-1: Formula: (> v_~E_5~0_9 1) InVars {~E_5~0=v_~E_5~0_9} OutVars{~E_5~0=v_~E_5~0_9} AuxVars[] AssignedVars[] 1122445#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 1130176#L576 312.69/160.51 [2019-03-28 12:22:40,868 INFO L796 eck$LassoCheckResult]: Loop: 1130176#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 1130172#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 1130169#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 1130168#L501 [3328] L501-->L501-1: Formula: (> v_ULTIMATE.start_eval_~tmp~0_4 0) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} OutVars{ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} AuxVars[] AssignedVars[] 1130165#L501-1 [2236] L501-1-->L509: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_2 |v_ULTIMATE.start_eval_#t~nondet2_3|) (= v_~m_st~0_9 0)) InVars {~m_st~0=v_~m_st~0_9, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_3|} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_2|, ~m_st~0=v_~m_st~0_9, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_1~0] 1130162#L509 [2460] L509-->L506: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} AuxVars[] AssignedVars[] 1130160#L506 [2670] L506-->L523: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_2 |v_ULTIMATE.start_eval_#t~nondet3_3|) (= 0 v_~t1_st~0_10)) InVars {ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_3|, ~t1_st~0=v_~t1_st~0_10} OutVars{ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_2|, ~t1_st~0=v_~t1_st~0_10, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_~tmp_ndt_2~0] 1130157#L523 [2255] L523-->L520: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} AuxVars[] AssignedVars[] 1130158#L520 [3353] L520-->L534: Formula: (> v_~t2_st~0_15 0) InVars {~t2_st~0=v_~t2_st~0_15} OutVars{~t2_st~0=v_~t2_st~0_15} AuxVars[] AssignedVars[] 1130187#L534 [3362] L534-->L548: Formula: (< 0 v_~t3_st~0_16) InVars {~t3_st~0=v_~t3_st~0_16} OutVars{~t3_st~0=v_~t3_st~0_16} AuxVars[] AssignedVars[] 1130185#L548 [3374] L548-->L562: Formula: (> 0 v_~t4_st~0_17) InVars {~t4_st~0=v_~t4_st~0_17} OutVars{~t4_st~0=v_~t4_st~0_17} AuxVars[] AssignedVars[] 1130178#L562 [3386] L562-->L576: Formula: (< v_~t5_st~0_18 0) InVars {~t5_st~0=v_~t5_st~0_18} OutVars{~t5_st~0=v_~t5_st~0_18} AuxVars[] AssignedVars[] 1130176#L576 312.69/160.51 [2019-03-28 12:22:40,869 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.51 [2019-03-28 12:22:40,869 INFO L82 PathProgramCache]: Analyzing trace with hash 1548254319, now seen corresponding path program 4 times 312.69/160.51 [2019-03-28 12:22:40,869 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.51 [2019-03-28 12:22:40,869 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.51 [2019-03-28 12:22:40,870 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:40,870 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:40,870 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:40,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:22:40,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:22:40,885 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.51 [2019-03-28 12:22:40,885 INFO L82 PathProgramCache]: Analyzing trace with hash 2043628843, now seen corresponding path program 1 times 312.69/160.51 [2019-03-28 12:22:40,885 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.51 [2019-03-28 12:22:40,885 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.51 [2019-03-28 12:22:40,886 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:40,886 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:40,886 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:40,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:22:40,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:22:40,891 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.51 [2019-03-28 12:22:40,891 INFO L82 PathProgramCache]: Analyzing trace with hash -1651862375, now seen corresponding path program 1 times 312.69/160.51 [2019-03-28 12:22:40,891 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.51 [2019-03-28 12:22:40,891 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.51 [2019-03-28 12:22:40,892 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:40,892 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:40,892 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:40,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.51 [2019-03-28 12:22:40,912 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.51 [2019-03-28 12:22:40,913 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.51 [2019-03-28 12:22:40,913 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 312.69/160.51 [2019-03-28 12:22:40,975 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 312.69/160.51 [2019-03-28 12:22:40,976 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 312.69/160.51 [2019-03-28 12:22:40,989 INFO L87 Difference]: Start difference. First operand 65878 states and 95455 transitions. cyclomatic complexity: 29581 Second operand 3 states. 312.69/160.51 [2019-03-28 12:22:42,069 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.51 [2019-03-28 12:22:42,069 INFO L93 Difference]: Finished difference Result 108216 states and 157720 transitions. 312.69/160.51 [2019-03-28 12:22:42,070 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 312.69/160.51 [2019-03-28 12:22:42,070 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 108216 states and 157720 transitions. 312.69/160.51 [2019-03-28 12:22:42,576 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 108140 312.69/160.51 [2019-03-28 12:22:42,891 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 108216 states to 108216 states and 157720 transitions. 312.69/160.51 [2019-03-28 12:22:42,891 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 108216 312.69/160.51 [2019-03-28 12:22:42,969 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 108216 312.69/160.51 [2019-03-28 12:22:42,969 INFO L73 IsDeterministic]: Start isDeterministic. Operand 108216 states and 157720 transitions. 312.69/160.51 [2019-03-28 12:22:43,039 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.51 [2019-03-28 12:22:43,039 INFO L706 BuchiCegarLoop]: Abstraction has 108216 states and 157720 transitions. 312.69/160.51 [2019-03-28 12:22:43,092 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 108216 states and 157720 transitions. 312.69/160.51 [2019-03-28 12:22:43,971 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 108216 to 108216. 312.69/160.51 [2019-03-28 12:22:43,971 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 108216 states. 312.69/160.51 [2019-03-28 12:22:44,187 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108216 states to 108216 states and 157720 transitions. 312.69/160.51 [2019-03-28 12:22:44,187 INFO L729 BuchiCegarLoop]: Abstraction has 108216 states and 157720 transitions. 312.69/160.51 [2019-03-28 12:22:44,187 INFO L609 BuchiCegarLoop]: Abstraction has 108216 states and 157720 transitions. 312.69/160.51 [2019-03-28 12:22:44,188 INFO L442 BuchiCegarLoop]: ======== Iteration 46============ 312.69/160.51 [2019-03-28 12:22:44,188 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 108216 states and 157720 transitions. 312.69/160.51 [2019-03-28 12:22:44,603 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 108140 312.69/160.51 [2019-03-28 12:22:44,603 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.51 [2019-03-28 12:22:44,603 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.51 [2019-03-28 12:22:44,604 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.51 [2019-03-28 12:22:44,604 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.51 [2019-03-28 12:22:44,605 INFO L794 eck$LassoCheckResult]: Stem: 1296858#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 1296658#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 1296659#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 1296728#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 1296729#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 1296660#L431-1 [2355] L431-1-->L436-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 1296661#L436-1 [2735] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 1296703#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 1296704#L601-1 [3235] L601-1-->L606-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 1296707#L606-1 [3236] L606-1-->L611-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 1296577#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 1296578#L616-1 [3240] L616-1-->L621-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 1296466#L621-1 [3242] L621-1-->L626-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 1296467#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 1296550#L631-1 [3246] L631-1-->L636-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 1296551#L636-1 [3248] L636-1-->L641-1: Formula: (> v_~E_2~0_4 0) InVars {~E_2~0=v_~E_2~0_4} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[] 1296755#L641-1 [3251] L641-1-->L646-1: Formula: (> v_~E_3~0_4 0) InVars {~E_3~0=v_~E_3~0_4} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[] 1296756#L646-1 [3253] L646-1-->L651-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 1296694#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 1296695#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 1296951#L294 [3256] L294-->L294-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 1296993#L294-2 [2905] L294-2-->L305: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 1297015#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 1297016#L745 [2925] L745-->L745-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_6) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} AuxVars[] AssignedVars[] 1297033#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 1296626#L313 [3262] L313-->L313-2: Formula: (< v_~t1_pc~0_3 1) InVars {~t1_pc~0=v_~t1_pc~0_3} OutVars{~t1_pc~0=v_~t1_pc~0_3} AuxVars[] AssignedVars[] 1296627#L313-2 [2314] L313-2-->L324: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 1296624#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 1296482#L753 [2130] L753-->L753-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} AuxVars[] AssignedVars[] 1296483#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 1296486#L332 [3268] L332-->L332-2: Formula: (< v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 1296668#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 1296666#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 1296667#L761 [2384] L761-->L761-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} AuxVars[] AssignedVars[] 1296690#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 1296691#L351 [3274] L351-->L351-2: Formula: (> 1 v_~t3_pc~0_3) InVars {~t3_pc~0=v_~t3_pc~0_3} OutVars{~t3_pc~0=v_~t3_pc~0_3} AuxVars[] AssignedVars[] 1296810#L351-2 [2543] L351-2-->L362: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 1296811#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 1296827#L769 [2585] L769-->L769-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} AuxVars[] AssignedVars[] 1296832#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 1296833#L370 [3280] L370-->L370-2: Formula: (< v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 1296928#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 1296924#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 1296925#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 1296950#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 1296542#L389 [3286] L389-->L389-2: Formula: (> 1 v_~t5_pc~0_3) InVars {~t5_pc~0=v_~t5_pc~0_3} OutVars{~t5_pc~0=v_~t5_pc~0_3} AuxVars[] AssignedVars[] 1296511#L389-2 [2164] L389-2-->L400: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 1296512#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 1296538#L785 [2215] L785-->L785-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_6} AuxVars[] AssignedVars[] 1296557#L785-2 [3292] L785-2-->L669-1: Formula: (< 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 1296559#L669-1 [3294] L669-1-->L674-1: Formula: (< 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 1296753#L674-1 [3296] L674-1-->L679-1: Formula: (< 1 v_~T2_E~0_7) InVars {~T2_E~0=v_~T2_E~0_7} OutVars{~T2_E~0=v_~T2_E~0_7} AuxVars[] AssignedVars[] 1296754#L679-1 [3298] L679-1-->L684-1: Formula: (> v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 1296692#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 1296693#L689-1 [3302] L689-1-->L694-1: Formula: (> v_~T5_E~0_7 1) InVars {~T5_E~0=v_~T5_E~0_7} OutVars{~T5_E~0=v_~T5_E~0_7} AuxVars[] AssignedVars[] 1296851#L694-1 [3304] L694-1-->L699-1: Formula: (> v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 1296600#L699-1 [3306] L699-1-->L704-1: Formula: (> v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 1296601#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 1296456#L709-1 [3310] L709-1-->L714-1: Formula: (> v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 1296457#L714-1 [3313] L714-1-->L719-1: Formula: (> v_~E_4~0_9 1) InVars {~E_4~0=v_~E_4~0_9} OutVars{~E_4~0=v_~E_4~0_9} AuxVars[] AssignedVars[] 1296544#L719-1 [3314] L719-1-->L930-1: Formula: (> v_~E_5~0_9 1) InVars {~E_5~0=v_~E_5~0_9} OutVars{~E_5~0=v_~E_5~0_9} AuxVars[] AssignedVars[] 1296545#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 1326996#L576 312.69/160.51 [2019-03-28 12:22:44,605 INFO L796 eck$LassoCheckResult]: Loop: 1326996#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 1326992#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 1326991#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 1326987#L501 [3328] L501-->L501-1: Formula: (> v_ULTIMATE.start_eval_~tmp~0_4 0) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} OutVars{ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} AuxVars[] AssignedVars[] 1326983#L501-1 [2236] L501-1-->L509: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_2 |v_ULTIMATE.start_eval_#t~nondet2_3|) (= v_~m_st~0_9 0)) InVars {~m_st~0=v_~m_st~0_9, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_3|} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_2|, ~m_st~0=v_~m_st~0_9, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_1~0] 1326980#L509 [2460] L509-->L506: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} AuxVars[] AssignedVars[] 1326978#L506 [2670] L506-->L523: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_2 |v_ULTIMATE.start_eval_#t~nondet3_3|) (= 0 v_~t1_st~0_10)) InVars {ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_3|, ~t1_st~0=v_~t1_st~0_10} OutVars{ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_2|, ~t1_st~0=v_~t1_st~0_10, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_~tmp_ndt_2~0] 1326975#L523 [2255] L523-->L520: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} AuxVars[] AssignedVars[] 1326972#L520 [2457] L520-->L537: Formula: (and (= v_~t2_st~0_11 0) (= v_ULTIMATE.start_eval_~tmp_ndt_3~0_2 |v_ULTIMATE.start_eval_#t~nondet4_3|)) InVars {ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_3|, ~t2_st~0=v_~t2_st~0_11} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_2|, ~t2_st~0=v_~t2_st~0_11, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_~tmp_ndt_3~0] 1326969#L537 [2805] L537-->L534: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_3~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_5} AuxVars[] AssignedVars[] 1326970#L534 [3362] L534-->L548: Formula: (< 0 v_~t3_st~0_16) InVars {~t3_st~0=v_~t3_st~0_16} OutVars{~t3_st~0=v_~t3_st~0_16} AuxVars[] AssignedVars[] 1327005#L548 [3374] L548-->L562: Formula: (> 0 v_~t4_st~0_17) InVars {~t4_st~0=v_~t4_st~0_17} OutVars{~t4_st~0=v_~t4_st~0_17} AuxVars[] AssignedVars[] 1326998#L562 [3386] L562-->L576: Formula: (< v_~t5_st~0_18 0) InVars {~t5_st~0=v_~t5_st~0_18} OutVars{~t5_st~0=v_~t5_st~0_18} AuxVars[] AssignedVars[] 1326996#L576 312.69/160.51 [2019-03-28 12:22:44,606 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.51 [2019-03-28 12:22:44,606 INFO L82 PathProgramCache]: Analyzing trace with hash 1548254319, now seen corresponding path program 5 times 312.69/160.51 [2019-03-28 12:22:44,606 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.51 [2019-03-28 12:22:44,606 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.51 [2019-03-28 12:22:44,607 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:44,607 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:44,607 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:44,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:22:44,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:22:44,623 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.51 [2019-03-28 12:22:44,623 INFO L82 PathProgramCache]: Analyzing trace with hash -1916092228, now seen corresponding path program 1 times 312.69/160.51 [2019-03-28 12:22:44,623 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.51 [2019-03-28 12:22:44,623 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.51 [2019-03-28 12:22:44,624 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:44,624 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:44,624 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:44,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:22:44,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:22:44,629 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.51 [2019-03-28 12:22:44,629 INFO L82 PathProgramCache]: Analyzing trace with hash -512202994, now seen corresponding path program 1 times 312.69/160.51 [2019-03-28 12:22:44,629 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.51 [2019-03-28 12:22:44,629 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.51 [2019-03-28 12:22:44,630 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:44,630 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:44,630 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:44,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.51 [2019-03-28 12:22:44,652 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.51 [2019-03-28 12:22:44,652 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.51 [2019-03-28 12:22:44,652 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 312.69/160.51 [2019-03-28 12:22:44,754 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 312.69/160.51 [2019-03-28 12:22:44,755 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 312.69/160.51 [2019-03-28 12:22:44,755 INFO L87 Difference]: Start difference. First operand 108216 states and 157720 transitions. cyclomatic complexity: 49508 Second operand 3 states. 312.69/160.51 [2019-03-28 12:22:46,295 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.51 [2019-03-28 12:22:46,296 INFO L93 Difference]: Finished difference Result 200804 states and 291363 transitions. 312.69/160.51 [2019-03-28 12:22:46,311 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 312.69/160.51 [2019-03-28 12:22:46,312 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 200804 states and 291363 transitions. 312.69/160.51 [2019-03-28 12:22:47,310 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 200728 312.69/160.51 [2019-03-28 12:22:47,917 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 200804 states to 200804 states and 291363 transitions. 312.69/160.51 [2019-03-28 12:22:47,917 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 200804 312.69/160.51 [2019-03-28 12:22:48,066 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 200804 312.69/160.51 [2019-03-28 12:22:48,066 INFO L73 IsDeterministic]: Start isDeterministic. Operand 200804 states and 291363 transitions. 312.69/160.51 [2019-03-28 12:22:48,196 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.51 [2019-03-28 12:22:48,196 INFO L706 BuchiCegarLoop]: Abstraction has 200804 states and 291363 transitions. 312.69/160.51 [2019-03-28 12:22:48,300 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 200804 states and 291363 transitions. 312.69/160.51 [2019-03-28 12:22:53,266 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 200804 to 200804. 312.69/160.51 [2019-03-28 12:22:53,266 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 200804 states. 312.69/160.51 [2019-03-28 12:22:53,696 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 200804 states to 200804 states and 291363 transitions. 312.69/160.51 [2019-03-28 12:22:53,696 INFO L729 BuchiCegarLoop]: Abstraction has 200804 states and 291363 transitions. 312.69/160.51 [2019-03-28 12:22:53,696 INFO L609 BuchiCegarLoop]: Abstraction has 200804 states and 291363 transitions. 312.69/160.51 [2019-03-28 12:22:53,697 INFO L442 BuchiCegarLoop]: ======== Iteration 47============ 312.69/160.51 [2019-03-28 12:22:53,697 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 200804 states and 291363 transitions. 312.69/160.51 [2019-03-28 12:22:54,500 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 200728 312.69/160.51 [2019-03-28 12:22:54,500 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.51 [2019-03-28 12:22:54,500 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.51 [2019-03-28 12:22:54,501 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.51 [2019-03-28 12:22:54,501 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.51 [2019-03-28 12:22:54,502 INFO L794 eck$LassoCheckResult]: Stem: 1605901#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 1605694#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 1605695#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 1605766#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 1605767#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 1605698#L431-1 [2355] L431-1-->L436-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 1605699#L436-1 [2735] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 1605739#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 1605740#L601-1 [3235] L601-1-->L606-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 1605742#L606-1 [3236] L606-1-->L611-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 1605611#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 1605612#L616-1 [3240] L616-1-->L621-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 1605494#L621-1 [3242] L621-1-->L626-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 1605495#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 1605583#L631-1 [3246] L631-1-->L636-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 1605584#L636-1 [3248] L636-1-->L641-1: Formula: (> v_~E_2~0_4 0) InVars {~E_2~0=v_~E_2~0_4} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[] 1605793#L641-1 [3251] L641-1-->L646-1: Formula: (> v_~E_3~0_4 0) InVars {~E_3~0=v_~E_3~0_4} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[] 1605794#L646-1 [3253] L646-1-->L651-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 1605730#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 1605731#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 1605992#L294 [3256] L294-->L294-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 1606031#L294-2 [2905] L294-2-->L305: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 1606052#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 1606053#L745 [2925] L745-->L745-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_6) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} AuxVars[] AssignedVars[] 1606066#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 1605661#L313 [3262] L313-->L313-2: Formula: (< v_~t1_pc~0_3 1) InVars {~t1_pc~0=v_~t1_pc~0_3} OutVars{~t1_pc~0=v_~t1_pc~0_3} AuxVars[] AssignedVars[] 1605662#L313-2 [2314] L313-2-->L324: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 1605659#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 1605509#L753 [2130] L753-->L753-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} AuxVars[] AssignedVars[] 1605510#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 1605513#L332 [3268] L332-->L332-2: Formula: (< v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 1605704#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 1605702#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 1605703#L761 [2384] L761-->L761-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} AuxVars[] AssignedVars[] 1605725#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 1605726#L351 [3274] L351-->L351-2: Formula: (> 1 v_~t3_pc~0_3) InVars {~t3_pc~0=v_~t3_pc~0_3} OutVars{~t3_pc~0=v_~t3_pc~0_3} AuxVars[] AssignedVars[] 1605849#L351-2 [2543] L351-2-->L362: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 1605850#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 1605869#L769 [2585] L769-->L769-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} AuxVars[] AssignedVars[] 1605874#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 1605875#L370 [3280] L370-->L370-2: Formula: (< v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 1605974#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 1605972#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 1605973#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 1605991#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 1605575#L389 [3286] L389-->L389-2: Formula: (> 1 v_~t5_pc~0_3) InVars {~t5_pc~0=v_~t5_pc~0_3} OutVars{~t5_pc~0=v_~t5_pc~0_3} AuxVars[] AssignedVars[] 1605542#L389-2 [2164] L389-2-->L400: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 1605543#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 1605574#L785 [2215] L785-->L785-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_6} AuxVars[] AssignedVars[] 1605591#L785-2 [3292] L785-2-->L669-1: Formula: (< 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 1605592#L669-1 [3294] L669-1-->L674-1: Formula: (< 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 1605791#L674-1 [3296] L674-1-->L679-1: Formula: (< 1 v_~T2_E~0_7) InVars {~T2_E~0=v_~T2_E~0_7} OutVars{~T2_E~0=v_~T2_E~0_7} AuxVars[] AssignedVars[] 1605792#L679-1 [3298] L679-1-->L684-1: Formula: (> v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 1605728#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 1605729#L689-1 [3302] L689-1-->L694-1: Formula: (> v_~T5_E~0_7 1) InVars {~T5_E~0=v_~T5_E~0_7} OutVars{~T5_E~0=v_~T5_E~0_7} AuxVars[] AssignedVars[] 1605893#L694-1 [3304] L694-1-->L699-1: Formula: (> v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 1605631#L699-1 [3306] L699-1-->L704-1: Formula: (> v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 1605632#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 1605484#L709-1 [3310] L709-1-->L714-1: Formula: (> v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 1605485#L714-1 [3313] L714-1-->L719-1: Formula: (> v_~E_4~0_9 1) InVars {~E_4~0=v_~E_4~0_9} OutVars{~E_4~0=v_~E_4~0_9} AuxVars[] AssignedVars[] 1605577#L719-1 [3314] L719-1-->L930-1: Formula: (> v_~E_5~0_9 1) InVars {~E_5~0=v_~E_5~0_9} OutVars{~E_5~0=v_~E_5~0_9} AuxVars[] AssignedVars[] 1605578#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 1641833#L576 312.69/160.51 [2019-03-28 12:22:54,503 INFO L796 eck$LassoCheckResult]: Loop: 1641833#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 1641829#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 1641828#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 1641826#L501 [3328] L501-->L501-1: Formula: (> v_ULTIMATE.start_eval_~tmp~0_4 0) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} OutVars{ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} AuxVars[] AssignedVars[] 1641823#L501-1 [2236] L501-1-->L509: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_2 |v_ULTIMATE.start_eval_#t~nondet2_3|) (= v_~m_st~0_9 0)) InVars {~m_st~0=v_~m_st~0_9, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_3|} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_2|, ~m_st~0=v_~m_st~0_9, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_1~0] 1641821#L509 [2460] L509-->L506: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} AuxVars[] AssignedVars[] 1641817#L506 [2670] L506-->L523: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_2 |v_ULTIMATE.start_eval_#t~nondet3_3|) (= 0 v_~t1_st~0_10)) InVars {ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_3|, ~t1_st~0=v_~t1_st~0_10} OutVars{ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_2|, ~t1_st~0=v_~t1_st~0_10, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_~tmp_ndt_2~0] 1641815#L523 [2255] L523-->L520: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} AuxVars[] AssignedVars[] 1641813#L520 [2457] L520-->L537: Formula: (and (= v_~t2_st~0_11 0) (= v_ULTIMATE.start_eval_~tmp_ndt_3~0_2 |v_ULTIMATE.start_eval_#t~nondet4_3|)) InVars {ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_3|, ~t2_st~0=v_~t2_st~0_11} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_2|, ~t2_st~0=v_~t2_st~0_11, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_~tmp_ndt_3~0] 1641809#L537 [2805] L537-->L534: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_3~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_5} AuxVars[] AssignedVars[] 1641806#L534 [3363] L534-->L548: Formula: (> 0 v_~t3_st~0_16) InVars {~t3_st~0=v_~t3_st~0_16} OutVars{~t3_st~0=v_~t3_st~0_16} AuxVars[] AssignedVars[] 1637678#L548 [3374] L548-->L562: Formula: (> 0 v_~t4_st~0_17) InVars {~t4_st~0=v_~t4_st~0_17} OutVars{~t4_st~0=v_~t4_st~0_17} AuxVars[] AssignedVars[] 1641835#L562 [3386] L562-->L576: Formula: (< v_~t5_st~0_18 0) InVars {~t5_st~0=v_~t5_st~0_18} OutVars{~t5_st~0=v_~t5_st~0_18} AuxVars[] AssignedVars[] 1641833#L576 312.69/160.51 [2019-03-28 12:22:54,503 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.51 [2019-03-28 12:22:54,503 INFO L82 PathProgramCache]: Analyzing trace with hash 1548254319, now seen corresponding path program 6 times 312.69/160.51 [2019-03-28 12:22:54,503 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.51 [2019-03-28 12:22:54,504 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.51 [2019-03-28 12:22:54,505 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:54,505 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:54,505 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:54,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:22:54,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:22:54,521 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.51 [2019-03-28 12:22:54,521 INFO L82 PathProgramCache]: Analyzing trace with hash -1916091267, now seen corresponding path program 1 times 312.69/160.51 [2019-03-28 12:22:54,521 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.51 [2019-03-28 12:22:54,521 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.51 [2019-03-28 12:22:54,522 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:54,522 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:54,522 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:54,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:22:54,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:22:54,526 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.51 [2019-03-28 12:22:54,527 INFO L82 PathProgramCache]: Analyzing trace with hash -512202033, now seen corresponding path program 1 times 312.69/160.51 [2019-03-28 12:22:54,527 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.51 [2019-03-28 12:22:54,527 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.51 [2019-03-28 12:22:54,527 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:54,528 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:54,528 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:22:54,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.51 [2019-03-28 12:22:54,550 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.51 [2019-03-28 12:22:54,550 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.51 [2019-03-28 12:22:54,550 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 312.69/160.51 [2019-03-28 12:22:54,623 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 312.69/160.51 [2019-03-28 12:22:54,623 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 312.69/160.51 [2019-03-28 12:22:54,624 INFO L87 Difference]: Start difference. First operand 200804 states and 291363 transitions. cyclomatic complexity: 90563 Second operand 3 states. 312.69/160.51 [2019-03-28 12:22:55,375 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.51 [2019-03-28 12:22:55,376 INFO L93 Difference]: Finished difference Result 178660 states and 260658 transitions. 312.69/160.51 [2019-03-28 12:22:55,376 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 312.69/160.51 [2019-03-28 12:22:55,377 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 178660 states and 260658 transitions. 312.69/160.51 [2019-03-28 12:22:56,205 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 178584 312.69/160.51 [2019-03-28 12:22:56,710 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 178660 states to 178660 states and 260658 transitions. 312.69/160.51 [2019-03-28 12:22:56,710 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 178660 312.69/160.51 [2019-03-28 12:22:56,845 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 178660 312.69/160.51 [2019-03-28 12:22:56,845 INFO L73 IsDeterministic]: Start isDeterministic. Operand 178660 states and 260658 transitions. 312.69/160.51 [2019-03-28 12:22:56,967 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.51 [2019-03-28 12:22:56,967 INFO L706 BuchiCegarLoop]: Abstraction has 178660 states and 260658 transitions. 312.69/160.51 [2019-03-28 12:22:57,062 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 178660 states and 260658 transitions. 312.69/160.51 [2019-03-28 12:22:59,538 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 178660 to 178660. 312.69/160.51 [2019-03-28 12:22:59,539 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 178660 states. 312.69/160.51 [2019-03-28 12:22:59,878 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 178660 states to 178660 states and 260658 transitions. 312.69/160.51 [2019-03-28 12:22:59,879 INFO L729 BuchiCegarLoop]: Abstraction has 178660 states and 260658 transitions. 312.69/160.51 [2019-03-28 12:22:59,879 INFO L609 BuchiCegarLoop]: Abstraction has 178660 states and 260658 transitions. 312.69/160.51 [2019-03-28 12:22:59,879 INFO L442 BuchiCegarLoop]: ======== Iteration 48============ 312.69/160.51 [2019-03-28 12:22:59,879 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 178660 states and 260658 transitions. 312.69/160.51 [2019-03-28 12:23:00,559 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 178584 312.69/160.51 [2019-03-28 12:23:00,560 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.51 [2019-03-28 12:23:00,560 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.51 [2019-03-28 12:23:00,560 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.51 [2019-03-28 12:23:00,560 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.51 [2019-03-28 12:23:00,561 INFO L794 eck$LassoCheckResult]: Stem: 1985380#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 1985170#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 1985171#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 1985245#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 1985246#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 1985174#L431-1 [2355] L431-1-->L436-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 1985175#L436-1 [2735] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 1985217#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 1985218#L601-1 [3235] L601-1-->L606-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 1985220#L606-1 [3236] L606-1-->L611-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 1985085#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 1985086#L616-1 [3240] L616-1-->L621-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 1984967#L621-1 [3242] L621-1-->L626-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 1984968#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 1985055#L631-1 [3246] L631-1-->L636-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 1985056#L636-1 [3248] L636-1-->L641-1: Formula: (> v_~E_2~0_4 0) InVars {~E_2~0=v_~E_2~0_4} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[] 1985271#L641-1 [3251] L641-1-->L646-1: Formula: (> v_~E_3~0_4 0) InVars {~E_3~0=v_~E_3~0_4} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[] 1985272#L646-1 [3253] L646-1-->L651-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 1985206#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 1985207#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 1985476#L294 [3256] L294-->L294-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 1985516#L294-2 [2905] L294-2-->L305: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 1985532#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 1985533#L745 [2925] L745-->L745-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_6) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} AuxVars[] AssignedVars[] 1985546#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 1985136#L313 [3262] L313-->L313-2: Formula: (< v_~t1_pc~0_3 1) InVars {~t1_pc~0=v_~t1_pc~0_3} OutVars{~t1_pc~0=v_~t1_pc~0_3} AuxVars[] AssignedVars[] 1985137#L313-2 [2314] L313-2-->L324: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 1985135#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 1984983#L753 [2130] L753-->L753-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} AuxVars[] AssignedVars[] 1984984#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 1984986#L332 [3268] L332-->L332-2: Formula: (< v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 1985180#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 1985178#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 1985179#L761 [2384] L761-->L761-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} AuxVars[] AssignedVars[] 1985200#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 1985201#L351 [3274] L351-->L351-2: Formula: (> 1 v_~t3_pc~0_3) InVars {~t3_pc~0=v_~t3_pc~0_3} OutVars{~t3_pc~0=v_~t3_pc~0_3} AuxVars[] AssignedVars[] 1985328#L351-2 [2543] L351-2-->L362: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 1985329#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 1985349#L769 [2585] L769-->L769-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} AuxVars[] AssignedVars[] 1985353#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 1985354#L370 [3280] L370-->L370-2: Formula: (< v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 1985458#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 1985456#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 1985457#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 1985475#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 1985047#L389 [3286] L389-->L389-2: Formula: (> 1 v_~t5_pc~0_3) InVars {~t5_pc~0=v_~t5_pc~0_3} OutVars{~t5_pc~0=v_~t5_pc~0_3} AuxVars[] AssignedVars[] 1985017#L389-2 [2164] L389-2-->L400: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 1985018#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 1985046#L785 [2215] L785-->L785-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_6} AuxVars[] AssignedVars[] 1985064#L785-2 [3292] L785-2-->L669-1: Formula: (< 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 1985065#L669-1 [3294] L669-1-->L674-1: Formula: (< 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 1985269#L674-1 [3296] L674-1-->L679-1: Formula: (< 1 v_~T2_E~0_7) InVars {~T2_E~0=v_~T2_E~0_7} OutVars{~T2_E~0=v_~T2_E~0_7} AuxVars[] AssignedVars[] 1985270#L679-1 [3298] L679-1-->L684-1: Formula: (> v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 1985204#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 1985205#L689-1 [3302] L689-1-->L694-1: Formula: (> v_~T5_E~0_7 1) InVars {~T5_E~0=v_~T5_E~0_7} OutVars{~T5_E~0=v_~T5_E~0_7} AuxVars[] AssignedVars[] 1985372#L694-1 [3304] L694-1-->L699-1: Formula: (> v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 1985108#L699-1 [3306] L699-1-->L704-1: Formula: (> v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 1985109#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 1984956#L709-1 [3310] L709-1-->L714-1: Formula: (> v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 1984957#L714-1 [3313] L714-1-->L719-1: Formula: (> v_~E_4~0_9 1) InVars {~E_4~0=v_~E_4~0_9} OutVars{~E_4~0=v_~E_4~0_9} AuxVars[] AssignedVars[] 1985050#L719-1 [3314] L719-1-->L930-1: Formula: (> v_~E_5~0_9 1) InVars {~E_5~0=v_~E_5~0_9} OutVars{~E_5~0=v_~E_5~0_9} AuxVars[] AssignedVars[] 1985051#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 2011395#L576 312.69/160.51 [2019-03-28 12:23:00,562 INFO L796 eck$LassoCheckResult]: Loop: 2011395#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 2011597#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 2011596#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 2011595#L501 [3328] L501-->L501-1: Formula: (> v_ULTIMATE.start_eval_~tmp~0_4 0) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} OutVars{ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} AuxVars[] AssignedVars[] 2011592#L501-1 [2236] L501-1-->L509: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_2 |v_ULTIMATE.start_eval_#t~nondet2_3|) (= v_~m_st~0_9 0)) InVars {~m_st~0=v_~m_st~0_9, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_3|} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_2|, ~m_st~0=v_~m_st~0_9, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_1~0] 2011588#L509 [2460] L509-->L506: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} AuxVars[] AssignedVars[] 2011586#L506 [2670] L506-->L523: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_2 |v_ULTIMATE.start_eval_#t~nondet3_3|) (= 0 v_~t1_st~0_10)) InVars {ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_3|, ~t1_st~0=v_~t1_st~0_10} OutVars{ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_2|, ~t1_st~0=v_~t1_st~0_10, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_~tmp_ndt_2~0] 2011584#L523 [2255] L523-->L520: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} AuxVars[] AssignedVars[] 2011582#L520 [2457] L520-->L537: Formula: (and (= v_~t2_st~0_11 0) (= v_ULTIMATE.start_eval_~tmp_ndt_3~0_2 |v_ULTIMATE.start_eval_#t~nondet4_3|)) InVars {ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_3|, ~t2_st~0=v_~t2_st~0_11} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_2|, ~t2_st~0=v_~t2_st~0_11, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_~tmp_ndt_3~0] 2011579#L537 [2805] L537-->L534: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_3~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_5} AuxVars[] AssignedVars[] 2011578#L534 [2252] L534-->L551: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_4~0_2 |v_ULTIMATE.start_eval_#t~nondet5_3|) (= 0 v_~t3_st~0_12)) InVars {~t3_st~0=v_~t3_st~0_12, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_3|} OutVars{~t3_st~0=v_~t3_st~0_12, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_2, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_2|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_#t~nondet5] 2011574#L551 [2412] L551-->L548: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_4~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_5} AuxVars[] AssignedVars[] 2011575#L548 [3374] L548-->L562: Formula: (> 0 v_~t4_st~0_17) InVars {~t4_st~0=v_~t4_st~0_17} OutVars{~t4_st~0=v_~t4_st~0_17} AuxVars[] AssignedVars[] 2011600#L562 [3386] L562-->L576: Formula: (< v_~t5_st~0_18 0) InVars {~t5_st~0=v_~t5_st~0_18} OutVars{~t5_st~0=v_~t5_st~0_18} AuxVars[] AssignedVars[] 2011395#L576 312.69/160.51 [2019-03-28 12:23:00,562 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.51 [2019-03-28 12:23:00,562 INFO L82 PathProgramCache]: Analyzing trace with hash 1548254319, now seen corresponding path program 7 times 312.69/160.51 [2019-03-28 12:23:00,562 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.51 [2019-03-28 12:23:00,562 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.51 [2019-03-28 12:23:00,563 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:23:00,563 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:23:00,563 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:23:00,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:23:00,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:23:00,577 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.51 [2019-03-28 12:23:00,577 INFO L82 PathProgramCache]: Analyzing trace with hash 696693598, now seen corresponding path program 1 times 312.69/160.51 [2019-03-28 12:23:00,577 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.51 [2019-03-28 12:23:00,577 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.51 [2019-03-28 12:23:00,578 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:23:00,578 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:23:00,578 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:23:00,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:23:00,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:23:00,583 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.51 [2019-03-28 12:23:00,583 INFO L82 PathProgramCache]: Analyzing trace with hash 1267586892, now seen corresponding path program 1 times 312.69/160.51 [2019-03-28 12:23:00,583 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.51 [2019-03-28 12:23:00,583 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.51 [2019-03-28 12:23:00,584 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:23:00,584 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:23:00,584 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:23:00,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.51 [2019-03-28 12:23:00,605 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.51 [2019-03-28 12:23:00,606 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.51 [2019-03-28 12:23:00,606 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 312.69/160.51 [2019-03-28 12:23:00,698 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 312.69/160.51 [2019-03-28 12:23:00,699 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 312.69/160.51 [2019-03-28 12:23:00,699 INFO L87 Difference]: Start difference. First operand 178660 states and 260658 transitions. cyclomatic complexity: 82002 Second operand 3 states. 312.69/160.51 [2019-03-28 12:23:01,444 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.51 [2019-03-28 12:23:01,444 INFO L93 Difference]: Finished difference Result 178660 states and 258753 transitions. 312.69/160.51 [2019-03-28 12:23:01,445 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 312.69/160.51 [2019-03-28 12:23:01,445 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 178660 states and 258753 transitions. 312.69/160.51 [2019-03-28 12:23:02,287 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 178584 312.69/160.51 [2019-03-28 12:23:02,798 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 178660 states to 178660 states and 258753 transitions. 312.69/160.51 [2019-03-28 12:23:02,798 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 178660 312.69/160.51 [2019-03-28 12:23:02,933 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 178660 312.69/160.51 [2019-03-28 12:23:02,934 INFO L73 IsDeterministic]: Start isDeterministic. Operand 178660 states and 258753 transitions. 312.69/160.51 [2019-03-28 12:23:06,236 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.51 [2019-03-28 12:23:06,237 INFO L706 BuchiCegarLoop]: Abstraction has 178660 states and 258753 transitions. 312.69/160.51 [2019-03-28 12:23:06,312 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 178660 states and 258753 transitions. 312.69/160.51 [2019-03-28 12:23:07,695 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 178660 to 178660. 312.69/160.51 [2019-03-28 12:23:07,696 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 178660 states. 312.69/160.51 [2019-03-28 12:23:08,038 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 178660 states to 178660 states and 258753 transitions. 312.69/160.51 [2019-03-28 12:23:08,038 INFO L729 BuchiCegarLoop]: Abstraction has 178660 states and 258753 transitions. 312.69/160.51 [2019-03-28 12:23:08,038 INFO L609 BuchiCegarLoop]: Abstraction has 178660 states and 258753 transitions. 312.69/160.51 [2019-03-28 12:23:08,038 INFO L442 BuchiCegarLoop]: ======== Iteration 49============ 312.69/160.51 [2019-03-28 12:23:08,038 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 178660 states and 258753 transitions. 312.69/160.51 [2019-03-28 12:23:08,722 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 178584 312.69/160.51 [2019-03-28 12:23:08,722 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.51 [2019-03-28 12:23:08,722 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.51 [2019-03-28 12:23:08,723 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.51 [2019-03-28 12:23:08,723 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.51 [2019-03-28 12:23:08,724 INFO L794 eck$LassoCheckResult]: Stem: 2342706#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 2342488#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 2342489#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 2342561#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 2342562#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 2342490#L431-1 [2355] L431-1-->L436-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 2342491#L436-1 [2735] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 2342533#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 2342534#L601-1 [3235] L601-1-->L606-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 2342538#L606-1 [3236] L606-1-->L611-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 2342404#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 2342405#L616-1 [3240] L616-1-->L621-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 2342294#L621-1 [3242] L621-1-->L626-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 2342295#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 2342377#L631-1 [3246] L631-1-->L636-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 2342378#L636-1 [3248] L636-1-->L641-1: Formula: (> v_~E_2~0_4 0) InVars {~E_2~0=v_~E_2~0_4} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[] 2342589#L641-1 [3251] L641-1-->L646-1: Formula: (> v_~E_3~0_4 0) InVars {~E_3~0=v_~E_3~0_4} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[] 2342590#L646-1 [3253] L646-1-->L651-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 2342524#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 2342525#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 2342801#L294 [3256] L294-->L294-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 2342840#L294-2 [2905] L294-2-->L305: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 2342861#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 2342862#L745 [2925] L745-->L745-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_6) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} AuxVars[] AssignedVars[] 2342880#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 2342455#L313 [3262] L313-->L313-2: Formula: (< v_~t1_pc~0_3 1) InVars {~t1_pc~0=v_~t1_pc~0_3} OutVars{~t1_pc~0=v_~t1_pc~0_3} AuxVars[] AssignedVars[] 2342456#L313-2 [2314] L313-2-->L324: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 2342453#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 2342309#L753 [2130] L753-->L753-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} AuxVars[] AssignedVars[] 2342310#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 2342313#L332 [3268] L332-->L332-2: Formula: (< v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 2342498#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 2342496#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 2342497#L761 [2384] L761-->L761-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} AuxVars[] AssignedVars[] 2342520#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 2342521#L351 [3274] L351-->L351-2: Formula: (> 1 v_~t3_pc~0_3) InVars {~t3_pc~0=v_~t3_pc~0_3} OutVars{~t3_pc~0=v_~t3_pc~0_3} AuxVars[] AssignedVars[] 2342650#L351-2 [2543] L351-2-->L362: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 2342651#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 2342675#L769 [2585] L769-->L769-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} AuxVars[] AssignedVars[] 2342679#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 2342680#L370 [3280] L370-->L370-2: Formula: (< v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 2342781#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 2342777#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 2342778#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 2342799#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 2342368#L389 [3286] L389-->L389-2: Formula: (> 1 v_~t5_pc~0_3) InVars {~t5_pc~0=v_~t5_pc~0_3} OutVars{~t5_pc~0=v_~t5_pc~0_3} AuxVars[] AssignedVars[] 2342339#L389-2 [2164] L389-2-->L400: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 2342340#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 2342365#L785 [2215] L785-->L785-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_6} AuxVars[] AssignedVars[] 2342384#L785-2 [3292] L785-2-->L669-1: Formula: (< 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 2342386#L669-1 [3294] L669-1-->L674-1: Formula: (< 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 2342587#L674-1 [3296] L674-1-->L679-1: Formula: (< 1 v_~T2_E~0_7) InVars {~T2_E~0=v_~T2_E~0_7} OutVars{~T2_E~0=v_~T2_E~0_7} AuxVars[] AssignedVars[] 2342588#L679-1 [3298] L679-1-->L684-1: Formula: (> v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 2342522#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 2342523#L689-1 [3302] L689-1-->L694-1: Formula: (> v_~T5_E~0_7 1) InVars {~T5_E~0=v_~T5_E~0_7} OutVars{~T5_E~0=v_~T5_E~0_7} AuxVars[] AssignedVars[] 2342698#L694-1 [3304] L694-1-->L699-1: Formula: (> v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 2342426#L699-1 [3306] L699-1-->L704-1: Formula: (> v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 2342427#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 2342284#L709-1 [3310] L709-1-->L714-1: Formula: (> v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 2342285#L714-1 [3313] L714-1-->L719-1: Formula: (> v_~E_4~0_9 1) InVars {~E_4~0=v_~E_4~0_9} OutVars{~E_4~0=v_~E_4~0_9} AuxVars[] AssignedVars[] 2342371#L719-1 [3314] L719-1-->L930-1: Formula: (> v_~E_5~0_9 1) InVars {~E_5~0=v_~E_5~0_9} OutVars{~E_5~0=v_~E_5~0_9} AuxVars[] AssignedVars[] 2342372#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 2379828#L576 312.69/160.51 [2019-03-28 12:23:08,724 INFO L796 eck$LassoCheckResult]: Loop: 2379828#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 2379819#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 2379812#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 2379805#L501 [3328] L501-->L501-1: Formula: (> v_ULTIMATE.start_eval_~tmp~0_4 0) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} OutVars{ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} AuxVars[] AssignedVars[] 2379796#L501-1 [2236] L501-1-->L509: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_2 |v_ULTIMATE.start_eval_#t~nondet2_3|) (= v_~m_st~0_9 0)) InVars {~m_st~0=v_~m_st~0_9, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_3|} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_2|, ~m_st~0=v_~m_st~0_9, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_1~0] 2379789#L509 [2460] L509-->L506: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} AuxVars[] AssignedVars[] 2379786#L506 [2670] L506-->L523: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_2 |v_ULTIMATE.start_eval_#t~nondet3_3|) (= 0 v_~t1_st~0_10)) InVars {ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_3|, ~t1_st~0=v_~t1_st~0_10} OutVars{ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_2|, ~t1_st~0=v_~t1_st~0_10, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_~tmp_ndt_2~0] 2379776#L523 [2255] L523-->L520: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} AuxVars[] AssignedVars[] 2379765#L520 [2457] L520-->L537: Formula: (and (= v_~t2_st~0_11 0) (= v_ULTIMATE.start_eval_~tmp_ndt_3~0_2 |v_ULTIMATE.start_eval_#t~nondet4_3|)) InVars {ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_3|, ~t2_st~0=v_~t2_st~0_11} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_2|, ~t2_st~0=v_~t2_st~0_11, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_~tmp_ndt_3~0] 2379754#L537 [2805] L537-->L534: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_3~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_5} AuxVars[] AssignedVars[] 2379747#L534 [2252] L534-->L551: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_4~0_2 |v_ULTIMATE.start_eval_#t~nondet5_3|) (= 0 v_~t3_st~0_12)) InVars {~t3_st~0=v_~t3_st~0_12, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_3|} OutVars{~t3_st~0=v_~t3_st~0_12, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_2, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_2|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_#t~nondet5] 2379740#L551 [2412] L551-->L548: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_4~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_5} AuxVars[] AssignedVars[] 2379741#L548 [3375] L548-->L562: Formula: (< 0 v_~t4_st~0_17) InVars {~t4_st~0=v_~t4_st~0_17} OutVars{~t4_st~0=v_~t4_st~0_17} AuxVars[] AssignedVars[] 2379835#L562 [3386] L562-->L576: Formula: (< v_~t5_st~0_18 0) InVars {~t5_st~0=v_~t5_st~0_18} OutVars{~t5_st~0=v_~t5_st~0_18} AuxVars[] AssignedVars[] 2379828#L576 312.69/160.51 [2019-03-28 12:23:08,724 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.51 [2019-03-28 12:23:08,725 INFO L82 PathProgramCache]: Analyzing trace with hash 1548254319, now seen corresponding path program 8 times 312.69/160.51 [2019-03-28 12:23:08,725 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.51 [2019-03-28 12:23:08,725 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.51 [2019-03-28 12:23:08,726 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:23:08,726 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:23:08,726 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:23:08,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:23:08,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:23:08,739 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.51 [2019-03-28 12:23:08,739 INFO L82 PathProgramCache]: Analyzing trace with hash 696693629, now seen corresponding path program 1 times 312.69/160.51 [2019-03-28 12:23:08,739 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.51 [2019-03-28 12:23:08,739 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.51 [2019-03-28 12:23:08,740 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:23:08,740 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:23:08,740 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:23:08,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:23:08,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:23:08,745 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.51 [2019-03-28 12:23:08,745 INFO L82 PathProgramCache]: Analyzing trace with hash 1267586923, now seen corresponding path program 1 times 312.69/160.51 [2019-03-28 12:23:08,745 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.51 [2019-03-28 12:23:08,745 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.51 [2019-03-28 12:23:08,746 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:23:08,746 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:23:08,746 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:23:08,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.51 [2019-03-28 12:23:08,766 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.51 [2019-03-28 12:23:08,767 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.51 [2019-03-28 12:23:08,767 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 312.69/160.51 [2019-03-28 12:23:08,875 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 312.69/160.51 [2019-03-28 12:23:08,876 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 312.69/160.51 [2019-03-28 12:23:08,876 INFO L87 Difference]: Start difference. First operand 178660 states and 258753 transitions. cyclomatic complexity: 80097 Second operand 3 states. 312.69/160.51 [2019-03-28 12:23:10,241 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.51 [2019-03-28 12:23:10,241 INFO L93 Difference]: Finished difference Result 326220 states and 469544 transitions. 312.69/160.51 [2019-03-28 12:23:10,242 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 312.69/160.51 [2019-03-28 12:23:10,242 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 326220 states and 469544 transitions. 312.69/160.51 [2019-03-28 12:23:12,518 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 326144 312.69/160.51 [2019-03-28 12:23:13,289 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 326220 states to 326220 states and 469544 transitions. 312.69/160.51 [2019-03-28 12:23:13,289 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 326220 312.69/160.51 [2019-03-28 12:23:13,470 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 326220 312.69/160.51 [2019-03-28 12:23:13,470 INFO L73 IsDeterministic]: Start isDeterministic. Operand 326220 states and 469544 transitions. 312.69/160.51 [2019-03-28 12:23:13,643 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.51 [2019-03-28 12:23:13,643 INFO L706 BuchiCegarLoop]: Abstraction has 326220 states and 469544 transitions. 312.69/160.51 [2019-03-28 12:23:13,790 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 326220 states and 469544 transitions. 312.69/160.51 [2019-03-28 12:23:21,851 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 326220 to 319692. 312.69/160.51 [2019-03-28 12:23:21,852 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 319692 states. 312.69/160.51 [2019-03-28 12:23:22,545 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 319692 states to 319692 states and 461096 transitions. 312.69/160.51 [2019-03-28 12:23:22,545 INFO L729 BuchiCegarLoop]: Abstraction has 319692 states and 461096 transitions. 312.69/160.51 [2019-03-28 12:23:22,545 INFO L609 BuchiCegarLoop]: Abstraction has 319692 states and 461096 transitions. 312.69/160.51 [2019-03-28 12:23:22,545 INFO L442 BuchiCegarLoop]: ======== Iteration 50============ 312.69/160.51 [2019-03-28 12:23:22,545 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 319692 states and 461096 transitions. 312.69/160.51 [2019-03-28 12:23:23,789 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 319616 312.69/160.51 [2019-03-28 12:23:23,790 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.51 [2019-03-28 12:23:23,790 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.51 [2019-03-28 12:23:23,790 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.51 [2019-03-28 12:23:23,790 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.51 [2019-03-28 12:23:23,791 INFO L794 eck$LassoCheckResult]: Stem: 2847610#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 2847385#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 2847386#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 2847461#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 2847462#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 2847389#L431-1 [2355] L431-1-->L436-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 2847390#L436-1 [2735] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 2847431#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 2847432#L601-1 [3235] L601-1-->L606-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 2847435#L606-1 [3236] L606-1-->L611-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 2847293#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 2847294#L616-1 [3240] L616-1-->L621-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 2847183#L621-1 [3242] L621-1-->L626-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 2847184#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 2847265#L631-1 [3246] L631-1-->L636-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 2847266#L636-1 [3248] L636-1-->L641-1: Formula: (> v_~E_2~0_4 0) InVars {~E_2~0=v_~E_2~0_4} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[] 2847488#L641-1 [3251] L641-1-->L646-1: Formula: (> v_~E_3~0_4 0) InVars {~E_3~0=v_~E_3~0_4} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[] 2847489#L646-1 [3253] L646-1-->L651-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 2847420#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 2847421#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 2847714#L294 [3256] L294-->L294-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 2847760#L294-2 [2905] L294-2-->L305: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 2847783#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 2847784#L745 [2925] L745-->L745-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_6) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} AuxVars[] AssignedVars[] 2847799#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 2847347#L313 [3262] L313-->L313-2: Formula: (< v_~t1_pc~0_3 1) InVars {~t1_pc~0=v_~t1_pc~0_3} OutVars{~t1_pc~0=v_~t1_pc~0_3} AuxVars[] AssignedVars[] 2847348#L313-2 [2314] L313-2-->L324: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 2847346#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 2847198#L753 [2130] L753-->L753-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} AuxVars[] AssignedVars[] 2847199#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 2847202#L332 [3268] L332-->L332-2: Formula: (< v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 2847395#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 2847393#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 2847394#L761 [2384] L761-->L761-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} AuxVars[] AssignedVars[] 2847416#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 2847417#L351 [3274] L351-->L351-2: Formula: (> 1 v_~t3_pc~0_3) InVars {~t3_pc~0=v_~t3_pc~0_3} OutVars{~t3_pc~0=v_~t3_pc~0_3} AuxVars[] AssignedVars[] 2847553#L351-2 [2543] L351-2-->L362: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 2847554#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 2847578#L769 [2585] L769-->L769-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} AuxVars[] AssignedVars[] 2847584#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 2847585#L370 [3280] L370-->L370-2: Formula: (< v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 2847691#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 2847689#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 2847690#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 2847712#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 2847257#L389 [3286] L389-->L389-2: Formula: (> 1 v_~t5_pc~0_3) InVars {~t5_pc~0=v_~t5_pc~0_3} OutVars{~t5_pc~0=v_~t5_pc~0_3} AuxVars[] AssignedVars[] 2847230#L389-2 [2164] L389-2-->L400: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 2847231#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 2847255#L785 [2215] L785-->L785-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_6} AuxVars[] AssignedVars[] 2847273#L785-2 [3292] L785-2-->L669-1: Formula: (< 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 2847274#L669-1 [3294] L669-1-->L674-1: Formula: (< 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 2847486#L674-1 [3296] L674-1-->L679-1: Formula: (< 1 v_~T2_E~0_7) InVars {~T2_E~0=v_~T2_E~0_7} OutVars{~T2_E~0=v_~T2_E~0_7} AuxVars[] AssignedVars[] 2847487#L679-1 [3298] L679-1-->L684-1: Formula: (> v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 2847418#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 2847419#L689-1 [3302] L689-1-->L694-1: Formula: (> v_~T5_E~0_7 1) InVars {~T5_E~0=v_~T5_E~0_7} OutVars{~T5_E~0=v_~T5_E~0_7} AuxVars[] AssignedVars[] 2847603#L694-1 [3304] L694-1-->L699-1: Formula: (> v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 2847315#L699-1 [3306] L699-1-->L704-1: Formula: (> v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 2847316#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 2847172#L709-1 [3310] L709-1-->L714-1: Formula: (> v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 2847173#L714-1 [3313] L714-1-->L719-1: Formula: (> v_~E_4~0_9 1) InVars {~E_4~0=v_~E_4~0_9} OutVars{~E_4~0=v_~E_4~0_9} AuxVars[] AssignedVars[] 2847260#L719-1 [3314] L719-1-->L930-1: Formula: (> v_~E_5~0_9 1) InVars {~E_5~0=v_~E_5~0_9} OutVars{~E_5~0=v_~E_5~0_9} AuxVars[] AssignedVars[] 2847261#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 3006274#L576 312.69/160.51 [2019-03-28 12:23:23,792 INFO L796 eck$LassoCheckResult]: Loop: 3006274#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 3006270#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 3006268#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 3006267#L501 [3328] L501-->L501-1: Formula: (> v_ULTIMATE.start_eval_~tmp~0_4 0) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} OutVars{ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} AuxVars[] AssignedVars[] 3006263#L501-1 [2236] L501-1-->L509: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_2 |v_ULTIMATE.start_eval_#t~nondet2_3|) (= v_~m_st~0_9 0)) InVars {~m_st~0=v_~m_st~0_9, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_3|} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_2|, ~m_st~0=v_~m_st~0_9, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_1~0] 3006260#L509 [2460] L509-->L506: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} AuxVars[] AssignedVars[] 3006258#L506 [2670] L506-->L523: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_2 |v_ULTIMATE.start_eval_#t~nondet3_3|) (= 0 v_~t1_st~0_10)) InVars {ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_3|, ~t1_st~0=v_~t1_st~0_10} OutVars{ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_2|, ~t1_st~0=v_~t1_st~0_10, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_~tmp_ndt_2~0] 3006254#L523 [2255] L523-->L520: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} AuxVars[] AssignedVars[] 3006252#L520 [2457] L520-->L537: Formula: (and (= v_~t2_st~0_11 0) (= v_ULTIMATE.start_eval_~tmp_ndt_3~0_2 |v_ULTIMATE.start_eval_#t~nondet4_3|)) InVars {ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_3|, ~t2_st~0=v_~t2_st~0_11} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_2|, ~t2_st~0=v_~t2_st~0_11, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_~tmp_ndt_3~0] 3006248#L537 [2805] L537-->L534: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_3~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_5} AuxVars[] AssignedVars[] 3006249#L534 [2252] L534-->L551: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_4~0_2 |v_ULTIMATE.start_eval_#t~nondet5_3|) (= 0 v_~t3_st~0_12)) InVars {~t3_st~0=v_~t3_st~0_12, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_3|} OutVars{~t3_st~0=v_~t3_st~0_12, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_2, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_2|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_#t~nondet5] 3006282#L551 [2412] L551-->L548: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_4~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_5} AuxVars[] AssignedVars[] 3006281#L548 [2801] L548-->L565: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_5~0_2 |v_ULTIMATE.start_eval_#t~nondet6_3|) (= 0 v_~t4_st~0_13)) InVars {ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_3|, ~t4_st~0=v_~t4_st~0_13} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_2, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_2|, ~t4_st~0=v_~t4_st~0_13} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_#t~nondet6] 3006279#L565 [2213] L565-->L562: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_5~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_5} AuxVars[] AssignedVars[] 3006276#L562 [3386] L562-->L576: Formula: (< v_~t5_st~0_18 0) InVars {~t5_st~0=v_~t5_st~0_18} OutVars{~t5_st~0=v_~t5_st~0_18} AuxVars[] AssignedVars[] 3006274#L576 312.69/160.51 [2019-03-28 12:23:23,792 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.51 [2019-03-28 12:23:23,792 INFO L82 PathProgramCache]: Analyzing trace with hash 1548254319, now seen corresponding path program 9 times 312.69/160.51 [2019-03-28 12:23:23,792 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.51 [2019-03-28 12:23:23,792 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.51 [2019-03-28 12:23:23,793 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:23:23,793 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:23:23,793 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:23:23,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:23:23,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:23:23,807 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.51 [2019-03-28 12:23:23,807 INFO L82 PathProgramCache]: Analyzing trace with hash 122081428, now seen corresponding path program 1 times 312.69/160.51 [2019-03-28 12:23:23,807 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.51 [2019-03-28 12:23:23,807 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.51 [2019-03-28 12:23:23,808 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:23:23,808 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:23:23,808 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:23:23,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:23:23,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:23:23,812 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.51 [2019-03-28 12:23:23,813 INFO L82 PathProgramCache]: Analyzing trace with hash 639904358, now seen corresponding path program 1 times 312.69/160.51 [2019-03-28 12:23:23,813 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.51 [2019-03-28 12:23:23,813 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.51 [2019-03-28 12:23:23,813 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:23:23,813 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:23:23,814 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:23:23,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.51 [2019-03-28 12:23:23,834 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.51 [2019-03-28 12:23:23,835 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.51 [2019-03-28 12:23:23,835 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 312.69/160.51 [2019-03-28 12:23:23,944 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 312.69/160.51 [2019-03-28 12:23:23,944 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 312.69/160.51 [2019-03-28 12:23:23,944 INFO L87 Difference]: Start difference. First operand 319692 states and 461096 transitions. cyclomatic complexity: 141408 Second operand 3 states. 312.69/160.51 [2019-03-28 12:23:25,166 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.51 [2019-03-28 12:23:25,166 INFO L93 Difference]: Finished difference Result 319692 states and 457671 transitions. 312.69/160.51 [2019-03-28 12:23:25,166 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 312.69/160.51 [2019-03-28 12:23:25,167 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 319692 states and 457671 transitions. 312.69/160.51 [2019-03-28 12:23:26,750 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 319616 312.69/160.51 [2019-03-28 12:23:27,691 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 319692 states to 319692 states and 457671 transitions. 312.69/160.51 [2019-03-28 12:23:27,691 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 319692 312.69/160.51 [2019-03-28 12:23:29,112 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 319692 312.69/160.51 [2019-03-28 12:23:29,112 INFO L73 IsDeterministic]: Start isDeterministic. Operand 319692 states and 457671 transitions. 312.69/160.51 [2019-03-28 12:23:29,250 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.51 [2019-03-28 12:23:29,250 INFO L706 BuchiCegarLoop]: Abstraction has 319692 states and 457671 transitions. 312.69/160.51 [2019-03-28 12:23:29,397 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 319692 states and 457671 transitions. 312.69/160.51 [2019-03-28 12:23:31,926 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 319692 to 319692. 312.69/160.51 [2019-03-28 12:23:31,927 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 319692 states. 312.69/160.51 [2019-03-28 12:23:32,602 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 319692 states to 319692 states and 457671 transitions. 312.69/160.51 [2019-03-28 12:23:32,602 INFO L729 BuchiCegarLoop]: Abstraction has 319692 states and 457671 transitions. 312.69/160.51 [2019-03-28 12:23:32,603 INFO L609 BuchiCegarLoop]: Abstraction has 319692 states and 457671 transitions. 312.69/160.51 [2019-03-28 12:23:32,603 INFO L442 BuchiCegarLoop]: ======== Iteration 51============ 312.69/160.51 [2019-03-28 12:23:32,603 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 319692 states and 457671 transitions. 312.69/160.51 [2019-03-28 12:23:33,898 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 319616 312.69/160.51 [2019-03-28 12:23:33,898 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.51 [2019-03-28 12:23:33,898 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.51 [2019-03-28 12:23:33,899 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.51 [2019-03-28 12:23:33,899 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.51 [2019-03-28 12:23:33,900 INFO L794 eck$LassoCheckResult]: Stem: 3486985#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 3486772#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 3486773#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 3486846#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 3486847#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 3486774#L431-1 [2355] L431-1-->L436-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 3486775#L436-1 [2735] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 3486818#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 3486819#L601-1 [3235] L601-1-->L606-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 3486823#L606-1 [3236] L606-1-->L611-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 3486689#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 3486690#L616-1 [3240] L616-1-->L621-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 3486574#L621-1 [3242] L621-1-->L626-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 3486575#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 3486662#L631-1 [3246] L631-1-->L636-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 3486663#L636-1 [3248] L636-1-->L641-1: Formula: (> v_~E_2~0_4 0) InVars {~E_2~0=v_~E_2~0_4} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[] 3486874#L641-1 [3251] L641-1-->L646-1: Formula: (> v_~E_3~0_4 0) InVars {~E_3~0=v_~E_3~0_4} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[] 3486875#L646-1 [3253] L646-1-->L651-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 3486809#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 3486810#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 3487081#L294 [3256] L294-->L294-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 3487115#L294-2 [2905] L294-2-->L305: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 3487141#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 3487142#L745 [2925] L745-->L745-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_6) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} AuxVars[] AssignedVars[] 3487158#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 3486743#L313 [3262] L313-->L313-2: Formula: (< v_~t1_pc~0_3 1) InVars {~t1_pc~0=v_~t1_pc~0_3} OutVars{~t1_pc~0=v_~t1_pc~0_3} AuxVars[] AssignedVars[] 3486744#L313-2 [2314] L313-2-->L324: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 3486741#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 3486589#L753 [2130] L753-->L753-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} AuxVars[] AssignedVars[] 3486590#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 3486595#L332 [3268] L332-->L332-2: Formula: (< v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 3486782#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 3486780#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 3486781#L761 [2384] L761-->L761-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} AuxVars[] AssignedVars[] 3486805#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 3486806#L351 [3274] L351-->L351-2: Formula: (> 1 v_~t3_pc~0_3) InVars {~t3_pc~0=v_~t3_pc~0_3} OutVars{~t3_pc~0=v_~t3_pc~0_3} AuxVars[] AssignedVars[] 3486933#L351-2 [2543] L351-2-->L362: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 3486934#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 3486955#L769 [2585] L769-->L769-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} AuxVars[] AssignedVars[] 3486959#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 3486960#L370 [3280] L370-->L370-2: Formula: (< v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 3487062#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 3487058#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 3487059#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 3487079#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 3486653#L389 [3286] L389-->L389-2: Formula: (> 1 v_~t5_pc~0_3) InVars {~t5_pc~0=v_~t5_pc~0_3} OutVars{~t5_pc~0=v_~t5_pc~0_3} AuxVars[] AssignedVars[] 3486620#L389-2 [2164] L389-2-->L400: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 3486621#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 3486650#L785 [2215] L785-->L785-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_6} AuxVars[] AssignedVars[] 3486669#L785-2 [3292] L785-2-->L669-1: Formula: (< 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 3486671#L669-1 [3294] L669-1-->L674-1: Formula: (< 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 3486872#L674-1 [3296] L674-1-->L679-1: Formula: (< 1 v_~T2_E~0_7) InVars {~T2_E~0=v_~T2_E~0_7} OutVars{~T2_E~0=v_~T2_E~0_7} AuxVars[] AssignedVars[] 3486873#L679-1 [3298] L679-1-->L684-1: Formula: (> v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 3486807#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 3486808#L689-1 [3302] L689-1-->L694-1: Formula: (> v_~T5_E~0_7 1) InVars {~T5_E~0=v_~T5_E~0_7} OutVars{~T5_E~0=v_~T5_E~0_7} AuxVars[] AssignedVars[] 3486978#L694-1 [3304] L694-1-->L699-1: Formula: (> v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 3486713#L699-1 [3306] L699-1-->L704-1: Formula: (> v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 3486714#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 3486564#L709-1 [3310] L709-1-->L714-1: Formula: (> v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 3486565#L714-1 [3313] L714-1-->L719-1: Formula: (> v_~E_4~0_9 1) InVars {~E_4~0=v_~E_4~0_9} OutVars{~E_4~0=v_~E_4~0_9} AuxVars[] AssignedVars[] 3486655#L719-1 [3314] L719-1-->L930-1: Formula: (> v_~E_5~0_9 1) InVars {~E_5~0=v_~E_5~0_9} OutVars{~E_5~0=v_~E_5~0_9} AuxVars[] AssignedVars[] 3486656#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 3565131#L576 312.69/160.51 [2019-03-28 12:23:33,900 INFO L796 eck$LassoCheckResult]: Loop: 3565131#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 3565126#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 3565125#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 3565121#L501 [3328] L501-->L501-1: Formula: (> v_ULTIMATE.start_eval_~tmp~0_4 0) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} OutVars{ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} AuxVars[] AssignedVars[] 3565117#L501-1 [2236] L501-1-->L509: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_2 |v_ULTIMATE.start_eval_#t~nondet2_3|) (= v_~m_st~0_9 0)) InVars {~m_st~0=v_~m_st~0_9, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_3|} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_2|, ~m_st~0=v_~m_st~0_9, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_1~0] 3565115#L509 [2460] L509-->L506: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} AuxVars[] AssignedVars[] 3565113#L506 [2670] L506-->L523: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_2 |v_ULTIMATE.start_eval_#t~nondet3_3|) (= 0 v_~t1_st~0_10)) InVars {ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_3|, ~t1_st~0=v_~t1_st~0_10} OutVars{ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_2|, ~t1_st~0=v_~t1_st~0_10, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_~tmp_ndt_2~0] 3565110#L523 [2255] L523-->L520: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} AuxVars[] AssignedVars[] 3565111#L520 [2457] L520-->L537: Formula: (and (= v_~t2_st~0_11 0) (= v_ULTIMATE.start_eval_~tmp_ndt_3~0_2 |v_ULTIMATE.start_eval_#t~nondet4_3|)) InVars {ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_3|, ~t2_st~0=v_~t2_st~0_11} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_2|, ~t2_st~0=v_~t2_st~0_11, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_~tmp_ndt_3~0] 3584882#L537 [2805] L537-->L534: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_3~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_5} AuxVars[] AssignedVars[] 3584880#L534 [2252] L534-->L551: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_4~0_2 |v_ULTIMATE.start_eval_#t~nondet5_3|) (= 0 v_~t3_st~0_12)) InVars {~t3_st~0=v_~t3_st~0_12, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_3|} OutVars{~t3_st~0=v_~t3_st~0_12, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_2, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_2|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_#t~nondet5] 3584877#L551 [2412] L551-->L548: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_4~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_5} AuxVars[] AssignedVars[] 3584875#L548 [2801] L548-->L565: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_5~0_2 |v_ULTIMATE.start_eval_#t~nondet6_3|) (= 0 v_~t4_st~0_13)) InVars {ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_3|, ~t4_st~0=v_~t4_st~0_13} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_2, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_2|, ~t4_st~0=v_~t4_st~0_13} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_#t~nondet6] 3584872#L565 [2213] L565-->L562: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_5~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_5} AuxVars[] AssignedVars[] 3565138#L562 [3387] L562-->L576: Formula: (> v_~t5_st~0_18 0) InVars {~t5_st~0=v_~t5_st~0_18} OutVars{~t5_st~0=v_~t5_st~0_18} AuxVars[] AssignedVars[] 3565131#L576 312.69/160.51 [2019-03-28 12:23:33,900 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.51 [2019-03-28 12:23:33,901 INFO L82 PathProgramCache]: Analyzing trace with hash 1548254319, now seen corresponding path program 10 times 312.69/160.51 [2019-03-28 12:23:33,901 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.51 [2019-03-28 12:23:33,901 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.51 [2019-03-28 12:23:33,901 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:23:33,902 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:23:33,902 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:23:33,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:23:33,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:23:33,914 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.51 [2019-03-28 12:23:33,915 INFO L82 PathProgramCache]: Analyzing trace with hash 122081429, now seen corresponding path program 1 times 312.69/160.51 [2019-03-28 12:23:33,915 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.51 [2019-03-28 12:23:33,915 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.51 [2019-03-28 12:23:33,915 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:23:33,916 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:23:33,916 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:23:33,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:23:33,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:23:33,920 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.51 [2019-03-28 12:23:33,920 INFO L82 PathProgramCache]: Analyzing trace with hash 639904359, now seen corresponding path program 1 times 312.69/160.51 [2019-03-28 12:23:33,920 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.51 [2019-03-28 12:23:33,920 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.51 [2019-03-28 12:23:33,921 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:23:33,921 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:23:33,921 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:23:33,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.51 [2019-03-28 12:23:33,941 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.51 [2019-03-28 12:23:33,942 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.51 [2019-03-28 12:23:33,942 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 312.69/160.51 [2019-03-28 12:23:34,061 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 312.69/160.51 [2019-03-28 12:23:34,061 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 312.69/160.51 [2019-03-28 12:23:34,061 INFO L87 Difference]: Start difference. First operand 319692 states and 457671 transitions. cyclomatic complexity: 137983 Second operand 3 states. 312.69/160.51 [2019-03-28 12:23:37,268 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.51 [2019-03-28 12:23:37,268 INFO L93 Difference]: Finished difference Result 518863 states and 747968 transitions. 312.69/160.51 [2019-03-28 12:23:37,269 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 312.69/160.51 [2019-03-28 12:23:37,269 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 518863 states and 747968 transitions. 312.69/160.51 [2019-03-28 12:23:39,812 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 518719 312.69/160.51 [2019-03-28 12:23:41,367 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 518863 states to 518863 states and 747968 transitions. 312.69/160.51 [2019-03-28 12:23:41,368 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 518863 312.69/160.51 [2019-03-28 12:23:41,726 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 518863 312.69/160.51 [2019-03-28 12:23:41,726 INFO L73 IsDeterministic]: Start isDeterministic. Operand 518863 states and 747968 transitions. 312.69/160.51 [2019-03-28 12:23:42,045 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.51 [2019-03-28 12:23:42,045 INFO L706 BuchiCegarLoop]: Abstraction has 518863 states and 747968 transitions. 312.69/160.51 [2019-03-28 12:23:42,314 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 518863 states and 747968 transitions. 312.69/160.51 [2019-03-28 12:23:54,034 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 518863 to 518863. 312.69/160.51 [2019-03-28 12:23:54,034 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 518863 states. 312.69/160.51 [2019-03-28 12:23:55,236 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 518863 states to 518863 states and 747968 transitions. 312.69/160.51 [2019-03-28 12:23:55,236 INFO L729 BuchiCegarLoop]: Abstraction has 518863 states and 747968 transitions. 312.69/160.51 [2019-03-28 12:23:55,236 INFO L609 BuchiCegarLoop]: Abstraction has 518863 states and 747968 transitions. 312.69/160.51 [2019-03-28 12:23:55,236 INFO L442 BuchiCegarLoop]: ======== Iteration 52============ 312.69/160.51 [2019-03-28 12:23:55,236 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 518863 states and 747968 transitions. 312.69/160.51 [2019-03-28 12:23:58,253 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 518719 312.69/160.51 [2019-03-28 12:23:58,253 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.51 [2019-03-28 12:23:58,253 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.51 [2019-03-28 12:23:58,254 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.51 [2019-03-28 12:23:58,254 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.51 [2019-03-28 12:23:58,255 INFO L794 eck$LassoCheckResult]: Stem: 4325537#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 4325332#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 4325333#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 4325405#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 4325406#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 4325336#L431-1 [2355] L431-1-->L436-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 4325337#L436-1 [3230] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_5 2) (< v_~t5_i~0_4 1)) InVars {~t5_i~0=v_~t5_i~0_4} OutVars{~t5_i~0=v_~t5_i~0_4, ~t5_st~0=v_~t5_st~0_5} AuxVars[] AssignedVars[~t5_st~0] 4325378#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 4325379#L601-1 [3235] L601-1-->L606-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 4325381#L606-1 [3236] L606-1-->L611-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 4325250#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 4325251#L616-1 [3240] L616-1-->L621-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 4325137#L621-1 [3242] L621-1-->L626-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 4325138#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 4325221#L631-1 [3246] L631-1-->L636-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 4325222#L636-1 [3248] L636-1-->L641-1: Formula: (> v_~E_2~0_4 0) InVars {~E_2~0=v_~E_2~0_4} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[] 4325430#L641-1 [3251] L641-1-->L646-1: Formula: (> v_~E_3~0_4 0) InVars {~E_3~0=v_~E_3~0_4} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[] 4325431#L646-1 [3253] L646-1-->L651-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 4325366#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 4325367#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 4325637#L294 [3256] L294-->L294-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 4325680#L294-2 [2905] L294-2-->L305: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 4325704#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 4325705#L745 [2925] L745-->L745-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_6) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} AuxVars[] AssignedVars[] 4325723#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 4325302#L313 [3262] L313-->L313-2: Formula: (< v_~t1_pc~0_3 1) InVars {~t1_pc~0=v_~t1_pc~0_3} OutVars{~t1_pc~0=v_~t1_pc~0_3} AuxVars[] AssignedVars[] 4325303#L313-2 [2314] L313-2-->L324: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 4325301#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 4325155#L753 [2130] L753-->L753-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} AuxVars[] AssignedVars[] 4325156#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 4325159#L332 [3268] L332-->L332-2: Formula: (< v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 4325342#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 4325340#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 4325341#L761 [2384] L761-->L761-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} AuxVars[] AssignedVars[] 4325362#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 4325363#L351 [3274] L351-->L351-2: Formula: (> 1 v_~t3_pc~0_3) InVars {~t3_pc~0=v_~t3_pc~0_3} OutVars{~t3_pc~0=v_~t3_pc~0_3} AuxVars[] AssignedVars[] 4325488#L351-2 [2543] L351-2-->L362: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 4325489#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 4325507#L769 [2585] L769-->L769-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} AuxVars[] AssignedVars[] 4325510#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 4325511#L370 [3280] L370-->L370-2: Formula: (< v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 4325617#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 4325615#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 4325616#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 4325635#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 4325213#L389 [3286] L389-->L389-2: Formula: (> 1 v_~t5_pc~0_3) InVars {~t5_pc~0=v_~t5_pc~0_3} OutVars{~t5_pc~0=v_~t5_pc~0_3} AuxVars[] AssignedVars[] 4325186#L389-2 [2164] L389-2-->L400: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 4325187#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 4325212#L785 [2215] L785-->L785-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_6} AuxVars[] AssignedVars[] 4325229#L785-2 [3292] L785-2-->L669-1: Formula: (< 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 4325230#L669-1 [3294] L669-1-->L674-1: Formula: (< 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 4325428#L674-1 [3296] L674-1-->L679-1: Formula: (< 1 v_~T2_E~0_7) InVars {~T2_E~0=v_~T2_E~0_7} OutVars{~T2_E~0=v_~T2_E~0_7} AuxVars[] AssignedVars[] 4325429#L679-1 [3298] L679-1-->L684-1: Formula: (> v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 4325364#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 4325365#L689-1 [3302] L689-1-->L694-1: Formula: (> v_~T5_E~0_7 1) InVars {~T5_E~0=v_~T5_E~0_7} OutVars{~T5_E~0=v_~T5_E~0_7} AuxVars[] AssignedVars[] 4325529#L694-1 [3304] L694-1-->L699-1: Formula: (> v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 4325272#L699-1 [3306] L699-1-->L704-1: Formula: (> v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 4325273#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 4325127#L709-1 [3310] L709-1-->L714-1: Formula: (> v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 4325128#L714-1 [3313] L714-1-->L719-1: Formula: (> v_~E_4~0_9 1) InVars {~E_4~0=v_~E_4~0_9} OutVars{~E_4~0=v_~E_4~0_9} AuxVars[] AssignedVars[] 4325215#L719-1 [3314] L719-1-->L930-1: Formula: (> v_~E_5~0_9 1) InVars {~E_5~0=v_~E_5~0_9} OutVars{~E_5~0=v_~E_5~0_9} AuxVars[] AssignedVars[] 4325216#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 4559465#L576 312.69/160.51 [2019-03-28 12:23:58,255 INFO L796 eck$LassoCheckResult]: Loop: 4559465#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 4559461#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 4559459#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 4559457#L501 [3328] L501-->L501-1: Formula: (> v_ULTIMATE.start_eval_~tmp~0_4 0) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} OutVars{ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} AuxVars[] AssignedVars[] 4559453#L501-1 [2236] L501-1-->L509: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_2 |v_ULTIMATE.start_eval_#t~nondet2_3|) (= v_~m_st~0_9 0)) InVars {~m_st~0=v_~m_st~0_9, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_3|} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_2|, ~m_st~0=v_~m_st~0_9, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_1~0] 4559450#L509 [2460] L509-->L506: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} AuxVars[] AssignedVars[] 4559448#L506 [2670] L506-->L523: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_2 |v_ULTIMATE.start_eval_#t~nondet3_3|) (= 0 v_~t1_st~0_10)) InVars {ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_3|, ~t1_st~0=v_~t1_st~0_10} OutVars{ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_2|, ~t1_st~0=v_~t1_st~0_10, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_~tmp_ndt_2~0] 4559444#L523 [2255] L523-->L520: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} AuxVars[] AssignedVars[] 4559446#L520 [2457] L520-->L537: Formula: (and (= v_~t2_st~0_11 0) (= v_ULTIMATE.start_eval_~tmp_ndt_3~0_2 |v_ULTIMATE.start_eval_#t~nondet4_3|)) InVars {ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_3|, ~t2_st~0=v_~t2_st~0_11} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_2|, ~t2_st~0=v_~t2_st~0_11, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_~tmp_ndt_3~0] 4559478#L537 [2805] L537-->L534: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_3~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_5} AuxVars[] AssignedVars[] 4559476#L534 [2252] L534-->L551: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_4~0_2 |v_ULTIMATE.start_eval_#t~nondet5_3|) (= 0 v_~t3_st~0_12)) InVars {~t3_st~0=v_~t3_st~0_12, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_3|} OutVars{~t3_st~0=v_~t3_st~0_12, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_2, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_2|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_#t~nondet5] 4559474#L551 [2412] L551-->L548: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_4~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_5} AuxVars[] AssignedVars[] 4559472#L548 [2801] L548-->L565: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_5~0_2 |v_ULTIMATE.start_eval_#t~nondet6_3|) (= 0 v_~t4_st~0_13)) InVars {ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_3|, ~t4_st~0=v_~t4_st~0_13} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_2, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_2|, ~t4_st~0=v_~t4_st~0_13} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_#t~nondet6] 4559469#L565 [2213] L565-->L562: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_5~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_5} AuxVars[] AssignedVars[] 4559467#L562 [3387] L562-->L576: Formula: (> v_~t5_st~0_18 0) InVars {~t5_st~0=v_~t5_st~0_18} OutVars{~t5_st~0=v_~t5_st~0_18} AuxVars[] AssignedVars[] 4559465#L576 312.69/160.51 [2019-03-28 12:23:58,255 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.51 [2019-03-28 12:23:58,256 INFO L82 PathProgramCache]: Analyzing trace with hash -1269646944, now seen corresponding path program 1 times 312.69/160.51 [2019-03-28 12:23:58,256 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.51 [2019-03-28 12:23:58,256 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.51 [2019-03-28 12:23:58,256 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:23:58,257 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:23:58,257 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:23:58,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 312.69/160.51 [2019-03-28 12:23:58,268 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 312.69/160.51 [2019-03-28 12:23:58,268 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 312.69/160.51 [2019-03-28 12:23:58,269 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 312.69/160.51 [2019-03-28 12:23:58,269 INFO L799 eck$LassoCheckResult]: stem already infeasible 312.69/160.51 [2019-03-28 12:23:58,269 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.51 [2019-03-28 12:23:58,269 INFO L82 PathProgramCache]: Analyzing trace with hash 122081429, now seen corresponding path program 2 times 312.69/160.51 [2019-03-28 12:23:58,269 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.51 [2019-03-28 12:23:58,269 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.51 [2019-03-28 12:23:58,270 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:23:58,270 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:23:58,270 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:23:58,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:23:58,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:23:58,374 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 312.69/160.51 [2019-03-28 12:23:58,374 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 312.69/160.51 [2019-03-28 12:23:58,374 INFO L87 Difference]: Start difference. First operand 518863 states and 747968 transitions. cyclomatic complexity: 229110 Second operand 3 states. 312.69/160.51 [2019-03-28 12:24:00,388 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 312.69/160.51 [2019-03-28 12:24:00,388 INFO L93 Difference]: Finished difference Result 518780 states and 747861 transitions. 312.69/160.51 [2019-03-28 12:24:00,389 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 312.69/160.51 [2019-03-28 12:24:00,389 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 518780 states and 747861 transitions. 312.69/160.51 [2019-03-28 12:24:03,033 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 518704 312.69/160.51 [2019-03-28 12:24:04,694 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 518780 states to 518780 states and 747861 transitions. 312.69/160.51 [2019-03-28 12:24:04,694 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 518780 312.69/160.51 [2019-03-28 12:24:05,088 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 518780 312.69/160.51 [2019-03-28 12:24:05,088 INFO L73 IsDeterministic]: Start isDeterministic. Operand 518780 states and 747861 transitions. 312.69/160.51 [2019-03-28 12:24:05,435 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 312.69/160.51 [2019-03-28 12:24:05,436 INFO L706 BuchiCegarLoop]: Abstraction has 518780 states and 747861 transitions. 312.69/160.51 [2019-03-28 12:24:05,729 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 518780 states and 747861 transitions. 312.69/160.51 [2019-03-28 12:24:19,000 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 518780 to 518780. 312.69/160.51 [2019-03-28 12:24:19,000 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 518780 states. 312.69/160.51 [2019-03-28 12:24:20,203 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 518780 states to 518780 states and 747861 transitions. 312.69/160.51 [2019-03-28 12:24:20,203 INFO L729 BuchiCegarLoop]: Abstraction has 518780 states and 747861 transitions. 312.69/160.51 [2019-03-28 12:24:20,203 INFO L609 BuchiCegarLoop]: Abstraction has 518780 states and 747861 transitions. 312.69/160.51 [2019-03-28 12:24:20,204 INFO L442 BuchiCegarLoop]: ======== Iteration 53============ 312.69/160.51 [2019-03-28 12:24:20,204 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 518780 states and 747861 transitions. 312.69/160.51 [2019-03-28 12:24:23,179 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 518704 312.69/160.51 [2019-03-28 12:24:23,180 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 312.69/160.51 [2019-03-28 12:24:23,190 INFO L119 BuchiIsEmpty]: Starting construction of run 312.69/160.51 [2019-03-28 12:24:23,191 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.51 [2019-03-28 12:24:23,191 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 312.69/160.51 [2019-03-28 12:24:23,192 INFO L794 eck$LassoCheckResult]: Stem: 5363203#ULTIMATE.startENTRY [3773] ULTIMATE.startENTRY-->L409: Formula: (and (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= 0 v_~token~0_16) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~M_E~0_19 2) (= v_~m_i~0_7 1) (= v_~local~0_6 0) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_M~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~M_E~0=v_~M_E~0_19, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ~token~0=v_~token~0_16, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ULTIMATE.start_start_simulation_#t~ret15=|v_ULTIMATE.start_start_simulation_#t~ret15_4|, ~T4_E~0=v_~T4_E~0_18, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ~T2_E~0=v_~T2_E~0_18, ULTIMATE.start_main_~__retres1~7=v_ULTIMATE.start_main_~__retres1~7_6, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_M~0=v_~E_M~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~local~0=v_~local~0_6, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t5_i~0, ~t1_pc~0, ~t5_st~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ~token~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_#t~ret15, ~T4_E~0, ~t2_st~0, ~t2_pc~0, ~T2_E~0, ULTIMATE.start_main_~__retres1~7, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_M~0, ULTIMATE.start_main_#res, ~E_2~0, ~local~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 5362986#L409 [2353] L409-->L416-1: Formula: (and (= v_~m_st~0_4 0) (= v_~m_i~0_3 1)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_4, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 5362987#L416-1 [2811] L416-1-->L421-1: Formula: (and (= v_~t1_st~0_4 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_4, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 5363061#L421-1 [2436] L421-1-->L426-1: Formula: (and (= 1 v_~t2_i~0_3) (= v_~t2_st~0_4 0)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_4} AuxVars[] AssignedVars[~t2_st~0] 5363062#L426-1 [2873] L426-1-->L431-1: Formula: (and (= v_~t3_i~0_3 1) (= v_~t3_st~0_4 0)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 5362990#L431-1 [2355] L431-1-->L436-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 5362991#L436-1 [2735] L436-1-->L441-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 5363034#L441-1 [3233] L441-1-->L601-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 5363035#L601-1 [3235] L601-1-->L606-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 5363037#L606-1 [3236] L606-1-->L611-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 5362898#L611-1 [3239] L611-1-->L616-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 5362899#L616-1 [3240] L616-1-->L621-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 5362786#L621-1 [3242] L621-1-->L626-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 5362787#L626-1 [3245] L626-1-->L631-1: Formula: (> v_~E_M~0_4 0) InVars {~E_M~0=v_~E_M~0_4} OutVars{~E_M~0=v_~E_M~0_4} AuxVars[] AssignedVars[] 5362871#L631-1 [3246] L631-1-->L636-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 5362872#L636-1 [3248] L636-1-->L641-1: Formula: (> v_~E_2~0_4 0) InVars {~E_2~0=v_~E_2~0_4} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[] 5363088#L641-1 [3251] L641-1-->L646-1: Formula: (> v_~E_3~0_4 0) InVars {~E_3~0=v_~E_3~0_4} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[] 5363089#L646-1 [3253] L646-1-->L651-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 5363021#L651-1 [3255] L651-1-->L656-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 5363022#L656-1 [2784] L656-1-->L294: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_1|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_1, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_1, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_1|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_1|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_1|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_1|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_1, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_1} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 5363301#L294 [3256] L294-->L294-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 5363344#L294-2 [2905] L294-2-->L305: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 5363366#L305 [3774] L305-->L745: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 5363367#L745 [2925] L745-->L745-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_6) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6} AuxVars[] AssignedVars[] 5363383#L745-2 [2929] L745-2-->L313: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 5362952#L313 [3262] L313-->L313-2: Formula: (< v_~t1_pc~0_3 1) InVars {~t1_pc~0=v_~t1_pc~0_3} OutVars{~t1_pc~0=v_~t1_pc~0_3} AuxVars[] AssignedVars[] 5362953#L313-2 [2314] L313-2-->L324: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 5362951#L324 [3775] L324-->L753: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 5362802#L753 [2130] L753-->L753-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_6} AuxVars[] AssignedVars[] 5362803#L753-2 [2134] L753-2-->L332: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_1|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 5362805#L332 [3268] L332-->L332-2: Formula: (< v_~t2_pc~0_3 1) InVars {~t2_pc~0=v_~t2_pc~0_3} OutVars{~t2_pc~0=v_~t2_pc~0_3} AuxVars[] AssignedVars[] 5362996#L332-2 [2367] L332-2-->L343: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 5362994#L343 [3776] L343-->L761: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 5362995#L761 [2384] L761-->L761-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___1~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_6} AuxVars[] AssignedVars[] 5363016#L761-2 [2385] L761-2-->L351: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_1|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 5363017#L351 [3274] L351-->L351-2: Formula: (> 1 v_~t3_pc~0_3) InVars {~t3_pc~0=v_~t3_pc~0_3} OutVars{~t3_pc~0=v_~t3_pc~0_3} AuxVars[] AssignedVars[] 5363151#L351-2 [2543] L351-2-->L362: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 5363152#L362 [3777] L362-->L769: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 5363173#L769 [2585] L769-->L769-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___2~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_6} AuxVars[] AssignedVars[] 5363177#L769-2 [2586] L769-2-->L370: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_1, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 5363178#L370 [3280] L370-->L370-2: Formula: (< v_~t4_pc~0_3 1) InVars {~t4_pc~0=v_~t4_pc~0_3} OutVars{~t4_pc~0=v_~t4_pc~0_3} AuxVars[] AssignedVars[] 5363281#L370-2 [2752] L370-2-->L381: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 5363279#L381 [3778] L381-->L777: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 5363280#L777 [2778] L777-->L777-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___3~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_6} AuxVars[] AssignedVars[] 5363299#L777-2 [2779] L777-2-->L389: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_1|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_1} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 5362861#L389 [3286] L389-->L389-2: Formula: (> 1 v_~t5_pc~0_3) InVars {~t5_pc~0=v_~t5_pc~0_3} OutVars{~t5_pc~0=v_~t5_pc~0_3} AuxVars[] AssignedVars[] 5362831#L389-2 [2164] L389-2-->L400: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 5362832#L400 [3779] L400-->L785: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 5362859#L785 [2215] L785-->L785-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___4~0_6) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_6} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_6} AuxVars[] AssignedVars[] 5362879#L785-2 [3292] L785-2-->L669-1: Formula: (< 1 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 5362880#L669-1 [3294] L669-1-->L674-1: Formula: (< 1 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 5363086#L674-1 [3296] L674-1-->L679-1: Formula: (< 1 v_~T2_E~0_7) InVars {~T2_E~0=v_~T2_E~0_7} OutVars{~T2_E~0=v_~T2_E~0_7} AuxVars[] AssignedVars[] 5363087#L679-1 [3298] L679-1-->L684-1: Formula: (> v_~T3_E~0_7 1) InVars {~T3_E~0=v_~T3_E~0_7} OutVars{~T3_E~0=v_~T3_E~0_7} AuxVars[] AssignedVars[] 5363019#L684-1 [3301] L684-1-->L689-1: Formula: (> v_~T4_E~0_7 1) InVars {~T4_E~0=v_~T4_E~0_7} OutVars{~T4_E~0=v_~T4_E~0_7} AuxVars[] AssignedVars[] 5363020#L689-1 [3302] L689-1-->L694-1: Formula: (> v_~T5_E~0_7 1) InVars {~T5_E~0=v_~T5_E~0_7} OutVars{~T5_E~0=v_~T5_E~0_7} AuxVars[] AssignedVars[] 5363196#L694-1 [3304] L694-1-->L699-1: Formula: (> v_~E_M~0_9 1) InVars {~E_M~0=v_~E_M~0_9} OutVars{~E_M~0=v_~E_M~0_9} AuxVars[] AssignedVars[] 5362920#L699-1 [3306] L699-1-->L704-1: Formula: (> v_~E_1~0_9 1) InVars {~E_1~0=v_~E_1~0_9} OutVars{~E_1~0=v_~E_1~0_9} AuxVars[] AssignedVars[] 5362921#L704-1 [3309] L704-1-->L709-1: Formula: (> v_~E_2~0_9 1) InVars {~E_2~0=v_~E_2~0_9} OutVars{~E_2~0=v_~E_2~0_9} AuxVars[] AssignedVars[] 5362776#L709-1 [3310] L709-1-->L714-1: Formula: (> v_~E_3~0_9 1) InVars {~E_3~0=v_~E_3~0_9} OutVars{~E_3~0=v_~E_3~0_9} AuxVars[] AssignedVars[] 5362777#L714-1 [3313] L714-1-->L719-1: Formula: (> v_~E_4~0_9 1) InVars {~E_4~0=v_~E_4~0_9} OutVars{~E_4~0=v_~E_4~0_9} AuxVars[] AssignedVars[] 5362863#L719-1 [3314] L719-1-->L930-1: Formula: (> v_~E_5~0_9 1) InVars {~E_5~0=v_~E_5~0_9} OutVars{~E_5~0=v_~E_5~0_9} AuxVars[] AssignedVars[] 5362864#L930-1 [3780] L930-1-->L576: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret1] 5469968#L576 312.69/160.51 [2019-03-28 12:24:23,192 INFO L796 eck$LassoCheckResult]: Loop: 5469968#L576 [3781] L576-->L454: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_34} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~6] 5470005#L454 [2463] L454-->L486: Formula: (and (= v_~m_st~0_7 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15 1)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_15} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~6] 5470004#L486 [3782] L486-->L501: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_#t~ret1=|v_ULTIMATE.start_eval_#t~ret1_5|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~6=v_ULTIMATE.start_exists_runnable_thread_~__retres1~6_35} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret1, ULTIMATE.start_eval_~tmp~0] 5470003#L501 [3328] L501-->L501-1: Formula: (> v_ULTIMATE.start_eval_~tmp~0_4 0) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} OutVars{ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} AuxVars[] AssignedVars[] 5470000#L501-1 [2236] L501-1-->L509: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_2 |v_ULTIMATE.start_eval_#t~nondet2_3|) (= v_~m_st~0_9 0)) InVars {~m_st~0=v_~m_st~0_9, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_3|} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_2|, ~m_st~0=v_~m_st~0_9, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_1~0] 5469997#L509 [2460] L509-->L506: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} AuxVars[] AssignedVars[] 5469995#L506 [2670] L506-->L523: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_2 |v_ULTIMATE.start_eval_#t~nondet3_3|) (= 0 v_~t1_st~0_10)) InVars {ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_3|, ~t1_st~0=v_~t1_st~0_10} OutVars{ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_2|, ~t1_st~0=v_~t1_st~0_10, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_~tmp_ndt_2~0] 5469991#L523 [2255] L523-->L520: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} AuxVars[] AssignedVars[] 5469988#L520 [2457] L520-->L537: Formula: (and (= v_~t2_st~0_11 0) (= v_ULTIMATE.start_eval_~tmp_ndt_3~0_2 |v_ULTIMATE.start_eval_#t~nondet4_3|)) InVars {ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_3|, ~t2_st~0=v_~t2_st~0_11} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_2|, ~t2_st~0=v_~t2_st~0_11, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_~tmp_ndt_3~0] 5469984#L537 [2805] L537-->L534: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_3~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_5} AuxVars[] AssignedVars[] 5469981#L534 [2252] L534-->L551: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_4~0_2 |v_ULTIMATE.start_eval_#t~nondet5_3|) (= 0 v_~t3_st~0_12)) InVars {~t3_st~0=v_~t3_st~0_12, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_3|} OutVars{~t3_st~0=v_~t3_st~0_12, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_2, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_2|} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_#t~nondet5] 5469978#L551 [2412] L551-->L548: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_4~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_5} AuxVars[] AssignedVars[] 5469976#L548 [2801] L548-->L565: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_5~0_2 |v_ULTIMATE.start_eval_#t~nondet6_3|) (= 0 v_~t4_st~0_13)) InVars {ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_3|, ~t4_st~0=v_~t4_st~0_13} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_2, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_2|, ~t4_st~0=v_~t4_st~0_13} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_#t~nondet6] 5469974#L565 [2213] L565-->L562: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_5~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_5} AuxVars[] AssignedVars[] 5469971#L562 [2409] L562-->L579: Formula: (and (= v_~t5_st~0_14 0) (= v_ULTIMATE.start_eval_~tmp_ndt_6~0_2 |v_ULTIMATE.start_eval_#t~nondet7_3|)) InVars {ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_3|, ~t5_st~0=v_~t5_st~0_14} OutVars{ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_2, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_2|, ~t5_st~0=v_~t5_st~0_14} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_eval_#t~nondet7] 5469967#L579 [2762] L579-->L576: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_6~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_5} AuxVars[] AssignedVars[] 5469968#L576 312.69/160.51 [2019-03-28 12:24:23,193 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.51 [2019-03-28 12:24:23,193 INFO L82 PathProgramCache]: Analyzing trace with hash 1548254319, now seen corresponding path program 11 times 312.69/160.51 [2019-03-28 12:24:23,193 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.51 [2019-03-28 12:24:23,193 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.51 [2019-03-28 12:24:23,194 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:24:23,194 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:24:23,194 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:24:23,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:24:23,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:24:23,206 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.51 [2019-03-28 12:24:23,206 INFO L82 PathProgramCache]: Analyzing trace with hash -510470553, now seen corresponding path program 1 times 312.69/160.51 [2019-03-28 12:24:23,206 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.51 [2019-03-28 12:24:23,207 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.51 [2019-03-28 12:24:23,207 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:24:23,207 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:24:23,207 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:24:23,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:24:23,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:24:23,211 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 312.69/160.51 [2019-03-28 12:24:23,212 INFO L82 PathProgramCache]: Analyzing trace with hash -1637828907, now seen corresponding path program 1 times 312.69/160.51 [2019-03-28 12:24:23,212 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 312.69/160.51 [2019-03-28 12:24:23,212 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 312.69/160.51 [2019-03-28 12:24:23,212 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:24:23,212 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:24:23,213 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 312.69/160.51 [2019-03-28 12:24:23,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:24:23,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 312.69/160.51 [2019-03-28 12:24:23,817 WARN L188 SmtUtils]: Spent 475.00 ms on a formula simplification. DAG size of input: 156 DAG size of output: 120 312.69/160.51 [2019-03-28 12:24:23,952 WARN L188 SmtUtils]: Spent 132.00 ms on a formula simplification that was a NOOP. DAG size: 106 312.69/160.51 [2019-03-28 12:24:23,992 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 28.03 12:24:23 BasicIcfg 312.69/160.51 [2019-03-28 12:24:23,992 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- 312.69/160.51 [2019-03-28 12:24:23,993 INFO L168 Benchmark]: Toolchain (without parser) took 156098.54 ms. Allocated memory was 649.6 MB in the beginning and 11.9 GB in the end (delta: 11.3 GB). Free memory was 563.5 MB in the beginning and 6.3 GB in the end (delta: -5.7 GB). Peak memory consumption was 5.6 GB. Max. memory is 50.3 GB. 312.69/160.51 [2019-03-28 12:24:23,994 INFO L168 Benchmark]: CDTParser took 0.17 ms. Allocated memory is still 649.6 MB. Free memory is still 585.4 MB. There was no memory consumed. Max. memory is 50.3 GB. 312.69/160.51 [2019-03-28 12:24:23,994 INFO L168 Benchmark]: CACSL2BoogieTranslator took 446.93 ms. Allocated memory was 649.6 MB in the beginning and 677.4 MB in the end (delta: 27.8 MB). Free memory was 562.5 MB in the beginning and 633.8 MB in the end (delta: -71.3 MB). Peak memory consumption was 32.3 MB. Max. memory is 50.3 GB. 312.69/160.51 [2019-03-28 12:24:23,994 INFO L168 Benchmark]: Boogie Procedure Inliner took 81.08 ms. Allocated memory is still 677.4 MB. Free memory was 633.8 MB in the beginning and 625.1 MB in the end (delta: 8.6 MB). Peak memory consumption was 8.6 MB. Max. memory is 50.3 GB. 312.69/160.51 [2019-03-28 12:24:23,995 INFO L168 Benchmark]: Boogie Preprocessor took 69.48 ms. Allocated memory is still 677.4 MB. Free memory was 625.1 MB in the beginning and 617.5 MB in the end (delta: 7.7 MB). Peak memory consumption was 7.7 MB. Max. memory is 50.3 GB. 312.69/160.51 [2019-03-28 12:24:23,996 INFO L168 Benchmark]: RCFGBuilder took 1347.13 ms. Allocated memory is still 677.4 MB. Free memory was 617.5 MB in the beginning and 487.3 MB in the end (delta: 130.2 MB). Peak memory consumption was 130.2 MB. Max. memory is 50.3 GB. 312.69/160.51 [2019-03-28 12:24:23,996 INFO L168 Benchmark]: BlockEncodingV2 took 381.42 ms. Allocated memory is still 677.4 MB. Free memory was 487.3 MB in the beginning and 419.6 MB in the end (delta: 67.7 MB). Peak memory consumption was 67.7 MB. Max. memory is 50.3 GB. 312.69/160.51 [2019-03-28 12:24:23,996 INFO L168 Benchmark]: TraceAbstraction took 404.61 ms. Allocated memory was 677.4 MB in the beginning and 758.1 MB in the end (delta: 80.7 MB). Free memory was 418.5 MB in the beginning and 687.6 MB in the end (delta: -269.1 MB). Peak memory consumption was 55.7 MB. Max. memory is 50.3 GB. 312.69/160.51 [2019-03-28 12:24:23,997 INFO L168 Benchmark]: BuchiAutomizer took 153362.62 ms. Allocated memory was 758.1 MB in the beginning and 11.9 GB in the end (delta: 11.2 GB). Free memory was 687.6 MB in the beginning and 6.3 GB in the end (delta: -5.6 GB). Peak memory consumption was 5.6 GB. Max. memory is 50.3 GB. 312.69/160.51 [2019-03-28 12:24:24,001 INFO L337 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### 312.69/160.51 --- Results --- 312.69/160.51 * Results from de.uni_freiburg.informatik.ultimate.plugins.blockencoding: 312.69/160.51 - StatisticsResult: Initial Icfg 312.69/160.51 538 locations, 833 edges 312.69/160.51 - StatisticsResult: Encoded RCFG 312.69/160.51 454 locations, 1005 edges 312.69/160.51 * Results from de.uni_freiburg.informatik.ultimate.core: 312.69/160.51 - StatisticsResult: Toolchain Benchmarks 312.69/160.51 Benchmark results are: 312.69/160.51 * CDTParser took 0.17 ms. Allocated memory is still 649.6 MB. Free memory is still 585.4 MB. There was no memory consumed. Max. memory is 50.3 GB. 312.69/160.51 * CACSL2BoogieTranslator took 446.93 ms. Allocated memory was 649.6 MB in the beginning and 677.4 MB in the end (delta: 27.8 MB). Free memory was 562.5 MB in the beginning and 633.8 MB in the end (delta: -71.3 MB). Peak memory consumption was 32.3 MB. Max. memory is 50.3 GB. 312.69/160.51 * Boogie Procedure Inliner took 81.08 ms. Allocated memory is still 677.4 MB. Free memory was 633.8 MB in the beginning and 625.1 MB in the end (delta: 8.6 MB). Peak memory consumption was 8.6 MB. Max. memory is 50.3 GB. 312.69/160.51 * Boogie Preprocessor took 69.48 ms. Allocated memory is still 677.4 MB. Free memory was 625.1 MB in the beginning and 617.5 MB in the end (delta: 7.7 MB). Peak memory consumption was 7.7 MB. Max. memory is 50.3 GB. 312.69/160.51 * RCFGBuilder took 1347.13 ms. Allocated memory is still 677.4 MB. Free memory was 617.5 MB in the beginning and 487.3 MB in the end (delta: 130.2 MB). Peak memory consumption was 130.2 MB. Max. memory is 50.3 GB. 312.69/160.51 * BlockEncodingV2 took 381.42 ms. Allocated memory is still 677.4 MB. Free memory was 487.3 MB in the beginning and 419.6 MB in the end (delta: 67.7 MB). Peak memory consumption was 67.7 MB. Max. memory is 50.3 GB. 312.69/160.51 * TraceAbstraction took 404.61 ms. Allocated memory was 677.4 MB in the beginning and 758.1 MB in the end (delta: 80.7 MB). Free memory was 418.5 MB in the beginning and 687.6 MB in the end (delta: -269.1 MB). Peak memory consumption was 55.7 MB. Max. memory is 50.3 GB. 312.69/160.51 * BuchiAutomizer took 153362.62 ms. Allocated memory was 758.1 MB in the beginning and 11.9 GB in the end (delta: 11.2 GB). Free memory was 687.6 MB in the beginning and 6.3 GB in the end (delta: -5.6 GB). Peak memory consumption was 5.6 GB. Max. memory is 50.3 GB. 312.69/160.51 * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: 312.69/160.51 - AllSpecificationsHoldResult: All specifications hold 312.69/160.51 We were not able to verify any specifiation because the program does not contain any specification. 312.69/160.51 - InvariantResult [Line: 496]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 350]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 453]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 416]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 350]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 350]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 331]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 331]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 331]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 350]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 350]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 350]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 665]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 453]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 350]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 350]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 453]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 153]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 185]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 369]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 369]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 113]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 369]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 818]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 496]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 369]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 501]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 369]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 350]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 388]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 293]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 117]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: -1]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 149]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 496]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 388]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 369]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 1]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 369]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 369]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 369]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 669]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 900]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 293]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 261]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 388]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 1]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 293]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 597]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 388]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 293]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 388]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 665]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 293]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 388]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 1]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 293]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 388]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 949]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 1]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 312]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 312]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 312]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 293]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 1]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 388]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 293]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 496]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 597]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 293]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 388]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 312]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 312]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 601]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 312]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 1]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 312]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 61]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 189]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 221]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 312]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 496]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 57]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 949]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 312]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 331]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 331]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 496]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 225]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 331]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 257]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 331]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 331]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 669]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - InvariantResult [Line: 331]: Loop Invariant 312.69/160.51 Derived loop invariant: 1 312.69/160.51 - StatisticsResult: Ultimate Automizer benchmark data 312.69/160.51 CFG has 1 procedures, 454 locations, 0 error locations. SAFE Result, 0.3s OverallTime, 0 OverallIterations, 0 TraceHistogramMax, 0.0s AutomataDifference, 0.0s DeadEndRemovalTime, 0.1s HoareAnnotationTime, HoareTripleCheckerStatistics: No data available, PredicateUnifierStatistics: No data available, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=454occurred in iteration=0, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: No data available, HoareAnnotationStatistics: 0.0s HoareAnnotationTime, 95 LocationsWithAnnotation, 95 PreInvPairs, 95 NumberOfFragments, 95 HoareAnnotationTreeSize, 95 FomulaSimplifications, 0 FormulaSimplificationTreeSizeReduction, 0.0s HoareSimplificationTime, 95 FomulaSimplificationsInter, 0 FormulaSimplificationTreeSizeReductionInter, 0.0s HoareSimplificationTimeInter, RefinementEngineStatistics: No data available, ReuseStatistics: No data available 312.69/160.51 - StatisticsResult: Constructed decomposition of program 312.69/160.51 Your program was decomposed into 52 terminating modules (52 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.52 modules have a trivial ranking function, the largest among these consists of 6 locations. The remainder module has 518780 locations. 312.69/160.51 - StatisticsResult: Timing statistics 312.69/160.51 BüchiAutomizer plugin needed 153.3s and 53 iterations. TraceHistogramMax:1. Analysis of lassos took 5.0s. Construction of modules took 25.3s. Büchi inclusion checks took 18.0s. Highest rank in rank-based complementation 0. Minimization of det autom 52. Minimization of nondet autom 0. Automata minimization 59.4s AutomataMinimizationTime, 52 MinimizatonAttempts, 73098 StatesRemovedByMinimization, 19 NontrivialMinimizations. Non-live state removal took 23.5s Buchi closure took 3.3s. Biggest automaton had 518863 states and ocurred in iteration 51. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 20605 SDtfs, 72266 SDslu, 22682 SDs, 0 SdLazy, 36746 SolverSat, 1340 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 25.3s Time LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc10 concLT0 SILN3 SILU0 SILI36 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s 312.69/160.51 - TerminationAnalysisResult: Nontermination possible 312.69/160.51 Buchi Automizer proved that your program is nonterminating for some inputs 312.69/160.51 - FixpointNonTerminationResult [Line: 496]: Nontermination argument in form of an infinite program execution. 312.69/160.51 Nontermination argument in form of an infinite execution 312.69/160.51 State at position 0 is 312.69/160.51 {} 312.69/160.51 State at position 1 is 312.69/160.51 {__retres1=0, t3_st=0, token=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@33617e8e=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2a9c6042=0, tmp=1, t5_i=1, __retres1=0, kernel_st=1, t2_st=0, t4_i=1, E_3=2, t4_pc=0, E_5=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2d9c87fb=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2087a97b=0, E_1=2, tmp_ndt_2=0, \result=0, __retres1=0, \result=0, tmp_ndt_4=0, tmp_ndt_6=0, m_st=0, tmp___2=0, tmp___0=0, t3_pc=0, tmp=0, \result=0, __retres1=0, m_pc=0, tmp___4=0, \result=0, __retres1=0, \result=0, __retres1=0, \result=0, T2_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@701cdef8=0, tmp___0=0, t1_pc=0, t5_st=0, __retres1=1, E_2=2, E_4=2, T1_E=2, tmp_ndt_1=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, T5_E=2, t2_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@991b1ca=0, T4_E=2, t3_i=1, t4_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6a78f012=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5a8b7bd4=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2fbc236e=0, t1_st=0, tmp_ndt_5=0, t5_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@462cc225=0, local=0, t2_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@477854c5=0, tmp___3=0, E_M=2, tmp___1=0, T3_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@110c7f96=0, t1_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3d08f5d5=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@50a40845=0, \result=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@41fcc3c8=0} 312.69/160.51 - StatisticsResult: NonterminationArgumentStatistics 312.69/160.51 Fixpoint 312.69/160.51 - NonterminatingLassoResult [Line: 496]: Nonterminating execution 312.69/160.51 Found a nonterminating execution for the following lasso shaped sequence of statements. 312.69/160.51 Stem: 312.69/160.51 [L14] int m_pc = 0; 312.69/160.51 [L15] int t1_pc = 0; 312.69/160.51 [L16] int t2_pc = 0; 312.69/160.51 [L17] int t3_pc = 0; 312.69/160.51 [L18] int t4_pc = 0; 312.69/160.51 [L19] int t5_pc = 0; 312.69/160.51 [L20] int m_st ; 312.69/160.51 [L21] int t1_st ; 312.69/160.51 [L22] int t2_st ; 312.69/160.51 [L23] int t3_st ; 312.69/160.51 [L24] int t4_st ; 312.69/160.51 [L25] int t5_st ; 312.69/160.51 [L26] int m_i ; 312.69/160.51 [L27] int t1_i ; 312.69/160.51 [L28] int t2_i ; 312.69/160.51 [L29] int t3_i ; 312.69/160.51 [L30] int t4_i ; 312.69/160.51 [L31] int t5_i ; 312.69/160.51 [L32] int M_E = 2; 312.69/160.51 [L33] int T1_E = 2; 312.69/160.51 [L34] int T2_E = 2; 312.69/160.51 [L35] int T3_E = 2; 312.69/160.51 [L36] int T4_E = 2; 312.69/160.51 [L37] int T5_E = 2; 312.69/160.51 [L38] int E_M = 2; 312.69/160.51 [L39] int E_1 = 2; 312.69/160.51 [L40] int E_2 = 2; 312.69/160.51 [L41] int E_3 = 2; 312.69/160.51 [L42] int E_4 = 2; 312.69/160.51 [L43] int E_5 = 2; 312.69/160.51 [L51] int token ; 312.69/160.51 [L53] int local ; 312.69/160.51 [L975] int __retres1 ; 312.69/160.51 [L886] m_i = 1 312.69/160.51 [L887] t1_i = 1 312.69/160.51 [L888] t2_i = 1 312.69/160.51 [L889] t3_i = 1 312.69/160.51 [L890] t4_i = 1 312.69/160.51 [L891] t5_i = 1 312.69/160.51 [L916] int kernel_st ; 312.69/160.51 [L917] int tmp ; 312.69/160.51 [L918] int tmp___0 ; 312.69/160.51 [L922] kernel_st = 0 312.69/160.51 [L416] COND TRUE m_i == 1 312.69/160.51 [L417] m_st = 0 312.69/160.51 [L421] COND TRUE t1_i == 1 312.69/160.51 [L422] t1_st = 0 312.69/160.51 [L426] COND TRUE t2_i == 1 312.69/160.51 [L427] t2_st = 0 312.69/160.51 [L431] COND TRUE t3_i == 1 312.69/160.51 [L432] t3_st = 0 312.69/160.51 [L436] COND TRUE t4_i == 1 312.69/160.51 [L437] t4_st = 0 312.69/160.51 [L441] COND TRUE t5_i == 1 312.69/160.51 [L442] t5_st = 0 312.69/160.51 [L601] COND FALSE !(M_E == 0) 312.69/160.51 [L606] COND FALSE !(T1_E == 0) 312.69/160.51 [L611] COND FALSE !(T2_E == 0) 312.69/160.51 [L616] COND FALSE !(T3_E == 0) 312.69/160.51 [L621] COND FALSE !(T4_E == 0) 312.69/160.51 [L626] COND FALSE !(T5_E == 0) 312.69/160.51 [L631] COND FALSE !(E_M == 0) 312.69/160.51 [L636] COND FALSE !(E_1 == 0) 312.69/160.51 [L641] COND FALSE !(E_2 == 0) 312.69/160.51 [L646] COND FALSE !(E_3 == 0) 312.69/160.51 [L651] COND FALSE !(E_4 == 0) 312.69/160.51 [L656] COND FALSE !(E_5 == 0) 312.69/160.51 [L734] int tmp ; 312.69/160.51 [L735] int tmp___0 ; 312.69/160.51 [L736] int tmp___1 ; 312.69/160.51 [L737] int tmp___2 ; 312.69/160.51 [L738] int tmp___3 ; 312.69/160.51 [L739] int tmp___4 ; 312.69/160.51 [L291] int __retres1 ; 312.69/160.51 [L294] COND FALSE !(m_pc == 1) 312.69/160.51 [L304] __retres1 = 0 312.69/160.51 [L306] return (__retres1); 312.69/160.51 [L743] tmp = is_master_triggered() 312.69/160.51 [L745] COND FALSE !(\read(tmp)) 312.69/160.51 [L310] int __retres1 ; 312.69/160.51 [L313] COND FALSE !(t1_pc == 1) 312.69/160.51 [L323] __retres1 = 0 312.69/160.51 [L325] return (__retres1); 312.69/160.51 [L751] tmp___0 = is_transmit1_triggered() 312.69/160.51 [L753] COND FALSE !(\read(tmp___0)) 312.69/160.51 [L329] int __retres1 ; 312.69/160.51 [L332] COND FALSE !(t2_pc == 1) 312.69/160.51 [L342] __retres1 = 0 312.69/160.51 [L344] return (__retres1); 312.69/160.51 [L759] tmp___1 = is_transmit2_triggered() 312.69/160.51 [L761] COND FALSE !(\read(tmp___1)) 312.69/160.51 [L348] int __retres1 ; 312.69/160.51 [L351] COND FALSE !(t3_pc == 1) 312.69/160.51 [L361] __retres1 = 0 312.69/160.51 [L363] return (__retres1); 312.69/160.51 [L767] tmp___2 = is_transmit3_triggered() 312.69/160.51 [L769] COND FALSE !(\read(tmp___2)) 312.69/160.51 [L367] int __retres1 ; 312.69/160.51 [L370] COND FALSE !(t4_pc == 1) 312.69/160.51 [L380] __retres1 = 0 312.69/160.51 [L382] return (__retres1); 312.69/160.51 [L775] tmp___3 = is_transmit4_triggered() 312.69/160.51 [L777] COND FALSE !(\read(tmp___3)) 312.69/160.51 [L386] int __retres1 ; 312.69/160.51 [L389] COND FALSE !(t5_pc == 1) 312.69/160.51 [L399] __retres1 = 0 312.69/160.51 [L401] return (__retres1); 312.69/160.51 [L783] tmp___4 = is_transmit5_triggered() 312.69/160.51 [L785] COND FALSE !(\read(tmp___4)) 312.69/160.51 [L669] COND FALSE !(M_E == 1) 312.69/160.51 [L674] COND FALSE !(T1_E == 1) 312.69/160.51 [L679] COND FALSE !(T2_E == 1) 312.69/160.51 [L684] COND FALSE !(T3_E == 1) 312.69/160.51 [L689] COND FALSE !(T4_E == 1) 312.69/160.51 [L694] COND FALSE !(T5_E == 1) 312.69/160.51 [L699] COND FALSE !(E_M == 1) 312.69/160.51 [L704] COND FALSE !(E_1 == 1) 312.69/160.51 [L709] COND FALSE !(E_2 == 1) 312.69/160.51 [L714] COND FALSE !(E_3 == 1) 312.69/160.51 [L719] COND FALSE !(E_4 == 1) 312.69/160.51 [L724] COND FALSE !(E_5 == 1) 312.69/160.51 [L930] COND TRUE 1 312.69/160.51 [L933] kernel_st = 1 312.69/160.51 [L492] int tmp ; 312.69/160.51 Loop: 312.69/160.51 [L496] COND TRUE 1 312.69/160.51 [L451] int __retres1 ; 312.69/160.51 [L454] COND TRUE m_st == 0 312.69/160.51 [L455] __retres1 = 1 312.69/160.51 [L487] return (__retres1); 312.69/160.51 [L499] tmp = exists_runnable_thread() 312.69/160.51 [L501] COND TRUE \read(tmp) 312.69/160.51 [L506] COND TRUE m_st == 0 312.69/160.51 [L507] int tmp_ndt_1; 312.69/160.51 [L508] tmp_ndt_1 = __VERIFIER_nondet_int() 312.69/160.51 [L509] COND FALSE !(\read(tmp_ndt_1)) 312.69/160.51 [L520] COND TRUE t1_st == 0 312.69/160.51 [L521] int tmp_ndt_2; 312.69/160.51 [L522] tmp_ndt_2 = __VERIFIER_nondet_int() 312.69/160.51 [L523] COND FALSE !(\read(tmp_ndt_2)) 312.69/160.51 [L534] COND TRUE t2_st == 0 312.69/160.51 [L535] int tmp_ndt_3; 312.69/160.51 [L536] tmp_ndt_3 = __VERIFIER_nondet_int() 312.69/160.51 [L537] COND FALSE !(\read(tmp_ndt_3)) 312.69/160.51 [L548] COND TRUE t3_st == 0 312.69/160.51 [L549] int tmp_ndt_4; 312.69/160.51 [L550] tmp_ndt_4 = __VERIFIER_nondet_int() 312.69/160.51 [L551] COND FALSE !(\read(tmp_ndt_4)) 312.69/160.51 [L562] COND TRUE t4_st == 0 312.69/160.51 [L563] int tmp_ndt_5; 312.69/160.51 [L564] tmp_ndt_5 = __VERIFIER_nondet_int() 312.69/160.51 [L565] COND FALSE !(\read(tmp_ndt_5)) 312.69/160.51 [L576] COND TRUE t5_st == 0 312.69/160.51 [L577] int tmp_ndt_6; 312.69/160.51 [L578] tmp_ndt_6 = __VERIFIER_nondet_int() 312.69/160.51 [L579] COND FALSE !(\read(tmp_ndt_6)) 312.69/160.51 End of lasso representation. 312.69/160.51 RESULT: Ultimate proved your program to be incorrect! 312.69/160.51 !SESSION 2019-03-28 12:21:44.600 ----------------------------------------------- 312.69/160.51 eclipse.buildId=unknown 312.69/160.51 java.version=1.8.0_181 312.69/160.51 java.vendor=Oracle Corporation 312.69/160.51 BootLoader constants: OS=linux, ARCH=x86_64, WS=gtk, NL=en_US 312.69/160.51 Framework arguments: -tc ./../AutomizerAndBuchiAutomizerCInlineWithBlockEncoding.xml -s ./../termcomp2017.epf -i /export/starexec/sandbox2/benchmark/theBenchmark.c 312.69/160.51 Command-line arguments: -os linux -ws gtk -arch x86_64 -consoleLog -data @user.home/.ultimate -tc ./../AutomizerAndBuchiAutomizerCInlineWithBlockEncoding.xml -s ./../termcomp2017.epf -data /export/starexec/sandbox2/tmp -i /export/starexec/sandbox2/benchmark/theBenchmark.c 312.69/160.51 312.69/160.51 !ENTRY org.eclipse.core.resources 2 10035 2019-03-28 12:24:24.257 312.69/160.51 !MESSAGE The workspace will exit with unsaved changes in this session. 312.69/160.51 Received shutdown request... 312.69/160.51 Ultimate: 312.69/160.51 GTK+ Version Check 312.69/160.51 EOF