37.10/18.53 NO 37.10/18.53 37.10/18.53 Ultimate: Cannot open display: 37.10/18.53 This is Ultimate 0.1.24-8dc7c08-m 37.10/18.53 [2019-03-28 12:18:33,007 INFO L170 SettingsManager]: Resetting all preferences to default values... 37.10/18.53 [2019-03-28 12:18:33,009 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values 37.10/18.53 [2019-03-28 12:18:33,021 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... 37.10/18.53 [2019-03-28 12:18:33,021 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values 37.10/18.53 [2019-03-28 12:18:33,022 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values 37.10/18.53 [2019-03-28 12:18:33,023 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values 37.10/18.53 [2019-03-28 12:18:33,025 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values 37.10/18.53 [2019-03-28 12:18:33,026 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values 37.10/18.53 [2019-03-28 12:18:33,027 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values 37.10/18.53 [2019-03-28 12:18:33,028 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... 37.10/18.53 [2019-03-28 12:18:33,028 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values 37.10/18.53 [2019-03-28 12:18:33,029 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values 37.10/18.53 [2019-03-28 12:18:33,030 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values 37.10/18.53 [2019-03-28 12:18:33,031 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values 37.10/18.53 [2019-03-28 12:18:33,032 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values 37.10/18.53 [2019-03-28 12:18:33,033 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values 37.10/18.53 [2019-03-28 12:18:33,034 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values 37.10/18.53 [2019-03-28 12:18:33,036 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values 37.10/18.53 [2019-03-28 12:18:33,038 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values 37.10/18.53 [2019-03-28 12:18:33,039 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values 37.10/18.53 [2019-03-28 12:18:33,040 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values 37.10/18.53 [2019-03-28 12:18:33,042 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 37.10/18.53 [2019-03-28 12:18:33,042 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... 37.10/18.53 [2019-03-28 12:18:33,042 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values 37.10/18.53 [2019-03-28 12:18:33,043 INFO L174 SettingsManager]: Resetting IcfgToChc preferences to default values 37.10/18.53 [2019-03-28 12:18:33,044 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values 37.10/18.53 [2019-03-28 12:18:33,045 INFO L177 SettingsManager]: ReqToTest provides no preferences, ignoring... 37.10/18.53 [2019-03-28 12:18:33,045 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values 37.10/18.53 [2019-03-28 12:18:33,045 INFO L174 SettingsManager]: Resetting ChcSmtPrinter preferences to default values 37.10/18.53 [2019-03-28 12:18:33,046 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values 37.10/18.53 [2019-03-28 12:18:33,047 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values 37.10/18.53 [2019-03-28 12:18:33,048 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... 37.10/18.53 [2019-03-28 12:18:33,048 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values 37.10/18.53 [2019-03-28 12:18:33,049 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... 37.10/18.53 [2019-03-28 12:18:33,049 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... 37.10/18.53 [2019-03-28 12:18:33,049 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values 37.10/18.53 [2019-03-28 12:18:33,050 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values 37.10/18.53 [2019-03-28 12:18:33,051 INFO L181 SettingsManager]: Finished resetting all preferences to default values... 37.10/18.53 [2019-03-28 12:18:33,051 INFO L98 SettingsManager]: Beginning loading settings from /export/starexec/sandbox/solver/bin/./../termcomp2017.epf 37.10/18.53 [2019-03-28 12:18:33,066 INFO L110 SettingsManager]: Loading preferences was successful 37.10/18.53 [2019-03-28 12:18:33,066 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: 37.10/18.53 [2019-03-28 12:18:33,067 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: 37.10/18.53 [2019-03-28 12:18:33,067 INFO L133 SettingsManager]: * Rewrite not-equals=true 37.10/18.53 [2019-03-28 12:18:33,067 INFO L133 SettingsManager]: * Create parallel compositions if possible=false 37.10/18.53 [2019-03-28 12:18:33,068 INFO L133 SettingsManager]: * Minimize states using LBE with the strategy=SINGLE 37.10/18.53 [2019-03-28 12:18:33,068 INFO L133 SettingsManager]: * Use SBE=true 37.10/18.53 [2019-03-28 12:18:33,068 INFO L131 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: 37.10/18.53 [2019-03-28 12:18:33,068 INFO L133 SettingsManager]: * Use old map elimination=false 37.10/18.53 [2019-03-28 12:18:33,068 INFO L133 SettingsManager]: * Use external solver (rank synthesis)=false 37.10/18.53 [2019-03-28 12:18:33,069 INFO L133 SettingsManager]: * Buchi interpolant automaton construction strategy=DANDELION 37.10/18.53 [2019-03-28 12:18:33,069 INFO L133 SettingsManager]: * Use only trivial implications for array writes=true 37.10/18.53 [2019-03-28 12:18:33,069 INFO L133 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES 37.10/18.53 [2019-03-28 12:18:33,069 INFO L133 SettingsManager]: * Construct termination proof for TermComp=true 37.10/18.53 [2019-03-28 12:18:33,069 INFO L133 SettingsManager]: * Command for external solver (GNTA synthesis)=z3 SMTLIB2_COMPLIANT=true -memory:4560 -smt2 -in -t:12000 37.10/18.53 [2019-03-28 12:18:33,070 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: 37.10/18.53 [2019-03-28 12:18:33,070 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false 37.10/18.53 [2019-03-28 12:18:33,070 INFO L133 SettingsManager]: * Check division by zero=IGNORE 37.10/18.53 [2019-03-28 12:18:33,070 INFO L133 SettingsManager]: * Check if freed pointer was valid=false 37.10/18.53 [2019-03-28 12:18:33,070 INFO L133 SettingsManager]: * Assume nondeterminstic values are in range=false 37.10/18.53 [2019-03-28 12:18:33,071 INFO L133 SettingsManager]: * How to treat unsigned ints differently from normal ones=IGNORE 37.10/18.53 [2019-03-28 12:18:33,071 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: 37.10/18.53 [2019-03-28 12:18:33,071 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements 37.10/18.53 [2019-03-28 12:18:33,071 INFO L133 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump 37.10/18.53 [2019-03-28 12:18:33,071 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:4560 -smt2 -in -t:5000 37.10/18.53 [2019-03-28 12:18:33,072 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: 37.10/18.53 [2019-03-28 12:18:33,072 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles 37.10/18.53 [2019-03-28 12:18:33,072 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL 37.10/18.53 [2019-03-28 12:18:33,072 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true 37.10/18.53 [2019-03-28 12:18:33,097 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp 37.10/18.53 [2019-03-28 12:18:33,128 INFO L259 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized 37.10/18.53 [2019-03-28 12:18:33,132 INFO L215 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. 37.10/18.53 [2019-03-28 12:18:33,133 INFO L271 PluginConnector]: Initializing CDTParser... 37.10/18.53 [2019-03-28 12:18:33,134 INFO L276 PluginConnector]: CDTParser initialized 37.10/18.53 [2019-03-28 12:18:33,134 INFO L430 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /export/starexec/sandbox/benchmark/theBenchmark.c 37.10/18.53 [2019-03-28 12:18:33,203 INFO L221 CDTParser]: Created temporary CDT project at /export/starexec/sandbox/tmp/9bd540dfed544fd7a97875bae8dee640/FLAG757730992 37.10/18.53 [2019-03-28 12:18:33,744 INFO L307 CDTParser]: Found 1 translation units. 37.10/18.53 [2019-03-28 12:18:33,745 INFO L161 CDTParser]: Scanning /export/starexec/sandbox/benchmark/theBenchmark.c 37.10/18.53 [2019-03-28 12:18:33,754 INFO L355 CDTParser]: About to delete temporary CDT project at /export/starexec/sandbox/tmp/9bd540dfed544fd7a97875bae8dee640/FLAG757730992 37.10/18.53 [2019-03-28 12:18:34,136 INFO L363 CDTParser]: Successfully deleted /export/starexec/sandbox/tmp/9bd540dfed544fd7a97875bae8dee640 37.10/18.53 [2019-03-28 12:18:34,148 INFO L297 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### 37.10/18.53 [2019-03-28 12:18:34,150 INFO L131 ToolchainWalker]: Walking toolchain with 7 elements. 37.10/18.53 [2019-03-28 12:18:34,151 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- 37.10/18.53 [2019-03-28 12:18:34,151 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... 37.10/18.53 [2019-03-28 12:18:34,155 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized 37.10/18.53 [2019-03-28 12:18:34,156 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.03 12:18:34" (1/1) ... 37.10/18.53 [2019-03-28 12:18:34,159 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3c41de6c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:18:34, skipping insertion in model container 37.10/18.53 [2019-03-28 12:18:34,160 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.03 12:18:34" (1/1) ... 37.10/18.53 [2019-03-28 12:18:34,168 INFO L145 MainTranslator]: Starting translation in SV-COMP mode 37.10/18.53 [2019-03-28 12:18:34,203 INFO L176 MainTranslator]: Built tables and reachable declarations 37.10/18.53 [2019-03-28 12:18:34,394 INFO L206 PostProcessor]: Analyzing one entry point: main 37.10/18.53 [2019-03-28 12:18:34,401 INFO L191 MainTranslator]: Completed pre-run 37.10/18.53 [2019-03-28 12:18:34,505 INFO L206 PostProcessor]: Analyzing one entry point: main 37.10/18.53 [2019-03-28 12:18:34,524 INFO L195 MainTranslator]: Completed translation 37.10/18.53 [2019-03-28 12:18:34,524 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:18:34 WrapperNode 37.10/18.53 [2019-03-28 12:18:34,525 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- 37.10/18.53 [2019-03-28 12:18:34,526 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- 37.10/18.53 [2019-03-28 12:18:34,526 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... 37.10/18.53 [2019-03-28 12:18:34,526 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized 37.10/18.53 [2019-03-28 12:18:34,537 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:18:34" (1/1) ... 37.10/18.53 [2019-03-28 12:18:34,545 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:18:34" (1/1) ... 37.10/18.53 [2019-03-28 12:18:34,575 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- 37.10/18.53 [2019-03-28 12:18:34,576 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- 37.10/18.53 [2019-03-28 12:18:34,576 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... 37.10/18.53 [2019-03-28 12:18:34,576 INFO L276 PluginConnector]: Boogie Preprocessor initialized 37.10/18.53 [2019-03-28 12:18:34,586 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:18:34" (1/1) ... 37.10/18.53 [2019-03-28 12:18:34,587 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:18:34" (1/1) ... 37.10/18.53 [2019-03-28 12:18:34,588 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:18:34" (1/1) ... 37.10/18.53 [2019-03-28 12:18:34,589 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:18:34" (1/1) ... 37.10/18.53 [2019-03-28 12:18:34,594 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:18:34" (1/1) ... 37.10/18.53 [2019-03-28 12:18:34,602 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:18:34" (1/1) ... 37.10/18.53 [2019-03-28 12:18:34,604 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:18:34" (1/1) ... 37.10/18.53 [2019-03-28 12:18:34,607 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- 37.10/18.53 [2019-03-28 12:18:34,607 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- 37.10/18.53 [2019-03-28 12:18:34,608 INFO L271 PluginConnector]: Initializing RCFGBuilder... 37.10/18.53 [2019-03-28 12:18:34,608 INFO L276 PluginConnector]: RCFGBuilder initialized 37.10/18.53 [2019-03-28 12:18:34,609 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:18:34" (1/1) ... 37.10/18.53 No working directory specified, using /export/starexec/sandbox/solver/bin/z3 37.10/18.53 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:4560 -smt2 -in -t:5000 (exit command is (exit), workingDir is null) 37.10/18.53 Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:4560 -smt2 -in -t:5000 37.10/18.53 [2019-03-28 12:18:34,684 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start 37.10/18.53 [2019-03-28 12:18:34,685 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start 37.10/18.53 [2019-03-28 12:18:35,037 INFO L281 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) 37.10/18.53 [2019-03-28 12:18:35,037 INFO L286 CfgBuilder]: Removed 44 assue(true) statements. 37.10/18.53 [2019-03-28 12:18:35,039 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.03 12:18:35 BoogieIcfgContainer 37.10/18.53 [2019-03-28 12:18:35,039 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- 37.10/18.53 [2019-03-28 12:18:35,039 INFO L113 PluginConnector]: ------------------------BlockEncodingV2---------------------------- 37.10/18.53 [2019-03-28 12:18:35,039 INFO L271 PluginConnector]: Initializing BlockEncodingV2... 37.10/18.53 [2019-03-28 12:18:35,042 INFO L276 PluginConnector]: BlockEncodingV2 initialized 37.10/18.53 [2019-03-28 12:18:35,042 INFO L185 PluginConnector]: Executing the observer BlockEncodingObserver from plugin BlockEncodingV2 for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.03 12:18:35" (1/1) ... 37.10/18.53 [2019-03-28 12:18:35,062 INFO L313 BlockEncoder]: Initial Icfg 75 locations, 115 edges 37.10/18.53 [2019-03-28 12:18:35,064 INFO L258 BlockEncoder]: Using Remove infeasible edges 37.10/18.53 [2019-03-28 12:18:35,065 INFO L263 BlockEncoder]: Using Maximize final states 37.10/18.53 [2019-03-28 12:18:35,066 INFO L270 BlockEncoder]: Using Minimize states even if more edges are added than removed.=false 37.10/18.53 [2019-03-28 12:18:35,066 INFO L276 BlockEncoder]: Using Minimize states using LBE with the strategy=SINGLE 37.10/18.53 [2019-03-28 12:18:35,068 INFO L296 BlockEncoder]: Using Remove sink states 37.10/18.53 [2019-03-28 12:18:35,069 INFO L171 BlockEncoder]: Using Apply optimizations until nothing changes=true 37.10/18.53 [2019-03-28 12:18:35,069 INFO L179 BlockEncoder]: Using Rewrite not-equals 37.10/18.53 [2019-03-28 12:18:35,100 INFO L185 BlockEncoder]: Using Use SBE 37.10/18.53 [2019-03-28 12:18:35,135 INFO L200 BlockEncoder]: SBE split 33 edges 37.10/18.53 [2019-03-28 12:18:35,140 INFO L70 emoveInfeasibleEdges]: Removed 11 edges and 0 locations because of local infeasibility 37.10/18.53 [2019-03-28 12:18:35,142 INFO L71 MaximizeFinalStates]: 0 new accepting states 37.10/18.53 [2019-03-28 12:18:35,181 INFO L100 BaseMinimizeStates]: Removed 30 edges and 15 locations by large block encoding 37.10/18.53 [2019-03-28 12:18:35,184 INFO L70 RemoveSinkStates]: Removed 8 edges and 5 locations by removing sink states 37.10/18.53 [2019-03-28 12:18:35,185 INFO L70 emoveInfeasibleEdges]: Removed 0 edges and 0 locations because of local infeasibility 37.10/18.53 [2019-03-28 12:18:35,186 INFO L71 MaximizeFinalStates]: 0 new accepting states 37.10/18.53 [2019-03-28 12:18:35,191 INFO L100 BaseMinimizeStates]: Removed 6 edges and 3 locations by large block encoding 37.10/18.53 [2019-03-28 12:18:35,192 INFO L70 RemoveSinkStates]: Removed 0 edges and 0 locations by removing sink states 37.10/18.53 [2019-03-28 12:18:35,192 INFO L70 emoveInfeasibleEdges]: Removed 0 edges and 0 locations because of local infeasibility 37.10/18.53 [2019-03-28 12:18:35,193 INFO L71 MaximizeFinalStates]: 0 new accepting states 37.10/18.53 [2019-03-28 12:18:35,193 INFO L100 BaseMinimizeStates]: Removed 0 edges and 0 locations by large block encoding 37.10/18.53 [2019-03-28 12:18:35,194 INFO L70 RemoveSinkStates]: Removed 0 edges and 0 locations by removing sink states 37.10/18.53 [2019-03-28 12:18:35,194 INFO L313 BlockEncoder]: Encoded RCFG 52 locations, 111 edges 37.10/18.53 [2019-03-28 12:18:35,195 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.blockencoding CFG 28.03 12:18:35 BasicIcfg 37.10/18.53 [2019-03-28 12:18:35,195 INFO L132 PluginConnector]: ------------------------ END BlockEncodingV2---------------------------- 37.10/18.53 [2019-03-28 12:18:35,196 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- 37.10/18.53 [2019-03-28 12:18:35,196 INFO L271 PluginConnector]: Initializing TraceAbstraction... 37.10/18.53 [2019-03-28 12:18:35,199 INFO L276 PluginConnector]: TraceAbstraction initialized 37.10/18.53 [2019-03-28 12:18:35,199 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 28.03 12:18:34" (1/4) ... 37.10/18.53 [2019-03-28 12:18:35,200 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@20c51ef6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.03 12:18:35, skipping insertion in model container 37.10/18.53 [2019-03-28 12:18:35,200 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:18:34" (2/4) ... 37.10/18.53 [2019-03-28 12:18:35,201 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@20c51ef6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.03 12:18:35, skipping insertion in model container 37.10/18.53 [2019-03-28 12:18:35,201 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.03 12:18:35" (3/4) ... 37.10/18.53 [2019-03-28 12:18:35,201 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@20c51ef6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.03 12:18:35, skipping insertion in model container 37.10/18.53 [2019-03-28 12:18:35,201 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.blockencoding CFG 28.03 12:18:35" (4/4) ... 37.10/18.53 [2019-03-28 12:18:35,203 INFO L112 eAbstractionObserver]: Analyzing ICFG theBenchmark.c_BEv2 37.10/18.53 [2019-03-28 12:18:35,213 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:ForwardPredicates Determinization: PREDICATE_ABSTRACTION 37.10/18.53 [2019-03-28 12:18:35,222 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 0 error locations. 37.10/18.53 [2019-03-28 12:18:35,243 INFO L257 AbstractCegarLoop]: Starting to check reachability of 0 error locations. 37.10/18.53 [2019-03-28 12:18:35,273 INFO L133 ementStrategyFactory]: Using default assertion order modulation 37.10/18.53 [2019-03-28 12:18:35,275 INFO L382 AbstractCegarLoop]: Interprodecural is true 37.10/18.53 [2019-03-28 12:18:35,275 INFO L383 AbstractCegarLoop]: Hoare is true 37.10/18.53 [2019-03-28 12:18:35,275 INFO L384 AbstractCegarLoop]: Compute interpolants for ForwardPredicates 37.10/18.53 [2019-03-28 12:18:35,275 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE 37.10/18.53 [2019-03-28 12:18:35,275 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION 37.10/18.53 [2019-03-28 12:18:35,276 INFO L387 AbstractCegarLoop]: Difference is false 37.10/18.53 [2019-03-28 12:18:35,276 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA 37.10/18.53 [2019-03-28 12:18:35,276 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== 37.10/18.53 [2019-03-28 12:18:35,292 INFO L276 IsEmpty]: Start isEmpty. Operand 52 states. 37.10/18.53 [2019-03-28 12:18:35,300 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. 37.10/18.53 [2019-03-28 12:18:35,304 INFO L343 DoubleDeckerVisitor]: Before removal of dead ends 52 states. 37.10/18.53 [2019-03-28 12:18:35,375 INFO L448 ceAbstractionStarter]: For program point L151(lines 150 185) no Hoare annotation was computed. 37.10/18.53 [2019-03-28 12:18:35,375 INFO L448 ceAbstractionStarter]: For program point L52(lines 52 57) no Hoare annotation was computed. 37.10/18.53 [2019-03-28 12:18:35,376 INFO L448 ceAbstractionStarter]: For program point L52-1(lines 52 57) no Hoare annotation was computed. 37.10/18.53 [2019-03-28 12:18:35,376 INFO L451 ceAbstractionStarter]: At program point L242(lines 242 246) the Hoare annotation is: true 37.10/18.53 [2019-03-28 12:18:35,376 INFO L448 ceAbstractionStarter]: For program point L242-1(lines 237 277) no Hoare annotation was computed. 37.10/18.53 [2019-03-28 12:18:35,376 INFO L448 ceAbstractionStarter]: For program point L139(lines 139 147) no Hoare annotation was computed. 37.10/18.53 [2019-03-28 12:18:35,376 INFO L448 ceAbstractionStarter]: For program point L292(lines 292 297) no Hoare annotation was computed. 37.10/18.53 [2019-03-28 12:18:35,377 INFO L451 ceAbstractionStarter]: At program point L226(lines 213 228) the Hoare annotation is: true 37.10/18.53 [2019-03-28 12:18:35,377 INFO L451 ceAbstractionStarter]: At program point L226-1(lines 213 228) the Hoare annotation is: true 37.10/18.53 [2019-03-28 12:18:35,377 INFO L448 ceAbstractionStarter]: For program point L32(lines 32 41) no Hoare annotation was computed. 37.10/18.53 [2019-03-28 12:18:35,377 INFO L448 ceAbstractionStarter]: For program point L32-2(lines 32 41) no Hoare annotation was computed. 37.10/18.53 [2019-03-28 12:18:35,377 INFO L451 ceAbstractionStarter]: At program point ULTIMATE.startENTRY(line -1) the Hoare annotation is: true 37.10/18.53 [2019-03-28 12:18:35,377 INFO L448 ceAbstractionStarter]: For program point L32-3(lines 32 41) no Hoare annotation was computed. 37.10/18.53 [2019-03-28 12:18:35,378 INFO L448 ceAbstractionStarter]: For program point L251(lines 251 258) no Hoare annotation was computed. 37.10/18.53 [2019-03-28 12:18:35,378 INFO L448 ceAbstractionStarter]: For program point L32-5(lines 32 41) no Hoare annotation was computed. 37.10/18.53 [2019-03-28 12:18:35,378 INFO L448 ceAbstractionStarter]: For program point L218(lines 218 223) no Hoare annotation was computed. 37.10/18.53 [2019-03-28 12:18:35,378 INFO L448 ceAbstractionStarter]: For program point L218-1(lines 218 223) no Hoare annotation was computed. 37.10/18.53 [2019-03-28 12:18:35,378 INFO L451 ceAbstractionStarter]: At program point L313-1(lines 192 325) the Hoare annotation is: true 37.10/18.53 [2019-03-28 12:18:35,378 INFO L451 ceAbstractionStarter]: At program point L247(lines 237 277) the Hoare annotation is: true 37.10/18.53 [2019-03-28 12:18:35,379 INFO L448 ceAbstractionStarter]: For program point L152-1(lines 152 162) no Hoare annotation was computed. 37.10/18.53 [2019-03-28 12:18:35,379 INFO L448 ceAbstractionStarter]: For program point L214(lines 214 224) no Hoare annotation was computed. 37.10/18.53 [2019-03-28 12:18:35,379 INFO L448 ceAbstractionStarter]: For program point L214-1(lines 214 224) no Hoare annotation was computed. 37.10/18.53 [2019-03-28 12:18:35,379 INFO L448 ceAbstractionStarter]: For program point L82(lines 82 86) no Hoare annotation was computed. 37.10/18.53 [2019-03-28 12:18:35,379 INFO L451 ceAbstractionStarter]: At program point L82-2(lines 66 90) the Hoare annotation is: true 37.10/18.53 [2019-03-28 12:18:35,379 INFO L448 ceAbstractionStarter]: For program point L82-3(lines 82 86) no Hoare annotation was computed. 37.10/18.53 [2019-03-28 12:18:35,380 INFO L451 ceAbstractionStarter]: At program point L82-5(lines 66 90) the Hoare annotation is: true 37.10/18.53 [2019-03-28 12:18:35,380 INFO L451 ceAbstractionStarter]: At program point L107-1(lines 95 132) the Hoare annotation is: true 37.10/18.53 [2019-03-28 12:18:35,380 INFO L448 ceAbstractionStarter]: For program point L74(lines 74 78) no Hoare annotation was computed. 37.10/18.53 [2019-03-28 12:18:35,380 INFO L448 ceAbstractionStarter]: For program point L74-2(lines 74 78) no Hoare annotation was computed. 37.10/18.53 [2019-03-28 12:18:35,380 INFO L448 ceAbstractionStarter]: For program point L74-3(lines 74 78) no Hoare annotation was computed. 37.10/18.53 [2019-03-28 12:18:35,380 INFO L448 ceAbstractionStarter]: For program point L74-5(lines 74 78) no Hoare annotation was computed. 37.10/18.53 [2019-03-28 12:18:35,380 INFO L448 ceAbstractionStarter]: For program point L99(lines 99 103) no Hoare annotation was computed. 37.10/18.53 [2019-03-28 12:18:35,381 INFO L448 ceAbstractionStarter]: For program point L33(lines 33 38) no Hoare annotation was computed. 37.10/18.53 [2019-03-28 12:18:35,381 INFO L448 ceAbstractionStarter]: For program point L33-1(lines 33 38) no Hoare annotation was computed. 37.10/18.53 [2019-03-28 12:18:35,381 INFO L451 ceAbstractionStarter]: At program point L62(lines 50 64) the Hoare annotation is: true 37.10/18.53 [2019-03-28 12:18:35,381 INFO L451 ceAbstractionStarter]: At program point L62-1(lines 50 64) the Hoare annotation is: true 37.10/18.53 [2019-03-28 12:18:35,381 INFO L448 ceAbstractionStarter]: For program point L108(lines 107 127) no Hoare annotation was computed. 37.10/18.53 [2019-03-28 12:18:35,381 INFO L448 ceAbstractionStarter]: For program point L96(lines 96 104) no Hoare annotation was computed. 37.10/18.53 [2019-03-28 12:18:35,382 INFO L448 ceAbstractionStarter]: For program point L51(lines 51 60) no Hoare annotation was computed. 37.10/18.53 [2019-03-28 12:18:35,382 INFO L448 ceAbstractionStarter]: For program point L51-2(lines 51 60) no Hoare annotation was computed. 37.10/18.53 [2019-03-28 12:18:35,382 INFO L448 ceAbstractionStarter]: For program point L51-3(lines 51 60) no Hoare annotation was computed. 37.10/18.53 [2019-03-28 12:18:35,382 INFO L451 ceAbstractionStarter]: At program point L142(lines 142 146) the Hoare annotation is: true 37.10/18.53 [2019-03-28 12:18:35,382 INFO L448 ceAbstractionStarter]: For program point L51-5(lines 51 60) no Hoare annotation was computed. 37.10/18.53 [2019-03-28 12:18:35,382 INFO L451 ceAbstractionStarter]: At program point L109(lines 95 132) the Hoare annotation is: true 37.10/18.53 [2019-03-28 12:18:35,383 INFO L451 ceAbstractionStarter]: At program point L299(lines 288 301) the Hoare annotation is: true 37.10/18.53 [2019-03-28 12:18:35,383 INFO L451 ceAbstractionStarter]: At program point L43(lines 31 45) the Hoare annotation is: true 37.10/18.53 [2019-03-28 12:18:35,383 INFO L448 ceAbstractionStarter]: For program point L266(lines 266 273) no Hoare annotation was computed. 37.10/18.53 [2019-03-28 12:18:35,383 INFO L451 ceAbstractionStarter]: At program point L43-1(lines 31 45) the Hoare annotation is: true 37.10/18.53 [2019-03-28 12:18:35,383 INFO L451 ceAbstractionStarter]: At program point L10-2(lines 138 190) the Hoare annotation is: true 37.10/18.53 [2019-03-28 12:18:35,383 INFO L451 ceAbstractionStarter]: At program point L262(lines 237 277) the Hoare annotation is: true 37.10/18.53 [2019-03-28 12:18:35,384 INFO L448 ceAbstractionStarter]: For program point L196(lines 196 200) no Hoare annotation was computed. 37.10/18.53 [2019-03-28 12:18:35,384 INFO L448 ceAbstractionStarter]: For program point L196-2(lines 195 208) no Hoare annotation was computed. 37.10/18.53 [2019-03-28 12:18:35,393 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.03 12:18:35 BasicIcfg 37.10/18.53 [2019-03-28 12:18:35,394 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- 37.10/18.53 [2019-03-28 12:18:35,394 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- 37.10/18.53 [2019-03-28 12:18:35,394 INFO L271 PluginConnector]: Initializing BuchiAutomizer... 37.10/18.53 [2019-03-28 12:18:35,398 INFO L276 PluginConnector]: BuchiAutomizer initialized 37.10/18.53 [2019-03-28 12:18:35,399 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis 37.10/18.53 [2019-03-28 12:18:35,399 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 28.03 12:18:34" (1/5) ... 37.10/18.53 [2019-03-28 12:18:35,400 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@75c51294 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.03 12:18:35, skipping insertion in model container 37.10/18.53 [2019-03-28 12:18:35,400 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis 37.10/18.53 [2019-03-28 12:18:35,400 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:18:34" (2/5) ... 37.10/18.53 [2019-03-28 12:18:35,400 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@75c51294 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.03 12:18:35, skipping insertion in model container 37.10/18.53 [2019-03-28 12:18:35,400 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis 37.10/18.53 [2019-03-28 12:18:35,400 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.03 12:18:35" (3/5) ... 37.10/18.53 [2019-03-28 12:18:35,401 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@75c51294 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 28.03 12:18:35, skipping insertion in model container 37.10/18.53 [2019-03-28 12:18:35,401 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis 37.10/18.53 [2019-03-28 12:18:35,401 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.blockencoding CFG 28.03 12:18:35" (4/5) ... 37.10/18.53 [2019-03-28 12:18:35,401 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@75c51294 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 28.03 12:18:35, skipping insertion in model container 37.10/18.53 [2019-03-28 12:18:35,402 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis 37.10/18.53 [2019-03-28 12:18:35,402 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.03 12:18:35" (5/5) ... 37.10/18.53 [2019-03-28 12:18:35,403 INFO L375 chiAutomizerObserver]: Analyzing ICFG theBenchmark.c_BEv2 37.10/18.53 [2019-03-28 12:18:35,429 INFO L133 ementStrategyFactory]: Using default assertion order modulation 37.10/18.53 [2019-03-28 12:18:35,430 INFO L374 BuchiCegarLoop]: Interprodecural is true 37.10/18.53 [2019-03-28 12:18:35,430 INFO L375 BuchiCegarLoop]: Hoare is true 37.10/18.53 [2019-03-28 12:18:35,430 INFO L376 BuchiCegarLoop]: Compute interpolants for ForwardPredicates 37.10/18.53 [2019-03-28 12:18:35,430 INFO L377 BuchiCegarLoop]: Backedges is STRAIGHT_LINE 37.10/18.53 [2019-03-28 12:18:35,430 INFO L378 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION 37.10/18.53 [2019-03-28 12:18:35,430 INFO L379 BuchiCegarLoop]: Difference is false 37.10/18.53 [2019-03-28 12:18:35,430 INFO L380 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA 37.10/18.53 [2019-03-28 12:18:35,430 INFO L383 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== 37.10/18.53 [2019-03-28 12:18:35,435 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 52 states. 37.10/18.53 [2019-03-28 12:18:35,456 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 49 37.10/18.53 [2019-03-28 12:18:35,456 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 37.10/18.53 [2019-03-28 12:18:35,456 INFO L119 BuchiIsEmpty]: Starting construction of run 37.10/18.53 [2019-03-28 12:18:35,464 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1] 37.10/18.53 [2019-03-28 12:18:35,464 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] 37.10/18.53 [2019-03-28 12:18:35,464 INFO L442 BuchiCegarLoop]: ======== Iteration 1============ 37.10/18.53 [2019-03-28 12:18:35,464 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 52 states. 37.10/18.53 [2019-03-28 12:18:35,468 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 49 37.10/18.53 [2019-03-28 12:18:35,468 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 37.10/18.53 [2019-03-28 12:18:35,468 INFO L119 BuchiIsEmpty]: Starting construction of run 37.10/18.53 [2019-03-28 12:18:35,469 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1] 37.10/18.53 [2019-03-28 12:18:35,469 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] 37.10/18.53 [2019-03-28 12:18:35,475 INFO L794 eck$LassoCheckResult]: Stem: 26#ULTIMATE.startENTRYtrue [520] ULTIMATE.startENTRY-->L196: Formula: (and (= v_~q_write_ev~0_11 v_~q_read_ev~0_11) (= 1 v_~c_dr_i~0_7) (= v_~q_free~0_11 1) (= v_~q_buf_0~0_5 0) (= v_~q_write_ev~0_11 2) (= 0 v_~p_last_write~0_6) (= 0 v_~c_last_read~0_6) (= v_~p_dw_pc~0_14 0) (= 0 v_~a_t~0_5) (= 0 v_~c_dr_st~0_15) (= v_~c_dr_pc~0_14 0) (= 0 v_~c_num_read~0_9) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 0) (= 0 v_~p_num_write~0_9) (= v_~p_dw_i~0_7 1) (= v_~p_dw_st~0_15 0)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ~p_last_write~0=v_~p_last_write~0_6, ~c_dr_pc~0=v_~c_dr_pc~0_14, ~c_dr_st~0=v_~c_dr_st~0_15, ~c_num_read~0=v_~c_num_read~0_9, ~p_num_write~0=v_~p_num_write~0_9, ~c_dr_i~0=v_~c_dr_i~0_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7, ~q_write_ev~0=v_~q_write_ev~0_11, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~p_dw_st~0=v_~p_dw_st~0_15, ~p_dw_i~0=v_~p_dw_i~0_7, ~c_last_read~0=v_~c_last_read~0_6, ~p_dw_pc~0=v_~p_dw_pc~0_14, ~q_free~0=v_~q_free~0_11, ~q_buf_0~0=v_~q_buf_0~0_5, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6, ~q_read_ev~0=v_~q_read_ev~0_11, ~a_t~0=v_~a_t~0_5} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ~p_last_write~0, ~c_dr_pc~0, ~c_dr_st~0, ~c_num_read~0, ~p_num_write~0, ~c_dr_i~0, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_~kernel_st~0, ~q_write_ev~0, ULTIMATE.start_main_#res, ~p_dw_st~0, ~p_dw_i~0, ~c_last_read~0, ~p_dw_pc~0, ~q_free~0, ~q_buf_0~0, ULTIMATE.start_main_~__retres1~3, ~q_read_ev~0, ~a_t~0] 54#L196true [454] L196-->L196-2: Formula: (and (< v_~p_dw_i~0_4 1) (= v_~p_dw_st~0_3 2)) InVars {~p_dw_i~0=v_~p_dw_i~0_4} OutVars{~p_dw_st~0=v_~p_dw_st~0_3, ~p_dw_i~0=v_~p_dw_i~0_4} AuxVars[] AssignedVars[~p_dw_st~0] 52#L196-2true [413] L196-2-->L313-1: Formula: (and (= 1 v_~c_dr_i~0_3) (= v_~c_dr_st~0_3 0)) InVars {~c_dr_i~0=v_~c_dr_i~0_3} OutVars{~c_dr_st~0=v_~c_dr_st~0_3, ~c_dr_i~0=v_~c_dr_i~0_3} AuxVars[] AssignedVars[~c_dr_st~0] 40#L313-1true 37.10/18.53 [2019-03-28 12:18:35,475 INFO L796 eck$LassoCheckResult]: Loop: 40#L313-1true [521] L313-1-->L262: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_8 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_8, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_4|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_6, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_6, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp~1, ULTIMATE.start_eval_~tmp___0~1, ULTIMATE.start_eval_~tmp___1~0] 43#L262true [522] L262-->L214: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 48#L214true [406] L214-->L226: Formula: (and (= v_~p_dw_st~0_6 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11 1)) InVars {~p_dw_st~0=v_~p_dw_st~0_6} OutVars{~p_dw_st~0=v_~p_dw_st~0_6, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 14#L226true [523] L226-->L242: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___1~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_5|, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp___1~0] 22#L242true [524] L242-->L214-1: Formula: (= v_ULTIMATE.start_eval_~tmp___1~0_8 0) InVars {ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_17, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_7, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_stop_simulation_#t~ret6=|v_ULTIMATE.start_stop_simulation_#t~ret6_4|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_4|, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret6, ULTIMATE.start_stop_simulation_#res] 47#L214-1true [404] L214-1-->L226-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_4 1) (= v_~p_dw_st~0_4 0)) InVars {~p_dw_st~0=v_~p_dw_st~0_4} OutVars{~p_dw_st~0=v_~p_dw_st~0_4, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 13#L226-1true [525] L226-1-->L292: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18 |v_ULTIMATE.start_exists_runnable_thread_#res_10|) (= v_ULTIMATE.start_stop_simulation_~tmp~2_8 |v_ULTIMATE.start_exists_runnable_thread_#res_10|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_8, ULTIMATE.start_stop_simulation_#t~ret6=|v_ULTIMATE.start_stop_simulation_#t~ret6_5|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret6] 18#L292true [465] L292-->L299: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_4 0) (< 0 v_ULTIMATE.start_stop_simulation_~tmp~2_5)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_4, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 11#L299true [534] L299-->L313-1: Formula: (and (= 0 v_ULTIMATE.start_start_simulation_~tmp~3_9) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_9 |v_ULTIMATE.start_stop_simulation_#res_6|) (= |v_ULTIMATE.start_stop_simulation_#res_6| v_ULTIMATE.start_start_simulation_~tmp~3_9)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_9} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_6|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_~tmp~3] 40#L313-1true 37.10/18.53 [2019-03-28 12:18:35,481 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.53 [2019-03-28 12:18:35,482 INFO L82 PathProgramCache]: Analyzing trace with hash 543998, now seen corresponding path program 1 times 37.10/18.53 [2019-03-28 12:18:35,483 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.53 [2019-03-28 12:18:35,484 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.53 [2019-03-28 12:18:35,504 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.53 [2019-03-28 12:18:35,504 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 37.10/18.53 [2019-03-28 12:18:35,505 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.53 [2019-03-28 12:18:35,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 37.10/18.53 [2019-03-28 12:18:35,581 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 37.10/18.53 [2019-03-28 12:18:35,584 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 37.10/18.53 [2019-03-28 12:18:35,584 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 37.10/18.53 [2019-03-28 12:18:35,589 INFO L799 eck$LassoCheckResult]: stem already infeasible 37.10/18.53 [2019-03-28 12:18:35,589 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.53 [2019-03-28 12:18:35,589 INFO L82 PathProgramCache]: Analyzing trace with hash 65342963, now seen corresponding path program 1 times 37.10/18.53 [2019-03-28 12:18:35,590 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.53 [2019-03-28 12:18:35,590 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.53 [2019-03-28 12:18:35,591 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.53 [2019-03-28 12:18:35,591 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 37.10/18.53 [2019-03-28 12:18:35,591 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.53 [2019-03-28 12:18:35,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 37.10/18.53 [2019-03-28 12:18:35,620 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 37.10/18.53 [2019-03-28 12:18:35,621 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 37.10/18.53 [2019-03-28 12:18:35,621 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 37.10/18.53 [2019-03-28 12:18:35,622 INFO L811 eck$LassoCheckResult]: loop already infeasible 37.10/18.53 [2019-03-28 12:18:35,637 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 37.10/18.53 [2019-03-28 12:18:35,637 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 37.10/18.53 [2019-03-28 12:18:35,639 INFO L87 Difference]: Start difference. First operand 52 states. Second operand 3 states. 37.10/18.53 [2019-03-28 12:18:35,759 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 37.10/18.53 [2019-03-28 12:18:35,760 INFO L93 Difference]: Finished difference Result 52 states and 110 transitions. 37.10/18.53 [2019-03-28 12:18:35,760 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 37.10/18.53 [2019-03-28 12:18:35,764 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 52 states and 110 transitions. 37.10/18.53 [2019-03-28 12:18:35,767 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 49 37.10/18.53 [2019-03-28 12:18:35,772 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 52 states to 52 states and 110 transitions. 37.10/18.53 [2019-03-28 12:18:35,773 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 52 37.10/18.53 [2019-03-28 12:18:35,774 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 52 37.10/18.53 [2019-03-28 12:18:35,775 INFO L73 IsDeterministic]: Start isDeterministic. Operand 52 states and 110 transitions. 37.10/18.53 [2019-03-28 12:18:35,775 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 37.10/18.53 [2019-03-28 12:18:35,775 INFO L706 BuchiCegarLoop]: Abstraction has 52 states and 110 transitions. 37.10/18.53 [2019-03-28 12:18:35,794 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states and 110 transitions. 37.10/18.53 [2019-03-28 12:18:35,806 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 52. 37.10/18.53 [2019-03-28 12:18:35,807 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 52 states. 37.10/18.53 [2019-03-28 12:18:35,808 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 110 transitions. 37.10/18.53 [2019-03-28 12:18:35,809 INFO L729 BuchiCegarLoop]: Abstraction has 52 states and 110 transitions. 37.10/18.53 [2019-03-28 12:18:35,810 INFO L609 BuchiCegarLoop]: Abstraction has 52 states and 110 transitions. 37.10/18.53 [2019-03-28 12:18:35,810 INFO L442 BuchiCegarLoop]: ======== Iteration 2============ 37.10/18.53 [2019-03-28 12:18:35,810 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 52 states and 110 transitions. 37.10/18.53 [2019-03-28 12:18:35,811 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 49 37.10/18.53 [2019-03-28 12:18:35,812 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 37.10/18.53 [2019-03-28 12:18:35,812 INFO L119 BuchiIsEmpty]: Starting construction of run 37.10/18.53 [2019-03-28 12:18:35,812 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1] 37.10/18.53 [2019-03-28 12:18:35,812 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] 37.10/18.53 [2019-03-28 12:18:35,813 INFO L794 eck$LassoCheckResult]: Stem: 151#ULTIMATE.startENTRY [520] ULTIMATE.startENTRY-->L196: Formula: (and (= v_~q_write_ev~0_11 v_~q_read_ev~0_11) (= 1 v_~c_dr_i~0_7) (= v_~q_free~0_11 1) (= v_~q_buf_0~0_5 0) (= v_~q_write_ev~0_11 2) (= 0 v_~p_last_write~0_6) (= 0 v_~c_last_read~0_6) (= v_~p_dw_pc~0_14 0) (= 0 v_~a_t~0_5) (= 0 v_~c_dr_st~0_15) (= v_~c_dr_pc~0_14 0) (= 0 v_~c_num_read~0_9) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 0) (= 0 v_~p_num_write~0_9) (= v_~p_dw_i~0_7 1) (= v_~p_dw_st~0_15 0)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ~p_last_write~0=v_~p_last_write~0_6, ~c_dr_pc~0=v_~c_dr_pc~0_14, ~c_dr_st~0=v_~c_dr_st~0_15, ~c_num_read~0=v_~c_num_read~0_9, ~p_num_write~0=v_~p_num_write~0_9, ~c_dr_i~0=v_~c_dr_i~0_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7, ~q_write_ev~0=v_~q_write_ev~0_11, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~p_dw_st~0=v_~p_dw_st~0_15, ~p_dw_i~0=v_~p_dw_i~0_7, ~c_last_read~0=v_~c_last_read~0_6, ~p_dw_pc~0=v_~p_dw_pc~0_14, ~q_free~0=v_~q_free~0_11, ~q_buf_0~0=v_~q_buf_0~0_5, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6, ~q_read_ev~0=v_~q_read_ev~0_11, ~a_t~0=v_~a_t~0_5} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ~p_last_write~0, ~c_dr_pc~0, ~c_dr_st~0, ~c_num_read~0, ~p_num_write~0, ~c_dr_i~0, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_~kernel_st~0, ~q_write_ev~0, ULTIMATE.start_main_#res, ~p_dw_st~0, ~p_dw_i~0, ~c_last_read~0, ~p_dw_pc~0, ~q_free~0, ~q_buf_0~0, ULTIMATE.start_main_~__retres1~3, ~q_read_ev~0, ~a_t~0] 152#L196 [453] L196-->L196-2: Formula: (and (> v_~p_dw_i~0_4 1) (= v_~p_dw_st~0_3 2)) InVars {~p_dw_i~0=v_~p_dw_i~0_4} OutVars{~p_dw_st~0=v_~p_dw_st~0_3, ~p_dw_i~0=v_~p_dw_i~0_4} AuxVars[] AssignedVars[~p_dw_st~0] 166#L196-2 [413] L196-2-->L313-1: Formula: (and (= 1 v_~c_dr_i~0_3) (= v_~c_dr_st~0_3 0)) InVars {~c_dr_i~0=v_~c_dr_i~0_3} OutVars{~c_dr_st~0=v_~c_dr_st~0_3, ~c_dr_i~0=v_~c_dr_i~0_3} AuxVars[] AssignedVars[~c_dr_st~0] 134#L313-1 37.10/18.53 [2019-03-28 12:18:35,814 INFO L796 eck$LassoCheckResult]: Loop: 134#L313-1 [521] L313-1-->L262: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_8 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_8, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_4|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_6, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_6, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp~1, ULTIMATE.start_eval_~tmp___0~1, ULTIMATE.start_eval_~tmp___1~0] 127#L262 [522] L262-->L214: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 163#L214 [406] L214-->L226: Formula: (and (= v_~p_dw_st~0_6 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11 1)) InVars {~p_dw_st~0=v_~p_dw_st~0_6} OutVars{~p_dw_st~0=v_~p_dw_st~0_6, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 139#L226 [523] L226-->L242: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___1~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_5|, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp___1~0] 140#L242 [524] L242-->L214-1: Formula: (= v_ULTIMATE.start_eval_~tmp___1~0_8 0) InVars {ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_17, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_7, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_stop_simulation_#t~ret6=|v_ULTIMATE.start_stop_simulation_#t~ret6_4|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_4|, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret6, ULTIMATE.start_stop_simulation_#res] 149#L214-1 [404] L214-1-->L226-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_4 1) (= v_~p_dw_st~0_4 0)) InVars {~p_dw_st~0=v_~p_dw_st~0_4} OutVars{~p_dw_st~0=v_~p_dw_st~0_4, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 137#L226-1 [525] L226-1-->L292: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18 |v_ULTIMATE.start_exists_runnable_thread_#res_10|) (= v_ULTIMATE.start_stop_simulation_~tmp~2_8 |v_ULTIMATE.start_exists_runnable_thread_#res_10|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_8, ULTIMATE.start_stop_simulation_#t~ret6=|v_ULTIMATE.start_stop_simulation_#t~ret6_5|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret6] 138#L292 [465] L292-->L299: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_4 0) (< 0 v_ULTIMATE.start_stop_simulation_~tmp~2_5)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_4, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 133#L299 [534] L299-->L313-1: Formula: (and (= 0 v_ULTIMATE.start_start_simulation_~tmp~3_9) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_9 |v_ULTIMATE.start_stop_simulation_#res_6|) (= |v_ULTIMATE.start_stop_simulation_#res_6| v_ULTIMATE.start_start_simulation_~tmp~3_9)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_9} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_6|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_~tmp~3] 134#L313-1 37.10/18.53 [2019-03-28 12:18:35,814 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.53 [2019-03-28 12:18:35,814 INFO L82 PathProgramCache]: Analyzing trace with hash 543967, now seen corresponding path program 1 times 37.10/18.53 [2019-03-28 12:18:35,814 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.53 [2019-03-28 12:18:35,814 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.53 [2019-03-28 12:18:35,815 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.53 [2019-03-28 12:18:35,815 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 37.10/18.53 [2019-03-28 12:18:35,816 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.53 [2019-03-28 12:18:35,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 37.10/18.53 [2019-03-28 12:18:35,832 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 37.10/18.53 [2019-03-28 12:18:35,832 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 37.10/18.53 [2019-03-28 12:18:35,832 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 37.10/18.53 [2019-03-28 12:18:35,832 INFO L799 eck$LassoCheckResult]: stem already infeasible 37.10/18.53 [2019-03-28 12:18:35,833 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.53 [2019-03-28 12:18:35,833 INFO L82 PathProgramCache]: Analyzing trace with hash 65342963, now seen corresponding path program 2 times 37.10/18.53 [2019-03-28 12:18:35,833 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.53 [2019-03-28 12:18:35,833 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.53 [2019-03-28 12:18:35,834 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.53 [2019-03-28 12:18:35,834 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 37.10/18.53 [2019-03-28 12:18:35,834 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.53 [2019-03-28 12:18:35,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 37.10/18.53 [2019-03-28 12:18:35,856 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 37.10/18.53 [2019-03-28 12:18:35,856 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 37.10/18.53 [2019-03-28 12:18:35,856 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 37.10/18.53 [2019-03-28 12:18:35,857 INFO L811 eck$LassoCheckResult]: loop already infeasible 37.10/18.53 [2019-03-28 12:18:35,857 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 37.10/18.53 [2019-03-28 12:18:35,857 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 37.10/18.53 [2019-03-28 12:18:35,857 INFO L87 Difference]: Start difference. First operand 52 states and 110 transitions. cyclomatic complexity: 59 Second operand 3 states. 37.10/18.53 [2019-03-28 12:18:35,935 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 37.10/18.53 [2019-03-28 12:18:35,936 INFO L93 Difference]: Finished difference Result 52 states and 109 transitions. 37.10/18.53 [2019-03-28 12:18:35,936 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 37.10/18.53 [2019-03-28 12:18:35,937 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 52 states and 109 transitions. 37.10/18.53 [2019-03-28 12:18:35,939 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 49 37.10/18.53 [2019-03-28 12:18:35,940 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 52 states to 52 states and 109 transitions. 37.10/18.53 [2019-03-28 12:18:35,940 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 52 37.10/18.53 [2019-03-28 12:18:35,941 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 52 37.10/18.53 [2019-03-28 12:18:35,941 INFO L73 IsDeterministic]: Start isDeterministic. Operand 52 states and 109 transitions. 37.10/18.53 [2019-03-28 12:18:35,942 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 37.10/18.53 [2019-03-28 12:18:35,942 INFO L706 BuchiCegarLoop]: Abstraction has 52 states and 109 transitions. 37.10/18.53 [2019-03-28 12:18:35,942 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states and 109 transitions. 37.10/18.53 [2019-03-28 12:18:35,945 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 52. 37.10/18.53 [2019-03-28 12:18:35,945 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 52 states. 37.10/18.53 [2019-03-28 12:18:35,946 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 109 transitions. 37.10/18.53 [2019-03-28 12:18:35,946 INFO L729 BuchiCegarLoop]: Abstraction has 52 states and 109 transitions. 37.10/18.53 [2019-03-28 12:18:35,946 INFO L609 BuchiCegarLoop]: Abstraction has 52 states and 109 transitions. 37.10/18.53 [2019-03-28 12:18:35,946 INFO L442 BuchiCegarLoop]: ======== Iteration 3============ 37.10/18.53 [2019-03-28 12:18:35,947 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 52 states and 109 transitions. 37.10/18.53 [2019-03-28 12:18:35,948 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 49 37.10/18.53 [2019-03-28 12:18:35,948 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 37.10/18.53 [2019-03-28 12:18:35,948 INFO L119 BuchiIsEmpty]: Starting construction of run 37.10/18.53 [2019-03-28 12:18:35,949 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1] 37.10/18.53 [2019-03-28 12:18:35,949 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] 37.10/18.53 [2019-03-28 12:18:35,949 INFO L794 eck$LassoCheckResult]: Stem: 263#ULTIMATE.startENTRY [520] ULTIMATE.startENTRY-->L196: Formula: (and (= v_~q_write_ev~0_11 v_~q_read_ev~0_11) (= 1 v_~c_dr_i~0_7) (= v_~q_free~0_11 1) (= v_~q_buf_0~0_5 0) (= v_~q_write_ev~0_11 2) (= 0 v_~p_last_write~0_6) (= 0 v_~c_last_read~0_6) (= v_~p_dw_pc~0_14 0) (= 0 v_~a_t~0_5) (= 0 v_~c_dr_st~0_15) (= v_~c_dr_pc~0_14 0) (= 0 v_~c_num_read~0_9) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 0) (= 0 v_~p_num_write~0_9) (= v_~p_dw_i~0_7 1) (= v_~p_dw_st~0_15 0)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ~p_last_write~0=v_~p_last_write~0_6, ~c_dr_pc~0=v_~c_dr_pc~0_14, ~c_dr_st~0=v_~c_dr_st~0_15, ~c_num_read~0=v_~c_num_read~0_9, ~p_num_write~0=v_~p_num_write~0_9, ~c_dr_i~0=v_~c_dr_i~0_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7, ~q_write_ev~0=v_~q_write_ev~0_11, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~p_dw_st~0=v_~p_dw_st~0_15, ~p_dw_i~0=v_~p_dw_i~0_7, ~c_last_read~0=v_~c_last_read~0_6, ~p_dw_pc~0=v_~p_dw_pc~0_14, ~q_free~0=v_~q_free~0_11, ~q_buf_0~0=v_~q_buf_0~0_5, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6, ~q_read_ev~0=v_~q_read_ev~0_11, ~a_t~0=v_~a_t~0_5} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ~p_last_write~0, ~c_dr_pc~0, ~c_dr_st~0, ~c_num_read~0, ~p_num_write~0, ~c_dr_i~0, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_~kernel_st~0, ~q_write_ev~0, ULTIMATE.start_main_#res, ~p_dw_st~0, ~p_dw_i~0, ~c_last_read~0, ~p_dw_pc~0, ~q_free~0, ~q_buf_0~0, ULTIMATE.start_main_~__retres1~3, ~q_read_ev~0, ~a_t~0] 264#L196 [418] L196-->L196-2: Formula: (and (= v_~p_dw_i~0_3 1) (= v_~p_dw_st~0_2 0)) InVars {~p_dw_i~0=v_~p_dw_i~0_3} OutVars{~p_dw_st~0=v_~p_dw_st~0_2, ~p_dw_i~0=v_~p_dw_i~0_3} AuxVars[] AssignedVars[~p_dw_st~0] 278#L196-2 [413] L196-2-->L313-1: Formula: (and (= 1 v_~c_dr_i~0_3) (= v_~c_dr_st~0_3 0)) InVars {~c_dr_i~0=v_~c_dr_i~0_3} OutVars{~c_dr_st~0=v_~c_dr_st~0_3, ~c_dr_i~0=v_~c_dr_i~0_3} AuxVars[] AssignedVars[~c_dr_st~0] 246#L313-1 37.10/18.53 [2019-03-28 12:18:35,950 INFO L796 eck$LassoCheckResult]: Loop: 246#L313-1 [521] L313-1-->L262: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_8 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_8, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_4|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_6, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_6, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp~1, ULTIMATE.start_eval_~tmp___0~1, ULTIMATE.start_eval_~tmp___1~0] 239#L262 [522] L262-->L214: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 275#L214 [406] L214-->L226: Formula: (and (= v_~p_dw_st~0_6 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11 1)) InVars {~p_dw_st~0=v_~p_dw_st~0_6} OutVars{~p_dw_st~0=v_~p_dw_st~0_6, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 251#L226 [523] L226-->L242: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___1~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_5|, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp___1~0] 252#L242 [524] L242-->L214-1: Formula: (= v_ULTIMATE.start_eval_~tmp___1~0_8 0) InVars {ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_17, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_7, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_stop_simulation_#t~ret6=|v_ULTIMATE.start_stop_simulation_#t~ret6_4|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_4|, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret6, ULTIMATE.start_stop_simulation_#res] 261#L214-1 [404] L214-1-->L226-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_4 1) (= v_~p_dw_st~0_4 0)) InVars {~p_dw_st~0=v_~p_dw_st~0_4} OutVars{~p_dw_st~0=v_~p_dw_st~0_4, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 249#L226-1 [525] L226-1-->L292: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18 |v_ULTIMATE.start_exists_runnable_thread_#res_10|) (= v_ULTIMATE.start_stop_simulation_~tmp~2_8 |v_ULTIMATE.start_exists_runnable_thread_#res_10|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_8, ULTIMATE.start_stop_simulation_#t~ret6=|v_ULTIMATE.start_stop_simulation_#t~ret6_5|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret6] 250#L292 [465] L292-->L299: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_4 0) (< 0 v_ULTIMATE.start_stop_simulation_~tmp~2_5)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_4, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 245#L299 [534] L299-->L313-1: Formula: (and (= 0 v_ULTIMATE.start_start_simulation_~tmp~3_9) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_9 |v_ULTIMATE.start_stop_simulation_#res_6|) (= |v_ULTIMATE.start_stop_simulation_#res_6| v_ULTIMATE.start_start_simulation_~tmp~3_9)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_9} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_6|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_~tmp~3] 246#L313-1 37.10/18.53 [2019-03-28 12:18:35,950 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.53 [2019-03-28 12:18:35,950 INFO L82 PathProgramCache]: Analyzing trace with hash 542882, now seen corresponding path program 1 times 37.10/18.53 [2019-03-28 12:18:35,950 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.53 [2019-03-28 12:18:35,950 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.53 [2019-03-28 12:18:35,951 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.53 [2019-03-28 12:18:35,952 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 37.10/18.53 [2019-03-28 12:18:35,952 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.53 [2019-03-28 12:18:35,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 37.10/18.53 [2019-03-28 12:18:35,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 37.10/18.53 [2019-03-28 12:18:35,981 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.53 [2019-03-28 12:18:35,982 INFO L82 PathProgramCache]: Analyzing trace with hash 65342963, now seen corresponding path program 3 times 37.10/18.53 [2019-03-28 12:18:35,982 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.53 [2019-03-28 12:18:35,982 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.53 [2019-03-28 12:18:35,983 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.53 [2019-03-28 12:18:35,983 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 37.10/18.53 [2019-03-28 12:18:35,983 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.53 [2019-03-28 12:18:35,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 37.10/18.53 [2019-03-28 12:18:36,002 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 37.10/18.53 [2019-03-28 12:18:36,002 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 37.10/18.53 [2019-03-28 12:18:36,002 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 37.10/18.53 [2019-03-28 12:18:36,003 INFO L811 eck$LassoCheckResult]: loop already infeasible 37.10/18.53 [2019-03-28 12:18:36,003 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. 37.10/18.53 [2019-03-28 12:18:36,003 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 37.10/18.53 [2019-03-28 12:18:36,003 INFO L87 Difference]: Start difference. First operand 52 states and 109 transitions. cyclomatic complexity: 58 Second operand 4 states. 37.10/18.53 [2019-03-28 12:18:36,360 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 37.10/18.53 [2019-03-28 12:18:36,360 INFO L93 Difference]: Finished difference Result 141 states and 290 transitions. 37.10/18.53 [2019-03-28 12:18:36,360 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. 37.10/18.53 [2019-03-28 12:18:36,361 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 141 states and 290 transitions. 37.10/18.53 [2019-03-28 12:18:36,364 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 138 37.10/18.53 [2019-03-28 12:18:36,366 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 141 states to 141 states and 290 transitions. 37.10/18.53 [2019-03-28 12:18:36,367 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 141 37.10/18.53 [2019-03-28 12:18:36,370 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 141 37.10/18.53 [2019-03-28 12:18:36,370 INFO L73 IsDeterministic]: Start isDeterministic. Operand 141 states and 290 transitions. 37.10/18.53 [2019-03-28 12:18:36,371 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 37.10/18.53 [2019-03-28 12:18:36,371 INFO L706 BuchiCegarLoop]: Abstraction has 141 states and 290 transitions. 37.10/18.53 [2019-03-28 12:18:36,372 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 141 states and 290 transitions. 37.10/18.53 [2019-03-28 12:18:36,377 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 141 to 54. 37.10/18.53 [2019-03-28 12:18:36,377 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. 37.10/18.53 [2019-03-28 12:18:36,377 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 111 transitions. 37.10/18.53 [2019-03-28 12:18:36,378 INFO L729 BuchiCegarLoop]: Abstraction has 54 states and 111 transitions. 37.10/18.53 [2019-03-28 12:18:36,378 INFO L609 BuchiCegarLoop]: Abstraction has 54 states and 111 transitions. 37.10/18.53 [2019-03-28 12:18:36,378 INFO L442 BuchiCegarLoop]: ======== Iteration 4============ 37.10/18.53 [2019-03-28 12:18:36,378 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54 states and 111 transitions. 37.10/18.53 [2019-03-28 12:18:36,379 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 51 37.10/18.53 [2019-03-28 12:18:36,379 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 37.10/18.53 [2019-03-28 12:18:36,379 INFO L119 BuchiIsEmpty]: Starting construction of run 37.10/18.53 [2019-03-28 12:18:36,380 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1] 37.10/18.53 [2019-03-28 12:18:36,380 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 37.10/18.53 [2019-03-28 12:18:36,380 INFO L794 eck$LassoCheckResult]: Stem: 464#ULTIMATE.startENTRY [520] ULTIMATE.startENTRY-->L196: Formula: (and (= v_~q_write_ev~0_11 v_~q_read_ev~0_11) (= 1 v_~c_dr_i~0_7) (= v_~q_free~0_11 1) (= v_~q_buf_0~0_5 0) (= v_~q_write_ev~0_11 2) (= 0 v_~p_last_write~0_6) (= 0 v_~c_last_read~0_6) (= v_~p_dw_pc~0_14 0) (= 0 v_~a_t~0_5) (= 0 v_~c_dr_st~0_15) (= v_~c_dr_pc~0_14 0) (= 0 v_~c_num_read~0_9) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 0) (= 0 v_~p_num_write~0_9) (= v_~p_dw_i~0_7 1) (= v_~p_dw_st~0_15 0)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ~p_last_write~0=v_~p_last_write~0_6, ~c_dr_pc~0=v_~c_dr_pc~0_14, ~c_dr_st~0=v_~c_dr_st~0_15, ~c_num_read~0=v_~c_num_read~0_9, ~p_num_write~0=v_~p_num_write~0_9, ~c_dr_i~0=v_~c_dr_i~0_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7, ~q_write_ev~0=v_~q_write_ev~0_11, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~p_dw_st~0=v_~p_dw_st~0_15, ~p_dw_i~0=v_~p_dw_i~0_7, ~c_last_read~0=v_~c_last_read~0_6, ~p_dw_pc~0=v_~p_dw_pc~0_14, ~q_free~0=v_~q_free~0_11, ~q_buf_0~0=v_~q_buf_0~0_5, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6, ~q_read_ev~0=v_~q_read_ev~0_11, ~a_t~0=v_~a_t~0_5} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ~p_last_write~0, ~c_dr_pc~0, ~c_dr_st~0, ~c_num_read~0, ~p_num_write~0, ~c_dr_i~0, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_~kernel_st~0, ~q_write_ev~0, ULTIMATE.start_main_#res, ~p_dw_st~0, ~p_dw_i~0, ~c_last_read~0, ~p_dw_pc~0, ~q_free~0, ~q_buf_0~0, ULTIMATE.start_main_~__retres1~3, ~q_read_ev~0, ~a_t~0] 465#L196 [418] L196-->L196-2: Formula: (and (= v_~p_dw_i~0_3 1) (= v_~p_dw_st~0_2 0)) InVars {~p_dw_i~0=v_~p_dw_i~0_3} OutVars{~p_dw_st~0=v_~p_dw_st~0_2, ~p_dw_i~0=v_~p_dw_i~0_3} AuxVars[] AssignedVars[~p_dw_st~0] 481#L196-2 [413] L196-2-->L313-1: Formula: (and (= 1 v_~c_dr_i~0_3) (= v_~c_dr_st~0_3 0)) InVars {~c_dr_i~0=v_~c_dr_i~0_3} OutVars{~c_dr_st~0=v_~c_dr_st~0_3, ~c_dr_i~0=v_~c_dr_i~0_3} AuxVars[] AssignedVars[~c_dr_st~0] 448#L313-1 37.10/18.53 [2019-03-28 12:18:36,381 INFO L796 eck$LassoCheckResult]: Loop: 448#L313-1 [521] L313-1-->L262: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_8 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_8, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_4|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_6, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_6, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp~1, ULTIMATE.start_eval_~tmp___0~1, ULTIMATE.start_eval_~tmp___1~0] 441#L262 [522] L262-->L214: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 477#L214 [459] L214-->L218: Formula: (< v_~p_dw_st~0_7 0) InVars {~p_dw_st~0=v_~p_dw_st~0_7} OutVars{~p_dw_st~0=v_~p_dw_st~0_7} AuxVars[] AssignedVars[] 475#L218 [464] L218-->L226: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_13 0) (> 0 v_~c_dr_st~0_8)) InVars {~c_dr_st~0=v_~c_dr_st~0_8} OutVars{~c_dr_st~0=v_~c_dr_st~0_8, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_13} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 476#L226 [523] L226-->L242: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___1~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_5|, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp___1~0] 482#L242 [524] L242-->L214-1: Formula: (= v_ULTIMATE.start_eval_~tmp___1~0_8 0) InVars {ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_17, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_7, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_stop_simulation_#t~ret6=|v_ULTIMATE.start_stop_simulation_#t~ret6_4|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_4|, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret6, ULTIMATE.start_stop_simulation_#res] 479#L214-1 [404] L214-1-->L226-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_4 1) (= v_~p_dw_st~0_4 0)) InVars {~p_dw_st~0=v_~p_dw_st~0_4} OutVars{~p_dw_st~0=v_~p_dw_st~0_4, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 451#L226-1 [525] L226-1-->L292: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18 |v_ULTIMATE.start_exists_runnable_thread_#res_10|) (= v_ULTIMATE.start_stop_simulation_~tmp~2_8 |v_ULTIMATE.start_exists_runnable_thread_#res_10|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_8, ULTIMATE.start_stop_simulation_#t~ret6=|v_ULTIMATE.start_stop_simulation_#t~ret6_5|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret6] 452#L292 [465] L292-->L299: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_4 0) (< 0 v_ULTIMATE.start_stop_simulation_~tmp~2_5)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_4, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 447#L299 [534] L299-->L313-1: Formula: (and (= 0 v_ULTIMATE.start_start_simulation_~tmp~3_9) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_9 |v_ULTIMATE.start_stop_simulation_#res_6|) (= |v_ULTIMATE.start_stop_simulation_#res_6| v_ULTIMATE.start_start_simulation_~tmp~3_9)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_9} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_6|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_~tmp~3] 448#L313-1 37.10/18.53 [2019-03-28 12:18:36,382 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.53 [2019-03-28 12:18:36,382 INFO L82 PathProgramCache]: Analyzing trace with hash 542882, now seen corresponding path program 2 times 37.10/18.53 [2019-03-28 12:18:36,382 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.53 [2019-03-28 12:18:36,382 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.53 [2019-03-28 12:18:36,383 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.53 [2019-03-28 12:18:36,383 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 37.10/18.53 [2019-03-28 12:18:36,383 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.53 [2019-03-28 12:18:36,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 37.10/18.53 [2019-03-28 12:18:36,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 37.10/18.53 [2019-03-28 12:18:36,396 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.53 [2019-03-28 12:18:36,396 INFO L82 PathProgramCache]: Analyzing trace with hash -839165818, now seen corresponding path program 1 times 37.10/18.53 [2019-03-28 12:18:36,396 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.53 [2019-03-28 12:18:36,396 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.53 [2019-03-28 12:18:36,397 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.53 [2019-03-28 12:18:36,397 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 37.10/18.53 [2019-03-28 12:18:36,398 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.53 [2019-03-28 12:18:36,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 37.10/18.53 [2019-03-28 12:18:36,414 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 37.10/18.53 [2019-03-28 12:18:36,414 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 37.10/18.53 [2019-03-28 12:18:36,414 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 37.10/18.53 [2019-03-28 12:18:36,415 INFO L811 eck$LassoCheckResult]: loop already infeasible 37.10/18.53 [2019-03-28 12:18:36,415 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 37.10/18.53 [2019-03-28 12:18:36,415 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 37.10/18.53 [2019-03-28 12:18:36,415 INFO L87 Difference]: Start difference. First operand 54 states and 111 transitions. cyclomatic complexity: 58 Second operand 3 states. 37.10/18.53 [2019-03-28 12:18:36,582 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 37.10/18.53 [2019-03-28 12:18:36,582 INFO L93 Difference]: Finished difference Result 87 states and 174 transitions. 37.10/18.53 [2019-03-28 12:18:36,582 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 37.10/18.53 [2019-03-28 12:18:36,583 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 87 states and 174 transitions. 37.10/18.53 [2019-03-28 12:18:36,584 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 84 37.10/18.53 [2019-03-28 12:18:36,586 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 87 states to 87 states and 174 transitions. 37.10/18.53 [2019-03-28 12:18:36,586 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 87 37.10/18.53 [2019-03-28 12:18:36,586 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 87 37.10/18.53 [2019-03-28 12:18:36,587 INFO L73 IsDeterministic]: Start isDeterministic. Operand 87 states and 174 transitions. 37.10/18.53 [2019-03-28 12:18:36,587 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 37.10/18.53 [2019-03-28 12:18:36,587 INFO L706 BuchiCegarLoop]: Abstraction has 87 states and 174 transitions. 37.10/18.53 [2019-03-28 12:18:36,588 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 87 states and 174 transitions. 37.10/18.53 [2019-03-28 12:18:36,593 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 87 to 87. 37.10/18.53 [2019-03-28 12:18:36,593 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 87 states. 37.10/18.53 [2019-03-28 12:18:36,594 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 174 transitions. 37.10/18.53 [2019-03-28 12:18:36,594 INFO L729 BuchiCegarLoop]: Abstraction has 87 states and 174 transitions. 37.10/18.53 [2019-03-28 12:18:36,594 INFO L609 BuchiCegarLoop]: Abstraction has 87 states and 174 transitions. 37.10/18.53 [2019-03-28 12:18:36,594 INFO L442 BuchiCegarLoop]: ======== Iteration 5============ 37.10/18.53 [2019-03-28 12:18:36,594 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 87 states and 174 transitions. 37.10/18.53 [2019-03-28 12:18:36,595 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 84 37.10/18.53 [2019-03-28 12:18:36,596 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 37.10/18.53 [2019-03-28 12:18:36,596 INFO L119 BuchiIsEmpty]: Starting construction of run 37.10/18.53 [2019-03-28 12:18:36,596 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1] 37.10/18.53 [2019-03-28 12:18:36,596 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 37.10/18.53 [2019-03-28 12:18:36,597 INFO L794 eck$LassoCheckResult]: Stem: 612#ULTIMATE.startENTRY [520] ULTIMATE.startENTRY-->L196: Formula: (and (= v_~q_write_ev~0_11 v_~q_read_ev~0_11) (= 1 v_~c_dr_i~0_7) (= v_~q_free~0_11 1) (= v_~q_buf_0~0_5 0) (= v_~q_write_ev~0_11 2) (= 0 v_~p_last_write~0_6) (= 0 v_~c_last_read~0_6) (= v_~p_dw_pc~0_14 0) (= 0 v_~a_t~0_5) (= 0 v_~c_dr_st~0_15) (= v_~c_dr_pc~0_14 0) (= 0 v_~c_num_read~0_9) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 0) (= 0 v_~p_num_write~0_9) (= v_~p_dw_i~0_7 1) (= v_~p_dw_st~0_15 0)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ~p_last_write~0=v_~p_last_write~0_6, ~c_dr_pc~0=v_~c_dr_pc~0_14, ~c_dr_st~0=v_~c_dr_st~0_15, ~c_num_read~0=v_~c_num_read~0_9, ~p_num_write~0=v_~p_num_write~0_9, ~c_dr_i~0=v_~c_dr_i~0_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7, ~q_write_ev~0=v_~q_write_ev~0_11, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~p_dw_st~0=v_~p_dw_st~0_15, ~p_dw_i~0=v_~p_dw_i~0_7, ~c_last_read~0=v_~c_last_read~0_6, ~p_dw_pc~0=v_~p_dw_pc~0_14, ~q_free~0=v_~q_free~0_11, ~q_buf_0~0=v_~q_buf_0~0_5, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6, ~q_read_ev~0=v_~q_read_ev~0_11, ~a_t~0=v_~a_t~0_5} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ~p_last_write~0, ~c_dr_pc~0, ~c_dr_st~0, ~c_num_read~0, ~p_num_write~0, ~c_dr_i~0, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_~kernel_st~0, ~q_write_ev~0, ULTIMATE.start_main_#res, ~p_dw_st~0, ~p_dw_i~0, ~c_last_read~0, ~p_dw_pc~0, ~q_free~0, ~q_buf_0~0, ULTIMATE.start_main_~__retres1~3, ~q_read_ev~0, ~a_t~0] 613#L196 [418] L196-->L196-2: Formula: (and (= v_~p_dw_i~0_3 1) (= v_~p_dw_st~0_2 0)) InVars {~p_dw_i~0=v_~p_dw_i~0_3} OutVars{~p_dw_st~0=v_~p_dw_st~0_2, ~p_dw_i~0=v_~p_dw_i~0_3} AuxVars[] AssignedVars[~p_dw_st~0] 631#L196-2 [413] L196-2-->L313-1: Formula: (and (= 1 v_~c_dr_i~0_3) (= v_~c_dr_st~0_3 0)) InVars {~c_dr_i~0=v_~c_dr_i~0_3} OutVars{~c_dr_st~0=v_~c_dr_st~0_3, ~c_dr_i~0=v_~c_dr_i~0_3} AuxVars[] AssignedVars[~c_dr_st~0] 623#L313-1 37.10/18.53 [2019-03-28 12:18:36,597 INFO L796 eck$LassoCheckResult]: Loop: 623#L313-1 [521] L313-1-->L262: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_8 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_8, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_4|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_6, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_6, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp~1, ULTIMATE.start_eval_~tmp___0~1, ULTIMATE.start_eval_~tmp___1~0] 588#L262 [522] L262-->L214: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 625#L214 [460] L214-->L218: Formula: (> v_~p_dw_st~0_7 0) InVars {~p_dw_st~0=v_~p_dw_st~0_7} OutVars{~p_dw_st~0=v_~p_dw_st~0_7} AuxVars[] AssignedVars[] 638#L218 [464] L218-->L226: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_13 0) (> 0 v_~c_dr_st~0_8)) InVars {~c_dr_st~0=v_~c_dr_st~0_8} OutVars{~c_dr_st~0=v_~c_dr_st~0_8, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_13} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 636#L226 [523] L226-->L242: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___1~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_5|, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp___1~0] 633#L242 [524] L242-->L214-1: Formula: (= v_ULTIMATE.start_eval_~tmp___1~0_8 0) InVars {ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_17, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_7, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_stop_simulation_#t~ret6=|v_ULTIMATE.start_stop_simulation_#t~ret6_4|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_4|, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret6, ULTIMATE.start_stop_simulation_#res] 634#L214-1 [404] L214-1-->L226-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_4 1) (= v_~p_dw_st~0_4 0)) InVars {~p_dw_st~0=v_~p_dw_st~0_4} OutVars{~p_dw_st~0=v_~p_dw_st~0_4, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_4} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 650#L226-1 [525] L226-1-->L292: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18 |v_ULTIMATE.start_exists_runnable_thread_#res_10|) (= v_ULTIMATE.start_stop_simulation_~tmp~2_8 |v_ULTIMATE.start_exists_runnable_thread_#res_10|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_8, ULTIMATE.start_stop_simulation_#t~ret6=|v_ULTIMATE.start_stop_simulation_#t~ret6_5|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret6] 648#L292 [465] L292-->L299: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_4 0) (< 0 v_ULTIMATE.start_stop_simulation_~tmp~2_5)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_4, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 647#L299 [534] L299-->L313-1: Formula: (and (= 0 v_ULTIMATE.start_start_simulation_~tmp~3_9) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_9 |v_ULTIMATE.start_stop_simulation_#res_6|) (= |v_ULTIMATE.start_stop_simulation_#res_6| v_ULTIMATE.start_start_simulation_~tmp~3_9)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_9} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_6|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_~tmp~3] 623#L313-1 37.10/18.53 [2019-03-28 12:18:36,598 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.53 [2019-03-28 12:18:36,598 INFO L82 PathProgramCache]: Analyzing trace with hash 542882, now seen corresponding path program 3 times 37.10/18.53 [2019-03-28 12:18:36,598 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.53 [2019-03-28 12:18:36,598 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.53 [2019-03-28 12:18:36,599 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.53 [2019-03-28 12:18:36,599 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 37.10/18.53 [2019-03-28 12:18:36,600 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.53 [2019-03-28 12:18:36,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 37.10/18.53 [2019-03-28 12:18:36,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 37.10/18.53 [2019-03-28 12:18:36,610 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.53 [2019-03-28 12:18:36,610 INFO L82 PathProgramCache]: Analyzing trace with hash 903644517, now seen corresponding path program 1 times 37.10/18.53 [2019-03-28 12:18:36,611 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.53 [2019-03-28 12:18:36,611 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.53 [2019-03-28 12:18:36,612 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.53 [2019-03-28 12:18:36,612 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 37.10/18.53 [2019-03-28 12:18:36,612 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.53 [2019-03-28 12:18:36,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 37.10/18.53 [2019-03-28 12:18:36,626 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 37.10/18.53 [2019-03-28 12:18:36,626 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 37.10/18.53 [2019-03-28 12:18:36,626 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 37.10/18.53 [2019-03-28 12:18:36,626 INFO L811 eck$LassoCheckResult]: loop already infeasible 37.10/18.53 [2019-03-28 12:18:36,627 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 37.10/18.53 [2019-03-28 12:18:36,627 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 37.10/18.53 [2019-03-28 12:18:36,628 INFO L87 Difference]: Start difference. First operand 87 states and 174 transitions. cyclomatic complexity: 88 Second operand 3 states. 37.10/18.53 [2019-03-28 12:18:36,765 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 37.10/18.53 [2019-03-28 12:18:36,766 INFO L93 Difference]: Finished difference Result 123 states and 236 transitions. 37.10/18.53 [2019-03-28 12:18:36,766 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 37.10/18.53 [2019-03-28 12:18:36,767 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 123 states and 236 transitions. 37.10/18.53 [2019-03-28 12:18:36,768 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 119 37.10/18.53 [2019-03-28 12:18:36,770 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 123 states to 123 states and 236 transitions. 37.10/18.53 [2019-03-28 12:18:36,770 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 123 37.10/18.53 [2019-03-28 12:18:36,771 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 123 37.10/18.53 [2019-03-28 12:18:36,771 INFO L73 IsDeterministic]: Start isDeterministic. Operand 123 states and 236 transitions. 37.10/18.53 [2019-03-28 12:18:36,772 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 37.10/18.53 [2019-03-28 12:18:36,772 INFO L706 BuchiCegarLoop]: Abstraction has 123 states and 236 transitions. 37.10/18.53 [2019-03-28 12:18:36,772 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 123 states and 236 transitions. 37.10/18.53 [2019-03-28 12:18:36,779 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 123 to 108. 37.10/18.53 [2019-03-28 12:18:36,779 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 108 states. 37.10/18.53 [2019-03-28 12:18:36,780 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108 states to 108 states and 207 transitions. 37.10/18.53 [2019-03-28 12:18:36,780 INFO L729 BuchiCegarLoop]: Abstraction has 108 states and 207 transitions. 37.10/18.53 [2019-03-28 12:18:36,780 INFO L609 BuchiCegarLoop]: Abstraction has 108 states and 207 transitions. 37.10/18.53 [2019-03-28 12:18:36,780 INFO L442 BuchiCegarLoop]: ======== Iteration 6============ 37.10/18.53 [2019-03-28 12:18:36,780 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 108 states and 207 transitions. 37.10/18.53 [2019-03-28 12:18:36,781 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 104 37.10/18.53 [2019-03-28 12:18:36,781 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 37.10/18.53 [2019-03-28 12:18:36,782 INFO L119 BuchiIsEmpty]: Starting construction of run 37.10/18.53 [2019-03-28 12:18:36,782 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1] 37.10/18.53 [2019-03-28 12:18:36,783 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 37.10/18.53 [2019-03-28 12:18:36,783 INFO L794 eck$LassoCheckResult]: Stem: 831#ULTIMATE.startENTRY [520] ULTIMATE.startENTRY-->L196: Formula: (and (= v_~q_write_ev~0_11 v_~q_read_ev~0_11) (= 1 v_~c_dr_i~0_7) (= v_~q_free~0_11 1) (= v_~q_buf_0~0_5 0) (= v_~q_write_ev~0_11 2) (= 0 v_~p_last_write~0_6) (= 0 v_~c_last_read~0_6) (= v_~p_dw_pc~0_14 0) (= 0 v_~a_t~0_5) (= 0 v_~c_dr_st~0_15) (= v_~c_dr_pc~0_14 0) (= 0 v_~c_num_read~0_9) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 0) (= 0 v_~p_num_write~0_9) (= v_~p_dw_i~0_7 1) (= v_~p_dw_st~0_15 0)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ~p_last_write~0=v_~p_last_write~0_6, ~c_dr_pc~0=v_~c_dr_pc~0_14, ~c_dr_st~0=v_~c_dr_st~0_15, ~c_num_read~0=v_~c_num_read~0_9, ~p_num_write~0=v_~p_num_write~0_9, ~c_dr_i~0=v_~c_dr_i~0_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7, ~q_write_ev~0=v_~q_write_ev~0_11, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~p_dw_st~0=v_~p_dw_st~0_15, ~p_dw_i~0=v_~p_dw_i~0_7, ~c_last_read~0=v_~c_last_read~0_6, ~p_dw_pc~0=v_~p_dw_pc~0_14, ~q_free~0=v_~q_free~0_11, ~q_buf_0~0=v_~q_buf_0~0_5, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6, ~q_read_ev~0=v_~q_read_ev~0_11, ~a_t~0=v_~a_t~0_5} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ~p_last_write~0, ~c_dr_pc~0, ~c_dr_st~0, ~c_num_read~0, ~p_num_write~0, ~c_dr_i~0, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_~kernel_st~0, ~q_write_ev~0, ULTIMATE.start_main_#res, ~p_dw_st~0, ~p_dw_i~0, ~c_last_read~0, ~p_dw_pc~0, ~q_free~0, ~q_buf_0~0, ULTIMATE.start_main_~__retres1~3, ~q_read_ev~0, ~a_t~0] 832#L196 [418] L196-->L196-2: Formula: (and (= v_~p_dw_i~0_3 1) (= v_~p_dw_st~0_2 0)) InVars {~p_dw_i~0=v_~p_dw_i~0_3} OutVars{~p_dw_st~0=v_~p_dw_st~0_2, ~p_dw_i~0=v_~p_dw_i~0_3} AuxVars[] AssignedVars[~p_dw_st~0] 853#L196-2 [413] L196-2-->L313-1: Formula: (and (= 1 v_~c_dr_i~0_3) (= v_~c_dr_st~0_3 0)) InVars {~c_dr_i~0=v_~c_dr_i~0_3} OutVars{~c_dr_st~0=v_~c_dr_st~0_3, ~c_dr_i~0=v_~c_dr_i~0_3} AuxVars[] AssignedVars[~c_dr_st~0] 854#L313-1 [521] L313-1-->L262: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_8 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_8, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_4|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_6, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_6, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp~1, ULTIMATE.start_eval_~tmp___0~1, ULTIMATE.start_eval_~tmp___1~0] 861#L262 37.10/18.53 [2019-03-28 12:18:36,784 INFO L796 eck$LassoCheckResult]: Loop: 861#L262 [522] L262-->L214: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 859#L214 [406] L214-->L226: Formula: (and (= v_~p_dw_st~0_6 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11 1)) InVars {~p_dw_st~0=v_~p_dw_st~0_6} OutVars{~p_dw_st~0=v_~p_dw_st~0_6, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 858#L226 [523] L226-->L242: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___1~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_5|, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp___1~0] 857#L242 [468] L242-->L242-1: Formula: (> v_ULTIMATE.start_eval_~tmp___1~0_4 0) InVars {ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} OutVars{ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} AuxVars[] AssignedVars[] 855#L242-1 [470] L242-1-->L247: Formula: (< v_~p_dw_st~0_12 0) InVars {~p_dw_st~0=v_~p_dw_st~0_12} OutVars{~p_dw_st~0=v_~p_dw_st~0_12} AuxVars[] AssignedVars[] 856#L247 [410] L247-->L266: Formula: (and (= 0 v_~c_dr_st~0_10) (= v_ULTIMATE.start_eval_~tmp___0~1_4 |v_ULTIMATE.start_eval_#t~nondet5_3|)) InVars {~c_dr_st~0=v_~c_dr_st~0_10, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_3|} OutVars{~c_dr_st~0=v_~c_dr_st~0_10, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_4, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_2|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp___0~1] 877#L266 [480] L266-->L139: Formula: (and (= v_~c_dr_st~0_11 1) (> v_ULTIMATE.start_eval_~tmp___0~1_5 0)) InVars {ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_5} OutVars{~c_dr_st~0=v_~c_dr_st~0_11, ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_1, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_5} AuxVars[] AssignedVars[~c_dr_st~0, ULTIMATE.start_do_read_c_~a~0] 878#L139 [483] L139-->L142: Formula: (< 0 v_~c_dr_pc~0_6) InVars {~c_dr_pc~0=v_~c_dr_pc~0_6} OutVars{~c_dr_pc~0=v_~c_dr_pc~0_6} AuxVars[] AssignedVars[] 882#L142 [526] L142-->L152-1: Formula: (and (= v_~c_dr_pc~0_15 1) (= v_ULTIMATE.start_do_read_c_~a~0_6 v_~a_t~0_6)) InVars {~c_dr_pc~0=v_~c_dr_pc~0_15, ~a_t~0=v_~a_t~0_6} OutVars{ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_6, ~c_dr_pc~0=v_~c_dr_pc~0_15, ~a_t~0=v_~a_t~0_6} AuxVars[] AssignedVars[ULTIMATE.start_do_read_c_~a~0] 852#L152-1 [412] L152-1-->L32-3: Formula: (and (= v_~c_num_read~0_3 (+ v_~c_num_read~0_4 1)) (= v_~q_read_ev~0_5 1) (= v_ULTIMATE.start_do_read_c_~a~0_5 v_~q_buf_0~0_3) (= v_~c_last_read~0_2 v_ULTIMATE.start_do_read_c_~a~0_5) (= v_~q_free~0_8 1)) InVars {~c_num_read~0=v_~c_num_read~0_4, ~q_buf_0~0=v_~q_buf_0~0_3} OutVars{~c_num_read~0=v_~c_num_read~0_3, ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_6, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_6, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_4|, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_4|, ~c_last_read~0=v_~c_last_read~0_2, ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_5, ~q_free~0=v_~q_free~0_8, ~q_buf_0~0=v_~q_buf_0~0_3, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_4|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_6, ~q_read_ev~0=v_~q_read_ev~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0, ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret1, ~c_last_read~0, ULTIMATE.start_do_read_c_~a~0, ~c_num_read~0, ~q_free~0, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0, ~q_read_ev~0] 848#L32-3 [396] L32-3-->L33-1: Formula: (= v_~p_dw_pc~0_10 1) InVars {~p_dw_pc~0=v_~p_dw_pc~0_10} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_10} AuxVars[] AssignedVars[] 829#L33-1 [346] L33-1-->L43-1: Formula: (and (= 1 v_~q_read_ev~0_6) (= v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_8 1)) InVars {~q_read_ev~0=v_~q_read_ev~0_6} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_8, ~q_read_ev~0=v_~q_read_ev~0_6} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0] 802#L43-1 [531] L43-1-->L74-3: Formula: (and (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_8| v_ULTIMATE.start_immediate_notify_threads_~tmp~0_12) (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_8| v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_12)) InVars {ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_12} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_12, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_8|, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_8|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_12} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 803#L74-3 [503] L74-3-->L74-5: Formula: (and (> v_ULTIMATE.start_immediate_notify_threads_~tmp~0_9 0) (= v_~p_dw_st~0_13 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_9} OutVars{~p_dw_st~0=v_~p_dw_st~0_13, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_9} AuxVars[] AssignedVars[~p_dw_st~0] 826#L74-5 [332] L74-5-->L51-3: Formula: true InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_4|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_7} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_#res, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 870#L51-3 [305] L51-3-->L52-1: Formula: (= v_~c_dr_pc~0_10 1) InVars {~c_dr_pc~0=v_~c_dr_pc~0_10} OutVars{~c_dr_pc~0=v_~c_dr_pc~0_10} AuxVars[] AssignedVars[] 868#L52-1 [340] L52-1-->L62-1: Formula: (and (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_10 1) (= v_~q_write_ev~0_7 1)) InVars {~q_write_ev~0=v_~q_write_ev~0_7} OutVars{~q_write_ev~0=v_~q_write_ev~0_7, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_10} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 867#L62-1 [533] L62-1-->L82-3: Formula: (and (= v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_12 |v_ULTIMATE.start_is_do_read_c_triggered_#res_8|) (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_14 |v_ULTIMATE.start_is_do_read_c_triggered_#res_8|)) InVars {ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_14} OutVars{ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_12, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_8|, ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_8|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_14} AuxVars[] AssignedVars[ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_immediate_notify_threads_#t~ret1, ULTIMATE.start_is_do_read_c_triggered_#res] 866#L82-3 [513] L82-3-->L82-5: Formula: (and (< v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_9 0) (= v_~c_dr_st~0_13 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_9} OutVars{~c_dr_st~0=v_~c_dr_st~0_13, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_9} AuxVars[] AssignedVars[~c_dr_st~0] 865#L82-5 [536] L82-5-->L10-2: Formula: (and (= v_~p_num_write~0_10 v_~c_num_read~0_10) (= 2 v_~q_read_ev~0_13) (= v_~c_last_read~0_8 v_~p_last_write~0_8)) InVars {~p_last_write~0=v_~p_last_write~0_8, ~c_last_read~0=v_~c_last_read~0_8, ~c_num_read~0=v_~c_num_read~0_10, ~p_num_write~0=v_~p_num_write~0_10} OutVars{~p_last_write~0=v_~p_last_write~0_8, ~c_last_read~0=v_~c_last_read~0_8, ~c_num_read~0=v_~c_num_read~0_10, ~p_num_write~0=v_~p_num_write~0_10, ~q_read_ev~0=v_~q_read_ev~0_13} AuxVars[] AssignedVars[~q_read_ev~0] 864#L10-2 [400] L10-2-->L151: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 862#L151 [380] L151-->L262: Formula: (and (= v_~c_dr_st~0_12 2) (= v_~c_dr_pc~0_9 1) (= v_~a_t~0_2 v_ULTIMATE.start_do_read_c_~a~0_3) (= v_~q_free~0_6 1)) InVars {ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_3, ~q_free~0=v_~q_free~0_6} OutVars{ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_3, ~c_dr_pc~0=v_~c_dr_pc~0_9, ~c_dr_st~0=v_~c_dr_st~0_12, ~q_free~0=v_~q_free~0_6, ~a_t~0=v_~a_t~0_2} AuxVars[] AssignedVars[~c_dr_pc~0, ~c_dr_st~0, ~a_t~0] 861#L262 37.10/18.54 [2019-03-28 12:18:36,785 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.54 [2019-03-28 12:18:36,785 INFO L82 PathProgramCache]: Analyzing trace with hash 16829863, now seen corresponding path program 1 times 37.10/18.54 [2019-03-28 12:18:36,785 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.54 [2019-03-28 12:18:36,785 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.54 [2019-03-28 12:18:36,786 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:36,787 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:36,787 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:36,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 37.10/18.54 [2019-03-28 12:18:36,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 37.10/18.54 [2019-03-28 12:18:36,797 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.54 [2019-03-28 12:18:36,798 INFO L82 PathProgramCache]: Analyzing trace with hash -1896095386, now seen corresponding path program 1 times 37.10/18.54 [2019-03-28 12:18:36,798 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.54 [2019-03-28 12:18:36,798 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.54 [2019-03-28 12:18:36,799 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:36,799 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:36,799 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:36,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 37.10/18.54 [2019-03-28 12:18:36,814 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 37.10/18.54 [2019-03-28 12:18:36,815 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 37.10/18.54 [2019-03-28 12:18:36,815 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 37.10/18.54 [2019-03-28 12:18:36,815 INFO L811 eck$LassoCheckResult]: loop already infeasible 37.10/18.54 [2019-03-28 12:18:36,815 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 37.10/18.54 [2019-03-28 12:18:36,816 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 37.10/18.54 [2019-03-28 12:18:36,816 INFO L87 Difference]: Start difference. First operand 108 states and 207 transitions. cyclomatic complexity: 100 Second operand 3 states. 37.10/18.54 [2019-03-28 12:18:36,900 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 37.10/18.54 [2019-03-28 12:18:36,900 INFO L93 Difference]: Finished difference Result 75 states and 142 transitions. 37.10/18.54 [2019-03-28 12:18:36,901 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 37.10/18.54 [2019-03-28 12:18:36,901 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 75 states and 142 transitions. 37.10/18.54 [2019-03-28 12:18:36,902 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 37.10/18.54 [2019-03-28 12:18:36,903 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 75 states to 75 states and 142 transitions. 37.10/18.54 [2019-03-28 12:18:36,903 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 75 37.10/18.54 [2019-03-28 12:18:36,904 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 75 37.10/18.54 [2019-03-28 12:18:36,904 INFO L73 IsDeterministic]: Start isDeterministic. Operand 75 states and 142 transitions. 37.10/18.54 [2019-03-28 12:18:36,904 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 37.10/18.54 [2019-03-28 12:18:36,904 INFO L706 BuchiCegarLoop]: Abstraction has 75 states and 142 transitions. 37.10/18.54 [2019-03-28 12:18:36,905 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75 states and 142 transitions. 37.10/18.54 [2019-03-28 12:18:36,908 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75 to 75. 37.10/18.54 [2019-03-28 12:18:36,909 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 75 states. 37.10/18.54 [2019-03-28 12:18:36,909 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75 states to 75 states and 142 transitions. 37.10/18.54 [2019-03-28 12:18:36,909 INFO L729 BuchiCegarLoop]: Abstraction has 75 states and 142 transitions. 37.10/18.54 [2019-03-28 12:18:36,910 INFO L609 BuchiCegarLoop]: Abstraction has 75 states and 142 transitions. 37.10/18.54 [2019-03-28 12:18:36,910 INFO L442 BuchiCegarLoop]: ======== Iteration 7============ 37.10/18.54 [2019-03-28 12:18:36,910 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 75 states and 142 transitions. 37.10/18.54 [2019-03-28 12:18:36,911 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 37.10/18.54 [2019-03-28 12:18:36,911 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 37.10/18.54 [2019-03-28 12:18:36,911 INFO L119 BuchiIsEmpty]: Starting construction of run 37.10/18.54 [2019-03-28 12:18:36,911 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1] 37.10/18.54 [2019-03-28 12:18:36,912 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 37.10/18.54 [2019-03-28 12:18:36,912 INFO L794 eck$LassoCheckResult]: Stem: 1018#ULTIMATE.startENTRY [520] ULTIMATE.startENTRY-->L196: Formula: (and (= v_~q_write_ev~0_11 v_~q_read_ev~0_11) (= 1 v_~c_dr_i~0_7) (= v_~q_free~0_11 1) (= v_~q_buf_0~0_5 0) (= v_~q_write_ev~0_11 2) (= 0 v_~p_last_write~0_6) (= 0 v_~c_last_read~0_6) (= v_~p_dw_pc~0_14 0) (= 0 v_~a_t~0_5) (= 0 v_~c_dr_st~0_15) (= v_~c_dr_pc~0_14 0) (= 0 v_~c_num_read~0_9) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 0) (= 0 v_~p_num_write~0_9) (= v_~p_dw_i~0_7 1) (= v_~p_dw_st~0_15 0)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ~p_last_write~0=v_~p_last_write~0_6, ~c_dr_pc~0=v_~c_dr_pc~0_14, ~c_dr_st~0=v_~c_dr_st~0_15, ~c_num_read~0=v_~c_num_read~0_9, ~p_num_write~0=v_~p_num_write~0_9, ~c_dr_i~0=v_~c_dr_i~0_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7, ~q_write_ev~0=v_~q_write_ev~0_11, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~p_dw_st~0=v_~p_dw_st~0_15, ~p_dw_i~0=v_~p_dw_i~0_7, ~c_last_read~0=v_~c_last_read~0_6, ~p_dw_pc~0=v_~p_dw_pc~0_14, ~q_free~0=v_~q_free~0_11, ~q_buf_0~0=v_~q_buf_0~0_5, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6, ~q_read_ev~0=v_~q_read_ev~0_11, ~a_t~0=v_~a_t~0_5} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ~p_last_write~0, ~c_dr_pc~0, ~c_dr_st~0, ~c_num_read~0, ~p_num_write~0, ~c_dr_i~0, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_~kernel_st~0, ~q_write_ev~0, ULTIMATE.start_main_#res, ~p_dw_st~0, ~p_dw_i~0, ~c_last_read~0, ~p_dw_pc~0, ~q_free~0, ~q_buf_0~0, ULTIMATE.start_main_~__retres1~3, ~q_read_ev~0, ~a_t~0] 1019#L196 [418] L196-->L196-2: Formula: (and (= v_~p_dw_i~0_3 1) (= v_~p_dw_st~0_2 0)) InVars {~p_dw_i~0=v_~p_dw_i~0_3} OutVars{~p_dw_st~0=v_~p_dw_st~0_2, ~p_dw_i~0=v_~p_dw_i~0_3} AuxVars[] AssignedVars[~p_dw_st~0] 1040#L196-2 [413] L196-2-->L313-1: Formula: (and (= 1 v_~c_dr_i~0_3) (= v_~c_dr_st~0_3 0)) InVars {~c_dr_i~0=v_~c_dr_i~0_3} OutVars{~c_dr_st~0=v_~c_dr_st~0_3, ~c_dr_i~0=v_~c_dr_i~0_3} AuxVars[] AssignedVars[~c_dr_st~0] 1034#L313-1 [521] L313-1-->L262: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_8 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_8, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_4|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_6, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_6, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp~1, ULTIMATE.start_eval_~tmp___0~1, ULTIMATE.start_eval_~tmp___1~0] 1030#L262 37.10/18.54 [2019-03-28 12:18:36,913 INFO L796 eck$LassoCheckResult]: Loop: 1030#L262 [522] L262-->L214: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 1045#L214 [406] L214-->L226: Formula: (and (= v_~p_dw_st~0_6 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11 1)) InVars {~p_dw_st~0=v_~p_dw_st~0_6} OutVars{~p_dw_st~0=v_~p_dw_st~0_6, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 1044#L226 [523] L226-->L242: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___1~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_5|, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp___1~0] 1043#L242 [468] L242-->L242-1: Formula: (> v_ULTIMATE.start_eval_~tmp___1~0_4 0) InVars {ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} OutVars{ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} AuxVars[] AssignedVars[] 1042#L242-1 [469] L242-1-->L247: Formula: (> v_~p_dw_st~0_12 0) InVars {~p_dw_st~0=v_~p_dw_st~0_12} OutVars{~p_dw_st~0=v_~p_dw_st~0_12} AuxVars[] AssignedVars[] 1014#L247 [410] L247-->L266: Formula: (and (= 0 v_~c_dr_st~0_10) (= v_ULTIMATE.start_eval_~tmp___0~1_4 |v_ULTIMATE.start_eval_#t~nondet5_3|)) InVars {~c_dr_st~0=v_~c_dr_st~0_10, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_3|} OutVars{~c_dr_st~0=v_~c_dr_st~0_10, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_4, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_2|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp___0~1] 991#L266 [480] L266-->L139: Formula: (and (= v_~c_dr_st~0_11 1) (> v_ULTIMATE.start_eval_~tmp___0~1_5 0)) InVars {ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_5} OutVars{~c_dr_st~0=v_~c_dr_st~0_11, ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_1, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_5} AuxVars[] AssignedVars[~c_dr_st~0, ULTIMATE.start_do_read_c_~a~0] 992#L139 [483] L139-->L142: Formula: (< 0 v_~c_dr_pc~0_6) InVars {~c_dr_pc~0=v_~c_dr_pc~0_6} OutVars{~c_dr_pc~0=v_~c_dr_pc~0_6} AuxVars[] AssignedVars[] 1008#L142 [526] L142-->L152-1: Formula: (and (= v_~c_dr_pc~0_15 1) (= v_ULTIMATE.start_do_read_c_~a~0_6 v_~a_t~0_6)) InVars {~c_dr_pc~0=v_~c_dr_pc~0_15, ~a_t~0=v_~a_t~0_6} OutVars{ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_6, ~c_dr_pc~0=v_~c_dr_pc~0_15, ~a_t~0=v_~a_t~0_6} AuxVars[] AssignedVars[ULTIMATE.start_do_read_c_~a~0] 1010#L152-1 [412] L152-1-->L32-3: Formula: (and (= v_~c_num_read~0_3 (+ v_~c_num_read~0_4 1)) (= v_~q_read_ev~0_5 1) (= v_ULTIMATE.start_do_read_c_~a~0_5 v_~q_buf_0~0_3) (= v_~c_last_read~0_2 v_ULTIMATE.start_do_read_c_~a~0_5) (= v_~q_free~0_8 1)) InVars {~c_num_read~0=v_~c_num_read~0_4, ~q_buf_0~0=v_~q_buf_0~0_3} OutVars{~c_num_read~0=v_~c_num_read~0_3, ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_6, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_6, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_4|, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_4|, ~c_last_read~0=v_~c_last_read~0_2, ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_5, ~q_free~0=v_~q_free~0_8, ~q_buf_0~0=v_~q_buf_0~0_3, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_4|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_6, ~q_read_ev~0=v_~q_read_ev~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0, ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret1, ~c_last_read~0, ULTIMATE.start_do_read_c_~a~0, ~c_num_read~0, ~q_free~0, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0, ~q_read_ev~0] 1037#L32-3 [396] L32-3-->L33-1: Formula: (= v_~p_dw_pc~0_10 1) InVars {~p_dw_pc~0=v_~p_dw_pc~0_10} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_10} AuxVars[] AssignedVars[] 1020#L33-1 [346] L33-1-->L43-1: Formula: (and (= 1 v_~q_read_ev~0_6) (= v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_8 1)) InVars {~q_read_ev~0=v_~q_read_ev~0_6} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_8, ~q_read_ev~0=v_~q_read_ev~0_6} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0] 994#L43-1 [531] L43-1-->L74-3: Formula: (and (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_8| v_ULTIMATE.start_immediate_notify_threads_~tmp~0_12) (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_8| v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_12)) InVars {ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_12} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_12, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_8|, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_8|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_12} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 995#L74-3 [503] L74-3-->L74-5: Formula: (and (> v_ULTIMATE.start_immediate_notify_threads_~tmp~0_9 0) (= v_~p_dw_st~0_13 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_9} OutVars{~p_dw_st~0=v_~p_dw_st~0_13, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_9} AuxVars[] AssignedVars[~p_dw_st~0] 1015#L74-5 [332] L74-5-->L51-3: Formula: true InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_4|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_7} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_#res, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 1050#L51-3 [507] L51-3-->L51-5: Formula: (> v_~c_dr_pc~0_11 1) InVars {~c_dr_pc~0=v_~c_dr_pc~0_11} OutVars{~c_dr_pc~0=v_~c_dr_pc~0_11} AuxVars[] AssignedVars[] 1011#L51-5 [327] L51-5-->L62-1: Formula: (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 986#L62-1 [533] L62-1-->L82-3: Formula: (and (= v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_12 |v_ULTIMATE.start_is_do_read_c_triggered_#res_8|) (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_14 |v_ULTIMATE.start_is_do_read_c_triggered_#res_8|)) InVars {ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_14} OutVars{ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_12, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_8|, ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_8|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_14} AuxVars[] AssignedVars[ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_immediate_notify_threads_#t~ret1, ULTIMATE.start_is_do_read_c_triggered_#res] 987#L82-3 [513] L82-3-->L82-5: Formula: (and (< v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_9 0) (= v_~c_dr_st~0_13 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_9} OutVars{~c_dr_st~0=v_~c_dr_st~0_13, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_9} AuxVars[] AssignedVars[~c_dr_st~0] 1024#L82-5 [536] L82-5-->L10-2: Formula: (and (= v_~p_num_write~0_10 v_~c_num_read~0_10) (= 2 v_~q_read_ev~0_13) (= v_~c_last_read~0_8 v_~p_last_write~0_8)) InVars {~p_last_write~0=v_~p_last_write~0_8, ~c_last_read~0=v_~c_last_read~0_8, ~c_num_read~0=v_~c_num_read~0_10, ~p_num_write~0=v_~p_num_write~0_10} OutVars{~p_last_write~0=v_~p_last_write~0_8, ~c_last_read~0=v_~c_last_read~0_8, ~c_num_read~0=v_~c_num_read~0_10, ~p_num_write~0=v_~p_num_write~0_10, ~q_read_ev~0=v_~q_read_ev~0_13} AuxVars[] AssignedVars[~q_read_ev~0] 1031#L10-2 [400] L10-2-->L151: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 1028#L151 [380] L151-->L262: Formula: (and (= v_~c_dr_st~0_12 2) (= v_~c_dr_pc~0_9 1) (= v_~a_t~0_2 v_ULTIMATE.start_do_read_c_~a~0_3) (= v_~q_free~0_6 1)) InVars {ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_3, ~q_free~0=v_~q_free~0_6} OutVars{ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_3, ~c_dr_pc~0=v_~c_dr_pc~0_9, ~c_dr_st~0=v_~c_dr_st~0_12, ~q_free~0=v_~q_free~0_6, ~a_t~0=v_~a_t~0_2} AuxVars[] AssignedVars[~c_dr_pc~0, ~c_dr_st~0, ~a_t~0] 1030#L262 37.10/18.54 [2019-03-28 12:18:36,913 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.54 [2019-03-28 12:18:36,913 INFO L82 PathProgramCache]: Analyzing trace with hash 16829863, now seen corresponding path program 2 times 37.10/18.54 [2019-03-28 12:18:36,914 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.54 [2019-03-28 12:18:36,914 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.54 [2019-03-28 12:18:36,915 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:36,915 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:36,915 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:36,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 37.10/18.54 [2019-03-28 12:18:36,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 37.10/18.54 [2019-03-28 12:18:36,925 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.54 [2019-03-28 12:18:36,925 INFO L82 PathProgramCache]: Analyzing trace with hash 1910882430, now seen corresponding path program 1 times 37.10/18.54 [2019-03-28 12:18:36,926 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.54 [2019-03-28 12:18:36,926 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.54 [2019-03-28 12:18:36,926 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:36,927 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:36,927 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:36,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 37.10/18.54 [2019-03-28 12:18:36,939 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 37.10/18.54 [2019-03-28 12:18:36,939 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 37.10/18.54 [2019-03-28 12:18:36,940 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 37.10/18.54 [2019-03-28 12:18:36,940 INFO L811 eck$LassoCheckResult]: loop already infeasible 37.10/18.54 [2019-03-28 12:18:36,940 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 37.10/18.54 [2019-03-28 12:18:36,940 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 37.10/18.54 [2019-03-28 12:18:36,941 INFO L87 Difference]: Start difference. First operand 75 states and 142 transitions. cyclomatic complexity: 68 Second operand 3 states. 37.10/18.54 [2019-03-28 12:18:37,073 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 37.10/18.54 [2019-03-28 12:18:37,073 INFO L93 Difference]: Finished difference Result 90 states and 169 transitions. 37.10/18.54 [2019-03-28 12:18:37,073 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 37.10/18.54 [2019-03-28 12:18:37,074 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 90 states and 169 transitions. 37.10/18.54 [2019-03-28 12:18:37,075 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 86 37.10/18.54 [2019-03-28 12:18:37,076 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 90 states to 90 states and 169 transitions. 37.10/18.54 [2019-03-28 12:18:37,076 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 90 37.10/18.54 [2019-03-28 12:18:37,076 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 90 37.10/18.54 [2019-03-28 12:18:37,077 INFO L73 IsDeterministic]: Start isDeterministic. Operand 90 states and 169 transitions. 37.10/18.54 [2019-03-28 12:18:37,077 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 37.10/18.54 [2019-03-28 12:18:37,077 INFO L706 BuchiCegarLoop]: Abstraction has 90 states and 169 transitions. 37.10/18.54 [2019-03-28 12:18:37,077 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90 states and 169 transitions. 37.10/18.54 [2019-03-28 12:18:37,081 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90 to 75. 37.10/18.54 [2019-03-28 12:18:37,081 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 75 states. 37.10/18.54 [2019-03-28 12:18:37,082 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75 states to 75 states and 140 transitions. 37.10/18.54 [2019-03-28 12:18:37,082 INFO L729 BuchiCegarLoop]: Abstraction has 75 states and 140 transitions. 37.10/18.54 [2019-03-28 12:18:37,082 INFO L609 BuchiCegarLoop]: Abstraction has 75 states and 140 transitions. 37.10/18.54 [2019-03-28 12:18:37,083 INFO L442 BuchiCegarLoop]: ======== Iteration 8============ 37.10/18.54 [2019-03-28 12:18:37,083 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 75 states and 140 transitions. 37.10/18.54 [2019-03-28 12:18:37,083 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 37.10/18.54 [2019-03-28 12:18:37,083 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 37.10/18.54 [2019-03-28 12:18:37,084 INFO L119 BuchiIsEmpty]: Starting construction of run 37.10/18.54 [2019-03-28 12:18:37,084 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1] 37.10/18.54 [2019-03-28 12:18:37,084 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 37.10/18.54 [2019-03-28 12:18:37,085 INFO L794 eck$LassoCheckResult]: Stem: 1187#ULTIMATE.startENTRY [520] ULTIMATE.startENTRY-->L196: Formula: (and (= v_~q_write_ev~0_11 v_~q_read_ev~0_11) (= 1 v_~c_dr_i~0_7) (= v_~q_free~0_11 1) (= v_~q_buf_0~0_5 0) (= v_~q_write_ev~0_11 2) (= 0 v_~p_last_write~0_6) (= 0 v_~c_last_read~0_6) (= v_~p_dw_pc~0_14 0) (= 0 v_~a_t~0_5) (= 0 v_~c_dr_st~0_15) (= v_~c_dr_pc~0_14 0) (= 0 v_~c_num_read~0_9) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 0) (= 0 v_~p_num_write~0_9) (= v_~p_dw_i~0_7 1) (= v_~p_dw_st~0_15 0)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ~p_last_write~0=v_~p_last_write~0_6, ~c_dr_pc~0=v_~c_dr_pc~0_14, ~c_dr_st~0=v_~c_dr_st~0_15, ~c_num_read~0=v_~c_num_read~0_9, ~p_num_write~0=v_~p_num_write~0_9, ~c_dr_i~0=v_~c_dr_i~0_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7, ~q_write_ev~0=v_~q_write_ev~0_11, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~p_dw_st~0=v_~p_dw_st~0_15, ~p_dw_i~0=v_~p_dw_i~0_7, ~c_last_read~0=v_~c_last_read~0_6, ~p_dw_pc~0=v_~p_dw_pc~0_14, ~q_free~0=v_~q_free~0_11, ~q_buf_0~0=v_~q_buf_0~0_5, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6, ~q_read_ev~0=v_~q_read_ev~0_11, ~a_t~0=v_~a_t~0_5} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ~p_last_write~0, ~c_dr_pc~0, ~c_dr_st~0, ~c_num_read~0, ~p_num_write~0, ~c_dr_i~0, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_~kernel_st~0, ~q_write_ev~0, ULTIMATE.start_main_#res, ~p_dw_st~0, ~p_dw_i~0, ~c_last_read~0, ~p_dw_pc~0, ~q_free~0, ~q_buf_0~0, ULTIMATE.start_main_~__retres1~3, ~q_read_ev~0, ~a_t~0] 1188#L196 [418] L196-->L196-2: Formula: (and (= v_~p_dw_i~0_3 1) (= v_~p_dw_st~0_2 0)) InVars {~p_dw_i~0=v_~p_dw_i~0_3} OutVars{~p_dw_st~0=v_~p_dw_st~0_2, ~p_dw_i~0=v_~p_dw_i~0_3} AuxVars[] AssignedVars[~p_dw_st~0] 1210#L196-2 [413] L196-2-->L313-1: Formula: (and (= 1 v_~c_dr_i~0_3) (= v_~c_dr_st~0_3 0)) InVars {~c_dr_i~0=v_~c_dr_i~0_3} OutVars{~c_dr_st~0=v_~c_dr_st~0_3, ~c_dr_i~0=v_~c_dr_i~0_3} AuxVars[] AssignedVars[~c_dr_st~0] 1211#L313-1 [521] L313-1-->L262: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_8 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_8, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_4|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_6, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_6, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp~1, ULTIMATE.start_eval_~tmp___0~1, ULTIMATE.start_eval_~tmp___1~0] 1214#L262 37.10/18.54 [2019-03-28 12:18:37,086 INFO L796 eck$LassoCheckResult]: Loop: 1214#L262 [522] L262-->L214: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 1207#L214 [406] L214-->L226: Formula: (and (= v_~p_dw_st~0_6 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11 1)) InVars {~p_dw_st~0=v_~p_dw_st~0_6} OutVars{~p_dw_st~0=v_~p_dw_st~0_6, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 1208#L226 [523] L226-->L242: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___1~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_5|, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp___1~0] 1215#L242 [468] L242-->L242-1: Formula: (> v_ULTIMATE.start_eval_~tmp___1~0_4 0) InVars {ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} OutVars{ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} AuxVars[] AssignedVars[] 1212#L242-1 [333] L242-1-->L251: Formula: (and (= v_ULTIMATE.start_eval_~tmp~1_3 |v_ULTIMATE.start_eval_#t~nondet4_3|) (= v_~p_dw_st~0_8 0)) InVars {ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_3|, ~p_dw_st~0=v_~p_dw_st~0_8} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_2|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_3, ~p_dw_st~0=v_~p_dw_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_~tmp~1] 1200#L251 [471] L251-->L96: Formula: (and (= v_~p_dw_st~0_9 1) (< v_ULTIMATE.start_eval_~tmp~1_4 0)) InVars {ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_4} OutVars{ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_4, ~p_dw_st~0=v_~p_dw_st~0_9, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_1|} AuxVars[] AssignedVars[~p_dw_st~0, ULTIMATE.start_do_write_p_#t~nondet2] 1196#L96 [378] L96-->L107-1: Formula: (= v_~p_dw_pc~0_3 0) InVars {~p_dw_pc~0=v_~p_dw_pc~0_3} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_3} AuxVars[] AssignedVars[] 1192#L107-1 [375] L107-1-->L108: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 1195#L108 [408] L108-->L247: Formula: (and (= v_~q_free~0_3 0) (= v_~p_dw_pc~0_7 1) (= v_~p_dw_st~0_10 2)) InVars {~q_free~0=v_~q_free~0_3} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_7, ~q_free~0=v_~q_free~0_3, ~p_dw_st~0=v_~p_dw_st~0_10} AuxVars[] AssignedVars[~p_dw_st~0, ~p_dw_pc~0] 1184#L247 [410] L247-->L266: Formula: (and (= 0 v_~c_dr_st~0_10) (= v_ULTIMATE.start_eval_~tmp___0~1_4 |v_ULTIMATE.start_eval_#t~nondet5_3|)) InVars {~c_dr_st~0=v_~c_dr_st~0_10, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_3|} OutVars{~c_dr_st~0=v_~c_dr_st~0_10, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_4, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_2|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp___0~1] 1162#L266 [480] L266-->L139: Formula: (and (= v_~c_dr_st~0_11 1) (> v_ULTIMATE.start_eval_~tmp___0~1_5 0)) InVars {ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_5} OutVars{~c_dr_st~0=v_~c_dr_st~0_11, ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_1, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_5} AuxVars[] AssignedVars[~c_dr_st~0, ULTIMATE.start_do_read_c_~a~0] 1163#L139 [483] L139-->L142: Formula: (< 0 v_~c_dr_pc~0_6) InVars {~c_dr_pc~0=v_~c_dr_pc~0_6} OutVars{~c_dr_pc~0=v_~c_dr_pc~0_6} AuxVars[] AssignedVars[] 1179#L142 [526] L142-->L152-1: Formula: (and (= v_~c_dr_pc~0_15 1) (= v_ULTIMATE.start_do_read_c_~a~0_6 v_~a_t~0_6)) InVars {~c_dr_pc~0=v_~c_dr_pc~0_15, ~a_t~0=v_~a_t~0_6} OutVars{ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_6, ~c_dr_pc~0=v_~c_dr_pc~0_15, ~a_t~0=v_~a_t~0_6} AuxVars[] AssignedVars[ULTIMATE.start_do_read_c_~a~0] 1181#L152-1 [412] L152-1-->L32-3: Formula: (and (= v_~c_num_read~0_3 (+ v_~c_num_read~0_4 1)) (= v_~q_read_ev~0_5 1) (= v_ULTIMATE.start_do_read_c_~a~0_5 v_~q_buf_0~0_3) (= v_~c_last_read~0_2 v_ULTIMATE.start_do_read_c_~a~0_5) (= v_~q_free~0_8 1)) InVars {~c_num_read~0=v_~c_num_read~0_4, ~q_buf_0~0=v_~q_buf_0~0_3} OutVars{~c_num_read~0=v_~c_num_read~0_3, ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_6, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_6, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_4|, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_4|, ~c_last_read~0=v_~c_last_read~0_2, ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_5, ~q_free~0=v_~q_free~0_8, ~q_buf_0~0=v_~q_buf_0~0_3, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_4|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_6, ~q_read_ev~0=v_~q_read_ev~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0, ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret1, ~c_last_read~0, ULTIMATE.start_do_read_c_~a~0, ~c_num_read~0, ~q_free~0, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0, ~q_read_ev~0] 1226#L32-3 [396] L32-3-->L33-1: Formula: (= v_~p_dw_pc~0_10 1) InVars {~p_dw_pc~0=v_~p_dw_pc~0_10} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_10} AuxVars[] AssignedVars[] 1189#L33-1 [346] L33-1-->L43-1: Formula: (and (= 1 v_~q_read_ev~0_6) (= v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_8 1)) InVars {~q_read_ev~0=v_~q_read_ev~0_6} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_8, ~q_read_ev~0=v_~q_read_ev~0_6} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0] 1165#L43-1 [531] L43-1-->L74-3: Formula: (and (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_8| v_ULTIMATE.start_immediate_notify_threads_~tmp~0_12) (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_8| v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_12)) InVars {ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_12} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_12, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_8|, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_8|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_12} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 1166#L74-3 [503] L74-3-->L74-5: Formula: (and (> v_ULTIMATE.start_immediate_notify_threads_~tmp~0_9 0) (= v_~p_dw_st~0_13 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_9} OutVars{~p_dw_st~0=v_~p_dw_st~0_13, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_9} AuxVars[] AssignedVars[~p_dw_st~0] 1185#L74-5 [332] L74-5-->L51-3: Formula: true InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_4|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_7} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_#res, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 1223#L51-3 [305] L51-3-->L52-1: Formula: (= v_~c_dr_pc~0_10 1) InVars {~c_dr_pc~0=v_~c_dr_pc~0_10} OutVars{~c_dr_pc~0=v_~c_dr_pc~0_10} AuxVars[] AssignedVars[] 1221#L52-1 [340] L52-1-->L62-1: Formula: (and (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_10 1) (= v_~q_write_ev~0_7 1)) InVars {~q_write_ev~0=v_~q_write_ev~0_7} OutVars{~q_write_ev~0=v_~q_write_ev~0_7, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_10} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 1220#L62-1 [533] L62-1-->L82-3: Formula: (and (= v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_12 |v_ULTIMATE.start_is_do_read_c_triggered_#res_8|) (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_14 |v_ULTIMATE.start_is_do_read_c_triggered_#res_8|)) InVars {ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_14} OutVars{ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_12, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_8|, ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_8|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_14} AuxVars[] AssignedVars[ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_immediate_notify_threads_#t~ret1, ULTIMATE.start_is_do_read_c_triggered_#res] 1219#L82-3 [513] L82-3-->L82-5: Formula: (and (< v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_9 0) (= v_~c_dr_st~0_13 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_9} OutVars{~c_dr_st~0=v_~c_dr_st~0_13, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_9} AuxVars[] AssignedVars[~c_dr_st~0] 1218#L82-5 [536] L82-5-->L10-2: Formula: (and (= v_~p_num_write~0_10 v_~c_num_read~0_10) (= 2 v_~q_read_ev~0_13) (= v_~c_last_read~0_8 v_~p_last_write~0_8)) InVars {~p_last_write~0=v_~p_last_write~0_8, ~c_last_read~0=v_~c_last_read~0_8, ~c_num_read~0=v_~c_num_read~0_10, ~p_num_write~0=v_~p_num_write~0_10} OutVars{~p_last_write~0=v_~p_last_write~0_8, ~c_last_read~0=v_~c_last_read~0_8, ~c_num_read~0=v_~c_num_read~0_10, ~p_num_write~0=v_~p_num_write~0_10, ~q_read_ev~0=v_~q_read_ev~0_13} AuxVars[] AssignedVars[~q_read_ev~0] 1217#L10-2 [400] L10-2-->L151: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 1216#L151 [380] L151-->L262: Formula: (and (= v_~c_dr_st~0_12 2) (= v_~c_dr_pc~0_9 1) (= v_~a_t~0_2 v_ULTIMATE.start_do_read_c_~a~0_3) (= v_~q_free~0_6 1)) InVars {ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_3, ~q_free~0=v_~q_free~0_6} OutVars{ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_3, ~c_dr_pc~0=v_~c_dr_pc~0_9, ~c_dr_st~0=v_~c_dr_st~0_12, ~q_free~0=v_~q_free~0_6, ~a_t~0=v_~a_t~0_2} AuxVars[] AssignedVars[~c_dr_pc~0, ~c_dr_st~0, ~a_t~0] 1214#L262 37.10/18.54 [2019-03-28 12:18:37,086 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.54 [2019-03-28 12:18:37,086 INFO L82 PathProgramCache]: Analyzing trace with hash 16829863, now seen corresponding path program 3 times 37.10/18.54 [2019-03-28 12:18:37,086 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.54 [2019-03-28 12:18:37,086 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.54 [2019-03-28 12:18:37,087 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:37,087 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:37,088 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:37,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 37.10/18.54 [2019-03-28 12:18:37,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 37.10/18.54 [2019-03-28 12:18:37,097 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.54 [2019-03-28 12:18:37,097 INFO L82 PathProgramCache]: Analyzing trace with hash -1091903989, now seen corresponding path program 1 times 37.10/18.54 [2019-03-28 12:18:37,098 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.54 [2019-03-28 12:18:37,098 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.54 [2019-03-28 12:18:37,099 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:37,099 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:37,099 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:37,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 37.10/18.54 [2019-03-28 12:18:37,129 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 37.10/18.54 [2019-03-28 12:18:37,130 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 37.10/18.54 [2019-03-28 12:18:37,130 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 37.10/18.54 [2019-03-28 12:18:37,130 INFO L811 eck$LassoCheckResult]: loop already infeasible 37.10/18.54 [2019-03-28 12:18:37,131 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. 37.10/18.54 [2019-03-28 12:18:37,131 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 37.10/18.54 [2019-03-28 12:18:37,131 INFO L87 Difference]: Start difference. First operand 75 states and 140 transitions. cyclomatic complexity: 66 Second operand 4 states. 37.10/18.54 [2019-03-28 12:18:37,355 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 37.10/18.54 [2019-03-28 12:18:37,356 INFO L93 Difference]: Finished difference Result 175 states and 312 transitions. 37.10/18.54 [2019-03-28 12:18:37,356 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. 37.10/18.54 [2019-03-28 12:18:37,356 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 175 states and 312 transitions. 37.10/18.54 [2019-03-28 12:18:37,358 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 171 37.10/18.54 [2019-03-28 12:18:37,360 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 175 states to 175 states and 312 transitions. 37.10/18.54 [2019-03-28 12:18:37,360 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 175 37.10/18.54 [2019-03-28 12:18:37,360 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 175 37.10/18.54 [2019-03-28 12:18:37,360 INFO L73 IsDeterministic]: Start isDeterministic. Operand 175 states and 312 transitions. 37.10/18.54 [2019-03-28 12:18:37,361 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 37.10/18.54 [2019-03-28 12:18:37,361 INFO L706 BuchiCegarLoop]: Abstraction has 175 states and 312 transitions. 37.10/18.54 [2019-03-28 12:18:37,361 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 175 states and 312 transitions. 37.10/18.54 [2019-03-28 12:18:37,365 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 175 to 81. 37.10/18.54 [2019-03-28 12:18:37,366 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 81 states. 37.10/18.54 [2019-03-28 12:18:37,366 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81 states to 81 states and 146 transitions. 37.10/18.54 [2019-03-28 12:18:37,366 INFO L729 BuchiCegarLoop]: Abstraction has 81 states and 146 transitions. 37.10/18.54 [2019-03-28 12:18:37,367 INFO L609 BuchiCegarLoop]: Abstraction has 81 states and 146 transitions. 37.10/18.54 [2019-03-28 12:18:37,367 INFO L442 BuchiCegarLoop]: ======== Iteration 9============ 37.10/18.54 [2019-03-28 12:18:37,367 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 81 states and 146 transitions. 37.10/18.54 [2019-03-28 12:18:37,367 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 77 37.10/18.54 [2019-03-28 12:18:37,368 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 37.10/18.54 [2019-03-28 12:18:37,368 INFO L119 BuchiIsEmpty]: Starting construction of run 37.10/18.54 [2019-03-28 12:18:37,368 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1] 37.10/18.54 [2019-03-28 12:18:37,368 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 37.10/18.54 [2019-03-28 12:18:37,369 INFO L794 eck$LassoCheckResult]: Stem: 1454#ULTIMATE.startENTRY [520] ULTIMATE.startENTRY-->L196: Formula: (and (= v_~q_write_ev~0_11 v_~q_read_ev~0_11) (= 1 v_~c_dr_i~0_7) (= v_~q_free~0_11 1) (= v_~q_buf_0~0_5 0) (= v_~q_write_ev~0_11 2) (= 0 v_~p_last_write~0_6) (= 0 v_~c_last_read~0_6) (= v_~p_dw_pc~0_14 0) (= 0 v_~a_t~0_5) (= 0 v_~c_dr_st~0_15) (= v_~c_dr_pc~0_14 0) (= 0 v_~c_num_read~0_9) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 0) (= 0 v_~p_num_write~0_9) (= v_~p_dw_i~0_7 1) (= v_~p_dw_st~0_15 0)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ~p_last_write~0=v_~p_last_write~0_6, ~c_dr_pc~0=v_~c_dr_pc~0_14, ~c_dr_st~0=v_~c_dr_st~0_15, ~c_num_read~0=v_~c_num_read~0_9, ~p_num_write~0=v_~p_num_write~0_9, ~c_dr_i~0=v_~c_dr_i~0_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7, ~q_write_ev~0=v_~q_write_ev~0_11, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~p_dw_st~0=v_~p_dw_st~0_15, ~p_dw_i~0=v_~p_dw_i~0_7, ~c_last_read~0=v_~c_last_read~0_6, ~p_dw_pc~0=v_~p_dw_pc~0_14, ~q_free~0=v_~q_free~0_11, ~q_buf_0~0=v_~q_buf_0~0_5, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6, ~q_read_ev~0=v_~q_read_ev~0_11, ~a_t~0=v_~a_t~0_5} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ~p_last_write~0, ~c_dr_pc~0, ~c_dr_st~0, ~c_num_read~0, ~p_num_write~0, ~c_dr_i~0, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_~kernel_st~0, ~q_write_ev~0, ULTIMATE.start_main_#res, ~p_dw_st~0, ~p_dw_i~0, ~c_last_read~0, ~p_dw_pc~0, ~q_free~0, ~q_buf_0~0, ULTIMATE.start_main_~__retres1~3, ~q_read_ev~0, ~a_t~0] 1455#L196 [418] L196-->L196-2: Formula: (and (= v_~p_dw_i~0_3 1) (= v_~p_dw_st~0_2 0)) InVars {~p_dw_i~0=v_~p_dw_i~0_3} OutVars{~p_dw_st~0=v_~p_dw_st~0_2, ~p_dw_i~0=v_~p_dw_i~0_3} AuxVars[] AssignedVars[~p_dw_st~0] 1476#L196-2 [413] L196-2-->L313-1: Formula: (and (= 1 v_~c_dr_i~0_3) (= v_~c_dr_st~0_3 0)) InVars {~c_dr_i~0=v_~c_dr_i~0_3} OutVars{~c_dr_st~0=v_~c_dr_st~0_3, ~c_dr_i~0=v_~c_dr_i~0_3} AuxVars[] AssignedVars[~c_dr_st~0] 1470#L313-1 [521] L313-1-->L262: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_8 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_8, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_4|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_6, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_6, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp~1, ULTIMATE.start_eval_~tmp___0~1, ULTIMATE.start_eval_~tmp___1~0] 1465#L262 37.10/18.54 [2019-03-28 12:18:37,370 INFO L796 eck$LassoCheckResult]: Loop: 1465#L262 [522] L262-->L214: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 1472#L214 [406] L214-->L226: Formula: (and (= v_~p_dw_st~0_6 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11 1)) InVars {~p_dw_st~0=v_~p_dw_st~0_6} OutVars{~p_dw_st~0=v_~p_dw_st~0_6, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 1436#L226 [523] L226-->L242: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___1~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_5|, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp___1~0] 1437#L242 [468] L242-->L242-1: Formula: (> v_ULTIMATE.start_eval_~tmp___1~0_4 0) InVars {ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} OutVars{ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} AuxVars[] AssignedVars[] 1448#L242-1 [333] L242-1-->L251: Formula: (and (= v_ULTIMATE.start_eval_~tmp~1_3 |v_ULTIMATE.start_eval_#t~nondet4_3|) (= v_~p_dw_st~0_8 0)) InVars {ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_3|, ~p_dw_st~0=v_~p_dw_st~0_8} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_2|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_3, ~p_dw_st~0=v_~p_dw_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_~tmp~1] 1471#L251 [471] L251-->L96: Formula: (and (= v_~p_dw_st~0_9 1) (< v_ULTIMATE.start_eval_~tmp~1_4 0)) InVars {ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_4} OutVars{ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_4, ~p_dw_st~0=v_~p_dw_st~0_9, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_1|} AuxVars[] AssignedVars[~p_dw_st~0, ULTIMATE.start_do_write_p_#t~nondet2] 1462#L96 [378] L96-->L107-1: Formula: (= v_~p_dw_pc~0_3 0) InVars {~p_dw_pc~0=v_~p_dw_pc~0_3} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_3} AuxVars[] AssignedVars[] 1457#L107-1 [375] L107-1-->L108: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 1461#L108 [408] L108-->L247: Formula: (and (= v_~q_free~0_3 0) (= v_~p_dw_pc~0_7 1) (= v_~p_dw_st~0_10 2)) InVars {~q_free~0=v_~q_free~0_3} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_7, ~q_free~0=v_~q_free~0_3, ~p_dw_st~0=v_~p_dw_st~0_10} AuxVars[] AssignedVars[~p_dw_st~0, ~p_dw_pc~0] 1446#L247 [410] L247-->L266: Formula: (and (= 0 v_~c_dr_st~0_10) (= v_ULTIMATE.start_eval_~tmp___0~1_4 |v_ULTIMATE.start_eval_#t~nondet5_3|)) InVars {~c_dr_st~0=v_~c_dr_st~0_10, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_3|} OutVars{~c_dr_st~0=v_~c_dr_st~0_10, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_4, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_2|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp___0~1] 1422#L266 [480] L266-->L139: Formula: (and (= v_~c_dr_st~0_11 1) (> v_ULTIMATE.start_eval_~tmp___0~1_5 0)) InVars {ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_5} OutVars{~c_dr_st~0=v_~c_dr_st~0_11, ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_1, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_5} AuxVars[] AssignedVars[~c_dr_st~0, ULTIMATE.start_do_read_c_~a~0] 1423#L139 [483] L139-->L142: Formula: (< 0 v_~c_dr_pc~0_6) InVars {~c_dr_pc~0=v_~c_dr_pc~0_6} OutVars{~c_dr_pc~0=v_~c_dr_pc~0_6} AuxVars[] AssignedVars[] 1441#L142 [526] L142-->L152-1: Formula: (and (= v_~c_dr_pc~0_15 1) (= v_ULTIMATE.start_do_read_c_~a~0_6 v_~a_t~0_6)) InVars {~c_dr_pc~0=v_~c_dr_pc~0_15, ~a_t~0=v_~a_t~0_6} OutVars{ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_6, ~c_dr_pc~0=v_~c_dr_pc~0_15, ~a_t~0=v_~a_t~0_6} AuxVars[] AssignedVars[ULTIMATE.start_do_read_c_~a~0] 1443#L152-1 [412] L152-1-->L32-3: Formula: (and (= v_~c_num_read~0_3 (+ v_~c_num_read~0_4 1)) (= v_~q_read_ev~0_5 1) (= v_ULTIMATE.start_do_read_c_~a~0_5 v_~q_buf_0~0_3) (= v_~c_last_read~0_2 v_ULTIMATE.start_do_read_c_~a~0_5) (= v_~q_free~0_8 1)) InVars {~c_num_read~0=v_~c_num_read~0_4, ~q_buf_0~0=v_~q_buf_0~0_3} OutVars{~c_num_read~0=v_~c_num_read~0_3, ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_6, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_6, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_4|, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_4|, ~c_last_read~0=v_~c_last_read~0_2, ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_5, ~q_free~0=v_~q_free~0_8, ~q_buf_0~0=v_~q_buf_0~0_3, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_4|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_6, ~q_read_ev~0=v_~q_read_ev~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0, ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret1, ~c_last_read~0, ULTIMATE.start_do_read_c_~a~0, ~c_num_read~0, ~q_free~0, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0, ~q_read_ev~0] 1473#L32-3 [396] L32-3-->L33-1: Formula: (= v_~p_dw_pc~0_10 1) InVars {~p_dw_pc~0=v_~p_dw_pc~0_10} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_10} AuxVars[] AssignedVars[] 1452#L33-1 [346] L33-1-->L43-1: Formula: (and (= 1 v_~q_read_ev~0_6) (= v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_8 1)) InVars {~q_read_ev~0=v_~q_read_ev~0_6} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_8, ~q_read_ev~0=v_~q_read_ev~0_6} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0] 1425#L43-1 [531] L43-1-->L74-3: Formula: (and (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_8| v_ULTIMATE.start_immediate_notify_threads_~tmp~0_12) (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_8| v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_12)) InVars {ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_12} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_12, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_8|, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_8|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_12} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 1426#L74-3 [503] L74-3-->L74-5: Formula: (and (> v_ULTIMATE.start_immediate_notify_threads_~tmp~0_9 0) (= v_~p_dw_st~0_13 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_9} OutVars{~p_dw_st~0=v_~p_dw_st~0_13, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_9} AuxVars[] AssignedVars[~p_dw_st~0] 1447#L74-5 [332] L74-5-->L51-3: Formula: true InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_4|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_7} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_#res, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 1485#L51-3 [305] L51-3-->L52-1: Formula: (= v_~c_dr_pc~0_10 1) InVars {~c_dr_pc~0=v_~c_dr_pc~0_10} OutVars{~c_dr_pc~0=v_~c_dr_pc~0_10} AuxVars[] AssignedVars[] 1450#L52-1 [340] L52-1-->L62-1: Formula: (and (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_10 1) (= v_~q_write_ev~0_7 1)) InVars {~q_write_ev~0=v_~q_write_ev~0_7} OutVars{~q_write_ev~0=v_~q_write_ev~0_7, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_10} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 1417#L62-1 [533] L62-1-->L82-3: Formula: (and (= v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_12 |v_ULTIMATE.start_is_do_read_c_triggered_#res_8|) (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_14 |v_ULTIMATE.start_is_do_read_c_triggered_#res_8|)) InVars {ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_14} OutVars{ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_12, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_8|, ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_8|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_14} AuxVars[] AssignedVars[ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_immediate_notify_threads_#t~ret1, ULTIMATE.start_is_do_read_c_triggered_#res] 1418#L82-3 [514] L82-3-->L82-5: Formula: (and (> v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_9 0) (= v_~c_dr_st~0_13 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_9} OutVars{~c_dr_st~0=v_~c_dr_st~0_13, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_9} AuxVars[] AssignedVars[~c_dr_st~0] 1458#L82-5 [536] L82-5-->L10-2: Formula: (and (= v_~p_num_write~0_10 v_~c_num_read~0_10) (= 2 v_~q_read_ev~0_13) (= v_~c_last_read~0_8 v_~p_last_write~0_8)) InVars {~p_last_write~0=v_~p_last_write~0_8, ~c_last_read~0=v_~c_last_read~0_8, ~c_num_read~0=v_~c_num_read~0_10, ~p_num_write~0=v_~p_num_write~0_10} OutVars{~p_last_write~0=v_~p_last_write~0_8, ~c_last_read~0=v_~c_last_read~0_8, ~c_num_read~0=v_~c_num_read~0_10, ~p_num_write~0=v_~p_num_write~0_10, ~q_read_ev~0=v_~q_read_ev~0_13} AuxVars[] AssignedVars[~q_read_ev~0] 1466#L10-2 [400] L10-2-->L151: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 1463#L151 [380] L151-->L262: Formula: (and (= v_~c_dr_st~0_12 2) (= v_~c_dr_pc~0_9 1) (= v_~a_t~0_2 v_ULTIMATE.start_do_read_c_~a~0_3) (= v_~q_free~0_6 1)) InVars {ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_3, ~q_free~0=v_~q_free~0_6} OutVars{ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_3, ~c_dr_pc~0=v_~c_dr_pc~0_9, ~c_dr_st~0=v_~c_dr_st~0_12, ~q_free~0=v_~q_free~0_6, ~a_t~0=v_~a_t~0_2} AuxVars[] AssignedVars[~c_dr_pc~0, ~c_dr_st~0, ~a_t~0] 1465#L262 37.10/18.54 [2019-03-28 12:18:37,370 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.54 [2019-03-28 12:18:37,370 INFO L82 PathProgramCache]: Analyzing trace with hash 16829863, now seen corresponding path program 4 times 37.10/18.54 [2019-03-28 12:18:37,370 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.54 [2019-03-28 12:18:37,370 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.54 [2019-03-28 12:18:37,371 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:37,372 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:37,372 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:37,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 37.10/18.54 [2019-03-28 12:18:37,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 37.10/18.54 [2019-03-28 12:18:37,381 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.54 [2019-03-28 12:18:37,381 INFO L82 PathProgramCache]: Analyzing trace with hash -1091874198, now seen corresponding path program 1 times 37.10/18.54 [2019-03-28 12:18:37,381 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.54 [2019-03-28 12:18:37,381 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.54 [2019-03-28 12:18:37,382 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:37,382 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:37,382 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:37,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 37.10/18.54 [2019-03-28 12:18:37,397 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 37.10/18.54 [2019-03-28 12:18:37,403 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.54 [2019-03-28 12:18:37,403 INFO L82 PathProgramCache]: Analyzing trace with hash -1796817776, now seen corresponding path program 1 times 37.10/18.54 [2019-03-28 12:18:37,403 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.54 [2019-03-28 12:18:37,403 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.54 [2019-03-28 12:18:37,404 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:37,404 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:37,405 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:37,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 37.10/18.54 [2019-03-28 12:18:37,429 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 37.10/18.54 [2019-03-28 12:18:37,429 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 37.10/18.54 [2019-03-28 12:18:37,430 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 37.10/18.54 [2019-03-28 12:18:37,661 WARN L188 SmtUtils]: Spent 225.00 ms on a formula simplification. DAG size of input: 86 DAG size of output: 82 37.10/18.54 [2019-03-28 12:18:37,766 INFO L216 LassoAnalysis]: Preferences: 37.10/18.54 [2019-03-28 12:18:37,767 INFO L124 ssoRankerPreferences]: Compute integeral hull: false 37.10/18.54 [2019-03-28 12:18:37,768 INFO L125 ssoRankerPreferences]: Enable LassoPartitioneer: true 37.10/18.54 [2019-03-28 12:18:37,768 INFO L126 ssoRankerPreferences]: Term annotations enabled: false 37.10/18.54 [2019-03-28 12:18:37,768 INFO L127 ssoRankerPreferences]: Use exernal solver: true 37.10/18.54 [2019-03-28 12:18:37,768 INFO L128 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:4560 -smt2 -in -t:12000 37.10/18.54 [2019-03-28 12:18:37,768 INFO L129 ssoRankerPreferences]: Dump SMT script to file: false 37.10/18.54 [2019-03-28 12:18:37,768 INFO L130 ssoRankerPreferences]: Path of dumped script: 37.10/18.54 [2019-03-28 12:18:37,769 INFO L131 ssoRankerPreferences]: Filename of dumped script: theBenchmark.c_BEv2_Iteration9_Loop 37.10/18.54 [2019-03-28 12:18:37,769 INFO L132 ssoRankerPreferences]: MapElimAlgo: Frank 37.10/18.54 [2019-03-28 12:18:37,769 INFO L282 LassoAnalysis]: Starting lasso preprocessing... 37.10/18.54 [2019-03-28 12:18:37,789 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 37.10/18.54 [2019-03-28 12:18:37,799 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 37.10/18.54 [2019-03-28 12:18:37,800 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 37.10/18.54 [2019-03-28 12:18:37,805 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 37.10/18.54 [2019-03-28 12:18:37,806 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 37.10/18.54 [2019-03-28 12:18:37,813 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 37.10/18.54 [2019-03-28 12:18:37,817 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 37.10/18.54 [2019-03-28 12:18:37,819 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 37.10/18.54 [2019-03-28 12:18:37,825 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 37.10/18.54 [2019-03-28 12:18:37,828 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 37.10/18.54 [2019-03-28 12:18:37,837 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 37.10/18.54 [2019-03-28 12:18:37,839 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 37.10/18.54 [2019-03-28 12:18:37,845 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 37.10/18.54 [2019-03-28 12:18:37,848 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 37.10/18.54 [2019-03-28 12:18:37,853 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 37.10/18.54 [2019-03-28 12:18:37,859 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 37.10/18.54 [2019-03-28 12:18:37,863 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 37.10/18.54 [2019-03-28 12:18:37,868 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 37.10/18.54 [2019-03-28 12:18:38,089 INFO L300 LassoAnalysis]: Preprocessing complete. 37.10/18.54 [2019-03-28 12:18:38,090 INFO L412 LassoAnalysis]: Checking for nontermination... 37.10/18.54 No working directory specified, using /export/starexec/sandbox/solver/bin/z3 37.10/18.54 Starting monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:4560 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) 37.10/18.54 Waiting until toolchain timeout for monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:4560 -smt2 -in -t:12000 37.10/18.54 [2019-03-28 12:18:38,097 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true 37.10/18.54 [2019-03-28 12:18:38,097 INFO L163 nArgumentSynthesizer]: Using integer mode. 37.10/18.54 [2019-03-28 12:18:38,109 INFO L445 LassoAnalysis]: Proved nontermination for one component. 37.10/18.54 [2019-03-28 12:18:38,109 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet4=-8, ULTIMATE.start_eval_~tmp~1=-8} Honda state: {ULTIMATE.start_eval_#t~nondet4=-8, ULTIMATE.start_eval_~tmp~1=-8} Generalized eigenvectors: [] Lambdas: [] Nus: [] 37.10/18.54 No working directory specified, using /export/starexec/sandbox/solver/bin/z3 37.10/18.54 Starting monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:4560 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) 37.10/18.54 Waiting until toolchain timeout for monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:4560 -smt2 -in -t:12000 37.10/18.54 [2019-03-28 12:18:38,139 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true 37.10/18.54 [2019-03-28 12:18:38,140 INFO L163 nArgumentSynthesizer]: Using integer mode. 37.10/18.54 [2019-03-28 12:18:38,143 INFO L445 LassoAnalysis]: Proved nontermination for one component. 37.10/18.54 [2019-03-28 12:18:38,143 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_immediate_notify_threads_#t~ret1=0} Honda state: {ULTIMATE.start_immediate_notify_threads_#t~ret1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] 37.10/18.54 No working directory specified, using /export/starexec/sandbox/solver/bin/z3 37.10/18.54 Starting monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:4560 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) 37.10/18.54 Waiting until toolchain timeout for monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:4560 -smt2 -in -t:12000 37.10/18.54 [2019-03-28 12:18:38,172 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true 37.10/18.54 [2019-03-28 12:18:38,172 INFO L163 nArgumentSynthesizer]: Using integer mode. 37.10/18.54 No working directory specified, using /export/starexec/sandbox/solver/bin/z3 37.10/18.54 Starting monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:4560 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) 37.10/18.54 Waiting until toolchain timeout for monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:4560 -smt2 -in -t:12000 37.10/18.54 [2019-03-28 12:18:38,203 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true 37.10/18.54 [2019-03-28 12:18:38,203 INFO L163 nArgumentSynthesizer]: Using integer mode. 37.10/18.54 [2019-03-28 12:18:38,209 INFO L452 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. 37.10/18.54 [2019-03-28 12:18:38,237 INFO L216 LassoAnalysis]: Preferences: 37.10/18.54 [2019-03-28 12:18:38,237 INFO L124 ssoRankerPreferences]: Compute integeral hull: false 37.10/18.54 [2019-03-28 12:18:38,237 INFO L125 ssoRankerPreferences]: Enable LassoPartitioneer: true 37.10/18.54 [2019-03-28 12:18:38,237 INFO L126 ssoRankerPreferences]: Term annotations enabled: false 37.10/18.54 [2019-03-28 12:18:38,238 INFO L127 ssoRankerPreferences]: Use exernal solver: false 37.10/18.54 [2019-03-28 12:18:38,238 INFO L128 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 37.10/18.54 [2019-03-28 12:18:38,238 INFO L129 ssoRankerPreferences]: Dump SMT script to file: false 37.10/18.54 [2019-03-28 12:18:38,238 INFO L130 ssoRankerPreferences]: Path of dumped script: 37.10/18.54 [2019-03-28 12:18:38,238 INFO L131 ssoRankerPreferences]: Filename of dumped script: theBenchmark.c_BEv2_Iteration9_Loop 37.10/18.54 [2019-03-28 12:18:38,238 INFO L132 ssoRankerPreferences]: MapElimAlgo: Frank 37.10/18.54 [2019-03-28 12:18:38,238 INFO L282 LassoAnalysis]: Starting lasso preprocessing... 37.10/18.54 [2019-03-28 12:18:38,242 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 37.10/18.54 [2019-03-28 12:18:38,254 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 37.10/18.54 [2019-03-28 12:18:38,257 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 37.10/18.54 [2019-03-28 12:18:38,263 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 37.10/18.54 [2019-03-28 12:18:38,270 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 37.10/18.54 [2019-03-28 12:18:38,272 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 37.10/18.54 [2019-03-28 12:18:38,306 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 37.10/18.54 [2019-03-28 12:18:38,338 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 37.10/18.54 [2019-03-28 12:18:38,342 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 37.10/18.54 [2019-03-28 12:18:38,344 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 37.10/18.54 [2019-03-28 12:18:38,351 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 37.10/18.54 [2019-03-28 12:18:38,355 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 37.10/18.54 [2019-03-28 12:18:38,357 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 37.10/18.54 [2019-03-28 12:18:38,363 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 37.10/18.54 [2019-03-28 12:18:38,369 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 37.10/18.54 [2019-03-28 12:18:38,375 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 37.10/18.54 [2019-03-28 12:18:38,381 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 37.10/18.54 [2019-03-28 12:18:38,388 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 37.10/18.54 [2019-03-28 12:18:38,661 INFO L300 LassoAnalysis]: Preprocessing complete. 37.10/18.54 [2019-03-28 12:18:38,667 INFO L497 LassoAnalysis]: Using template 'affine'. 37.10/18.54 [2019-03-28 12:18:38,669 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: 37.10/18.54 Termination analysis: LINEAR_WITH_GUESSES 37.10/18.54 Number of strict supporting invariants: 0 37.10/18.54 Number of non-strict supporting invariants: 1 37.10/18.54 Consider only non-deceasing supporting invariants: true 37.10/18.54 Simplify termination arguments: true 37.10/18.54 Simplify supporting invariants: trueOverapproximate stem: false 37.10/18.54 [2019-03-28 12:18:38,671 INFO L339 nArgumentSynthesizer]: Template has degree 0. 37.10/18.54 [2019-03-28 12:18:38,671 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. 37.10/18.54 [2019-03-28 12:18:38,672 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts 37.10/18.54 [2019-03-28 12:18:38,672 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts 37.10/18.54 [2019-03-28 12:18:38,673 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. 37.10/18.54 [2019-03-28 12:18:38,675 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. 37.10/18.54 [2019-03-28 12:18:38,675 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. 37.10/18.54 [2019-03-28 12:18:38,682 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. 37.10/18.54 [2019-03-28 12:18:38,682 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: 37.10/18.54 Termination analysis: LINEAR_WITH_GUESSES 37.10/18.54 Number of strict supporting invariants: 0 37.10/18.54 Number of non-strict supporting invariants: 1 37.10/18.54 Consider only non-deceasing supporting invariants: true 37.10/18.54 Simplify termination arguments: true 37.10/18.54 Simplify supporting invariants: trueOverapproximate stem: false 37.10/18.54 [2019-03-28 12:18:38,683 INFO L339 nArgumentSynthesizer]: Template has degree 0. 37.10/18.54 [2019-03-28 12:18:38,683 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. 37.10/18.54 [2019-03-28 12:18:38,683 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts 37.10/18.54 [2019-03-28 12:18:38,684 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts 37.10/18.54 [2019-03-28 12:18:38,684 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. 37.10/18.54 [2019-03-28 12:18:38,684 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. 37.10/18.54 [2019-03-28 12:18:38,684 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. 37.10/18.54 [2019-03-28 12:18:38,685 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. 37.10/18.54 [2019-03-28 12:18:38,686 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: 37.10/18.54 Termination analysis: LINEAR_WITH_GUESSES 37.10/18.54 Number of strict supporting invariants: 0 37.10/18.54 Number of non-strict supporting invariants: 1 37.10/18.54 Consider only non-deceasing supporting invariants: true 37.10/18.54 Simplify termination arguments: true 37.10/18.54 Simplify supporting invariants: trueOverapproximate stem: false 37.10/18.54 [2019-03-28 12:18:38,686 INFO L339 nArgumentSynthesizer]: Template has degree 0. 37.10/18.54 [2019-03-28 12:18:38,686 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. 37.10/18.54 [2019-03-28 12:18:38,686 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts 37.10/18.54 [2019-03-28 12:18:38,687 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts 37.10/18.54 [2019-03-28 12:18:38,687 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. 37.10/18.54 [2019-03-28 12:18:38,688 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. 37.10/18.54 [2019-03-28 12:18:38,688 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. 37.10/18.54 [2019-03-28 12:18:38,691 INFO L421 nArgumentSynthesizer]: Found a termination argument, trying to simplify. 37.10/18.54 [2019-03-28 12:18:38,694 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. 37.10/18.54 [2019-03-28 12:18:38,694 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. 37.10/18.54 [2019-03-28 12:18:38,696 INFO L437 nArgumentSynthesizer]: Simplifying supporting invariants... 37.10/18.54 [2019-03-28 12:18:38,696 INFO L440 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. 37.10/18.54 [2019-03-28 12:18:38,697 INFO L518 LassoAnalysis]: Proved termination. 37.10/18.54 [2019-03-28 12:18:38,697 INFO L520 LassoAnalysis]: Termination argument consisting of: 37.10/18.54 Ranking function f(~q_free~0) = -2*~q_free~0 + 1 37.10/18.54 Supporting invariants [] 37.10/18.54 [2019-03-28 12:18:38,698 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed 37.10/18.54 [2019-03-28 12:18:38,744 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.54 [2019-03-28 12:18:38,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 37.10/18.54 [2019-03-28 12:18:38,766 INFO L256 TraceCheckSpWp]: Trace formula consists of 44 conjuncts, 2 conjunts are in the unsatisfiable core 37.10/18.54 [2019-03-28 12:18:38,768 INFO L279 TraceCheckSpWp]: Computing forward predicates... 37.10/18.54 [2019-03-28 12:18:38,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 37.10/18.54 [2019-03-28 12:18:38,794 INFO L256 TraceCheckSpWp]: Trace formula consists of 92 conjuncts, 4 conjunts are in the unsatisfiable core 37.10/18.54 [2019-03-28 12:18:38,795 INFO L279 TraceCheckSpWp]: Computing forward predicates... 37.10/18.54 [2019-03-28 12:18:38,874 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 37.10/18.54 [2019-03-28 12:18:39,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 37.10/18.54 [2019-03-28 12:18:39,039 INFO L256 TraceCheckSpWp]: Trace formula consists of 92 conjuncts, 2 conjunts are in the unsatisfiable core 37.10/18.54 [2019-03-28 12:18:39,041 INFO L279 TraceCheckSpWp]: Computing forward predicates... 37.10/18.54 [2019-03-28 12:18:39,504 WARN L860 $PredicateComparison]: unable to prove that (exists ((~q_free~0 Int)) (<= 1 (+ (* 2 ~q_free~0) c_oldRank0))) is different from true 37.10/18.54 [2019-03-28 12:18:40,382 WARN L188 SmtUtils]: Spent 437.00 ms on a formula simplification that was a NOOP. DAG size: 11 37.10/18.54 [2019-03-28 12:18:40,828 WARN L860 $PredicateComparison]: unable to prove that (exists ((v_prenex_2 Int)) (<= 1 (+ (* 2 v_prenex_2) c_oldRank0))) is different from true 37.10/18.54 [2019-03-28 12:18:40,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 37.10/18.54 [2019-03-28 12:18:40,850 INFO L256 TraceCheckSpWp]: Trace formula consists of 92 conjuncts, 2 conjunts are in the unsatisfiable core 37.10/18.54 [2019-03-28 12:18:40,851 INFO L279 TraceCheckSpWp]: Computing forward predicates... 37.10/18.54 [2019-03-28 12:18:41,300 WARN L188 SmtUtils]: Spent 438.00 ms on a formula simplification that was a NOOP. DAG size: 11 37.10/18.54 [2019-03-28 12:18:41,768 INFO L98 LoopCannibalizer]: 3 predicates before loop cannibalization 7 predicates after loop cannibalization 37.10/18.54 [2019-03-28 12:18:41,772 INFO L152 lantAutomatonBouncer]: Defining Buchi interpolant automaton with scrooge nondeterminism in stemwith honda bouncer for stem and without honda bouncer for loop.1 stem predicates 7 loop predicates 37.10/18.54 [2019-03-28 12:18:41,772 INFO L69 BuchiDifferenceNCSB]: Start buchiDifferenceNCSB. First operand 81 states and 146 transitions. cyclomatic complexity: 66 Second operand 5 states. 37.10/18.54 [2019-03-28 12:18:43,937 INFO L73 BuchiDifferenceNCSB]: Finished buchiDifferenceNCSB. First operand 81 states and 146 transitions. cyclomatic complexity: 66. Second operand 5 states. Result 6232 states and 10876 transitions. Complement of second has 491 states. 37.10/18.54 [2019-03-28 12:18:43,938 INFO L142 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 14 states 1 stem states 9 non-accepting loop states 3 accepting loop states 37.10/18.54 [2019-03-28 12:18:43,938 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5 states. 37.10/18.54 [2019-03-28 12:18:43,940 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 724 transitions. 37.10/18.54 [2019-03-28 12:18:43,942 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 14 states and 724 transitions. Stem has 4 letters. Loop has 26 letters. 37.10/18.54 [2019-03-28 12:18:43,946 INFO L116 BuchiAccepts]: Finished buchiAccepts. 37.10/18.54 [2019-03-28 12:18:43,946 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 14 states and 724 transitions. Stem has 30 letters. Loop has 26 letters. 37.10/18.54 [2019-03-28 12:18:43,948 INFO L116 BuchiAccepts]: Finished buchiAccepts. 37.10/18.54 [2019-03-28 12:18:43,948 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 14 states and 724 transitions. Stem has 4 letters. Loop has 52 letters. 37.10/18.54 [2019-03-28 12:18:43,950 INFO L116 BuchiAccepts]: Finished buchiAccepts. 37.10/18.54 [2019-03-28 12:18:43,964 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6232 states and 10876 transitions. 37.10/18.54 [2019-03-28 12:18:44,027 INFO L131 ngComponentsAnalysis]: Automaton has 9 accepting balls. 815 37.10/18.54 [2019-03-28 12:18:44,036 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6232 states to 1018 states and 1743 transitions. 37.10/18.54 [2019-03-28 12:18:44,036 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 828 37.10/18.54 [2019-03-28 12:18:44,037 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 888 37.10/18.54 [2019-03-28 12:18:44,038 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1018 states and 1743 transitions. 37.10/18.54 [2019-03-28 12:18:44,038 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. 37.10/18.54 [2019-03-28 12:18:44,038 INFO L706 BuchiCegarLoop]: Abstraction has 1018 states and 1743 transitions. 37.10/18.54 [2019-03-28 12:18:44,039 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1018 states and 1743 transitions. 37.10/18.54 [2019-03-28 12:18:44,056 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1018 to 422. 37.10/18.54 [2019-03-28 12:18:44,057 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 422 states. 37.10/18.54 [2019-03-28 12:18:44,059 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 422 states to 422 states and 735 transitions. 37.10/18.54 [2019-03-28 12:18:44,059 INFO L729 BuchiCegarLoop]: Abstraction has 422 states and 735 transitions. 37.10/18.54 [2019-03-28 12:18:44,059 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 37.10/18.54 [2019-03-28 12:18:44,060 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 37.10/18.54 [2019-03-28 12:18:44,060 INFO L87 Difference]: Start difference. First operand 422 states and 735 transitions. Second operand 3 states. 37.10/18.54 [2019-03-28 12:18:44,179 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 37.10/18.54 [2019-03-28 12:18:44,180 INFO L93 Difference]: Finished difference Result 395 states and 682 transitions. 37.10/18.54 [2019-03-28 12:18:44,180 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 37.10/18.54 [2019-03-28 12:18:44,186 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 395 states and 682 transitions. 37.10/18.54 [2019-03-28 12:18:44,190 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 346 37.10/18.54 [2019-03-28 12:18:44,192 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 395 states to 363 states and 632 transitions. 37.10/18.54 [2019-03-28 12:18:44,193 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 331 37.10/18.54 [2019-03-28 12:18:44,193 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 331 37.10/18.54 [2019-03-28 12:18:44,193 INFO L73 IsDeterministic]: Start isDeterministic. Operand 363 states and 632 transitions. 37.10/18.54 [2019-03-28 12:18:44,194 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. 37.10/18.54 [2019-03-28 12:18:44,194 INFO L706 BuchiCegarLoop]: Abstraction has 363 states and 632 transitions. 37.10/18.54 [2019-03-28 12:18:44,194 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 363 states and 632 transitions. 37.10/18.54 [2019-03-28 12:18:44,199 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 363 to 296. 37.10/18.54 [2019-03-28 12:18:44,200 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 296 states. 37.10/18.54 [2019-03-28 12:18:44,201 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 296 states to 296 states and 521 transitions. 37.10/18.54 [2019-03-28 12:18:44,201 INFO L729 BuchiCegarLoop]: Abstraction has 296 states and 521 transitions. 37.10/18.54 [2019-03-28 12:18:44,201 INFO L609 BuchiCegarLoop]: Abstraction has 296 states and 521 transitions. 37.10/18.54 [2019-03-28 12:18:44,201 INFO L442 BuchiCegarLoop]: ======== Iteration 10============ 37.10/18.54 [2019-03-28 12:18:44,201 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 296 states and 521 transitions. 37.10/18.54 [2019-03-28 12:18:44,203 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 292 37.10/18.54 [2019-03-28 12:18:44,203 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 37.10/18.54 [2019-03-28 12:18:44,203 INFO L119 BuchiIsEmpty]: Starting construction of run 37.10/18.54 [2019-03-28 12:18:44,205 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1] 37.10/18.54 [2019-03-28 12:18:44,205 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 37.10/18.54 [2019-03-28 12:18:44,205 INFO L794 eck$LassoCheckResult]: Stem: 9375#ULTIMATE.startENTRY [520] ULTIMATE.startENTRY-->L196: Formula: (and (= v_~q_write_ev~0_11 v_~q_read_ev~0_11) (= 1 v_~c_dr_i~0_7) (= v_~q_free~0_11 1) (= v_~q_buf_0~0_5 0) (= v_~q_write_ev~0_11 2) (= 0 v_~p_last_write~0_6) (= 0 v_~c_last_read~0_6) (= v_~p_dw_pc~0_14 0) (= 0 v_~a_t~0_5) (= 0 v_~c_dr_st~0_15) (= v_~c_dr_pc~0_14 0) (= 0 v_~c_num_read~0_9) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 0) (= 0 v_~p_num_write~0_9) (= v_~p_dw_i~0_7 1) (= v_~p_dw_st~0_15 0)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ~p_last_write~0=v_~p_last_write~0_6, ~c_dr_pc~0=v_~c_dr_pc~0_14, ~c_dr_st~0=v_~c_dr_st~0_15, ~c_num_read~0=v_~c_num_read~0_9, ~p_num_write~0=v_~p_num_write~0_9, ~c_dr_i~0=v_~c_dr_i~0_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7, ~q_write_ev~0=v_~q_write_ev~0_11, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~p_dw_st~0=v_~p_dw_st~0_15, ~p_dw_i~0=v_~p_dw_i~0_7, ~c_last_read~0=v_~c_last_read~0_6, ~p_dw_pc~0=v_~p_dw_pc~0_14, ~q_free~0=v_~q_free~0_11, ~q_buf_0~0=v_~q_buf_0~0_5, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6, ~q_read_ev~0=v_~q_read_ev~0_11, ~a_t~0=v_~a_t~0_5} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ~p_last_write~0, ~c_dr_pc~0, ~c_dr_st~0, ~c_num_read~0, ~p_num_write~0, ~c_dr_i~0, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_~kernel_st~0, ~q_write_ev~0, ULTIMATE.start_main_#res, ~p_dw_st~0, ~p_dw_i~0, ~c_last_read~0, ~p_dw_pc~0, ~q_free~0, ~q_buf_0~0, ULTIMATE.start_main_~__retres1~3, ~q_read_ev~0, ~a_t~0] 9376#L196 [418] L196-->L196-2: Formula: (and (= v_~p_dw_i~0_3 1) (= v_~p_dw_st~0_2 0)) InVars {~p_dw_i~0=v_~p_dw_i~0_3} OutVars{~p_dw_st~0=v_~p_dw_st~0_2, ~p_dw_i~0=v_~p_dw_i~0_3} AuxVars[] AssignedVars[~p_dw_st~0] 9423#L196-2 [413] L196-2-->L313-1: Formula: (and (= 1 v_~c_dr_i~0_3) (= v_~c_dr_st~0_3 0)) InVars {~c_dr_i~0=v_~c_dr_i~0_3} OutVars{~c_dr_st~0=v_~c_dr_st~0_3, ~c_dr_i~0=v_~c_dr_i~0_3} AuxVars[] AssignedVars[~c_dr_st~0] 9424#L313-1 [521] L313-1-->L262: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_8 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_8, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_4|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_6, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_6, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp~1, ULTIMATE.start_eval_~tmp___0~1, ULTIMATE.start_eval_~tmp___1~0] 9569#L262 37.10/18.54 [2019-03-28 12:18:44,206 INFO L796 eck$LassoCheckResult]: Loop: 9569#L262 [522] L262-->L214: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 9583#L214 [406] L214-->L226: Formula: (and (= v_~p_dw_st~0_6 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11 1)) InVars {~p_dw_st~0=v_~p_dw_st~0_6} OutVars{~p_dw_st~0=v_~p_dw_st~0_6, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 9567#L226 [523] L226-->L242: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___1~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_5|, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp___1~0] 9564#L242 [468] L242-->L242-1: Formula: (> v_ULTIMATE.start_eval_~tmp___1~0_4 0) InVars {ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} OutVars{ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} AuxVars[] AssignedVars[] 9537#L242-1 [333] L242-1-->L251: Formula: (and (= v_ULTIMATE.start_eval_~tmp~1_3 |v_ULTIMATE.start_eval_#t~nondet4_3|) (= v_~p_dw_st~0_8 0)) InVars {ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_3|, ~p_dw_st~0=v_~p_dw_st~0_8} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_2|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_3, ~p_dw_st~0=v_~p_dw_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_~tmp~1] 9406#L251 [471] L251-->L96: Formula: (and (= v_~p_dw_st~0_9 1) (< v_ULTIMATE.start_eval_~tmp~1_4 0)) InVars {ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_4} OutVars{ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_4, ~p_dw_st~0=v_~p_dw_st~0_9, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_1|} AuxVars[] AssignedVars[~p_dw_st~0, ULTIMATE.start_do_write_p_#t~nondet2] 9407#L96 [378] L96-->L107-1: Formula: (= v_~p_dw_pc~0_3 0) InVars {~p_dw_pc~0=v_~p_dw_pc~0_3} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_3} AuxVars[] AssignedVars[] 9385#L107-1 [375] L107-1-->L108: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 9392#L108 [486] L108-->L109: Formula: (> v_~q_free~0_4 0) InVars {~q_free~0=v_~q_free~0_4} OutVars{~q_free~0=v_~q_free~0_4} AuxVars[] AssignedVars[] 9355#L109 [323] L109-->L32: Formula: (and (= v_~q_buf_0~0_2 |v_ULTIMATE.start_do_write_p_#t~nondet2_3|) (= v_~p_last_write~0_2 v_~q_buf_0~0_2) (= v_~q_write_ev~0_3 1) (= v_~p_num_write~0_3 (+ v_~p_num_write~0_4 1)) (= v_~q_free~0_5 0)) InVars {~p_num_write~0=v_~p_num_write~0_4, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_3|} OutVars{~p_last_write~0=v_~p_last_write~0_2, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_2|, ~p_num_write~0=v_~p_num_write~0_3, ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_1, ~q_write_ev~0=v_~q_write_ev~0_3, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_1, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_1|, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_1|, ~q_free~0=v_~q_free~0_5, ~q_buf_0~0=v_~q_buf_0~0_2, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_1|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_1} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0, ~q_write_ev~0, ~p_last_write~0, ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_do_write_p_#t~nondet2, ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret1, ~p_num_write~0, ~q_free~0, ~q_buf_0~0, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 9356#L32 [489] L32-->L32-2: Formula: (< v_~p_dw_pc~0_9 1) InVars {~p_dw_pc~0=v_~p_dw_pc~0_9} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_9} AuxVars[] AssignedVars[] 9431#L32-2 [403] L32-2-->L43: Formula: (= v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_4 0) InVars {} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_4} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0] 9345#L43 [528] L43-->L74: Formula: (and (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_7| v_ULTIMATE.start_immediate_notify_threads_~tmp~0_11) (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_7| v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11)) InVars {ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_7|, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_7|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 9346#L74 [499] L74-->L74-2: Formula: (and (> v_ULTIMATE.start_immediate_notify_threads_~tmp~0_4 0) (= v_~p_dw_st~0_11 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_4} OutVars{~p_dw_st~0=v_~p_dw_st~0_11, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_4} AuxVars[] AssignedVars[~p_dw_st~0] 9444#L74-2 [339] L74-2-->L51: Formula: true InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_1|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_1} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_#res, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 9443#L51 [309] L51-->L52: Formula: (= 1 v_~c_dr_pc~0_3) InVars {~c_dr_pc~0=v_~c_dr_pc~0_3} OutVars{~c_dr_pc~0=v_~c_dr_pc~0_3} AuxVars[] AssignedVars[] 9441#L52 [343] L52-->L62: Formula: (and (= v_~q_write_ev~0_4 1) (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_4 1)) InVars {~q_write_ev~0=v_~q_write_ev~0_4} OutVars{~q_write_ev~0=v_~q_write_ev~0_4, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_4} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 9328#L62 [532] L62-->L82: Formula: (and (= v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_11 |v_ULTIMATE.start_is_do_read_c_triggered_#res_7|) (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13 |v_ULTIMATE.start_is_do_read_c_triggered_#res_7|)) InVars {ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13} OutVars{ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_11, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_7|, ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_7|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13} AuxVars[] AssignedVars[ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_immediate_notify_threads_#t~ret1, ULTIMATE.start_is_do_read_c_triggered_#res] 9329#L82 [512] L82-->L82-2: Formula: (and (> v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_4 0) (= v_~c_dr_st~0_9 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_4} OutVars{~c_dr_st~0=v_~c_dr_st~0_9, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_4} AuxVars[] AssignedVars[~c_dr_st~0] 9388#L82-2 [366] L82-2-->L107-1: Formula: (= v_~q_write_ev~0_6 2) InVars {} OutVars{~q_write_ev~0=v_~q_write_ev~0_6} AuxVars[] AssignedVars[~q_write_ev~0] 9389#L107-1 [375] L107-1-->L108: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 9445#L108 [408] L108-->L247: Formula: (and (= v_~q_free~0_3 0) (= v_~p_dw_pc~0_7 1) (= v_~p_dw_st~0_10 2)) InVars {~q_free~0=v_~q_free~0_3} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_7, ~q_free~0=v_~q_free~0_3, ~p_dw_st~0=v_~p_dw_st~0_10} AuxVars[] AssignedVars[~p_dw_st~0, ~p_dw_pc~0] 9446#L247 [473] L247-->L262: Formula: (< 0 v_~c_dr_st~0_2) InVars {~c_dr_st~0=v_~c_dr_st~0_2} OutVars{~c_dr_st~0=v_~c_dr_st~0_2} AuxVars[] AssignedVars[] 9490#L262 [522] L262-->L214: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 9509#L214 [460] L214-->L218: Formula: (> v_~p_dw_st~0_7 0) InVars {~p_dw_st~0=v_~p_dw_st~0_7} OutVars{~p_dw_st~0=v_~p_dw_st~0_7} AuxVars[] AssignedVars[] 9507#L218 [464] L218-->L226: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_13 0) (> 0 v_~c_dr_st~0_8)) InVars {~c_dr_st~0=v_~c_dr_st~0_8} OutVars{~c_dr_st~0=v_~c_dr_st~0_8, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_13} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 9508#L226 [523] L226-->L242: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___1~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_5|, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp___1~0] 9502#L242 [524] L242-->L214-1: Formula: (= v_ULTIMATE.start_eval_~tmp___1~0_8 0) InVars {ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_17, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_7, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_stop_simulation_#t~ret6=|v_ULTIMATE.start_stop_simulation_#t~ret6_4|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_4|, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret6, ULTIMATE.start_stop_simulation_#res] 9503#L214-1 [458] L214-1-->L218-1: Formula: (> v_~p_dw_st~0_5 0) InVars {~p_dw_st~0=v_~p_dw_st~0_5} OutVars{~p_dw_st~0=v_~p_dw_st~0_5} AuxVars[] AssignedVars[] 9526#L218-1 [416] L218-1-->L226-1: Formula: (and (= 0 v_~c_dr_st~0_5) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_5 1)) InVars {~c_dr_st~0=v_~c_dr_st~0_5} OutVars{~c_dr_st~0=v_~c_dr_st~0_5, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_5} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 9522#L226-1 [525] L226-1-->L292: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18 |v_ULTIMATE.start_exists_runnable_thread_#res_10|) (= v_ULTIMATE.start_stop_simulation_~tmp~2_8 |v_ULTIMATE.start_exists_runnable_thread_#res_10|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_8, ULTIMATE.start_stop_simulation_#t~ret6=|v_ULTIMATE.start_stop_simulation_#t~ret6_5|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret6] 9523#L292 [465] L292-->L299: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_4 0) (< 0 v_ULTIMATE.start_stop_simulation_~tmp~2_5)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_4, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 9518#L299 [534] L299-->L313-1: Formula: (and (= 0 v_ULTIMATE.start_start_simulation_~tmp~3_9) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_9 |v_ULTIMATE.start_stop_simulation_#res_6|) (= |v_ULTIMATE.start_stop_simulation_#res_6| v_ULTIMATE.start_start_simulation_~tmp~3_9)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_9} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_6|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_~tmp~3] 9519#L313-1 [521] L313-1-->L262: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_8 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_8, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_4|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_6, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_6, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp~1, ULTIMATE.start_eval_~tmp___0~1, ULTIMATE.start_eval_~tmp___1~0] 9514#L262 [522] L262-->L214: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 9515#L214 [460] L214-->L218: Formula: (> v_~p_dw_st~0_7 0) InVars {~p_dw_st~0=v_~p_dw_st~0_7} OutVars{~p_dw_st~0=v_~p_dw_st~0_7} AuxVars[] AssignedVars[] 9610#L218 [464] L218-->L226: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_13 0) (> 0 v_~c_dr_st~0_8)) InVars {~c_dr_st~0=v_~c_dr_st~0_8} OutVars{~c_dr_st~0=v_~c_dr_st~0_8, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_13} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 9606#L226 [523] L226-->L242: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___1~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_5|, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp___1~0] 9602#L242 [467] L242-->L242-1: Formula: (< v_ULTIMATE.start_eval_~tmp___1~0_4 0) InVars {ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} OutVars{ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} AuxVars[] AssignedVars[] 9364#L242-1 [469] L242-1-->L247: Formula: (> v_~p_dw_st~0_12 0) InVars {~p_dw_st~0=v_~p_dw_st~0_12} OutVars{~p_dw_st~0=v_~p_dw_st~0_12} AuxVars[] AssignedVars[] 9365#L247 [410] L247-->L266: Formula: (and (= 0 v_~c_dr_st~0_10) (= v_ULTIMATE.start_eval_~tmp___0~1_4 |v_ULTIMATE.start_eval_#t~nondet5_3|)) InVars {~c_dr_st~0=v_~c_dr_st~0_10, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_3|} OutVars{~c_dr_st~0=v_~c_dr_st~0_10, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_4, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_2|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp___0~1] 9330#L266 [480] L266-->L139: Formula: (and (= v_~c_dr_st~0_11 1) (> v_ULTIMATE.start_eval_~tmp___0~1_5 0)) InVars {ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_5} OutVars{~c_dr_st~0=v_~c_dr_st~0_11, ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_1, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_5} AuxVars[] AssignedVars[~c_dr_st~0, ULTIMATE.start_do_read_c_~a~0] 9331#L139 [483] L139-->L142: Formula: (< 0 v_~c_dr_pc~0_6) InVars {~c_dr_pc~0=v_~c_dr_pc~0_6} OutVars{~c_dr_pc~0=v_~c_dr_pc~0_6} AuxVars[] AssignedVars[] 9587#L142 [526] L142-->L152-1: Formula: (and (= v_~c_dr_pc~0_15 1) (= v_ULTIMATE.start_do_read_c_~a~0_6 v_~a_t~0_6)) InVars {~c_dr_pc~0=v_~c_dr_pc~0_15, ~a_t~0=v_~a_t~0_6} OutVars{ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_6, ~c_dr_pc~0=v_~c_dr_pc~0_15, ~a_t~0=v_~a_t~0_6} AuxVars[] AssignedVars[ULTIMATE.start_do_read_c_~a~0] 9397#L152-1 [412] L152-1-->L32-3: Formula: (and (= v_~c_num_read~0_3 (+ v_~c_num_read~0_4 1)) (= v_~q_read_ev~0_5 1) (= v_ULTIMATE.start_do_read_c_~a~0_5 v_~q_buf_0~0_3) (= v_~c_last_read~0_2 v_ULTIMATE.start_do_read_c_~a~0_5) (= v_~q_free~0_8 1)) InVars {~c_num_read~0=v_~c_num_read~0_4, ~q_buf_0~0=v_~q_buf_0~0_3} OutVars{~c_num_read~0=v_~c_num_read~0_3, ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_6, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_6, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_4|, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_4|, ~c_last_read~0=v_~c_last_read~0_2, ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_5, ~q_free~0=v_~q_free~0_8, ~q_buf_0~0=v_~q_buf_0~0_3, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_4|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_6, ~q_read_ev~0=v_~q_read_ev~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0, ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret1, ~c_last_read~0, ULTIMATE.start_do_read_c_~a~0, ~c_num_read~0, ~q_free~0, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0, ~q_read_ev~0] 9582#L32-3 [495] L32-3-->L32-5: Formula: (< v_~p_dw_pc~0_11 1) InVars {~p_dw_pc~0=v_~p_dw_pc~0_11} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_11} AuxVars[] AssignedVars[] 9408#L32-5 [392] L32-5-->L43-1: Formula: (= v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_9 0) InVars {} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_9} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0] 9336#L43-1 [531] L43-1-->L74-3: Formula: (and (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_8| v_ULTIMATE.start_immediate_notify_threads_~tmp~0_12) (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_8| v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_12)) InVars {ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_12} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_12, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_8|, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_8|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_12} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 9337#L74-3 [503] L74-3-->L74-5: Formula: (and (> v_ULTIMATE.start_immediate_notify_threads_~tmp~0_9 0) (= v_~p_dw_st~0_13 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_9} OutVars{~p_dw_st~0=v_~p_dw_st~0_13, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_9} AuxVars[] AssignedVars[~p_dw_st~0] 9368#L74-5 [332] L74-5-->L51-3: Formula: true InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_4|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_7} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_#res, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 9578#L51-3 [507] L51-3-->L51-5: Formula: (> v_~c_dr_pc~0_11 1) InVars {~c_dr_pc~0=v_~c_dr_pc~0_11} OutVars{~c_dr_pc~0=v_~c_dr_pc~0_11} AuxVars[] AssignedVars[] 9576#L51-5 [327] L51-5-->L62-1: Formula: (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 9574#L62-1 [533] L62-1-->L82-3: Formula: (and (= v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_12 |v_ULTIMATE.start_is_do_read_c_triggered_#res_8|) (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_14 |v_ULTIMATE.start_is_do_read_c_triggered_#res_8|)) InVars {ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_14} OutVars{ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_12, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_8|, ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_8|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_14} AuxVars[] AssignedVars[ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_immediate_notify_threads_#t~ret1, ULTIMATE.start_is_do_read_c_triggered_#res] 9572#L82-3 [513] L82-3-->L82-5: Formula: (and (< v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_9 0) (= v_~c_dr_st~0_13 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_9} OutVars{~c_dr_st~0=v_~c_dr_st~0_13, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_9} AuxVars[] AssignedVars[~c_dr_st~0] 9571#L82-5 [536] L82-5-->L10-2: Formula: (and (= v_~p_num_write~0_10 v_~c_num_read~0_10) (= 2 v_~q_read_ev~0_13) (= v_~c_last_read~0_8 v_~p_last_write~0_8)) InVars {~p_last_write~0=v_~p_last_write~0_8, ~c_last_read~0=v_~c_last_read~0_8, ~c_num_read~0=v_~c_num_read~0_10, ~p_num_write~0=v_~p_num_write~0_10} OutVars{~p_last_write~0=v_~p_last_write~0_8, ~c_last_read~0=v_~c_last_read~0_8, ~c_num_read~0=v_~c_num_read~0_10, ~p_num_write~0=v_~p_num_write~0_10, ~q_read_ev~0=v_~q_read_ev~0_13} AuxVars[] AssignedVars[~q_read_ev~0] 9570#L10-2 [400] L10-2-->L151: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 9568#L151 [380] L151-->L262: Formula: (and (= v_~c_dr_st~0_12 2) (= v_~c_dr_pc~0_9 1) (= v_~a_t~0_2 v_ULTIMATE.start_do_read_c_~a~0_3) (= v_~q_free~0_6 1)) InVars {ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_3, ~q_free~0=v_~q_free~0_6} OutVars{ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_3, ~c_dr_pc~0=v_~c_dr_pc~0_9, ~c_dr_st~0=v_~c_dr_st~0_12, ~q_free~0=v_~q_free~0_6, ~a_t~0=v_~a_t~0_2} AuxVars[] AssignedVars[~c_dr_pc~0, ~c_dr_st~0, ~a_t~0] 9569#L262 37.10/18.54 [2019-03-28 12:18:44,207 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.54 [2019-03-28 12:18:44,207 INFO L82 PathProgramCache]: Analyzing trace with hash 16829863, now seen corresponding path program 5 times 37.10/18.54 [2019-03-28 12:18:44,207 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.54 [2019-03-28 12:18:44,207 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.54 [2019-03-28 12:18:44,208 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:44,208 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:44,208 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:44,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 37.10/18.54 [2019-03-28 12:18:44,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 37.10/18.54 [2019-03-28 12:18:44,216 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.54 [2019-03-28 12:18:44,216 INFO L82 PathProgramCache]: Analyzing trace with hash -1670093295, now seen corresponding path program 1 times 37.10/18.54 [2019-03-28 12:18:44,217 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.54 [2019-03-28 12:18:44,217 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.54 [2019-03-28 12:18:44,217 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:44,218 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:44,218 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:44,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 37.10/18.54 [2019-03-28 12:18:44,252 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 12 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. 37.10/18.54 [2019-03-28 12:18:44,252 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 37.10/18.54 [2019-03-28 12:18:44,252 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 37.10/18.54 [2019-03-28 12:18:44,253 INFO L811 eck$LassoCheckResult]: loop already infeasible 37.10/18.54 [2019-03-28 12:18:44,253 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 37.10/18.54 [2019-03-28 12:18:44,253 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 37.10/18.54 [2019-03-28 12:18:44,253 INFO L87 Difference]: Start difference. First operand 296 states and 521 transitions. cyclomatic complexity: 227 Second operand 3 states. 37.10/18.54 [2019-03-28 12:18:44,425 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 37.10/18.54 [2019-03-28 12:18:44,425 INFO L93 Difference]: Finished difference Result 505 states and 849 transitions. 37.10/18.54 [2019-03-28 12:18:44,426 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 37.10/18.54 [2019-03-28 12:18:44,431 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 505 states and 849 transitions. 37.10/18.54 [2019-03-28 12:18:44,436 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 487 37.10/18.54 [2019-03-28 12:18:44,441 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 505 states to 505 states and 849 transitions. 37.10/18.54 [2019-03-28 12:18:44,441 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 455 37.10/18.54 [2019-03-28 12:18:44,442 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 455 37.10/18.54 [2019-03-28 12:18:44,442 INFO L73 IsDeterministic]: Start isDeterministic. Operand 505 states and 849 transitions. 37.10/18.54 [2019-03-28 12:18:44,442 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. 37.10/18.54 [2019-03-28 12:18:44,443 INFO L706 BuchiCegarLoop]: Abstraction has 505 states and 849 transitions. 37.10/18.54 [2019-03-28 12:18:44,443 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 505 states and 849 transitions. 37.10/18.54 [2019-03-28 12:18:44,450 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 505 to 401. 37.10/18.54 [2019-03-28 12:18:44,451 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 401 states. 37.10/18.54 [2019-03-28 12:18:44,453 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 401 states to 401 states and 673 transitions. 37.10/18.54 [2019-03-28 12:18:44,453 INFO L729 BuchiCegarLoop]: Abstraction has 401 states and 673 transitions. 37.10/18.54 [2019-03-28 12:18:44,453 INFO L609 BuchiCegarLoop]: Abstraction has 401 states and 673 transitions. 37.10/18.54 [2019-03-28 12:18:44,453 INFO L442 BuchiCegarLoop]: ======== Iteration 11============ 37.10/18.54 [2019-03-28 12:18:44,453 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 401 states and 673 transitions. 37.10/18.54 [2019-03-28 12:18:44,455 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 383 37.10/18.54 [2019-03-28 12:18:44,456 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 37.10/18.54 [2019-03-28 12:18:44,456 INFO L119 BuchiIsEmpty]: Starting construction of run 37.10/18.54 [2019-03-28 12:18:44,457 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1] 37.10/18.54 [2019-03-28 12:18:44,457 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 37.10/18.54 [2019-03-28 12:18:44,457 INFO L794 eck$LassoCheckResult]: Stem: 10178#ULTIMATE.startENTRY [520] ULTIMATE.startENTRY-->L196: Formula: (and (= v_~q_write_ev~0_11 v_~q_read_ev~0_11) (= 1 v_~c_dr_i~0_7) (= v_~q_free~0_11 1) (= v_~q_buf_0~0_5 0) (= v_~q_write_ev~0_11 2) (= 0 v_~p_last_write~0_6) (= 0 v_~c_last_read~0_6) (= v_~p_dw_pc~0_14 0) (= 0 v_~a_t~0_5) (= 0 v_~c_dr_st~0_15) (= v_~c_dr_pc~0_14 0) (= 0 v_~c_num_read~0_9) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 0) (= 0 v_~p_num_write~0_9) (= v_~p_dw_i~0_7 1) (= v_~p_dw_st~0_15 0)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ~p_last_write~0=v_~p_last_write~0_6, ~c_dr_pc~0=v_~c_dr_pc~0_14, ~c_dr_st~0=v_~c_dr_st~0_15, ~c_num_read~0=v_~c_num_read~0_9, ~p_num_write~0=v_~p_num_write~0_9, ~c_dr_i~0=v_~c_dr_i~0_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7, ~q_write_ev~0=v_~q_write_ev~0_11, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~p_dw_st~0=v_~p_dw_st~0_15, ~p_dw_i~0=v_~p_dw_i~0_7, ~c_last_read~0=v_~c_last_read~0_6, ~p_dw_pc~0=v_~p_dw_pc~0_14, ~q_free~0=v_~q_free~0_11, ~q_buf_0~0=v_~q_buf_0~0_5, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6, ~q_read_ev~0=v_~q_read_ev~0_11, ~a_t~0=v_~a_t~0_5} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ~p_last_write~0, ~c_dr_pc~0, ~c_dr_st~0, ~c_num_read~0, ~p_num_write~0, ~c_dr_i~0, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_~kernel_st~0, ~q_write_ev~0, ULTIMATE.start_main_#res, ~p_dw_st~0, ~p_dw_i~0, ~c_last_read~0, ~p_dw_pc~0, ~q_free~0, ~q_buf_0~0, ULTIMATE.start_main_~__retres1~3, ~q_read_ev~0, ~a_t~0] 10179#L196 [418] L196-->L196-2: Formula: (and (= v_~p_dw_i~0_3 1) (= v_~p_dw_st~0_2 0)) InVars {~p_dw_i~0=v_~p_dw_i~0_3} OutVars{~p_dw_st~0=v_~p_dw_st~0_2, ~p_dw_i~0=v_~p_dw_i~0_3} AuxVars[] AssignedVars[~p_dw_st~0] 10219#L196-2 [456] L196-2-->L313-1: Formula: (and (= v_~c_dr_st~0_4 2) (< 1 v_~c_dr_i~0_4)) InVars {~c_dr_i~0=v_~c_dr_i~0_4} OutVars{~c_dr_st~0=v_~c_dr_st~0_4, ~c_dr_i~0=v_~c_dr_i~0_4} AuxVars[] AssignedVars[~c_dr_st~0] 10220#L313-1 [521] L313-1-->L262: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_8 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_8, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_4|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_6, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_6, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp~1, ULTIMATE.start_eval_~tmp___0~1, ULTIMATE.start_eval_~tmp___1~0] 10351#L262 37.10/18.54 [2019-03-28 12:18:44,458 INFO L796 eck$LassoCheckResult]: Loop: 10351#L262 [522] L262-->L214: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 10350#L214 [406] L214-->L226: Formula: (and (= v_~p_dw_st~0_6 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11 1)) InVars {~p_dw_st~0=v_~p_dw_st~0_6} OutVars{~p_dw_st~0=v_~p_dw_st~0_6, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 10347#L226 [523] L226-->L242: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___1~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_5|, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp___1~0] 10345#L242 [468] L242-->L242-1: Formula: (> v_ULTIMATE.start_eval_~tmp___1~0_4 0) InVars {ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} OutVars{ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} AuxVars[] AssignedVars[] 10343#L242-1 [333] L242-1-->L251: Formula: (and (= v_ULTIMATE.start_eval_~tmp~1_3 |v_ULTIMATE.start_eval_#t~nondet4_3|) (= v_~p_dw_st~0_8 0)) InVars {ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_3|, ~p_dw_st~0=v_~p_dw_st~0_8} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_2|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_3, ~p_dw_st~0=v_~p_dw_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_~tmp~1] 10341#L251 [471] L251-->L96: Formula: (and (= v_~p_dw_st~0_9 1) (< v_ULTIMATE.start_eval_~tmp~1_4 0)) InVars {ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_4} OutVars{ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_4, ~p_dw_st~0=v_~p_dw_st~0_9, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_1|} AuxVars[] AssignedVars[~p_dw_st~0, ULTIMATE.start_do_write_p_#t~nondet2] 10339#L96 [378] L96-->L107-1: Formula: (= v_~p_dw_pc~0_3 0) InVars {~p_dw_pc~0=v_~p_dw_pc~0_3} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_3} AuxVars[] AssignedVars[] 10334#L107-1 [375] L107-1-->L108: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 10332#L108 [486] L108-->L109: Formula: (> v_~q_free~0_4 0) InVars {~q_free~0=v_~q_free~0_4} OutVars{~q_free~0=v_~q_free~0_4} AuxVars[] AssignedVars[] 10279#L109 [323] L109-->L32: Formula: (and (= v_~q_buf_0~0_2 |v_ULTIMATE.start_do_write_p_#t~nondet2_3|) (= v_~p_last_write~0_2 v_~q_buf_0~0_2) (= v_~q_write_ev~0_3 1) (= v_~p_num_write~0_3 (+ v_~p_num_write~0_4 1)) (= v_~q_free~0_5 0)) InVars {~p_num_write~0=v_~p_num_write~0_4, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_3|} OutVars{~p_last_write~0=v_~p_last_write~0_2, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_2|, ~p_num_write~0=v_~p_num_write~0_3, ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_1, ~q_write_ev~0=v_~q_write_ev~0_3, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_1, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_1|, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_1|, ~q_free~0=v_~q_free~0_5, ~q_buf_0~0=v_~q_buf_0~0_2, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_1|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_1} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0, ~q_write_ev~0, ~p_last_write~0, ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_do_write_p_#t~nondet2, ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret1, ~p_num_write~0, ~q_free~0, ~q_buf_0~0, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 10300#L32 [316] L32-->L33: Formula: (= v_~p_dw_pc~0_8 1) InVars {~p_dw_pc~0=v_~p_dw_pc~0_8} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_8} AuxVars[] AssignedVars[] 10183#L33 [352] L33-->L43: Formula: (and (= v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_3 1) (= 1 v_~q_read_ev~0_3)) InVars {~q_read_ev~0=v_~q_read_ev~0_3} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_3, ~q_read_ev~0=v_~q_read_ev~0_3} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0] 10184#L43 [528] L43-->L74: Formula: (and (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_7| v_ULTIMATE.start_immediate_notify_threads_~tmp~0_11) (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_7| v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11)) InVars {ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_7|, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_7|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 10194#L74 [499] L74-->L74-2: Formula: (and (> v_ULTIMATE.start_immediate_notify_threads_~tmp~0_4 0) (= v_~p_dw_st~0_11 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_4} OutVars{~p_dw_st~0=v_~p_dw_st~0_11, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_4} AuxVars[] AssignedVars[~p_dw_st~0] 10195#L74-2 [339] L74-2-->L51: Formula: true InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_1|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_1} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_#res, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 10296#L51 [501] L51-->L51-2: Formula: (< 1 v_~c_dr_pc~0_4) InVars {~c_dr_pc~0=v_~c_dr_pc~0_4} OutVars{~c_dr_pc~0=v_~c_dr_pc~0_4} AuxVars[] AssignedVars[] 10290#L51-2 [307] L51-2-->L62: Formula: (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 10291#L62 [532] L62-->L82: Formula: (and (= v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_11 |v_ULTIMATE.start_is_do_read_c_triggered_#res_7|) (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13 |v_ULTIMATE.start_is_do_read_c_triggered_#res_7|)) InVars {ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13} OutVars{ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_11, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_7|, ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_7|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13} AuxVars[] AssignedVars[ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_immediate_notify_threads_#t~ret1, ULTIMATE.start_is_do_read_c_triggered_#res] 10285#L82 [369] L82-->L82-2: Formula: (= v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_5 0) InVars {ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_5} OutVars{ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_5} AuxVars[] AssignedVars[] 10190#L82-2 [366] L82-2-->L107-1: Formula: (= v_~q_write_ev~0_6 2) InVars {} OutVars{~q_write_ev~0=v_~q_write_ev~0_6} AuxVars[] AssignedVars[~q_write_ev~0] 10191#L107-1 [375] L107-1-->L108: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 10261#L108 [408] L108-->L247: Formula: (and (= v_~q_free~0_3 0) (= v_~p_dw_pc~0_7 1) (= v_~p_dw_st~0_10 2)) InVars {~q_free~0=v_~q_free~0_3} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_7, ~q_free~0=v_~q_free~0_3, ~p_dw_st~0=v_~p_dw_st~0_10} AuxVars[] AssignedVars[~p_dw_st~0, ~p_dw_pc~0] 10280#L247 [473] L247-->L262: Formula: (< 0 v_~c_dr_st~0_2) InVars {~c_dr_st~0=v_~c_dr_st~0_2} OutVars{~c_dr_st~0=v_~c_dr_st~0_2} AuxVars[] AssignedVars[] 10274#L262 [522] L262-->L214: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 10275#L214 [460] L214-->L218: Formula: (> v_~p_dw_st~0_7 0) InVars {~p_dw_st~0=v_~p_dw_st~0_7} OutVars{~p_dw_st~0=v_~p_dw_st~0_7} AuxVars[] AssignedVars[] 10269#L218 [464] L218-->L226: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_13 0) (> 0 v_~c_dr_st~0_8)) InVars {~c_dr_st~0=v_~c_dr_st~0_8} OutVars{~c_dr_st~0=v_~c_dr_st~0_8, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_13} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 10270#L226 [523] L226-->L242: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___1~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_5|, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp___1~0] 10265#L242 [524] L242-->L214-1: Formula: (= v_ULTIMATE.start_eval_~tmp___1~0_8 0) InVars {ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_17, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_7, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_stop_simulation_#t~ret6=|v_ULTIMATE.start_stop_simulation_#t~ret6_4|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_4|, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret6, ULTIMATE.start_stop_simulation_#res] 10209#L214-1 [458] L214-1-->L218-1: Formula: (> v_~p_dw_st~0_5 0) InVars {~p_dw_st~0=v_~p_dw_st~0_5} OutVars{~p_dw_st~0=v_~p_dw_st~0_5} AuxVars[] AssignedVars[] 10210#L218-1 [461] L218-1-->L226-1: Formula: (and (< 0 v_~c_dr_st~0_6) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_6 0)) InVars {~c_dr_st~0=v_~c_dr_st~0_6} OutVars{~c_dr_st~0=v_~c_dr_st~0_6, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_6} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 10246#L226-1 [525] L226-1-->L292: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18 |v_ULTIMATE.start_exists_runnable_thread_#res_10|) (= v_ULTIMATE.start_stop_simulation_~tmp~2_8 |v_ULTIMATE.start_exists_runnable_thread_#res_10|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_8, ULTIMATE.start_stop_simulation_#t~ret6=|v_ULTIMATE.start_stop_simulation_#t~ret6_5|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret6] 10244#L292 [465] L292-->L299: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_4 0) (< 0 v_ULTIMATE.start_stop_simulation_~tmp~2_5)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_4, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 10240#L299 [534] L299-->L313-1: Formula: (and (= 0 v_ULTIMATE.start_start_simulation_~tmp~3_9) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_9 |v_ULTIMATE.start_stop_simulation_#res_6|) (= |v_ULTIMATE.start_stop_simulation_#res_6| v_ULTIMATE.start_start_simulation_~tmp~3_9)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_9} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_6|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_~tmp~3] 10236#L313-1 [521] L313-1-->L262: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_8 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_8, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_4|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_6, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_6, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp~1, ULTIMATE.start_eval_~tmp___0~1, ULTIMATE.start_eval_~tmp___1~0] 10237#L262 [522] L262-->L214: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 10456#L214 [460] L214-->L218: Formula: (> v_~p_dw_st~0_7 0) InVars {~p_dw_st~0=v_~p_dw_st~0_7} OutVars{~p_dw_st~0=v_~p_dw_st~0_7} AuxVars[] AssignedVars[] 10453#L218 [385] L218-->L226: Formula: (and (= 0 v_~c_dr_st~0_7) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_12 1)) InVars {~c_dr_st~0=v_~c_dr_st~0_7} OutVars{~c_dr_st~0=v_~c_dr_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_12} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 10451#L226 [523] L226-->L242: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___1~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_5|, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp___1~0] 10449#L242 [468] L242-->L242-1: Formula: (> v_ULTIMATE.start_eval_~tmp___1~0_4 0) InVars {ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} OutVars{ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} AuxVars[] AssignedVars[] 10446#L242-1 [469] L242-1-->L247: Formula: (> v_~p_dw_st~0_12 0) InVars {~p_dw_st~0=v_~p_dw_st~0_12} OutVars{~p_dw_st~0=v_~p_dw_st~0_12} AuxVars[] AssignedVars[] 10443#L247 [410] L247-->L266: Formula: (and (= 0 v_~c_dr_st~0_10) (= v_ULTIMATE.start_eval_~tmp___0~1_4 |v_ULTIMATE.start_eval_#t~nondet5_3|)) InVars {~c_dr_st~0=v_~c_dr_st~0_10, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_3|} OutVars{~c_dr_st~0=v_~c_dr_st~0_10, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_4, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_2|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp___0~1] 10441#L266 [480] L266-->L139: Formula: (and (= v_~c_dr_st~0_11 1) (> v_ULTIMATE.start_eval_~tmp___0~1_5 0)) InVars {ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_5} OutVars{~c_dr_st~0=v_~c_dr_st~0_11, ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_1, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_5} AuxVars[] AssignedVars[~c_dr_st~0, ULTIMATE.start_do_read_c_~a~0] 10438#L139 [483] L139-->L142: Formula: (< 0 v_~c_dr_pc~0_6) InVars {~c_dr_pc~0=v_~c_dr_pc~0_6} OutVars{~c_dr_pc~0=v_~c_dr_pc~0_6} AuxVars[] AssignedVars[] 10435#L142 [526] L142-->L152-1: Formula: (and (= v_~c_dr_pc~0_15 1) (= v_ULTIMATE.start_do_read_c_~a~0_6 v_~a_t~0_6)) InVars {~c_dr_pc~0=v_~c_dr_pc~0_15, ~a_t~0=v_~a_t~0_6} OutVars{ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_6, ~c_dr_pc~0=v_~c_dr_pc~0_15, ~a_t~0=v_~a_t~0_6} AuxVars[] AssignedVars[ULTIMATE.start_do_read_c_~a~0] 10432#L152-1 [412] L152-1-->L32-3: Formula: (and (= v_~c_num_read~0_3 (+ v_~c_num_read~0_4 1)) (= v_~q_read_ev~0_5 1) (= v_ULTIMATE.start_do_read_c_~a~0_5 v_~q_buf_0~0_3) (= v_~c_last_read~0_2 v_ULTIMATE.start_do_read_c_~a~0_5) (= v_~q_free~0_8 1)) InVars {~c_num_read~0=v_~c_num_read~0_4, ~q_buf_0~0=v_~q_buf_0~0_3} OutVars{~c_num_read~0=v_~c_num_read~0_3, ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_6, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_6, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_4|, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_4|, ~c_last_read~0=v_~c_last_read~0_2, ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_5, ~q_free~0=v_~q_free~0_8, ~q_buf_0~0=v_~q_buf_0~0_3, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_4|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_6, ~q_read_ev~0=v_~q_read_ev~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0, ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret1, ~c_last_read~0, ULTIMATE.start_do_read_c_~a~0, ~c_num_read~0, ~q_free~0, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0, ~q_read_ev~0] 10429#L32-3 [495] L32-3-->L32-5: Formula: (< v_~p_dw_pc~0_11 1) InVars {~p_dw_pc~0=v_~p_dw_pc~0_11} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_11} AuxVars[] AssignedVars[] 10428#L32-5 [392] L32-5-->L43-1: Formula: (= v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_9 0) InVars {} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_9} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0] 10426#L43-1 [531] L43-1-->L74-3: Formula: (and (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_8| v_ULTIMATE.start_immediate_notify_threads_~tmp~0_12) (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_8| v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_12)) InVars {ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_12} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_12, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_8|, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_8|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_12} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 10376#L74-3 [503] L74-3-->L74-5: Formula: (and (> v_ULTIMATE.start_immediate_notify_threads_~tmp~0_9 0) (= v_~p_dw_st~0_13 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_9} OutVars{~p_dw_st~0=v_~p_dw_st~0_13, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_9} AuxVars[] AssignedVars[~p_dw_st~0] 10372#L74-5 [332] L74-5-->L51-3: Formula: true InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_4|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_7} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_#res, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 10370#L51-3 [507] L51-3-->L51-5: Formula: (> v_~c_dr_pc~0_11 1) InVars {~c_dr_pc~0=v_~c_dr_pc~0_11} OutVars{~c_dr_pc~0=v_~c_dr_pc~0_11} AuxVars[] AssignedVars[] 10368#L51-5 [327] L51-5-->L62-1: Formula: (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 10504#L62-1 [533] L62-1-->L82-3: Formula: (and (= v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_12 |v_ULTIMATE.start_is_do_read_c_triggered_#res_8|) (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_14 |v_ULTIMATE.start_is_do_read_c_triggered_#res_8|)) InVars {ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_14} OutVars{ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_12, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_8|, ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_8|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_14} AuxVars[] AssignedVars[ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_immediate_notify_threads_#t~ret1, ULTIMATE.start_is_do_read_c_triggered_#res] 10361#L82-3 [513] L82-3-->L82-5: Formula: (and (< v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_9 0) (= v_~c_dr_st~0_13 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_9} OutVars{~c_dr_st~0=v_~c_dr_st~0_13, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_9} AuxVars[] AssignedVars[~c_dr_st~0] 10358#L82-5 [536] L82-5-->L10-2: Formula: (and (= v_~p_num_write~0_10 v_~c_num_read~0_10) (= 2 v_~q_read_ev~0_13) (= v_~c_last_read~0_8 v_~p_last_write~0_8)) InVars {~p_last_write~0=v_~p_last_write~0_8, ~c_last_read~0=v_~c_last_read~0_8, ~c_num_read~0=v_~c_num_read~0_10, ~p_num_write~0=v_~p_num_write~0_10} OutVars{~p_last_write~0=v_~p_last_write~0_8, ~c_last_read~0=v_~c_last_read~0_8, ~c_num_read~0=v_~c_num_read~0_10, ~p_num_write~0=v_~p_num_write~0_10, ~q_read_ev~0=v_~q_read_ev~0_13} AuxVars[] AssignedVars[~q_read_ev~0] 10356#L10-2 [400] L10-2-->L151: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 10352#L151 [380] L151-->L262: Formula: (and (= v_~c_dr_st~0_12 2) (= v_~c_dr_pc~0_9 1) (= v_~a_t~0_2 v_ULTIMATE.start_do_read_c_~a~0_3) (= v_~q_free~0_6 1)) InVars {ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_3, ~q_free~0=v_~q_free~0_6} OutVars{ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_3, ~c_dr_pc~0=v_~c_dr_pc~0_9, ~c_dr_st~0=v_~c_dr_st~0_12, ~q_free~0=v_~q_free~0_6, ~a_t~0=v_~a_t~0_2} AuxVars[] AssignedVars[~c_dr_pc~0, ~c_dr_st~0, ~a_t~0] 10351#L262 37.10/18.54 [2019-03-28 12:18:44,459 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.54 [2019-03-28 12:18:44,459 INFO L82 PathProgramCache]: Analyzing trace with hash 16831196, now seen corresponding path program 1 times 37.10/18.54 [2019-03-28 12:18:44,459 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.54 [2019-03-28 12:18:44,459 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.54 [2019-03-28 12:18:44,460 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:44,460 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:44,460 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:44,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 37.10/18.54 [2019-03-28 12:18:44,477 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 37.10/18.54 [2019-03-28 12:18:44,478 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 37.10/18.54 [2019-03-28 12:18:44,478 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 37.10/18.54 [2019-03-28 12:18:44,478 INFO L799 eck$LassoCheckResult]: stem already infeasible 37.10/18.54 [2019-03-28 12:18:44,478 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.54 [2019-03-28 12:18:44,479 INFO L82 PathProgramCache]: Analyzing trace with hash 52686313, now seen corresponding path program 1 times 37.10/18.54 [2019-03-28 12:18:44,479 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.54 [2019-03-28 12:18:44,479 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.54 [2019-03-28 12:18:44,480 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:44,480 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:44,480 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:44,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 37.10/18.54 [2019-03-28 12:18:44,498 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. 37.10/18.54 [2019-03-28 12:18:44,499 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 37.10/18.54 [2019-03-28 12:18:44,499 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 37.10/18.54 [2019-03-28 12:18:44,499 INFO L811 eck$LassoCheckResult]: loop already infeasible 37.10/18.54 [2019-03-28 12:18:44,499 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 37.10/18.54 [2019-03-28 12:18:44,499 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 37.10/18.54 [2019-03-28 12:18:44,500 INFO L87 Difference]: Start difference. First operand 401 states and 673 transitions. cyclomatic complexity: 274 Second operand 3 states. 37.10/18.54 [2019-03-28 12:18:44,651 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 37.10/18.54 [2019-03-28 12:18:44,651 INFO L93 Difference]: Finished difference Result 401 states and 672 transitions. 37.10/18.54 [2019-03-28 12:18:44,651 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 37.10/18.54 [2019-03-28 12:18:44,657 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 401 states and 672 transitions. 37.10/18.54 [2019-03-28 12:18:44,661 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 383 37.10/18.54 [2019-03-28 12:18:44,664 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 401 states to 401 states and 672 transitions. 37.10/18.54 [2019-03-28 12:18:44,664 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 351 37.10/18.54 [2019-03-28 12:18:44,665 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 351 37.10/18.54 [2019-03-28 12:18:44,665 INFO L73 IsDeterministic]: Start isDeterministic. Operand 401 states and 672 transitions. 37.10/18.54 [2019-03-28 12:18:44,665 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. 37.10/18.54 [2019-03-28 12:18:44,665 INFO L706 BuchiCegarLoop]: Abstraction has 401 states and 672 transitions. 37.10/18.54 [2019-03-28 12:18:44,666 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 401 states and 672 transitions. 37.10/18.54 [2019-03-28 12:18:44,672 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 401 to 401. 37.10/18.54 [2019-03-28 12:18:44,673 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 401 states. 37.10/18.54 [2019-03-28 12:18:44,674 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 401 states to 401 states and 672 transitions. 37.10/18.54 [2019-03-28 12:18:44,675 INFO L729 BuchiCegarLoop]: Abstraction has 401 states and 672 transitions. 37.10/18.54 [2019-03-28 12:18:44,675 INFO L609 BuchiCegarLoop]: Abstraction has 401 states and 672 transitions. 37.10/18.54 [2019-03-28 12:18:44,675 INFO L442 BuchiCegarLoop]: ======== Iteration 12============ 37.10/18.54 [2019-03-28 12:18:44,675 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 401 states and 672 transitions. 37.10/18.54 [2019-03-28 12:18:44,677 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 383 37.10/18.54 [2019-03-28 12:18:44,677 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 37.10/18.54 [2019-03-28 12:18:44,678 INFO L119 BuchiIsEmpty]: Starting construction of run 37.10/18.54 [2019-03-28 12:18:44,678 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1] 37.10/18.54 [2019-03-28 12:18:44,678 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 37.10/18.54 [2019-03-28 12:18:44,679 INFO L794 eck$LassoCheckResult]: Stem: 10992#ULTIMATE.startENTRY [520] ULTIMATE.startENTRY-->L196: Formula: (and (= v_~q_write_ev~0_11 v_~q_read_ev~0_11) (= 1 v_~c_dr_i~0_7) (= v_~q_free~0_11 1) (= v_~q_buf_0~0_5 0) (= v_~q_write_ev~0_11 2) (= 0 v_~p_last_write~0_6) (= 0 v_~c_last_read~0_6) (= v_~p_dw_pc~0_14 0) (= 0 v_~a_t~0_5) (= 0 v_~c_dr_st~0_15) (= v_~c_dr_pc~0_14 0) (= 0 v_~c_num_read~0_9) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 0) (= 0 v_~p_num_write~0_9) (= v_~p_dw_i~0_7 1) (= v_~p_dw_st~0_15 0)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ~p_last_write~0=v_~p_last_write~0_6, ~c_dr_pc~0=v_~c_dr_pc~0_14, ~c_dr_st~0=v_~c_dr_st~0_15, ~c_num_read~0=v_~c_num_read~0_9, ~p_num_write~0=v_~p_num_write~0_9, ~c_dr_i~0=v_~c_dr_i~0_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7, ~q_write_ev~0=v_~q_write_ev~0_11, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~p_dw_st~0=v_~p_dw_st~0_15, ~p_dw_i~0=v_~p_dw_i~0_7, ~c_last_read~0=v_~c_last_read~0_6, ~p_dw_pc~0=v_~p_dw_pc~0_14, ~q_free~0=v_~q_free~0_11, ~q_buf_0~0=v_~q_buf_0~0_5, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6, ~q_read_ev~0=v_~q_read_ev~0_11, ~a_t~0=v_~a_t~0_5} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ~p_last_write~0, ~c_dr_pc~0, ~c_dr_st~0, ~c_num_read~0, ~p_num_write~0, ~c_dr_i~0, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_~kernel_st~0, ~q_write_ev~0, ULTIMATE.start_main_#res, ~p_dw_st~0, ~p_dw_i~0, ~c_last_read~0, ~p_dw_pc~0, ~q_free~0, ~q_buf_0~0, ULTIMATE.start_main_~__retres1~3, ~q_read_ev~0, ~a_t~0] 10993#L196 [418] L196-->L196-2: Formula: (and (= v_~p_dw_i~0_3 1) (= v_~p_dw_st~0_2 0)) InVars {~p_dw_i~0=v_~p_dw_i~0_3} OutVars{~p_dw_st~0=v_~p_dw_st~0_2, ~p_dw_i~0=v_~p_dw_i~0_3} AuxVars[] AssignedVars[~p_dw_st~0] 11028#L196-2 [455] L196-2-->L313-1: Formula: (and (= v_~c_dr_st~0_4 2) (> 1 v_~c_dr_i~0_4)) InVars {~c_dr_i~0=v_~c_dr_i~0_4} OutVars{~c_dr_st~0=v_~c_dr_st~0_4, ~c_dr_i~0=v_~c_dr_i~0_4} AuxVars[] AssignedVars[~c_dr_st~0] 11029#L313-1 [521] L313-1-->L262: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_8 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_8, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_4|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_6, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_6, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp~1, ULTIMATE.start_eval_~tmp___0~1, ULTIMATE.start_eval_~tmp___1~0] 11172#L262 37.10/18.54 [2019-03-28 12:18:44,680 INFO L796 eck$LassoCheckResult]: Loop: 11172#L262 [522] L262-->L214: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 11171#L214 [406] L214-->L226: Formula: (and (= v_~p_dw_st~0_6 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11 1)) InVars {~p_dw_st~0=v_~p_dw_st~0_6} OutVars{~p_dw_st~0=v_~p_dw_st~0_6, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 11170#L226 [523] L226-->L242: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___1~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_5|, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp___1~0] 11169#L242 [468] L242-->L242-1: Formula: (> v_ULTIMATE.start_eval_~tmp___1~0_4 0) InVars {ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} OutVars{ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} AuxVars[] AssignedVars[] 11168#L242-1 [333] L242-1-->L251: Formula: (and (= v_ULTIMATE.start_eval_~tmp~1_3 |v_ULTIMATE.start_eval_#t~nondet4_3|) (= v_~p_dw_st~0_8 0)) InVars {ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_3|, ~p_dw_st~0=v_~p_dw_st~0_8} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_2|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_3, ~p_dw_st~0=v_~p_dw_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_~tmp~1] 11166#L251 [471] L251-->L96: Formula: (and (= v_~p_dw_st~0_9 1) (< v_ULTIMATE.start_eval_~tmp~1_4 0)) InVars {ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_4} OutVars{ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_4, ~p_dw_st~0=v_~p_dw_st~0_9, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_1|} AuxVars[] AssignedVars[~p_dw_st~0, ULTIMATE.start_do_write_p_#t~nondet2] 11136#L96 [378] L96-->L107-1: Formula: (= v_~p_dw_pc~0_3 0) InVars {~p_dw_pc~0=v_~p_dw_pc~0_3} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_3} AuxVars[] AssignedVars[] 10999#L107-1 [375] L107-1-->L108: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 11003#L108 [486] L108-->L109: Formula: (> v_~q_free~0_4 0) InVars {~q_free~0=v_~q_free~0_4} OutVars{~q_free~0=v_~q_free~0_4} AuxVars[] AssignedVars[] 10972#L109 [323] L109-->L32: Formula: (and (= v_~q_buf_0~0_2 |v_ULTIMATE.start_do_write_p_#t~nondet2_3|) (= v_~p_last_write~0_2 v_~q_buf_0~0_2) (= v_~q_write_ev~0_3 1) (= v_~p_num_write~0_3 (+ v_~p_num_write~0_4 1)) (= v_~q_free~0_5 0)) InVars {~p_num_write~0=v_~p_num_write~0_4, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_3|} OutVars{~p_last_write~0=v_~p_last_write~0_2, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_2|, ~p_num_write~0=v_~p_num_write~0_3, ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_1, ~q_write_ev~0=v_~q_write_ev~0_3, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_1, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_1|, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_1|, ~q_free~0=v_~q_free~0_5, ~q_buf_0~0=v_~q_buf_0~0_2, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_1|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_1} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0, ~q_write_ev~0, ~p_last_write~0, ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_do_write_p_#t~nondet2, ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret1, ~p_num_write~0, ~q_free~0, ~q_buf_0~0, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 10955#L32 [489] L32-->L32-2: Formula: (< v_~p_dw_pc~0_9 1) InVars {~p_dw_pc~0=v_~p_dw_pc~0_9} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_9} AuxVars[] AssignedVars[] 10956#L32-2 [403] L32-2-->L43: Formula: (= v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_4 0) InVars {} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_4} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0] 10958#L43 [528] L43-->L74: Formula: (and (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_7| v_ULTIMATE.start_immediate_notify_threads_~tmp~0_11) (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_7| v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11)) InVars {ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_7|, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_7|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 10959#L74 [499] L74-->L74-2: Formula: (and (> v_ULTIMATE.start_immediate_notify_threads_~tmp~0_4 0) (= v_~p_dw_st~0_11 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_4} OutVars{~p_dw_st~0=v_~p_dw_st~0_11, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_4} AuxVars[] AssignedVars[~p_dw_st~0] 11004#L74-2 [339] L74-2-->L51: Formula: true InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_1|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_1} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_#res, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 11085#L51 [501] L51-->L51-2: Formula: (< 1 v_~c_dr_pc~0_4) InVars {~c_dr_pc~0=v_~c_dr_pc~0_4} OutVars{~c_dr_pc~0=v_~c_dr_pc~0_4} AuxVars[] AssignedVars[] 11079#L51-2 [307] L51-2-->L62: Formula: (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 11080#L62 [532] L62-->L82: Formula: (and (= v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_11 |v_ULTIMATE.start_is_do_read_c_triggered_#res_7|) (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13 |v_ULTIMATE.start_is_do_read_c_triggered_#res_7|)) InVars {ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13} OutVars{ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_11, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_7|, ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_7|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13} AuxVars[] AssignedVars[ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_immediate_notify_threads_#t~ret1, ULTIMATE.start_is_do_read_c_triggered_#res] 11076#L82 [369] L82-->L82-2: Formula: (= v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_5 0) InVars {ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_5} OutVars{ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_5} AuxVars[] AssignedVars[] 11075#L82-2 [366] L82-2-->L107-1: Formula: (= v_~q_write_ev~0_6 2) InVars {} OutVars{~q_write_ev~0=v_~q_write_ev~0_6} AuxVars[] AssignedVars[~q_write_ev~0] 11074#L107-1 [375] L107-1-->L108: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 11072#L108 [408] L108-->L247: Formula: (and (= v_~q_free~0_3 0) (= v_~p_dw_pc~0_7 1) (= v_~p_dw_st~0_10 2)) InVars {~q_free~0=v_~q_free~0_3} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_7, ~q_free~0=v_~q_free~0_3, ~p_dw_st~0=v_~p_dw_st~0_10} AuxVars[] AssignedVars[~p_dw_st~0, ~p_dw_pc~0] 11073#L247 [473] L247-->L262: Formula: (< 0 v_~c_dr_st~0_2) InVars {~c_dr_st~0=v_~c_dr_st~0_2} OutVars{~c_dr_st~0=v_~c_dr_st~0_2} AuxVars[] AssignedVars[] 11257#L262 [522] L262-->L214: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 11256#L214 [460] L214-->L218: Formula: (> v_~p_dw_st~0_7 0) InVars {~p_dw_st~0=v_~p_dw_st~0_7} OutVars{~p_dw_st~0=v_~p_dw_st~0_7} AuxVars[] AssignedVars[] 11254#L218 [464] L218-->L226: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_13 0) (> 0 v_~c_dr_st~0_8)) InVars {~c_dr_st~0=v_~c_dr_st~0_8} OutVars{~c_dr_st~0=v_~c_dr_st~0_8, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_13} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 11253#L226 [523] L226-->L242: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___1~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_5|, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp___1~0] 11251#L242 [524] L242-->L214-1: Formula: (= v_ULTIMATE.start_eval_~tmp___1~0_8 0) InVars {ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_17, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_7, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_stop_simulation_#t~ret6=|v_ULTIMATE.start_stop_simulation_#t~ret6_4|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_4|, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret6, ULTIMATE.start_stop_simulation_#res] 11250#L214-1 [458] L214-1-->L218-1: Formula: (> v_~p_dw_st~0_5 0) InVars {~p_dw_st~0=v_~p_dw_st~0_5} OutVars{~p_dw_st~0=v_~p_dw_st~0_5} AuxVars[] AssignedVars[] 11249#L218-1 [461] L218-1-->L226-1: Formula: (and (< 0 v_~c_dr_st~0_6) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_6 0)) InVars {~c_dr_st~0=v_~c_dr_st~0_6} OutVars{~c_dr_st~0=v_~c_dr_st~0_6, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_6} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 11248#L226-1 [525] L226-1-->L292: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18 |v_ULTIMATE.start_exists_runnable_thread_#res_10|) (= v_ULTIMATE.start_stop_simulation_~tmp~2_8 |v_ULTIMATE.start_exists_runnable_thread_#res_10|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_8, ULTIMATE.start_stop_simulation_#t~ret6=|v_ULTIMATE.start_stop_simulation_#t~ret6_5|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret6] 11247#L292 [465] L292-->L299: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_4 0) (< 0 v_ULTIMATE.start_stop_simulation_~tmp~2_5)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_4, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 11246#L299 [534] L299-->L313-1: Formula: (and (= 0 v_ULTIMATE.start_start_simulation_~tmp~3_9) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_9 |v_ULTIMATE.start_stop_simulation_#res_6|) (= |v_ULTIMATE.start_stop_simulation_#res_6| v_ULTIMATE.start_start_simulation_~tmp~3_9)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_9} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_6|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_~tmp~3] 11042#L313-1 [521] L313-1-->L262: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_8 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_8, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_4|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_6, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_6, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp~1, ULTIMATE.start_eval_~tmp___0~1, ULTIMATE.start_eval_~tmp___1~0] 11039#L262 [522] L262-->L214: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 11040#L214 [460] L214-->L218: Formula: (> v_~p_dw_st~0_7 0) InVars {~p_dw_st~0=v_~p_dw_st~0_7} OutVars{~p_dw_st~0=v_~p_dw_st~0_7} AuxVars[] AssignedVars[] 11312#L218 [464] L218-->L226: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_13 0) (> 0 v_~c_dr_st~0_8)) InVars {~c_dr_st~0=v_~c_dr_st~0_8} OutVars{~c_dr_st~0=v_~c_dr_st~0_8, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_13} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 11310#L226 [523] L226-->L242: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___1~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_5|, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp___1~0] 11307#L242 [467] L242-->L242-1: Formula: (< v_ULTIMATE.start_eval_~tmp___1~0_4 0) InVars {ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} OutVars{ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} AuxVars[] AssignedVars[] 11290#L242-1 [469] L242-1-->L247: Formula: (> v_~p_dw_st~0_12 0) InVars {~p_dw_st~0=v_~p_dw_st~0_12} OutVars{~p_dw_st~0=v_~p_dw_st~0_12} AuxVars[] AssignedVars[] 11291#L247 [410] L247-->L266: Formula: (and (= 0 v_~c_dr_st~0_10) (= v_ULTIMATE.start_eval_~tmp___0~1_4 |v_ULTIMATE.start_eval_#t~nondet5_3|)) InVars {~c_dr_st~0=v_~c_dr_st~0_10, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_3|} OutVars{~c_dr_st~0=v_~c_dr_st~0_10, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_4, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_2|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp___0~1] 11216#L266 [480] L266-->L139: Formula: (and (= v_~c_dr_st~0_11 1) (> v_ULTIMATE.start_eval_~tmp___0~1_5 0)) InVars {ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_5} OutVars{~c_dr_st~0=v_~c_dr_st~0_11, ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_1, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_5} AuxVars[] AssignedVars[~c_dr_st~0, ULTIMATE.start_do_read_c_~a~0] 11212#L139 [483] L139-->L142: Formula: (< 0 v_~c_dr_pc~0_6) InVars {~c_dr_pc~0=v_~c_dr_pc~0_6} OutVars{~c_dr_pc~0=v_~c_dr_pc~0_6} AuxVars[] AssignedVars[] 11208#L142 [526] L142-->L152-1: Formula: (and (= v_~c_dr_pc~0_15 1) (= v_ULTIMATE.start_do_read_c_~a~0_6 v_~a_t~0_6)) InVars {~c_dr_pc~0=v_~c_dr_pc~0_15, ~a_t~0=v_~a_t~0_6} OutVars{ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_6, ~c_dr_pc~0=v_~c_dr_pc~0_15, ~a_t~0=v_~a_t~0_6} AuxVars[] AssignedVars[ULTIMATE.start_do_read_c_~a~0] 11202#L152-1 [412] L152-1-->L32-3: Formula: (and (= v_~c_num_read~0_3 (+ v_~c_num_read~0_4 1)) (= v_~q_read_ev~0_5 1) (= v_ULTIMATE.start_do_read_c_~a~0_5 v_~q_buf_0~0_3) (= v_~c_last_read~0_2 v_ULTIMATE.start_do_read_c_~a~0_5) (= v_~q_free~0_8 1)) InVars {~c_num_read~0=v_~c_num_read~0_4, ~q_buf_0~0=v_~q_buf_0~0_3} OutVars{~c_num_read~0=v_~c_num_read~0_3, ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_6, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_6, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_4|, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_4|, ~c_last_read~0=v_~c_last_read~0_2, ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_5, ~q_free~0=v_~q_free~0_8, ~q_buf_0~0=v_~q_buf_0~0_3, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_4|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_6, ~q_read_ev~0=v_~q_read_ev~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0, ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret1, ~c_last_read~0, ULTIMATE.start_do_read_c_~a~0, ~c_num_read~0, ~q_free~0, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0, ~q_read_ev~0] 11199#L32-3 [495] L32-3-->L32-5: Formula: (< v_~p_dw_pc~0_11 1) InVars {~p_dw_pc~0=v_~p_dw_pc~0_11} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_11} AuxVars[] AssignedVars[] 11196#L32-5 [392] L32-5-->L43-1: Formula: (= v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_9 0) InVars {} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_9} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0] 11194#L43-1 [531] L43-1-->L74-3: Formula: (and (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_8| v_ULTIMATE.start_immediate_notify_threads_~tmp~0_12) (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_8| v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_12)) InVars {ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_12} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_12, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_8|, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_8|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_12} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 11191#L74-3 [503] L74-3-->L74-5: Formula: (and (> v_ULTIMATE.start_immediate_notify_threads_~tmp~0_9 0) (= v_~p_dw_st~0_13 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_9} OutVars{~p_dw_st~0=v_~p_dw_st~0_13, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_9} AuxVars[] AssignedVars[~p_dw_st~0] 11187#L74-5 [332] L74-5-->L51-3: Formula: true InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_4|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_7} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_#res, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 11185#L51-3 [507] L51-3-->L51-5: Formula: (> v_~c_dr_pc~0_11 1) InVars {~c_dr_pc~0=v_~c_dr_pc~0_11} OutVars{~c_dr_pc~0=v_~c_dr_pc~0_11} AuxVars[] AssignedVars[] 10975#L51-5 [327] L51-5-->L62-1: Formula: (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 10976#L62-1 [533] L62-1-->L82-3: Formula: (and (= v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_12 |v_ULTIMATE.start_is_do_read_c_triggered_#res_8|) (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_14 |v_ULTIMATE.start_is_do_read_c_triggered_#res_8|)) InVars {ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_14} OutVars{ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_12, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_8|, ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_8|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_14} AuxVars[] AssignedVars[ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_immediate_notify_threads_#t~ret1, ULTIMATE.start_is_do_read_c_triggered_#res] 11178#L82-3 [513] L82-3-->L82-5: Formula: (and (< v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_9 0) (= v_~c_dr_st~0_13 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_9} OutVars{~c_dr_st~0=v_~c_dr_st~0_13, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_9} AuxVars[] AssignedVars[~c_dr_st~0] 11176#L82-5 [536] L82-5-->L10-2: Formula: (and (= v_~p_num_write~0_10 v_~c_num_read~0_10) (= 2 v_~q_read_ev~0_13) (= v_~c_last_read~0_8 v_~p_last_write~0_8)) InVars {~p_last_write~0=v_~p_last_write~0_8, ~c_last_read~0=v_~c_last_read~0_8, ~c_num_read~0=v_~c_num_read~0_10, ~p_num_write~0=v_~p_num_write~0_10} OutVars{~p_last_write~0=v_~p_last_write~0_8, ~c_last_read~0=v_~c_last_read~0_8, ~c_num_read~0=v_~c_num_read~0_10, ~p_num_write~0=v_~p_num_write~0_10, ~q_read_ev~0=v_~q_read_ev~0_13} AuxVars[] AssignedVars[~q_read_ev~0] 11175#L10-2 [400] L10-2-->L151: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 11173#L151 [380] L151-->L262: Formula: (and (= v_~c_dr_st~0_12 2) (= v_~c_dr_pc~0_9 1) (= v_~a_t~0_2 v_ULTIMATE.start_do_read_c_~a~0_3) (= v_~q_free~0_6 1)) InVars {ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_3, ~q_free~0=v_~q_free~0_6} OutVars{ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_3, ~c_dr_pc~0=v_~c_dr_pc~0_9, ~c_dr_st~0=v_~c_dr_st~0_12, ~q_free~0=v_~q_free~0_6, ~a_t~0=v_~a_t~0_2} AuxVars[] AssignedVars[~c_dr_pc~0, ~c_dr_st~0, ~a_t~0] 11172#L262 37.10/18.54 [2019-03-28 12:18:44,680 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.54 [2019-03-28 12:18:44,680 INFO L82 PathProgramCache]: Analyzing trace with hash 16831165, now seen corresponding path program 1 times 37.10/18.54 [2019-03-28 12:18:44,681 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.54 [2019-03-28 12:18:44,681 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.54 [2019-03-28 12:18:44,682 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:44,682 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:44,682 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:44,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 37.10/18.54 [2019-03-28 12:18:44,700 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 37.10/18.54 [2019-03-28 12:18:44,700 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 37.10/18.54 [2019-03-28 12:18:44,701 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 37.10/18.54 [2019-03-28 12:18:44,701 INFO L799 eck$LassoCheckResult]: stem already infeasible 37.10/18.54 [2019-03-28 12:18:44,701 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.54 [2019-03-28 12:18:44,701 INFO L82 PathProgramCache]: Analyzing trace with hash 1862950801, now seen corresponding path program 1 times 37.10/18.54 [2019-03-28 12:18:44,701 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.54 [2019-03-28 12:18:44,702 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.54 [2019-03-28 12:18:44,702 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:44,703 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:44,703 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:44,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 37.10/18.54 [2019-03-28 12:18:44,730 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. 37.10/18.54 [2019-03-28 12:18:44,736 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 37.10/18.54 [2019-03-28 12:18:44,736 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 37.10/18.54 [2019-03-28 12:18:44,737 INFO L811 eck$LassoCheckResult]: loop already infeasible 37.10/18.54 [2019-03-28 12:18:44,737 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 37.10/18.54 [2019-03-28 12:18:44,737 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 37.10/18.54 [2019-03-28 12:18:44,737 INFO L87 Difference]: Start difference. First operand 401 states and 672 transitions. cyclomatic complexity: 273 Second operand 3 states. 37.10/18.54 [2019-03-28 12:18:44,804 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 37.10/18.54 [2019-03-28 12:18:44,804 INFO L93 Difference]: Finished difference Result 400 states and 670 transitions. 37.10/18.54 [2019-03-28 12:18:44,805 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 37.10/18.54 [2019-03-28 12:18:44,810 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 400 states and 670 transitions. 37.10/18.54 [2019-03-28 12:18:44,813 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 383 37.10/18.54 [2019-03-28 12:18:44,816 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 400 states to 400 states and 670 transitions. 37.10/18.54 [2019-03-28 12:18:44,817 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 350 37.10/18.54 [2019-03-28 12:18:44,817 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 350 37.10/18.54 [2019-03-28 12:18:44,817 INFO L73 IsDeterministic]: Start isDeterministic. Operand 400 states and 670 transitions. 37.10/18.54 [2019-03-28 12:18:44,818 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. 37.10/18.54 [2019-03-28 12:18:44,818 INFO L706 BuchiCegarLoop]: Abstraction has 400 states and 670 transitions. 37.10/18.54 [2019-03-28 12:18:44,818 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 400 states and 670 transitions. 37.10/18.54 [2019-03-28 12:18:44,825 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 400 to 400. 37.10/18.54 [2019-03-28 12:18:44,825 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 400 states. 37.10/18.54 [2019-03-28 12:18:44,827 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 400 states to 400 states and 670 transitions. 37.10/18.54 [2019-03-28 12:18:44,827 INFO L729 BuchiCegarLoop]: Abstraction has 400 states and 670 transitions. 37.10/18.54 [2019-03-28 12:18:44,827 INFO L609 BuchiCegarLoop]: Abstraction has 400 states and 670 transitions. 37.10/18.54 [2019-03-28 12:18:44,827 INFO L442 BuchiCegarLoop]: ======== Iteration 13============ 37.10/18.54 [2019-03-28 12:18:44,827 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 400 states and 670 transitions. 37.10/18.54 [2019-03-28 12:18:44,829 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 383 37.10/18.54 [2019-03-28 12:18:44,829 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 37.10/18.54 [2019-03-28 12:18:44,830 INFO L119 BuchiIsEmpty]: Starting construction of run 37.10/18.54 [2019-03-28 12:18:44,830 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 37.10/18.54 [2019-03-28 12:18:44,830 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 37.10/18.54 [2019-03-28 12:18:44,831 INFO L794 eck$LassoCheckResult]: Stem: 11795#ULTIMATE.startENTRY [520] ULTIMATE.startENTRY-->L196: Formula: (and (= v_~q_write_ev~0_11 v_~q_read_ev~0_11) (= 1 v_~c_dr_i~0_7) (= v_~q_free~0_11 1) (= v_~q_buf_0~0_5 0) (= v_~q_write_ev~0_11 2) (= 0 v_~p_last_write~0_6) (= 0 v_~c_last_read~0_6) (= v_~p_dw_pc~0_14 0) (= 0 v_~a_t~0_5) (= 0 v_~c_dr_st~0_15) (= v_~c_dr_pc~0_14 0) (= 0 v_~c_num_read~0_9) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 0) (= 0 v_~p_num_write~0_9) (= v_~p_dw_i~0_7 1) (= v_~p_dw_st~0_15 0)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ~p_last_write~0=v_~p_last_write~0_6, ~c_dr_pc~0=v_~c_dr_pc~0_14, ~c_dr_st~0=v_~c_dr_st~0_15, ~c_num_read~0=v_~c_num_read~0_9, ~p_num_write~0=v_~p_num_write~0_9, ~c_dr_i~0=v_~c_dr_i~0_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7, ~q_write_ev~0=v_~q_write_ev~0_11, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~p_dw_st~0=v_~p_dw_st~0_15, ~p_dw_i~0=v_~p_dw_i~0_7, ~c_last_read~0=v_~c_last_read~0_6, ~p_dw_pc~0=v_~p_dw_pc~0_14, ~q_free~0=v_~q_free~0_11, ~q_buf_0~0=v_~q_buf_0~0_5, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6, ~q_read_ev~0=v_~q_read_ev~0_11, ~a_t~0=v_~a_t~0_5} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ~p_last_write~0, ~c_dr_pc~0, ~c_dr_st~0, ~c_num_read~0, ~p_num_write~0, ~c_dr_i~0, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_~kernel_st~0, ~q_write_ev~0, ULTIMATE.start_main_#res, ~p_dw_st~0, ~p_dw_i~0, ~c_last_read~0, ~p_dw_pc~0, ~q_free~0, ~q_buf_0~0, ULTIMATE.start_main_~__retres1~3, ~q_read_ev~0, ~a_t~0] 11796#L196 [418] L196-->L196-2: Formula: (and (= v_~p_dw_i~0_3 1) (= v_~p_dw_st~0_2 0)) InVars {~p_dw_i~0=v_~p_dw_i~0_3} OutVars{~p_dw_st~0=v_~p_dw_st~0_2, ~p_dw_i~0=v_~p_dw_i~0_3} AuxVars[] AssignedVars[~p_dw_st~0] 11830#L196-2 [413] L196-2-->L313-1: Formula: (and (= 1 v_~c_dr_i~0_3) (= v_~c_dr_st~0_3 0)) InVars {~c_dr_i~0=v_~c_dr_i~0_3} OutVars{~c_dr_st~0=v_~c_dr_st~0_3, ~c_dr_i~0=v_~c_dr_i~0_3} AuxVars[] AssignedVars[~c_dr_st~0] 11831#L313-1 [521] L313-1-->L262: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_8 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_8, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_4|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_6, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_6, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp~1, ULTIMATE.start_eval_~tmp___0~1, ULTIMATE.start_eval_~tmp___1~0] 11920#L262 [522] L262-->L214: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 11918#L214 [406] L214-->L226: Formula: (and (= v_~p_dw_st~0_6 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11 1)) InVars {~p_dw_st~0=v_~p_dw_st~0_6} OutVars{~p_dw_st~0=v_~p_dw_st~0_6, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 11917#L226 [523] L226-->L242: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___1~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_5|, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp___1~0] 11916#L242 [468] L242-->L242-1: Formula: (> v_ULTIMATE.start_eval_~tmp___1~0_4 0) InVars {ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} OutVars{ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} AuxVars[] AssignedVars[] 11915#L242-1 [333] L242-1-->L251: Formula: (and (= v_ULTIMATE.start_eval_~tmp~1_3 |v_ULTIMATE.start_eval_#t~nondet4_3|) (= v_~p_dw_st~0_8 0)) InVars {ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_3|, ~p_dw_st~0=v_~p_dw_st~0_8} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_2|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_3, ~p_dw_st~0=v_~p_dw_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_~tmp~1] 11913#L251 [472] L251-->L96: Formula: (and (= v_~p_dw_st~0_9 1) (> v_ULTIMATE.start_eval_~tmp~1_4 0)) InVars {ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_4} OutVars{ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_4, ~p_dw_st~0=v_~p_dw_st~0_9, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_1|} AuxVars[] AssignedVars[~p_dw_st~0, ULTIMATE.start_do_write_p_#t~nondet2] 11910#L96 [477] L96-->L99: Formula: (< v_~p_dw_pc~0_4 0) InVars {~p_dw_pc~0=v_~p_dw_pc~0_4} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_4} AuxVars[] AssignedVars[] 11909#L99 [361] L99-->L109: Formula: (= v_~p_dw_pc~0_5 1) InVars {~p_dw_pc~0=v_~p_dw_pc~0_5} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_5} AuxVars[] AssignedVars[] 11896#L109 37.10/18.54 [2019-03-28 12:18:44,831 INFO L796 eck$LassoCheckResult]: Loop: 11896#L109 [323] L109-->L32: Formula: (and (= v_~q_buf_0~0_2 |v_ULTIMATE.start_do_write_p_#t~nondet2_3|) (= v_~p_last_write~0_2 v_~q_buf_0~0_2) (= v_~q_write_ev~0_3 1) (= v_~p_num_write~0_3 (+ v_~p_num_write~0_4 1)) (= v_~q_free~0_5 0)) InVars {~p_num_write~0=v_~p_num_write~0_4, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_3|} OutVars{~p_last_write~0=v_~p_last_write~0_2, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_2|, ~p_num_write~0=v_~p_num_write~0_3, ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_1, ~q_write_ev~0=v_~q_write_ev~0_3, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_1, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_1|, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_1|, ~q_free~0=v_~q_free~0_5, ~q_buf_0~0=v_~q_buf_0~0_2, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_1|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_1} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0, ~q_write_ev~0, ~p_last_write~0, ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_do_write_p_#t~nondet2, ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret1, ~p_num_write~0, ~q_free~0, ~q_buf_0~0, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 11892#L32 [316] L32-->L33: Formula: (= v_~p_dw_pc~0_8 1) InVars {~p_dw_pc~0=v_~p_dw_pc~0_8} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_8} AuxVars[] AssignedVars[] 11890#L33 [352] L33-->L43: Formula: (and (= v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_3 1) (= 1 v_~q_read_ev~0_3)) InVars {~q_read_ev~0=v_~q_read_ev~0_3} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_3, ~q_read_ev~0=v_~q_read_ev~0_3} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0] 11889#L43 [528] L43-->L74: Formula: (and (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_7| v_ULTIMATE.start_immediate_notify_threads_~tmp~0_11) (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_7| v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11)) InVars {ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_7|, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_7|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 11888#L74 [499] L74-->L74-2: Formula: (and (> v_ULTIMATE.start_immediate_notify_threads_~tmp~0_4 0) (= v_~p_dw_st~0_11 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_4} OutVars{~p_dw_st~0=v_~p_dw_st~0_11, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_4} AuxVars[] AssignedVars[~p_dw_st~0] 11793#L74-2 [339] L74-2-->L51: Formula: true InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_1|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_1} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_#res, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 11750#L51 [309] L51-->L52: Formula: (= 1 v_~c_dr_pc~0_3) InVars {~c_dr_pc~0=v_~c_dr_pc~0_3} OutVars{~c_dr_pc~0=v_~c_dr_pc~0_3} AuxVars[] AssignedVars[] 11751#L52 [343] L52-->L62: Formula: (and (= v_~q_write_ev~0_4 1) (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_4 1)) InVars {~q_write_ev~0=v_~q_write_ev~0_4} OutVars{~q_write_ev~0=v_~q_write_ev~0_4, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_4} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 11914#L62 [532] L62-->L82: Formula: (and (= v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_11 |v_ULTIMATE.start_is_do_read_c_triggered_#res_7|) (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13 |v_ULTIMATE.start_is_do_read_c_triggered_#res_7|)) InVars {ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13} OutVars{ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_11, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_7|, ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_7|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13} AuxVars[] AssignedVars[ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_immediate_notify_threads_#t~ret1, ULTIMATE.start_is_do_read_c_triggered_#res] 11911#L82 [512] L82-->L82-2: Formula: (and (> v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_4 0) (= v_~c_dr_st~0_9 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_4} OutVars{~c_dr_st~0=v_~c_dr_st~0_9, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_4} AuxVars[] AssignedVars[~c_dr_st~0] 11908#L82-2 [366] L82-2-->L107-1: Formula: (= v_~q_write_ev~0_6 2) InVars {} OutVars{~q_write_ev~0=v_~q_write_ev~0_6} AuxVars[] AssignedVars[~q_write_ev~0] 11906#L107-1 [375] L107-1-->L108: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 11898#L108 [485] L108-->L109: Formula: (< v_~q_free~0_4 0) InVars {~q_free~0=v_~q_free~0_4} OutVars{~q_free~0=v_~q_free~0_4} AuxVars[] AssignedVars[] 11896#L109 37.10/18.54 [2019-03-28 12:18:44,831 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.54 [2019-03-28 12:18:44,831 INFO L82 PathProgramCache]: Analyzing trace with hash -743982669, now seen corresponding path program 1 times 37.10/18.54 [2019-03-28 12:18:44,832 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.54 [2019-03-28 12:18:44,832 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.54 [2019-03-28 12:18:44,832 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:44,833 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:44,833 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:44,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 37.10/18.54 [2019-03-28 12:18:44,846 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 37.10/18.54 [2019-03-28 12:18:44,846 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 37.10/18.54 [2019-03-28 12:18:44,847 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 37.10/18.54 [2019-03-28 12:18:44,847 INFO L799 eck$LassoCheckResult]: stem already infeasible 37.10/18.54 [2019-03-28 12:18:44,847 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.54 [2019-03-28 12:18:44,847 INFO L82 PathProgramCache]: Analyzing trace with hash -1268520700, now seen corresponding path program 1 times 37.10/18.54 [2019-03-28 12:18:44,847 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.54 [2019-03-28 12:18:44,847 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.54 [2019-03-28 12:18:44,848 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:44,848 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:44,849 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:44,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 37.10/18.54 [2019-03-28 12:18:44,862 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 37.10/18.54 [2019-03-28 12:18:44,862 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 37.10/18.54 [2019-03-28 12:18:44,862 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 37.10/18.54 [2019-03-28 12:18:44,862 INFO L811 eck$LassoCheckResult]: loop already infeasible 37.10/18.54 [2019-03-28 12:18:44,863 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 37.10/18.54 [2019-03-28 12:18:44,863 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 37.10/18.54 [2019-03-28 12:18:44,863 INFO L87 Difference]: Start difference. First operand 400 states and 670 transitions. cyclomatic complexity: 272 Second operand 3 states. 37.10/18.54 [2019-03-28 12:18:44,932 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 37.10/18.54 [2019-03-28 12:18:44,932 INFO L93 Difference]: Finished difference Result 398 states and 661 transitions. 37.10/18.54 [2019-03-28 12:18:44,933 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 37.10/18.54 [2019-03-28 12:18:44,938 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 398 states and 661 transitions. 37.10/18.54 [2019-03-28 12:18:44,941 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 382 37.10/18.54 [2019-03-28 12:18:44,944 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 398 states to 398 states and 661 transitions. 37.10/18.54 [2019-03-28 12:18:44,945 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 348 37.10/18.54 [2019-03-28 12:18:44,945 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 348 37.10/18.54 [2019-03-28 12:18:44,945 INFO L73 IsDeterministic]: Start isDeterministic. Operand 398 states and 661 transitions. 37.10/18.54 [2019-03-28 12:18:44,946 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. 37.10/18.54 [2019-03-28 12:18:44,946 INFO L706 BuchiCegarLoop]: Abstraction has 398 states and 661 transitions. 37.10/18.54 [2019-03-28 12:18:44,946 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 398 states and 661 transitions. 37.10/18.54 [2019-03-28 12:18:44,953 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 398 to 398. 37.10/18.54 [2019-03-28 12:18:44,953 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 398 states. 37.10/18.54 [2019-03-28 12:18:44,955 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 398 states to 398 states and 661 transitions. 37.10/18.54 [2019-03-28 12:18:44,955 INFO L729 BuchiCegarLoop]: Abstraction has 398 states and 661 transitions. 37.10/18.54 [2019-03-28 12:18:44,955 INFO L609 BuchiCegarLoop]: Abstraction has 398 states and 661 transitions. 37.10/18.54 [2019-03-28 12:18:44,955 INFO L442 BuchiCegarLoop]: ======== Iteration 14============ 37.10/18.54 [2019-03-28 12:18:44,955 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 398 states and 661 transitions. 37.10/18.54 [2019-03-28 12:18:44,958 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 382 37.10/18.54 [2019-03-28 12:18:44,958 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 37.10/18.54 [2019-03-28 12:18:44,958 INFO L119 BuchiIsEmpty]: Starting construction of run 37.10/18.54 [2019-03-28 12:18:44,958 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 37.10/18.54 [2019-03-28 12:18:44,958 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 37.10/18.54 [2019-03-28 12:18:44,959 INFO L794 eck$LassoCheckResult]: Stem: 12604#ULTIMATE.startENTRY [520] ULTIMATE.startENTRY-->L196: Formula: (and (= v_~q_write_ev~0_11 v_~q_read_ev~0_11) (= 1 v_~c_dr_i~0_7) (= v_~q_free~0_11 1) (= v_~q_buf_0~0_5 0) (= v_~q_write_ev~0_11 2) (= 0 v_~p_last_write~0_6) (= 0 v_~c_last_read~0_6) (= v_~p_dw_pc~0_14 0) (= 0 v_~a_t~0_5) (= 0 v_~c_dr_st~0_15) (= v_~c_dr_pc~0_14 0) (= 0 v_~c_num_read~0_9) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 0) (= 0 v_~p_num_write~0_9) (= v_~p_dw_i~0_7 1) (= v_~p_dw_st~0_15 0)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ~p_last_write~0=v_~p_last_write~0_6, ~c_dr_pc~0=v_~c_dr_pc~0_14, ~c_dr_st~0=v_~c_dr_st~0_15, ~c_num_read~0=v_~c_num_read~0_9, ~p_num_write~0=v_~p_num_write~0_9, ~c_dr_i~0=v_~c_dr_i~0_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7, ~q_write_ev~0=v_~q_write_ev~0_11, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~p_dw_st~0=v_~p_dw_st~0_15, ~p_dw_i~0=v_~p_dw_i~0_7, ~c_last_read~0=v_~c_last_read~0_6, ~p_dw_pc~0=v_~p_dw_pc~0_14, ~q_free~0=v_~q_free~0_11, ~q_buf_0~0=v_~q_buf_0~0_5, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6, ~q_read_ev~0=v_~q_read_ev~0_11, ~a_t~0=v_~a_t~0_5} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ~p_last_write~0, ~c_dr_pc~0, ~c_dr_st~0, ~c_num_read~0, ~p_num_write~0, ~c_dr_i~0, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_~kernel_st~0, ~q_write_ev~0, ULTIMATE.start_main_#res, ~p_dw_st~0, ~p_dw_i~0, ~c_last_read~0, ~p_dw_pc~0, ~q_free~0, ~q_buf_0~0, ULTIMATE.start_main_~__retres1~3, ~q_read_ev~0, ~a_t~0] 12605#L196 [418] L196-->L196-2: Formula: (and (= v_~p_dw_i~0_3 1) (= v_~p_dw_st~0_2 0)) InVars {~p_dw_i~0=v_~p_dw_i~0_3} OutVars{~p_dw_st~0=v_~p_dw_st~0_2, ~p_dw_i~0=v_~p_dw_i~0_3} AuxVars[] AssignedVars[~p_dw_st~0] 12641#L196-2 [413] L196-2-->L313-1: Formula: (and (= 1 v_~c_dr_i~0_3) (= v_~c_dr_st~0_3 0)) InVars {~c_dr_i~0=v_~c_dr_i~0_3} OutVars{~c_dr_st~0=v_~c_dr_st~0_3, ~c_dr_i~0=v_~c_dr_i~0_3} AuxVars[] AssignedVars[~c_dr_st~0] 12642#L313-1 [521] L313-1-->L262: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_8 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_8, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_4|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_6, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_6, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp~1, ULTIMATE.start_eval_~tmp___0~1, ULTIMATE.start_eval_~tmp___1~0] 12836#L262 [522] L262-->L214: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 12835#L214 [406] L214-->L226: Formula: (and (= v_~p_dw_st~0_6 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11 1)) InVars {~p_dw_st~0=v_~p_dw_st~0_6} OutVars{~p_dw_st~0=v_~p_dw_st~0_6, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 12834#L226 [523] L226-->L242: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___1~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_5|, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp___1~0] 12833#L242 [468] L242-->L242-1: Formula: (> v_ULTIMATE.start_eval_~tmp___1~0_4 0) InVars {ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} OutVars{ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} AuxVars[] AssignedVars[] 12832#L242-1 [333] L242-1-->L251: Formula: (and (= v_ULTIMATE.start_eval_~tmp~1_3 |v_ULTIMATE.start_eval_#t~nondet4_3|) (= v_~p_dw_st~0_8 0)) InVars {ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_3|, ~p_dw_st~0=v_~p_dw_st~0_8} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_2|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_3, ~p_dw_st~0=v_~p_dw_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_~tmp~1] 12831#L251 [472] L251-->L96: Formula: (and (= v_~p_dw_st~0_9 1) (> v_ULTIMATE.start_eval_~tmp~1_4 0)) InVars {ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_4} OutVars{ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_4, ~p_dw_st~0=v_~p_dw_st~0_9, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_1|} AuxVars[] AssignedVars[~p_dw_st~0, ULTIMATE.start_do_write_p_#t~nondet2] 12829#L96 [478] L96-->L99: Formula: (> v_~p_dw_pc~0_4 0) InVars {~p_dw_pc~0=v_~p_dw_pc~0_4} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_4} AuxVars[] AssignedVars[] 12827#L99 [361] L99-->L109: Formula: (= v_~p_dw_pc~0_5 1) InVars {~p_dw_pc~0=v_~p_dw_pc~0_5} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_5} AuxVars[] AssignedVars[] 12670#L109 37.10/18.54 [2019-03-28 12:18:44,959 INFO L796 eck$LassoCheckResult]: Loop: 12670#L109 [323] L109-->L32: Formula: (and (= v_~q_buf_0~0_2 |v_ULTIMATE.start_do_write_p_#t~nondet2_3|) (= v_~p_last_write~0_2 v_~q_buf_0~0_2) (= v_~q_write_ev~0_3 1) (= v_~p_num_write~0_3 (+ v_~p_num_write~0_4 1)) (= v_~q_free~0_5 0)) InVars {~p_num_write~0=v_~p_num_write~0_4, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_3|} OutVars{~p_last_write~0=v_~p_last_write~0_2, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_2|, ~p_num_write~0=v_~p_num_write~0_3, ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_1, ~q_write_ev~0=v_~q_write_ev~0_3, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_1, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_1|, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_1|, ~q_free~0=v_~q_free~0_5, ~q_buf_0~0=v_~q_buf_0~0_2, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_1|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_1} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0, ~q_write_ev~0, ~p_last_write~0, ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_do_write_p_#t~nondet2, ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret1, ~p_num_write~0, ~q_free~0, ~q_buf_0~0, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 12825#L32 [316] L32-->L33: Formula: (= v_~p_dw_pc~0_8 1) InVars {~p_dw_pc~0=v_~p_dw_pc~0_8} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_8} AuxVars[] AssignedVars[] 12823#L33 [352] L33-->L43: Formula: (and (= v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_3 1) (= 1 v_~q_read_ev~0_3)) InVars {~q_read_ev~0=v_~q_read_ev~0_3} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_3, ~q_read_ev~0=v_~q_read_ev~0_3} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0] 12822#L43 [528] L43-->L74: Formula: (and (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_7| v_ULTIMATE.start_immediate_notify_threads_~tmp~0_11) (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_7| v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11)) InVars {ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_7|, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_7|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 12700#L74 [499] L74-->L74-2: Formula: (and (> v_ULTIMATE.start_immediate_notify_threads_~tmp~0_4 0) (= v_~p_dw_st~0_11 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_4} OutVars{~p_dw_st~0=v_~p_dw_st~0_11, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_4} AuxVars[] AssignedVars[~p_dw_st~0] 12701#L74-2 [339] L74-2-->L51: Formula: true InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_1|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_1} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_#res, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 12820#L51 [501] L51-->L51-2: Formula: (< 1 v_~c_dr_pc~0_4) InVars {~c_dr_pc~0=v_~c_dr_pc~0_4} OutVars{~c_dr_pc~0=v_~c_dr_pc~0_4} AuxVars[] AssignedVars[] 12817#L51-2 [307] L51-2-->L62: Formula: (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 12815#L62 [532] L62-->L82: Formula: (and (= v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_11 |v_ULTIMATE.start_is_do_read_c_triggered_#res_7|) (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13 |v_ULTIMATE.start_is_do_read_c_triggered_#res_7|)) InVars {ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13} OutVars{ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_11, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_7|, ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_7|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13} AuxVars[] AssignedVars[ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_immediate_notify_threads_#t~ret1, ULTIMATE.start_is_do_read_c_triggered_#res] 12813#L82 [512] L82-->L82-2: Formula: (and (> v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_4 0) (= v_~c_dr_st~0_9 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_4} OutVars{~c_dr_st~0=v_~c_dr_st~0_9, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_4} AuxVars[] AssignedVars[~c_dr_st~0] 12614#L82-2 [366] L82-2-->L107-1: Formula: (= v_~q_write_ev~0_6 2) InVars {} OutVars{~q_write_ev~0=v_~q_write_ev~0_6} AuxVars[] AssignedVars[~q_write_ev~0] 12615#L107-1 [375] L107-1-->L108: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 12669#L108 [485] L108-->L109: Formula: (< v_~q_free~0_4 0) InVars {~q_free~0=v_~q_free~0_4} OutVars{~q_free~0=v_~q_free~0_4} AuxVars[] AssignedVars[] 12670#L109 37.10/18.54 [2019-03-28 12:18:44,959 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.54 [2019-03-28 12:18:44,960 INFO L82 PathProgramCache]: Analyzing trace with hash -743982638, now seen corresponding path program 1 times 37.10/18.54 [2019-03-28 12:18:44,960 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.54 [2019-03-28 12:18:44,960 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.54 [2019-03-28 12:18:44,961 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:44,961 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:44,961 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:44,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 37.10/18.54 [2019-03-28 12:18:44,973 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 37.10/18.54 [2019-03-28 12:18:44,973 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 37.10/18.54 [2019-03-28 12:18:44,973 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 37.10/18.54 [2019-03-28 12:18:44,974 INFO L799 eck$LassoCheckResult]: stem already infeasible 37.10/18.54 [2019-03-28 12:18:44,974 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.54 [2019-03-28 12:18:44,974 INFO L82 PathProgramCache]: Analyzing trace with hash 597812072, now seen corresponding path program 1 times 37.10/18.54 [2019-03-28 12:18:44,974 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.54 [2019-03-28 12:18:44,974 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.54 [2019-03-28 12:18:44,975 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:44,975 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:44,975 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:44,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 37.10/18.54 [2019-03-28 12:18:44,987 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 37.10/18.54 [2019-03-28 12:18:44,988 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 37.10/18.54 [2019-03-28 12:18:44,988 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 37.10/18.54 [2019-03-28 12:18:44,988 INFO L811 eck$LassoCheckResult]: loop already infeasible 37.10/18.54 [2019-03-28 12:18:44,988 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 37.10/18.54 [2019-03-28 12:18:44,988 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 37.10/18.54 [2019-03-28 12:18:44,989 INFO L87 Difference]: Start difference. First operand 398 states and 661 transitions. cyclomatic complexity: 265 Second operand 3 states. 37.10/18.54 [2019-03-28 12:18:45,129 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 37.10/18.54 [2019-03-28 12:18:45,130 INFO L93 Difference]: Finished difference Result 514 states and 842 transitions. 37.10/18.54 [2019-03-28 12:18:45,130 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 37.10/18.54 [2019-03-28 12:18:45,136 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 514 states and 842 transitions. 37.10/18.54 [2019-03-28 12:18:45,139 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 501 37.10/18.54 [2019-03-28 12:18:45,146 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 514 states to 514 states and 842 transitions. 37.10/18.54 [2019-03-28 12:18:45,146 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 464 37.10/18.54 [2019-03-28 12:18:45,147 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 464 37.10/18.54 [2019-03-28 12:18:45,147 INFO L73 IsDeterministic]: Start isDeterministic. Operand 514 states and 842 transitions. 37.10/18.54 [2019-03-28 12:18:45,147 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. 37.10/18.54 [2019-03-28 12:18:45,147 INFO L706 BuchiCegarLoop]: Abstraction has 514 states and 842 transitions. 37.10/18.54 [2019-03-28 12:18:45,148 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 514 states and 842 transitions. 37.10/18.54 [2019-03-28 12:18:45,157 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 514 to 458. 37.10/18.54 [2019-03-28 12:18:45,158 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 458 states. 37.10/18.54 [2019-03-28 12:18:45,159 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 458 states to 458 states and 755 transitions. 37.10/18.54 [2019-03-28 12:18:45,160 INFO L729 BuchiCegarLoop]: Abstraction has 458 states and 755 transitions. 37.10/18.54 [2019-03-28 12:18:45,160 INFO L609 BuchiCegarLoop]: Abstraction has 458 states and 755 transitions. 37.10/18.54 [2019-03-28 12:18:45,160 INFO L442 BuchiCegarLoop]: ======== Iteration 15============ 37.10/18.54 [2019-03-28 12:18:45,160 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 458 states and 755 transitions. 37.10/18.54 [2019-03-28 12:18:45,162 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 445 37.10/18.54 [2019-03-28 12:18:45,163 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 37.10/18.54 [2019-03-28 12:18:45,163 INFO L119 BuchiIsEmpty]: Starting construction of run 37.10/18.54 [2019-03-28 12:18:45,163 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 37.10/18.54 [2019-03-28 12:18:45,163 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 37.10/18.54 [2019-03-28 12:18:45,164 INFO L794 eck$LassoCheckResult]: Stem: 13521#ULTIMATE.startENTRY [520] ULTIMATE.startENTRY-->L196: Formula: (and (= v_~q_write_ev~0_11 v_~q_read_ev~0_11) (= 1 v_~c_dr_i~0_7) (= v_~q_free~0_11 1) (= v_~q_buf_0~0_5 0) (= v_~q_write_ev~0_11 2) (= 0 v_~p_last_write~0_6) (= 0 v_~c_last_read~0_6) (= v_~p_dw_pc~0_14 0) (= 0 v_~a_t~0_5) (= 0 v_~c_dr_st~0_15) (= v_~c_dr_pc~0_14 0) (= 0 v_~c_num_read~0_9) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 0) (= 0 v_~p_num_write~0_9) (= v_~p_dw_i~0_7 1) (= v_~p_dw_st~0_15 0)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ~p_last_write~0=v_~p_last_write~0_6, ~c_dr_pc~0=v_~c_dr_pc~0_14, ~c_dr_st~0=v_~c_dr_st~0_15, ~c_num_read~0=v_~c_num_read~0_9, ~p_num_write~0=v_~p_num_write~0_9, ~c_dr_i~0=v_~c_dr_i~0_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7, ~q_write_ev~0=v_~q_write_ev~0_11, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~p_dw_st~0=v_~p_dw_st~0_15, ~p_dw_i~0=v_~p_dw_i~0_7, ~c_last_read~0=v_~c_last_read~0_6, ~p_dw_pc~0=v_~p_dw_pc~0_14, ~q_free~0=v_~q_free~0_11, ~q_buf_0~0=v_~q_buf_0~0_5, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6, ~q_read_ev~0=v_~q_read_ev~0_11, ~a_t~0=v_~a_t~0_5} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ~p_last_write~0, ~c_dr_pc~0, ~c_dr_st~0, ~c_num_read~0, ~p_num_write~0, ~c_dr_i~0, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_~kernel_st~0, ~q_write_ev~0, ULTIMATE.start_main_#res, ~p_dw_st~0, ~p_dw_i~0, ~c_last_read~0, ~p_dw_pc~0, ~q_free~0, ~q_buf_0~0, ULTIMATE.start_main_~__retres1~3, ~q_read_ev~0, ~a_t~0] 13522#L196 [418] L196-->L196-2: Formula: (and (= v_~p_dw_i~0_3 1) (= v_~p_dw_st~0_2 0)) InVars {~p_dw_i~0=v_~p_dw_i~0_3} OutVars{~p_dw_st~0=v_~p_dw_st~0_2, ~p_dw_i~0=v_~p_dw_i~0_3} AuxVars[] AssignedVars[~p_dw_st~0] 13555#L196-2 [413] L196-2-->L313-1: Formula: (and (= 1 v_~c_dr_i~0_3) (= v_~c_dr_st~0_3 0)) InVars {~c_dr_i~0=v_~c_dr_i~0_3} OutVars{~c_dr_st~0=v_~c_dr_st~0_3, ~c_dr_i~0=v_~c_dr_i~0_3} AuxVars[] AssignedVars[~c_dr_st~0] 13556#L313-1 [521] L313-1-->L262: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_8 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_8, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_4|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_6, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_6, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp~1, ULTIMATE.start_eval_~tmp___0~1, ULTIMATE.start_eval_~tmp___1~0] 13689#L262 [522] L262-->L214: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 13774#L214 [406] L214-->L226: Formula: (and (= v_~p_dw_st~0_6 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11 1)) InVars {~p_dw_st~0=v_~p_dw_st~0_6} OutVars{~p_dw_st~0=v_~p_dw_st~0_6, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 13773#L226 [523] L226-->L242: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___1~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_5|, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp___1~0] 13767#L242 [468] L242-->L242-1: Formula: (> v_ULTIMATE.start_eval_~tmp___1~0_4 0) InVars {ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} OutVars{ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} AuxVars[] AssignedVars[] 13746#L242-1 [333] L242-1-->L251: Formula: (and (= v_ULTIMATE.start_eval_~tmp~1_3 |v_ULTIMATE.start_eval_#t~nondet4_3|) (= v_~p_dw_st~0_8 0)) InVars {ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_3|, ~p_dw_st~0=v_~p_dw_st~0_8} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_2|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_3, ~p_dw_st~0=v_~p_dw_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_~tmp~1] 13744#L251 [472] L251-->L96: Formula: (and (= v_~p_dw_st~0_9 1) (> v_ULTIMATE.start_eval_~tmp~1_4 0)) InVars {ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_4} OutVars{ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_4, ~p_dw_st~0=v_~p_dw_st~0_9, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_1|} AuxVars[] AssignedVars[~p_dw_st~0, ULTIMATE.start_do_write_p_#t~nondet2] 13536#L96 [378] L96-->L107-1: Formula: (= v_~p_dw_pc~0_3 0) InVars {~p_dw_pc~0=v_~p_dw_pc~0_3} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_3} AuxVars[] AssignedVars[] 13534#L107-1 [375] L107-1-->L108: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 13535#L108 [486] L108-->L109: Formula: (> v_~q_free~0_4 0) InVars {~q_free~0=v_~q_free~0_4} OutVars{~q_free~0=v_~q_free~0_4} AuxVars[] AssignedVars[] 13503#L109 37.10/18.54 [2019-03-28 12:18:45,164 INFO L796 eck$LassoCheckResult]: Loop: 13503#L109 [323] L109-->L32: Formula: (and (= v_~q_buf_0~0_2 |v_ULTIMATE.start_do_write_p_#t~nondet2_3|) (= v_~p_last_write~0_2 v_~q_buf_0~0_2) (= v_~q_write_ev~0_3 1) (= v_~p_num_write~0_3 (+ v_~p_num_write~0_4 1)) (= v_~q_free~0_5 0)) InVars {~p_num_write~0=v_~p_num_write~0_4, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_3|} OutVars{~p_last_write~0=v_~p_last_write~0_2, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_2|, ~p_num_write~0=v_~p_num_write~0_3, ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_1, ~q_write_ev~0=v_~q_write_ev~0_3, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_1, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_1|, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_1|, ~q_free~0=v_~q_free~0_5, ~q_buf_0~0=v_~q_buf_0~0_2, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_1|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_1} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0, ~q_write_ev~0, ~p_last_write~0, ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_do_write_p_#t~nondet2, ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret1, ~p_num_write~0, ~q_free~0, ~q_buf_0~0, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 13487#L32 [489] L32-->L32-2: Formula: (< v_~p_dw_pc~0_9 1) InVars {~p_dw_pc~0=v_~p_dw_pc~0_9} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_9} AuxVars[] AssignedVars[] 13488#L32-2 [403] L32-2-->L43: Formula: (= v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_4 0) InVars {} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_4} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0] 13816#L43 [528] L43-->L74: Formula: (and (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_7| v_ULTIMATE.start_immediate_notify_threads_~tmp~0_11) (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_7| v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11)) InVars {ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_7|, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_7|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 13815#L74 [499] L74-->L74-2: Formula: (and (> v_ULTIMATE.start_immediate_notify_threads_~tmp~0_4 0) (= v_~p_dw_st~0_11 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_4} OutVars{~p_dw_st~0=v_~p_dw_st~0_11, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_4} AuxVars[] AssignedVars[~p_dw_st~0] 13813#L74-2 [339] L74-2-->L51: Formula: true InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_1|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_1} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_#res, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 13812#L51 [309] L51-->L52: Formula: (= 1 v_~c_dr_pc~0_3) InVars {~c_dr_pc~0=v_~c_dr_pc~0_3} OutVars{~c_dr_pc~0=v_~c_dr_pc~0_3} AuxVars[] AssignedVars[] 13811#L52 [343] L52-->L62: Formula: (and (= v_~q_write_ev~0_4 1) (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_4 1)) InVars {~q_write_ev~0=v_~q_write_ev~0_4} OutVars{~q_write_ev~0=v_~q_write_ev~0_4, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_4} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 13760#L62 [532] L62-->L82: Formula: (and (= v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_11 |v_ULTIMATE.start_is_do_read_c_triggered_#res_7|) (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13 |v_ULTIMATE.start_is_do_read_c_triggered_#res_7|)) InVars {ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13} OutVars{ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_11, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_7|, ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_7|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13} AuxVars[] AssignedVars[ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_immediate_notify_threads_#t~ret1, ULTIMATE.start_is_do_read_c_triggered_#res] 13809#L82 [512] L82-->L82-2: Formula: (and (> v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_4 0) (= v_~c_dr_st~0_9 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_4} OutVars{~c_dr_st~0=v_~c_dr_st~0_9, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_4} AuxVars[] AssignedVars[~c_dr_st~0] 13754#L82-2 [366] L82-2-->L107-1: Formula: (= v_~q_write_ev~0_6 2) InVars {} OutVars{~q_write_ev~0=v_~q_write_ev~0_6} AuxVars[] AssignedVars[~q_write_ev~0] 13805#L107-1 [375] L107-1-->L108: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 13775#L108 [485] L108-->L109: Formula: (< v_~q_free~0_4 0) InVars {~q_free~0=v_~q_free~0_4} OutVars{~q_free~0=v_~q_free~0_4} AuxVars[] AssignedVars[] 13503#L109 37.10/18.54 [2019-03-28 12:18:45,164 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.54 [2019-03-28 12:18:45,165 INFO L82 PathProgramCache]: Analyzing trace with hash -1588720478, now seen corresponding path program 1 times 37.10/18.54 [2019-03-28 12:18:45,165 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.54 [2019-03-28 12:18:45,165 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.54 [2019-03-28 12:18:45,166 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:45,166 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:45,166 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:45,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 37.10/18.54 [2019-03-28 12:18:45,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 37.10/18.54 [2019-03-28 12:18:45,176 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.54 [2019-03-28 12:18:45,176 INFO L82 PathProgramCache]: Analyzing trace with hash -1862252886, now seen corresponding path program 1 times 37.10/18.54 [2019-03-28 12:18:45,176 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.54 [2019-03-28 12:18:45,176 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.54 [2019-03-28 12:18:45,179 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:45,179 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:45,179 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:45,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 37.10/18.54 [2019-03-28 12:18:45,227 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 37.10/18.54 [2019-03-28 12:18:45,227 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 37.10/18.54 [2019-03-28 12:18:45,227 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 37.10/18.54 [2019-03-28 12:18:45,227 INFO L811 eck$LassoCheckResult]: loop already infeasible 37.10/18.54 [2019-03-28 12:18:45,228 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 37.10/18.54 [2019-03-28 12:18:45,228 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 37.10/18.54 [2019-03-28 12:18:45,228 INFO L87 Difference]: Start difference. First operand 458 states and 755 transitions. cyclomatic complexity: 299 Second operand 3 states. 37.10/18.54 [2019-03-28 12:18:45,300 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 37.10/18.54 [2019-03-28 12:18:45,300 INFO L93 Difference]: Finished difference Result 458 states and 749 transitions. 37.10/18.54 [2019-03-28 12:18:45,300 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 37.10/18.54 [2019-03-28 12:18:45,306 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 458 states and 749 transitions. 37.10/18.54 [2019-03-28 12:18:45,309 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 445 37.10/18.54 [2019-03-28 12:18:45,312 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 458 states to 458 states and 749 transitions. 37.10/18.54 [2019-03-28 12:18:45,312 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 408 37.10/18.54 [2019-03-28 12:18:45,313 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 408 37.10/18.54 [2019-03-28 12:18:45,313 INFO L73 IsDeterministic]: Start isDeterministic. Operand 458 states and 749 transitions. 37.10/18.54 [2019-03-28 12:18:45,313 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. 37.10/18.54 [2019-03-28 12:18:45,313 INFO L706 BuchiCegarLoop]: Abstraction has 458 states and 749 transitions. 37.10/18.54 [2019-03-28 12:18:45,314 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 458 states and 749 transitions. 37.10/18.54 [2019-03-28 12:18:45,321 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 458 to 458. 37.10/18.54 [2019-03-28 12:18:45,321 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 458 states. 37.10/18.54 [2019-03-28 12:18:45,323 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 458 states to 458 states and 749 transitions. 37.10/18.54 [2019-03-28 12:18:45,323 INFO L729 BuchiCegarLoop]: Abstraction has 458 states and 749 transitions. 37.10/18.54 [2019-03-28 12:18:45,323 INFO L609 BuchiCegarLoop]: Abstraction has 458 states and 749 transitions. 37.10/18.54 [2019-03-28 12:18:45,323 INFO L442 BuchiCegarLoop]: ======== Iteration 16============ 37.10/18.54 [2019-03-28 12:18:45,323 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 458 states and 749 transitions. 37.10/18.54 [2019-03-28 12:18:45,325 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 445 37.10/18.54 [2019-03-28 12:18:45,325 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 37.10/18.54 [2019-03-28 12:18:45,326 INFO L119 BuchiIsEmpty]: Starting construction of run 37.10/18.54 [2019-03-28 12:18:45,326 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 37.10/18.54 [2019-03-28 12:18:45,326 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 37.10/18.54 [2019-03-28 12:18:45,326 INFO L794 eck$LassoCheckResult]: Stem: 14440#ULTIMATE.startENTRY [520] ULTIMATE.startENTRY-->L196: Formula: (and (= v_~q_write_ev~0_11 v_~q_read_ev~0_11) (= 1 v_~c_dr_i~0_7) (= v_~q_free~0_11 1) (= v_~q_buf_0~0_5 0) (= v_~q_write_ev~0_11 2) (= 0 v_~p_last_write~0_6) (= 0 v_~c_last_read~0_6) (= v_~p_dw_pc~0_14 0) (= 0 v_~a_t~0_5) (= 0 v_~c_dr_st~0_15) (= v_~c_dr_pc~0_14 0) (= 0 v_~c_num_read~0_9) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 0) (= 0 v_~p_num_write~0_9) (= v_~p_dw_i~0_7 1) (= v_~p_dw_st~0_15 0)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ~p_last_write~0=v_~p_last_write~0_6, ~c_dr_pc~0=v_~c_dr_pc~0_14, ~c_dr_st~0=v_~c_dr_st~0_15, ~c_num_read~0=v_~c_num_read~0_9, ~p_num_write~0=v_~p_num_write~0_9, ~c_dr_i~0=v_~c_dr_i~0_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7, ~q_write_ev~0=v_~q_write_ev~0_11, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~p_dw_st~0=v_~p_dw_st~0_15, ~p_dw_i~0=v_~p_dw_i~0_7, ~c_last_read~0=v_~c_last_read~0_6, ~p_dw_pc~0=v_~p_dw_pc~0_14, ~q_free~0=v_~q_free~0_11, ~q_buf_0~0=v_~q_buf_0~0_5, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6, ~q_read_ev~0=v_~q_read_ev~0_11, ~a_t~0=v_~a_t~0_5} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ~p_last_write~0, ~c_dr_pc~0, ~c_dr_st~0, ~c_num_read~0, ~p_num_write~0, ~c_dr_i~0, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_~kernel_st~0, ~q_write_ev~0, ULTIMATE.start_main_#res, ~p_dw_st~0, ~p_dw_i~0, ~c_last_read~0, ~p_dw_pc~0, ~q_free~0, ~q_buf_0~0, ULTIMATE.start_main_~__retres1~3, ~q_read_ev~0, ~a_t~0] 14441#L196 [418] L196-->L196-2: Formula: (and (= v_~p_dw_i~0_3 1) (= v_~p_dw_st~0_2 0)) InVars {~p_dw_i~0=v_~p_dw_i~0_3} OutVars{~p_dw_st~0=v_~p_dw_st~0_2, ~p_dw_i~0=v_~p_dw_i~0_3} AuxVars[] AssignedVars[~p_dw_st~0] 14482#L196-2 [413] L196-2-->L313-1: Formula: (and (= 1 v_~c_dr_i~0_3) (= v_~c_dr_st~0_3 0)) InVars {~c_dr_i~0=v_~c_dr_i~0_3} OutVars{~c_dr_st~0=v_~c_dr_st~0_3, ~c_dr_i~0=v_~c_dr_i~0_3} AuxVars[] AssignedVars[~c_dr_st~0] 14483#L313-1 [521] L313-1-->L262: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_8 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_8, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_4|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_6, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_6, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp~1, ULTIMATE.start_eval_~tmp___0~1, ULTIMATE.start_eval_~tmp___1~0] 14513#L262 [522] L262-->L214: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 14846#L214 [406] L214-->L226: Formula: (and (= v_~p_dw_st~0_6 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11 1)) InVars {~p_dw_st~0=v_~p_dw_st~0_6} OutVars{~p_dw_st~0=v_~p_dw_st~0_6, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 14845#L226 [523] L226-->L242: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___1~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_5|, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp___1~0] 14844#L242 [468] L242-->L242-1: Formula: (> v_ULTIMATE.start_eval_~tmp___1~0_4 0) InVars {ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} OutVars{ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} AuxVars[] AssignedVars[] 14843#L242-1 [333] L242-1-->L251: Formula: (and (= v_ULTIMATE.start_eval_~tmp~1_3 |v_ULTIMATE.start_eval_#t~nondet4_3|) (= v_~p_dw_st~0_8 0)) InVars {ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_3|, ~p_dw_st~0=v_~p_dw_st~0_8} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_2|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_3, ~p_dw_st~0=v_~p_dw_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_~tmp~1] 14842#L251 [472] L251-->L96: Formula: (and (= v_~p_dw_st~0_9 1) (> v_ULTIMATE.start_eval_~tmp~1_4 0)) InVars {ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_4} OutVars{ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_4, ~p_dw_st~0=v_~p_dw_st~0_9, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_1|} AuxVars[] AssignedVars[~p_dw_st~0, ULTIMATE.start_do_write_p_#t~nondet2] 14827#L96 [378] L96-->L107-1: Formula: (= v_~p_dw_pc~0_3 0) InVars {~p_dw_pc~0=v_~p_dw_pc~0_3} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_3} AuxVars[] AssignedVars[] 14826#L107-1 [375] L107-1-->L108: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 14821#L108 [486] L108-->L109: Formula: (> v_~q_free~0_4 0) InVars {~q_free~0=v_~q_free~0_4} OutVars{~q_free~0=v_~q_free~0_4} AuxVars[] AssignedVars[] 14694#L109 37.10/18.54 [2019-03-28 12:18:45,327 INFO L796 eck$LassoCheckResult]: Loop: 14694#L109 [323] L109-->L32: Formula: (and (= v_~q_buf_0~0_2 |v_ULTIMATE.start_do_write_p_#t~nondet2_3|) (= v_~p_last_write~0_2 v_~q_buf_0~0_2) (= v_~q_write_ev~0_3 1) (= v_~p_num_write~0_3 (+ v_~p_num_write~0_4 1)) (= v_~q_free~0_5 0)) InVars {~p_num_write~0=v_~p_num_write~0_4, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_3|} OutVars{~p_last_write~0=v_~p_last_write~0_2, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_2|, ~p_num_write~0=v_~p_num_write~0_3, ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_1, ~q_write_ev~0=v_~q_write_ev~0_3, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_1, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_1|, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_1|, ~q_free~0=v_~q_free~0_5, ~q_buf_0~0=v_~q_buf_0~0_2, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_1|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_1} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0, ~q_write_ev~0, ~p_last_write~0, ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_do_write_p_#t~nondet2, ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret1, ~p_num_write~0, ~q_free~0, ~q_buf_0~0, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 14815#L32 [489] L32-->L32-2: Formula: (< v_~p_dw_pc~0_9 1) InVars {~p_dw_pc~0=v_~p_dw_pc~0_9} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_9} AuxVars[] AssignedVars[] 14811#L32-2 [403] L32-2-->L43: Formula: (= v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_4 0) InVars {} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_4} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0] 14806#L43 [528] L43-->L74: Formula: (and (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_7| v_ULTIMATE.start_immediate_notify_threads_~tmp~0_11) (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_7| v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11)) InVars {ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_7|, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_7|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 14803#L74 [499] L74-->L74-2: Formula: (and (> v_ULTIMATE.start_immediate_notify_threads_~tmp~0_4 0) (= v_~p_dw_st~0_11 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_4} OutVars{~p_dw_st~0=v_~p_dw_st~0_11, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_4} AuxVars[] AssignedVars[~p_dw_st~0] 14804#L74-2 [339] L74-2-->L51: Formula: true InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_1|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_1} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_#res, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 14838#L51 [501] L51-->L51-2: Formula: (< 1 v_~c_dr_pc~0_4) InVars {~c_dr_pc~0=v_~c_dr_pc~0_4} OutVars{~c_dr_pc~0=v_~c_dr_pc~0_4} AuxVars[] AssignedVars[] 14835#L51-2 [307] L51-2-->L62: Formula: (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 14834#L62 [532] L62-->L82: Formula: (and (= v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_11 |v_ULTIMATE.start_is_do_read_c_triggered_#res_7|) (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13 |v_ULTIMATE.start_is_do_read_c_triggered_#res_7|)) InVars {ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13} OutVars{ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_11, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_7|, ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_7|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13} AuxVars[] AssignedVars[ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_immediate_notify_threads_#t~ret1, ULTIMATE.start_is_do_read_c_triggered_#res] 14823#L82 [512] L82-->L82-2: Formula: (and (> v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_4 0) (= v_~c_dr_st~0_9 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_4} OutVars{~c_dr_st~0=v_~c_dr_st~0_9, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_4} AuxVars[] AssignedVars[~c_dr_st~0] 14820#L82-2 [366] L82-2-->L107-1: Formula: (= v_~q_write_ev~0_6 2) InVars {} OutVars{~q_write_ev~0=v_~q_write_ev~0_6} AuxVars[] AssignedVars[~q_write_ev~0] 14819#L107-1 [375] L107-1-->L108: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 14693#L108 [486] L108-->L109: Formula: (> v_~q_free~0_4 0) InVars {~q_free~0=v_~q_free~0_4} OutVars{~q_free~0=v_~q_free~0_4} AuxVars[] AssignedVars[] 14694#L109 37.10/18.54 [2019-03-28 12:18:45,327 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.54 [2019-03-28 12:18:45,327 INFO L82 PathProgramCache]: Analyzing trace with hash -1588720478, now seen corresponding path program 2 times 37.10/18.54 [2019-03-28 12:18:45,327 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.54 [2019-03-28 12:18:45,327 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.54 [2019-03-28 12:18:45,328 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:45,328 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:45,329 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:45,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 37.10/18.54 [2019-03-28 12:18:45,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 37.10/18.54 [2019-03-28 12:18:45,337 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.54 [2019-03-28 12:18:45,338 INFO L82 PathProgramCache]: Analyzing trace with hash 4079887, now seen corresponding path program 1 times 37.10/18.54 [2019-03-28 12:18:45,338 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.54 [2019-03-28 12:18:45,338 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.54 [2019-03-28 12:18:45,339 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:45,339 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:45,339 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:45,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 37.10/18.54 [2019-03-28 12:18:45,353 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 37.10/18.54 [2019-03-28 12:18:45,353 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 37.10/18.54 [2019-03-28 12:18:45,353 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 37.10/18.54 [2019-03-28 12:18:45,354 INFO L811 eck$LassoCheckResult]: loop already infeasible 37.10/18.54 [2019-03-28 12:18:45,354 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 37.10/18.54 [2019-03-28 12:18:45,354 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 37.10/18.54 [2019-03-28 12:18:45,354 INFO L87 Difference]: Start difference. First operand 458 states and 749 transitions. cyclomatic complexity: 293 Second operand 3 states. 37.10/18.54 [2019-03-28 12:18:45,456 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 37.10/18.54 [2019-03-28 12:18:45,456 INFO L93 Difference]: Finished difference Result 495 states and 787 transitions. 37.10/18.54 [2019-03-28 12:18:45,457 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 37.10/18.54 [2019-03-28 12:18:45,462 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 495 states and 787 transitions. 37.10/18.54 [2019-03-28 12:18:45,465 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 467 37.10/18.54 [2019-03-28 12:18:45,469 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 495 states to 491 states and 779 transitions. 37.10/18.54 [2019-03-28 12:18:45,469 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 441 37.10/18.54 [2019-03-28 12:18:45,469 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 441 37.10/18.54 [2019-03-28 12:18:45,470 INFO L73 IsDeterministic]: Start isDeterministic. Operand 491 states and 779 transitions. 37.10/18.54 [2019-03-28 12:18:45,470 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. 37.10/18.54 [2019-03-28 12:18:45,470 INFO L706 BuchiCegarLoop]: Abstraction has 491 states and 779 transitions. 37.10/18.54 [2019-03-28 12:18:45,471 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 491 states and 779 transitions. 37.10/18.54 [2019-03-28 12:18:45,478 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 491 to 469. 37.10/18.54 [2019-03-28 12:18:45,478 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 469 states. 37.10/18.54 [2019-03-28 12:18:45,480 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 469 states to 469 states and 749 transitions. 37.10/18.54 [2019-03-28 12:18:45,480 INFO L729 BuchiCegarLoop]: Abstraction has 469 states and 749 transitions. 37.10/18.54 [2019-03-28 12:18:45,480 INFO L609 BuchiCegarLoop]: Abstraction has 469 states and 749 transitions. 37.10/18.54 [2019-03-28 12:18:45,480 INFO L442 BuchiCegarLoop]: ======== Iteration 17============ 37.10/18.54 [2019-03-28 12:18:45,480 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 469 states and 749 transitions. 37.10/18.54 [2019-03-28 12:18:45,482 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 445 37.10/18.54 [2019-03-28 12:18:45,483 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 37.10/18.54 [2019-03-28 12:18:45,483 INFO L119 BuchiIsEmpty]: Starting construction of run 37.10/18.54 [2019-03-28 12:18:45,483 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 37.10/18.54 [2019-03-28 12:18:45,484 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 37.10/18.54 [2019-03-28 12:18:45,484 INFO L794 eck$LassoCheckResult]: Stem: 15399#ULTIMATE.startENTRY [520] ULTIMATE.startENTRY-->L196: Formula: (and (= v_~q_write_ev~0_11 v_~q_read_ev~0_11) (= 1 v_~c_dr_i~0_7) (= v_~q_free~0_11 1) (= v_~q_buf_0~0_5 0) (= v_~q_write_ev~0_11 2) (= 0 v_~p_last_write~0_6) (= 0 v_~c_last_read~0_6) (= v_~p_dw_pc~0_14 0) (= 0 v_~a_t~0_5) (= 0 v_~c_dr_st~0_15) (= v_~c_dr_pc~0_14 0) (= 0 v_~c_num_read~0_9) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 0) (= 0 v_~p_num_write~0_9) (= v_~p_dw_i~0_7 1) (= v_~p_dw_st~0_15 0)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ~p_last_write~0=v_~p_last_write~0_6, ~c_dr_pc~0=v_~c_dr_pc~0_14, ~c_dr_st~0=v_~c_dr_st~0_15, ~c_num_read~0=v_~c_num_read~0_9, ~p_num_write~0=v_~p_num_write~0_9, ~c_dr_i~0=v_~c_dr_i~0_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7, ~q_write_ev~0=v_~q_write_ev~0_11, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~p_dw_st~0=v_~p_dw_st~0_15, ~p_dw_i~0=v_~p_dw_i~0_7, ~c_last_read~0=v_~c_last_read~0_6, ~p_dw_pc~0=v_~p_dw_pc~0_14, ~q_free~0=v_~q_free~0_11, ~q_buf_0~0=v_~q_buf_0~0_5, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6, ~q_read_ev~0=v_~q_read_ev~0_11, ~a_t~0=v_~a_t~0_5} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ~p_last_write~0, ~c_dr_pc~0, ~c_dr_st~0, ~c_num_read~0, ~p_num_write~0, ~c_dr_i~0, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_~kernel_st~0, ~q_write_ev~0, ULTIMATE.start_main_#res, ~p_dw_st~0, ~p_dw_i~0, ~c_last_read~0, ~p_dw_pc~0, ~q_free~0, ~q_buf_0~0, ULTIMATE.start_main_~__retres1~3, ~q_read_ev~0, ~a_t~0] 15400#L196 [418] L196-->L196-2: Formula: (and (= v_~p_dw_i~0_3 1) (= v_~p_dw_st~0_2 0)) InVars {~p_dw_i~0=v_~p_dw_i~0_3} OutVars{~p_dw_st~0=v_~p_dw_st~0_2, ~p_dw_i~0=v_~p_dw_i~0_3} AuxVars[] AssignedVars[~p_dw_st~0] 15446#L196-2 [413] L196-2-->L313-1: Formula: (and (= 1 v_~c_dr_i~0_3) (= v_~c_dr_st~0_3 0)) InVars {~c_dr_i~0=v_~c_dr_i~0_3} OutVars{~c_dr_st~0=v_~c_dr_st~0_3, ~c_dr_i~0=v_~c_dr_i~0_3} AuxVars[] AssignedVars[~c_dr_st~0] 15447#L313-1 [521] L313-1-->L262: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_8 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_8, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_4|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_6, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_6, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp~1, ULTIMATE.start_eval_~tmp___0~1, ULTIMATE.start_eval_~tmp___1~0] 15553#L262 [522] L262-->L214: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 15554#L214 [406] L214-->L226: Formula: (and (= v_~p_dw_st~0_6 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11 1)) InVars {~p_dw_st~0=v_~p_dw_st~0_6} OutVars{~p_dw_st~0=v_~p_dw_st~0_6, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 15547#L226 [523] L226-->L242: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___1~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_5|, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp___1~0] 15548#L242 [468] L242-->L242-1: Formula: (> v_ULTIMATE.start_eval_~tmp___1~0_4 0) InVars {ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} OutVars{ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} AuxVars[] AssignedVars[] 15535#L242-1 [333] L242-1-->L251: Formula: (and (= v_ULTIMATE.start_eval_~tmp~1_3 |v_ULTIMATE.start_eval_#t~nondet4_3|) (= v_~p_dw_st~0_8 0)) InVars {ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_3|, ~p_dw_st~0=v_~p_dw_st~0_8} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_2|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_3, ~p_dw_st~0=v_~p_dw_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_~tmp~1] 15536#L251 [472] L251-->L96: Formula: (and (= v_~p_dw_st~0_9 1) (> v_ULTIMATE.start_eval_~tmp~1_4 0)) InVars {ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_4} OutVars{ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_4, ~p_dw_st~0=v_~p_dw_st~0_9, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_1|} AuxVars[] AssignedVars[~p_dw_st~0, ULTIMATE.start_do_write_p_#t~nondet2] 15415#L96 [378] L96-->L107-1: Formula: (= v_~p_dw_pc~0_3 0) InVars {~p_dw_pc~0=v_~p_dw_pc~0_3} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_3} AuxVars[] AssignedVars[] 15416#L107-1 [375] L107-1-->L108: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 15609#L108 [486] L108-->L109: Formula: (> v_~q_free~0_4 0) InVars {~q_free~0=v_~q_free~0_4} OutVars{~q_free~0=v_~q_free~0_4} AuxVars[] AssignedVars[] 15610#L109 [323] L109-->L32: Formula: (and (= v_~q_buf_0~0_2 |v_ULTIMATE.start_do_write_p_#t~nondet2_3|) (= v_~p_last_write~0_2 v_~q_buf_0~0_2) (= v_~q_write_ev~0_3 1) (= v_~p_num_write~0_3 (+ v_~p_num_write~0_4 1)) (= v_~q_free~0_5 0)) InVars {~p_num_write~0=v_~p_num_write~0_4, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_3|} OutVars{~p_last_write~0=v_~p_last_write~0_2, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_2|, ~p_num_write~0=v_~p_num_write~0_3, ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_1, ~q_write_ev~0=v_~q_write_ev~0_3, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_1, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_1|, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_1|, ~q_free~0=v_~q_free~0_5, ~q_buf_0~0=v_~q_buf_0~0_2, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_1|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_1} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0, ~q_write_ev~0, ~p_last_write~0, ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_do_write_p_#t~nondet2, ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret1, ~p_num_write~0, ~q_free~0, ~q_buf_0~0, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 15688#L32 [489] L32-->L32-2: Formula: (< v_~p_dw_pc~0_9 1) InVars {~p_dw_pc~0=v_~p_dw_pc~0_9} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_9} AuxVars[] AssignedVars[] 15687#L32-2 [403] L32-2-->L43: Formula: (= v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_4 0) InVars {} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_4} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0] 15686#L43 [528] L43-->L74: Formula: (and (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_7| v_ULTIMATE.start_immediate_notify_threads_~tmp~0_11) (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_7| v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11)) InVars {ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_7|, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_7|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 15685#L74 [377] L74-->L74-2: Formula: (= v_ULTIMATE.start_immediate_notify_threads_~tmp~0_5 0) InVars {ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_5} OutVars{ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_5} AuxVars[] AssignedVars[] 15684#L74-2 [339] L74-2-->L51: Formula: true InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_1|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_1} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_#res, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 15682#L51 [309] L51-->L52: Formula: (= 1 v_~c_dr_pc~0_3) InVars {~c_dr_pc~0=v_~c_dr_pc~0_3} OutVars{~c_dr_pc~0=v_~c_dr_pc~0_3} AuxVars[] AssignedVars[] 15683#L52 [343] L52-->L62: Formula: (and (= v_~q_write_ev~0_4 1) (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_4 1)) InVars {~q_write_ev~0=v_~q_write_ev~0_4} OutVars{~q_write_ev~0=v_~q_write_ev~0_4, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_4} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 15357#L62 37.10/18.54 [2019-03-28 12:18:45,485 INFO L796 eck$LassoCheckResult]: Loop: 15357#L62 [532] L62-->L82: Formula: (and (= v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_11 |v_ULTIMATE.start_is_do_read_c_triggered_#res_7|) (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13 |v_ULTIMATE.start_is_do_read_c_triggered_#res_7|)) InVars {ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13} OutVars{ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_11, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_7|, ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_7|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13} AuxVars[] AssignedVars[ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_immediate_notify_threads_#t~ret1, ULTIMATE.start_is_do_read_c_triggered_#res] 15358#L82 [512] L82-->L82-2: Formula: (and (> v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_4 0) (= v_~c_dr_st~0_9 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_4} OutVars{~c_dr_st~0=v_~c_dr_st~0_9, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_4} AuxVars[] AssignedVars[~c_dr_st~0] 15670#L82-2 [366] L82-2-->L107-1: Formula: (= v_~q_write_ev~0_6 2) InVars {} OutVars{~q_write_ev~0=v_~q_write_ev~0_6} AuxVars[] AssignedVars[~q_write_ev~0] 15669#L107-1 [375] L107-1-->L108: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 15665#L108 [408] L108-->L247: Formula: (and (= v_~q_free~0_3 0) (= v_~p_dw_pc~0_7 1) (= v_~p_dw_st~0_10 2)) InVars {~q_free~0=v_~q_free~0_3} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_7, ~q_free~0=v_~q_free~0_3, ~p_dw_st~0=v_~p_dw_st~0_10} AuxVars[] AssignedVars[~p_dw_st~0, ~p_dw_pc~0] 15662#L247 [410] L247-->L266: Formula: (and (= 0 v_~c_dr_st~0_10) (= v_ULTIMATE.start_eval_~tmp___0~1_4 |v_ULTIMATE.start_eval_#t~nondet5_3|)) InVars {~c_dr_st~0=v_~c_dr_st~0_10, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_3|} OutVars{~c_dr_st~0=v_~c_dr_st~0_10, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_4, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_2|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp___0~1] 15659#L266 [480] L266-->L139: Formula: (and (= v_~c_dr_st~0_11 1) (> v_ULTIMATE.start_eval_~tmp___0~1_5 0)) InVars {ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_5} OutVars{~c_dr_st~0=v_~c_dr_st~0_11, ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_1, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_5} AuxVars[] AssignedVars[~c_dr_st~0, ULTIMATE.start_do_read_c_~a~0] 15658#L139 [483] L139-->L142: Formula: (< 0 v_~c_dr_pc~0_6) InVars {~c_dr_pc~0=v_~c_dr_pc~0_6} OutVars{~c_dr_pc~0=v_~c_dr_pc~0_6} AuxVars[] AssignedVars[] 15651#L142 [526] L142-->L152-1: Formula: (and (= v_~c_dr_pc~0_15 1) (= v_ULTIMATE.start_do_read_c_~a~0_6 v_~a_t~0_6)) InVars {~c_dr_pc~0=v_~c_dr_pc~0_15, ~a_t~0=v_~a_t~0_6} OutVars{ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_6, ~c_dr_pc~0=v_~c_dr_pc~0_15, ~a_t~0=v_~a_t~0_6} AuxVars[] AssignedVars[ULTIMATE.start_do_read_c_~a~0] 15581#L152-1 [412] L152-1-->L32-3: Formula: (and (= v_~c_num_read~0_3 (+ v_~c_num_read~0_4 1)) (= v_~q_read_ev~0_5 1) (= v_ULTIMATE.start_do_read_c_~a~0_5 v_~q_buf_0~0_3) (= v_~c_last_read~0_2 v_ULTIMATE.start_do_read_c_~a~0_5) (= v_~q_free~0_8 1)) InVars {~c_num_read~0=v_~c_num_read~0_4, ~q_buf_0~0=v_~q_buf_0~0_3} OutVars{~c_num_read~0=v_~c_num_read~0_3, ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_6, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_6, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_4|, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_4|, ~c_last_read~0=v_~c_last_read~0_2, ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_5, ~q_free~0=v_~q_free~0_8, ~q_buf_0~0=v_~q_buf_0~0_3, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_4|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_6, ~q_read_ev~0=v_~q_read_ev~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0, ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret1, ~c_last_read~0, ULTIMATE.start_do_read_c_~a~0, ~c_num_read~0, ~q_free~0, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0, ~q_read_ev~0] 15579#L32-3 [396] L32-3-->L33-1: Formula: (= v_~p_dw_pc~0_10 1) InVars {~p_dw_pc~0=v_~p_dw_pc~0_10} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_10} AuxVars[] AssignedVars[] 15401#L33-1 [346] L33-1-->L43-1: Formula: (and (= 1 v_~q_read_ev~0_6) (= v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_8 1)) InVars {~q_read_ev~0=v_~q_read_ev~0_6} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_8, ~q_read_ev~0=v_~q_read_ev~0_6} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0] 15403#L43-1 [531] L43-1-->L74-3: Formula: (and (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_8| v_ULTIMATE.start_immediate_notify_threads_~tmp~0_12) (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_8| v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_12)) InVars {ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_12} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_12, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_8|, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_8|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_12} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 15525#L74-3 [503] L74-3-->L74-5: Formula: (and (> v_ULTIMATE.start_immediate_notify_threads_~tmp~0_9 0) (= v_~p_dw_st~0_13 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_9} OutVars{~p_dw_st~0=v_~p_dw_st~0_13, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_9} AuxVars[] AssignedVars[~p_dw_st~0] 15524#L74-5 [332] L74-5-->L51-3: Formula: true InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_4|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_7} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_#res, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 15513#L51-3 [305] L51-3-->L52-1: Formula: (= v_~c_dr_pc~0_10 1) InVars {~c_dr_pc~0=v_~c_dr_pc~0_10} OutVars{~c_dr_pc~0=v_~c_dr_pc~0_10} AuxVars[] AssignedVars[] 15514#L52-1 [340] L52-1-->L62-1: Formula: (and (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_10 1) (= v_~q_write_ev~0_7 1)) InVars {~q_write_ev~0=v_~q_write_ev~0_7} OutVars{~q_write_ev~0=v_~q_write_ev~0_7, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_10} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 15505#L62-1 [533] L62-1-->L82-3: Formula: (and (= v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_12 |v_ULTIMATE.start_is_do_read_c_triggered_#res_8|) (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_14 |v_ULTIMATE.start_is_do_read_c_triggered_#res_8|)) InVars {ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_14} OutVars{ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_12, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_8|, ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_8|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_14} AuxVars[] AssignedVars[ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_immediate_notify_threads_#t~ret1, ULTIMATE.start_is_do_read_c_triggered_#res] 15506#L82-3 [514] L82-3-->L82-5: Formula: (and (> v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_9 0) (= v_~c_dr_st~0_13 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_9} OutVars{~c_dr_st~0=v_~c_dr_st~0_13, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_9} AuxVars[] AssignedVars[~c_dr_st~0] 15496#L82-5 [536] L82-5-->L10-2: Formula: (and (= v_~p_num_write~0_10 v_~c_num_read~0_10) (= 2 v_~q_read_ev~0_13) (= v_~c_last_read~0_8 v_~p_last_write~0_8)) InVars {~p_last_write~0=v_~p_last_write~0_8, ~c_last_read~0=v_~c_last_read~0_8, ~c_num_read~0=v_~c_num_read~0_10, ~p_num_write~0=v_~p_num_write~0_10} OutVars{~p_last_write~0=v_~p_last_write~0_8, ~c_last_read~0=v_~c_last_read~0_8, ~c_num_read~0=v_~c_num_read~0_10, ~p_num_write~0=v_~p_num_write~0_10, ~q_read_ev~0=v_~q_read_ev~0_13} AuxVars[] AssignedVars[~q_read_ev~0] 15497#L10-2 [400] L10-2-->L151: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 15488#L151 [380] L151-->L262: Formula: (and (= v_~c_dr_st~0_12 2) (= v_~c_dr_pc~0_9 1) (= v_~a_t~0_2 v_ULTIMATE.start_do_read_c_~a~0_3) (= v_~q_free~0_6 1)) InVars {ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_3, ~q_free~0=v_~q_free~0_6} OutVars{ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_3, ~c_dr_pc~0=v_~c_dr_pc~0_9, ~c_dr_st~0=v_~c_dr_st~0_12, ~q_free~0=v_~q_free~0_6, ~a_t~0=v_~a_t~0_2} AuxVars[] AssignedVars[~c_dr_pc~0, ~c_dr_st~0, ~a_t~0] 15485#L262 [522] L262-->L214: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 15477#L214 [406] L214-->L226: Formula: (and (= v_~p_dw_st~0_6 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11 1)) InVars {~p_dw_st~0=v_~p_dw_st~0_6} OutVars{~p_dw_st~0=v_~p_dw_st~0_6, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 15471#L226 [523] L226-->L242: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___1~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_5|, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp___1~0] 15468#L242 [468] L242-->L242-1: Formula: (> v_ULTIMATE.start_eval_~tmp___1~0_4 0) InVars {ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} OutVars{ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} AuxVars[] AssignedVars[] 15463#L242-1 [333] L242-1-->L251: Formula: (and (= v_ULTIMATE.start_eval_~tmp~1_3 |v_ULTIMATE.start_eval_#t~nondet4_3|) (= v_~p_dw_st~0_8 0)) InVars {ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_3|, ~p_dw_st~0=v_~p_dw_st~0_8} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_2|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_3, ~p_dw_st~0=v_~p_dw_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_~tmp~1] 15458#L251 [471] L251-->L96: Formula: (and (= v_~p_dw_st~0_9 1) (< v_ULTIMATE.start_eval_~tmp~1_4 0)) InVars {ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_4} OutVars{ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_4, ~p_dw_st~0=v_~p_dw_st~0_9, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_1|} AuxVars[] AssignedVars[~p_dw_st~0, ULTIMATE.start_do_write_p_#t~nondet2] 15459#L96 [478] L96-->L99: Formula: (> v_~p_dw_pc~0_4 0) InVars {~p_dw_pc~0=v_~p_dw_pc~0_4} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_4} AuxVars[] AssignedVars[] 15616#L99 [361] L99-->L109: Formula: (= v_~p_dw_pc~0_5 1) InVars {~p_dw_pc~0=v_~p_dw_pc~0_5} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_5} AuxVars[] AssignedVars[] 15456#L109 [323] L109-->L32: Formula: (and (= v_~q_buf_0~0_2 |v_ULTIMATE.start_do_write_p_#t~nondet2_3|) (= v_~p_last_write~0_2 v_~q_buf_0~0_2) (= v_~q_write_ev~0_3 1) (= v_~p_num_write~0_3 (+ v_~p_num_write~0_4 1)) (= v_~q_free~0_5 0)) InVars {~p_num_write~0=v_~p_num_write~0_4, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_3|} OutVars{~p_last_write~0=v_~p_last_write~0_2, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_2|, ~p_num_write~0=v_~p_num_write~0_3, ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_1, ~q_write_ev~0=v_~q_write_ev~0_3, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_1, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_1|, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_1|, ~q_free~0=v_~q_free~0_5, ~q_buf_0~0=v_~q_buf_0~0_2, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_1|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_1} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0, ~q_write_ev~0, ~p_last_write~0, ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_do_write_p_#t~nondet2, ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret1, ~p_num_write~0, ~q_free~0, ~q_buf_0~0, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 15457#L32 [489] L32-->L32-2: Formula: (< v_~p_dw_pc~0_9 1) InVars {~p_dw_pc~0=v_~p_dw_pc~0_9} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_9} AuxVars[] AssignedVars[] 15368#L32-2 [403] L32-2-->L43: Formula: (= v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_4 0) InVars {} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_4} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0] 15369#L43 [528] L43-->L74: Formula: (and (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_7| v_ULTIMATE.start_immediate_notify_threads_~tmp~0_11) (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_7| v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11)) InVars {ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_7|, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_7|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 15370#L74 [499] L74-->L74-2: Formula: (and (> v_ULTIMATE.start_immediate_notify_threads_~tmp~0_4 0) (= v_~p_dw_st~0_11 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_4} OutVars{~p_dw_st~0=v_~p_dw_st~0_11, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_4} AuxVars[] AssignedVars[~p_dw_st~0] 15398#L74-2 [339] L74-2-->L51: Formula: true InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_1|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_1} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_#res, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 15355#L51 [309] L51-->L52: Formula: (= 1 v_~c_dr_pc~0_3) InVars {~c_dr_pc~0=v_~c_dr_pc~0_3} OutVars{~c_dr_pc~0=v_~c_dr_pc~0_3} AuxVars[] AssignedVars[] 15356#L52 [343] L52-->L62: Formula: (and (= v_~q_write_ev~0_4 1) (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_4 1)) InVars {~q_write_ev~0=v_~q_write_ev~0_4} OutVars{~q_write_ev~0=v_~q_write_ev~0_4, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_4} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 15357#L62 37.10/18.54 [2019-03-28 12:18:45,485 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.54 [2019-03-28 12:18:45,485 INFO L82 PathProgramCache]: Analyzing trace with hash 1713705665, now seen corresponding path program 1 times 37.10/18.54 [2019-03-28 12:18:45,485 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.54 [2019-03-28 12:18:45,486 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.54 [2019-03-28 12:18:45,486 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:45,486 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:45,487 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:45,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 37.10/18.54 [2019-03-28 12:18:45,503 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 37.10/18.54 [2019-03-28 12:18:45,504 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 37.10/18.54 [2019-03-28 12:18:45,504 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 37.10/18.54 [2019-03-28 12:18:45,504 INFO L799 eck$LassoCheckResult]: stem already infeasible 37.10/18.54 [2019-03-28 12:18:45,504 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.54 [2019-03-28 12:18:45,504 INFO L82 PathProgramCache]: Analyzing trace with hash 201315666, now seen corresponding path program 1 times 37.10/18.54 [2019-03-28 12:18:45,505 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.54 [2019-03-28 12:18:45,505 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.54 [2019-03-28 12:18:45,505 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:45,505 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:45,506 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:45,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 37.10/18.54 [2019-03-28 12:18:45,532 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 37.10/18.54 [2019-03-28 12:18:45,532 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 37.10/18.54 [2019-03-28 12:18:45,532 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 37.10/18.54 [2019-03-28 12:18:45,532 INFO L811 eck$LassoCheckResult]: loop already infeasible 37.10/18.54 [2019-03-28 12:18:45,533 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 37.10/18.54 [2019-03-28 12:18:45,533 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 37.10/18.54 [2019-03-28 12:18:45,533 INFO L87 Difference]: Start difference. First operand 469 states and 749 transitions. cyclomatic complexity: 282 Second operand 3 states. 37.10/18.54 [2019-03-28 12:18:45,648 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 37.10/18.54 [2019-03-28 12:18:45,648 INFO L93 Difference]: Finished difference Result 748 states and 1165 transitions. 37.10/18.54 [2019-03-28 12:18:45,648 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 37.10/18.54 [2019-03-28 12:18:45,654 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 748 states and 1165 transitions. 37.10/18.54 [2019-03-28 12:18:45,658 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 713 37.10/18.54 [2019-03-28 12:18:45,662 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 748 states to 744 states and 1157 transitions. 37.10/18.54 [2019-03-28 12:18:45,663 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 644 37.10/18.54 [2019-03-28 12:18:45,663 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 644 37.10/18.54 [2019-03-28 12:18:45,663 INFO L73 IsDeterministic]: Start isDeterministic. Operand 744 states and 1157 transitions. 37.10/18.54 [2019-03-28 12:18:45,664 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. 37.10/18.54 [2019-03-28 12:18:45,664 INFO L706 BuchiCegarLoop]: Abstraction has 744 states and 1157 transitions. 37.10/18.54 [2019-03-28 12:18:45,664 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 744 states and 1157 transitions. 37.10/18.54 [2019-03-28 12:18:45,674 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 744 to 717. 37.10/18.54 [2019-03-28 12:18:45,675 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 717 states. 37.10/18.54 [2019-03-28 12:18:45,676 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 717 states to 717 states and 1117 transitions. 37.10/18.54 [2019-03-28 12:18:45,676 INFO L729 BuchiCegarLoop]: Abstraction has 717 states and 1117 transitions. 37.10/18.54 [2019-03-28 12:18:45,676 INFO L609 BuchiCegarLoop]: Abstraction has 717 states and 1117 transitions. 37.10/18.54 [2019-03-28 12:18:45,677 INFO L442 BuchiCegarLoop]: ======== Iteration 18============ 37.10/18.54 [2019-03-28 12:18:45,677 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 717 states and 1117 transitions. 37.10/18.54 [2019-03-28 12:18:45,680 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 690 37.10/18.54 [2019-03-28 12:18:45,680 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 37.10/18.54 [2019-03-28 12:18:45,680 INFO L119 BuchiIsEmpty]: Starting construction of run 37.10/18.54 [2019-03-28 12:18:45,681 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 37.10/18.54 [2019-03-28 12:18:45,681 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 37.10/18.54 [2019-03-28 12:18:45,681 INFO L794 eck$LassoCheckResult]: Stem: 16622#ULTIMATE.startENTRY [520] ULTIMATE.startENTRY-->L196: Formula: (and (= v_~q_write_ev~0_11 v_~q_read_ev~0_11) (= 1 v_~c_dr_i~0_7) (= v_~q_free~0_11 1) (= v_~q_buf_0~0_5 0) (= v_~q_write_ev~0_11 2) (= 0 v_~p_last_write~0_6) (= 0 v_~c_last_read~0_6) (= v_~p_dw_pc~0_14 0) (= 0 v_~a_t~0_5) (= 0 v_~c_dr_st~0_15) (= v_~c_dr_pc~0_14 0) (= 0 v_~c_num_read~0_9) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 0) (= 0 v_~p_num_write~0_9) (= v_~p_dw_i~0_7 1) (= v_~p_dw_st~0_15 0)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ~p_last_write~0=v_~p_last_write~0_6, ~c_dr_pc~0=v_~c_dr_pc~0_14, ~c_dr_st~0=v_~c_dr_st~0_15, ~c_num_read~0=v_~c_num_read~0_9, ~p_num_write~0=v_~p_num_write~0_9, ~c_dr_i~0=v_~c_dr_i~0_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7, ~q_write_ev~0=v_~q_write_ev~0_11, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~p_dw_st~0=v_~p_dw_st~0_15, ~p_dw_i~0=v_~p_dw_i~0_7, ~c_last_read~0=v_~c_last_read~0_6, ~p_dw_pc~0=v_~p_dw_pc~0_14, ~q_free~0=v_~q_free~0_11, ~q_buf_0~0=v_~q_buf_0~0_5, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6, ~q_read_ev~0=v_~q_read_ev~0_11, ~a_t~0=v_~a_t~0_5} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ~p_last_write~0, ~c_dr_pc~0, ~c_dr_st~0, ~c_num_read~0, ~p_num_write~0, ~c_dr_i~0, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_~kernel_st~0, ~q_write_ev~0, ULTIMATE.start_main_#res, ~p_dw_st~0, ~p_dw_i~0, ~c_last_read~0, ~p_dw_pc~0, ~q_free~0, ~q_buf_0~0, ULTIMATE.start_main_~__retres1~3, ~q_read_ev~0, ~a_t~0] 16623#L196 [418] L196-->L196-2: Formula: (and (= v_~p_dw_i~0_3 1) (= v_~p_dw_st~0_2 0)) InVars {~p_dw_i~0=v_~p_dw_i~0_3} OutVars{~p_dw_st~0=v_~p_dw_st~0_2, ~p_dw_i~0=v_~p_dw_i~0_3} AuxVars[] AssignedVars[~p_dw_st~0] 16660#L196-2 [413] L196-2-->L313-1: Formula: (and (= 1 v_~c_dr_i~0_3) (= v_~c_dr_st~0_3 0)) InVars {~c_dr_i~0=v_~c_dr_i~0_3} OutVars{~c_dr_st~0=v_~c_dr_st~0_3, ~c_dr_i~0=v_~c_dr_i~0_3} AuxVars[] AssignedVars[~c_dr_st~0] 16661#L313-1 [521] L313-1-->L262: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_8 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_8, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_4|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_6, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_6, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp~1, ULTIMATE.start_eval_~tmp___0~1, ULTIMATE.start_eval_~tmp___1~0] 16696#L262 [522] L262-->L214: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 16697#L214 [406] L214-->L226: Formula: (and (= v_~p_dw_st~0_6 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11 1)) InVars {~p_dw_st~0=v_~p_dw_st~0_6} OutVars{~p_dw_st~0=v_~p_dw_st~0_6, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 16688#L226 [523] L226-->L242: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___1~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_5|, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp___1~0] 16689#L242 [468] L242-->L242-1: Formula: (> v_ULTIMATE.start_eval_~tmp___1~0_4 0) InVars {ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} OutVars{ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} AuxVars[] AssignedVars[] 16682#L242-1 [333] L242-1-->L251: Formula: (and (= v_ULTIMATE.start_eval_~tmp~1_3 |v_ULTIMATE.start_eval_#t~nondet4_3|) (= v_~p_dw_st~0_8 0)) InVars {ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_3|, ~p_dw_st~0=v_~p_dw_st~0_8} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_2|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_3, ~p_dw_st~0=v_~p_dw_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_~tmp~1] 16683#L251 [472] L251-->L96: Formula: (and (= v_~p_dw_st~0_9 1) (> v_ULTIMATE.start_eval_~tmp~1_4 0)) InVars {ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_4} OutVars{ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_4, ~p_dw_st~0=v_~p_dw_st~0_9, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_1|} AuxVars[] AssignedVars[~p_dw_st~0, ULTIMATE.start_do_write_p_#t~nondet2] 16642#L96 [378] L96-->L107-1: Formula: (= v_~p_dw_pc~0_3 0) InVars {~p_dw_pc~0=v_~p_dw_pc~0_3} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_3} AuxVars[] AssignedVars[] 16643#L107-1 [375] L107-1-->L108: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 16717#L108 [486] L108-->L109: Formula: (> v_~q_free~0_4 0) InVars {~q_free~0=v_~q_free~0_4} OutVars{~q_free~0=v_~q_free~0_4} AuxVars[] AssignedVars[] 16603#L109 [323] L109-->L32: Formula: (and (= v_~q_buf_0~0_2 |v_ULTIMATE.start_do_write_p_#t~nondet2_3|) (= v_~p_last_write~0_2 v_~q_buf_0~0_2) (= v_~q_write_ev~0_3 1) (= v_~p_num_write~0_3 (+ v_~p_num_write~0_4 1)) (= v_~q_free~0_5 0)) InVars {~p_num_write~0=v_~p_num_write~0_4, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_3|} OutVars{~p_last_write~0=v_~p_last_write~0_2, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_2|, ~p_num_write~0=v_~p_num_write~0_3, ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_1, ~q_write_ev~0=v_~q_write_ev~0_3, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_1, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_1|, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_1|, ~q_free~0=v_~q_free~0_5, ~q_buf_0~0=v_~q_buf_0~0_2, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_1|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_1} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0, ~q_write_ev~0, ~p_last_write~0, ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_do_write_p_#t~nondet2, ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret1, ~p_num_write~0, ~q_free~0, ~q_buf_0~0, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 16604#L32 [489] L32-->L32-2: Formula: (< v_~p_dw_pc~0_9 1) InVars {~p_dw_pc~0=v_~p_dw_pc~0_9} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_9} AuxVars[] AssignedVars[] 16677#L32-2 [403] L32-2-->L43: Formula: (= v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_4 0) InVars {} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_4} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0] 16676#L43 [528] L43-->L74: Formula: (and (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_7| v_ULTIMATE.start_immediate_notify_threads_~tmp~0_11) (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_7| v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11)) InVars {ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_7|, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_7|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 16641#L74 [377] L74-->L74-2: Formula: (= v_ULTIMATE.start_immediate_notify_threads_~tmp~0_5 0) InVars {ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_5} OutVars{ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_5} AuxVars[] AssignedVars[] 16615#L74-2 [339] L74-2-->L51: Formula: true InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_1|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_1} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_#res, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 16578#L51 [502] L51-->L51-2: Formula: (> 1 v_~c_dr_pc~0_4) InVars {~c_dr_pc~0=v_~c_dr_pc~0_4} OutVars{~c_dr_pc~0=v_~c_dr_pc~0_4} AuxVars[] AssignedVars[] 16574#L51-2 [307] L51-2-->L62: Formula: (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 16575#L62 [532] L62-->L82: Formula: (and (= v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_11 |v_ULTIMATE.start_is_do_read_c_triggered_#res_7|) (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13 |v_ULTIMATE.start_is_do_read_c_triggered_#res_7|)) InVars {ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13} OutVars{ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_11, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_7|, ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_7|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13} AuxVars[] AssignedVars[ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_immediate_notify_threads_#t~ret1, ULTIMATE.start_is_do_read_c_triggered_#res] 16579#L82 [511] L82-->L82-2: Formula: (and (< v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_4 0) (= v_~c_dr_st~0_9 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_4} OutVars{~c_dr_st~0=v_~c_dr_st~0_9, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_4} AuxVars[] AssignedVars[~c_dr_st~0] 16639#L82-2 37.10/18.54 [2019-03-28 12:18:45,682 INFO L796 eck$LassoCheckResult]: Loop: 16639#L82-2 [366] L82-2-->L107-1: Formula: (= v_~q_write_ev~0_6 2) InVars {} OutVars{~q_write_ev~0=v_~q_write_ev~0_6} AuxVars[] AssignedVars[~q_write_ev~0] 17165#L107-1 [375] L107-1-->L108: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 16877#L108 [408] L108-->L247: Formula: (and (= v_~q_free~0_3 0) (= v_~p_dw_pc~0_7 1) (= v_~p_dw_st~0_10 2)) InVars {~q_free~0=v_~q_free~0_3} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_7, ~q_free~0=v_~q_free~0_3, ~p_dw_st~0=v_~p_dw_st~0_10} AuxVars[] AssignedVars[~p_dw_st~0, ~p_dw_pc~0] 16839#L247 [410] L247-->L266: Formula: (and (= 0 v_~c_dr_st~0_10) (= v_ULTIMATE.start_eval_~tmp___0~1_4 |v_ULTIMATE.start_eval_#t~nondet5_3|)) InVars {~c_dr_st~0=v_~c_dr_st~0_10, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_3|} OutVars{~c_dr_st~0=v_~c_dr_st~0_10, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_4, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_2|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp___0~1] 16840#L266 [480] L266-->L139: Formula: (and (= v_~c_dr_st~0_11 1) (> v_ULTIMATE.start_eval_~tmp___0~1_5 0)) InVars {ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_5} OutVars{~c_dr_st~0=v_~c_dr_st~0_11, ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_1, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_5} AuxVars[] AssignedVars[~c_dr_st~0, ULTIMATE.start_do_read_c_~a~0] 16828#L139 [348] L139-->L10-2: Formula: (= 0 v_~c_dr_pc~0_5) InVars {~c_dr_pc~0=v_~c_dr_pc~0_5} OutVars{~c_dr_pc~0=v_~c_dr_pc~0_5} AuxVars[] AssignedVars[] 16781#L10-2 [400] L10-2-->L151: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 16826#L151 [491] L151-->L152-1: Formula: (< v_~q_free~0_7 1) InVars {~q_free~0=v_~q_free~0_7} OutVars{~q_free~0=v_~q_free~0_7} AuxVars[] AssignedVars[] 16814#L152-1 [412] L152-1-->L32-3: Formula: (and (= v_~c_num_read~0_3 (+ v_~c_num_read~0_4 1)) (= v_~q_read_ev~0_5 1) (= v_ULTIMATE.start_do_read_c_~a~0_5 v_~q_buf_0~0_3) (= v_~c_last_read~0_2 v_ULTIMATE.start_do_read_c_~a~0_5) (= v_~q_free~0_8 1)) InVars {~c_num_read~0=v_~c_num_read~0_4, ~q_buf_0~0=v_~q_buf_0~0_3} OutVars{~c_num_read~0=v_~c_num_read~0_3, ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_6, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_6, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_4|, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_4|, ~c_last_read~0=v_~c_last_read~0_2, ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_5, ~q_free~0=v_~q_free~0_8, ~q_buf_0~0=v_~q_buf_0~0_3, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_4|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_6, ~q_read_ev~0=v_~q_read_ev~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0, ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret1, ~c_last_read~0, ULTIMATE.start_do_read_c_~a~0, ~c_num_read~0, ~q_free~0, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0, ~q_read_ev~0] 16825#L32-3 [496] L32-3-->L32-5: Formula: (> v_~p_dw_pc~0_11 1) InVars {~p_dw_pc~0=v_~p_dw_pc~0_11} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_11} AuxVars[] AssignedVars[] 16823#L32-5 [392] L32-5-->L43-1: Formula: (= v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_9 0) InVars {} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_9} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0] 16822#L43-1 [531] L43-1-->L74-3: Formula: (and (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_8| v_ULTIMATE.start_immediate_notify_threads_~tmp~0_12) (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_8| v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_12)) InVars {ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_12} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_12, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_8|, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_8|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_12} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 16820#L74-3 [503] L74-3-->L74-5: Formula: (and (> v_ULTIMATE.start_immediate_notify_threads_~tmp~0_9 0) (= v_~p_dw_st~0_13 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_9} OutVars{~p_dw_st~0=v_~p_dw_st~0_13, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_9} AuxVars[] AssignedVars[~p_dw_st~0] 16821#L74-5 [332] L74-5-->L51-3: Formula: true InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_4|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_7} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_#res, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 16852#L51-3 [508] L51-3-->L51-5: Formula: (< v_~c_dr_pc~0_11 1) InVars {~c_dr_pc~0=v_~c_dr_pc~0_11} OutVars{~c_dr_pc~0=v_~c_dr_pc~0_11} AuxVars[] AssignedVars[] 16761#L51-5 [327] L51-5-->L62-1: Formula: (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 16832#L62-1 [533] L62-1-->L82-3: Formula: (and (= v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_12 |v_ULTIMATE.start_is_do_read_c_triggered_#res_8|) (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_14 |v_ULTIMATE.start_is_do_read_c_triggered_#res_8|)) InVars {ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_14} OutVars{ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_12, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_8|, ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_8|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_14} AuxVars[] AssignedVars[ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_immediate_notify_threads_#t~ret1, ULTIMATE.start_is_do_read_c_triggered_#res] 16754#L82-3 [513] L82-3-->L82-5: Formula: (and (< v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_9 0) (= v_~c_dr_st~0_13 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_9} OutVars{~c_dr_st~0=v_~c_dr_st~0_13, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_9} AuxVars[] AssignedVars[~c_dr_st~0] 16739#L82-5 [536] L82-5-->L10-2: Formula: (and (= v_~p_num_write~0_10 v_~c_num_read~0_10) (= 2 v_~q_read_ev~0_13) (= v_~c_last_read~0_8 v_~p_last_write~0_8)) InVars {~p_last_write~0=v_~p_last_write~0_8, ~c_last_read~0=v_~c_last_read~0_8, ~c_num_read~0=v_~c_num_read~0_10, ~p_num_write~0=v_~p_num_write~0_10} OutVars{~p_last_write~0=v_~p_last_write~0_8, ~c_last_read~0=v_~c_last_read~0_8, ~c_num_read~0=v_~c_num_read~0_10, ~p_num_write~0=v_~p_num_write~0_10, ~q_read_ev~0=v_~q_read_ev~0_13} AuxVars[] AssignedVars[~q_read_ev~0] 16711#L10-2 [400] L10-2-->L151: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 16712#L151 [380] L151-->L262: Formula: (and (= v_~c_dr_st~0_12 2) (= v_~c_dr_pc~0_9 1) (= v_~a_t~0_2 v_ULTIMATE.start_do_read_c_~a~0_3) (= v_~q_free~0_6 1)) InVars {ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_3, ~q_free~0=v_~q_free~0_6} OutVars{ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_3, ~c_dr_pc~0=v_~c_dr_pc~0_9, ~c_dr_st~0=v_~c_dr_st~0_12, ~q_free~0=v_~q_free~0_6, ~a_t~0=v_~a_t~0_2} AuxVars[] AssignedVars[~c_dr_pc~0, ~c_dr_st~0, ~a_t~0] 16704#L262 [522] L262-->L214: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 16702#L214 [406] L214-->L226: Formula: (and (= v_~p_dw_st~0_6 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11 1)) InVars {~p_dw_st~0=v_~p_dw_st~0_6} OutVars{~p_dw_st~0=v_~p_dw_st~0_6, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 16698#L226 [523] L226-->L242: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___1~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_5|, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp___1~0] 16695#L242 [468] L242-->L242-1: Formula: (> v_ULTIMATE.start_eval_~tmp___1~0_4 0) InVars {ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} OutVars{ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} AuxVars[] AssignedVars[] 16692#L242-1 [333] L242-1-->L251: Formula: (and (= v_ULTIMATE.start_eval_~tmp~1_3 |v_ULTIMATE.start_eval_#t~nondet4_3|) (= v_~p_dw_st~0_8 0)) InVars {ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_3|, ~p_dw_st~0=v_~p_dw_st~0_8} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_2|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_3, ~p_dw_st~0=v_~p_dw_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_~tmp~1] 16650#L251 [471] L251-->L96: Formula: (and (= v_~p_dw_st~0_9 1) (< v_ULTIMATE.start_eval_~tmp~1_4 0)) InVars {ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_4} OutVars{ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_4, ~p_dw_st~0=v_~p_dw_st~0_9, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_1|} AuxVars[] AssignedVars[~p_dw_st~0, ULTIMATE.start_do_write_p_#t~nondet2] 16651#L96 [478] L96-->L99: Formula: (> v_~p_dw_pc~0_4 0) InVars {~p_dw_pc~0=v_~p_dw_pc~0_4} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_4} AuxVars[] AssignedVars[] 16687#L99 [361] L99-->L109: Formula: (= v_~p_dw_pc~0_5 1) InVars {~p_dw_pc~0=v_~p_dw_pc~0_5} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_5} AuxVars[] AssignedVars[] 16668#L109 [323] L109-->L32: Formula: (and (= v_~q_buf_0~0_2 |v_ULTIMATE.start_do_write_p_#t~nondet2_3|) (= v_~p_last_write~0_2 v_~q_buf_0~0_2) (= v_~q_write_ev~0_3 1) (= v_~p_num_write~0_3 (+ v_~p_num_write~0_4 1)) (= v_~q_free~0_5 0)) InVars {~p_num_write~0=v_~p_num_write~0_4, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_3|} OutVars{~p_last_write~0=v_~p_last_write~0_2, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_2|, ~p_num_write~0=v_~p_num_write~0_3, ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_1, ~q_write_ev~0=v_~q_write_ev~0_3, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_1, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_1|, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_1|, ~q_free~0=v_~q_free~0_5, ~q_buf_0~0=v_~q_buf_0~0_2, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_1|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_1} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0, ~q_write_ev~0, ~p_last_write~0, ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_do_write_p_#t~nondet2, ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret1, ~p_num_write~0, ~q_free~0, ~q_buf_0~0, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 16669#L32 [316] L32-->L33: Formula: (= v_~p_dw_pc~0_8 1) InVars {~p_dw_pc~0=v_~p_dw_pc~0_8} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_8} AuxVars[] AssignedVars[] 16691#L33 [352] L33-->L43: Formula: (and (= v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_3 1) (= 1 v_~q_read_ev~0_3)) InVars {~q_read_ev~0=v_~q_read_ev~0_3} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_3, ~q_read_ev~0=v_~q_read_ev~0_3} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0] 16593#L43 [528] L43-->L74: Formula: (and (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_7| v_ULTIMATE.start_immediate_notify_threads_~tmp~0_11) (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_7| v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11)) InVars {ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_7|, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_7|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 16594#L74 [499] L74-->L74-2: Formula: (and (> v_ULTIMATE.start_immediate_notify_threads_~tmp~0_4 0) (= v_~p_dw_st~0_11 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_4} OutVars{~p_dw_st~0=v_~p_dw_st~0_11, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_4} AuxVars[] AssignedVars[~p_dw_st~0] 16670#L74-2 [339] L74-2-->L51: Formula: true InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_1|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_1} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_#res, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 16671#L51 [502] L51-->L51-2: Formula: (> 1 v_~c_dr_pc~0_4) InVars {~c_dr_pc~0=v_~c_dr_pc~0_4} OutVars{~c_dr_pc~0=v_~c_dr_pc~0_4} AuxVars[] AssignedVars[] 17056#L51-2 [307] L51-2-->L62: Formula: (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 17174#L62 [532] L62-->L82: Formula: (and (= v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_11 |v_ULTIMATE.start_is_do_read_c_triggered_#res_7|) (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13 |v_ULTIMATE.start_is_do_read_c_triggered_#res_7|)) InVars {ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13} OutVars{ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_11, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_7|, ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_7|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13} AuxVars[] AssignedVars[ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_immediate_notify_threads_#t~ret1, ULTIMATE.start_is_do_read_c_triggered_#res] 17170#L82 [512] L82-->L82-2: Formula: (and (> v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_4 0) (= v_~c_dr_st~0_9 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_4} OutVars{~c_dr_st~0=v_~c_dr_st~0_9, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_4} AuxVars[] AssignedVars[~c_dr_st~0] 16639#L82-2 37.10/18.54 [2019-03-28 12:18:45,682 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.54 [2019-03-28 12:18:45,683 INFO L82 PathProgramCache]: Analyzing trace with hash 1904401767, now seen corresponding path program 1 times 37.10/18.54 [2019-03-28 12:18:45,683 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.54 [2019-03-28 12:18:45,683 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.54 [2019-03-28 12:18:45,684 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:45,684 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:45,684 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:45,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 37.10/18.54 [2019-03-28 12:18:45,702 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 37.10/18.54 [2019-03-28 12:18:45,703 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 37.10/18.54 [2019-03-28 12:18:45,703 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 37.10/18.54 [2019-03-28 12:18:45,703 INFO L799 eck$LassoCheckResult]: stem already infeasible 37.10/18.54 [2019-03-28 12:18:45,703 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.54 [2019-03-28 12:18:45,703 INFO L82 PathProgramCache]: Analyzing trace with hash -2127134446, now seen corresponding path program 1 times 37.10/18.54 [2019-03-28 12:18:45,704 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.54 [2019-03-28 12:18:45,704 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.54 [2019-03-28 12:18:45,704 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:45,705 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:45,705 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:45,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 37.10/18.54 [2019-03-28 12:18:45,718 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 37.10/18.54 [2019-03-28 12:18:45,718 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 37.10/18.54 [2019-03-28 12:18:45,718 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 37.10/18.54 [2019-03-28 12:18:45,719 INFO L811 eck$LassoCheckResult]: loop already infeasible 37.10/18.54 [2019-03-28 12:18:45,719 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. 37.10/18.54 [2019-03-28 12:18:45,719 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 37.10/18.54 [2019-03-28 12:18:45,719 INFO L87 Difference]: Start difference. First operand 717 states and 1117 transitions. cyclomatic complexity: 404 Second operand 4 states. 37.10/18.54 [2019-03-28 12:18:45,829 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 37.10/18.54 [2019-03-28 12:18:45,829 INFO L93 Difference]: Finished difference Result 717 states and 1100 transitions. 37.10/18.54 [2019-03-28 12:18:45,830 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. 37.10/18.54 [2019-03-28 12:18:45,835 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 717 states and 1100 transitions. 37.10/18.54 [2019-03-28 12:18:45,839 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 690 37.10/18.54 [2019-03-28 12:18:45,843 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 717 states to 717 states and 1100 transitions. 37.10/18.54 [2019-03-28 12:18:45,844 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 617 37.10/18.54 [2019-03-28 12:18:45,844 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 617 37.10/18.54 [2019-03-28 12:18:45,845 INFO L73 IsDeterministic]: Start isDeterministic. Operand 717 states and 1100 transitions. 37.10/18.54 [2019-03-28 12:18:45,845 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. 37.10/18.54 [2019-03-28 12:18:45,845 INFO L706 BuchiCegarLoop]: Abstraction has 717 states and 1100 transitions. 37.10/18.54 [2019-03-28 12:18:45,846 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 717 states and 1100 transitions. 37.10/18.54 [2019-03-28 12:18:45,858 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 717 to 717. 37.10/18.54 [2019-03-28 12:18:45,858 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 717 states. 37.10/18.54 [2019-03-28 12:18:45,860 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 717 states to 717 states and 1100 transitions. 37.10/18.54 [2019-03-28 12:18:45,860 INFO L729 BuchiCegarLoop]: Abstraction has 717 states and 1100 transitions. 37.10/18.54 [2019-03-28 12:18:45,860 INFO L609 BuchiCegarLoop]: Abstraction has 717 states and 1100 transitions. 37.10/18.54 [2019-03-28 12:18:45,860 INFO L442 BuchiCegarLoop]: ======== Iteration 19============ 37.10/18.54 [2019-03-28 12:18:45,861 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 717 states and 1100 transitions. 37.10/18.54 [2019-03-28 12:18:45,863 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 690 37.10/18.54 [2019-03-28 12:18:45,864 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 37.10/18.54 [2019-03-28 12:18:45,864 INFO L119 BuchiIsEmpty]: Starting construction of run 37.10/18.54 [2019-03-28 12:18:45,864 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 37.10/18.54 [2019-03-28 12:18:45,865 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 37.10/18.54 [2019-03-28 12:18:45,865 INFO L794 eck$LassoCheckResult]: Stem: 18072#ULTIMATE.startENTRY [520] ULTIMATE.startENTRY-->L196: Formula: (and (= v_~q_write_ev~0_11 v_~q_read_ev~0_11) (= 1 v_~c_dr_i~0_7) (= v_~q_free~0_11 1) (= v_~q_buf_0~0_5 0) (= v_~q_write_ev~0_11 2) (= 0 v_~p_last_write~0_6) (= 0 v_~c_last_read~0_6) (= v_~p_dw_pc~0_14 0) (= 0 v_~a_t~0_5) (= 0 v_~c_dr_st~0_15) (= v_~c_dr_pc~0_14 0) (= 0 v_~c_num_read~0_9) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 0) (= 0 v_~p_num_write~0_9) (= v_~p_dw_i~0_7 1) (= v_~p_dw_st~0_15 0)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ~p_last_write~0=v_~p_last_write~0_6, ~c_dr_pc~0=v_~c_dr_pc~0_14, ~c_dr_st~0=v_~c_dr_st~0_15, ~c_num_read~0=v_~c_num_read~0_9, ~p_num_write~0=v_~p_num_write~0_9, ~c_dr_i~0=v_~c_dr_i~0_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7, ~q_write_ev~0=v_~q_write_ev~0_11, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~p_dw_st~0=v_~p_dw_st~0_15, ~p_dw_i~0=v_~p_dw_i~0_7, ~c_last_read~0=v_~c_last_read~0_6, ~p_dw_pc~0=v_~p_dw_pc~0_14, ~q_free~0=v_~q_free~0_11, ~q_buf_0~0=v_~q_buf_0~0_5, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6, ~q_read_ev~0=v_~q_read_ev~0_11, ~a_t~0=v_~a_t~0_5} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ~p_last_write~0, ~c_dr_pc~0, ~c_dr_st~0, ~c_num_read~0, ~p_num_write~0, ~c_dr_i~0, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_~kernel_st~0, ~q_write_ev~0, ULTIMATE.start_main_#res, ~p_dw_st~0, ~p_dw_i~0, ~c_last_read~0, ~p_dw_pc~0, ~q_free~0, ~q_buf_0~0, ULTIMATE.start_main_~__retres1~3, ~q_read_ev~0, ~a_t~0] 18073#L196 [418] L196-->L196-2: Formula: (and (= v_~p_dw_i~0_3 1) (= v_~p_dw_st~0_2 0)) InVars {~p_dw_i~0=v_~p_dw_i~0_3} OutVars{~p_dw_st~0=v_~p_dw_st~0_2, ~p_dw_i~0=v_~p_dw_i~0_3} AuxVars[] AssignedVars[~p_dw_st~0] 18112#L196-2 [413] L196-2-->L313-1: Formula: (and (= 1 v_~c_dr_i~0_3) (= v_~c_dr_st~0_3 0)) InVars {~c_dr_i~0=v_~c_dr_i~0_3} OutVars{~c_dr_st~0=v_~c_dr_st~0_3, ~c_dr_i~0=v_~c_dr_i~0_3} AuxVars[] AssignedVars[~c_dr_st~0] 18113#L313-1 [521] L313-1-->L262: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_8 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_8, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_4|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_6, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_6, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp~1, ULTIMATE.start_eval_~tmp___0~1, ULTIMATE.start_eval_~tmp___1~0] 18197#L262 [522] L262-->L214: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 18190#L214 [406] L214-->L226: Formula: (and (= v_~p_dw_st~0_6 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11 1)) InVars {~p_dw_st~0=v_~p_dw_st~0_6} OutVars{~p_dw_st~0=v_~p_dw_st~0_6, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 18187#L226 [523] L226-->L242: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___1~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_5|, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp___1~0] 18137#L242 [468] L242-->L242-1: Formula: (> v_ULTIMATE.start_eval_~tmp___1~0_4 0) InVars {ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} OutVars{ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} AuxVars[] AssignedVars[] 18124#L242-1 [333] L242-1-->L251: Formula: (and (= v_ULTIMATE.start_eval_~tmp~1_3 |v_ULTIMATE.start_eval_#t~nondet4_3|) (= v_~p_dw_st~0_8 0)) InVars {ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_3|, ~p_dw_st~0=v_~p_dw_st~0_8} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_2|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_3, ~p_dw_st~0=v_~p_dw_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_~tmp~1] 18094#L251 [472] L251-->L96: Formula: (and (= v_~p_dw_st~0_9 1) (> v_ULTIMATE.start_eval_~tmp~1_4 0)) InVars {ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_4} OutVars{ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_4, ~p_dw_st~0=v_~p_dw_st~0_9, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_1|} AuxVars[] AssignedVars[~p_dw_st~0, ULTIMATE.start_do_write_p_#t~nondet2] 18086#L96 [378] L96-->L107-1: Formula: (= v_~p_dw_pc~0_3 0) InVars {~p_dw_pc~0=v_~p_dw_pc~0_3} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_3} AuxVars[] AssignedVars[] 18087#L107-1 [375] L107-1-->L108: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 18146#L108 [486] L108-->L109: Formula: (> v_~q_free~0_4 0) InVars {~q_free~0=v_~q_free~0_4} OutVars{~q_free~0=v_~q_free~0_4} AuxVars[] AssignedVars[] 18048#L109 [323] L109-->L32: Formula: (and (= v_~q_buf_0~0_2 |v_ULTIMATE.start_do_write_p_#t~nondet2_3|) (= v_~p_last_write~0_2 v_~q_buf_0~0_2) (= v_~q_write_ev~0_3 1) (= v_~p_num_write~0_3 (+ v_~p_num_write~0_4 1)) (= v_~q_free~0_5 0)) InVars {~p_num_write~0=v_~p_num_write~0_4, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_3|} OutVars{~p_last_write~0=v_~p_last_write~0_2, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_2|, ~p_num_write~0=v_~p_num_write~0_3, ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_1, ~q_write_ev~0=v_~q_write_ev~0_3, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_1, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_1|, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_1|, ~q_free~0=v_~q_free~0_5, ~q_buf_0~0=v_~q_buf_0~0_2, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_1|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_1} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0, ~q_write_ev~0, ~p_last_write~0, ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_do_write_p_#t~nondet2, ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret1, ~p_num_write~0, ~q_free~0, ~q_buf_0~0, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 18049#L32 [489] L32-->L32-2: Formula: (< v_~p_dw_pc~0_9 1) InVars {~p_dw_pc~0=v_~p_dw_pc~0_9} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_9} AuxVars[] AssignedVars[] 18135#L32-2 [403] L32-2-->L43: Formula: (= v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_4 0) InVars {} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_4} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0] 18134#L43 [528] L43-->L74: Formula: (and (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_7| v_ULTIMATE.start_immediate_notify_threads_~tmp~0_11) (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_7| v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11)) InVars {ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_7|, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_7|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 18129#L74 [377] L74-->L74-2: Formula: (= v_ULTIMATE.start_immediate_notify_threads_~tmp~0_5 0) InVars {ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_5} OutVars{ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_5} AuxVars[] AssignedVars[] 18127#L74-2 [339] L74-2-->L51: Formula: true InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_1|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_1} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_#res, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 18023#L51 [502] L51-->L51-2: Formula: (> 1 v_~c_dr_pc~0_4) InVars {~c_dr_pc~0=v_~c_dr_pc~0_4} OutVars{~c_dr_pc~0=v_~c_dr_pc~0_4} AuxVars[] AssignedVars[] 18019#L51-2 [307] L51-2-->L62: Formula: (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 18020#L62 [532] L62-->L82: Formula: (and (= v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_11 |v_ULTIMATE.start_is_do_read_c_triggered_#res_7|) (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13 |v_ULTIMATE.start_is_do_read_c_triggered_#res_7|)) InVars {ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13} OutVars{ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_11, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_7|, ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_7|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13} AuxVars[] AssignedVars[ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_immediate_notify_threads_#t~ret1, ULTIMATE.start_is_do_read_c_triggered_#res] 18024#L82 [369] L82-->L82-2: Formula: (= v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_5 0) InVars {ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_5} OutVars{ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_5} AuxVars[] AssignedVars[] 18083#L82-2 37.10/18.54 [2019-03-28 12:18:45,866 INFO L796 eck$LassoCheckResult]: Loop: 18083#L82-2 [366] L82-2-->L107-1: Formula: (= v_~q_write_ev~0_6 2) InVars {} OutVars{~q_write_ev~0=v_~q_write_ev~0_6} AuxVars[] AssignedVars[~q_write_ev~0] 18084#L107-1 [375] L107-1-->L108: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 18085#L108 [408] L108-->L247: Formula: (and (= v_~q_free~0_3 0) (= v_~p_dw_pc~0_7 1) (= v_~p_dw_st~0_10 2)) InVars {~q_free~0=v_~q_free~0_3} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_7, ~q_free~0=v_~q_free~0_3, ~p_dw_st~0=v_~p_dw_st~0_10} AuxVars[] AssignedVars[~p_dw_st~0, ~p_dw_pc~0] 18109#L247 [410] L247-->L266: Formula: (and (= 0 v_~c_dr_st~0_10) (= v_ULTIMATE.start_eval_~tmp___0~1_4 |v_ULTIMATE.start_eval_#t~nondet5_3|)) InVars {~c_dr_st~0=v_~c_dr_st~0_10, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_3|} OutVars{~c_dr_st~0=v_~c_dr_st~0_10, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_4, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_2|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp___0~1] 18110#L266 [480] L266-->L139: Formula: (and (= v_~c_dr_st~0_11 1) (> v_ULTIMATE.start_eval_~tmp___0~1_5 0)) InVars {ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_5} OutVars{~c_dr_st~0=v_~c_dr_st~0_11, ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_1, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_5} AuxVars[] AssignedVars[~c_dr_st~0, ULTIMATE.start_do_read_c_~a~0] 18074#L139 [348] L139-->L10-2: Formula: (= 0 v_~c_dr_pc~0_5) InVars {~c_dr_pc~0=v_~c_dr_pc~0_5} OutVars{~c_dr_pc~0=v_~c_dr_pc~0_5} AuxVars[] AssignedVars[] 18076#L10-2 [400] L10-2-->L151: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 18446#L151 [491] L151-->L152-1: Formula: (< v_~q_free~0_7 1) InVars {~q_free~0=v_~q_free~0_7} OutVars{~q_free~0=v_~q_free~0_7} AuxVars[] AssignedVars[] 18444#L152-1 [412] L152-1-->L32-3: Formula: (and (= v_~c_num_read~0_3 (+ v_~c_num_read~0_4 1)) (= v_~q_read_ev~0_5 1) (= v_ULTIMATE.start_do_read_c_~a~0_5 v_~q_buf_0~0_3) (= v_~c_last_read~0_2 v_ULTIMATE.start_do_read_c_~a~0_5) (= v_~q_free~0_8 1)) InVars {~c_num_read~0=v_~c_num_read~0_4, ~q_buf_0~0=v_~q_buf_0~0_3} OutVars{~c_num_read~0=v_~c_num_read~0_3, ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_6, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_6, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_4|, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_4|, ~c_last_read~0=v_~c_last_read~0_2, ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_5, ~q_free~0=v_~q_free~0_8, ~q_buf_0~0=v_~q_buf_0~0_3, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_4|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_6, ~q_read_ev~0=v_~q_read_ev~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0, ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret1, ~c_last_read~0, ULTIMATE.start_do_read_c_~a~0, ~c_num_read~0, ~q_free~0, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0, ~q_read_ev~0] 18442#L32-3 [496] L32-3-->L32-5: Formula: (> v_~p_dw_pc~0_11 1) InVars {~p_dw_pc~0=v_~p_dw_pc~0_11} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_11} AuxVars[] AssignedVars[] 18434#L32-5 [392] L32-5-->L43-1: Formula: (= v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_9 0) InVars {} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_9} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0] 18399#L43-1 [531] L43-1-->L74-3: Formula: (and (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_8| v_ULTIMATE.start_immediate_notify_threads_~tmp~0_12) (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_8| v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_12)) InVars {ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_12} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_12, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_8|, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_8|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_12} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 18394#L74-3 [503] L74-3-->L74-5: Formula: (and (> v_ULTIMATE.start_immediate_notify_threads_~tmp~0_9 0) (= v_~p_dw_st~0_13 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_9} OutVars{~p_dw_st~0=v_~p_dw_st~0_13, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_9} AuxVars[] AssignedVars[~p_dw_st~0] 18392#L74-5 [332] L74-5-->L51-3: Formula: true InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_4|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_7} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_#res, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 18363#L51-3 [508] L51-3-->L51-5: Formula: (< v_~c_dr_pc~0_11 1) InVars {~c_dr_pc~0=v_~c_dr_pc~0_11} OutVars{~c_dr_pc~0=v_~c_dr_pc~0_11} AuxVars[] AssignedVars[] 18362#L51-5 [327] L51-5-->L62-1: Formula: (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 18361#L62-1 [533] L62-1-->L82-3: Formula: (and (= v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_12 |v_ULTIMATE.start_is_do_read_c_triggered_#res_8|) (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_14 |v_ULTIMATE.start_is_do_read_c_triggered_#res_8|)) InVars {ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_14} OutVars{ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_12, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_8|, ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_8|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_14} AuxVars[] AssignedVars[ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_immediate_notify_threads_#t~ret1, ULTIMATE.start_is_do_read_c_triggered_#res] 18360#L82-3 [514] L82-3-->L82-5: Formula: (and (> v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_9 0) (= v_~c_dr_st~0_13 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_9} OutVars{~c_dr_st~0=v_~c_dr_st~0_13, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_9} AuxVars[] AssignedVars[~c_dr_st~0] 18359#L82-5 [536] L82-5-->L10-2: Formula: (and (= v_~p_num_write~0_10 v_~c_num_read~0_10) (= 2 v_~q_read_ev~0_13) (= v_~c_last_read~0_8 v_~p_last_write~0_8)) InVars {~p_last_write~0=v_~p_last_write~0_8, ~c_last_read~0=v_~c_last_read~0_8, ~c_num_read~0=v_~c_num_read~0_10, ~p_num_write~0=v_~p_num_write~0_10} OutVars{~p_last_write~0=v_~p_last_write~0_8, ~c_last_read~0=v_~c_last_read~0_8, ~c_num_read~0=v_~c_num_read~0_10, ~p_num_write~0=v_~p_num_write~0_10, ~q_read_ev~0=v_~q_read_ev~0_13} AuxVars[] AssignedVars[~q_read_ev~0] 18358#L10-2 [400] L10-2-->L151: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 18356#L151 [380] L151-->L262: Formula: (and (= v_~c_dr_st~0_12 2) (= v_~c_dr_pc~0_9 1) (= v_~a_t~0_2 v_ULTIMATE.start_do_read_c_~a~0_3) (= v_~q_free~0_6 1)) InVars {ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_3, ~q_free~0=v_~q_free~0_6} OutVars{ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_3, ~c_dr_pc~0=v_~c_dr_pc~0_9, ~c_dr_st~0=v_~c_dr_st~0_12, ~q_free~0=v_~q_free~0_6, ~a_t~0=v_~a_t~0_2} AuxVars[] AssignedVars[~c_dr_pc~0, ~c_dr_st~0, ~a_t~0] 18302#L262 [522] L262-->L214: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 18294#L214 [406] L214-->L226: Formula: (and (= v_~p_dw_st~0_6 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11 1)) InVars {~p_dw_st~0=v_~p_dw_st~0_6} OutVars{~p_dw_st~0=v_~p_dw_st~0_6, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 18286#L226 [523] L226-->L242: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___1~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_5|, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp___1~0] 18285#L242 [468] L242-->L242-1: Formula: (> v_ULTIMATE.start_eval_~tmp___1~0_4 0) InVars {ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} OutVars{ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} AuxVars[] AssignedVars[] 18136#L242-1 [333] L242-1-->L251: Formula: (and (= v_ULTIMATE.start_eval_~tmp~1_3 |v_ULTIMATE.start_eval_#t~nondet4_3|) (= v_~p_dw_st~0_8 0)) InVars {ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_3|, ~p_dw_st~0=v_~p_dw_st~0_8} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_2|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_3, ~p_dw_st~0=v_~p_dw_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_~tmp~1] 18120#L251 [471] L251-->L96: Formula: (and (= v_~p_dw_st~0_9 1) (< v_ULTIMATE.start_eval_~tmp~1_4 0)) InVars {ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_4} OutVars{ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_4, ~p_dw_st~0=v_~p_dw_st~0_9, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_1|} AuxVars[] AssignedVars[~p_dw_st~0, ULTIMATE.start_do_write_p_#t~nondet2] 18121#L96 [478] L96-->L99: Formula: (> v_~p_dw_pc~0_4 0) InVars {~p_dw_pc~0=v_~p_dw_pc~0_4} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_4} AuxVars[] AssignedVars[] 18131#L99 [361] L99-->L109: Formula: (= v_~p_dw_pc~0_5 1) InVars {~p_dw_pc~0=v_~p_dw_pc~0_5} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_5} AuxVars[] AssignedVars[] 18128#L109 [323] L109-->L32: Formula: (and (= v_~q_buf_0~0_2 |v_ULTIMATE.start_do_write_p_#t~nondet2_3|) (= v_~p_last_write~0_2 v_~q_buf_0~0_2) (= v_~q_write_ev~0_3 1) (= v_~p_num_write~0_3 (+ v_~p_num_write~0_4 1)) (= v_~q_free~0_5 0)) InVars {~p_num_write~0=v_~p_num_write~0_4, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_3|} OutVars{~p_last_write~0=v_~p_last_write~0_2, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_2|, ~p_num_write~0=v_~p_num_write~0_3, ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_1, ~q_write_ev~0=v_~q_write_ev~0_3, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_1, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_1|, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_1|, ~q_free~0=v_~q_free~0_5, ~q_buf_0~0=v_~q_buf_0~0_2, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_1|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_1} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0, ~q_write_ev~0, ~p_last_write~0, ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_do_write_p_#t~nondet2, ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret1, ~p_num_write~0, ~q_free~0, ~q_buf_0~0, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 18125#L32 [489] L32-->L32-2: Formula: (< v_~p_dw_pc~0_9 1) InVars {~p_dw_pc~0=v_~p_dw_pc~0_9} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_9} AuxVars[] AssignedVars[] 18033#L32-2 [403] L32-2-->L43: Formula: (= v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_4 0) InVars {} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_4} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0] 18276#L43 [528] L43-->L74: Formula: (and (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_7| v_ULTIMATE.start_immediate_notify_threads_~tmp~0_11) (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_7| v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11)) InVars {ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_7|, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_7|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 18275#L74 [499] L74-->L74-2: Formula: (and (> v_ULTIMATE.start_immediate_notify_threads_~tmp~0_4 0) (= v_~p_dw_st~0_11 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_4} OutVars{~p_dw_st~0=v_~p_dw_st~0_11, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_4} AuxVars[] AssignedVars[~p_dw_st~0] 18274#L74-2 [339] L74-2-->L51: Formula: true InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_1|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_1} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_#res, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 18116#L51 [502] L51-->L51-2: Formula: (> 1 v_~c_dr_pc~0_4) InVars {~c_dr_pc~0=v_~c_dr_pc~0_4} OutVars{~c_dr_pc~0=v_~c_dr_pc~0_4} AuxVars[] AssignedVars[] 18117#L51-2 [307] L51-2-->L62: Formula: (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 18651#L62 [532] L62-->L82: Formula: (and (= v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_11 |v_ULTIMATE.start_is_do_read_c_triggered_#res_7|) (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13 |v_ULTIMATE.start_is_do_read_c_triggered_#res_7|)) InVars {ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13} OutVars{ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_11, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_7|, ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_7|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13} AuxVars[] AssignedVars[ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_immediate_notify_threads_#t~ret1, ULTIMATE.start_is_do_read_c_triggered_#res] 18649#L82 [512] L82-->L82-2: Formula: (and (> v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_4 0) (= v_~c_dr_st~0_9 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_4} OutVars{~c_dr_st~0=v_~c_dr_st~0_9, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_4} AuxVars[] AssignedVars[~c_dr_st~0] 18083#L82-2 37.10/18.54 [2019-03-28 12:18:45,866 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.54 [2019-03-28 12:18:45,866 INFO L82 PathProgramCache]: Analyzing trace with hash 1904401625, now seen corresponding path program 1 times 37.10/18.54 [2019-03-28 12:18:45,867 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.54 [2019-03-28 12:18:45,867 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.54 [2019-03-28 12:18:45,867 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:45,867 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:45,868 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:45,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 37.10/18.54 [2019-03-28 12:18:45,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 37.10/18.54 [2019-03-28 12:18:45,884 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.54 [2019-03-28 12:18:45,885 INFO L82 PathProgramCache]: Analyzing trace with hash -338219061, now seen corresponding path program 1 times 37.10/18.54 [2019-03-28 12:18:45,885 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.54 [2019-03-28 12:18:45,886 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.54 [2019-03-28 12:18:45,886 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:45,886 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:45,887 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:45,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 37.10/18.54 [2019-03-28 12:18:45,916 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 37.10/18.54 [2019-03-28 12:18:45,917 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 37.10/18.54 [2019-03-28 12:18:45,917 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 37.10/18.54 [2019-03-28 12:18:45,917 INFO L811 eck$LassoCheckResult]: loop already infeasible 37.10/18.54 [2019-03-28 12:18:45,917 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 37.10/18.54 [2019-03-28 12:18:45,917 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 37.10/18.54 [2019-03-28 12:18:45,918 INFO L87 Difference]: Start difference. First operand 717 states and 1100 transitions. cyclomatic complexity: 387 Second operand 3 states. 37.10/18.54 [2019-03-28 12:18:45,983 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 37.10/18.54 [2019-03-28 12:18:45,984 INFO L93 Difference]: Finished difference Result 713 states and 1082 transitions. 37.10/18.54 [2019-03-28 12:18:45,985 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 37.10/18.54 [2019-03-28 12:18:45,990 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 713 states and 1082 transitions. 37.10/18.54 [2019-03-28 12:18:45,993 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 686 37.10/18.54 [2019-03-28 12:18:45,997 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 713 states to 713 states and 1082 transitions. 37.10/18.54 [2019-03-28 12:18:45,998 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 613 37.10/18.54 [2019-03-28 12:18:45,998 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 613 37.10/18.54 [2019-03-28 12:18:45,998 INFO L73 IsDeterministic]: Start isDeterministic. Operand 713 states and 1082 transitions. 37.10/18.54 [2019-03-28 12:18:45,999 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. 37.10/18.54 [2019-03-28 12:18:45,999 INFO L706 BuchiCegarLoop]: Abstraction has 713 states and 1082 transitions. 37.10/18.54 [2019-03-28 12:18:46,000 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 713 states and 1082 transitions. 37.10/18.54 [2019-03-28 12:18:46,009 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 713 to 713. 37.10/18.54 [2019-03-28 12:18:46,009 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 713 states. 37.10/18.54 [2019-03-28 12:18:46,011 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 713 states to 713 states and 1082 transitions. 37.10/18.54 [2019-03-28 12:18:46,011 INFO L729 BuchiCegarLoop]: Abstraction has 713 states and 1082 transitions. 37.10/18.54 [2019-03-28 12:18:46,011 INFO L609 BuchiCegarLoop]: Abstraction has 713 states and 1082 transitions. 37.10/18.54 [2019-03-28 12:18:46,011 INFO L442 BuchiCegarLoop]: ======== Iteration 20============ 37.10/18.54 [2019-03-28 12:18:46,011 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 713 states and 1082 transitions. 37.10/18.54 [2019-03-28 12:18:46,014 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 686 37.10/18.54 [2019-03-28 12:18:46,014 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 37.10/18.54 [2019-03-28 12:18:46,015 INFO L119 BuchiIsEmpty]: Starting construction of run 37.10/18.54 [2019-03-28 12:18:46,015 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 37.10/18.54 [2019-03-28 12:18:46,016 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 37.10/18.54 [2019-03-28 12:18:46,016 INFO L794 eck$LassoCheckResult]: Stem: 19505#ULTIMATE.startENTRY [520] ULTIMATE.startENTRY-->L196: Formula: (and (= v_~q_write_ev~0_11 v_~q_read_ev~0_11) (= 1 v_~c_dr_i~0_7) (= v_~q_free~0_11 1) (= v_~q_buf_0~0_5 0) (= v_~q_write_ev~0_11 2) (= 0 v_~p_last_write~0_6) (= 0 v_~c_last_read~0_6) (= v_~p_dw_pc~0_14 0) (= 0 v_~a_t~0_5) (= 0 v_~c_dr_st~0_15) (= v_~c_dr_pc~0_14 0) (= 0 v_~c_num_read~0_9) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 0) (= 0 v_~p_num_write~0_9) (= v_~p_dw_i~0_7 1) (= v_~p_dw_st~0_15 0)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ~p_last_write~0=v_~p_last_write~0_6, ~c_dr_pc~0=v_~c_dr_pc~0_14, ~c_dr_st~0=v_~c_dr_st~0_15, ~c_num_read~0=v_~c_num_read~0_9, ~p_num_write~0=v_~p_num_write~0_9, ~c_dr_i~0=v_~c_dr_i~0_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7, ~q_write_ev~0=v_~q_write_ev~0_11, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~p_dw_st~0=v_~p_dw_st~0_15, ~p_dw_i~0=v_~p_dw_i~0_7, ~c_last_read~0=v_~c_last_read~0_6, ~p_dw_pc~0=v_~p_dw_pc~0_14, ~q_free~0=v_~q_free~0_11, ~q_buf_0~0=v_~q_buf_0~0_5, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6, ~q_read_ev~0=v_~q_read_ev~0_11, ~a_t~0=v_~a_t~0_5} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ~p_last_write~0, ~c_dr_pc~0, ~c_dr_st~0, ~c_num_read~0, ~p_num_write~0, ~c_dr_i~0, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_~kernel_st~0, ~q_write_ev~0, ULTIMATE.start_main_#res, ~p_dw_st~0, ~p_dw_i~0, ~c_last_read~0, ~p_dw_pc~0, ~q_free~0, ~q_buf_0~0, ULTIMATE.start_main_~__retres1~3, ~q_read_ev~0, ~a_t~0] 19506#L196 [418] L196-->L196-2: Formula: (and (= v_~p_dw_i~0_3 1) (= v_~p_dw_st~0_2 0)) InVars {~p_dw_i~0=v_~p_dw_i~0_3} OutVars{~p_dw_st~0=v_~p_dw_st~0_2, ~p_dw_i~0=v_~p_dw_i~0_3} AuxVars[] AssignedVars[~p_dw_st~0] 19548#L196-2 [413] L196-2-->L313-1: Formula: (and (= 1 v_~c_dr_i~0_3) (= v_~c_dr_st~0_3 0)) InVars {~c_dr_i~0=v_~c_dr_i~0_3} OutVars{~c_dr_st~0=v_~c_dr_st~0_3, ~c_dr_i~0=v_~c_dr_i~0_3} AuxVars[] AssignedVars[~c_dr_st~0] 19549#L313-1 [521] L313-1-->L262: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_8 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_8, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_4|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_6, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_6, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp~1, ULTIMATE.start_eval_~tmp___0~1, ULTIMATE.start_eval_~tmp___1~0] 19575#L262 [522] L262-->L214: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 19574#L214 [406] L214-->L226: Formula: (and (= v_~p_dw_st~0_6 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11 1)) InVars {~p_dw_st~0=v_~p_dw_st~0_6} OutVars{~p_dw_st~0=v_~p_dw_st~0_6, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 19573#L226 [523] L226-->L242: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___1~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_5|, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp___1~0] 19572#L242 [468] L242-->L242-1: Formula: (> v_ULTIMATE.start_eval_~tmp___1~0_4 0) InVars {ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} OutVars{ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} AuxVars[] AssignedVars[] 19571#L242-1 [333] L242-1-->L251: Formula: (and (= v_ULTIMATE.start_eval_~tmp~1_3 |v_ULTIMATE.start_eval_#t~nondet4_3|) (= v_~p_dw_st~0_8 0)) InVars {ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_3|, ~p_dw_st~0=v_~p_dw_st~0_8} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_2|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_3, ~p_dw_st~0=v_~p_dw_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_~tmp~1] 19570#L251 [472] L251-->L96: Formula: (and (= v_~p_dw_st~0_9 1) (> v_ULTIMATE.start_eval_~tmp~1_4 0)) InVars {ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_4} OutVars{ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_4, ~p_dw_st~0=v_~p_dw_st~0_9, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_1|} AuxVars[] AssignedVars[~p_dw_st~0, ULTIMATE.start_do_write_p_#t~nondet2] 19569#L96 [378] L96-->L107-1: Formula: (= v_~p_dw_pc~0_3 0) InVars {~p_dw_pc~0=v_~p_dw_pc~0_3} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_3} AuxVars[] AssignedVars[] 19568#L107-1 [375] L107-1-->L108: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 19567#L108 [486] L108-->L109: Formula: (> v_~q_free~0_4 0) InVars {~q_free~0=v_~q_free~0_4} OutVars{~q_free~0=v_~q_free~0_4} AuxVars[] AssignedVars[] 19566#L109 [323] L109-->L32: Formula: (and (= v_~q_buf_0~0_2 |v_ULTIMATE.start_do_write_p_#t~nondet2_3|) (= v_~p_last_write~0_2 v_~q_buf_0~0_2) (= v_~q_write_ev~0_3 1) (= v_~p_num_write~0_3 (+ v_~p_num_write~0_4 1)) (= v_~q_free~0_5 0)) InVars {~p_num_write~0=v_~p_num_write~0_4, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_3|} OutVars{~p_last_write~0=v_~p_last_write~0_2, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_2|, ~p_num_write~0=v_~p_num_write~0_3, ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_1, ~q_write_ev~0=v_~q_write_ev~0_3, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_1, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_1|, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_1|, ~q_free~0=v_~q_free~0_5, ~q_buf_0~0=v_~q_buf_0~0_2, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_1|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_1} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0, ~q_write_ev~0, ~p_last_write~0, ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_do_write_p_#t~nondet2, ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret1, ~p_num_write~0, ~q_free~0, ~q_buf_0~0, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 19565#L32 [489] L32-->L32-2: Formula: (< v_~p_dw_pc~0_9 1) InVars {~p_dw_pc~0=v_~p_dw_pc~0_9} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_9} AuxVars[] AssignedVars[] 19564#L32-2 [403] L32-2-->L43: Formula: (= v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_4 0) InVars {} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_4} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0] 19563#L43 [528] L43-->L74: Formula: (and (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_7| v_ULTIMATE.start_immediate_notify_threads_~tmp~0_11) (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_7| v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11)) InVars {ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_7|, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_7|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 19562#L74 [377] L74-->L74-2: Formula: (= v_ULTIMATE.start_immediate_notify_threads_~tmp~0_5 0) InVars {ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_5} OutVars{ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_5} AuxVars[] AssignedVars[] 19561#L74-2 [339] L74-2-->L51: Formula: true InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_1|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_1} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_#res, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 19459#L51 [502] L51-->L51-2: Formula: (> 1 v_~c_dr_pc~0_4) InVars {~c_dr_pc~0=v_~c_dr_pc~0_4} OutVars{~c_dr_pc~0=v_~c_dr_pc~0_4} AuxVars[] AssignedVars[] 19460#L51-2 [307] L51-2-->L62: Formula: (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 20136#L62 [532] L62-->L82: Formula: (and (= v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_11 |v_ULTIMATE.start_is_do_read_c_triggered_#res_7|) (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13 |v_ULTIMATE.start_is_do_read_c_triggered_#res_7|)) InVars {ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13} OutVars{ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_11, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_7|, ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_7|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13} AuxVars[] AssignedVars[ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_immediate_notify_threads_#t~ret1, ULTIMATE.start_is_do_read_c_triggered_#res] 20135#L82 [369] L82-->L82-2: Formula: (= v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_5 0) InVars {ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_5} OutVars{ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_5} AuxVars[] AssignedVars[] 19519#L82-2 37.10/18.54 [2019-03-28 12:18:46,017 INFO L796 eck$LassoCheckResult]: Loop: 19519#L82-2 [366] L82-2-->L107-1: Formula: (= v_~q_write_ev~0_6 2) InVars {} OutVars{~q_write_ev~0=v_~q_write_ev~0_6} AuxVars[] AssignedVars[~q_write_ev~0] 20133#L107-1 [375] L107-1-->L108: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 20132#L108 [408] L108-->L247: Formula: (and (= v_~q_free~0_3 0) (= v_~p_dw_pc~0_7 1) (= v_~p_dw_st~0_10 2)) InVars {~q_free~0=v_~q_free~0_3} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_7, ~q_free~0=v_~q_free~0_3, ~p_dw_st~0=v_~p_dw_st~0_10} AuxVars[] AssignedVars[~p_dw_st~0, ~p_dw_pc~0] 19816#L247 [410] L247-->L266: Formula: (and (= 0 v_~c_dr_st~0_10) (= v_ULTIMATE.start_eval_~tmp___0~1_4 |v_ULTIMATE.start_eval_#t~nondet5_3|)) InVars {~c_dr_st~0=v_~c_dr_st~0_10, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_3|} OutVars{~c_dr_st~0=v_~c_dr_st~0_10, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_4, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_2|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp___0~1] 19814#L266 [480] L266-->L139: Formula: (and (= v_~c_dr_st~0_11 1) (> v_ULTIMATE.start_eval_~tmp___0~1_5 0)) InVars {ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_5} OutVars{~c_dr_st~0=v_~c_dr_st~0_11, ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_1, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_5} AuxVars[] AssignedVars[~c_dr_st~0, ULTIMATE.start_do_read_c_~a~0] 19813#L139 [348] L139-->L10-2: Formula: (= 0 v_~c_dr_pc~0_5) InVars {~c_dr_pc~0=v_~c_dr_pc~0_5} OutVars{~c_dr_pc~0=v_~c_dr_pc~0_5} AuxVars[] AssignedVars[] 19687#L10-2 [400] L10-2-->L151: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 19724#L151 [491] L151-->L152-1: Formula: (< v_~q_free~0_7 1) InVars {~q_free~0=v_~q_free~0_7} OutVars{~q_free~0=v_~q_free~0_7} AuxVars[] AssignedVars[] 19725#L152-1 [412] L152-1-->L32-3: Formula: (and (= v_~c_num_read~0_3 (+ v_~c_num_read~0_4 1)) (= v_~q_read_ev~0_5 1) (= v_ULTIMATE.start_do_read_c_~a~0_5 v_~q_buf_0~0_3) (= v_~c_last_read~0_2 v_ULTIMATE.start_do_read_c_~a~0_5) (= v_~q_free~0_8 1)) InVars {~c_num_read~0=v_~c_num_read~0_4, ~q_buf_0~0=v_~q_buf_0~0_3} OutVars{~c_num_read~0=v_~c_num_read~0_3, ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_6, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_6, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_4|, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_4|, ~c_last_read~0=v_~c_last_read~0_2, ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_5, ~q_free~0=v_~q_free~0_8, ~q_buf_0~0=v_~q_buf_0~0_3, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_4|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_6, ~q_read_ev~0=v_~q_read_ev~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0, ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret1, ~c_last_read~0, ULTIMATE.start_do_read_c_~a~0, ~c_num_read~0, ~q_free~0, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0, ~q_read_ev~0] 20052#L32-3 [396] L32-3-->L33-1: Formula: (= v_~p_dw_pc~0_10 1) InVars {~p_dw_pc~0=v_~p_dw_pc~0_10} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_10} AuxVars[] AssignedVars[] 19507#L33-1 [346] L33-1-->L43-1: Formula: (and (= 1 v_~q_read_ev~0_6) (= v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_8 1)) InVars {~q_read_ev~0=v_~q_read_ev~0_6} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_8, ~q_read_ev~0=v_~q_read_ev~0_6} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0] 19509#L43-1 [531] L43-1-->L74-3: Formula: (and (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_8| v_ULTIMATE.start_immediate_notify_threads_~tmp~0_12) (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_8| v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_12)) InVars {ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_12} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_12, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_8|, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_8|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_12} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 19717#L74-3 [503] L74-3-->L74-5: Formula: (and (> v_ULTIMATE.start_immediate_notify_threads_~tmp~0_9 0) (= v_~p_dw_st~0_13 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_9} OutVars{~p_dw_st~0=v_~p_dw_st~0_13, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_9} AuxVars[] AssignedVars[~p_dw_st~0] 19713#L74-5 [332] L74-5-->L51-3: Formula: true InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_4|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_7} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_#res, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 19710#L51-3 [508] L51-3-->L51-5: Formula: (< v_~c_dr_pc~0_11 1) InVars {~c_dr_pc~0=v_~c_dr_pc~0_11} OutVars{~c_dr_pc~0=v_~c_dr_pc~0_11} AuxVars[] AssignedVars[] 19626#L51-5 [327] L51-5-->L62-1: Formula: (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 19698#L62-1 [533] L62-1-->L82-3: Formula: (and (= v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_12 |v_ULTIMATE.start_is_do_read_c_triggered_#res_8|) (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_14 |v_ULTIMATE.start_is_do_read_c_triggered_#res_8|)) InVars {ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_14} OutVars{ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_12, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_8|, ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_8|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_14} AuxVars[] AssignedVars[ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_immediate_notify_threads_#t~ret1, ULTIMATE.start_is_do_read_c_triggered_#res] 19610#L82-3 [514] L82-3-->L82-5: Formula: (and (> v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_9 0) (= v_~c_dr_st~0_13 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_9} OutVars{~c_dr_st~0=v_~c_dr_st~0_13, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_9} AuxVars[] AssignedVars[~c_dr_st~0] 19611#L82-5 [536] L82-5-->L10-2: Formula: (and (= v_~p_num_write~0_10 v_~c_num_read~0_10) (= 2 v_~q_read_ev~0_13) (= v_~c_last_read~0_8 v_~p_last_write~0_8)) InVars {~p_last_write~0=v_~p_last_write~0_8, ~c_last_read~0=v_~c_last_read~0_8, ~c_num_read~0=v_~c_num_read~0_10, ~p_num_write~0=v_~p_num_write~0_10} OutVars{~p_last_write~0=v_~p_last_write~0_8, ~c_last_read~0=v_~c_last_read~0_8, ~c_num_read~0=v_~c_num_read~0_10, ~p_num_write~0=v_~p_num_write~0_10, ~q_read_ev~0=v_~q_read_ev~0_13} AuxVars[] AssignedVars[~q_read_ev~0] 19697#L10-2 [400] L10-2-->L151: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 19690#L151 [380] L151-->L262: Formula: (and (= v_~c_dr_st~0_12 2) (= v_~c_dr_pc~0_9 1) (= v_~a_t~0_2 v_ULTIMATE.start_do_read_c_~a~0_3) (= v_~q_free~0_6 1)) InVars {ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_3, ~q_free~0=v_~q_free~0_6} OutVars{ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_3, ~c_dr_pc~0=v_~c_dr_pc~0_9, ~c_dr_st~0=v_~c_dr_st~0_12, ~q_free~0=v_~q_free~0_6, ~a_t~0=v_~a_t~0_2} AuxVars[] AssignedVars[~c_dr_pc~0, ~c_dr_st~0, ~a_t~0] 19593#L262 [522] L262-->L214: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 19591#L214 [406] L214-->L226: Formula: (and (= v_~p_dw_st~0_6 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11 1)) InVars {~p_dw_st~0=v_~p_dw_st~0_6} OutVars{~p_dw_st~0=v_~p_dw_st~0_6, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 19589#L226 [523] L226-->L242: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___1~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_5|, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp___1~0] 19587#L242 [468] L242-->L242-1: Formula: (> v_ULTIMATE.start_eval_~tmp___1~0_4 0) InVars {ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} OutVars{ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} AuxVars[] AssignedVars[] 19576#L242-1 [333] L242-1-->L251: Formula: (and (= v_ULTIMATE.start_eval_~tmp~1_3 |v_ULTIMATE.start_eval_#t~nondet4_3|) (= v_~p_dw_st~0_8 0)) InVars {ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_3|, ~p_dw_st~0=v_~p_dw_st~0_8} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_2|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_3, ~p_dw_st~0=v_~p_dw_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_~tmp~1] 19577#L251 [471] L251-->L96: Formula: (and (= v_~p_dw_st~0_9 1) (< v_ULTIMATE.start_eval_~tmp~1_4 0)) InVars {ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_4} OutVars{ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_4, ~p_dw_st~0=v_~p_dw_st~0_9, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_1|} AuxVars[] AssignedVars[~p_dw_st~0, ULTIMATE.start_do_write_p_#t~nondet2] 19554#L96 [478] L96-->L99: Formula: (> v_~p_dw_pc~0_4 0) InVars {~p_dw_pc~0=v_~p_dw_pc~0_4} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_4} AuxVars[] AssignedVars[] 19555#L99 [361] L99-->L109: Formula: (= v_~p_dw_pc~0_5 1) InVars {~p_dw_pc~0=v_~p_dw_pc~0_5} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_5} AuxVars[] AssignedVars[] 19557#L109 [323] L109-->L32: Formula: (and (= v_~q_buf_0~0_2 |v_ULTIMATE.start_do_write_p_#t~nondet2_3|) (= v_~p_last_write~0_2 v_~q_buf_0~0_2) (= v_~q_write_ev~0_3 1) (= v_~p_num_write~0_3 (+ v_~p_num_write~0_4 1)) (= v_~q_free~0_5 0)) InVars {~p_num_write~0=v_~p_num_write~0_4, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_3|} OutVars{~p_last_write~0=v_~p_last_write~0_2, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_2|, ~p_num_write~0=v_~p_num_write~0_3, ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_1, ~q_write_ev~0=v_~q_write_ev~0_3, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_1, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_1|, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_1|, ~q_free~0=v_~q_free~0_5, ~q_buf_0~0=v_~q_buf_0~0_2, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_1|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_1} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0, ~q_write_ev~0, ~p_last_write~0, ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_do_write_p_#t~nondet2, ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret1, ~p_num_write~0, ~q_free~0, ~q_buf_0~0, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 19558#L32 [316] L32-->L33: Formula: (= v_~p_dw_pc~0_8 1) InVars {~p_dw_pc~0=v_~p_dw_pc~0_8} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_8} AuxVars[] AssignedVars[] 19578#L33 [352] L33-->L43: Formula: (and (= v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_3 1) (= 1 v_~q_read_ev~0_3)) InVars {~q_read_ev~0=v_~q_read_ev~0_3} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_3, ~q_read_ev~0=v_~q_read_ev~0_3} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0] 19766#L43 [528] L43-->L74: Formula: (and (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_7| v_ULTIMATE.start_immediate_notify_threads_~tmp~0_11) (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_7| v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11)) InVars {ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_7|, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_7|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 19765#L74 [499] L74-->L74-2: Formula: (and (> v_ULTIMATE.start_immediate_notify_threads_~tmp~0_4 0) (= v_~p_dw_st~0_11 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_4} OutVars{~p_dw_st~0=v_~p_dw_st~0_11, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_4} AuxVars[] AssignedVars[~p_dw_st~0] 19764#L74-2 [339] L74-2-->L51: Formula: true InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_1|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_1} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_#res, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 19763#L51 [502] L51-->L51-2: Formula: (> 1 v_~c_dr_pc~0_4) InVars {~c_dr_pc~0=v_~c_dr_pc~0_4} OutVars{~c_dr_pc~0=v_~c_dr_pc~0_4} AuxVars[] AssignedVars[] 19455#L51-2 [307] L51-2-->L62: Formula: (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 19456#L62 [532] L62-->L82: Formula: (and (= v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_11 |v_ULTIMATE.start_is_do_read_c_triggered_#res_7|) (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13 |v_ULTIMATE.start_is_do_read_c_triggered_#res_7|)) InVars {ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13} OutVars{ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_11, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_7|, ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_7|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13} AuxVars[] AssignedVars[ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_immediate_notify_threads_#t~ret1, ULTIMATE.start_is_do_read_c_triggered_#res] 19461#L82 [512] L82-->L82-2: Formula: (and (> v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_4 0) (= v_~c_dr_st~0_9 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_4} OutVars{~c_dr_st~0=v_~c_dr_st~0_9, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_4} AuxVars[] AssignedVars[~c_dr_st~0] 19519#L82-2 37.10/18.54 [2019-03-28 12:18:46,018 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.54 [2019-03-28 12:18:46,018 INFO L82 PathProgramCache]: Analyzing trace with hash 1904401625, now seen corresponding path program 2 times 37.10/18.54 [2019-03-28 12:18:46,018 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.54 [2019-03-28 12:18:46,018 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.54 [2019-03-28 12:18:46,019 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:46,019 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:46,019 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:46,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 37.10/18.54 [2019-03-28 12:18:46,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 37.10/18.54 [2019-03-28 12:18:46,034 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.54 [2019-03-28 12:18:46,034 INFO L82 PathProgramCache]: Analyzing trace with hash 1475224167, now seen corresponding path program 1 times 37.10/18.54 [2019-03-28 12:18:46,034 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.54 [2019-03-28 12:18:46,034 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.54 [2019-03-28 12:18:46,035 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:46,035 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:46,035 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:46,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 37.10/18.54 [2019-03-28 12:18:46,056 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 37.10/18.54 [2019-03-28 12:18:46,057 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 37.10/18.54 [2019-03-28 12:18:46,057 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 37.10/18.54 [2019-03-28 12:18:46,057 INFO L811 eck$LassoCheckResult]: loop already infeasible 37.10/18.54 [2019-03-28 12:18:46,057 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 37.10/18.54 [2019-03-28 12:18:46,057 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 37.10/18.54 [2019-03-28 12:18:46,058 INFO L87 Difference]: Start difference. First operand 713 states and 1082 transitions. cyclomatic complexity: 373 Second operand 3 states. 37.10/18.54 [2019-03-28 12:18:46,131 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 37.10/18.54 [2019-03-28 12:18:46,132 INFO L93 Difference]: Finished difference Result 797 states and 1202 transitions. 37.10/18.54 [2019-03-28 12:18:46,132 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 37.10/18.54 [2019-03-28 12:18:46,139 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 797 states and 1202 transitions. 37.10/18.54 [2019-03-28 12:18:46,143 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 770 37.10/18.54 [2019-03-28 12:18:46,148 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 797 states to 797 states and 1202 transitions. 37.10/18.54 [2019-03-28 12:18:46,149 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 697 37.10/18.54 [2019-03-28 12:18:46,149 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 697 37.10/18.54 [2019-03-28 12:18:46,149 INFO L73 IsDeterministic]: Start isDeterministic. Operand 797 states and 1202 transitions. 37.10/18.54 [2019-03-28 12:18:46,150 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. 37.10/18.54 [2019-03-28 12:18:46,150 INFO L706 BuchiCegarLoop]: Abstraction has 797 states and 1202 transitions. 37.10/18.54 [2019-03-28 12:18:46,150 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 797 states and 1202 transitions. 37.10/18.54 [2019-03-28 12:18:46,161 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 797 to 713. 37.10/18.54 [2019-03-28 12:18:46,162 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 713 states. 37.10/18.54 [2019-03-28 12:18:46,163 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 713 states to 713 states and 1078 transitions. 37.10/18.54 [2019-03-28 12:18:46,163 INFO L729 BuchiCegarLoop]: Abstraction has 713 states and 1078 transitions. 37.10/18.54 [2019-03-28 12:18:46,164 INFO L609 BuchiCegarLoop]: Abstraction has 713 states and 1078 transitions. 37.10/18.54 [2019-03-28 12:18:46,164 INFO L442 BuchiCegarLoop]: ======== Iteration 21============ 37.10/18.54 [2019-03-28 12:18:46,164 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 713 states and 1078 transitions. 37.10/18.54 [2019-03-28 12:18:46,166 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 686 37.10/18.54 [2019-03-28 12:18:46,166 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 37.10/18.54 [2019-03-28 12:18:46,166 INFO L119 BuchiIsEmpty]: Starting construction of run 37.10/18.54 [2019-03-28 12:18:46,167 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 37.10/18.54 [2019-03-28 12:18:46,167 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 37.10/18.54 [2019-03-28 12:18:46,168 INFO L794 eck$LassoCheckResult]: Stem: 21022#ULTIMATE.startENTRY [520] ULTIMATE.startENTRY-->L196: Formula: (and (= v_~q_write_ev~0_11 v_~q_read_ev~0_11) (= 1 v_~c_dr_i~0_7) (= v_~q_free~0_11 1) (= v_~q_buf_0~0_5 0) (= v_~q_write_ev~0_11 2) (= 0 v_~p_last_write~0_6) (= 0 v_~c_last_read~0_6) (= v_~p_dw_pc~0_14 0) (= 0 v_~a_t~0_5) (= 0 v_~c_dr_st~0_15) (= v_~c_dr_pc~0_14 0) (= 0 v_~c_num_read~0_9) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 0) (= 0 v_~p_num_write~0_9) (= v_~p_dw_i~0_7 1) (= v_~p_dw_st~0_15 0)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ~p_last_write~0=v_~p_last_write~0_6, ~c_dr_pc~0=v_~c_dr_pc~0_14, ~c_dr_st~0=v_~c_dr_st~0_15, ~c_num_read~0=v_~c_num_read~0_9, ~p_num_write~0=v_~p_num_write~0_9, ~c_dr_i~0=v_~c_dr_i~0_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7, ~q_write_ev~0=v_~q_write_ev~0_11, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~p_dw_st~0=v_~p_dw_st~0_15, ~p_dw_i~0=v_~p_dw_i~0_7, ~c_last_read~0=v_~c_last_read~0_6, ~p_dw_pc~0=v_~p_dw_pc~0_14, ~q_free~0=v_~q_free~0_11, ~q_buf_0~0=v_~q_buf_0~0_5, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6, ~q_read_ev~0=v_~q_read_ev~0_11, ~a_t~0=v_~a_t~0_5} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ~p_last_write~0, ~c_dr_pc~0, ~c_dr_st~0, ~c_num_read~0, ~p_num_write~0, ~c_dr_i~0, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_~kernel_st~0, ~q_write_ev~0, ULTIMATE.start_main_#res, ~p_dw_st~0, ~p_dw_i~0, ~c_last_read~0, ~p_dw_pc~0, ~q_free~0, ~q_buf_0~0, ULTIMATE.start_main_~__retres1~3, ~q_read_ev~0, ~a_t~0] 21023#L196 [418] L196-->L196-2: Formula: (and (= v_~p_dw_i~0_3 1) (= v_~p_dw_st~0_2 0)) InVars {~p_dw_i~0=v_~p_dw_i~0_3} OutVars{~p_dw_st~0=v_~p_dw_st~0_2, ~p_dw_i~0=v_~p_dw_i~0_3} AuxVars[] AssignedVars[~p_dw_st~0] 21066#L196-2 [413] L196-2-->L313-1: Formula: (and (= 1 v_~c_dr_i~0_3) (= v_~c_dr_st~0_3 0)) InVars {~c_dr_i~0=v_~c_dr_i~0_3} OutVars{~c_dr_st~0=v_~c_dr_st~0_3, ~c_dr_i~0=v_~c_dr_i~0_3} AuxVars[] AssignedVars[~c_dr_st~0] 21067#L313-1 [521] L313-1-->L262: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_8 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_8, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_4|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_6, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_6, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp~1, ULTIMATE.start_eval_~tmp___0~1, ULTIMATE.start_eval_~tmp___1~0] 21115#L262 [522] L262-->L214: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 21103#L214 [406] L214-->L226: Formula: (and (= v_~p_dw_st~0_6 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11 1)) InVars {~p_dw_st~0=v_~p_dw_st~0_6} OutVars{~p_dw_st~0=v_~p_dw_st~0_6, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 21104#L226 [523] L226-->L242: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___1~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_5|, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp___1~0] 21097#L242 [468] L242-->L242-1: Formula: (> v_ULTIMATE.start_eval_~tmp___1~0_4 0) InVars {ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} OutVars{ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} AuxVars[] AssignedVars[] 21098#L242-1 [333] L242-1-->L251: Formula: (and (= v_ULTIMATE.start_eval_~tmp~1_3 |v_ULTIMATE.start_eval_#t~nondet4_3|) (= v_~p_dw_st~0_8 0)) InVars {ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_3|, ~p_dw_st~0=v_~p_dw_st~0_8} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_2|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_3, ~p_dw_st~0=v_~p_dw_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_~tmp~1] 21048#L251 [472] L251-->L96: Formula: (and (= v_~p_dw_st~0_9 1) (> v_ULTIMATE.start_eval_~tmp~1_4 0)) InVars {ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_4} OutVars{ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_4, ~p_dw_st~0=v_~p_dw_st~0_9, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_1|} AuxVars[] AssignedVars[~p_dw_st~0, ULTIMATE.start_do_write_p_#t~nondet2] 21049#L96 [378] L96-->L107-1: Formula: (= v_~p_dw_pc~0_3 0) InVars {~p_dw_pc~0=v_~p_dw_pc~0_3} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_3} AuxVars[] AssignedVars[] 21110#L107-1 [375] L107-1-->L108: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 21107#L108 [486] L108-->L109: Formula: (> v_~q_free~0_4 0) InVars {~q_free~0=v_~q_free~0_4} OutVars{~q_free~0=v_~q_free~0_4} AuxVars[] AssignedVars[] 21002#L109 [323] L109-->L32: Formula: (and (= v_~q_buf_0~0_2 |v_ULTIMATE.start_do_write_p_#t~nondet2_3|) (= v_~p_last_write~0_2 v_~q_buf_0~0_2) (= v_~q_write_ev~0_3 1) (= v_~p_num_write~0_3 (+ v_~p_num_write~0_4 1)) (= v_~q_free~0_5 0)) InVars {~p_num_write~0=v_~p_num_write~0_4, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_3|} OutVars{~p_last_write~0=v_~p_last_write~0_2, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_2|, ~p_num_write~0=v_~p_num_write~0_3, ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_1, ~q_write_ev~0=v_~q_write_ev~0_3, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_1, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_1|, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_1|, ~q_free~0=v_~q_free~0_5, ~q_buf_0~0=v_~q_buf_0~0_2, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_1|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_1} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0, ~q_write_ev~0, ~p_last_write~0, ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_do_write_p_#t~nondet2, ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret1, ~p_num_write~0, ~q_free~0, ~q_buf_0~0, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 21003#L32 [489] L32-->L32-2: Formula: (< v_~p_dw_pc~0_9 1) InVars {~p_dw_pc~0=v_~p_dw_pc~0_9} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_9} AuxVars[] AssignedVars[] 21085#L32-2 [403] L32-2-->L43: Formula: (= v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_4 0) InVars {} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_4} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0] 21083#L43 [528] L43-->L74: Formula: (and (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_7| v_ULTIMATE.start_immediate_notify_threads_~tmp~0_11) (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_7| v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11)) InVars {ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_7|, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_7|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 21081#L74 [377] L74-->L74-2: Formula: (= v_ULTIMATE.start_immediate_notify_threads_~tmp~0_5 0) InVars {ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_5} OutVars{ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_5} AuxVars[] AssignedVars[] 21079#L74-2 [339] L74-2-->L51: Formula: true InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_1|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_1} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_#res, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 20975#L51 [502] L51-->L51-2: Formula: (> 1 v_~c_dr_pc~0_4) InVars {~c_dr_pc~0=v_~c_dr_pc~0_4} OutVars{~c_dr_pc~0=v_~c_dr_pc~0_4} AuxVars[] AssignedVars[] 20976#L51-2 [307] L51-2-->L62: Formula: (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 21345#L62 [532] L62-->L82: Formula: (and (= v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_11 |v_ULTIMATE.start_is_do_read_c_triggered_#res_7|) (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13 |v_ULTIMATE.start_is_do_read_c_triggered_#res_7|)) InVars {ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13} OutVars{ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_11, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_7|, ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_7|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13} AuxVars[] AssignedVars[ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_immediate_notify_threads_#t~ret1, ULTIMATE.start_is_do_read_c_triggered_#res] 21342#L82 [369] L82-->L82-2: Formula: (= v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_5 0) InVars {ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_5} OutVars{ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_5} AuxVars[] AssignedVars[] 21339#L82-2 37.10/18.54 [2019-03-28 12:18:46,169 INFO L796 eck$LassoCheckResult]: Loop: 21339#L82-2 [366] L82-2-->L107-1: Formula: (= v_~q_write_ev~0_6 2) InVars {} OutVars{~q_write_ev~0=v_~q_write_ev~0_6} AuxVars[] AssignedVars[~q_write_ev~0] 21291#L107-1 [375] L107-1-->L108: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 21292#L108 [408] L108-->L247: Formula: (and (= v_~q_free~0_3 0) (= v_~p_dw_pc~0_7 1) (= v_~p_dw_st~0_10 2)) InVars {~q_free~0=v_~q_free~0_3} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_7, ~q_free~0=v_~q_free~0_3, ~p_dw_st~0=v_~p_dw_st~0_10} AuxVars[] AssignedVars[~p_dw_st~0, ~p_dw_pc~0] 21277#L247 [410] L247-->L266: Formula: (and (= 0 v_~c_dr_st~0_10) (= v_ULTIMATE.start_eval_~tmp___0~1_4 |v_ULTIMATE.start_eval_#t~nondet5_3|)) InVars {~c_dr_st~0=v_~c_dr_st~0_10, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_3|} OutVars{~c_dr_st~0=v_~c_dr_st~0_10, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_4, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_2|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp___0~1] 21273#L266 [480] L266-->L139: Formula: (and (= v_~c_dr_st~0_11 1) (> v_ULTIMATE.start_eval_~tmp___0~1_5 0)) InVars {ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_5} OutVars{~c_dr_st~0=v_~c_dr_st~0_11, ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_1, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_5} AuxVars[] AssignedVars[~c_dr_st~0, ULTIMATE.start_do_read_c_~a~0] 21274#L139 [348] L139-->L10-2: Formula: (= 0 v_~c_dr_pc~0_5) InVars {~c_dr_pc~0=v_~c_dr_pc~0_5} OutVars{~c_dr_pc~0=v_~c_dr_pc~0_5} AuxVars[] AssignedVars[] 21194#L10-2 [400] L10-2-->L151: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 21225#L151 [491] L151-->L152-1: Formula: (< v_~q_free~0_7 1) InVars {~q_free~0=v_~q_free~0_7} OutVars{~q_free~0=v_~q_free~0_7} AuxVars[] AssignedVars[] 21392#L152-1 [412] L152-1-->L32-3: Formula: (and (= v_~c_num_read~0_3 (+ v_~c_num_read~0_4 1)) (= v_~q_read_ev~0_5 1) (= v_ULTIMATE.start_do_read_c_~a~0_5 v_~q_buf_0~0_3) (= v_~c_last_read~0_2 v_ULTIMATE.start_do_read_c_~a~0_5) (= v_~q_free~0_8 1)) InVars {~c_num_read~0=v_~c_num_read~0_4, ~q_buf_0~0=v_~q_buf_0~0_3} OutVars{~c_num_read~0=v_~c_num_read~0_3, ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_6, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_6, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_4|, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_4|, ~c_last_read~0=v_~c_last_read~0_2, ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_5, ~q_free~0=v_~q_free~0_8, ~q_buf_0~0=v_~q_buf_0~0_3, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_4|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_6, ~q_read_ev~0=v_~q_read_ev~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0, ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret1, ~c_last_read~0, ULTIMATE.start_do_read_c_~a~0, ~c_num_read~0, ~q_free~0, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0, ~q_read_ev~0] 21427#L32-3 [396] L32-3-->L33-1: Formula: (= v_~p_dw_pc~0_10 1) InVars {~p_dw_pc~0=v_~p_dw_pc~0_10} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_10} AuxVars[] AssignedVars[] 21426#L33-1 [346] L33-1-->L43-1: Formula: (and (= 1 v_~q_read_ev~0_6) (= v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_8 1)) InVars {~q_read_ev~0=v_~q_read_ev~0_6} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_8, ~q_read_ev~0=v_~q_read_ev~0_6} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0] 21420#L43-1 [531] L43-1-->L74-3: Formula: (and (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_8| v_ULTIMATE.start_immediate_notify_threads_~tmp~0_12) (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_8| v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_12)) InVars {ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_12} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_12, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_8|, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_8|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_12} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 21418#L74-3 [503] L74-3-->L74-5: Formula: (and (> v_ULTIMATE.start_immediate_notify_threads_~tmp~0_9 0) (= v_~p_dw_st~0_13 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_9} OutVars{~p_dw_st~0=v_~p_dw_st~0_13, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_9} AuxVars[] AssignedVars[~p_dw_st~0] 21410#L74-5 [332] L74-5-->L51-3: Formula: true InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_4|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_7} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_#res, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 21407#L51-3 [508] L51-3-->L51-5: Formula: (< v_~c_dr_pc~0_11 1) InVars {~c_dr_pc~0=v_~c_dr_pc~0_11} OutVars{~c_dr_pc~0=v_~c_dr_pc~0_11} AuxVars[] AssignedVars[] 21173#L51-5 [327] L51-5-->L62-1: Formula: (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 21400#L62-1 [533] L62-1-->L82-3: Formula: (and (= v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_12 |v_ULTIMATE.start_is_do_read_c_triggered_#res_8|) (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_14 |v_ULTIMATE.start_is_do_read_c_triggered_#res_8|)) InVars {ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_14} OutVars{ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_12, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_8|, ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_8|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_14} AuxVars[] AssignedVars[ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_immediate_notify_threads_#t~ret1, ULTIMATE.start_is_do_read_c_triggered_#res] 21394#L82-3 [514] L82-3-->L82-5: Formula: (and (> v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_9 0) (= v_~c_dr_st~0_13 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_9} OutVars{~c_dr_st~0=v_~c_dr_st~0_13, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_9} AuxVars[] AssignedVars[~c_dr_st~0] 21099#L82-5 [536] L82-5-->L10-2: Formula: (and (= v_~p_num_write~0_10 v_~c_num_read~0_10) (= 2 v_~q_read_ev~0_13) (= v_~c_last_read~0_8 v_~p_last_write~0_8)) InVars {~p_last_write~0=v_~p_last_write~0_8, ~c_last_read~0=v_~c_last_read~0_8, ~c_num_read~0=v_~c_num_read~0_10, ~p_num_write~0=v_~p_num_write~0_10} OutVars{~p_last_write~0=v_~p_last_write~0_8, ~c_last_read~0=v_~c_last_read~0_8, ~c_num_read~0=v_~c_num_read~0_10, ~p_num_write~0=v_~p_num_write~0_10, ~q_read_ev~0=v_~q_read_ev~0_13} AuxVars[] AssignedVars[~q_read_ev~0] 21100#L10-2 [400] L10-2-->L151: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 21091#L151 [380] L151-->L262: Formula: (and (= v_~c_dr_st~0_12 2) (= v_~c_dr_pc~0_9 1) (= v_~a_t~0_2 v_ULTIMATE.start_do_read_c_~a~0_3) (= v_~q_free~0_6 1)) InVars {ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_3, ~q_free~0=v_~q_free~0_6} OutVars{ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_3, ~c_dr_pc~0=v_~c_dr_pc~0_9, ~c_dr_st~0=v_~c_dr_st~0_12, ~q_free~0=v_~q_free~0_6, ~a_t~0=v_~a_t~0_2} AuxVars[] AssignedVars[~c_dr_pc~0, ~c_dr_st~0, ~a_t~0] 21090#L262 [522] L262-->L214: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 21089#L214 [406] L214-->L226: Formula: (and (= v_~p_dw_st~0_6 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11 1)) InVars {~p_dw_st~0=v_~p_dw_st~0_6} OutVars{~p_dw_st~0=v_~p_dw_st~0_6, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 21088#L226 [523] L226-->L242: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___1~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_5|, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp___1~0] 21087#L242 [468] L242-->L242-1: Formula: (> v_ULTIMATE.start_eval_~tmp___1~0_4 0) InVars {ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} OutVars{ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} AuxVars[] AssignedVars[] 21076#L242-1 [333] L242-1-->L251: Formula: (and (= v_ULTIMATE.start_eval_~tmp~1_3 |v_ULTIMATE.start_eval_#t~nondet4_3|) (= v_~p_dw_st~0_8 0)) InVars {ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_3|, ~p_dw_st~0=v_~p_dw_st~0_8} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_2|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_3, ~p_dw_st~0=v_~p_dw_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_~tmp~1] 21077#L251 [471] L251-->L96: Formula: (and (= v_~p_dw_st~0_9 1) (< v_ULTIMATE.start_eval_~tmp~1_4 0)) InVars {ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_4} OutVars{ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_4, ~p_dw_st~0=v_~p_dw_st~0_9, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_1|} AuxVars[] AssignedVars[~p_dw_st~0, ULTIMATE.start_do_write_p_#t~nondet2] 21084#L96 [478] L96-->L99: Formula: (> v_~p_dw_pc~0_4 0) InVars {~p_dw_pc~0=v_~p_dw_pc~0_4} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_4} AuxVars[] AssignedVars[] 21082#L99 [361] L99-->L109: Formula: (= v_~p_dw_pc~0_5 1) InVars {~p_dw_pc~0=v_~p_dw_pc~0_5} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_5} AuxVars[] AssignedVars[] 21080#L109 [323] L109-->L32: Formula: (and (= v_~q_buf_0~0_2 |v_ULTIMATE.start_do_write_p_#t~nondet2_3|) (= v_~p_last_write~0_2 v_~q_buf_0~0_2) (= v_~q_write_ev~0_3 1) (= v_~p_num_write~0_3 (+ v_~p_num_write~0_4 1)) (= v_~q_free~0_5 0)) InVars {~p_num_write~0=v_~p_num_write~0_4, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_3|} OutVars{~p_last_write~0=v_~p_last_write~0_2, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_2|, ~p_num_write~0=v_~p_num_write~0_3, ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_1, ~q_write_ev~0=v_~q_write_ev~0_3, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_1, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_1|, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_1|, ~q_free~0=v_~q_free~0_5, ~q_buf_0~0=v_~q_buf_0~0_2, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_1|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_1} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0, ~q_write_ev~0, ~p_last_write~0, ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_do_write_p_#t~nondet2, ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret1, ~p_num_write~0, ~q_free~0, ~q_buf_0~0, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 21078#L32 [489] L32-->L32-2: Formula: (< v_~p_dw_pc~0_9 1) InVars {~p_dw_pc~0=v_~p_dw_pc~0_9} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_9} AuxVars[] AssignedVars[] 20987#L32-2 [403] L32-2-->L43: Formula: (= v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_4 0) InVars {} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_4} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0] 20992#L43 [528] L43-->L74: Formula: (and (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_7| v_ULTIMATE.start_immediate_notify_threads_~tmp~0_11) (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_7| v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11)) InVars {ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_7|, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_7|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 20993#L74 [499] L74-->L74-2: Formula: (and (> v_ULTIMATE.start_immediate_notify_threads_~tmp~0_4 0) (= v_~p_dw_st~0_11 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_4} OutVars{~p_dw_st~0=v_~p_dw_st~0_11, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_4} AuxVars[] AssignedVars[~p_dw_st~0] 21015#L74-2 [339] L74-2-->L51: Formula: true InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_1|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_1} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_#res, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 21016#L51 [502] L51-->L51-2: Formula: (> 1 v_~c_dr_pc~0_4) InVars {~c_dr_pc~0=v_~c_dr_pc~0_4} OutVars{~c_dr_pc~0=v_~c_dr_pc~0_4} AuxVars[] AssignedVars[] 21285#L51-2 [307] L51-2-->L62: Formula: (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 21344#L62 [532] L62-->L82: Formula: (and (= v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_11 |v_ULTIMATE.start_is_do_read_c_triggered_#res_7|) (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13 |v_ULTIMATE.start_is_do_read_c_triggered_#res_7|)) InVars {ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13} OutVars{ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_11, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_7|, ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_7|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13} AuxVars[] AssignedVars[ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_immediate_notify_threads_#t~ret1, ULTIMATE.start_is_do_read_c_triggered_#res] 21341#L82 [512] L82-->L82-2: Formula: (and (> v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_4 0) (= v_~c_dr_st~0_9 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_4} OutVars{~c_dr_st~0=v_~c_dr_st~0_9, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_4} AuxVars[] AssignedVars[~c_dr_st~0] 21339#L82-2 37.10/18.54 [2019-03-28 12:18:46,169 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.54 [2019-03-28 12:18:46,169 INFO L82 PathProgramCache]: Analyzing trace with hash 1904401625, now seen corresponding path program 3 times 37.10/18.54 [2019-03-28 12:18:46,170 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.54 [2019-03-28 12:18:46,170 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.54 [2019-03-28 12:18:46,170 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:46,171 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:46,171 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:46,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 37.10/18.54 [2019-03-28 12:18:46,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 37.10/18.54 [2019-03-28 12:18:46,185 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.54 [2019-03-28 12:18:46,185 INFO L82 PathProgramCache]: Analyzing trace with hash 1007228545, now seen corresponding path program 1 times 37.10/18.54 [2019-03-28 12:18:46,185 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.54 [2019-03-28 12:18:46,185 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.54 [2019-03-28 12:18:46,186 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:46,186 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:46,186 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:46,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 37.10/18.54 [2019-03-28 12:18:46,213 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. 37.10/18.54 [2019-03-28 12:18:46,213 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 37.10/18.54 [2019-03-28 12:18:46,213 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 37.10/18.54 [2019-03-28 12:18:46,213 INFO L811 eck$LassoCheckResult]: loop already infeasible 37.10/18.54 [2019-03-28 12:18:46,214 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 37.10/18.54 [2019-03-28 12:18:46,214 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 37.10/18.54 [2019-03-28 12:18:46,214 INFO L87 Difference]: Start difference. First operand 713 states and 1078 transitions. cyclomatic complexity: 369 Second operand 3 states. 37.10/18.54 [2019-03-28 12:18:46,321 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 37.10/18.54 [2019-03-28 12:18:46,321 INFO L93 Difference]: Finished difference Result 619 states and 932 transitions. 37.10/18.54 [2019-03-28 12:18:46,323 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 37.10/18.54 [2019-03-28 12:18:46,328 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 619 states and 932 transitions. 37.10/18.54 [2019-03-28 12:18:46,330 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 497 37.10/18.54 [2019-03-28 12:18:46,333 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 619 states to 619 states and 932 transitions. 37.10/18.54 [2019-03-28 12:18:46,333 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 519 37.10/18.54 [2019-03-28 12:18:46,334 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 519 37.10/18.54 [2019-03-28 12:18:46,334 INFO L73 IsDeterministic]: Start isDeterministic. Operand 619 states and 932 transitions. 37.10/18.54 [2019-03-28 12:18:46,335 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. 37.10/18.54 [2019-03-28 12:18:46,335 INFO L706 BuchiCegarLoop]: Abstraction has 619 states and 932 transitions. 37.10/18.54 [2019-03-28 12:18:46,335 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 619 states and 932 transitions. 37.10/18.54 [2019-03-28 12:18:46,340 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 619 to 316. 37.10/18.54 [2019-03-28 12:18:46,341 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 316 states. 37.10/18.54 [2019-03-28 12:18:46,341 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 316 states to 316 states and 473 transitions. 37.10/18.54 [2019-03-28 12:18:46,341 INFO L729 BuchiCegarLoop]: Abstraction has 316 states and 473 transitions. 37.10/18.54 [2019-03-28 12:18:46,342 INFO L609 BuchiCegarLoop]: Abstraction has 316 states and 473 transitions. 37.10/18.54 [2019-03-28 12:18:46,342 INFO L442 BuchiCegarLoop]: ======== Iteration 22============ 37.10/18.54 [2019-03-28 12:18:46,342 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 316 states and 473 transitions. 37.10/18.54 [2019-03-28 12:18:46,343 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 289 37.10/18.54 [2019-03-28 12:18:46,343 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 37.10/18.54 [2019-03-28 12:18:46,343 INFO L119 BuchiIsEmpty]: Starting construction of run 37.10/18.54 [2019-03-28 12:18:46,343 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 37.10/18.54 [2019-03-28 12:18:46,344 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 37.10/18.54 [2019-03-28 12:18:46,344 INFO L794 eck$LassoCheckResult]: Stem: 22362#ULTIMATE.startENTRY [520] ULTIMATE.startENTRY-->L196: Formula: (and (= v_~q_write_ev~0_11 v_~q_read_ev~0_11) (= 1 v_~c_dr_i~0_7) (= v_~q_free~0_11 1) (= v_~q_buf_0~0_5 0) (= v_~q_write_ev~0_11 2) (= 0 v_~p_last_write~0_6) (= 0 v_~c_last_read~0_6) (= v_~p_dw_pc~0_14 0) (= 0 v_~a_t~0_5) (= 0 v_~c_dr_st~0_15) (= v_~c_dr_pc~0_14 0) (= 0 v_~c_num_read~0_9) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 0) (= 0 v_~p_num_write~0_9) (= v_~p_dw_i~0_7 1) (= v_~p_dw_st~0_15 0)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ~p_last_write~0=v_~p_last_write~0_6, ~c_dr_pc~0=v_~c_dr_pc~0_14, ~c_dr_st~0=v_~c_dr_st~0_15, ~c_num_read~0=v_~c_num_read~0_9, ~p_num_write~0=v_~p_num_write~0_9, ~c_dr_i~0=v_~c_dr_i~0_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7, ~q_write_ev~0=v_~q_write_ev~0_11, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~p_dw_st~0=v_~p_dw_st~0_15, ~p_dw_i~0=v_~p_dw_i~0_7, ~c_last_read~0=v_~c_last_read~0_6, ~p_dw_pc~0=v_~p_dw_pc~0_14, ~q_free~0=v_~q_free~0_11, ~q_buf_0~0=v_~q_buf_0~0_5, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6, ~q_read_ev~0=v_~q_read_ev~0_11, ~a_t~0=v_~a_t~0_5} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ~p_last_write~0, ~c_dr_pc~0, ~c_dr_st~0, ~c_num_read~0, ~p_num_write~0, ~c_dr_i~0, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_~kernel_st~0, ~q_write_ev~0, ULTIMATE.start_main_#res, ~p_dw_st~0, ~p_dw_i~0, ~c_last_read~0, ~p_dw_pc~0, ~q_free~0, ~q_buf_0~0, ULTIMATE.start_main_~__retres1~3, ~q_read_ev~0, ~a_t~0] 22363#L196 [418] L196-->L196-2: Formula: (and (= v_~p_dw_i~0_3 1) (= v_~p_dw_st~0_2 0)) InVars {~p_dw_i~0=v_~p_dw_i~0_3} OutVars{~p_dw_st~0=v_~p_dw_st~0_2, ~p_dw_i~0=v_~p_dw_i~0_3} AuxVars[] AssignedVars[~p_dw_st~0] 22402#L196-2 [413] L196-2-->L313-1: Formula: (and (= 1 v_~c_dr_i~0_3) (= v_~c_dr_st~0_3 0)) InVars {~c_dr_i~0=v_~c_dr_i~0_3} OutVars{~c_dr_st~0=v_~c_dr_st~0_3, ~c_dr_i~0=v_~c_dr_i~0_3} AuxVars[] AssignedVars[~c_dr_st~0] 22403#L313-1 [521] L313-1-->L262: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_8 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_8, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_4|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_6, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_6, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp~1, ULTIMATE.start_eval_~tmp___0~1, ULTIMATE.start_eval_~tmp___1~0] 22417#L262 [522] L262-->L214: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 22416#L214 [406] L214-->L226: Formula: (and (= v_~p_dw_st~0_6 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11 1)) InVars {~p_dw_st~0=v_~p_dw_st~0_6} OutVars{~p_dw_st~0=v_~p_dw_st~0_6, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 22415#L226 [523] L226-->L242: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___1~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_5|, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp___1~0] 22414#L242 [468] L242-->L242-1: Formula: (> v_ULTIMATE.start_eval_~tmp___1~0_4 0) InVars {ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} OutVars{ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} AuxVars[] AssignedVars[] 22413#L242-1 [333] L242-1-->L251: Formula: (and (= v_ULTIMATE.start_eval_~tmp~1_3 |v_ULTIMATE.start_eval_#t~nondet4_3|) (= v_~p_dw_st~0_8 0)) InVars {ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_3|, ~p_dw_st~0=v_~p_dw_st~0_8} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_2|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_3, ~p_dw_st~0=v_~p_dw_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_~tmp~1] 22412#L251 [472] L251-->L96: Formula: (and (= v_~p_dw_st~0_9 1) (> v_ULTIMATE.start_eval_~tmp~1_4 0)) InVars {ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_4} OutVars{ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_4, ~p_dw_st~0=v_~p_dw_st~0_9, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_1|} AuxVars[] AssignedVars[~p_dw_st~0, ULTIMATE.start_do_write_p_#t~nondet2] 22376#L96 [378] L96-->L107-1: Formula: (= v_~p_dw_pc~0_3 0) InVars {~p_dw_pc~0=v_~p_dw_pc~0_3} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_3} AuxVars[] AssignedVars[] 22377#L107-1 [375] L107-1-->L108: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 22408#L108 [486] L108-->L109: Formula: (> v_~q_free~0_4 0) InVars {~q_free~0=v_~q_free~0_4} OutVars{~q_free~0=v_~q_free~0_4} AuxVars[] AssignedVars[] 22407#L109 [323] L109-->L32: Formula: (and (= v_~q_buf_0~0_2 |v_ULTIMATE.start_do_write_p_#t~nondet2_3|) (= v_~p_last_write~0_2 v_~q_buf_0~0_2) (= v_~q_write_ev~0_3 1) (= v_~p_num_write~0_3 (+ v_~p_num_write~0_4 1)) (= v_~q_free~0_5 0)) InVars {~p_num_write~0=v_~p_num_write~0_4, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_3|} OutVars{~p_last_write~0=v_~p_last_write~0_2, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_2|, ~p_num_write~0=v_~p_num_write~0_3, ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_1, ~q_write_ev~0=v_~q_write_ev~0_3, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_1, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_1|, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_1|, ~q_free~0=v_~q_free~0_5, ~q_buf_0~0=v_~q_buf_0~0_2, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_1|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_1} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0, ~q_write_ev~0, ~p_last_write~0, ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_do_write_p_#t~nondet2, ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret1, ~p_num_write~0, ~q_free~0, ~q_buf_0~0, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 22324#L32 [489] L32-->L32-2: Formula: (< v_~p_dw_pc~0_9 1) InVars {~p_dw_pc~0=v_~p_dw_pc~0_9} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_9} AuxVars[] AssignedVars[] 22325#L32-2 [403] L32-2-->L43: Formula: (= v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_4 0) InVars {} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_4} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0] 22411#L43 [528] L43-->L74: Formula: (and (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_7| v_ULTIMATE.start_immediate_notify_threads_~tmp~0_11) (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_7| v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11)) InVars {ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_7|, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_7|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 22410#L74 [377] L74-->L74-2: Formula: (= v_ULTIMATE.start_immediate_notify_threads_~tmp~0_5 0) InVars {ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_5} OutVars{ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_5} AuxVars[] AssignedVars[] 22409#L74-2 [339] L74-2-->L51: Formula: true InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_1|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_1} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_#res, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 22313#L51 [502] L51-->L51-2: Formula: (> 1 v_~c_dr_pc~0_4) InVars {~c_dr_pc~0=v_~c_dr_pc~0_4} OutVars{~c_dr_pc~0=v_~c_dr_pc~0_4} AuxVars[] AssignedVars[] 22314#L51-2 [307] L51-2-->L62: Formula: (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 22599#L62 [532] L62-->L82: Formula: (and (= v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_11 |v_ULTIMATE.start_is_do_read_c_triggered_#res_7|) (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13 |v_ULTIMATE.start_is_do_read_c_triggered_#res_7|)) InVars {ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13} OutVars{ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_11, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_7|, ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_7|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13} AuxVars[] AssignedVars[ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_immediate_notify_threads_#t~ret1, ULTIMATE.start_is_do_read_c_triggered_#res] 22374#L82 [369] L82-->L82-2: Formula: (= v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_5 0) InVars {ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_5} OutVars{ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_5} AuxVars[] AssignedVars[] 22372#L82-2 37.10/18.54 [2019-03-28 12:18:46,345 INFO L796 eck$LassoCheckResult]: Loop: 22372#L82-2 [366] L82-2-->L107-1: Formula: (= v_~q_write_ev~0_6 2) InVars {} OutVars{~q_write_ev~0=v_~q_write_ev~0_6} AuxVars[] AssignedVars[~q_write_ev~0] 22373#L107-1 [375] L107-1-->L108: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 22375#L108 [408] L108-->L247: Formula: (and (= v_~q_free~0_3 0) (= v_~p_dw_pc~0_7 1) (= v_~p_dw_st~0_10 2)) InVars {~q_free~0=v_~q_free~0_3} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_7, ~q_free~0=v_~q_free~0_3, ~p_dw_st~0=v_~p_dw_st~0_10} AuxVars[] AssignedVars[~p_dw_st~0, ~p_dw_pc~0] 22496#L247 [410] L247-->L266: Formula: (and (= 0 v_~c_dr_st~0_10) (= v_ULTIMATE.start_eval_~tmp___0~1_4 |v_ULTIMATE.start_eval_#t~nondet5_3|)) InVars {~c_dr_st~0=v_~c_dr_st~0_10, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_3|} OutVars{~c_dr_st~0=v_~c_dr_st~0_10, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_4, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_2|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp___0~1] 22494#L266 [480] L266-->L139: Formula: (and (= v_~c_dr_st~0_11 1) (> v_ULTIMATE.start_eval_~tmp___0~1_5 0)) InVars {ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_5} OutVars{~c_dr_st~0=v_~c_dr_st~0_11, ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_1, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_5} AuxVars[] AssignedVars[~c_dr_st~0, ULTIMATE.start_do_read_c_~a~0] 22320#L139 [348] L139-->L10-2: Formula: (= 0 v_~c_dr_pc~0_5) InVars {~c_dr_pc~0=v_~c_dr_pc~0_5} OutVars{~c_dr_pc~0=v_~c_dr_pc~0_5} AuxVars[] AssignedVars[] 22479#L10-2 [400] L10-2-->L151: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 22477#L151 [491] L151-->L152-1: Formula: (< v_~q_free~0_7 1) InVars {~q_free~0=v_~q_free~0_7} OutVars{~q_free~0=v_~q_free~0_7} AuxVars[] AssignedVars[] 22380#L152-1 [412] L152-1-->L32-3: Formula: (and (= v_~c_num_read~0_3 (+ v_~c_num_read~0_4 1)) (= v_~q_read_ev~0_5 1) (= v_ULTIMATE.start_do_read_c_~a~0_5 v_~q_buf_0~0_3) (= v_~c_last_read~0_2 v_ULTIMATE.start_do_read_c_~a~0_5) (= v_~q_free~0_8 1)) InVars {~c_num_read~0=v_~c_num_read~0_4, ~q_buf_0~0=v_~q_buf_0~0_3} OutVars{~c_num_read~0=v_~c_num_read~0_3, ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_6, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_6, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_4|, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_4|, ~c_last_read~0=v_~c_last_read~0_2, ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_5, ~q_free~0=v_~q_free~0_8, ~q_buf_0~0=v_~q_buf_0~0_3, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_4|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_6, ~q_read_ev~0=v_~q_read_ev~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0, ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret1, ~c_last_read~0, ULTIMATE.start_do_read_c_~a~0, ~c_num_read~0, ~q_free~0, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0, ~q_read_ev~0] 22470#L32-3 [396] L32-3-->L33-1: Formula: (= v_~p_dw_pc~0_10 1) InVars {~p_dw_pc~0=v_~p_dw_pc~0_10} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_10} AuxVars[] AssignedVars[] 22469#L33-1 [346] L33-1-->L43-1: Formula: (and (= 1 v_~q_read_ev~0_6) (= v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_8 1)) InVars {~q_read_ev~0=v_~q_read_ev~0_6} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_8, ~q_read_ev~0=v_~q_read_ev~0_6} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0] 22467#L43-1 [531] L43-1-->L74-3: Formula: (and (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_8| v_ULTIMATE.start_immediate_notify_threads_~tmp~0_12) (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_8| v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_12)) InVars {ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_12} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_12, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_8|, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_8|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_12} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 22351#L74-3 [503] L74-3-->L74-5: Formula: (and (> v_ULTIMATE.start_immediate_notify_threads_~tmp~0_9 0) (= v_~p_dw_st~0_13 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_9} OutVars{~p_dw_st~0=v_~p_dw_st~0_13, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_9} AuxVars[] AssignedVars[~p_dw_st~0] 22352#L74-5 [332] L74-5-->L51-3: Formula: true InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_4|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_7} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_#res, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 22466#L51-3 [508] L51-3-->L51-5: Formula: (< v_~c_dr_pc~0_11 1) InVars {~c_dr_pc~0=v_~c_dr_pc~0_11} OutVars{~c_dr_pc~0=v_~c_dr_pc~0_11} AuxVars[] AssignedVars[] 22427#L51-5 [327] L51-5-->L62-1: Formula: (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 22446#L62-1 [533] L62-1-->L82-3: Formula: (and (= v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_12 |v_ULTIMATE.start_is_do_read_c_triggered_#res_8|) (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_14 |v_ULTIMATE.start_is_do_read_c_triggered_#res_8|)) InVars {ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_14} OutVars{ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_12, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_8|, ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_8|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_14} AuxVars[] AssignedVars[ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_immediate_notify_threads_#t~ret1, ULTIMATE.start_is_do_read_c_triggered_#res] 22447#L82-3 [514] L82-3-->L82-5: Formula: (and (> v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_9 0) (= v_~c_dr_st~0_13 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_9} OutVars{~c_dr_st~0=v_~c_dr_st~0_13, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_9} AuxVars[] AssignedVars[~c_dr_st~0] 22435#L82-5 [536] L82-5-->L10-2: Formula: (and (= v_~p_num_write~0_10 v_~c_num_read~0_10) (= 2 v_~q_read_ev~0_13) (= v_~c_last_read~0_8 v_~p_last_write~0_8)) InVars {~p_last_write~0=v_~p_last_write~0_8, ~c_last_read~0=v_~c_last_read~0_8, ~c_num_read~0=v_~c_num_read~0_10, ~p_num_write~0=v_~p_num_write~0_10} OutVars{~p_last_write~0=v_~p_last_write~0_8, ~c_last_read~0=v_~c_last_read~0_8, ~c_num_read~0=v_~c_num_read~0_10, ~p_num_write~0=v_~p_num_write~0_10, ~q_read_ev~0=v_~q_read_ev~0_13} AuxVars[] AssignedVars[~q_read_ev~0] 22436#L10-2 [400] L10-2-->L151: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 22423#L151 [380] L151-->L262: Formula: (and (= v_~c_dr_st~0_12 2) (= v_~c_dr_pc~0_9 1) (= v_~a_t~0_2 v_ULTIMATE.start_do_read_c_~a~0_3) (= v_~q_free~0_6 1)) InVars {ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_3, ~q_free~0=v_~q_free~0_6} OutVars{ULTIMATE.start_do_read_c_~a~0=v_ULTIMATE.start_do_read_c_~a~0_3, ~c_dr_pc~0=v_~c_dr_pc~0_9, ~c_dr_st~0=v_~c_dr_st~0_12, ~q_free~0=v_~q_free~0_6, ~a_t~0=v_~a_t~0_2} AuxVars[] AssignedVars[~c_dr_pc~0, ~c_dr_st~0, ~a_t~0] 22422#L262 [522] L262-->L214: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 22421#L214 [406] L214-->L226: Formula: (and (= v_~p_dw_st~0_6 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11 1)) InVars {~p_dw_st~0=v_~p_dw_st~0_6} OutVars{~p_dw_st~0=v_~p_dw_st~0_6, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 22420#L226 [523] L226-->L242: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___1~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_5|, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp___1~0] 22419#L242 [468] L242-->L242-1: Formula: (> v_ULTIMATE.start_eval_~tmp___1~0_4 0) InVars {ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} OutVars{ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} AuxVars[] AssignedVars[] 22418#L242-1 [333] L242-1-->L251: Formula: (and (= v_ULTIMATE.start_eval_~tmp~1_3 |v_ULTIMATE.start_eval_#t~nondet4_3|) (= v_~p_dw_st~0_8 0)) InVars {ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_3|, ~p_dw_st~0=v_~p_dw_st~0_8} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_2|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_3, ~p_dw_st~0=v_~p_dw_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_~tmp~1] 22387#L251 [471] L251-->L96: Formula: (and (= v_~p_dw_st~0_9 1) (< v_ULTIMATE.start_eval_~tmp~1_4 0)) InVars {ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_4} OutVars{ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_4, ~p_dw_st~0=v_~p_dw_st~0_9, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_1|} AuxVars[] AssignedVars[~p_dw_st~0, ULTIMATE.start_do_write_p_#t~nondet2] 22388#L96 [478] L96-->L99: Formula: (> v_~p_dw_pc~0_4 0) InVars {~p_dw_pc~0=v_~p_dw_pc~0_4} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_4} AuxVars[] AssignedVars[] 22370#L99 [361] L99-->L109: Formula: (= v_~p_dw_pc~0_5 1) InVars {~p_dw_pc~0=v_~p_dw_pc~0_5} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_5} AuxVars[] AssignedVars[] 22340#L109 [323] L109-->L32: Formula: (and (= v_~q_buf_0~0_2 |v_ULTIMATE.start_do_write_p_#t~nondet2_3|) (= v_~p_last_write~0_2 v_~q_buf_0~0_2) (= v_~q_write_ev~0_3 1) (= v_~p_num_write~0_3 (+ v_~p_num_write~0_4 1)) (= v_~q_free~0_5 0)) InVars {~p_num_write~0=v_~p_num_write~0_4, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_3|} OutVars{~p_last_write~0=v_~p_last_write~0_2, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_2|, ~p_num_write~0=v_~p_num_write~0_3, ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_1, ~q_write_ev~0=v_~q_write_ev~0_3, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_1, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_1|, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_1|, ~q_free~0=v_~q_free~0_5, ~q_buf_0~0=v_~q_buf_0~0_2, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_1|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_1} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0, ~q_write_ev~0, ~p_last_write~0, ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_do_write_p_#t~nondet2, ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret1, ~p_num_write~0, ~q_free~0, ~q_buf_0~0, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 22341#L32 [316] L32-->L33: Formula: (= v_~p_dw_pc~0_8 1) InVars {~p_dw_pc~0=v_~p_dw_pc~0_8} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_8} AuxVars[] AssignedVars[] 22368#L33 [493] L33-->L32-2: Formula: (< 1 v_~q_read_ev~0_4) InVars {~q_read_ev~0=v_~q_read_ev~0_4} OutVars{~q_read_ev~0=v_~q_read_ev~0_4} AuxVars[] AssignedVars[] 22369#L32-2 [403] L32-2-->L43: Formula: (= v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_4 0) InVars {} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_4} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0] 22326#L43 [528] L43-->L74: Formula: (and (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_7| v_ULTIMATE.start_immediate_notify_threads_~tmp~0_11) (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_7| v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11)) InVars {ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_7|, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_7|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 22327#L74 [499] L74-->L74-2: Formula: (and (> v_ULTIMATE.start_immediate_notify_threads_~tmp~0_4 0) (= v_~p_dw_st~0_11 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_4} OutVars{~p_dw_st~0=v_~p_dw_st~0_11, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_4} AuxVars[] AssignedVars[~p_dw_st~0] 22355#L74-2 [339] L74-2-->L51: Formula: true InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_1|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_1} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_#res, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 22356#L51 [502] L51-->L51-2: Formula: (> 1 v_~c_dr_pc~0_4) InVars {~c_dr_pc~0=v_~c_dr_pc~0_4} OutVars{~c_dr_pc~0=v_~c_dr_pc~0_4} AuxVars[] AssignedVars[] 22309#L51-2 [307] L51-2-->L62: Formula: (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 22310#L62 [532] L62-->L82: Formula: (and (= v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_11 |v_ULTIMATE.start_is_do_read_c_triggered_#res_7|) (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13 |v_ULTIMATE.start_is_do_read_c_triggered_#res_7|)) InVars {ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13} OutVars{ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_11, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_7|, ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_7|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13} AuxVars[] AssignedVars[ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_immediate_notify_threads_#t~ret1, ULTIMATE.start_is_do_read_c_triggered_#res] 22574#L82 [512] L82-->L82-2: Formula: (and (> v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_4 0) (= v_~c_dr_st~0_9 0)) InVars {ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_4} OutVars{~c_dr_st~0=v_~c_dr_st~0_9, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_4} AuxVars[] AssignedVars[~c_dr_st~0] 22372#L82-2 37.10/18.54 [2019-03-28 12:18:46,345 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.54 [2019-03-28 12:18:46,346 INFO L82 PathProgramCache]: Analyzing trace with hash 1904401625, now seen corresponding path program 4 times 37.10/18.54 [2019-03-28 12:18:46,346 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.54 [2019-03-28 12:18:46,346 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.54 [2019-03-28 12:18:46,347 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:46,347 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:46,347 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:46,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 37.10/18.54 [2019-03-28 12:18:46,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 37.10/18.54 [2019-03-28 12:18:46,359 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.54 [2019-03-28 12:18:46,359 INFO L82 PathProgramCache]: Analyzing trace with hash -1660099611, now seen corresponding path program 1 times 37.10/18.54 [2019-03-28 12:18:46,359 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.54 [2019-03-28 12:18:46,359 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.54 [2019-03-28 12:18:46,360 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:46,360 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:46,360 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:46,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 37.10/18.54 [2019-03-28 12:18:46,381 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. 37.10/18.54 [2019-03-28 12:18:46,381 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 37.10/18.54 [2019-03-28 12:18:46,381 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 37.10/18.54 [2019-03-28 12:18:46,382 INFO L811 eck$LassoCheckResult]: loop already infeasible 37.10/18.54 [2019-03-28 12:18:46,382 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 37.10/18.54 [2019-03-28 12:18:46,382 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 37.10/18.54 [2019-03-28 12:18:46,382 INFO L87 Difference]: Start difference. First operand 316 states and 473 transitions. cyclomatic complexity: 160 Second operand 3 states. 37.10/18.54 [2019-03-28 12:18:46,515 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 37.10/18.54 [2019-03-28 12:18:46,515 INFO L93 Difference]: Finished difference Result 240 states and 344 transitions. 37.10/18.54 [2019-03-28 12:18:46,515 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 37.10/18.54 [2019-03-28 12:18:46,520 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 240 states and 344 transitions. 37.10/18.54 [2019-03-28 12:18:46,521 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 210 37.10/18.54 [2019-03-28 12:18:46,523 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 240 states to 240 states and 344 transitions. 37.10/18.54 [2019-03-28 12:18:46,523 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 215 37.10/18.54 [2019-03-28 12:18:46,523 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 215 37.10/18.54 [2019-03-28 12:18:46,523 INFO L73 IsDeterministic]: Start isDeterministic. Operand 240 states and 344 transitions. 37.10/18.54 [2019-03-28 12:18:46,524 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. 37.10/18.54 [2019-03-28 12:18:46,524 INFO L706 BuchiCegarLoop]: Abstraction has 240 states and 344 transitions. 37.10/18.54 [2019-03-28 12:18:46,524 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 240 states and 344 transitions. 37.10/18.54 [2019-03-28 12:18:46,528 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 240 to 240. 37.10/18.54 [2019-03-28 12:18:46,528 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 240 states. 37.10/18.54 [2019-03-28 12:18:46,529 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 240 states to 240 states and 344 transitions. 37.10/18.54 [2019-03-28 12:18:46,529 INFO L729 BuchiCegarLoop]: Abstraction has 240 states and 344 transitions. 37.10/18.54 [2019-03-28 12:18:46,529 INFO L609 BuchiCegarLoop]: Abstraction has 240 states and 344 transitions. 37.10/18.54 [2019-03-28 12:18:46,529 INFO L442 BuchiCegarLoop]: ======== Iteration 23============ 37.10/18.54 [2019-03-28 12:18:46,529 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 240 states and 344 transitions. 37.10/18.54 [2019-03-28 12:18:46,530 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 210 37.10/18.54 [2019-03-28 12:18:46,530 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 37.10/18.54 [2019-03-28 12:18:46,530 INFO L119 BuchiIsEmpty]: Starting construction of run 37.10/18.54 [2019-03-28 12:18:46,531 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 37.10/18.54 [2019-03-28 12:18:46,531 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] 37.10/18.54 [2019-03-28 12:18:46,531 INFO L794 eck$LassoCheckResult]: Stem: 22920#ULTIMATE.startENTRY [520] ULTIMATE.startENTRY-->L196: Formula: (and (= v_~q_write_ev~0_11 v_~q_read_ev~0_11) (= 1 v_~c_dr_i~0_7) (= v_~q_free~0_11 1) (= v_~q_buf_0~0_5 0) (= v_~q_write_ev~0_11 2) (= 0 v_~p_last_write~0_6) (= 0 v_~c_last_read~0_6) (= v_~p_dw_pc~0_14 0) (= 0 v_~a_t~0_5) (= 0 v_~c_dr_st~0_15) (= v_~c_dr_pc~0_14 0) (= 0 v_~c_num_read~0_9) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 0) (= 0 v_~p_num_write~0_9) (= v_~p_dw_i~0_7 1) (= v_~p_dw_st~0_15 0)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ~p_last_write~0=v_~p_last_write~0_6, ~c_dr_pc~0=v_~c_dr_pc~0_14, ~c_dr_st~0=v_~c_dr_st~0_15, ~c_num_read~0=v_~c_num_read~0_9, ~p_num_write~0=v_~p_num_write~0_9, ~c_dr_i~0=v_~c_dr_i~0_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7, ~q_write_ev~0=v_~q_write_ev~0_11, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~p_dw_st~0=v_~p_dw_st~0_15, ~p_dw_i~0=v_~p_dw_i~0_7, ~c_last_read~0=v_~c_last_read~0_6, ~p_dw_pc~0=v_~p_dw_pc~0_14, ~q_free~0=v_~q_free~0_11, ~q_buf_0~0=v_~q_buf_0~0_5, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6, ~q_read_ev~0=v_~q_read_ev~0_11, ~a_t~0=v_~a_t~0_5} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ~p_last_write~0, ~c_dr_pc~0, ~c_dr_st~0, ~c_num_read~0, ~p_num_write~0, ~c_dr_i~0, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_~kernel_st~0, ~q_write_ev~0, ULTIMATE.start_main_#res, ~p_dw_st~0, ~p_dw_i~0, ~c_last_read~0, ~p_dw_pc~0, ~q_free~0, ~q_buf_0~0, ULTIMATE.start_main_~__retres1~3, ~q_read_ev~0, ~a_t~0] 22921#L196 [418] L196-->L196-2: Formula: (and (= v_~p_dw_i~0_3 1) (= v_~p_dw_st~0_2 0)) InVars {~p_dw_i~0=v_~p_dw_i~0_3} OutVars{~p_dw_st~0=v_~p_dw_st~0_2, ~p_dw_i~0=v_~p_dw_i~0_3} AuxVars[] AssignedVars[~p_dw_st~0] 22957#L196-2 [413] L196-2-->L313-1: Formula: (and (= 1 v_~c_dr_i~0_3) (= v_~c_dr_st~0_3 0)) InVars {~c_dr_i~0=v_~c_dr_i~0_3} OutVars{~c_dr_st~0=v_~c_dr_st~0_3, ~c_dr_i~0=v_~c_dr_i~0_3} AuxVars[] AssignedVars[~c_dr_st~0] 22958#L313-1 [521] L313-1-->L262: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_8 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_8, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_4|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_6, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_6, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp~1, ULTIMATE.start_eval_~tmp___0~1, ULTIMATE.start_eval_~tmp___1~0] 22990#L262 [522] L262-->L214: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 22989#L214 [406] L214-->L226: Formula: (and (= v_~p_dw_st~0_6 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11 1)) InVars {~p_dw_st~0=v_~p_dw_st~0_6} OutVars{~p_dw_st~0=v_~p_dw_st~0_6, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 22988#L226 [523] L226-->L242: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___1~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_5|, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp___1~0] 22986#L242 [468] L242-->L242-1: Formula: (> v_ULTIMATE.start_eval_~tmp___1~0_4 0) InVars {ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} OutVars{ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} AuxVars[] AssignedVars[] 22985#L242-1 [333] L242-1-->L251: Formula: (and (= v_ULTIMATE.start_eval_~tmp~1_3 |v_ULTIMATE.start_eval_#t~nondet4_3|) (= v_~p_dw_st~0_8 0)) InVars {ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_3|, ~p_dw_st~0=v_~p_dw_st~0_8} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_2|, ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_3, ~p_dw_st~0=v_~p_dw_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_~tmp~1] 22946#L251 [472] L251-->L96: Formula: (and (= v_~p_dw_st~0_9 1) (> v_ULTIMATE.start_eval_~tmp~1_4 0)) InVars {ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_4} OutVars{ULTIMATE.start_eval_~tmp~1=v_ULTIMATE.start_eval_~tmp~1_4, ~p_dw_st~0=v_~p_dw_st~0_9, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_1|} AuxVars[] AssignedVars[~p_dw_st~0, ULTIMATE.start_do_write_p_#t~nondet2] 22934#L96 [378] L96-->L107-1: Formula: (= v_~p_dw_pc~0_3 0) InVars {~p_dw_pc~0=v_~p_dw_pc~0_3} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_3} AuxVars[] AssignedVars[] 22935#L107-1 [375] L107-1-->L108: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 22984#L108 [486] L108-->L109: Formula: (> v_~q_free~0_4 0) InVars {~q_free~0=v_~q_free~0_4} OutVars{~q_free~0=v_~q_free~0_4} AuxVars[] AssignedVars[] 22901#L109 [323] L109-->L32: Formula: (and (= v_~q_buf_0~0_2 |v_ULTIMATE.start_do_write_p_#t~nondet2_3|) (= v_~p_last_write~0_2 v_~q_buf_0~0_2) (= v_~q_write_ev~0_3 1) (= v_~p_num_write~0_3 (+ v_~p_num_write~0_4 1)) (= v_~q_free~0_5 0)) InVars {~p_num_write~0=v_~p_num_write~0_4, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_3|} OutVars{~p_last_write~0=v_~p_last_write~0_2, ULTIMATE.start_do_write_p_#t~nondet2=|v_ULTIMATE.start_do_write_p_#t~nondet2_2|, ~p_num_write~0=v_~p_num_write~0_3, ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_1, ~q_write_ev~0=v_~q_write_ev~0_3, ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_1, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_1|, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_1|, ~q_free~0=v_~q_free~0_5, ~q_buf_0~0=v_~q_buf_0~0_2, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_1|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_1} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0, ~q_write_ev~0, ~p_last_write~0, ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_do_write_p_#t~nondet2, ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret1, ~p_num_write~0, ~q_free~0, ~q_buf_0~0, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 22885#L32 [489] L32-->L32-2: Formula: (< v_~p_dw_pc~0_9 1) InVars {~p_dw_pc~0=v_~p_dw_pc~0_9} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_9} AuxVars[] AssignedVars[] 22886#L32-2 [403] L32-2-->L43: Formula: (= v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_4 0) InVars {} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_4} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_~__retres1~0] 22887#L43 [528] L43-->L74: Formula: (and (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_7| v_ULTIMATE.start_immediate_notify_threads_~tmp~0_11) (= |v_ULTIMATE.start_is_do_write_p_triggered_#res_7| v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11)) InVars {ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11} OutVars{ULTIMATE.start_is_do_write_p_triggered_~__retres1~0=v_ULTIMATE.start_is_do_write_p_triggered_~__retres1~0_11, ULTIMATE.start_is_do_write_p_triggered_#res=|v_ULTIMATE.start_is_do_write_p_triggered_#res_7|, ULTIMATE.start_immediate_notify_threads_#t~ret0=|v_ULTIMATE.start_immediate_notify_threads_#t~ret0_7|, ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_do_write_p_triggered_#res, ULTIMATE.start_immediate_notify_threads_#t~ret0, ULTIMATE.start_immediate_notify_threads_~tmp~0] 22888#L74 [377] L74-->L74-2: Formula: (= v_ULTIMATE.start_immediate_notify_threads_~tmp~0_5 0) InVars {ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_5} OutVars{ULTIMATE.start_immediate_notify_threads_~tmp~0=v_ULTIMATE.start_immediate_notify_threads_~tmp~0_5} AuxVars[] AssignedVars[] 22913#L74-2 [339] L74-2-->L51: Formula: true InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_1|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_1} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_#res, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 22875#L51 [502] L51-->L51-2: Formula: (> 1 v_~c_dr_pc~0_4) InVars {~c_dr_pc~0=v_~c_dr_pc~0_4} OutVars{~c_dr_pc~0=v_~c_dr_pc~0_4} AuxVars[] AssignedVars[] 22871#L51-2 [307] L51-2-->L62: Formula: (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_do_read_c_triggered_~__retres1~1] 22872#L62 [532] L62-->L82: Formula: (and (= v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_11 |v_ULTIMATE.start_is_do_read_c_triggered_#res_7|) (= v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13 |v_ULTIMATE.start_is_do_read_c_triggered_#res_7|)) InVars {ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13} OutVars{ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_11, ULTIMATE.start_immediate_notify_threads_#t~ret1=|v_ULTIMATE.start_immediate_notify_threads_#t~ret1_7|, ULTIMATE.start_is_do_read_c_triggered_#res=|v_ULTIMATE.start_is_do_read_c_triggered_#res_7|, ULTIMATE.start_is_do_read_c_triggered_~__retres1~1=v_ULTIMATE.start_is_do_read_c_triggered_~__retres1~1_13} AuxVars[] AssignedVars[ULTIMATE.start_immediate_notify_threads_~tmp___0~0, ULTIMATE.start_immediate_notify_threads_#t~ret1, ULTIMATE.start_is_do_read_c_triggered_#res] 22876#L82 [369] L82-->L82-2: Formula: (= v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_5 0) InVars {ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_5} OutVars{ULTIMATE.start_immediate_notify_threads_~tmp___0~0=v_ULTIMATE.start_immediate_notify_threads_~tmp___0~0_5} AuxVars[] AssignedVars[] 23020#L82-2 [366] L82-2-->L107-1: Formula: (= v_~q_write_ev~0_6 2) InVars {} OutVars{~q_write_ev~0=v_~q_write_ev~0_6} AuxVars[] AssignedVars[~q_write_ev~0] 22932#L107-1 [375] L107-1-->L108: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 22933#L108 [408] L108-->L247: Formula: (and (= v_~q_free~0_3 0) (= v_~p_dw_pc~0_7 1) (= v_~p_dw_st~0_10 2)) InVars {~q_free~0=v_~q_free~0_3} OutVars{~p_dw_pc~0=v_~p_dw_pc~0_7, ~q_free~0=v_~q_free~0_3, ~p_dw_st~0=v_~p_dw_st~0_10} AuxVars[] AssignedVars[~p_dw_st~0, ~p_dw_pc~0] 22955#L247 37.10/18.54 [2019-03-28 12:18:46,532 INFO L796 eck$LassoCheckResult]: Loop: 22955#L247 [410] L247-->L266: Formula: (and (= 0 v_~c_dr_st~0_10) (= v_ULTIMATE.start_eval_~tmp___0~1_4 |v_ULTIMATE.start_eval_#t~nondet5_3|)) InVars {~c_dr_st~0=v_~c_dr_st~0_10, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_3|} OutVars{~c_dr_st~0=v_~c_dr_st~0_10, ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_4, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_2|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp___0~1] 22877#L266 [314] L266-->L262: Formula: (= v_ULTIMATE.start_eval_~tmp___0~1_1 0) InVars {ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_1} OutVars{ULTIMATE.start_eval_~tmp___0~1=v_ULTIMATE.start_eval_~tmp___0~1_1} AuxVars[] AssignedVars[] 22879#L262 [522] L262-->L214: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 22947#L214 [460] L214-->L218: Formula: (> v_~p_dw_st~0_7 0) InVars {~p_dw_st~0=v_~p_dw_st~0_7} OutVars{~p_dw_st~0=v_~p_dw_st~0_7} AuxVars[] AssignedVars[] 22940#L218 [385] L218-->L226: Formula: (and (= 0 v_~c_dr_st~0_7) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_12 1)) InVars {~c_dr_st~0=v_~c_dr_st~0_7} OutVars{~c_dr_st~0=v_~c_dr_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_12} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 22941#L226 [523] L226-->L242: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___1~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_16, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret3=|v_ULTIMATE.start_eval_#t~ret3_5|, ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret3, ULTIMATE.start_eval_~tmp___1~0] 23088#L242 [468] L242-->L242-1: Formula: (> v_ULTIMATE.start_eval_~tmp___1~0_4 0) InVars {ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} OutVars{ULTIMATE.start_eval_~tmp___1~0=v_ULTIMATE.start_eval_~tmp___1~0_4} AuxVars[] AssignedVars[] 23087#L242-1 [469] L242-1-->L247: Formula: (> v_~p_dw_st~0_12 0) InVars {~p_dw_st~0=v_~p_dw_st~0_12} OutVars{~p_dw_st~0=v_~p_dw_st~0_12} AuxVars[] AssignedVars[] 22955#L247 37.10/18.54 [2019-03-28 12:18:46,532 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.54 [2019-03-28 12:18:46,532 INFO L82 PathProgramCache]: Analyzing trace with hash 1806161270, now seen corresponding path program 1 times 37.10/18.54 [2019-03-28 12:18:46,532 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.54 [2019-03-28 12:18:46,532 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.54 [2019-03-28 12:18:46,533 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:46,533 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:46,533 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:46,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 37.10/18.54 [2019-03-28 12:18:46,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 37.10/18.54 [2019-03-28 12:18:46,550 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.54 [2019-03-28 12:18:46,550 INFO L82 PathProgramCache]: Analyzing trace with hash 1779815054, now seen corresponding path program 1 times 37.10/18.54 [2019-03-28 12:18:46,550 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.54 [2019-03-28 12:18:46,550 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.54 [2019-03-28 12:18:46,551 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:46,551 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:46,551 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:46,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 37.10/18.54 [2019-03-28 12:18:46,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 37.10/18.54 [2019-03-28 12:18:46,556 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 37.10/18.54 [2019-03-28 12:18:46,556 INFO L82 PathProgramCache]: Analyzing trace with hash -228629757, now seen corresponding path program 1 times 37.10/18.54 [2019-03-28 12:18:46,556 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 37.10/18.54 [2019-03-28 12:18:46,556 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 37.10/18.54 [2019-03-28 12:18:46,562 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:46,562 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:46,562 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 37.10/18.54 [2019-03-28 12:18:46,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 37.10/18.54 [2019-03-28 12:18:46,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 37.10/18.54 [2019-03-28 12:18:46,864 WARN L188 SmtUtils]: Spent 240.00 ms on a formula simplification. DAG size of input: 90 DAG size of output: 84 37.10/18.54 [2019-03-28 12:18:46,942 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 28.03 12:18:46 BasicIcfg 37.10/18.54 [2019-03-28 12:18:46,942 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- 37.10/18.54 [2019-03-28 12:18:46,943 INFO L168 Benchmark]: Toolchain (without parser) took 12793.73 ms. Allocated memory was 649.6 MB in the beginning and 867.2 MB in the end (delta: 217.6 MB). Free memory was 559.1 MB in the beginning and 651.0 MB in the end (delta: -91.9 MB). Peak memory consumption was 125.7 MB. Max. memory is 50.3 GB. 37.10/18.54 [2019-03-28 12:18:46,943 INFO L168 Benchmark]: CDTParser took 0.16 ms. Allocated memory is still 649.6 MB. Free memory is still 580.1 MB. There was no memory consumed. Max. memory is 50.3 GB. 37.10/18.54 [2019-03-28 12:18:46,944 INFO L168 Benchmark]: CACSL2BoogieTranslator took 374.24 ms. Allocated memory is still 649.6 MB. Free memory was 558.0 MB in the beginning and 613.5 MB in the end (delta: -55.5 MB). Peak memory consumption was 31.5 MB. Max. memory is 50.3 GB. 37.10/18.54 [2019-03-28 12:18:46,944 INFO L168 Benchmark]: Boogie Procedure Inliner took 50.19 ms. Allocated memory is still 649.6 MB. Free memory was 612.4 MB in the beginning and 610.3 MB in the end (delta: 2.2 MB). Peak memory consumption was 2.2 MB. Max. memory is 50.3 GB. 37.10/18.54 [2019-03-28 12:18:46,945 INFO L168 Benchmark]: Boogie Preprocessor took 31.06 ms. Allocated memory is still 649.6 MB. Free memory was 610.3 MB in the beginning and 608.1 MB in the end (delta: 2.2 MB). Peak memory consumption was 2.2 MB. Max. memory is 50.3 GB. 37.10/18.54 [2019-03-28 12:18:46,945 INFO L168 Benchmark]: RCFGBuilder took 431.58 ms. Allocated memory is still 649.6 MB. Free memory was 608.1 MB in the beginning and 578.4 MB in the end (delta: 29.7 MB). Peak memory consumption was 29.7 MB. Max. memory is 50.3 GB. 37.10/18.54 [2019-03-28 12:18:46,946 INFO L168 Benchmark]: BlockEncodingV2 took 155.52 ms. Allocated memory is still 649.6 MB. Free memory was 578.4 MB in the beginning and 563.2 MB in the end (delta: 15.1 MB). Peak memory consumption was 15.1 MB. Max. memory is 50.3 GB. 37.10/18.54 [2019-03-28 12:18:46,946 INFO L168 Benchmark]: TraceAbstraction took 198.08 ms. Allocated memory is still 649.6 MB. Free memory was 563.2 MB in the beginning and 547.0 MB in the end (delta: 16.2 MB). Peak memory consumption was 16.2 MB. Max. memory is 50.3 GB. 37.10/18.54 [2019-03-28 12:18:46,947 INFO L168 Benchmark]: BuchiAutomizer took 11547.86 ms. Allocated memory was 649.6 MB in the beginning and 867.2 MB in the end (delta: 217.6 MB). Free memory was 547.0 MB in the beginning and 651.0 MB in the end (delta: -104.0 MB). Peak memory consumption was 113.6 MB. Max. memory is 50.3 GB. 37.10/18.54 [2019-03-28 12:18:46,950 INFO L337 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### 37.10/18.54 --- Results --- 37.10/18.54 * Results from de.uni_freiburg.informatik.ultimate.plugins.blockencoding: 37.10/18.54 - StatisticsResult: Initial Icfg 37.10/18.54 75 locations, 115 edges 37.10/18.54 - StatisticsResult: Encoded RCFG 37.10/18.54 52 locations, 111 edges 37.10/18.54 * Results from de.uni_freiburg.informatik.ultimate.core: 37.10/18.54 - StatisticsResult: Toolchain Benchmarks 37.10/18.54 Benchmark results are: 37.10/18.54 * CDTParser took 0.16 ms. Allocated memory is still 649.6 MB. Free memory is still 580.1 MB. There was no memory consumed. Max. memory is 50.3 GB. 37.10/18.54 * CACSL2BoogieTranslator took 374.24 ms. Allocated memory is still 649.6 MB. Free memory was 558.0 MB in the beginning and 613.5 MB in the end (delta: -55.5 MB). Peak memory consumption was 31.5 MB. Max. memory is 50.3 GB. 37.10/18.54 * Boogie Procedure Inliner took 50.19 ms. Allocated memory is still 649.6 MB. Free memory was 612.4 MB in the beginning and 610.3 MB in the end (delta: 2.2 MB). Peak memory consumption was 2.2 MB. Max. memory is 50.3 GB. 37.10/18.54 * Boogie Preprocessor took 31.06 ms. Allocated memory is still 649.6 MB. Free memory was 610.3 MB in the beginning and 608.1 MB in the end (delta: 2.2 MB). Peak memory consumption was 2.2 MB. Max. memory is 50.3 GB. 37.10/18.54 * RCFGBuilder took 431.58 ms. Allocated memory is still 649.6 MB. Free memory was 608.1 MB in the beginning and 578.4 MB in the end (delta: 29.7 MB). Peak memory consumption was 29.7 MB. Max. memory is 50.3 GB. 37.10/18.54 * BlockEncodingV2 took 155.52 ms. Allocated memory is still 649.6 MB. Free memory was 578.4 MB in the beginning and 563.2 MB in the end (delta: 15.1 MB). Peak memory consumption was 15.1 MB. Max. memory is 50.3 GB. 37.10/18.54 * TraceAbstraction took 198.08 ms. Allocated memory is still 649.6 MB. Free memory was 563.2 MB in the beginning and 547.0 MB in the end (delta: 16.2 MB). Peak memory consumption was 16.2 MB. Max. memory is 50.3 GB. 37.10/18.54 * BuchiAutomizer took 11547.86 ms. Allocated memory was 649.6 MB in the beginning and 867.2 MB in the end (delta: 217.6 MB). Free memory was 547.0 MB in the beginning and 651.0 MB in the end (delta: -104.0 MB). Peak memory consumption was 113.6 MB. Max. memory is 50.3 GB. 37.10/18.54 * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: 37.10/18.54 - AllSpecificationsHoldResult: All specifications hold 37.10/18.54 We were not able to verify any specifiation because the program does not contain any specification. 37.10/18.54 - InvariantResult [Line: 66]: Loop Invariant 37.10/18.54 Derived loop invariant: 1 37.10/18.54 - InvariantResult [Line: 192]: Loop Invariant 37.10/18.54 Derived loop invariant: 1 37.10/18.54 - InvariantResult [Line: 237]: Loop Invariant 37.10/18.54 Derived loop invariant: 1 37.10/18.54 - InvariantResult [Line: 242]: Loop Invariant 37.10/18.54 Derived loop invariant: 1 37.10/18.54 - InvariantResult [Line: 50]: Loop Invariant 37.10/18.54 Derived loop invariant: 1 37.10/18.54 - InvariantResult [Line: 138]: Loop Invariant 37.10/18.54 Derived loop invariant: 1 37.10/18.54 - InvariantResult [Line: 50]: Loop Invariant 37.10/18.54 Derived loop invariant: 1 37.10/18.54 - InvariantResult [Line: 95]: Loop Invariant 37.10/18.54 Derived loop invariant: 1 37.10/18.54 - InvariantResult [Line: 31]: Loop Invariant 37.10/18.54 Derived loop invariant: 1 37.10/18.54 - InvariantResult [Line: -1]: Loop Invariant 37.10/18.54 Derived loop invariant: 1 37.10/18.54 - InvariantResult [Line: 288]: Loop Invariant 37.10/18.54 Derived loop invariant: 1 37.10/18.54 - InvariantResult [Line: 31]: Loop Invariant 37.10/18.54 Derived loop invariant: 1 37.10/18.54 - InvariantResult [Line: 213]: Loop Invariant 37.10/18.54 Derived loop invariant: 1 37.10/18.54 - InvariantResult [Line: 237]: Loop Invariant 37.10/18.54 Derived loop invariant: 1 37.10/18.54 - InvariantResult [Line: 213]: Loop Invariant 37.10/18.54 Derived loop invariant: 1 37.10/18.54 - InvariantResult [Line: 95]: Loop Invariant 37.10/18.54 Derived loop invariant: 1 37.10/18.54 - InvariantResult [Line: 66]: Loop Invariant 37.10/18.54 Derived loop invariant: 1 37.10/18.54 - InvariantResult [Line: 142]: Loop Invariant 37.10/18.54 Derived loop invariant: 1 37.10/18.54 - StatisticsResult: Ultimate Automizer benchmark data 37.10/18.54 CFG has 1 procedures, 52 locations, 0 error locations. SAFE Result, 0.1s OverallTime, 0 OverallIterations, 0 TraceHistogramMax, 0.0s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: No data available, PredicateUnifierStatistics: No data available, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=52occurred in iteration=0, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: No data available, HoareAnnotationStatistics: 0.0s HoareAnnotationTime, 18 LocationsWithAnnotation, 18 PreInvPairs, 18 NumberOfFragments, 18 HoareAnnotationTreeSize, 18 FomulaSimplifications, 0 FormulaSimplificationTreeSizeReduction, 0.0s HoareSimplificationTime, 18 FomulaSimplificationsInter, 0 FormulaSimplificationTreeSizeReductionInter, 0.0s HoareSimplificationTimeInter, RefinementEngineStatistics: No data available, ReuseStatistics: No data available 37.10/18.54 - StatisticsResult: Constructed decomposition of program 37.10/18.54 Your program was decomposed into 23 terminating modules (22 trivial, 0 deterministic, 1 nondeterministic) and one nonterminating remainder module.One nondeterministic module has affine ranking function -2 * q_free + 1 and consists of 14 locations. 22 modules have a trivial ranking function, the largest among these consists of 4 locations. The remainder module has 240 locations. 37.10/18.54 - StatisticsResult: Timing statistics 37.10/18.54 BüchiAutomizer plugin needed 11.4s and 23 iterations. TraceHistogramMax:3. Analysis of lassos took 2.7s. Construction of modules took 2.6s. Büchi inclusion checks took 5.5s. Highest rank in rank-based complementation 3. Minimization of det autom 8. Minimization of nondet autom 15. Automata minimization 0.2s AutomataMinimizationTime, 23 MinimizatonAttempts, 1470 StatesRemovedByMinimization, 12 NontrivialMinimizations. Non-live state removal took 0.2s Buchi closure took 0.0s. Biggest automaton had 717 states and ocurred in iteration 17. Nontrivial modules had stage [1, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 1465 SDtfs, 2849 SDslu, 2049 SDs, 0 SdLazy, 2902 SolverSat, 158 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 2.6s Time LassoAnalysisResults: nont1 unkn0 SFLI13 SFLT0 conc0 concLT1 SILN0 SILU0 SILI8 SILT0 lasso0 LassoPreprocessingBenchmarks: Lassos: inital97 mio100 ax100 hnf100 lsp14 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq214 hnf86 smp100 dnf100 smp100 tf107 neg100 sie100 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 13ms VariablesStem: 0 VariablesLoop: 3 DisjunctsStem: 1 DisjunctsLoop: 1 SupportingInvariants: 0 MotzkinApplications: 2 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 2 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 1 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s 37.10/18.54 - TerminationAnalysisResult: Nontermination possible 37.10/18.54 Buchi Automizer proved that your program is nonterminating for some inputs 37.10/18.54 - FixpointNonTerminationResult [Line: 262]: Nontermination argument in form of an infinite program execution. 37.10/18.54 Nontermination argument in form of an infinite execution 37.10/18.54 State at position 0 is 37.10/18.54 {} 37.10/18.54 State at position 1 is 37.10/18.54 {p_last_write=3, c_dr_i=1, c_dr_pc=0, a_t=0, \result=0, \result=0, c_num_read=0, tmp=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@31a544dc=0, c_dr_st=0, kernel_st=1, q_read_ev=2, p_dw_i=1, tmp___0=0, tmp___1=1, q_write_ev=2, __retres1=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@32e1efe2=0, p_dw_pc=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2c3f2c2e=0, tmp=0, q_free=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2c820743=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@600a7add=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@8077171=0, p_dw_st=2, \result=0, tmp___0=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6eb1c287=0, tmp=0, c_last_read=0, __retres1=0, p_num_write=1, q_buf_0=3, __retres1=0, \result=1} 37.10/18.54 - StatisticsResult: NonterminationArgumentStatistics 37.10/18.54 Fixpoint 37.10/18.54 - NonterminatingLassoResult [Line: 237]: Nonterminating execution 37.10/18.54 Found a nonterminating execution for the following lasso shaped sequence of statements. 37.10/18.54 Stem: 37.10/18.54 [L14] int q_buf_0 ; 37.10/18.54 [L15] int q_free ; 37.10/18.54 [L16] int q_read_ev ; 37.10/18.55 [L17] int q_write_ev ; 37.10/18.55 [L18] int p_num_write ; 37.10/18.55 [L19] int p_last_write ; 37.10/18.55 [L20] int p_dw_st ; 37.10/18.55 [L21] int p_dw_pc ; 37.10/18.55 [L22] int p_dw_i ; 37.10/18.55 [L23] int c_num_read ; 37.10/18.55 [L24] int c_last_read ; 37.10/18.55 [L25] int c_dr_st ; 37.10/18.55 [L26] int c_dr_pc ; 37.10/18.55 [L27] int c_dr_i ; 37.10/18.55 [L134] static int a_t ; 37.10/18.55 [L350] int __retres1 ; 37.10/18.55 [L336] q_free = 1 37.10/18.55 [L337] q_write_ev = 2 37.10/18.55 [L338] q_read_ev = q_write_ev 37.10/18.55 [L339] p_num_write = 0 37.10/18.55 [L340] p_dw_pc = 0 37.10/18.55 [L341] p_dw_i = 1 37.10/18.55 [L342] c_num_read = 0 37.10/18.55 [L343] c_dr_pc = 0 37.10/18.55 [L344] c_dr_i = 1 37.10/18.55 [L304] int kernel_st ; 37.10/18.55 [L305] int tmp ; 37.10/18.55 [L309] kernel_st = 0 37.10/18.55 [L196] COND TRUE (int )p_dw_i == 1 37.10/18.55 [L197] p_dw_st = 0 37.10/18.55 [L201] COND TRUE (int )c_dr_i == 1 37.10/18.55 [L202] c_dr_st = 0 37.10/18.55 [L313] COND TRUE 1 37.10/18.55 [L316] kernel_st = 1 37.10/18.55 [L231] int tmp ; 37.10/18.55 [L232] int tmp___0 ; 37.10/18.55 [L233] int tmp___1 ; 37.10/18.55 [L237] COND TRUE 1 37.10/18.55 [L211] int __retres1 ; 37.10/18.55 [L214] COND TRUE (int )p_dw_st == 0 37.10/18.55 [L215] __retres1 = 1 37.10/18.55 [L227] return (__retres1); 37.10/18.55 [L240] tmp___1 = exists_runnable_thread() 37.10/18.55 [L242] COND TRUE \read(tmp___1) 37.10/18.55 [L247] COND TRUE (int )p_dw_st == 0 37.10/18.55 [L249] tmp = __VERIFIER_nondet_int() 37.10/18.55 [L251] COND TRUE \read(tmp) 37.10/18.55 [L253] p_dw_st = 1 37.10/18.55 [L96] COND TRUE (int )p_dw_pc == 0 37.10/18.55 [L107] COND TRUE 1 37.10/18.55 [L109] COND FALSE !((int )q_free == 0) 37.10/18.55 [L119] q_buf_0 = __VERIFIER_nondet_int() 37.10/18.55 [L120] p_last_write = q_buf_0 37.10/18.55 [L121] p_num_write += 1 37.10/18.55 [L122] q_free = 0 37.10/18.55 [L123] q_write_ev = 1 37.10/18.55 [L67] int tmp ; 37.10/18.55 [L68] int tmp___0 ; 37.10/18.55 [L29] int __retres1 ; 37.10/18.55 [L32] COND FALSE !((int )p_dw_pc == 1) 37.10/18.55 [L42] __retres1 = 0 37.10/18.55 [L44] return (__retres1); 37.10/18.55 [L72] tmp = is_do_write_p_triggered() 37.10/18.55 [L74] COND FALSE !(\read(tmp)) 37.10/18.55 [L48] int __retres1 ; 37.10/18.55 [L51] COND FALSE !((int )c_dr_pc == 1) 37.10/18.55 [L61] __retres1 = 0 37.10/18.55 [L63] return (__retres1); 37.10/18.55 [L80] tmp___0 = is_do_read_c_triggered() 37.10/18.55 [L82] COND FALSE !(\read(tmp___0)) 37.10/18.55 [L125] q_write_ev = 2 37.10/18.55 [L107] COND TRUE 1 37.10/18.55 [L109] COND TRUE (int )q_free == 0 37.10/18.55 [L110] p_dw_st = 2 37.10/18.55 [L111] p_dw_pc = 1 37.10/18.55 Loop: 37.10/18.55 [L262] COND TRUE (int )c_dr_st == 0 37.10/18.55 [L264] tmp___0 = __VERIFIER_nondet_int() 37.10/18.55 [L266] COND FALSE !(\read(tmp___0)) 37.10/18.55 [L237] COND TRUE 1 37.10/18.55 [L211] int __retres1 ; 37.10/18.55 [L214] COND FALSE !((int )p_dw_st == 0) 37.10/18.55 [L218] COND TRUE (int )c_dr_st == 0 37.10/18.55 [L219] __retres1 = 1 37.10/18.55 [L227] return (__retres1); 37.10/18.55 [L240] tmp___1 = exists_runnable_thread() 37.10/18.55 [L242] COND TRUE \read(tmp___1) 37.10/18.55 [L247] COND FALSE !((int )p_dw_st == 0) 37.10/18.55 End of lasso representation. 37.10/18.55 RESULT: Ultimate proved your program to be incorrect! 37.10/18.55 !SESSION 2019-03-28 12:18:30.267 ----------------------------------------------- 37.10/18.55 eclipse.buildId=unknown 37.10/18.55 java.version=1.8.0_181 37.10/18.55 java.vendor=Oracle Corporation 37.10/18.55 BootLoader constants: OS=linux, ARCH=x86_64, WS=gtk, NL=en_US 37.10/18.55 Framework arguments: -tc ./../AutomizerAndBuchiAutomizerCInlineWithBlockEncoding.xml -s ./../termcomp2017.epf -i /export/starexec/sandbox/benchmark/theBenchmark.c 37.10/18.55 Command-line arguments: -os linux -ws gtk -arch x86_64 -consoleLog -data @user.home/.ultimate -tc ./../AutomizerAndBuchiAutomizerCInlineWithBlockEncoding.xml -s ./../termcomp2017.epf -data /export/starexec/sandbox/tmp -i /export/starexec/sandbox/benchmark/theBenchmark.c 37.10/18.55 37.10/18.55 !ENTRY org.eclipse.core.resources 2 10035 2019-03-28 12:18:47.196 37.10/18.55 !MESSAGE The workspace will exit with unsaved changes in this session. 37.10/18.55 Received shutdown request... 37.10/18.55 Ultimate: 37.10/18.55 GTK+ Version Check 37.10/18.55 EOF