54.07/20.04 NO 54.07/20.04 54.07/20.04 Ultimate: Cannot open display: 54.07/20.04 This is Ultimate 0.1.24-8dc7c08-m 54.07/20.04 [2019-03-28 12:18:45,367 INFO L170 SettingsManager]: Resetting all preferences to default values... 54.07/20.04 [2019-03-28 12:18:45,370 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values 54.07/20.04 [2019-03-28 12:18:45,381 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... 54.07/20.04 [2019-03-28 12:18:45,381 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values 54.07/20.04 [2019-03-28 12:18:45,382 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values 54.07/20.04 [2019-03-28 12:18:45,384 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values 54.07/20.04 [2019-03-28 12:18:45,385 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values 54.07/20.04 [2019-03-28 12:18:45,387 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values 54.07/20.04 [2019-03-28 12:18:45,387 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values 54.07/20.04 [2019-03-28 12:18:45,388 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... 54.07/20.04 [2019-03-28 12:18:45,389 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values 54.07/20.04 [2019-03-28 12:18:45,389 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values 54.07/20.04 [2019-03-28 12:18:45,390 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values 54.07/20.04 [2019-03-28 12:18:45,391 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values 54.07/20.04 [2019-03-28 12:18:45,392 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values 54.07/20.04 [2019-03-28 12:18:45,393 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values 54.07/20.04 [2019-03-28 12:18:45,394 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values 54.07/20.04 [2019-03-28 12:18:45,396 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values 54.07/20.04 [2019-03-28 12:18:45,398 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values 54.07/20.04 [2019-03-28 12:18:45,399 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values 54.07/20.04 [2019-03-28 12:18:45,400 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values 54.07/20.04 [2019-03-28 12:18:45,403 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 54.07/20.04 [2019-03-28 12:18:45,403 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... 54.07/20.04 [2019-03-28 12:18:45,403 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values 54.07/20.04 [2019-03-28 12:18:45,404 INFO L174 SettingsManager]: Resetting IcfgToChc preferences to default values 54.07/20.04 [2019-03-28 12:18:45,404 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values 54.07/20.04 [2019-03-28 12:18:45,405 INFO L177 SettingsManager]: ReqToTest provides no preferences, ignoring... 54.07/20.04 [2019-03-28 12:18:45,405 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values 54.07/20.04 [2019-03-28 12:18:45,406 INFO L174 SettingsManager]: Resetting ChcSmtPrinter preferences to default values 54.07/20.04 [2019-03-28 12:18:45,407 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values 54.07/20.04 [2019-03-28 12:18:45,408 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values 54.07/20.04 [2019-03-28 12:18:45,409 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... 54.07/20.04 [2019-03-28 12:18:45,409 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values 54.07/20.04 [2019-03-28 12:18:45,409 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... 54.07/20.04 [2019-03-28 12:18:45,410 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... 54.07/20.04 [2019-03-28 12:18:45,410 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values 54.07/20.04 [2019-03-28 12:18:45,411 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values 54.07/20.04 [2019-03-28 12:18:45,411 INFO L181 SettingsManager]: Finished resetting all preferences to default values... 54.07/20.04 [2019-03-28 12:18:45,412 INFO L98 SettingsManager]: Beginning loading settings from /export/starexec/sandbox/solver/bin/./../termcomp2017.epf 54.07/20.04 [2019-03-28 12:18:45,426 INFO L110 SettingsManager]: Loading preferences was successful 54.07/20.04 [2019-03-28 12:18:45,427 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: 54.07/20.04 [2019-03-28 12:18:45,428 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: 54.07/20.04 [2019-03-28 12:18:45,428 INFO L133 SettingsManager]: * Rewrite not-equals=true 54.07/20.04 [2019-03-28 12:18:45,428 INFO L133 SettingsManager]: * Create parallel compositions if possible=false 54.07/20.04 [2019-03-28 12:18:45,429 INFO L133 SettingsManager]: * Minimize states using LBE with the strategy=SINGLE 54.07/20.04 [2019-03-28 12:18:45,429 INFO L133 SettingsManager]: * Use SBE=true 54.07/20.04 [2019-03-28 12:18:45,429 INFO L131 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: 54.07/20.04 [2019-03-28 12:18:45,429 INFO L133 SettingsManager]: * Use old map elimination=false 54.07/20.04 [2019-03-28 12:18:45,429 INFO L133 SettingsManager]: * Use external solver (rank synthesis)=false 54.07/20.04 [2019-03-28 12:18:45,430 INFO L133 SettingsManager]: * Buchi interpolant automaton construction strategy=DANDELION 54.07/20.04 [2019-03-28 12:18:45,430 INFO L133 SettingsManager]: * Use only trivial implications for array writes=true 54.07/20.04 [2019-03-28 12:18:45,430 INFO L133 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES 54.07/20.04 [2019-03-28 12:18:45,430 INFO L133 SettingsManager]: * Construct termination proof for TermComp=true 54.07/20.04 [2019-03-28 12:18:45,430 INFO L133 SettingsManager]: * Command for external solver (GNTA synthesis)=z3 SMTLIB2_COMPLIANT=true -memory:4560 -smt2 -in -t:12000 54.07/20.04 [2019-03-28 12:18:45,431 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: 54.07/20.04 [2019-03-28 12:18:45,431 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false 54.07/20.04 [2019-03-28 12:18:45,431 INFO L133 SettingsManager]: * Check division by zero=IGNORE 54.07/20.04 [2019-03-28 12:18:45,431 INFO L133 SettingsManager]: * Check if freed pointer was valid=false 54.07/20.04 [2019-03-28 12:18:45,431 INFO L133 SettingsManager]: * Assume nondeterminstic values are in range=false 54.07/20.04 [2019-03-28 12:18:45,431 INFO L133 SettingsManager]: * How to treat unsigned ints differently from normal ones=IGNORE 54.07/20.04 [2019-03-28 12:18:45,432 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: 54.07/20.04 [2019-03-28 12:18:45,432 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements 54.07/20.04 [2019-03-28 12:18:45,432 INFO L133 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump 54.07/20.04 [2019-03-28 12:18:45,432 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:4560 -smt2 -in -t:5000 54.07/20.04 [2019-03-28 12:18:45,432 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: 54.07/20.04 [2019-03-28 12:18:45,433 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles 54.07/20.04 [2019-03-28 12:18:45,433 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL 54.07/20.04 [2019-03-28 12:18:45,433 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true 54.07/20.04 [2019-03-28 12:18:45,458 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp 54.07/20.04 [2019-03-28 12:18:45,471 INFO L259 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized 54.07/20.04 [2019-03-28 12:18:45,475 INFO L215 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. 54.07/20.04 [2019-03-28 12:18:45,476 INFO L271 PluginConnector]: Initializing CDTParser... 54.07/20.04 [2019-03-28 12:18:45,477 INFO L276 PluginConnector]: CDTParser initialized 54.07/20.04 [2019-03-28 12:18:45,478 INFO L430 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /export/starexec/sandbox/benchmark/theBenchmark.c 54.07/20.04 [2019-03-28 12:18:45,542 INFO L221 CDTParser]: Created temporary CDT project at /export/starexec/sandbox/tmp/5a6fc5a497eb4ac78c3c47874f0af4e3/FLAG7f1393c93 54.07/20.04 [2019-03-28 12:18:45,900 INFO L307 CDTParser]: Found 1 translation units. 54.07/20.04 [2019-03-28 12:18:45,901 INFO L161 CDTParser]: Scanning /export/starexec/sandbox/benchmark/theBenchmark.c 54.07/20.04 [2019-03-28 12:18:45,910 INFO L355 CDTParser]: About to delete temporary CDT project at /export/starexec/sandbox/tmp/5a6fc5a497eb4ac78c3c47874f0af4e3/FLAG7f1393c93 54.07/20.04 [2019-03-28 12:18:46,285 INFO L363 CDTParser]: Successfully deleted /export/starexec/sandbox/tmp/5a6fc5a497eb4ac78c3c47874f0af4e3 54.07/20.04 [2019-03-28 12:18:46,297 INFO L297 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### 54.07/20.04 [2019-03-28 12:18:46,299 INFO L131 ToolchainWalker]: Walking toolchain with 7 elements. 54.07/20.04 [2019-03-28 12:18:46,300 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- 54.07/20.04 [2019-03-28 12:18:46,300 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... 54.07/20.04 [2019-03-28 12:18:46,304 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized 54.07/20.04 [2019-03-28 12:18:46,305 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.03 12:18:46" (1/1) ... 54.07/20.04 [2019-03-28 12:18:46,308 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5a0a5f65 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:18:46, skipping insertion in model container 54.07/20.04 [2019-03-28 12:18:46,308 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.03 12:18:46" (1/1) ... 54.07/20.04 [2019-03-28 12:18:46,316 INFO L145 MainTranslator]: Starting translation in SV-COMP mode 54.07/20.04 [2019-03-28 12:18:46,352 INFO L176 MainTranslator]: Built tables and reachable declarations 54.07/20.04 [2019-03-28 12:18:46,552 INFO L206 PostProcessor]: Analyzing one entry point: main 54.07/20.04 [2019-03-28 12:18:46,558 INFO L191 MainTranslator]: Completed pre-run 54.07/20.04 [2019-03-28 12:18:46,659 INFO L206 PostProcessor]: Analyzing one entry point: main 54.07/20.04 [2019-03-28 12:18:46,679 INFO L195 MainTranslator]: Completed translation 54.07/20.04 [2019-03-28 12:18:46,679 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:18:46 WrapperNode 54.07/20.04 [2019-03-28 12:18:46,680 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- 54.07/20.04 [2019-03-28 12:18:46,681 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- 54.07/20.04 [2019-03-28 12:18:46,681 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... 54.07/20.04 [2019-03-28 12:18:46,681 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized 54.07/20.04 [2019-03-28 12:18:46,690 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:18:46" (1/1) ... 54.07/20.04 [2019-03-28 12:18:46,698 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:18:46" (1/1) ... 54.07/20.04 [2019-03-28 12:18:46,730 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- 54.07/20.04 [2019-03-28 12:18:46,731 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- 54.07/20.04 [2019-03-28 12:18:46,731 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... 54.07/20.04 [2019-03-28 12:18:46,731 INFO L276 PluginConnector]: Boogie Preprocessor initialized 54.07/20.04 [2019-03-28 12:18:46,741 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:18:46" (1/1) ... 54.07/20.04 [2019-03-28 12:18:46,741 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:18:46" (1/1) ... 54.07/20.04 [2019-03-28 12:18:46,744 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:18:46" (1/1) ... 54.07/20.04 [2019-03-28 12:18:46,744 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:18:46" (1/1) ... 54.07/20.04 [2019-03-28 12:18:46,750 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:18:46" (1/1) ... 54.07/20.04 [2019-03-28 12:18:46,759 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:18:46" (1/1) ... 54.07/20.04 [2019-03-28 12:18:46,761 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:18:46" (1/1) ... 54.07/20.04 [2019-03-28 12:18:46,765 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- 54.07/20.04 [2019-03-28 12:18:46,765 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- 54.07/20.04 [2019-03-28 12:18:46,765 INFO L271 PluginConnector]: Initializing RCFGBuilder... 54.07/20.04 [2019-03-28 12:18:46,766 INFO L276 PluginConnector]: RCFGBuilder initialized 54.07/20.04 [2019-03-28 12:18:46,766 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:18:46" (1/1) ... 54.07/20.04 No working directory specified, using /export/starexec/sandbox/solver/bin/z3 54.07/20.04 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:4560 -smt2 -in -t:5000 (exit command is (exit), workingDir is null) 54.07/20.04 Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:4560 -smt2 -in -t:5000 54.07/20.04 [2019-03-28 12:18:46,832 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start 54.07/20.04 [2019-03-28 12:18:46,832 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start 54.07/20.04 [2019-03-28 12:18:47,298 INFO L281 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) 54.07/20.04 [2019-03-28 12:18:47,298 INFO L286 CfgBuilder]: Removed 64 assue(true) statements. 54.07/20.04 [2019-03-28 12:18:47,300 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.03 12:18:47 BoogieIcfgContainer 54.07/20.04 [2019-03-28 12:18:47,300 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- 54.07/20.04 [2019-03-28 12:18:47,301 INFO L113 PluginConnector]: ------------------------BlockEncodingV2---------------------------- 54.07/20.04 [2019-03-28 12:18:47,301 INFO L271 PluginConnector]: Initializing BlockEncodingV2... 54.07/20.04 [2019-03-28 12:18:47,303 INFO L276 PluginConnector]: BlockEncodingV2 initialized 54.07/20.04 [2019-03-28 12:18:47,304 INFO L185 PluginConnector]: Executing the observer BlockEncodingObserver from plugin BlockEncodingV2 for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.03 12:18:47" (1/1) ... 54.07/20.04 [2019-03-28 12:18:47,327 INFO L313 BlockEncoder]: Initial Icfg 107 locations, 179 edges 54.07/20.04 [2019-03-28 12:18:47,329 INFO L258 BlockEncoder]: Using Remove infeasible edges 54.07/20.04 [2019-03-28 12:18:47,330 INFO L263 BlockEncoder]: Using Maximize final states 54.07/20.04 [2019-03-28 12:18:47,330 INFO L270 BlockEncoder]: Using Minimize states even if more edges are added than removed.=false 54.07/20.04 [2019-03-28 12:18:47,331 INFO L276 BlockEncoder]: Using Minimize states using LBE with the strategy=SINGLE 54.07/20.04 [2019-03-28 12:18:47,332 INFO L296 BlockEncoder]: Using Remove sink states 54.07/20.04 [2019-03-28 12:18:47,333 INFO L171 BlockEncoder]: Using Apply optimizations until nothing changes=true 54.07/20.04 [2019-03-28 12:18:47,334 INFO L179 BlockEncoder]: Using Rewrite not-equals 54.07/20.04 [2019-03-28 12:18:47,374 INFO L185 BlockEncoder]: Using Use SBE 54.07/20.04 [2019-03-28 12:18:47,425 INFO L200 BlockEncoder]: SBE split 69 edges 54.07/20.04 [2019-03-28 12:18:47,431 INFO L70 emoveInfeasibleEdges]: Removed 5 edges and 0 locations because of local infeasibility 54.07/20.04 [2019-03-28 12:18:47,433 INFO L71 MaximizeFinalStates]: 0 new accepting states 54.07/20.04 [2019-03-28 12:18:47,461 INFO L100 BaseMinimizeStates]: Removed 26 edges and 13 locations by large block encoding 54.07/20.04 [2019-03-28 12:18:47,464 INFO L70 RemoveSinkStates]: Removed 5 edges and 3 locations by removing sink states 54.07/20.04 [2019-03-28 12:18:47,466 INFO L70 emoveInfeasibleEdges]: Removed 0 edges and 0 locations because of local infeasibility 54.07/20.04 [2019-03-28 12:18:47,466 INFO L71 MaximizeFinalStates]: 0 new accepting states 54.07/20.04 [2019-03-28 12:18:47,469 INFO L100 BaseMinimizeStates]: Removed 2 edges and 1 locations by large block encoding 54.07/20.04 [2019-03-28 12:18:47,469 INFO L70 RemoveSinkStates]: Removed 0 edges and 0 locations by removing sink states 54.07/20.04 [2019-03-28 12:18:47,470 INFO L70 emoveInfeasibleEdges]: Removed 0 edges and 0 locations because of local infeasibility 54.07/20.04 [2019-03-28 12:18:47,471 INFO L71 MaximizeFinalStates]: 0 new accepting states 54.07/20.04 [2019-03-28 12:18:47,471 INFO L100 BaseMinimizeStates]: Removed 0 edges and 0 locations by large block encoding 54.07/20.04 [2019-03-28 12:18:47,472 INFO L70 RemoveSinkStates]: Removed 0 edges and 0 locations by removing sink states 54.07/20.04 [2019-03-28 12:18:47,472 INFO L313 BlockEncoder]: Encoded RCFG 90 locations, 224 edges 54.07/20.04 [2019-03-28 12:18:47,473 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.blockencoding CFG 28.03 12:18:47 BasicIcfg 54.07/20.04 [2019-03-28 12:18:47,473 INFO L132 PluginConnector]: ------------------------ END BlockEncodingV2---------------------------- 54.07/20.04 [2019-03-28 12:18:47,474 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- 54.07/20.04 [2019-03-28 12:18:47,474 INFO L271 PluginConnector]: Initializing TraceAbstraction... 54.07/20.04 [2019-03-28 12:18:47,478 INFO L276 PluginConnector]: TraceAbstraction initialized 54.07/20.04 [2019-03-28 12:18:47,478 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 28.03 12:18:46" (1/4) ... 54.07/20.04 [2019-03-28 12:18:47,479 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@773cbfff and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.03 12:18:47, skipping insertion in model container 54.07/20.04 [2019-03-28 12:18:47,479 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:18:46" (2/4) ... 54.07/20.04 [2019-03-28 12:18:47,479 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@773cbfff and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.03 12:18:47, skipping insertion in model container 54.07/20.04 [2019-03-28 12:18:47,480 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.03 12:18:47" (3/4) ... 54.07/20.04 [2019-03-28 12:18:47,480 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@773cbfff and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.03 12:18:47, skipping insertion in model container 54.07/20.05 [2019-03-28 12:18:47,480 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.blockencoding CFG 28.03 12:18:47" (4/4) ... 54.07/20.05 [2019-03-28 12:18:47,482 INFO L112 eAbstractionObserver]: Analyzing ICFG theBenchmark.c_BEv2 54.07/20.05 [2019-03-28 12:18:47,492 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:ForwardPredicates Determinization: PREDICATE_ABSTRACTION 54.07/20.05 [2019-03-28 12:18:47,500 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 0 error locations. 54.07/20.05 [2019-03-28 12:18:47,517 INFO L257 AbstractCegarLoop]: Starting to check reachability of 0 error locations. 54.07/20.05 [2019-03-28 12:18:47,546 INFO L133 ementStrategyFactory]: Using default assertion order modulation 54.07/20.05 [2019-03-28 12:18:47,547 INFO L382 AbstractCegarLoop]: Interprodecural is true 54.07/20.05 [2019-03-28 12:18:47,547 INFO L383 AbstractCegarLoop]: Hoare is true 54.07/20.05 [2019-03-28 12:18:47,547 INFO L384 AbstractCegarLoop]: Compute interpolants for ForwardPredicates 54.07/20.05 [2019-03-28 12:18:47,547 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE 54.07/20.05 [2019-03-28 12:18:47,547 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION 54.07/20.05 [2019-03-28 12:18:47,548 INFO L387 AbstractCegarLoop]: Difference is false 54.07/20.05 [2019-03-28 12:18:47,548 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA 54.07/20.05 [2019-03-28 12:18:47,548 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== 54.07/20.05 [2019-03-28 12:18:47,564 INFO L276 IsEmpty]: Start isEmpty. Operand 90 states. 54.07/20.05 [2019-03-28 12:18:47,572 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. 54.07/20.05 [2019-03-28 12:18:47,577 INFO L343 DoubleDeckerVisitor]: Before removal of dead ends 90 states. 54.07/20.05 [2019-03-28 12:18:47,653 INFO L448 ceAbstractionStarter]: For program point L258-1(lines 258 263) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,653 INFO L448 ceAbstractionStarter]: For program point L349-1(lines 343 371) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,654 INFO L448 ceAbstractionStarter]: For program point L316-1(lines 310 338) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,654 INFO L448 ceAbstractionStarter]: For program point L349-3(lines 343 371) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,654 INFO L448 ceAbstractionStarter]: For program point L316-3(lines 310 338) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,654 INFO L448 ceAbstractionStarter]: For program point L52(lines 52 56) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,654 INFO L451 ceAbstractionStarter]: At program point L209(lines 201 239) the Hoare annotation is: true 54.07/20.05 [2019-03-28 12:18:47,655 INFO L451 ceAbstractionStarter]: At program point L209-1(lines 201 239) the Hoare annotation is: true 54.07/20.05 [2019-03-28 12:18:47,655 INFO L448 ceAbstractionStarter]: For program point L69(lines 41 91) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,655 INFO L448 ceAbstractionStarter]: For program point L127(lines 127 132) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,655 INFO L451 ceAbstractionStarter]: At program point ULTIMATE.startENTRY(line -1) the Hoare annotation is: true 54.07/20.05 [2019-03-28 12:18:47,655 INFO L448 ceAbstractionStarter]: For program point L127-2(lines 127 132) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,655 INFO L448 ceAbstractionStarter]: For program point L127-3(lines 127 132) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,656 INFO L448 ceAbstractionStarter]: For program point L127-5(lines 127 132) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,656 INFO L451 ceAbstractionStarter]: At program point L119(lines 96 121) the Hoare annotation is: true 54.07/20.05 [2019-03-28 12:18:47,656 INFO L451 ceAbstractionStarter]: At program point L119-1(lines 96 121) the Hoare annotation is: true 54.07/20.05 [2019-03-28 12:18:47,656 INFO L448 ceAbstractionStarter]: For program point L202(lines 202 208) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,656 INFO L451 ceAbstractionStarter]: At program point L202-1(lines 201 239) the Hoare annotation is: true 54.07/20.05 [2019-03-28 12:18:47,656 INFO L448 ceAbstractionStarter]: For program point L202-2(lines 202 208) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,657 INFO L451 ceAbstractionStarter]: At program point L202-3(lines 201 239) the Hoare annotation is: true 54.07/20.05 [2019-03-28 12:18:47,657 INFO L448 ceAbstractionStarter]: For program point L359-1(lines 343 371) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,657 INFO L448 ceAbstractionStarter]: For program point L70(lines 70 74) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,657 INFO L448 ceAbstractionStarter]: For program point L326-1(lines 310 338) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,657 INFO L448 ceAbstractionStarter]: For program point L359-3(lines 343 371) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,657 INFO L448 ceAbstractionStarter]: For program point L326-3(lines 310 338) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,658 INFO L451 ceAbstractionStarter]: At program point L285(lines 275 300) the Hoare annotation is: true 54.07/20.05 [2019-03-28 12:18:47,658 INFO L448 ceAbstractionStarter]: For program point L63(lines 63 67) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,658 INFO L448 ceAbstractionStarter]: For program point L63-2(lines 41 91) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,658 INFO L448 ceAbstractionStarter]: For program point L187(lines 187 192) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,658 INFO L448 ceAbstractionStarter]: For program point L187-2(lines 187 192) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,658 INFO L448 ceAbstractionStarter]: For program point L187-3(lines 187 192) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,658 INFO L448 ceAbstractionStarter]: For program point L344-1(lines 343 371) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,659 INFO L448 ceAbstractionStarter]: For program point L311-1(lines 310 338) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,659 INFO L448 ceAbstractionStarter]: For program point L187-5(lines 187 192) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,659 INFO L448 ceAbstractionStarter]: For program point L311-2(lines 311 315) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,659 INFO L448 ceAbstractionStarter]: For program point L344-3(lines 343 371) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,659 INFO L451 ceAbstractionStarter]: At program point L245-1(lines 311 315) the Hoare annotation is: true 54.07/20.05 [2019-03-28 12:18:47,659 INFO L448 ceAbstractionStarter]: For program point L311-4(lines 310 338) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,659 INFO L448 ceAbstractionStarter]: For program point L105(lines 105 115) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,660 INFO L448 ceAbstractionStarter]: For program point L105-1(lines 105 115) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,660 INFO L448 ceAbstractionStarter]: For program point L97(lines 97 117) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,660 INFO L448 ceAbstractionStarter]: For program point L97-1(lines 97 117) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,660 INFO L448 ceAbstractionStarter]: For program point L81(lines 81 85) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,660 INFO L448 ceAbstractionStarter]: For program point L81-2(lines 78 86) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,660 INFO L448 ceAbstractionStarter]: For program point L172(lines 172 177) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,661 INFO L448 ceAbstractionStarter]: For program point L172-2(lines 172 177) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,661 INFO L448 ceAbstractionStarter]: For program point L172-3(lines 172 177) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,661 INFO L448 ceAbstractionStarter]: For program point L172-5(lines 172 177) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,661 INFO L451 ceAbstractionStarter]: At program point L230(lines 245 249) the Hoare annotation is: true 54.07/20.05 [2019-03-28 12:18:47,661 INFO L451 ceAbstractionStarter]: At program point L230-1(lines 198 240) the Hoare annotation is: true 54.07/20.05 [2019-03-28 12:18:47,661 INFO L448 ceAbstractionStarter]: For program point L354-1(lines 343 371) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,661 INFO L448 ceAbstractionStarter]: For program point L321-1(lines 310 338) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,662 INFO L448 ceAbstractionStarter]: For program point L354-3(lines 343 371) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,662 INFO L448 ceAbstractionStarter]: For program point L321-3(lines 310 338) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,662 INFO L451 ceAbstractionStarter]: At program point L280(lines 280 284) the Hoare annotation is: true 54.07/20.05 [2019-03-28 12:18:47,662 INFO L448 ceAbstractionStarter]: For program point L280-1(lines 275 300) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,662 INFO L451 ceAbstractionStarter]: At program point L404(lines 393 406) the Hoare annotation is: true 54.07/20.05 [2019-03-28 12:18:47,662 INFO L448 ceAbstractionStarter]: For program point L289(lines 289 296) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,663 INFO L451 ceAbstractionStarter]: At program point L223(lines 201 239) the Hoare annotation is: true 54.07/20.05 [2019-03-28 12:18:47,663 INFO L451 ceAbstractionStarter]: At program point L223-1(lines 201 239) the Hoare annotation is: true 54.07/20.05 [2019-03-28 12:18:47,663 INFO L448 ceAbstractionStarter]: For program point L157(lines 157 162) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,663 INFO L448 ceAbstractionStarter]: For program point L380(lines 380 384) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,663 INFO L448 ceAbstractionStarter]: For program point L157-2(lines 157 162) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,663 INFO L451 ceAbstractionStarter]: At program point L380-2(lines 344 348) the Hoare annotation is: true 54.07/20.05 [2019-03-28 12:18:47,663 INFO L448 ceAbstractionStarter]: For program point L157-3(lines 157 162) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,664 INFO L448 ceAbstractionStarter]: For program point L380-3(lines 380 384) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,664 INFO L448 ceAbstractionStarter]: For program point L157-5(lines 157 162) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,664 INFO L451 ceAbstractionStarter]: At program point L380-5(lines 344 348) the Hoare annotation is: true 54.07/20.05 [2019-03-28 12:18:47,664 INFO L448 ceAbstractionStarter]: For program point L397(lines 397 402) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,664 INFO L451 ceAbstractionStarter]: At program point L331-1(lines 307 339) the Hoare annotation is: true 54.07/20.05 [2019-03-28 12:18:47,664 INFO L448 ceAbstractionStarter]: For program point L42(lines 42 50) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,665 INFO L451 ceAbstractionStarter]: At program point L265(lines 257 267) the Hoare annotation is: true 54.07/20.05 [2019-03-28 12:18:47,665 INFO L448 ceAbstractionStarter]: For program point L42-1(lines 41 91) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,665 INFO L451 ceAbstractionStarter]: At program point L364-3(lines 340 372) the Hoare annotation is: true 54.07/20.05 [2019-03-28 12:18:47,665 INFO L451 ceAbstractionStarter]: At program point L331-3(lines 307 339) the Hoare annotation is: true 54.07/20.05 [2019-03-28 12:18:47,665 INFO L451 ceAbstractionStarter]: At program point L265-1(lines 257 267) the Hoare annotation is: true 54.07/20.05 [2019-03-28 12:18:47,665 INFO L451 ceAbstractionStarter]: At program point L422-1(lines 340 444) the Hoare annotation is: true 54.07/20.05 [2019-03-28 12:18:47,666 INFO L451 ceAbstractionStarter]: At program point L216(lines 201 239) the Hoare annotation is: true 54.07/20.05 [2019-03-28 12:18:47,666 INFO L451 ceAbstractionStarter]: At program point L216-1(lines 201 239) the Hoare annotation is: true 54.07/20.05 [2019-03-28 12:18:47,666 INFO L448 ceAbstractionStarter]: For program point L51(lines 41 91) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,666 INFO L448 ceAbstractionStarter]: For program point L142(lines 142 147) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,666 INFO L448 ceAbstractionStarter]: For program point L109(lines 109 114) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,666 INFO L448 ceAbstractionStarter]: For program point L142-2(lines 142 147) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,667 INFO L448 ceAbstractionStarter]: For program point L109-1(lines 109 114) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,667 INFO L448 ceAbstractionStarter]: For program point L142-3(lines 142 147) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,667 INFO L448 ceAbstractionStarter]: For program point L43(lines 43 47) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,667 INFO L448 ceAbstractionStarter]: For program point L142-5(lines 142 147) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,667 INFO L448 ceAbstractionStarter]: For program point L101(lines 101 116) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,667 INFO L448 ceAbstractionStarter]: For program point L101-1(lines 101 116) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,667 INFO L448 ceAbstractionStarter]: For program point L258(lines 258 263) no Hoare annotation was computed. 54.07/20.05 [2019-03-28 12:18:47,677 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.03 12:18:47 BasicIcfg 54.07/20.05 [2019-03-28 12:18:47,678 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- 54.07/20.05 [2019-03-28 12:18:47,678 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- 54.07/20.05 [2019-03-28 12:18:47,679 INFO L271 PluginConnector]: Initializing BuchiAutomizer... 54.07/20.05 [2019-03-28 12:18:47,682 INFO L276 PluginConnector]: BuchiAutomizer initialized 54.07/20.05 [2019-03-28 12:18:47,683 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis 54.07/20.05 [2019-03-28 12:18:47,683 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 28.03 12:18:46" (1/5) ... 54.07/20.05 [2019-03-28 12:18:47,684 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@71dbaeed and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.03 12:18:47, skipping insertion in model container 54.07/20.05 [2019-03-28 12:18:47,684 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis 54.07/20.05 [2019-03-28 12:18:47,684 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:18:46" (2/5) ... 54.07/20.05 [2019-03-28 12:18:47,684 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@71dbaeed and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.03 12:18:47, skipping insertion in model container 54.07/20.05 [2019-03-28 12:18:47,684 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis 54.07/20.05 [2019-03-28 12:18:47,685 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.03 12:18:47" (3/5) ... 54.07/20.05 [2019-03-28 12:18:47,685 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@71dbaeed and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 28.03 12:18:47, skipping insertion in model container 54.07/20.05 [2019-03-28 12:18:47,685 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis 54.07/20.05 [2019-03-28 12:18:47,685 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.blockencoding CFG 28.03 12:18:47" (4/5) ... 54.07/20.05 [2019-03-28 12:18:47,685 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@71dbaeed and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 28.03 12:18:47, skipping insertion in model container 54.07/20.05 [2019-03-28 12:18:47,686 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis 54.07/20.05 [2019-03-28 12:18:47,686 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.03 12:18:47" (5/5) ... 54.07/20.05 [2019-03-28 12:18:47,687 INFO L375 chiAutomizerObserver]: Analyzing ICFG theBenchmark.c_BEv2 54.07/20.05 [2019-03-28 12:18:47,712 INFO L133 ementStrategyFactory]: Using default assertion order modulation 54.07/20.05 [2019-03-28 12:18:47,713 INFO L374 BuchiCegarLoop]: Interprodecural is true 54.07/20.05 [2019-03-28 12:18:47,713 INFO L375 BuchiCegarLoop]: Hoare is true 54.07/20.05 [2019-03-28 12:18:47,713 INFO L376 BuchiCegarLoop]: Compute interpolants for ForwardPredicates 54.07/20.05 [2019-03-28 12:18:47,713 INFO L377 BuchiCegarLoop]: Backedges is STRAIGHT_LINE 54.07/20.05 [2019-03-28 12:18:47,713 INFO L378 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION 54.07/20.05 [2019-03-28 12:18:47,713 INFO L379 BuchiCegarLoop]: Difference is false 54.07/20.05 [2019-03-28 12:18:47,714 INFO L380 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA 54.07/20.05 [2019-03-28 12:18:47,714 INFO L383 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== 54.07/20.05 [2019-03-28 12:18:47,718 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 90 states. 54.07/20.05 [2019-03-28 12:18:47,742 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 56 54.07/20.05 [2019-03-28 12:18:47,743 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 54.07/20.05 [2019-03-28 12:18:47,743 INFO L119 BuchiIsEmpty]: Starting construction of run 54.07/20.05 [2019-03-28 12:18:47,751 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.05 [2019-03-28 12:18:47,752 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.05 [2019-03-28 12:18:47,752 INFO L442 BuchiCegarLoop]: ======== Iteration 1============ 54.07/20.05 [2019-03-28 12:18:47,752 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 90 states. 54.07/20.05 [2019-03-28 12:18:47,757 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 56 54.07/20.05 [2019-03-28 12:18:47,757 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 54.07/20.05 [2019-03-28 12:18:47,757 INFO L119 BuchiIsEmpty]: Starting construction of run 54.07/20.05 [2019-03-28 12:18:47,759 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.05 [2019-03-28 12:18:47,759 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.05 [2019-03-28 12:18:47,765 INFO L794 eck$LassoCheckResult]: Stem: 50#ULTIMATE.startENTRYtrue [885] ULTIMATE.startENTRY-->L202: Formula: (and (= v_~d0_ev~0_23 2) (= 0 v_~z_val~0_13) (= 2 v_~b1_ev~0_23) (= v_~d0_val_t~0_9 1) (= v_~b0_val~0_13 0) (= 1 v_~b1_val_t~0_9) (= 1 v_~d1_req_up~0_12) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_9 0) (= 2 v_~d1_ev~0_23) (= v_~b1_val~0_13 0) (= v_~b0_val_t~0_9 1) (= v_~b0_req_up~0_12 1) (= 0 v_~comp_m1_i~0_7) (= v_~d0_req_up~0_12 1) (= v_~comp_m1_st~0_15 0) (= v_~b0_ev~0_23 2) (= 1 v_~d1_val_t~0_9) (= v_~z_req_up~0_12 0) (= v_~z_val_t~0_10 0) (= 0 v_~d1_val~0_13) (= v_~z_ev~0_19 2) (= v_~b1_req_up~0_12 1) (= 0 v_~d0_val~0_13)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_4|, ~b1_val~0=v_~b1_val~0_13, ~b0_val~0=v_~b0_val~0_13, ~d0_req_up~0=v_~d0_req_up~0_12, ~d0_val~0=v_~d0_val~0_13, ~d1_val_t~0=v_~d1_val_t~0_9, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_9, ~d1_ev~0=v_~d1_ev~0_23, ~d1_val~0=v_~d1_val~0_13, ~b0_req_up~0=v_~b0_req_up~0_12, ~z_ev~0=v_~z_ev~0_19, ~b1_val_t~0=v_~b1_val_t~0_9, ~b1_ev~0=v_~b1_ev~0_23, ULTIMATE.start_main_~__retres1~2=v_ULTIMATE.start_main_~__retres1~2_6, ~z_val~0=v_~z_val~0_13, ~d1_req_up~0=v_~d1_req_up~0_12, ~z_val_t~0=v_~z_val_t~0_10, ~b0_val_t~0=v_~b0_val_t~0_9, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~z_req_up~0=v_~z_req_up~0_12, ~b1_req_up~0=v_~b1_req_up~0_12, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~d0_ev~0=v_~d0_ev~0_23, ~b0_ev~0=v_~b0_ev~0_23, ~d0_val_t~0=v_~d0_val_t~0_9, ~comp_m1_st~0=v_~comp_m1_st~0_15, ~comp_m1_i~0=v_~comp_m1_i~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ~b1_val~0, ~b0_val~0, ~d0_req_up~0, ~d0_val~0, ~d1_val_t~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~d1_ev~0, ~d1_val~0, ~b0_req_up~0, ~z_ev~0, ~b1_val_t~0, ~b1_ev~0, ULTIMATE.start_main_~__retres1~2, ~z_val~0, ~d1_req_up~0, ~z_val_t~0, ~b0_val_t~0, ULTIMATE.start_start_simulation_~tmp~3, ~z_req_up~0, ~b1_req_up~0, ULTIMATE.start_main_#res, ~d0_ev~0, ~b0_ev~0, ~d0_val_t~0, ~comp_m1_st~0, ~comp_m1_i~0] 66#L202true [747] L202-->L202-1: Formula: (< 1 v_~b0_req_up~0_6) InVars {~b0_req_up~0=v_~b0_req_up~0_6} OutVars{~b0_req_up~0=v_~b0_req_up~0_6} AuxVars[] AssignedVars[] 46#L202-1true [751] L202-1-->L209: Formula: (> 1 v_~b1_req_up~0_6) InVars {~b1_req_up~0=v_~b1_req_up~0_6} OutVars{~b1_req_up~0=v_~b1_req_up~0_6} AuxVars[] AssignedVars[] 37#L209true [755] L209-->L216: Formula: (< v_~d0_req_up~0_6 1) InVars {~d0_req_up~0=v_~d0_req_up~0_6} OutVars{~d0_req_up~0=v_~d0_req_up~0_6} AuxVars[] AssignedVars[] 56#L216true [759] L216-->L223: Formula: (> v_~d1_req_up~0_6 1) InVars {~d1_req_up~0=v_~d1_req_up~0_6} OutVars{~d1_req_up~0=v_~d1_req_up~0_6} AuxVars[] AssignedVars[] 48#L223true [763] L223-->L230: Formula: (< 1 v_~z_req_up~0_6) InVars {~z_req_up~0=v_~z_req_up~0_6} OutVars{~z_req_up~0=v_~z_req_up~0_6} AuxVars[] AssignedVars[] 8#L230true [767] L230-->L245-1: Formula: (and (> 1 v_~comp_m1_i~0_4) (= v_~comp_m1_st~0_5 2)) InVars {~comp_m1_i~0=v_~comp_m1_i~0_4} OutVars{~comp_m1_st~0=v_~comp_m1_st~0_5, ~comp_m1_i~0=v_~comp_m1_i~0_4} AuxVars[] AssignedVars[~comp_m1_st~0] 18#L245-1true [769] L245-1-->L311-1: Formula: (> v_~b0_ev~0_7 0) InVars {~b0_ev~0=v_~b0_ev~0_7} OutVars{~b0_ev~0=v_~b0_ev~0_7} AuxVars[] AssignedVars[] 41#L311-1true [628] L311-1-->L316-1: Formula: (and (= 0 v_~b1_ev~0_6) (= v_~b1_ev~0_5 1)) InVars {~b1_ev~0=v_~b1_ev~0_6} OutVars{~b1_ev~0=v_~b1_ev~0_5} AuxVars[] AssignedVars[~b1_ev~0] 70#L316-1true [654] L316-1-->L321-1: Formula: (and (= v_~d0_ev~0_5 1) (= v_~d0_ev~0_6 0)) InVars {~d0_ev~0=v_~d0_ev~0_6} OutVars{~d0_ev~0=v_~d0_ev~0_5} AuxVars[] AssignedVars[~d0_ev~0] 14#L321-1true [507] L321-1-->L326-1: Formula: (and (= 0 v_~d1_ev~0_6) (= v_~d1_ev~0_5 1)) InVars {~d1_ev~0=v_~d1_ev~0_6} OutVars{~d1_ev~0=v_~d1_ev~0_5} AuxVars[] AssignedVars[~d1_ev~0] 58#L326-1true [556] L326-1-->L331-1: Formula: (and (= 0 v_~z_ev~0_6) (= v_~z_ev~0_5 1)) InVars {~z_ev~0=v_~z_ev~0_6} OutVars{~z_ev~0=v_~z_ev~0_5} AuxVars[] AssignedVars[~z_ev~0] 79#L331-1true [583] L331-1-->L97: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_1|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 86#L97true [591] L97-->L119: Formula: (and (= v_~b0_ev~0_11 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4 1)) InVars {~b0_ev~0=v_~b0_ev~0_11} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4, ~b0_ev~0=v_~b0_ev~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 88#L119true [886] L119-->L380: Formula: (and (= |v_ULTIMATE.start_is_method1_triggered_#res_7| v_ULTIMATE.start_activate_threads_~tmp~1_13) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19 |v_ULTIMATE.start_is_method1_triggered_#res_7|)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_13, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_7|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_7|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 26#L380true [615] L380-->L380-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_9) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} AuxVars[] AssignedVars[] 30#L380-2true [618] L380-2-->L344-1: Formula: (and (= v_~b0_ev~0_15 2) (= v_~b0_ev~0_16 1)) InVars {~b0_ev~0=v_~b0_ev~0_16} OutVars{~b0_ev~0=v_~b0_ev~0_15} AuxVars[] AssignedVars[~b0_ev~0] 39#L344-1true [791] L344-1-->L349-1: Formula: (> 1 v_~b1_ev~0_17) InVars {~b1_ev~0=v_~b1_ev~0_17} OutVars{~b1_ev~0=v_~b1_ev~0_17} AuxVars[] AssignedVars[] 69#L349-1true [652] L349-1-->L354-1: Formula: (and (= v_~d0_ev~0_15 2) (= v_~d0_ev~0_16 1)) InVars {~d0_ev~0=v_~d0_ev~0_16} OutVars{~d0_ev~0=v_~d0_ev~0_15} AuxVars[] AssignedVars[~d0_ev~0] 11#L354-1true [795] L354-1-->L359-1: Formula: (> 1 v_~d1_ev~0_17) InVars {~d1_ev~0=v_~d1_ev~0_17} OutVars{~d1_ev~0=v_~d1_ev~0_17} AuxVars[] AssignedVars[] 55#L359-1true [797] L359-1-->L422-1: Formula: (> v_~z_ev~0_13 1) InVars {~z_ev~0=v_~z_ev~0_13} OutVars{~z_ev~0=v_~z_ev~0_13} AuxVars[] AssignedVars[] 71#L422-1true 54.07/20.05 [2019-03-28 12:18:47,767 INFO L796 eck$LassoCheckResult]: Loop: 71#L422-1true [887] L422-1-->L285: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 1) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 13#L285true [888] L285-->L258: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_13, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res] 90#L258true [802] L258-->L265: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8 0) (> 0 v_~comp_m1_st~0_9)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_9} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8, ~comp_m1_st~0=v_~comp_m1_st~0_9} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 62#L265true [889] L265-->L280: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___0~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 91#L280true [890] L280-->L202-2: Formula: (and (= v_ULTIMATE.start_eval_~tmp___0~0_8 0) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 2)) InVars {ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 43#L202-2true [800] L202-2-->L202-3: Formula: (> 1 v_~b0_req_up~0_9) InVars {~b0_req_up~0=v_~b0_req_up~0_9} OutVars{~b0_req_up~0=v_~b0_req_up~0_9} AuxVars[] AssignedVars[] 40#L202-3true [806] L202-3-->L209-1: Formula: (< 1 v_~b1_req_up~0_9) InVars {~b1_req_up~0=v_~b1_req_up~0_9} OutVars{~b1_req_up~0=v_~b1_req_up~0_9} AuxVars[] AssignedVars[] 33#L209-1true [810] L209-1-->L216-1: Formula: (> v_~d0_req_up~0_9 1) InVars {~d0_req_up~0=v_~d0_req_up~0_9} OutVars{~d0_req_up~0=v_~d0_req_up~0_9} AuxVars[] AssignedVars[] 54#L216-1true [814] L216-1-->L223-1: Formula: (> v_~d1_req_up~0_9 1) InVars {~d1_req_up~0=v_~d1_req_up~0_9} OutVars{~d1_req_up~0=v_~d1_req_up~0_9} AuxVars[] AssignedVars[] 16#L223-1true [820] L223-1-->L230-1: Formula: (< 1 v_~z_req_up~0_9) InVars {~z_req_up~0=v_~z_req_up~0_9} OutVars{~z_req_up~0=v_~z_req_up~0_9} AuxVars[] AssignedVars[] 5#L230-1true [498] L230-1-->L311-2: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 3) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 44#L311-2true [632] L311-2-->L311-4: Formula: (and (= v_~b0_ev~0_8 1) (= v_~b0_ev~0_9 0)) InVars {~b0_ev~0=v_~b0_ev~0_9} OutVars{~b0_ev~0=v_~b0_ev~0_8} AuxVars[] AssignedVars[~b0_ev~0] 21#L311-4true [832] L311-4-->L316-3: Formula: (> 0 v_~b1_ev~0_10) InVars {~b1_ev~0=v_~b1_ev~0_10} OutVars{~b1_ev~0=v_~b1_ev~0_10} AuxVars[] AssignedVars[] 60#L316-3true [838] L316-3-->L321-3: Formula: (< v_~d0_ev~0_10 0) InVars {~d0_ev~0=v_~d0_ev~0_10} OutVars{~d0_ev~0=v_~d0_ev~0_10} AuxVars[] AssignedVars[] 83#L321-3true [662] L321-3-->L326-3: Formula: (and (= v_~d1_ev~0_8 1) (= 0 v_~d1_ev~0_9)) InVars {~d1_ev~0=v_~d1_ev~0_9} OutVars{~d1_ev~0=v_~d1_ev~0_8} AuxVars[] AssignedVars[~d1_ev~0] 34#L326-3true [850] L326-3-->L331-3: Formula: (> v_~z_ev~0_10 0) InVars {~z_ev~0=v_~z_ev~0_10} OutVars{~z_ev~0=v_~z_ev~0_10} AuxVars[] AssignedVars[] 68#L331-3true [570] L331-3-->L97-1: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_4|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_10, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 84#L97-1true [588] L97-1-->L119-1: Formula: (and (= v_~b0_ev~0_13 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13 1)) InVars {~b0_ev~0=v_~b0_ev~0_13} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13, ~b0_ev~0=v_~b0_ev~0_13} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 85#L119-1true [891] L119-1-->L380-3: Formula: (and (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20 |v_ULTIMATE.start_is_method1_triggered_#res_8|) (= |v_ULTIMATE.start_is_method1_triggered_#res_8| v_ULTIMATE.start_activate_threads_~tmp~1_14)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_14, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_8|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_8|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 4#L380-3true [864] L380-3-->L380-5: Formula: (and (= v_~comp_m1_st~0_7 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11, ~comp_m1_st~0=v_~comp_m1_st~0_7} AuxVars[] AssignedVars[~comp_m1_st~0] 9#L380-5true [868] L380-5-->L344-3: Formula: (< v_~b0_ev~0_20 1) InVars {~b0_ev~0=v_~b0_ev~0_20} OutVars{~b0_ev~0=v_~b0_ev~0_20} AuxVars[] AssignedVars[] 45#L344-3true [870] L344-3-->L349-3: Formula: (< 1 v_~b1_ev~0_20) InVars {~b1_ev~0=v_~b1_ev~0_20} OutVars{~b1_ev~0=v_~b1_ev~0_20} AuxVars[] AssignedVars[] 72#L349-3true [656] L349-3-->L354-3: Formula: (and (= v_~d0_ev~0_18 2) (= v_~d0_ev~0_19 1)) InVars {~d0_ev~0=v_~d0_ev~0_19} OutVars{~d0_ev~0=v_~d0_ev~0_18} AuxVars[] AssignedVars[~d0_ev~0] 19#L354-3true [513] L354-3-->L359-3: Formula: (and (= 1 v_~d1_ev~0_19) (= v_~d1_ev~0_18 2)) InVars {~d1_ev~0=v_~d1_ev~0_19} OutVars{~d1_ev~0=v_~d1_ev~0_18} AuxVars[] AssignedVars[~d1_ev~0] 32#L359-3true [531] L359-3-->L364-3: Formula: (and (= v_~z_ev~0_15 1) (= v_~z_ev~0_14 2)) InVars {~z_ev~0=v_~z_ev~0_15} OutVars{~z_ev~0=v_~z_ev~0_14} AuxVars[] AssignedVars[~z_ev~0] 67#L364-3true [568] L364-3-->L258-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_5, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_2|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_#res] 87#L258-1true [666] L258-1-->L265-1: Formula: (and (= v_~comp_m1_st~0_10 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9 1)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_10} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9, ~comp_m1_st~0=v_~comp_m1_st~0_10} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 61#L265-1true [892] L265-1-->L397: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_stop_simulation_~tmp~2_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_4|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_~tmp~2] 75#L397true [880] L397-->L404: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_4 0) (< 0 v_ULTIMATE.start_stop_simulation_~tmp~2_5)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_4, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 65#L404true [897] L404-->L422-1: Formula: (and (= 0 v_ULTIMATE.start_start_simulation_~tmp~3_9) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= |v_ULTIMATE.start_stop_simulation_#res_5| v_ULTIMATE.start_start_simulation_~tmp~3_9)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_~tmp~3] 71#L422-1true 54.07/20.05 [2019-03-28 12:18:47,773 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.05 [2019-03-28 12:18:47,773 INFO L82 PathProgramCache]: Analyzing trace with hash 783833340, now seen corresponding path program 1 times 54.07/20.05 [2019-03-28 12:18:47,775 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.05 [2019-03-28 12:18:47,776 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.05 [2019-03-28 12:18:47,796 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:47,796 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:47,797 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:47,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.05 [2019-03-28 12:18:47,877 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.05 [2019-03-28 12:18:47,880 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.05 [2019-03-28 12:18:47,880 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 54.07/20.05 [2019-03-28 12:18:47,885 INFO L799 eck$LassoCheckResult]: stem already infeasible 54.07/20.05 [2019-03-28 12:18:47,885 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.05 [2019-03-28 12:18:47,886 INFO L82 PathProgramCache]: Analyzing trace with hash -285154061, now seen corresponding path program 1 times 54.07/20.05 [2019-03-28 12:18:47,886 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.05 [2019-03-28 12:18:47,886 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.05 [2019-03-28 12:18:47,887 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:47,887 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:47,887 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:47,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.05 [2019-03-28 12:18:47,930 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.05 [2019-03-28 12:18:47,931 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.05 [2019-03-28 12:18:47,931 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 54.07/20.05 [2019-03-28 12:18:47,932 INFO L811 eck$LassoCheckResult]: loop already infeasible 54.07/20.05 [2019-03-28 12:18:47,947 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 54.07/20.05 [2019-03-28 12:18:47,948 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 54.07/20.05 [2019-03-28 12:18:47,950 INFO L87 Difference]: Start difference. First operand 90 states. Second operand 3 states. 54.07/20.05 [2019-03-28 12:18:48,193 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 54.07/20.05 [2019-03-28 12:18:48,193 INFO L93 Difference]: Finished difference Result 90 states and 222 transitions. 54.07/20.05 [2019-03-28 12:18:48,193 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 54.07/20.05 [2019-03-28 12:18:48,197 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 90 states and 222 transitions. 54.07/20.05 [2019-03-28 12:18:48,201 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 56 54.07/20.05 [2019-03-28 12:18:48,206 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 90 states to 90 states and 222 transitions. 54.07/20.05 [2019-03-28 12:18:48,208 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 90 54.07/20.05 [2019-03-28 12:18:48,208 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 90 54.07/20.05 [2019-03-28 12:18:48,209 INFO L73 IsDeterministic]: Start isDeterministic. Operand 90 states and 222 transitions. 54.07/20.05 [2019-03-28 12:18:48,210 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 54.07/20.05 [2019-03-28 12:18:48,211 INFO L706 BuchiCegarLoop]: Abstraction has 90 states and 222 transitions. 54.07/20.05 [2019-03-28 12:18:48,230 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90 states and 222 transitions. 54.07/20.05 [2019-03-28 12:18:48,247 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90 to 90. 54.07/20.05 [2019-03-28 12:18:48,248 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 90 states. 54.07/20.05 [2019-03-28 12:18:48,249 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90 states to 90 states and 222 transitions. 54.07/20.05 [2019-03-28 12:18:48,250 INFO L729 BuchiCegarLoop]: Abstraction has 90 states and 222 transitions. 54.07/20.05 [2019-03-28 12:18:48,250 INFO L609 BuchiCegarLoop]: Abstraction has 90 states and 222 transitions. 54.07/20.05 [2019-03-28 12:18:48,250 INFO L442 BuchiCegarLoop]: ======== Iteration 2============ 54.07/20.05 [2019-03-28 12:18:48,250 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 90 states and 222 transitions. 54.07/20.05 [2019-03-28 12:18:48,253 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 56 54.07/20.05 [2019-03-28 12:18:48,253 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 54.07/20.05 [2019-03-28 12:18:48,253 INFO L119 BuchiIsEmpty]: Starting construction of run 54.07/20.05 [2019-03-28 12:18:48,254 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.05 [2019-03-28 12:18:48,254 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.05 [2019-03-28 12:18:48,256 INFO L794 eck$LassoCheckResult]: Stem: 257#ULTIMATE.startENTRY [885] ULTIMATE.startENTRY-->L202: Formula: (and (= v_~d0_ev~0_23 2) (= 0 v_~z_val~0_13) (= 2 v_~b1_ev~0_23) (= v_~d0_val_t~0_9 1) (= v_~b0_val~0_13 0) (= 1 v_~b1_val_t~0_9) (= 1 v_~d1_req_up~0_12) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_9 0) (= 2 v_~d1_ev~0_23) (= v_~b1_val~0_13 0) (= v_~b0_val_t~0_9 1) (= v_~b0_req_up~0_12 1) (= 0 v_~comp_m1_i~0_7) (= v_~d0_req_up~0_12 1) (= v_~comp_m1_st~0_15 0) (= v_~b0_ev~0_23 2) (= 1 v_~d1_val_t~0_9) (= v_~z_req_up~0_12 0) (= v_~z_val_t~0_10 0) (= 0 v_~d1_val~0_13) (= v_~z_ev~0_19 2) (= v_~b1_req_up~0_12 1) (= 0 v_~d0_val~0_13)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_4|, ~b1_val~0=v_~b1_val~0_13, ~b0_val~0=v_~b0_val~0_13, ~d0_req_up~0=v_~d0_req_up~0_12, ~d0_val~0=v_~d0_val~0_13, ~d1_val_t~0=v_~d1_val_t~0_9, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_9, ~d1_ev~0=v_~d1_ev~0_23, ~d1_val~0=v_~d1_val~0_13, ~b0_req_up~0=v_~b0_req_up~0_12, ~z_ev~0=v_~z_ev~0_19, ~b1_val_t~0=v_~b1_val_t~0_9, ~b1_ev~0=v_~b1_ev~0_23, ULTIMATE.start_main_~__retres1~2=v_ULTIMATE.start_main_~__retres1~2_6, ~z_val~0=v_~z_val~0_13, ~d1_req_up~0=v_~d1_req_up~0_12, ~z_val_t~0=v_~z_val_t~0_10, ~b0_val_t~0=v_~b0_val_t~0_9, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~z_req_up~0=v_~z_req_up~0_12, ~b1_req_up~0=v_~b1_req_up~0_12, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~d0_ev~0=v_~d0_ev~0_23, ~b0_ev~0=v_~b0_ev~0_23, ~d0_val_t~0=v_~d0_val_t~0_9, ~comp_m1_st~0=v_~comp_m1_st~0_15, ~comp_m1_i~0=v_~comp_m1_i~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ~b1_val~0, ~b0_val~0, ~d0_req_up~0, ~d0_val~0, ~d1_val_t~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~d1_ev~0, ~d1_val~0, ~b0_req_up~0, ~z_ev~0, ~b1_val_t~0, ~b1_ev~0, ULTIMATE.start_main_~__retres1~2, ~z_val~0, ~d1_req_up~0, ~z_val_t~0, ~b0_val_t~0, ULTIMATE.start_start_simulation_~tmp~3, ~z_req_up~0, ~b1_req_up~0, ULTIMATE.start_main_#res, ~d0_ev~0, ~b0_ev~0, ~d0_val_t~0, ~comp_m1_st~0, ~comp_m1_i~0] 258#L202 [746] L202-->L202-1: Formula: (> 1 v_~b0_req_up~0_6) InVars {~b0_req_up~0=v_~b0_req_up~0_6} OutVars{~b0_req_up~0=v_~b0_req_up~0_6} AuxVars[] AssignedVars[] 253#L202-1 [751] L202-1-->L209: Formula: (> 1 v_~b1_req_up~0_6) InVars {~b1_req_up~0=v_~b1_req_up~0_6} OutVars{~b1_req_up~0=v_~b1_req_up~0_6} AuxVars[] AssignedVars[] 232#L209 [755] L209-->L216: Formula: (< v_~d0_req_up~0_6 1) InVars {~d0_req_up~0=v_~d0_req_up~0_6} OutVars{~d0_req_up~0=v_~d0_req_up~0_6} AuxVars[] AssignedVars[] 200#L216 [759] L216-->L223: Formula: (> v_~d1_req_up~0_6 1) InVars {~d1_req_up~0=v_~d1_req_up~0_6} OutVars{~d1_req_up~0=v_~d1_req_up~0_6} AuxVars[] AssignedVars[] 255#L223 [763] L223-->L230: Formula: (< 1 v_~z_req_up~0_6) InVars {~z_req_up~0=v_~z_req_up~0_6} OutVars{~z_req_up~0=v_~z_req_up~0_6} AuxVars[] AssignedVars[] 201#L230 [767] L230-->L245-1: Formula: (and (> 1 v_~comp_m1_i~0_4) (= v_~comp_m1_st~0_5 2)) InVars {~comp_m1_i~0=v_~comp_m1_i~0_4} OutVars{~comp_m1_st~0=v_~comp_m1_st~0_5, ~comp_m1_i~0=v_~comp_m1_i~0_4} AuxVars[] AssignedVars[~comp_m1_st~0] 202#L245-1 [769] L245-1-->L311-1: Formula: (> v_~b0_ev~0_7 0) InVars {~b0_ev~0=v_~b0_ev~0_7} OutVars{~b0_ev~0=v_~b0_ev~0_7} AuxVars[] AssignedVars[] 220#L311-1 [628] L311-1-->L316-1: Formula: (and (= 0 v_~b1_ev~0_6) (= v_~b1_ev~0_5 1)) InVars {~b1_ev~0=v_~b1_ev~0_6} OutVars{~b1_ev~0=v_~b1_ev~0_5} AuxVars[] AssignedVars[~b1_ev~0] 249#L316-1 [654] L316-1-->L321-1: Formula: (and (= v_~d0_ev~0_5 1) (= v_~d0_ev~0_6 0)) InVars {~d0_ev~0=v_~d0_ev~0_6} OutVars{~d0_ev~0=v_~d0_ev~0_5} AuxVars[] AssignedVars[~d0_ev~0] 214#L321-1 [507] L321-1-->L326-1: Formula: (and (= 0 v_~d1_ev~0_6) (= v_~d1_ev~0_5 1)) InVars {~d1_ev~0=v_~d1_ev~0_6} OutVars{~d1_ev~0=v_~d1_ev~0_5} AuxVars[] AssignedVars[~d1_ev~0] 215#L326-1 [556] L326-1-->L331-1: Formula: (and (= 0 v_~z_ev~0_6) (= v_~z_ev~0_5 1)) InVars {~z_ev~0=v_~z_ev~0_6} OutVars{~z_ev~0=v_~z_ev~0_5} AuxVars[] AssignedVars[~z_ev~0] 264#L331-1 [583] L331-1-->L97: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_1|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 277#L97 [591] L97-->L119: Formula: (and (= v_~b0_ev~0_11 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4 1)) InVars {~b0_ev~0=v_~b0_ev~0_11} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4, ~b0_ev~0=v_~b0_ev~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 236#L119 [886] L119-->L380: Formula: (and (= |v_ULTIMATE.start_is_method1_triggered_#res_7| v_ULTIMATE.start_activate_threads_~tmp~1_13) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19 |v_ULTIMATE.start_is_method1_triggered_#res_7|)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_13, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_7|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_7|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 233#L380 [615] L380-->L380-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_9) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} AuxVars[] AssignedVars[] 234#L380-2 [618] L380-2-->L344-1: Formula: (and (= v_~b0_ev~0_15 2) (= v_~b0_ev~0_16 1)) InVars {~b0_ev~0=v_~b0_ev~0_16} OutVars{~b0_ev~0=v_~b0_ev~0_15} AuxVars[] AssignedVars[~b0_ev~0] 239#L344-1 [791] L344-1-->L349-1: Formula: (> 1 v_~b1_ev~0_17) InVars {~b1_ev~0=v_~b1_ev~0_17} OutVars{~b1_ev~0=v_~b1_ev~0_17} AuxVars[] AssignedVars[] 247#L349-1 [652] L349-1-->L354-1: Formula: (and (= v_~d0_ev~0_15 2) (= v_~d0_ev~0_16 1)) InVars {~d0_ev~0=v_~d0_ev~0_16} OutVars{~d0_ev~0=v_~d0_ev~0_15} AuxVars[] AssignedVars[~d0_ev~0] 206#L354-1 [795] L354-1-->L359-1: Formula: (> 1 v_~d1_ev~0_17) InVars {~d1_ev~0=v_~d1_ev~0_17} OutVars{~d1_ev~0=v_~d1_ev~0_17} AuxVars[] AssignedVars[] 207#L359-1 [797] L359-1-->L422-1: Formula: (> v_~z_ev~0_13 1) InVars {~z_ev~0=v_~z_ev~0_13} OutVars{~z_ev~0=v_~z_ev~0_13} AuxVars[] AssignedVars[] 263#L422-1 54.07/20.05 [2019-03-28 12:18:48,257 INFO L796 eck$LassoCheckResult]: Loop: 263#L422-1 [887] L422-1-->L285: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 1) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 208#L285 [888] L285-->L258: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_13, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res] 209#L258 [802] L258-->L265: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8 0) (> 0 v_~comp_m1_st~0_9)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_9} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8, ~comp_m1_st~0=v_~comp_m1_st~0_9} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 268#L265 [889] L265-->L280: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___0~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 269#L280 [890] L280-->L202-2: Formula: (and (= v_ULTIMATE.start_eval_~tmp___0~0_8 0) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 2)) InVars {ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 250#L202-2 [800] L202-2-->L202-3: Formula: (> 1 v_~b0_req_up~0_9) InVars {~b0_req_up~0=v_~b0_req_up~0_9} OutVars{~b0_req_up~0=v_~b0_req_up~0_9} AuxVars[] AssignedVars[] 248#L202-3 [806] L202-3-->L209-1: Formula: (< 1 v_~b1_req_up~0_9) InVars {~b1_req_up~0=v_~b1_req_up~0_9} OutVars{~b1_req_up~0=v_~b1_req_up~0_9} AuxVars[] AssignedVars[] 241#L209-1 [810] L209-1-->L216-1: Formula: (> v_~d0_req_up~0_9 1) InVars {~d0_req_up~0=v_~d0_req_up~0_9} OutVars{~d0_req_up~0=v_~d0_req_up~0_9} AuxVars[] AssignedVars[] 237#L216-1 [814] L216-1-->L223-1: Formula: (> v_~d1_req_up~0_9 1) InVars {~d1_req_up~0=v_~d1_req_up~0_9} OutVars{~d1_req_up~0=v_~d1_req_up~0_9} AuxVars[] AssignedVars[] 205#L223-1 [820] L223-1-->L230-1: Formula: (< 1 v_~z_req_up~0_9) InVars {~z_req_up~0=v_~z_req_up~0_9} OutVars{~z_req_up~0=v_~z_req_up~0_9} AuxVars[] AssignedVars[] 194#L230-1 [498] L230-1-->L311-2: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 3) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 195#L311-2 [632] L311-2-->L311-4: Formula: (and (= v_~b0_ev~0_8 1) (= v_~b0_ev~0_9 0)) InVars {~b0_ev~0=v_~b0_ev~0_9} OutVars{~b0_ev~0=v_~b0_ev~0_8} AuxVars[] AssignedVars[~b0_ev~0] 223#L311-4 [832] L311-4-->L316-3: Formula: (> 0 v_~b1_ev~0_10) InVars {~b1_ev~0=v_~b1_ev~0_10} OutVars{~b1_ev~0=v_~b1_ev~0_10} AuxVars[] AssignedVars[] 224#L316-3 [838] L316-3-->L321-3: Formula: (< v_~d0_ev~0_10 0) InVars {~d0_ev~0=v_~d0_ev~0_10} OutVars{~d0_ev~0=v_~d0_ev~0_10} AuxVars[] AssignedVars[] 265#L321-3 [662] L321-3-->L326-3: Formula: (and (= v_~d1_ev~0_8 1) (= 0 v_~d1_ev~0_9)) InVars {~d1_ev~0=v_~d1_ev~0_9} OutVars{~d1_ev~0=v_~d1_ev~0_8} AuxVars[] AssignedVars[~d1_ev~0] 242#L326-3 [850] L326-3-->L331-3: Formula: (> v_~z_ev~0_10 0) InVars {~z_ev~0=v_~z_ev~0_10} OutVars{~z_ev~0=v_~z_ev~0_10} AuxVars[] AssignedVars[] 243#L331-3 [570] L331-3-->L97-1: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_4|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_10, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 272#L97-1 [588] L97-1-->L119-1: Formula: (and (= v_~b0_ev~0_13 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13 1)) InVars {~b0_ev~0=v_~b0_ev~0_13} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13, ~b0_ev~0=v_~b0_ev~0_13} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 230#L119-1 [891] L119-1-->L380-3: Formula: (and (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20 |v_ULTIMATE.start_is_method1_triggered_#res_8|) (= |v_ULTIMATE.start_is_method1_triggered_#res_8| v_ULTIMATE.start_activate_threads_~tmp~1_14)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_14, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_8|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_8|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 192#L380-3 [864] L380-3-->L380-5: Formula: (and (= v_~comp_m1_st~0_7 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11, ~comp_m1_st~0=v_~comp_m1_st~0_7} AuxVars[] AssignedVars[~comp_m1_st~0] 193#L380-5 [868] L380-5-->L344-3: Formula: (< v_~b0_ev~0_20 1) InVars {~b0_ev~0=v_~b0_ev~0_20} OutVars{~b0_ev~0=v_~b0_ev~0_20} AuxVars[] AssignedVars[] 203#L344-3 [870] L344-3-->L349-3: Formula: (< 1 v_~b1_ev~0_20) InVars {~b1_ev~0=v_~b1_ev~0_20} OutVars{~b1_ev~0=v_~b1_ev~0_20} AuxVars[] AssignedVars[] 252#L349-3 [656] L349-3-->L354-3: Formula: (and (= v_~d0_ev~0_18 2) (= v_~d0_ev~0_19 1)) InVars {~d0_ev~0=v_~d0_ev~0_19} OutVars{~d0_ev~0=v_~d0_ev~0_18} AuxVars[] AssignedVars[~d0_ev~0] 218#L354-3 [513] L354-3-->L359-3: Formula: (and (= 1 v_~d1_ev~0_19) (= v_~d1_ev~0_18 2)) InVars {~d1_ev~0=v_~d1_ev~0_19} OutVars{~d1_ev~0=v_~d1_ev~0_18} AuxVars[] AssignedVars[~d1_ev~0] 219#L359-3 [531] L359-3-->L364-3: Formula: (and (= v_~z_ev~0_15 1) (= v_~z_ev~0_14 2)) InVars {~z_ev~0=v_~z_ev~0_15} OutVars{~z_ev~0=v_~z_ev~0_14} AuxVars[] AssignedVars[~z_ev~0] 240#L364-3 [568] L364-3-->L258-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_5, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_2|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_#res] 271#L258-1 [666] L258-1-->L265-1: Formula: (and (= v_~comp_m1_st~0_10 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9 1)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_10} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9, ~comp_m1_st~0=v_~comp_m1_st~0_10} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 266#L265-1 [892] L265-1-->L397: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_stop_simulation_~tmp~2_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_4|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_~tmp~2] 267#L397 [880] L397-->L404: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_4 0) (< 0 v_ULTIMATE.start_stop_simulation_~tmp~2_5)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_4, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 270#L404 [897] L404-->L422-1: Formula: (and (= 0 v_ULTIMATE.start_start_simulation_~tmp~3_9) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= |v_ULTIMATE.start_stop_simulation_#res_5| v_ULTIMATE.start_start_simulation_~tmp~3_9)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_~tmp~3] 263#L422-1 54.07/20.05 [2019-03-28 12:18:48,257 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.05 [2019-03-28 12:18:48,257 INFO L82 PathProgramCache]: Analyzing trace with hash 1192657565, now seen corresponding path program 1 times 54.07/20.05 [2019-03-28 12:18:48,258 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.05 [2019-03-28 12:18:48,258 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.05 [2019-03-28 12:18:48,259 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:48,259 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:48,259 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:48,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.05 [2019-03-28 12:18:48,295 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.05 [2019-03-28 12:18:48,296 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.05 [2019-03-28 12:18:48,296 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 54.07/20.05 [2019-03-28 12:18:48,297 INFO L799 eck$LassoCheckResult]: stem already infeasible 54.07/20.05 [2019-03-28 12:18:48,297 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.05 [2019-03-28 12:18:48,297 INFO L82 PathProgramCache]: Analyzing trace with hash -285154061, now seen corresponding path program 2 times 54.07/20.05 [2019-03-28 12:18:48,297 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.05 [2019-03-28 12:18:48,298 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.05 [2019-03-28 12:18:48,299 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:48,299 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:48,299 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:48,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.05 [2019-03-28 12:18:48,332 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.05 [2019-03-28 12:18:48,333 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.05 [2019-03-28 12:18:48,333 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 54.07/20.05 [2019-03-28 12:18:48,333 INFO L811 eck$LassoCheckResult]: loop already infeasible 54.07/20.05 [2019-03-28 12:18:48,334 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 54.07/20.05 [2019-03-28 12:18:48,334 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 54.07/20.05 [2019-03-28 12:18:48,334 INFO L87 Difference]: Start difference. First operand 90 states and 222 transitions. cyclomatic complexity: 133 Second operand 3 states. 54.07/20.05 [2019-03-28 12:18:48,597 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 54.07/20.05 [2019-03-28 12:18:48,598 INFO L93 Difference]: Finished difference Result 90 states and 221 transitions. 54.07/20.05 [2019-03-28 12:18:48,598 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 54.07/20.05 [2019-03-28 12:18:48,599 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 90 states and 221 transitions. 54.07/20.05 [2019-03-28 12:18:48,601 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 56 54.07/20.05 [2019-03-28 12:18:48,603 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 90 states to 90 states and 221 transitions. 54.07/20.05 [2019-03-28 12:18:48,603 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 90 54.07/20.05 [2019-03-28 12:18:48,604 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 90 54.07/20.05 [2019-03-28 12:18:48,604 INFO L73 IsDeterministic]: Start isDeterministic. Operand 90 states and 221 transitions. 54.07/20.05 [2019-03-28 12:18:48,605 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 54.07/20.05 [2019-03-28 12:18:48,605 INFO L706 BuchiCegarLoop]: Abstraction has 90 states and 221 transitions. 54.07/20.05 [2019-03-28 12:18:48,605 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90 states and 221 transitions. 54.07/20.05 [2019-03-28 12:18:48,610 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90 to 90. 54.07/20.05 [2019-03-28 12:18:48,611 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 90 states. 54.07/20.05 [2019-03-28 12:18:48,611 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90 states to 90 states and 221 transitions. 54.07/20.05 [2019-03-28 12:18:48,612 INFO L729 BuchiCegarLoop]: Abstraction has 90 states and 221 transitions. 54.07/20.05 [2019-03-28 12:18:48,612 INFO L609 BuchiCegarLoop]: Abstraction has 90 states and 221 transitions. 54.07/20.05 [2019-03-28 12:18:48,612 INFO L442 BuchiCegarLoop]: ======== Iteration 3============ 54.07/20.05 [2019-03-28 12:18:48,612 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 90 states and 221 transitions. 54.07/20.05 [2019-03-28 12:18:48,613 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 56 54.07/20.05 [2019-03-28 12:18:48,614 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 54.07/20.05 [2019-03-28 12:18:48,614 INFO L119 BuchiIsEmpty]: Starting construction of run 54.07/20.05 [2019-03-28 12:18:48,616 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.05 [2019-03-28 12:18:48,616 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.05 [2019-03-28 12:18:48,617 INFO L794 eck$LassoCheckResult]: Stem: 444#ULTIMATE.startENTRY [885] ULTIMATE.startENTRY-->L202: Formula: (and (= v_~d0_ev~0_23 2) (= 0 v_~z_val~0_13) (= 2 v_~b1_ev~0_23) (= v_~d0_val_t~0_9 1) (= v_~b0_val~0_13 0) (= 1 v_~b1_val_t~0_9) (= 1 v_~d1_req_up~0_12) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_9 0) (= 2 v_~d1_ev~0_23) (= v_~b1_val~0_13 0) (= v_~b0_val_t~0_9 1) (= v_~b0_req_up~0_12 1) (= 0 v_~comp_m1_i~0_7) (= v_~d0_req_up~0_12 1) (= v_~comp_m1_st~0_15 0) (= v_~b0_ev~0_23 2) (= 1 v_~d1_val_t~0_9) (= v_~z_req_up~0_12 0) (= v_~z_val_t~0_10 0) (= 0 v_~d1_val~0_13) (= v_~z_ev~0_19 2) (= v_~b1_req_up~0_12 1) (= 0 v_~d0_val~0_13)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_4|, ~b1_val~0=v_~b1_val~0_13, ~b0_val~0=v_~b0_val~0_13, ~d0_req_up~0=v_~d0_req_up~0_12, ~d0_val~0=v_~d0_val~0_13, ~d1_val_t~0=v_~d1_val_t~0_9, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_9, ~d1_ev~0=v_~d1_ev~0_23, ~d1_val~0=v_~d1_val~0_13, ~b0_req_up~0=v_~b0_req_up~0_12, ~z_ev~0=v_~z_ev~0_19, ~b1_val_t~0=v_~b1_val_t~0_9, ~b1_ev~0=v_~b1_ev~0_23, ULTIMATE.start_main_~__retres1~2=v_ULTIMATE.start_main_~__retres1~2_6, ~z_val~0=v_~z_val~0_13, ~d1_req_up~0=v_~d1_req_up~0_12, ~z_val_t~0=v_~z_val_t~0_10, ~b0_val_t~0=v_~b0_val_t~0_9, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~z_req_up~0=v_~z_req_up~0_12, ~b1_req_up~0=v_~b1_req_up~0_12, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~d0_ev~0=v_~d0_ev~0_23, ~b0_ev~0=v_~b0_ev~0_23, ~d0_val_t~0=v_~d0_val_t~0_9, ~comp_m1_st~0=v_~comp_m1_st~0_15, ~comp_m1_i~0=v_~comp_m1_i~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ~b1_val~0, ~b0_val~0, ~d0_req_up~0, ~d0_val~0, ~d1_val_t~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~d1_ev~0, ~d1_val~0, ~b0_req_up~0, ~z_ev~0, ~b1_val_t~0, ~b1_ev~0, ULTIMATE.start_main_~__retres1~2, ~z_val~0, ~d1_req_up~0, ~z_val_t~0, ~b0_val_t~0, ULTIMATE.start_start_simulation_~tmp~3, ~z_req_up~0, ~b1_req_up~0, ULTIMATE.start_main_#res, ~d0_ev~0, ~b0_ev~0, ~d0_val_t~0, ~comp_m1_st~0, ~comp_m1_i~0] 445#L202 [566] L202-->L127: Formula: (= 1 v_~b0_req_up~0_4) InVars {~b0_req_up~0=v_~b0_req_up~0_4} OutVars{~b0_req_up~0=v_~b0_req_up~0_4} AuxVars[] AssignedVars[] 408#L127 [749] L127-->L127-2: Formula: (and (= v_~b0_val~0_3 v_~b0_val_t~0_3) (= v_~b0_ev~0_3 0) (< v_~b0_val_t~0_3 v_~b0_val~0_4)) InVars {~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_4} OutVars{~b0_ev~0=v_~b0_ev~0_3, ~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_3} AuxVars[] AssignedVars[~b0_val~0, ~b0_ev~0] 409#L127-2 [580] L127-2-->L202-1: Formula: (= v_~b0_req_up~0_5 0) InVars {} OutVars{~b0_req_up~0=v_~b0_req_up~0_5} AuxVars[] AssignedVars[~b0_req_up~0] 440#L202-1 [751] L202-1-->L209: Formula: (> 1 v_~b1_req_up~0_6) InVars {~b1_req_up~0=v_~b1_req_up~0_6} OutVars{~b1_req_up~0=v_~b1_req_up~0_6} AuxVars[] AssignedVars[] 417#L209 [755] L209-->L216: Formula: (< v_~d0_req_up~0_6 1) InVars {~d0_req_up~0=v_~d0_req_up~0_6} OutVars{~d0_req_up~0=v_~d0_req_up~0_6} AuxVars[] AssignedVars[] 387#L216 [759] L216-->L223: Formula: (> v_~d1_req_up~0_6 1) InVars {~d1_req_up~0=v_~d1_req_up~0_6} OutVars{~d1_req_up~0=v_~d1_req_up~0_6} AuxVars[] AssignedVars[] 442#L223 [763] L223-->L230: Formula: (< 1 v_~z_req_up~0_6) InVars {~z_req_up~0=v_~z_req_up~0_6} OutVars{~z_req_up~0=v_~z_req_up~0_6} AuxVars[] AssignedVars[] 388#L230 [767] L230-->L245-1: Formula: (and (> 1 v_~comp_m1_i~0_4) (= v_~comp_m1_st~0_5 2)) InVars {~comp_m1_i~0=v_~comp_m1_i~0_4} OutVars{~comp_m1_st~0=v_~comp_m1_st~0_5, ~comp_m1_i~0=v_~comp_m1_i~0_4} AuxVars[] AssignedVars[~comp_m1_st~0] 389#L245-1 [769] L245-1-->L311-1: Formula: (> v_~b0_ev~0_7 0) InVars {~b0_ev~0=v_~b0_ev~0_7} OutVars{~b0_ev~0=v_~b0_ev~0_7} AuxVars[] AssignedVars[] 405#L311-1 [628] L311-1-->L316-1: Formula: (and (= 0 v_~b1_ev~0_6) (= v_~b1_ev~0_5 1)) InVars {~b1_ev~0=v_~b1_ev~0_6} OutVars{~b1_ev~0=v_~b1_ev~0_5} AuxVars[] AssignedVars[~b1_ev~0] 436#L316-1 [654] L316-1-->L321-1: Formula: (and (= v_~d0_ev~0_5 1) (= v_~d0_ev~0_6 0)) InVars {~d0_ev~0=v_~d0_ev~0_6} OutVars{~d0_ev~0=v_~d0_ev~0_5} AuxVars[] AssignedVars[~d0_ev~0] 398#L321-1 [507] L321-1-->L326-1: Formula: (and (= 0 v_~d1_ev~0_6) (= v_~d1_ev~0_5 1)) InVars {~d1_ev~0=v_~d1_ev~0_6} OutVars{~d1_ev~0=v_~d1_ev~0_5} AuxVars[] AssignedVars[~d1_ev~0] 399#L326-1 [556] L326-1-->L331-1: Formula: (and (= 0 v_~z_ev~0_6) (= v_~z_ev~0_5 1)) InVars {~z_ev~0=v_~z_ev~0_6} OutVars{~z_ev~0=v_~z_ev~0_5} AuxVars[] AssignedVars[~z_ev~0] 451#L331-1 [583] L331-1-->L97: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_1|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 464#L97 [591] L97-->L119: Formula: (and (= v_~b0_ev~0_11 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4 1)) InVars {~b0_ev~0=v_~b0_ev~0_11} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4, ~b0_ev~0=v_~b0_ev~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 423#L119 [886] L119-->L380: Formula: (and (= |v_ULTIMATE.start_is_method1_triggered_#res_7| v_ULTIMATE.start_activate_threads_~tmp~1_13) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19 |v_ULTIMATE.start_is_method1_triggered_#res_7|)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_13, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_7|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_7|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 420#L380 [615] L380-->L380-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_9) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} AuxVars[] AssignedVars[] 421#L380-2 [618] L380-2-->L344-1: Formula: (and (= v_~b0_ev~0_15 2) (= v_~b0_ev~0_16 1)) InVars {~b0_ev~0=v_~b0_ev~0_16} OutVars{~b0_ev~0=v_~b0_ev~0_15} AuxVars[] AssignedVars[~b0_ev~0] 426#L344-1 [791] L344-1-->L349-1: Formula: (> 1 v_~b1_ev~0_17) InVars {~b1_ev~0=v_~b1_ev~0_17} OutVars{~b1_ev~0=v_~b1_ev~0_17} AuxVars[] AssignedVars[] 434#L349-1 [652] L349-1-->L354-1: Formula: (and (= v_~d0_ev~0_15 2) (= v_~d0_ev~0_16 1)) InVars {~d0_ev~0=v_~d0_ev~0_16} OutVars{~d0_ev~0=v_~d0_ev~0_15} AuxVars[] AssignedVars[~d0_ev~0] 393#L354-1 [795] L354-1-->L359-1: Formula: (> 1 v_~d1_ev~0_17) InVars {~d1_ev~0=v_~d1_ev~0_17} OutVars{~d1_ev~0=v_~d1_ev~0_17} AuxVars[] AssignedVars[] 394#L359-1 [797] L359-1-->L422-1: Formula: (> v_~z_ev~0_13 1) InVars {~z_ev~0=v_~z_ev~0_13} OutVars{~z_ev~0=v_~z_ev~0_13} AuxVars[] AssignedVars[] 450#L422-1 54.07/20.05 [2019-03-28 12:18:48,617 INFO L796 eck$LassoCheckResult]: Loop: 450#L422-1 [887] L422-1-->L285: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 1) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 396#L285 [888] L285-->L258: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_13, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res] 397#L258 [802] L258-->L265: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8 0) (> 0 v_~comp_m1_st~0_9)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_9} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8, ~comp_m1_st~0=v_~comp_m1_st~0_9} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 455#L265 [889] L265-->L280: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___0~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 456#L280 [890] L280-->L202-2: Formula: (and (= v_ULTIMATE.start_eval_~tmp___0~0_8 0) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 2)) InVars {ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 437#L202-2 [800] L202-2-->L202-3: Formula: (> 1 v_~b0_req_up~0_9) InVars {~b0_req_up~0=v_~b0_req_up~0_9} OutVars{~b0_req_up~0=v_~b0_req_up~0_9} AuxVars[] AssignedVars[] 435#L202-3 [806] L202-3-->L209-1: Formula: (< 1 v_~b1_req_up~0_9) InVars {~b1_req_up~0=v_~b1_req_up~0_9} OutVars{~b1_req_up~0=v_~b1_req_up~0_9} AuxVars[] AssignedVars[] 428#L209-1 [810] L209-1-->L216-1: Formula: (> v_~d0_req_up~0_9 1) InVars {~d0_req_up~0=v_~d0_req_up~0_9} OutVars{~d0_req_up~0=v_~d0_req_up~0_9} AuxVars[] AssignedVars[] 424#L216-1 [814] L216-1-->L223-1: Formula: (> v_~d1_req_up~0_9 1) InVars {~d1_req_up~0=v_~d1_req_up~0_9} OutVars{~d1_req_up~0=v_~d1_req_up~0_9} AuxVars[] AssignedVars[] 392#L223-1 [820] L223-1-->L230-1: Formula: (< 1 v_~z_req_up~0_9) InVars {~z_req_up~0=v_~z_req_up~0_9} OutVars{~z_req_up~0=v_~z_req_up~0_9} AuxVars[] AssignedVars[] 381#L230-1 [498] L230-1-->L311-2: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 3) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 382#L311-2 [632] L311-2-->L311-4: Formula: (and (= v_~b0_ev~0_8 1) (= v_~b0_ev~0_9 0)) InVars {~b0_ev~0=v_~b0_ev~0_9} OutVars{~b0_ev~0=v_~b0_ev~0_8} AuxVars[] AssignedVars[~b0_ev~0] 410#L311-4 [832] L311-4-->L316-3: Formula: (> 0 v_~b1_ev~0_10) InVars {~b1_ev~0=v_~b1_ev~0_10} OutVars{~b1_ev~0=v_~b1_ev~0_10} AuxVars[] AssignedVars[] 411#L316-3 [838] L316-3-->L321-3: Formula: (< v_~d0_ev~0_10 0) InVars {~d0_ev~0=v_~d0_ev~0_10} OutVars{~d0_ev~0=v_~d0_ev~0_10} AuxVars[] AssignedVars[] 452#L321-3 [662] L321-3-->L326-3: Formula: (and (= v_~d1_ev~0_8 1) (= 0 v_~d1_ev~0_9)) InVars {~d1_ev~0=v_~d1_ev~0_9} OutVars{~d1_ev~0=v_~d1_ev~0_8} AuxVars[] AssignedVars[~d1_ev~0] 429#L326-3 [850] L326-3-->L331-3: Formula: (> v_~z_ev~0_10 0) InVars {~z_ev~0=v_~z_ev~0_10} OutVars{~z_ev~0=v_~z_ev~0_10} AuxVars[] AssignedVars[] 430#L331-3 [570] L331-3-->L97-1: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_4|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_10, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 459#L97-1 [588] L97-1-->L119-1: Formula: (and (= v_~b0_ev~0_13 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13 1)) InVars {~b0_ev~0=v_~b0_ev~0_13} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13, ~b0_ev~0=v_~b0_ev~0_13} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 419#L119-1 [891] L119-1-->L380-3: Formula: (and (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20 |v_ULTIMATE.start_is_method1_triggered_#res_8|) (= |v_ULTIMATE.start_is_method1_triggered_#res_8| v_ULTIMATE.start_activate_threads_~tmp~1_14)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_14, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_8|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_8|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 379#L380-3 [864] L380-3-->L380-5: Formula: (and (= v_~comp_m1_st~0_7 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11, ~comp_m1_st~0=v_~comp_m1_st~0_7} AuxVars[] AssignedVars[~comp_m1_st~0] 380#L380-5 [868] L380-5-->L344-3: Formula: (< v_~b0_ev~0_20 1) InVars {~b0_ev~0=v_~b0_ev~0_20} OutVars{~b0_ev~0=v_~b0_ev~0_20} AuxVars[] AssignedVars[] 390#L344-3 [870] L344-3-->L349-3: Formula: (< 1 v_~b1_ev~0_20) InVars {~b1_ev~0=v_~b1_ev~0_20} OutVars{~b1_ev~0=v_~b1_ev~0_20} AuxVars[] AssignedVars[] 439#L349-3 [656] L349-3-->L354-3: Formula: (and (= v_~d0_ev~0_18 2) (= v_~d0_ev~0_19 1)) InVars {~d0_ev~0=v_~d0_ev~0_19} OutVars{~d0_ev~0=v_~d0_ev~0_18} AuxVars[] AssignedVars[~d0_ev~0] 406#L354-3 [513] L354-3-->L359-3: Formula: (and (= 1 v_~d1_ev~0_19) (= v_~d1_ev~0_18 2)) InVars {~d1_ev~0=v_~d1_ev~0_19} OutVars{~d1_ev~0=v_~d1_ev~0_18} AuxVars[] AssignedVars[~d1_ev~0] 407#L359-3 [531] L359-3-->L364-3: Formula: (and (= v_~z_ev~0_15 1) (= v_~z_ev~0_14 2)) InVars {~z_ev~0=v_~z_ev~0_15} OutVars{~z_ev~0=v_~z_ev~0_14} AuxVars[] AssignedVars[~z_ev~0] 427#L364-3 [568] L364-3-->L258-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_5, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_2|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_#res] 458#L258-1 [666] L258-1-->L265-1: Formula: (and (= v_~comp_m1_st~0_10 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9 1)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_10} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9, ~comp_m1_st~0=v_~comp_m1_st~0_10} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 453#L265-1 [892] L265-1-->L397: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_stop_simulation_~tmp~2_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_4|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_~tmp~2] 454#L397 [880] L397-->L404: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_4 0) (< 0 v_ULTIMATE.start_stop_simulation_~tmp~2_5)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_4, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 457#L404 [897] L404-->L422-1: Formula: (and (= 0 v_ULTIMATE.start_start_simulation_~tmp~3_9) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= |v_ULTIMATE.start_stop_simulation_#res_5| v_ULTIMATE.start_start_simulation_~tmp~3_9)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_~tmp~3] 450#L422-1 54.07/20.05 [2019-03-28 12:18:48,618 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.05 [2019-03-28 12:18:48,618 INFO L82 PathProgramCache]: Analyzing trace with hash -1048555014, now seen corresponding path program 1 times 54.07/20.05 [2019-03-28 12:18:48,618 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.05 [2019-03-28 12:18:48,618 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.05 [2019-03-28 12:18:48,619 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:48,619 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:48,619 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:48,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.05 [2019-03-28 12:18:48,643 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.05 [2019-03-28 12:18:48,643 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.05 [2019-03-28 12:18:48,643 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 54.07/20.05 [2019-03-28 12:18:48,643 INFO L799 eck$LassoCheckResult]: stem already infeasible 54.07/20.05 [2019-03-28 12:18:48,644 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.05 [2019-03-28 12:18:48,644 INFO L82 PathProgramCache]: Analyzing trace with hash -285154061, now seen corresponding path program 3 times 54.07/20.05 [2019-03-28 12:18:48,644 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.05 [2019-03-28 12:18:48,644 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.05 [2019-03-28 12:18:48,645 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:48,645 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:48,645 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:48,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.05 [2019-03-28 12:18:48,674 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.05 [2019-03-28 12:18:48,675 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.05 [2019-03-28 12:18:48,675 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 54.07/20.05 [2019-03-28 12:18:48,675 INFO L811 eck$LassoCheckResult]: loop already infeasible 54.07/20.05 [2019-03-28 12:18:48,675 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 54.07/20.05 [2019-03-28 12:18:48,676 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 54.07/20.05 [2019-03-28 12:18:48,676 INFO L87 Difference]: Start difference. First operand 90 states and 221 transitions. cyclomatic complexity: 132 Second operand 3 states. 54.07/20.05 [2019-03-28 12:18:48,898 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 54.07/20.05 [2019-03-28 12:18:48,898 INFO L93 Difference]: Finished difference Result 90 states and 219 transitions. 54.07/20.05 [2019-03-28 12:18:48,898 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 54.07/20.05 [2019-03-28 12:18:48,899 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 90 states and 219 transitions. 54.07/20.05 [2019-03-28 12:18:48,901 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 56 54.07/20.05 [2019-03-28 12:18:48,902 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 90 states to 90 states and 219 transitions. 54.07/20.05 [2019-03-28 12:18:48,902 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 90 54.07/20.05 [2019-03-28 12:18:48,903 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 90 54.07/20.05 [2019-03-28 12:18:48,903 INFO L73 IsDeterministic]: Start isDeterministic. Operand 90 states and 219 transitions. 54.07/20.05 [2019-03-28 12:18:48,904 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 54.07/20.05 [2019-03-28 12:18:48,904 INFO L706 BuchiCegarLoop]: Abstraction has 90 states and 219 transitions. 54.07/20.05 [2019-03-28 12:18:48,904 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90 states and 219 transitions. 54.07/20.05 [2019-03-28 12:18:48,909 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90 to 90. 54.07/20.05 [2019-03-28 12:18:48,909 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 90 states. 54.07/20.05 [2019-03-28 12:18:48,910 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90 states to 90 states and 219 transitions. 54.07/20.05 [2019-03-28 12:18:48,910 INFO L729 BuchiCegarLoop]: Abstraction has 90 states and 219 transitions. 54.07/20.05 [2019-03-28 12:18:48,910 INFO L609 BuchiCegarLoop]: Abstraction has 90 states and 219 transitions. 54.07/20.05 [2019-03-28 12:18:48,910 INFO L442 BuchiCegarLoop]: ======== Iteration 4============ 54.07/20.05 [2019-03-28 12:18:48,910 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 90 states and 219 transitions. 54.07/20.05 [2019-03-28 12:18:48,913 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 56 54.07/20.05 [2019-03-28 12:18:48,914 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 54.07/20.05 [2019-03-28 12:18:48,914 INFO L119 BuchiIsEmpty]: Starting construction of run 54.07/20.05 [2019-03-28 12:18:48,915 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.05 [2019-03-28 12:18:48,915 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.05 [2019-03-28 12:18:48,916 INFO L794 eck$LassoCheckResult]: Stem: 631#ULTIMATE.startENTRY [885] ULTIMATE.startENTRY-->L202: Formula: (and (= v_~d0_ev~0_23 2) (= 0 v_~z_val~0_13) (= 2 v_~b1_ev~0_23) (= v_~d0_val_t~0_9 1) (= v_~b0_val~0_13 0) (= 1 v_~b1_val_t~0_9) (= 1 v_~d1_req_up~0_12) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_9 0) (= 2 v_~d1_ev~0_23) (= v_~b1_val~0_13 0) (= v_~b0_val_t~0_9 1) (= v_~b0_req_up~0_12 1) (= 0 v_~comp_m1_i~0_7) (= v_~d0_req_up~0_12 1) (= v_~comp_m1_st~0_15 0) (= v_~b0_ev~0_23 2) (= 1 v_~d1_val_t~0_9) (= v_~z_req_up~0_12 0) (= v_~z_val_t~0_10 0) (= 0 v_~d1_val~0_13) (= v_~z_ev~0_19 2) (= v_~b1_req_up~0_12 1) (= 0 v_~d0_val~0_13)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_4|, ~b1_val~0=v_~b1_val~0_13, ~b0_val~0=v_~b0_val~0_13, ~d0_req_up~0=v_~d0_req_up~0_12, ~d0_val~0=v_~d0_val~0_13, ~d1_val_t~0=v_~d1_val_t~0_9, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_9, ~d1_ev~0=v_~d1_ev~0_23, ~d1_val~0=v_~d1_val~0_13, ~b0_req_up~0=v_~b0_req_up~0_12, ~z_ev~0=v_~z_ev~0_19, ~b1_val_t~0=v_~b1_val_t~0_9, ~b1_ev~0=v_~b1_ev~0_23, ULTIMATE.start_main_~__retres1~2=v_ULTIMATE.start_main_~__retres1~2_6, ~z_val~0=v_~z_val~0_13, ~d1_req_up~0=v_~d1_req_up~0_12, ~z_val_t~0=v_~z_val_t~0_10, ~b0_val_t~0=v_~b0_val_t~0_9, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~z_req_up~0=v_~z_req_up~0_12, ~b1_req_up~0=v_~b1_req_up~0_12, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~d0_ev~0=v_~d0_ev~0_23, ~b0_ev~0=v_~b0_ev~0_23, ~d0_val_t~0=v_~d0_val_t~0_9, ~comp_m1_st~0=v_~comp_m1_st~0_15, ~comp_m1_i~0=v_~comp_m1_i~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ~b1_val~0, ~b0_val~0, ~d0_req_up~0, ~d0_val~0, ~d1_val_t~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~d1_ev~0, ~d1_val~0, ~b0_req_up~0, ~z_ev~0, ~b1_val_t~0, ~b1_ev~0, ULTIMATE.start_main_~__retres1~2, ~z_val~0, ~d1_req_up~0, ~z_val_t~0, ~b0_val_t~0, ULTIMATE.start_start_simulation_~tmp~3, ~z_req_up~0, ~b1_req_up~0, ULTIMATE.start_main_#res, ~d0_ev~0, ~b0_ev~0, ~d0_val_t~0, ~comp_m1_st~0, ~comp_m1_i~0] 632#L202 [566] L202-->L127: Formula: (= 1 v_~b0_req_up~0_4) InVars {~b0_req_up~0=v_~b0_req_up~0_4} OutVars{~b0_req_up~0=v_~b0_req_up~0_4} AuxVars[] AssignedVars[] 595#L127 [748] L127-->L127-2: Formula: (and (= v_~b0_val~0_3 v_~b0_val_t~0_3) (> v_~b0_val_t~0_3 v_~b0_val~0_4) (= v_~b0_ev~0_3 0)) InVars {~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_4} OutVars{~b0_ev~0=v_~b0_ev~0_3, ~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_3} AuxVars[] AssignedVars[~b0_val~0, ~b0_ev~0] 596#L127-2 [580] L127-2-->L202-1: Formula: (= v_~b0_req_up~0_5 0) InVars {} OutVars{~b0_req_up~0=v_~b0_req_up~0_5} AuxVars[] AssignedVars[~b0_req_up~0] 627#L202-1 [751] L202-1-->L209: Formula: (> 1 v_~b1_req_up~0_6) InVars {~b1_req_up~0=v_~b1_req_up~0_6} OutVars{~b1_req_up~0=v_~b1_req_up~0_6} AuxVars[] AssignedVars[] 606#L209 [755] L209-->L216: Formula: (< v_~d0_req_up~0_6 1) InVars {~d0_req_up~0=v_~d0_req_up~0_6} OutVars{~d0_req_up~0=v_~d0_req_up~0_6} AuxVars[] AssignedVars[] 574#L216 [759] L216-->L223: Formula: (> v_~d1_req_up~0_6 1) InVars {~d1_req_up~0=v_~d1_req_up~0_6} OutVars{~d1_req_up~0=v_~d1_req_up~0_6} AuxVars[] AssignedVars[] 629#L223 [763] L223-->L230: Formula: (< 1 v_~z_req_up~0_6) InVars {~z_req_up~0=v_~z_req_up~0_6} OutVars{~z_req_up~0=v_~z_req_up~0_6} AuxVars[] AssignedVars[] 575#L230 [767] L230-->L245-1: Formula: (and (> 1 v_~comp_m1_i~0_4) (= v_~comp_m1_st~0_5 2)) InVars {~comp_m1_i~0=v_~comp_m1_i~0_4} OutVars{~comp_m1_st~0=v_~comp_m1_st~0_5, ~comp_m1_i~0=v_~comp_m1_i~0_4} AuxVars[] AssignedVars[~comp_m1_st~0] 576#L245-1 [769] L245-1-->L311-1: Formula: (> v_~b0_ev~0_7 0) InVars {~b0_ev~0=v_~b0_ev~0_7} OutVars{~b0_ev~0=v_~b0_ev~0_7} AuxVars[] AssignedVars[] 594#L311-1 [628] L311-1-->L316-1: Formula: (and (= 0 v_~b1_ev~0_6) (= v_~b1_ev~0_5 1)) InVars {~b1_ev~0=v_~b1_ev~0_6} OutVars{~b1_ev~0=v_~b1_ev~0_5} AuxVars[] AssignedVars[~b1_ev~0] 623#L316-1 [654] L316-1-->L321-1: Formula: (and (= v_~d0_ev~0_5 1) (= v_~d0_ev~0_6 0)) InVars {~d0_ev~0=v_~d0_ev~0_6} OutVars{~d0_ev~0=v_~d0_ev~0_5} AuxVars[] AssignedVars[~d0_ev~0] 588#L321-1 [507] L321-1-->L326-1: Formula: (and (= 0 v_~d1_ev~0_6) (= v_~d1_ev~0_5 1)) InVars {~d1_ev~0=v_~d1_ev~0_6} OutVars{~d1_ev~0=v_~d1_ev~0_5} AuxVars[] AssignedVars[~d1_ev~0] 589#L326-1 [556] L326-1-->L331-1: Formula: (and (= 0 v_~z_ev~0_6) (= v_~z_ev~0_5 1)) InVars {~z_ev~0=v_~z_ev~0_6} OutVars{~z_ev~0=v_~z_ev~0_5} AuxVars[] AssignedVars[~z_ev~0] 638#L331-1 [583] L331-1-->L97: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_1|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 651#L97 [591] L97-->L119: Formula: (and (= v_~b0_ev~0_11 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4 1)) InVars {~b0_ev~0=v_~b0_ev~0_11} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4, ~b0_ev~0=v_~b0_ev~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 610#L119 [886] L119-->L380: Formula: (and (= |v_ULTIMATE.start_is_method1_triggered_#res_7| v_ULTIMATE.start_activate_threads_~tmp~1_13) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19 |v_ULTIMATE.start_is_method1_triggered_#res_7|)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_13, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_7|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_7|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 607#L380 [615] L380-->L380-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_9) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} AuxVars[] AssignedVars[] 608#L380-2 [618] L380-2-->L344-1: Formula: (and (= v_~b0_ev~0_15 2) (= v_~b0_ev~0_16 1)) InVars {~b0_ev~0=v_~b0_ev~0_16} OutVars{~b0_ev~0=v_~b0_ev~0_15} AuxVars[] AssignedVars[~b0_ev~0] 613#L344-1 [791] L344-1-->L349-1: Formula: (> 1 v_~b1_ev~0_17) InVars {~b1_ev~0=v_~b1_ev~0_17} OutVars{~b1_ev~0=v_~b1_ev~0_17} AuxVars[] AssignedVars[] 621#L349-1 [652] L349-1-->L354-1: Formula: (and (= v_~d0_ev~0_15 2) (= v_~d0_ev~0_16 1)) InVars {~d0_ev~0=v_~d0_ev~0_16} OutVars{~d0_ev~0=v_~d0_ev~0_15} AuxVars[] AssignedVars[~d0_ev~0] 580#L354-1 [795] L354-1-->L359-1: Formula: (> 1 v_~d1_ev~0_17) InVars {~d1_ev~0=v_~d1_ev~0_17} OutVars{~d1_ev~0=v_~d1_ev~0_17} AuxVars[] AssignedVars[] 581#L359-1 [797] L359-1-->L422-1: Formula: (> v_~z_ev~0_13 1) InVars {~z_ev~0=v_~z_ev~0_13} OutVars{~z_ev~0=v_~z_ev~0_13} AuxVars[] AssignedVars[] 637#L422-1 54.07/20.05 [2019-03-28 12:18:48,917 INFO L796 eck$LassoCheckResult]: Loop: 637#L422-1 [887] L422-1-->L285: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 1) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 583#L285 [888] L285-->L258: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_13, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res] 584#L258 [802] L258-->L265: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8 0) (> 0 v_~comp_m1_st~0_9)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_9} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8, ~comp_m1_st~0=v_~comp_m1_st~0_9} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 642#L265 [889] L265-->L280: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___0~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 643#L280 [890] L280-->L202-2: Formula: (and (= v_ULTIMATE.start_eval_~tmp___0~0_8 0) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 2)) InVars {ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 624#L202-2 [800] L202-2-->L202-3: Formula: (> 1 v_~b0_req_up~0_9) InVars {~b0_req_up~0=v_~b0_req_up~0_9} OutVars{~b0_req_up~0=v_~b0_req_up~0_9} AuxVars[] AssignedVars[] 622#L202-3 [806] L202-3-->L209-1: Formula: (< 1 v_~b1_req_up~0_9) InVars {~b1_req_up~0=v_~b1_req_up~0_9} OutVars{~b1_req_up~0=v_~b1_req_up~0_9} AuxVars[] AssignedVars[] 615#L209-1 [810] L209-1-->L216-1: Formula: (> v_~d0_req_up~0_9 1) InVars {~d0_req_up~0=v_~d0_req_up~0_9} OutVars{~d0_req_up~0=v_~d0_req_up~0_9} AuxVars[] AssignedVars[] 611#L216-1 [814] L216-1-->L223-1: Formula: (> v_~d1_req_up~0_9 1) InVars {~d1_req_up~0=v_~d1_req_up~0_9} OutVars{~d1_req_up~0=v_~d1_req_up~0_9} AuxVars[] AssignedVars[] 579#L223-1 [820] L223-1-->L230-1: Formula: (< 1 v_~z_req_up~0_9) InVars {~z_req_up~0=v_~z_req_up~0_9} OutVars{~z_req_up~0=v_~z_req_up~0_9} AuxVars[] AssignedVars[] 568#L230-1 [498] L230-1-->L311-2: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 3) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 569#L311-2 [632] L311-2-->L311-4: Formula: (and (= v_~b0_ev~0_8 1) (= v_~b0_ev~0_9 0)) InVars {~b0_ev~0=v_~b0_ev~0_9} OutVars{~b0_ev~0=v_~b0_ev~0_8} AuxVars[] AssignedVars[~b0_ev~0] 597#L311-4 [832] L311-4-->L316-3: Formula: (> 0 v_~b1_ev~0_10) InVars {~b1_ev~0=v_~b1_ev~0_10} OutVars{~b1_ev~0=v_~b1_ev~0_10} AuxVars[] AssignedVars[] 598#L316-3 [838] L316-3-->L321-3: Formula: (< v_~d0_ev~0_10 0) InVars {~d0_ev~0=v_~d0_ev~0_10} OutVars{~d0_ev~0=v_~d0_ev~0_10} AuxVars[] AssignedVars[] 639#L321-3 [662] L321-3-->L326-3: Formula: (and (= v_~d1_ev~0_8 1) (= 0 v_~d1_ev~0_9)) InVars {~d1_ev~0=v_~d1_ev~0_9} OutVars{~d1_ev~0=v_~d1_ev~0_8} AuxVars[] AssignedVars[~d1_ev~0] 616#L326-3 [850] L326-3-->L331-3: Formula: (> v_~z_ev~0_10 0) InVars {~z_ev~0=v_~z_ev~0_10} OutVars{~z_ev~0=v_~z_ev~0_10} AuxVars[] AssignedVars[] 617#L331-3 [570] L331-3-->L97-1: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_4|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_10, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 646#L97-1 [588] L97-1-->L119-1: Formula: (and (= v_~b0_ev~0_13 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13 1)) InVars {~b0_ev~0=v_~b0_ev~0_13} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13, ~b0_ev~0=v_~b0_ev~0_13} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 604#L119-1 [891] L119-1-->L380-3: Formula: (and (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20 |v_ULTIMATE.start_is_method1_triggered_#res_8|) (= |v_ULTIMATE.start_is_method1_triggered_#res_8| v_ULTIMATE.start_activate_threads_~tmp~1_14)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_14, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_8|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_8|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 566#L380-3 [864] L380-3-->L380-5: Formula: (and (= v_~comp_m1_st~0_7 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11, ~comp_m1_st~0=v_~comp_m1_st~0_7} AuxVars[] AssignedVars[~comp_m1_st~0] 567#L380-5 [868] L380-5-->L344-3: Formula: (< v_~b0_ev~0_20 1) InVars {~b0_ev~0=v_~b0_ev~0_20} OutVars{~b0_ev~0=v_~b0_ev~0_20} AuxVars[] AssignedVars[] 577#L344-3 [870] L344-3-->L349-3: Formula: (< 1 v_~b1_ev~0_20) InVars {~b1_ev~0=v_~b1_ev~0_20} OutVars{~b1_ev~0=v_~b1_ev~0_20} AuxVars[] AssignedVars[] 626#L349-3 [656] L349-3-->L354-3: Formula: (and (= v_~d0_ev~0_18 2) (= v_~d0_ev~0_19 1)) InVars {~d0_ev~0=v_~d0_ev~0_19} OutVars{~d0_ev~0=v_~d0_ev~0_18} AuxVars[] AssignedVars[~d0_ev~0] 592#L354-3 [513] L354-3-->L359-3: Formula: (and (= 1 v_~d1_ev~0_19) (= v_~d1_ev~0_18 2)) InVars {~d1_ev~0=v_~d1_ev~0_19} OutVars{~d1_ev~0=v_~d1_ev~0_18} AuxVars[] AssignedVars[~d1_ev~0] 593#L359-3 [531] L359-3-->L364-3: Formula: (and (= v_~z_ev~0_15 1) (= v_~z_ev~0_14 2)) InVars {~z_ev~0=v_~z_ev~0_15} OutVars{~z_ev~0=v_~z_ev~0_14} AuxVars[] AssignedVars[~z_ev~0] 614#L364-3 [568] L364-3-->L258-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_5, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_2|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_#res] 645#L258-1 [666] L258-1-->L265-1: Formula: (and (= v_~comp_m1_st~0_10 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9 1)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_10} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9, ~comp_m1_st~0=v_~comp_m1_st~0_10} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 640#L265-1 [892] L265-1-->L397: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_stop_simulation_~tmp~2_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_4|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_~tmp~2] 641#L397 [880] L397-->L404: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_4 0) (< 0 v_ULTIMATE.start_stop_simulation_~tmp~2_5)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_4, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 644#L404 [897] L404-->L422-1: Formula: (and (= 0 v_ULTIMATE.start_start_simulation_~tmp~3_9) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= |v_ULTIMATE.start_stop_simulation_#res_5| v_ULTIMATE.start_start_simulation_~tmp~3_9)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_~tmp~3] 637#L422-1 54.07/20.05 [2019-03-28 12:18:48,917 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.05 [2019-03-28 12:18:48,917 INFO L82 PathProgramCache]: Analyzing trace with hash -1259905927, now seen corresponding path program 1 times 54.07/20.05 [2019-03-28 12:18:48,917 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.05 [2019-03-28 12:18:48,917 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.05 [2019-03-28 12:18:48,918 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:48,919 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:48,919 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:48,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.05 [2019-03-28 12:18:48,939 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.05 [2019-03-28 12:18:48,939 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.05 [2019-03-28 12:18:48,939 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 54.07/20.05 [2019-03-28 12:18:48,939 INFO L799 eck$LassoCheckResult]: stem already infeasible 54.07/20.05 [2019-03-28 12:18:48,940 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.05 [2019-03-28 12:18:48,940 INFO L82 PathProgramCache]: Analyzing trace with hash -285154061, now seen corresponding path program 4 times 54.07/20.05 [2019-03-28 12:18:48,940 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.05 [2019-03-28 12:18:48,940 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.05 [2019-03-28 12:18:48,941 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:48,941 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:48,941 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:48,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.05 [2019-03-28 12:18:48,978 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.05 [2019-03-28 12:18:48,979 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.05 [2019-03-28 12:18:48,979 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 54.07/20.05 [2019-03-28 12:18:48,979 INFO L811 eck$LassoCheckResult]: loop already infeasible 54.07/20.05 [2019-03-28 12:18:48,980 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 54.07/20.05 [2019-03-28 12:18:48,980 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 54.07/20.05 [2019-03-28 12:18:48,980 INFO L87 Difference]: Start difference. First operand 90 states and 219 transitions. cyclomatic complexity: 130 Second operand 3 states. 54.07/20.05 [2019-03-28 12:18:49,229 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 54.07/20.05 [2019-03-28 12:18:49,230 INFO L93 Difference]: Finished difference Result 171 states and 421 transitions. 54.07/20.05 [2019-03-28 12:18:49,230 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 54.07/20.05 [2019-03-28 12:18:49,230 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 171 states and 421 transitions. 54.07/20.05 [2019-03-28 12:18:49,232 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 110 54.07/20.05 [2019-03-28 12:18:49,235 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 171 states to 171 states and 421 transitions. 54.07/20.05 [2019-03-28 12:18:49,235 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 171 54.07/20.05 [2019-03-28 12:18:49,235 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 171 54.07/20.05 [2019-03-28 12:18:49,235 INFO L73 IsDeterministic]: Start isDeterministic. Operand 171 states and 421 transitions. 54.07/20.05 [2019-03-28 12:18:49,237 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 54.07/20.05 [2019-03-28 12:18:49,237 INFO L706 BuchiCegarLoop]: Abstraction has 171 states and 421 transitions. 54.07/20.05 [2019-03-28 12:18:49,237 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 171 states and 421 transitions. 54.07/20.05 [2019-03-28 12:18:49,246 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 171 to 171. 54.07/20.05 [2019-03-28 12:18:49,246 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 171 states. 54.07/20.05 [2019-03-28 12:18:49,247 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 171 states to 171 states and 421 transitions. 54.07/20.05 [2019-03-28 12:18:49,248 INFO L729 BuchiCegarLoop]: Abstraction has 171 states and 421 transitions. 54.07/20.05 [2019-03-28 12:18:49,248 INFO L609 BuchiCegarLoop]: Abstraction has 171 states and 421 transitions. 54.07/20.05 [2019-03-28 12:18:49,248 INFO L442 BuchiCegarLoop]: ======== Iteration 5============ 54.07/20.05 [2019-03-28 12:18:49,248 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 171 states and 421 transitions. 54.07/20.05 [2019-03-28 12:18:49,250 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 110 54.07/20.05 [2019-03-28 12:18:49,250 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 54.07/20.05 [2019-03-28 12:18:49,250 INFO L119 BuchiIsEmpty]: Starting construction of run 54.07/20.05 [2019-03-28 12:18:49,251 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.05 [2019-03-28 12:18:49,251 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.05 [2019-03-28 12:18:49,252 INFO L794 eck$LassoCheckResult]: Stem: 902#ULTIMATE.startENTRY [885] ULTIMATE.startENTRY-->L202: Formula: (and (= v_~d0_ev~0_23 2) (= 0 v_~z_val~0_13) (= 2 v_~b1_ev~0_23) (= v_~d0_val_t~0_9 1) (= v_~b0_val~0_13 0) (= 1 v_~b1_val_t~0_9) (= 1 v_~d1_req_up~0_12) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_9 0) (= 2 v_~d1_ev~0_23) (= v_~b1_val~0_13 0) (= v_~b0_val_t~0_9 1) (= v_~b0_req_up~0_12 1) (= 0 v_~comp_m1_i~0_7) (= v_~d0_req_up~0_12 1) (= v_~comp_m1_st~0_15 0) (= v_~b0_ev~0_23 2) (= 1 v_~d1_val_t~0_9) (= v_~z_req_up~0_12 0) (= v_~z_val_t~0_10 0) (= 0 v_~d1_val~0_13) (= v_~z_ev~0_19 2) (= v_~b1_req_up~0_12 1) (= 0 v_~d0_val~0_13)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_4|, ~b1_val~0=v_~b1_val~0_13, ~b0_val~0=v_~b0_val~0_13, ~d0_req_up~0=v_~d0_req_up~0_12, ~d0_val~0=v_~d0_val~0_13, ~d1_val_t~0=v_~d1_val_t~0_9, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_9, ~d1_ev~0=v_~d1_ev~0_23, ~d1_val~0=v_~d1_val~0_13, ~b0_req_up~0=v_~b0_req_up~0_12, ~z_ev~0=v_~z_ev~0_19, ~b1_val_t~0=v_~b1_val_t~0_9, ~b1_ev~0=v_~b1_ev~0_23, ULTIMATE.start_main_~__retres1~2=v_ULTIMATE.start_main_~__retres1~2_6, ~z_val~0=v_~z_val~0_13, ~d1_req_up~0=v_~d1_req_up~0_12, ~z_val_t~0=v_~z_val_t~0_10, ~b0_val_t~0=v_~b0_val_t~0_9, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~z_req_up~0=v_~z_req_up~0_12, ~b1_req_up~0=v_~b1_req_up~0_12, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~d0_ev~0=v_~d0_ev~0_23, ~b0_ev~0=v_~b0_ev~0_23, ~d0_val_t~0=v_~d0_val_t~0_9, ~comp_m1_st~0=v_~comp_m1_st~0_15, ~comp_m1_i~0=v_~comp_m1_i~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ~b1_val~0, ~b0_val~0, ~d0_req_up~0, ~d0_val~0, ~d1_val_t~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~d1_ev~0, ~d1_val~0, ~b0_req_up~0, ~z_ev~0, ~b1_val_t~0, ~b1_ev~0, ULTIMATE.start_main_~__retres1~2, ~z_val~0, ~d1_req_up~0, ~z_val_t~0, ~b0_val_t~0, ULTIMATE.start_start_simulation_~tmp~3, ~z_req_up~0, ~b1_req_up~0, ULTIMATE.start_main_#res, ~d0_ev~0, ~b0_ev~0, ~d0_val_t~0, ~comp_m1_st~0, ~comp_m1_i~0] 903#L202 [566] L202-->L127: Formula: (= 1 v_~b0_req_up~0_4) InVars {~b0_req_up~0=v_~b0_req_up~0_4} OutVars{~b0_req_up~0=v_~b0_req_up~0_4} AuxVars[] AssignedVars[] 863#L127 [748] L127-->L127-2: Formula: (and (= v_~b0_val~0_3 v_~b0_val_t~0_3) (> v_~b0_val_t~0_3 v_~b0_val~0_4) (= v_~b0_ev~0_3 0)) InVars {~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_4} OutVars{~b0_ev~0=v_~b0_ev~0_3, ~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_3} AuxVars[] AssignedVars[~b0_val~0, ~b0_ev~0] 864#L127-2 [580] L127-2-->L202-1: Formula: (= v_~b0_req_up~0_5 0) InVars {} OutVars{~b0_req_up~0=v_~b0_req_up~0_5} AuxVars[] AssignedVars[~b0_req_up~0] 898#L202-1 [750] L202-1-->L209: Formula: (< 1 v_~b1_req_up~0_6) InVars {~b1_req_up~0=v_~b1_req_up~0_6} OutVars{~b1_req_up~0=v_~b1_req_up~0_6} AuxVars[] AssignedVars[] 889#L209 [755] L209-->L216: Formula: (< v_~d0_req_up~0_6 1) InVars {~d0_req_up~0=v_~d0_req_up~0_6} OutVars{~d0_req_up~0=v_~d0_req_up~0_6} AuxVars[] AssignedVars[] 842#L216 [759] L216-->L223: Formula: (> v_~d1_req_up~0_6 1) InVars {~d1_req_up~0=v_~d1_req_up~0_6} OutVars{~d1_req_up~0=v_~d1_req_up~0_6} AuxVars[] AssignedVars[] 900#L223 [763] L223-->L230: Formula: (< 1 v_~z_req_up~0_6) InVars {~z_req_up~0=v_~z_req_up~0_6} OutVars{~z_req_up~0=v_~z_req_up~0_6} AuxVars[] AssignedVars[] 843#L230 [767] L230-->L245-1: Formula: (and (> 1 v_~comp_m1_i~0_4) (= v_~comp_m1_st~0_5 2)) InVars {~comp_m1_i~0=v_~comp_m1_i~0_4} OutVars{~comp_m1_st~0=v_~comp_m1_st~0_5, ~comp_m1_i~0=v_~comp_m1_i~0_4} AuxVars[] AssignedVars[~comp_m1_st~0] 844#L245-1 [769] L245-1-->L311-1: Formula: (> v_~b0_ev~0_7 0) InVars {~b0_ev~0=v_~b0_ev~0_7} OutVars{~b0_ev~0=v_~b0_ev~0_7} AuxVars[] AssignedVars[] 862#L311-1 [628] L311-1-->L316-1: Formula: (and (= 0 v_~b1_ev~0_6) (= v_~b1_ev~0_5 1)) InVars {~b1_ev~0=v_~b1_ev~0_6} OutVars{~b1_ev~0=v_~b1_ev~0_5} AuxVars[] AssignedVars[~b1_ev~0] 894#L316-1 [654] L316-1-->L321-1: Formula: (and (= v_~d0_ev~0_5 1) (= v_~d0_ev~0_6 0)) InVars {~d0_ev~0=v_~d0_ev~0_6} OutVars{~d0_ev~0=v_~d0_ev~0_5} AuxVars[] AssignedVars[~d0_ev~0] 856#L321-1 [507] L321-1-->L326-1: Formula: (and (= 0 v_~d1_ev~0_6) (= v_~d1_ev~0_5 1)) InVars {~d1_ev~0=v_~d1_ev~0_6} OutVars{~d1_ev~0=v_~d1_ev~0_5} AuxVars[] AssignedVars[~d1_ev~0] 857#L326-1 [556] L326-1-->L331-1: Formula: (and (= 0 v_~z_ev~0_6) (= v_~z_ev~0_5 1)) InVars {~z_ev~0=v_~z_ev~0_6} OutVars{~z_ev~0=v_~z_ev~0_5} AuxVars[] AssignedVars[~z_ev~0] 909#L331-1 [583] L331-1-->L97: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_1|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 926#L97 [591] L97-->L119: Formula: (and (= v_~b0_ev~0_11 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4 1)) InVars {~b0_ev~0=v_~b0_ev~0_11} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4, ~b0_ev~0=v_~b0_ev~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 878#L119 [886] L119-->L380: Formula: (and (= |v_ULTIMATE.start_is_method1_triggered_#res_7| v_ULTIMATE.start_activate_threads_~tmp~1_13) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19 |v_ULTIMATE.start_is_method1_triggered_#res_7|)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_13, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_7|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_7|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 875#L380 [615] L380-->L380-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_9) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} AuxVars[] AssignedVars[] 876#L380-2 [618] L380-2-->L344-1: Formula: (and (= v_~b0_ev~0_15 2) (= v_~b0_ev~0_16 1)) InVars {~b0_ev~0=v_~b0_ev~0_16} OutVars{~b0_ev~0=v_~b0_ev~0_15} AuxVars[] AssignedVars[~b0_ev~0] 881#L344-1 [791] L344-1-->L349-1: Formula: (> 1 v_~b1_ev~0_17) InVars {~b1_ev~0=v_~b1_ev~0_17} OutVars{~b1_ev~0=v_~b1_ev~0_17} AuxVars[] AssignedVars[] 948#L349-1 [652] L349-1-->L354-1: Formula: (and (= v_~d0_ev~0_15 2) (= v_~d0_ev~0_16 1)) InVars {~d0_ev~0=v_~d0_ev~0_16} OutVars{~d0_ev~0=v_~d0_ev~0_15} AuxVars[] AssignedVars[~d0_ev~0] 947#L354-1 [795] L354-1-->L359-1: Formula: (> 1 v_~d1_ev~0_17) InVars {~d1_ev~0=v_~d1_ev~0_17} OutVars{~d1_ev~0=v_~d1_ev~0_17} AuxVars[] AssignedVars[] 943#L359-1 [797] L359-1-->L422-1: Formula: (> v_~z_ev~0_13 1) InVars {~z_ev~0=v_~z_ev~0_13} OutVars{~z_ev~0=v_~z_ev~0_13} AuxVars[] AssignedVars[] 918#L422-1 54.07/20.05 [2019-03-28 12:18:49,253 INFO L796 eck$LassoCheckResult]: Loop: 918#L422-1 [887] L422-1-->L285: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 1) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 851#L285 [888] L285-->L258: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_13, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res] 852#L258 [802] L258-->L265: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8 0) (> 0 v_~comp_m1_st~0_9)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_9} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8, ~comp_m1_st~0=v_~comp_m1_st~0_9} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 913#L265 [889] L265-->L280: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___0~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 914#L280 [890] L280-->L202-2: Formula: (and (= v_ULTIMATE.start_eval_~tmp___0~0_8 0) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 2)) InVars {ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 895#L202-2 [800] L202-2-->L202-3: Formula: (> 1 v_~b0_req_up~0_9) InVars {~b0_req_up~0=v_~b0_req_up~0_9} OutVars{~b0_req_up~0=v_~b0_req_up~0_9} AuxVars[] AssignedVars[] 892#L202-3 [806] L202-3-->L209-1: Formula: (< 1 v_~b1_req_up~0_9) InVars {~b1_req_up~0=v_~b1_req_up~0_9} OutVars{~b1_req_up~0=v_~b1_req_up~0_9} AuxVars[] AssignedVars[] 885#L209-1 [810] L209-1-->L216-1: Formula: (> v_~d0_req_up~0_9 1) InVars {~d0_req_up~0=v_~d0_req_up~0_9} OutVars{~d0_req_up~0=v_~d0_req_up~0_9} AuxVars[] AssignedVars[] 879#L216-1 [814] L216-1-->L223-1: Formula: (> v_~d1_req_up~0_9 1) InVars {~d1_req_up~0=v_~d1_req_up~0_9} OutVars{~d1_req_up~0=v_~d1_req_up~0_9} AuxVars[] AssignedVars[] 847#L223-1 [820] L223-1-->L230-1: Formula: (< 1 v_~z_req_up~0_9) InVars {~z_req_up~0=v_~z_req_up~0_9} OutVars{~z_req_up~0=v_~z_req_up~0_9} AuxVars[] AssignedVars[] 839#L230-1 [498] L230-1-->L311-2: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 3) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 840#L311-2 [632] L311-2-->L311-4: Formula: (and (= v_~b0_ev~0_8 1) (= v_~b0_ev~0_9 0)) InVars {~b0_ev~0=v_~b0_ev~0_9} OutVars{~b0_ev~0=v_~b0_ev~0_8} AuxVars[] AssignedVars[~b0_ev~0] 865#L311-4 [832] L311-4-->L316-3: Formula: (> 0 v_~b1_ev~0_10) InVars {~b1_ev~0=v_~b1_ev~0_10} OutVars{~b1_ev~0=v_~b1_ev~0_10} AuxVars[] AssignedVars[] 866#L316-3 [838] L316-3-->L321-3: Formula: (< v_~d0_ev~0_10 0) InVars {~d0_ev~0=v_~d0_ev~0_10} OutVars{~d0_ev~0=v_~d0_ev~0_10} AuxVars[] AssignedVars[] 910#L321-3 [662] L321-3-->L326-3: Formula: (and (= v_~d1_ev~0_8 1) (= 0 v_~d1_ev~0_9)) InVars {~d1_ev~0=v_~d1_ev~0_9} OutVars{~d1_ev~0=v_~d1_ev~0_8} AuxVars[] AssignedVars[~d1_ev~0] 883#L326-3 [850] L326-3-->L331-3: Formula: (> v_~z_ev~0_10 0) InVars {~z_ev~0=v_~z_ev~0_10} OutVars{~z_ev~0=v_~z_ev~0_10} AuxVars[] AssignedVars[] 884#L331-3 [570] L331-3-->L97-1: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_4|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_10, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 917#L97-1 [588] L97-1-->L119-1: Formula: (and (= v_~b0_ev~0_13 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13 1)) InVars {~b0_ev~0=v_~b0_ev~0_13} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13, ~b0_ev~0=v_~b0_ev~0_13} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 872#L119-1 [891] L119-1-->L380-3: Formula: (and (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20 |v_ULTIMATE.start_is_method1_triggered_#res_8|) (= |v_ULTIMATE.start_is_method1_triggered_#res_8| v_ULTIMATE.start_activate_threads_~tmp~1_14)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_14, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_8|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_8|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 832#L380-3 [864] L380-3-->L380-5: Formula: (and (= v_~comp_m1_st~0_7 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11, ~comp_m1_st~0=v_~comp_m1_st~0_7} AuxVars[] AssignedVars[~comp_m1_st~0] 833#L380-5 [868] L380-5-->L344-3: Formula: (< v_~b0_ev~0_20 1) InVars {~b0_ev~0=v_~b0_ev~0_20} OutVars{~b0_ev~0=v_~b0_ev~0_20} AuxVars[] AssignedVars[] 845#L344-3 [870] L344-3-->L349-3: Formula: (< 1 v_~b1_ev~0_20) InVars {~b1_ev~0=v_~b1_ev~0_20} OutVars{~b1_ev~0=v_~b1_ev~0_20} AuxVars[] AssignedVars[] 897#L349-3 [656] L349-3-->L354-3: Formula: (and (= v_~d0_ev~0_18 2) (= v_~d0_ev~0_19 1)) InVars {~d0_ev~0=v_~d0_ev~0_19} OutVars{~d0_ev~0=v_~d0_ev~0_18} AuxVars[] AssignedVars[~d0_ev~0] 860#L354-3 [513] L354-3-->L359-3: Formula: (and (= 1 v_~d1_ev~0_19) (= v_~d1_ev~0_18 2)) InVars {~d1_ev~0=v_~d1_ev~0_19} OutVars{~d1_ev~0=v_~d1_ev~0_18} AuxVars[] AssignedVars[~d1_ev~0] 861#L359-3 [531] L359-3-->L364-3: Formula: (and (= v_~z_ev~0_15 1) (= v_~z_ev~0_14 2)) InVars {~z_ev~0=v_~z_ev~0_15} OutVars{~z_ev~0=v_~z_ev~0_14} AuxVars[] AssignedVars[~z_ev~0] 882#L364-3 [568] L364-3-->L258-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_5, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_2|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_#res] 916#L258-1 [666] L258-1-->L265-1: Formula: (and (= v_~comp_m1_st~0_10 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9 1)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_10} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9, ~comp_m1_st~0=v_~comp_m1_st~0_10} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 911#L265-1 [892] L265-1-->L397: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_stop_simulation_~tmp~2_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_4|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_~tmp~2] 912#L397 [880] L397-->L404: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_4 0) (< 0 v_ULTIMATE.start_stop_simulation_~tmp~2_5)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_4, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 942#L404 [897] L404-->L422-1: Formula: (and (= 0 v_ULTIMATE.start_start_simulation_~tmp~3_9) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= |v_ULTIMATE.start_stop_simulation_#res_5| v_ULTIMATE.start_start_simulation_~tmp~3_9)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_~tmp~3] 918#L422-1 54.07/20.05 [2019-03-28 12:18:49,253 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.05 [2019-03-28 12:18:49,253 INFO L82 PathProgramCache]: Analyzing trace with hash -415434056, now seen corresponding path program 1 times 54.07/20.05 [2019-03-28 12:18:49,253 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.05 [2019-03-28 12:18:49,253 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.05 [2019-03-28 12:18:49,254 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:49,255 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:49,255 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:49,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.05 [2019-03-28 12:18:49,282 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.05 [2019-03-28 12:18:49,283 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.05 [2019-03-28 12:18:49,283 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 54.07/20.05 [2019-03-28 12:18:49,283 INFO L799 eck$LassoCheckResult]: stem already infeasible 54.07/20.05 [2019-03-28 12:18:49,284 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.05 [2019-03-28 12:18:49,284 INFO L82 PathProgramCache]: Analyzing trace with hash -285154061, now seen corresponding path program 5 times 54.07/20.05 [2019-03-28 12:18:49,284 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.05 [2019-03-28 12:18:49,284 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.05 [2019-03-28 12:18:49,285 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:49,285 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:49,285 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:49,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.05 [2019-03-28 12:18:49,313 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.05 [2019-03-28 12:18:49,313 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.05 [2019-03-28 12:18:49,314 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 54.07/20.05 [2019-03-28 12:18:49,314 INFO L811 eck$LassoCheckResult]: loop already infeasible 54.07/20.05 [2019-03-28 12:18:49,314 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 54.07/20.05 [2019-03-28 12:18:49,314 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 54.07/20.05 [2019-03-28 12:18:49,315 INFO L87 Difference]: Start difference. First operand 171 states and 421 transitions. cyclomatic complexity: 251 Second operand 3 states. 54.07/20.05 [2019-03-28 12:18:49,465 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 54.07/20.05 [2019-03-28 12:18:49,466 INFO L93 Difference]: Finished difference Result 90 states and 216 transitions. 54.07/20.05 [2019-03-28 12:18:49,466 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 54.07/20.05 [2019-03-28 12:18:49,466 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 90 states and 216 transitions. 54.07/20.05 [2019-03-28 12:18:49,467 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 56 54.07/20.05 [2019-03-28 12:18:49,468 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 90 states to 90 states and 216 transitions. 54.07/20.05 [2019-03-28 12:18:49,469 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 90 54.07/20.05 [2019-03-28 12:18:49,469 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 90 54.07/20.05 [2019-03-28 12:18:49,469 INFO L73 IsDeterministic]: Start isDeterministic. Operand 90 states and 216 transitions. 54.07/20.05 [2019-03-28 12:18:49,470 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 54.07/20.05 [2019-03-28 12:18:49,470 INFO L706 BuchiCegarLoop]: Abstraction has 90 states and 216 transitions. 54.07/20.05 [2019-03-28 12:18:49,470 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90 states and 216 transitions. 54.07/20.05 [2019-03-28 12:18:49,474 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90 to 90. 54.07/20.05 [2019-03-28 12:18:49,474 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 90 states. 54.07/20.05 [2019-03-28 12:18:49,475 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90 states to 90 states and 216 transitions. 54.07/20.05 [2019-03-28 12:18:49,475 INFO L729 BuchiCegarLoop]: Abstraction has 90 states and 216 transitions. 54.07/20.05 [2019-03-28 12:18:49,475 INFO L609 BuchiCegarLoop]: Abstraction has 90 states and 216 transitions. 54.07/20.05 [2019-03-28 12:18:49,475 INFO L442 BuchiCegarLoop]: ======== Iteration 6============ 54.07/20.05 [2019-03-28 12:18:49,475 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 90 states and 216 transitions. 54.07/20.05 [2019-03-28 12:18:49,476 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 56 54.07/20.05 [2019-03-28 12:18:49,476 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 54.07/20.05 [2019-03-28 12:18:49,477 INFO L119 BuchiIsEmpty]: Starting construction of run 54.07/20.05 [2019-03-28 12:18:49,477 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.05 [2019-03-28 12:18:49,478 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.05 [2019-03-28 12:18:49,478 INFO L794 eck$LassoCheckResult]: Stem: 1167#ULTIMATE.startENTRY [885] ULTIMATE.startENTRY-->L202: Formula: (and (= v_~d0_ev~0_23 2) (= 0 v_~z_val~0_13) (= 2 v_~b1_ev~0_23) (= v_~d0_val_t~0_9 1) (= v_~b0_val~0_13 0) (= 1 v_~b1_val_t~0_9) (= 1 v_~d1_req_up~0_12) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_9 0) (= 2 v_~d1_ev~0_23) (= v_~b1_val~0_13 0) (= v_~b0_val_t~0_9 1) (= v_~b0_req_up~0_12 1) (= 0 v_~comp_m1_i~0_7) (= v_~d0_req_up~0_12 1) (= v_~comp_m1_st~0_15 0) (= v_~b0_ev~0_23 2) (= 1 v_~d1_val_t~0_9) (= v_~z_req_up~0_12 0) (= v_~z_val_t~0_10 0) (= 0 v_~d1_val~0_13) (= v_~z_ev~0_19 2) (= v_~b1_req_up~0_12 1) (= 0 v_~d0_val~0_13)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_4|, ~b1_val~0=v_~b1_val~0_13, ~b0_val~0=v_~b0_val~0_13, ~d0_req_up~0=v_~d0_req_up~0_12, ~d0_val~0=v_~d0_val~0_13, ~d1_val_t~0=v_~d1_val_t~0_9, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_9, ~d1_ev~0=v_~d1_ev~0_23, ~d1_val~0=v_~d1_val~0_13, ~b0_req_up~0=v_~b0_req_up~0_12, ~z_ev~0=v_~z_ev~0_19, ~b1_val_t~0=v_~b1_val_t~0_9, ~b1_ev~0=v_~b1_ev~0_23, ULTIMATE.start_main_~__retres1~2=v_ULTIMATE.start_main_~__retres1~2_6, ~z_val~0=v_~z_val~0_13, ~d1_req_up~0=v_~d1_req_up~0_12, ~z_val_t~0=v_~z_val_t~0_10, ~b0_val_t~0=v_~b0_val_t~0_9, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~z_req_up~0=v_~z_req_up~0_12, ~b1_req_up~0=v_~b1_req_up~0_12, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~d0_ev~0=v_~d0_ev~0_23, ~b0_ev~0=v_~b0_ev~0_23, ~d0_val_t~0=v_~d0_val_t~0_9, ~comp_m1_st~0=v_~comp_m1_st~0_15, ~comp_m1_i~0=v_~comp_m1_i~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ~b1_val~0, ~b0_val~0, ~d0_req_up~0, ~d0_val~0, ~d1_val_t~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~d1_ev~0, ~d1_val~0, ~b0_req_up~0, ~z_ev~0, ~b1_val_t~0, ~b1_ev~0, ULTIMATE.start_main_~__retres1~2, ~z_val~0, ~d1_req_up~0, ~z_val_t~0, ~b0_val_t~0, ULTIMATE.start_start_simulation_~tmp~3, ~z_req_up~0, ~b1_req_up~0, ULTIMATE.start_main_#res, ~d0_ev~0, ~b0_ev~0, ~d0_val_t~0, ~comp_m1_st~0, ~comp_m1_i~0] 1168#L202 [566] L202-->L127: Formula: (= 1 v_~b0_req_up~0_4) InVars {~b0_req_up~0=v_~b0_req_up~0_4} OutVars{~b0_req_up~0=v_~b0_req_up~0_4} AuxVars[] AssignedVars[] 1131#L127 [748] L127-->L127-2: Formula: (and (= v_~b0_val~0_3 v_~b0_val_t~0_3) (> v_~b0_val_t~0_3 v_~b0_val~0_4) (= v_~b0_ev~0_3 0)) InVars {~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_4} OutVars{~b0_ev~0=v_~b0_ev~0_3, ~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_3} AuxVars[] AssignedVars[~b0_val~0, ~b0_ev~0] 1132#L127-2 [580] L127-2-->L202-1: Formula: (= v_~b0_req_up~0_5 0) InVars {} OutVars{~b0_req_up~0=v_~b0_req_up~0_5} AuxVars[] AssignedVars[~b0_req_up~0] 1163#L202-1 [545] L202-1-->L142: Formula: (= 1 v_~b1_req_up~0_4) InVars {~b1_req_up~0=v_~b1_req_up~0_4} OutVars{~b1_req_up~0=v_~b1_req_up~0_4} AuxVars[] AssignedVars[] 1148#L142 [753] L142-->L142-2: Formula: (and (= v_~b1_ev~0_3 0) (> v_~b1_val~0_4 v_~b1_val_t~0_3) (= v_~b1_val~0_3 v_~b1_val_t~0_3)) InVars {~b1_val_t~0=v_~b1_val_t~0_3, ~b1_val~0=v_~b1_val~0_4} OutVars{~b1_val_t~0=v_~b1_val_t~0_3, ~b1_ev~0=v_~b1_ev~0_3, ~b1_val~0=v_~b1_val~0_3} AuxVars[] AssignedVars[~b1_val~0, ~b1_ev~0] 1141#L142-2 [521] L142-2-->L209: Formula: (= v_~b1_req_up~0_5 0) InVars {} OutVars{~b1_req_up~0=v_~b1_req_up~0_5} AuxVars[] AssignedVars[~b1_req_up~0] 1142#L209 [755] L209-->L216: Formula: (< v_~d0_req_up~0_6 1) InVars {~d0_req_up~0=v_~d0_req_up~0_6} OutVars{~d0_req_up~0=v_~d0_req_up~0_6} AuxVars[] AssignedVars[] 1110#L216 [759] L216-->L223: Formula: (> v_~d1_req_up~0_6 1) InVars {~d1_req_up~0=v_~d1_req_up~0_6} OutVars{~d1_req_up~0=v_~d1_req_up~0_6} AuxVars[] AssignedVars[] 1165#L223 [763] L223-->L230: Formula: (< 1 v_~z_req_up~0_6) InVars {~z_req_up~0=v_~z_req_up~0_6} OutVars{~z_req_up~0=v_~z_req_up~0_6} AuxVars[] AssignedVars[] 1111#L230 [767] L230-->L245-1: Formula: (and (> 1 v_~comp_m1_i~0_4) (= v_~comp_m1_st~0_5 2)) InVars {~comp_m1_i~0=v_~comp_m1_i~0_4} OutVars{~comp_m1_st~0=v_~comp_m1_st~0_5, ~comp_m1_i~0=v_~comp_m1_i~0_4} AuxVars[] AssignedVars[~comp_m1_st~0] 1112#L245-1 [769] L245-1-->L311-1: Formula: (> v_~b0_ev~0_7 0) InVars {~b0_ev~0=v_~b0_ev~0_7} OutVars{~b0_ev~0=v_~b0_ev~0_7} AuxVars[] AssignedVars[] 1128#L311-1 [628] L311-1-->L316-1: Formula: (and (= 0 v_~b1_ev~0_6) (= v_~b1_ev~0_5 1)) InVars {~b1_ev~0=v_~b1_ev~0_6} OutVars{~b1_ev~0=v_~b1_ev~0_5} AuxVars[] AssignedVars[~b1_ev~0] 1159#L316-1 [654] L316-1-->L321-1: Formula: (and (= v_~d0_ev~0_5 1) (= v_~d0_ev~0_6 0)) InVars {~d0_ev~0=v_~d0_ev~0_6} OutVars{~d0_ev~0=v_~d0_ev~0_5} AuxVars[] AssignedVars[~d0_ev~0] 1121#L321-1 [507] L321-1-->L326-1: Formula: (and (= 0 v_~d1_ev~0_6) (= v_~d1_ev~0_5 1)) InVars {~d1_ev~0=v_~d1_ev~0_6} OutVars{~d1_ev~0=v_~d1_ev~0_5} AuxVars[] AssignedVars[~d1_ev~0] 1122#L326-1 [556] L326-1-->L331-1: Formula: (and (= 0 v_~z_ev~0_6) (= v_~z_ev~0_5 1)) InVars {~z_ev~0=v_~z_ev~0_6} OutVars{~z_ev~0=v_~z_ev~0_5} AuxVars[] AssignedVars[~z_ev~0] 1174#L331-1 [583] L331-1-->L97: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_1|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 1187#L97 [591] L97-->L119: Formula: (and (= v_~b0_ev~0_11 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4 1)) InVars {~b0_ev~0=v_~b0_ev~0_11} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4, ~b0_ev~0=v_~b0_ev~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 1146#L119 [886] L119-->L380: Formula: (and (= |v_ULTIMATE.start_is_method1_triggered_#res_7| v_ULTIMATE.start_activate_threads_~tmp~1_13) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19 |v_ULTIMATE.start_is_method1_triggered_#res_7|)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_13, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_7|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_7|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 1143#L380 [615] L380-->L380-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_9) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} AuxVars[] AssignedVars[] 1144#L380-2 [618] L380-2-->L344-1: Formula: (and (= v_~b0_ev~0_15 2) (= v_~b0_ev~0_16 1)) InVars {~b0_ev~0=v_~b0_ev~0_16} OutVars{~b0_ev~0=v_~b0_ev~0_15} AuxVars[] AssignedVars[~b0_ev~0] 1149#L344-1 [791] L344-1-->L349-1: Formula: (> 1 v_~b1_ev~0_17) InVars {~b1_ev~0=v_~b1_ev~0_17} OutVars{~b1_ev~0=v_~b1_ev~0_17} AuxVars[] AssignedVars[] 1157#L349-1 [652] L349-1-->L354-1: Formula: (and (= v_~d0_ev~0_15 2) (= v_~d0_ev~0_16 1)) InVars {~d0_ev~0=v_~d0_ev~0_16} OutVars{~d0_ev~0=v_~d0_ev~0_15} AuxVars[] AssignedVars[~d0_ev~0] 1116#L354-1 [795] L354-1-->L359-1: Formula: (> 1 v_~d1_ev~0_17) InVars {~d1_ev~0=v_~d1_ev~0_17} OutVars{~d1_ev~0=v_~d1_ev~0_17} AuxVars[] AssignedVars[] 1117#L359-1 [797] L359-1-->L422-1: Formula: (> v_~z_ev~0_13 1) InVars {~z_ev~0=v_~z_ev~0_13} OutVars{~z_ev~0=v_~z_ev~0_13} AuxVars[] AssignedVars[] 1173#L422-1 54.07/20.05 [2019-03-28 12:18:49,479 INFO L796 eck$LassoCheckResult]: Loop: 1173#L422-1 [887] L422-1-->L285: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 1) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 1118#L285 [888] L285-->L258: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_13, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res] 1119#L258 [802] L258-->L265: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8 0) (> 0 v_~comp_m1_st~0_9)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_9} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8, ~comp_m1_st~0=v_~comp_m1_st~0_9} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 1178#L265 [889] L265-->L280: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___0~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 1179#L280 [890] L280-->L202-2: Formula: (and (= v_ULTIMATE.start_eval_~tmp___0~0_8 0) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 2)) InVars {ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 1160#L202-2 [800] L202-2-->L202-3: Formula: (> 1 v_~b0_req_up~0_9) InVars {~b0_req_up~0=v_~b0_req_up~0_9} OutVars{~b0_req_up~0=v_~b0_req_up~0_9} AuxVars[] AssignedVars[] 1158#L202-3 [807] L202-3-->L209-1: Formula: (> 1 v_~b1_req_up~0_9) InVars {~b1_req_up~0=v_~b1_req_up~0_9} OutVars{~b1_req_up~0=v_~b1_req_up~0_9} AuxVars[] AssignedVars[] 1151#L209-1 [810] L209-1-->L216-1: Formula: (> v_~d0_req_up~0_9 1) InVars {~d0_req_up~0=v_~d0_req_up~0_9} OutVars{~d0_req_up~0=v_~d0_req_up~0_9} AuxVars[] AssignedVars[] 1147#L216-1 [814] L216-1-->L223-1: Formula: (> v_~d1_req_up~0_9 1) InVars {~d1_req_up~0=v_~d1_req_up~0_9} OutVars{~d1_req_up~0=v_~d1_req_up~0_9} AuxVars[] AssignedVars[] 1115#L223-1 [820] L223-1-->L230-1: Formula: (< 1 v_~z_req_up~0_9) InVars {~z_req_up~0=v_~z_req_up~0_9} OutVars{~z_req_up~0=v_~z_req_up~0_9} AuxVars[] AssignedVars[] 1104#L230-1 [498] L230-1-->L311-2: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 3) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 1105#L311-2 [632] L311-2-->L311-4: Formula: (and (= v_~b0_ev~0_8 1) (= v_~b0_ev~0_9 0)) InVars {~b0_ev~0=v_~b0_ev~0_9} OutVars{~b0_ev~0=v_~b0_ev~0_8} AuxVars[] AssignedVars[~b0_ev~0] 1133#L311-4 [832] L311-4-->L316-3: Formula: (> 0 v_~b1_ev~0_10) InVars {~b1_ev~0=v_~b1_ev~0_10} OutVars{~b1_ev~0=v_~b1_ev~0_10} AuxVars[] AssignedVars[] 1134#L316-3 [838] L316-3-->L321-3: Formula: (< v_~d0_ev~0_10 0) InVars {~d0_ev~0=v_~d0_ev~0_10} OutVars{~d0_ev~0=v_~d0_ev~0_10} AuxVars[] AssignedVars[] 1175#L321-3 [662] L321-3-->L326-3: Formula: (and (= v_~d1_ev~0_8 1) (= 0 v_~d1_ev~0_9)) InVars {~d1_ev~0=v_~d1_ev~0_9} OutVars{~d1_ev~0=v_~d1_ev~0_8} AuxVars[] AssignedVars[~d1_ev~0] 1152#L326-3 [850] L326-3-->L331-3: Formula: (> v_~z_ev~0_10 0) InVars {~z_ev~0=v_~z_ev~0_10} OutVars{~z_ev~0=v_~z_ev~0_10} AuxVars[] AssignedVars[] 1153#L331-3 [570] L331-3-->L97-1: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_4|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_10, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 1182#L97-1 [588] L97-1-->L119-1: Formula: (and (= v_~b0_ev~0_13 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13 1)) InVars {~b0_ev~0=v_~b0_ev~0_13} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13, ~b0_ev~0=v_~b0_ev~0_13} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 1140#L119-1 [891] L119-1-->L380-3: Formula: (and (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20 |v_ULTIMATE.start_is_method1_triggered_#res_8|) (= |v_ULTIMATE.start_is_method1_triggered_#res_8| v_ULTIMATE.start_activate_threads_~tmp~1_14)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_14, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_8|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_8|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 1102#L380-3 [864] L380-3-->L380-5: Formula: (and (= v_~comp_m1_st~0_7 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11, ~comp_m1_st~0=v_~comp_m1_st~0_7} AuxVars[] AssignedVars[~comp_m1_st~0] 1103#L380-5 [868] L380-5-->L344-3: Formula: (< v_~b0_ev~0_20 1) InVars {~b0_ev~0=v_~b0_ev~0_20} OutVars{~b0_ev~0=v_~b0_ev~0_20} AuxVars[] AssignedVars[] 1113#L344-3 [870] L344-3-->L349-3: Formula: (< 1 v_~b1_ev~0_20) InVars {~b1_ev~0=v_~b1_ev~0_20} OutVars{~b1_ev~0=v_~b1_ev~0_20} AuxVars[] AssignedVars[] 1162#L349-3 [656] L349-3-->L354-3: Formula: (and (= v_~d0_ev~0_18 2) (= v_~d0_ev~0_19 1)) InVars {~d0_ev~0=v_~d0_ev~0_19} OutVars{~d0_ev~0=v_~d0_ev~0_18} AuxVars[] AssignedVars[~d0_ev~0] 1129#L354-3 [513] L354-3-->L359-3: Formula: (and (= 1 v_~d1_ev~0_19) (= v_~d1_ev~0_18 2)) InVars {~d1_ev~0=v_~d1_ev~0_19} OutVars{~d1_ev~0=v_~d1_ev~0_18} AuxVars[] AssignedVars[~d1_ev~0] 1130#L359-3 [531] L359-3-->L364-3: Formula: (and (= v_~z_ev~0_15 1) (= v_~z_ev~0_14 2)) InVars {~z_ev~0=v_~z_ev~0_15} OutVars{~z_ev~0=v_~z_ev~0_14} AuxVars[] AssignedVars[~z_ev~0] 1150#L364-3 [568] L364-3-->L258-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_5, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_2|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_#res] 1181#L258-1 [666] L258-1-->L265-1: Formula: (and (= v_~comp_m1_st~0_10 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9 1)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_10} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9, ~comp_m1_st~0=v_~comp_m1_st~0_10} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 1176#L265-1 [892] L265-1-->L397: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_stop_simulation_~tmp~2_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_4|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_~tmp~2] 1177#L397 [880] L397-->L404: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_4 0) (< 0 v_ULTIMATE.start_stop_simulation_~tmp~2_5)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_4, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 1180#L404 [897] L404-->L422-1: Formula: (and (= 0 v_ULTIMATE.start_start_simulation_~tmp~3_9) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= |v_ULTIMATE.start_stop_simulation_#res_5| v_ULTIMATE.start_start_simulation_~tmp~3_9)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_~tmp~3] 1173#L422-1 54.07/20.05 [2019-03-28 12:18:49,479 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.05 [2019-03-28 12:18:49,480 INFO L82 PathProgramCache]: Analyzing trace with hash 1274004643, now seen corresponding path program 1 times 54.07/20.05 [2019-03-28 12:18:49,480 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.05 [2019-03-28 12:18:49,480 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.05 [2019-03-28 12:18:49,481 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:49,481 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:49,481 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:49,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.05 [2019-03-28 12:18:49,500 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.05 [2019-03-28 12:18:49,501 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.05 [2019-03-28 12:18:49,501 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 54.07/20.05 [2019-03-28 12:18:49,501 INFO L799 eck$LassoCheckResult]: stem already infeasible 54.07/20.05 [2019-03-28 12:18:49,501 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.05 [2019-03-28 12:18:49,502 INFO L82 PathProgramCache]: Analyzing trace with hash -352160814, now seen corresponding path program 1 times 54.07/20.05 [2019-03-28 12:18:49,502 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.05 [2019-03-28 12:18:49,502 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.05 [2019-03-28 12:18:49,503 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:49,503 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:49,503 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:49,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.05 [2019-03-28 12:18:49,524 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.05 [2019-03-28 12:18:49,525 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.05 [2019-03-28 12:18:49,525 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 54.07/20.05 [2019-03-28 12:18:49,525 INFO L811 eck$LassoCheckResult]: loop already infeasible 54.07/20.05 [2019-03-28 12:18:49,525 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 54.07/20.05 [2019-03-28 12:18:49,525 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 54.07/20.05 [2019-03-28 12:18:49,526 INFO L87 Difference]: Start difference. First operand 90 states and 216 transitions. cyclomatic complexity: 127 Second operand 3 states. 54.07/20.05 [2019-03-28 12:18:49,704 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 54.07/20.05 [2019-03-28 12:18:49,704 INFO L93 Difference]: Finished difference Result 90 states and 214 transitions. 54.07/20.05 [2019-03-28 12:18:49,705 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 54.07/20.05 [2019-03-28 12:18:49,705 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 90 states and 214 transitions. 54.07/20.05 [2019-03-28 12:18:49,706 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 56 54.07/20.05 [2019-03-28 12:18:49,707 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 90 states to 90 states and 214 transitions. 54.07/20.05 [2019-03-28 12:18:49,708 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 90 54.07/20.05 [2019-03-28 12:18:49,708 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 90 54.07/20.05 [2019-03-28 12:18:49,708 INFO L73 IsDeterministic]: Start isDeterministic. Operand 90 states and 214 transitions. 54.07/20.05 [2019-03-28 12:18:49,709 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 54.07/20.05 [2019-03-28 12:18:49,709 INFO L706 BuchiCegarLoop]: Abstraction has 90 states and 214 transitions. 54.07/20.05 [2019-03-28 12:18:49,709 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90 states and 214 transitions. 54.07/20.05 [2019-03-28 12:18:49,712 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90 to 90. 54.07/20.05 [2019-03-28 12:18:49,712 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 90 states. 54.07/20.05 [2019-03-28 12:18:49,713 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90 states to 90 states and 214 transitions. 54.07/20.05 [2019-03-28 12:18:49,713 INFO L729 BuchiCegarLoop]: Abstraction has 90 states and 214 transitions. 54.07/20.05 [2019-03-28 12:18:49,713 INFO L609 BuchiCegarLoop]: Abstraction has 90 states and 214 transitions. 54.07/20.05 [2019-03-28 12:18:49,713 INFO L442 BuchiCegarLoop]: ======== Iteration 7============ 54.07/20.05 [2019-03-28 12:18:49,714 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 90 states and 214 transitions. 54.07/20.05 [2019-03-28 12:18:49,714 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 56 54.07/20.05 [2019-03-28 12:18:49,714 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 54.07/20.05 [2019-03-28 12:18:49,715 INFO L119 BuchiIsEmpty]: Starting construction of run 54.07/20.05 [2019-03-28 12:18:49,716 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.05 [2019-03-28 12:18:49,716 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.05 [2019-03-28 12:18:49,717 INFO L794 eck$LassoCheckResult]: Stem: 1354#ULTIMATE.startENTRY [885] ULTIMATE.startENTRY-->L202: Formula: (and (= v_~d0_ev~0_23 2) (= 0 v_~z_val~0_13) (= 2 v_~b1_ev~0_23) (= v_~d0_val_t~0_9 1) (= v_~b0_val~0_13 0) (= 1 v_~b1_val_t~0_9) (= 1 v_~d1_req_up~0_12) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_9 0) (= 2 v_~d1_ev~0_23) (= v_~b1_val~0_13 0) (= v_~b0_val_t~0_9 1) (= v_~b0_req_up~0_12 1) (= 0 v_~comp_m1_i~0_7) (= v_~d0_req_up~0_12 1) (= v_~comp_m1_st~0_15 0) (= v_~b0_ev~0_23 2) (= 1 v_~d1_val_t~0_9) (= v_~z_req_up~0_12 0) (= v_~z_val_t~0_10 0) (= 0 v_~d1_val~0_13) (= v_~z_ev~0_19 2) (= v_~b1_req_up~0_12 1) (= 0 v_~d0_val~0_13)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_4|, ~b1_val~0=v_~b1_val~0_13, ~b0_val~0=v_~b0_val~0_13, ~d0_req_up~0=v_~d0_req_up~0_12, ~d0_val~0=v_~d0_val~0_13, ~d1_val_t~0=v_~d1_val_t~0_9, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_9, ~d1_ev~0=v_~d1_ev~0_23, ~d1_val~0=v_~d1_val~0_13, ~b0_req_up~0=v_~b0_req_up~0_12, ~z_ev~0=v_~z_ev~0_19, ~b1_val_t~0=v_~b1_val_t~0_9, ~b1_ev~0=v_~b1_ev~0_23, ULTIMATE.start_main_~__retres1~2=v_ULTIMATE.start_main_~__retres1~2_6, ~z_val~0=v_~z_val~0_13, ~d1_req_up~0=v_~d1_req_up~0_12, ~z_val_t~0=v_~z_val_t~0_10, ~b0_val_t~0=v_~b0_val_t~0_9, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~z_req_up~0=v_~z_req_up~0_12, ~b1_req_up~0=v_~b1_req_up~0_12, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~d0_ev~0=v_~d0_ev~0_23, ~b0_ev~0=v_~b0_ev~0_23, ~d0_val_t~0=v_~d0_val_t~0_9, ~comp_m1_st~0=v_~comp_m1_st~0_15, ~comp_m1_i~0=v_~comp_m1_i~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ~b1_val~0, ~b0_val~0, ~d0_req_up~0, ~d0_val~0, ~d1_val_t~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~d1_ev~0, ~d1_val~0, ~b0_req_up~0, ~z_ev~0, ~b1_val_t~0, ~b1_ev~0, ULTIMATE.start_main_~__retres1~2, ~z_val~0, ~d1_req_up~0, ~z_val_t~0, ~b0_val_t~0, ULTIMATE.start_start_simulation_~tmp~3, ~z_req_up~0, ~b1_req_up~0, ULTIMATE.start_main_#res, ~d0_ev~0, ~b0_ev~0, ~d0_val_t~0, ~comp_m1_st~0, ~comp_m1_i~0] 1355#L202 [566] L202-->L127: Formula: (= 1 v_~b0_req_up~0_4) InVars {~b0_req_up~0=v_~b0_req_up~0_4} OutVars{~b0_req_up~0=v_~b0_req_up~0_4} AuxVars[] AssignedVars[] 1318#L127 [748] L127-->L127-2: Formula: (and (= v_~b0_val~0_3 v_~b0_val_t~0_3) (> v_~b0_val_t~0_3 v_~b0_val~0_4) (= v_~b0_ev~0_3 0)) InVars {~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_4} OutVars{~b0_ev~0=v_~b0_ev~0_3, ~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_3} AuxVars[] AssignedVars[~b0_val~0, ~b0_ev~0] 1319#L127-2 [580] L127-2-->L202-1: Formula: (= v_~b0_req_up~0_5 0) InVars {} OutVars{~b0_req_up~0=v_~b0_req_up~0_5} AuxVars[] AssignedVars[~b0_req_up~0] 1350#L202-1 [545] L202-1-->L142: Formula: (= 1 v_~b1_req_up~0_4) InVars {~b1_req_up~0=v_~b1_req_up~0_4} OutVars{~b1_req_up~0=v_~b1_req_up~0_4} AuxVars[] AssignedVars[] 1335#L142 [752] L142-->L142-2: Formula: (and (= v_~b1_ev~0_3 0) (< v_~b1_val~0_4 v_~b1_val_t~0_3) (= v_~b1_val~0_3 v_~b1_val_t~0_3)) InVars {~b1_val_t~0=v_~b1_val_t~0_3, ~b1_val~0=v_~b1_val~0_4} OutVars{~b1_val_t~0=v_~b1_val_t~0_3, ~b1_ev~0=v_~b1_ev~0_3, ~b1_val~0=v_~b1_val~0_3} AuxVars[] AssignedVars[~b1_val~0, ~b1_ev~0] 1326#L142-2 [521] L142-2-->L209: Formula: (= v_~b1_req_up~0_5 0) InVars {} OutVars{~b1_req_up~0=v_~b1_req_up~0_5} AuxVars[] AssignedVars[~b1_req_up~0] 1327#L209 [755] L209-->L216: Formula: (< v_~d0_req_up~0_6 1) InVars {~d0_req_up~0=v_~d0_req_up~0_6} OutVars{~d0_req_up~0=v_~d0_req_up~0_6} AuxVars[] AssignedVars[] 1297#L216 [759] L216-->L223: Formula: (> v_~d1_req_up~0_6 1) InVars {~d1_req_up~0=v_~d1_req_up~0_6} OutVars{~d1_req_up~0=v_~d1_req_up~0_6} AuxVars[] AssignedVars[] 1352#L223 [763] L223-->L230: Formula: (< 1 v_~z_req_up~0_6) InVars {~z_req_up~0=v_~z_req_up~0_6} OutVars{~z_req_up~0=v_~z_req_up~0_6} AuxVars[] AssignedVars[] 1298#L230 [767] L230-->L245-1: Formula: (and (> 1 v_~comp_m1_i~0_4) (= v_~comp_m1_st~0_5 2)) InVars {~comp_m1_i~0=v_~comp_m1_i~0_4} OutVars{~comp_m1_st~0=v_~comp_m1_st~0_5, ~comp_m1_i~0=v_~comp_m1_i~0_4} AuxVars[] AssignedVars[~comp_m1_st~0] 1299#L245-1 [769] L245-1-->L311-1: Formula: (> v_~b0_ev~0_7 0) InVars {~b0_ev~0=v_~b0_ev~0_7} OutVars{~b0_ev~0=v_~b0_ev~0_7} AuxVars[] AssignedVars[] 1317#L311-1 [628] L311-1-->L316-1: Formula: (and (= 0 v_~b1_ev~0_6) (= v_~b1_ev~0_5 1)) InVars {~b1_ev~0=v_~b1_ev~0_6} OutVars{~b1_ev~0=v_~b1_ev~0_5} AuxVars[] AssignedVars[~b1_ev~0] 1346#L316-1 [654] L316-1-->L321-1: Formula: (and (= v_~d0_ev~0_5 1) (= v_~d0_ev~0_6 0)) InVars {~d0_ev~0=v_~d0_ev~0_6} OutVars{~d0_ev~0=v_~d0_ev~0_5} AuxVars[] AssignedVars[~d0_ev~0] 1308#L321-1 [507] L321-1-->L326-1: Formula: (and (= 0 v_~d1_ev~0_6) (= v_~d1_ev~0_5 1)) InVars {~d1_ev~0=v_~d1_ev~0_6} OutVars{~d1_ev~0=v_~d1_ev~0_5} AuxVars[] AssignedVars[~d1_ev~0] 1309#L326-1 [556] L326-1-->L331-1: Formula: (and (= 0 v_~z_ev~0_6) (= v_~z_ev~0_5 1)) InVars {~z_ev~0=v_~z_ev~0_6} OutVars{~z_ev~0=v_~z_ev~0_5} AuxVars[] AssignedVars[~z_ev~0] 1361#L331-1 [583] L331-1-->L97: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_1|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 1374#L97 [591] L97-->L119: Formula: (and (= v_~b0_ev~0_11 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4 1)) InVars {~b0_ev~0=v_~b0_ev~0_11} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4, ~b0_ev~0=v_~b0_ev~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 1333#L119 [886] L119-->L380: Formula: (and (= |v_ULTIMATE.start_is_method1_triggered_#res_7| v_ULTIMATE.start_activate_threads_~tmp~1_13) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19 |v_ULTIMATE.start_is_method1_triggered_#res_7|)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_13, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_7|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_7|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 1330#L380 [615] L380-->L380-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_9) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} AuxVars[] AssignedVars[] 1331#L380-2 [618] L380-2-->L344-1: Formula: (and (= v_~b0_ev~0_15 2) (= v_~b0_ev~0_16 1)) InVars {~b0_ev~0=v_~b0_ev~0_16} OutVars{~b0_ev~0=v_~b0_ev~0_15} AuxVars[] AssignedVars[~b0_ev~0] 1336#L344-1 [791] L344-1-->L349-1: Formula: (> 1 v_~b1_ev~0_17) InVars {~b1_ev~0=v_~b1_ev~0_17} OutVars{~b1_ev~0=v_~b1_ev~0_17} AuxVars[] AssignedVars[] 1344#L349-1 [652] L349-1-->L354-1: Formula: (and (= v_~d0_ev~0_15 2) (= v_~d0_ev~0_16 1)) InVars {~d0_ev~0=v_~d0_ev~0_16} OutVars{~d0_ev~0=v_~d0_ev~0_15} AuxVars[] AssignedVars[~d0_ev~0] 1303#L354-1 [795] L354-1-->L359-1: Formula: (> 1 v_~d1_ev~0_17) InVars {~d1_ev~0=v_~d1_ev~0_17} OutVars{~d1_ev~0=v_~d1_ev~0_17} AuxVars[] AssignedVars[] 1304#L359-1 [797] L359-1-->L422-1: Formula: (> v_~z_ev~0_13 1) InVars {~z_ev~0=v_~z_ev~0_13} OutVars{~z_ev~0=v_~z_ev~0_13} AuxVars[] AssignedVars[] 1360#L422-1 54.07/20.05 [2019-03-28 12:18:49,717 INFO L796 eck$LassoCheckResult]: Loop: 1360#L422-1 [887] L422-1-->L285: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 1) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 1306#L285 [888] L285-->L258: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_13, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res] 1307#L258 [802] L258-->L265: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8 0) (> 0 v_~comp_m1_st~0_9)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_9} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8, ~comp_m1_st~0=v_~comp_m1_st~0_9} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 1365#L265 [889] L265-->L280: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___0~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 1366#L280 [890] L280-->L202-2: Formula: (and (= v_ULTIMATE.start_eval_~tmp___0~0_8 0) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 2)) InVars {ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 1347#L202-2 [800] L202-2-->L202-3: Formula: (> 1 v_~b0_req_up~0_9) InVars {~b0_req_up~0=v_~b0_req_up~0_9} OutVars{~b0_req_up~0=v_~b0_req_up~0_9} AuxVars[] AssignedVars[] 1345#L202-3 [807] L202-3-->L209-1: Formula: (> 1 v_~b1_req_up~0_9) InVars {~b1_req_up~0=v_~b1_req_up~0_9} OutVars{~b1_req_up~0=v_~b1_req_up~0_9} AuxVars[] AssignedVars[] 1338#L209-1 [810] L209-1-->L216-1: Formula: (> v_~d0_req_up~0_9 1) InVars {~d0_req_up~0=v_~d0_req_up~0_9} OutVars{~d0_req_up~0=v_~d0_req_up~0_9} AuxVars[] AssignedVars[] 1334#L216-1 [814] L216-1-->L223-1: Formula: (> v_~d1_req_up~0_9 1) InVars {~d1_req_up~0=v_~d1_req_up~0_9} OutVars{~d1_req_up~0=v_~d1_req_up~0_9} AuxVars[] AssignedVars[] 1302#L223-1 [820] L223-1-->L230-1: Formula: (< 1 v_~z_req_up~0_9) InVars {~z_req_up~0=v_~z_req_up~0_9} OutVars{~z_req_up~0=v_~z_req_up~0_9} AuxVars[] AssignedVars[] 1291#L230-1 [498] L230-1-->L311-2: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 3) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 1292#L311-2 [632] L311-2-->L311-4: Formula: (and (= v_~b0_ev~0_8 1) (= v_~b0_ev~0_9 0)) InVars {~b0_ev~0=v_~b0_ev~0_9} OutVars{~b0_ev~0=v_~b0_ev~0_8} AuxVars[] AssignedVars[~b0_ev~0] 1320#L311-4 [832] L311-4-->L316-3: Formula: (> 0 v_~b1_ev~0_10) InVars {~b1_ev~0=v_~b1_ev~0_10} OutVars{~b1_ev~0=v_~b1_ev~0_10} AuxVars[] AssignedVars[] 1321#L316-3 [838] L316-3-->L321-3: Formula: (< v_~d0_ev~0_10 0) InVars {~d0_ev~0=v_~d0_ev~0_10} OutVars{~d0_ev~0=v_~d0_ev~0_10} AuxVars[] AssignedVars[] 1362#L321-3 [662] L321-3-->L326-3: Formula: (and (= v_~d1_ev~0_8 1) (= 0 v_~d1_ev~0_9)) InVars {~d1_ev~0=v_~d1_ev~0_9} OutVars{~d1_ev~0=v_~d1_ev~0_8} AuxVars[] AssignedVars[~d1_ev~0] 1339#L326-3 [850] L326-3-->L331-3: Formula: (> v_~z_ev~0_10 0) InVars {~z_ev~0=v_~z_ev~0_10} OutVars{~z_ev~0=v_~z_ev~0_10} AuxVars[] AssignedVars[] 1340#L331-3 [570] L331-3-->L97-1: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_4|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_10, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 1369#L97-1 [588] L97-1-->L119-1: Formula: (and (= v_~b0_ev~0_13 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13 1)) InVars {~b0_ev~0=v_~b0_ev~0_13} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13, ~b0_ev~0=v_~b0_ev~0_13} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 1329#L119-1 [891] L119-1-->L380-3: Formula: (and (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20 |v_ULTIMATE.start_is_method1_triggered_#res_8|) (= |v_ULTIMATE.start_is_method1_triggered_#res_8| v_ULTIMATE.start_activate_threads_~tmp~1_14)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_14, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_8|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_8|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 1289#L380-3 [864] L380-3-->L380-5: Formula: (and (= v_~comp_m1_st~0_7 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11, ~comp_m1_st~0=v_~comp_m1_st~0_7} AuxVars[] AssignedVars[~comp_m1_st~0] 1290#L380-5 [868] L380-5-->L344-3: Formula: (< v_~b0_ev~0_20 1) InVars {~b0_ev~0=v_~b0_ev~0_20} OutVars{~b0_ev~0=v_~b0_ev~0_20} AuxVars[] AssignedVars[] 1300#L344-3 [870] L344-3-->L349-3: Formula: (< 1 v_~b1_ev~0_20) InVars {~b1_ev~0=v_~b1_ev~0_20} OutVars{~b1_ev~0=v_~b1_ev~0_20} AuxVars[] AssignedVars[] 1349#L349-3 [656] L349-3-->L354-3: Formula: (and (= v_~d0_ev~0_18 2) (= v_~d0_ev~0_19 1)) InVars {~d0_ev~0=v_~d0_ev~0_19} OutVars{~d0_ev~0=v_~d0_ev~0_18} AuxVars[] AssignedVars[~d0_ev~0] 1315#L354-3 [513] L354-3-->L359-3: Formula: (and (= 1 v_~d1_ev~0_19) (= v_~d1_ev~0_18 2)) InVars {~d1_ev~0=v_~d1_ev~0_19} OutVars{~d1_ev~0=v_~d1_ev~0_18} AuxVars[] AssignedVars[~d1_ev~0] 1316#L359-3 [531] L359-3-->L364-3: Formula: (and (= v_~z_ev~0_15 1) (= v_~z_ev~0_14 2)) InVars {~z_ev~0=v_~z_ev~0_15} OutVars{~z_ev~0=v_~z_ev~0_14} AuxVars[] AssignedVars[~z_ev~0] 1337#L364-3 [568] L364-3-->L258-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_5, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_2|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_#res] 1368#L258-1 [666] L258-1-->L265-1: Formula: (and (= v_~comp_m1_st~0_10 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9 1)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_10} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9, ~comp_m1_st~0=v_~comp_m1_st~0_10} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 1363#L265-1 [892] L265-1-->L397: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_stop_simulation_~tmp~2_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_4|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_~tmp~2] 1364#L397 [880] L397-->L404: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_4 0) (< 0 v_ULTIMATE.start_stop_simulation_~tmp~2_5)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_4, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 1367#L404 [897] L404-->L422-1: Formula: (and (= 0 v_ULTIMATE.start_start_simulation_~tmp~3_9) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= |v_ULTIMATE.start_stop_simulation_#res_5| v_ULTIMATE.start_start_simulation_~tmp~3_9)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_~tmp~3] 1360#L422-1 54.07/20.05 [2019-03-28 12:18:49,718 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.05 [2019-03-28 12:18:49,718 INFO L82 PathProgramCache]: Analyzing trace with hash 1682828868, now seen corresponding path program 1 times 54.07/20.05 [2019-03-28 12:18:49,718 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.05 [2019-03-28 12:18:49,718 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.05 [2019-03-28 12:18:49,719 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:49,719 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:49,720 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:49,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.05 [2019-03-28 12:18:49,736 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.05 [2019-03-28 12:18:49,737 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.05 [2019-03-28 12:18:49,737 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 54.07/20.05 [2019-03-28 12:18:49,737 INFO L799 eck$LassoCheckResult]: stem already infeasible 54.07/20.05 [2019-03-28 12:18:49,738 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.05 [2019-03-28 12:18:49,738 INFO L82 PathProgramCache]: Analyzing trace with hash -352160814, now seen corresponding path program 2 times 54.07/20.05 [2019-03-28 12:18:49,738 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.05 [2019-03-28 12:18:49,738 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.05 [2019-03-28 12:18:49,739 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:49,739 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:49,739 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:49,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.05 [2019-03-28 12:18:49,761 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.05 [2019-03-28 12:18:49,762 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.05 [2019-03-28 12:18:49,762 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 54.07/20.05 [2019-03-28 12:18:49,762 INFO L811 eck$LassoCheckResult]: loop already infeasible 54.07/20.05 [2019-03-28 12:18:49,762 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 54.07/20.05 [2019-03-28 12:18:49,762 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 54.07/20.05 [2019-03-28 12:18:49,763 INFO L87 Difference]: Start difference. First operand 90 states and 214 transitions. cyclomatic complexity: 125 Second operand 3 states. 54.07/20.05 [2019-03-28 12:18:50,026 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 54.07/20.05 [2019-03-28 12:18:50,027 INFO L93 Difference]: Finished difference Result 168 states and 408 transitions. 54.07/20.05 [2019-03-28 12:18:50,027 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 54.07/20.05 [2019-03-28 12:18:50,027 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 168 states and 408 transitions. 54.07/20.05 [2019-03-28 12:18:50,029 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 110 54.07/20.05 [2019-03-28 12:18:50,031 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 168 states to 168 states and 408 transitions. 54.07/20.05 [2019-03-28 12:18:50,031 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 168 54.07/20.05 [2019-03-28 12:18:50,031 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 168 54.07/20.05 [2019-03-28 12:18:50,031 INFO L73 IsDeterministic]: Start isDeterministic. Operand 168 states and 408 transitions. 54.07/20.05 [2019-03-28 12:18:50,032 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 54.07/20.05 [2019-03-28 12:18:50,032 INFO L706 BuchiCegarLoop]: Abstraction has 168 states and 408 transitions. 54.07/20.05 [2019-03-28 12:18:50,032 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 168 states and 408 transitions. 54.07/20.05 [2019-03-28 12:18:50,038 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 168 to 168. 54.07/20.05 [2019-03-28 12:18:50,038 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 168 states. 54.07/20.05 [2019-03-28 12:18:50,039 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 168 states to 168 states and 408 transitions. 54.07/20.05 [2019-03-28 12:18:50,039 INFO L729 BuchiCegarLoop]: Abstraction has 168 states and 408 transitions. 54.07/20.05 [2019-03-28 12:18:50,039 INFO L609 BuchiCegarLoop]: Abstraction has 168 states and 408 transitions. 54.07/20.05 [2019-03-28 12:18:50,040 INFO L442 BuchiCegarLoop]: ======== Iteration 8============ 54.07/20.05 [2019-03-28 12:18:50,040 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 168 states and 408 transitions. 54.07/20.05 [2019-03-28 12:18:50,041 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 110 54.07/20.05 [2019-03-28 12:18:50,041 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 54.07/20.05 [2019-03-28 12:18:50,041 INFO L119 BuchiIsEmpty]: Starting construction of run 54.07/20.05 [2019-03-28 12:18:50,042 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.05 [2019-03-28 12:18:50,042 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.05 [2019-03-28 12:18:50,043 INFO L794 eck$LassoCheckResult]: Stem: 1625#ULTIMATE.startENTRY [885] ULTIMATE.startENTRY-->L202: Formula: (and (= v_~d0_ev~0_23 2) (= 0 v_~z_val~0_13) (= 2 v_~b1_ev~0_23) (= v_~d0_val_t~0_9 1) (= v_~b0_val~0_13 0) (= 1 v_~b1_val_t~0_9) (= 1 v_~d1_req_up~0_12) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_9 0) (= 2 v_~d1_ev~0_23) (= v_~b1_val~0_13 0) (= v_~b0_val_t~0_9 1) (= v_~b0_req_up~0_12 1) (= 0 v_~comp_m1_i~0_7) (= v_~d0_req_up~0_12 1) (= v_~comp_m1_st~0_15 0) (= v_~b0_ev~0_23 2) (= 1 v_~d1_val_t~0_9) (= v_~z_req_up~0_12 0) (= v_~z_val_t~0_10 0) (= 0 v_~d1_val~0_13) (= v_~z_ev~0_19 2) (= v_~b1_req_up~0_12 1) (= 0 v_~d0_val~0_13)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_4|, ~b1_val~0=v_~b1_val~0_13, ~b0_val~0=v_~b0_val~0_13, ~d0_req_up~0=v_~d0_req_up~0_12, ~d0_val~0=v_~d0_val~0_13, ~d1_val_t~0=v_~d1_val_t~0_9, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_9, ~d1_ev~0=v_~d1_ev~0_23, ~d1_val~0=v_~d1_val~0_13, ~b0_req_up~0=v_~b0_req_up~0_12, ~z_ev~0=v_~z_ev~0_19, ~b1_val_t~0=v_~b1_val_t~0_9, ~b1_ev~0=v_~b1_ev~0_23, ULTIMATE.start_main_~__retres1~2=v_ULTIMATE.start_main_~__retres1~2_6, ~z_val~0=v_~z_val~0_13, ~d1_req_up~0=v_~d1_req_up~0_12, ~z_val_t~0=v_~z_val_t~0_10, ~b0_val_t~0=v_~b0_val_t~0_9, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~z_req_up~0=v_~z_req_up~0_12, ~b1_req_up~0=v_~b1_req_up~0_12, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~d0_ev~0=v_~d0_ev~0_23, ~b0_ev~0=v_~b0_ev~0_23, ~d0_val_t~0=v_~d0_val_t~0_9, ~comp_m1_st~0=v_~comp_m1_st~0_15, ~comp_m1_i~0=v_~comp_m1_i~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ~b1_val~0, ~b0_val~0, ~d0_req_up~0, ~d0_val~0, ~d1_val_t~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~d1_ev~0, ~d1_val~0, ~b0_req_up~0, ~z_ev~0, ~b1_val_t~0, ~b1_ev~0, ULTIMATE.start_main_~__retres1~2, ~z_val~0, ~d1_req_up~0, ~z_val_t~0, ~b0_val_t~0, ULTIMATE.start_start_simulation_~tmp~3, ~z_req_up~0, ~b1_req_up~0, ULTIMATE.start_main_#res, ~d0_ev~0, ~b0_ev~0, ~d0_val_t~0, ~comp_m1_st~0, ~comp_m1_i~0] 1626#L202 [566] L202-->L127: Formula: (= 1 v_~b0_req_up~0_4) InVars {~b0_req_up~0=v_~b0_req_up~0_4} OutVars{~b0_req_up~0=v_~b0_req_up~0_4} AuxVars[] AssignedVars[] 1583#L127 [748] L127-->L127-2: Formula: (and (= v_~b0_val~0_3 v_~b0_val_t~0_3) (> v_~b0_val_t~0_3 v_~b0_val~0_4) (= v_~b0_ev~0_3 0)) InVars {~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_4} OutVars{~b0_ev~0=v_~b0_ev~0_3, ~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_3} AuxVars[] AssignedVars[~b0_val~0, ~b0_ev~0] 1584#L127-2 [580] L127-2-->L202-1: Formula: (= v_~b0_req_up~0_5 0) InVars {} OutVars{~b0_req_up~0=v_~b0_req_up~0_5} AuxVars[] AssignedVars[~b0_req_up~0] 1619#L202-1 [545] L202-1-->L142: Formula: (= 1 v_~b1_req_up~0_4) InVars {~b1_req_up~0=v_~b1_req_up~0_4} OutVars{~b1_req_up~0=v_~b1_req_up~0_4} AuxVars[] AssignedVars[] 1600#L142 [752] L142-->L142-2: Formula: (and (= v_~b1_ev~0_3 0) (< v_~b1_val~0_4 v_~b1_val_t~0_3) (= v_~b1_val~0_3 v_~b1_val_t~0_3)) InVars {~b1_val_t~0=v_~b1_val_t~0_3, ~b1_val~0=v_~b1_val~0_4} OutVars{~b1_val_t~0=v_~b1_val_t~0_3, ~b1_ev~0=v_~b1_ev~0_3, ~b1_val~0=v_~b1_val~0_3} AuxVars[] AssignedVars[~b1_val~0, ~b1_ev~0] 1591#L142-2 [521] L142-2-->L209: Formula: (= v_~b1_req_up~0_5 0) InVars {} OutVars{~b1_req_up~0=v_~b1_req_up~0_5} AuxVars[] AssignedVars[~b1_req_up~0] 1592#L209 [754] L209-->L216: Formula: (> v_~d0_req_up~0_6 1) InVars {~d0_req_up~0=v_~d0_req_up~0_6} OutVars{~d0_req_up~0=v_~d0_req_up~0_6} AuxVars[] AssignedVars[] 1610#L216 [759] L216-->L223: Formula: (> v_~d1_req_up~0_6 1) InVars {~d1_req_up~0=v_~d1_req_up~0_6} OutVars{~d1_req_up~0=v_~d1_req_up~0_6} AuxVars[] AssignedVars[] 1624#L223 [763] L223-->L230: Formula: (< 1 v_~z_req_up~0_6) InVars {~z_req_up~0=v_~z_req_up~0_6} OutVars{~z_req_up~0=v_~z_req_up~0_6} AuxVars[] AssignedVars[] 1563#L230 [767] L230-->L245-1: Formula: (and (> 1 v_~comp_m1_i~0_4) (= v_~comp_m1_st~0_5 2)) InVars {~comp_m1_i~0=v_~comp_m1_i~0_4} OutVars{~comp_m1_st~0=v_~comp_m1_st~0_5, ~comp_m1_i~0=v_~comp_m1_i~0_4} AuxVars[] AssignedVars[~comp_m1_st~0] 1564#L245-1 [769] L245-1-->L311-1: Formula: (> v_~b0_ev~0_7 0) InVars {~b0_ev~0=v_~b0_ev~0_7} OutVars{~b0_ev~0=v_~b0_ev~0_7} AuxVars[] AssignedVars[] 1582#L311-1 [628] L311-1-->L316-1: Formula: (and (= 0 v_~b1_ev~0_6) (= v_~b1_ev~0_5 1)) InVars {~b1_ev~0=v_~b1_ev~0_6} OutVars{~b1_ev~0=v_~b1_ev~0_5} AuxVars[] AssignedVars[~b1_ev~0] 1615#L316-1 [654] L316-1-->L321-1: Formula: (and (= v_~d0_ev~0_5 1) (= v_~d0_ev~0_6 0)) InVars {~d0_ev~0=v_~d0_ev~0_6} OutVars{~d0_ev~0=v_~d0_ev~0_5} AuxVars[] AssignedVars[~d0_ev~0] 1573#L321-1 [507] L321-1-->L326-1: Formula: (and (= 0 v_~d1_ev~0_6) (= v_~d1_ev~0_5 1)) InVars {~d1_ev~0=v_~d1_ev~0_6} OutVars{~d1_ev~0=v_~d1_ev~0_5} AuxVars[] AssignedVars[~d1_ev~0] 1574#L326-1 [556] L326-1-->L331-1: Formula: (and (= 0 v_~z_ev~0_6) (= v_~z_ev~0_5 1)) InVars {~z_ev~0=v_~z_ev~0_6} OutVars{~z_ev~0=v_~z_ev~0_5} AuxVars[] AssignedVars[~z_ev~0] 1633#L331-1 [583] L331-1-->L97: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_1|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 1653#L97 [591] L97-->L119: Formula: (and (= v_~b0_ev~0_11 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4 1)) InVars {~b0_ev~0=v_~b0_ev~0_11} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4, ~b0_ev~0=v_~b0_ev~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 1598#L119 [886] L119-->L380: Formula: (and (= |v_ULTIMATE.start_is_method1_triggered_#res_7| v_ULTIMATE.start_activate_threads_~tmp~1_13) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19 |v_ULTIMATE.start_is_method1_triggered_#res_7|)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_13, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_7|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_7|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 1595#L380 [615] L380-->L380-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_9) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} AuxVars[] AssignedVars[] 1596#L380-2 [618] L380-2-->L344-1: Formula: (and (= v_~b0_ev~0_15 2) (= v_~b0_ev~0_16 1)) InVars {~b0_ev~0=v_~b0_ev~0_16} OutVars{~b0_ev~0=v_~b0_ev~0_15} AuxVars[] AssignedVars[~b0_ev~0] 1601#L344-1 [791] L344-1-->L349-1: Formula: (> 1 v_~b1_ev~0_17) InVars {~b1_ev~0=v_~b1_ev~0_17} OutVars{~b1_ev~0=v_~b1_ev~0_17} AuxVars[] AssignedVars[] 1642#L349-1 [652] L349-1-->L354-1: Formula: (and (= v_~d0_ev~0_15 2) (= v_~d0_ev~0_16 1)) InVars {~d0_ev~0=v_~d0_ev~0_16} OutVars{~d0_ev~0=v_~d0_ev~0_15} AuxVars[] AssignedVars[~d0_ev~0] 1643#L354-1 [795] L354-1-->L359-1: Formula: (> 1 v_~d1_ev~0_17) InVars {~d1_ev~0=v_~d1_ev~0_17} OutVars{~d1_ev~0=v_~d1_ev~0_17} AuxVars[] AssignedVars[] 1631#L359-1 [797] L359-1-->L422-1: Formula: (> v_~z_ev~0_13 1) InVars {~z_ev~0=v_~z_ev~0_13} OutVars{~z_ev~0=v_~z_ev~0_13} AuxVars[] AssignedVars[] 1632#L422-1 54.07/20.05 [2019-03-28 12:18:50,044 INFO L796 eck$LassoCheckResult]: Loop: 1632#L422-1 [887] L422-1-->L285: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 1) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 1665#L285 [888] L285-->L258: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_13, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res] 1664#L258 [802] L258-->L265: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8 0) (> 0 v_~comp_m1_st~0_9)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_9} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8, ~comp_m1_st~0=v_~comp_m1_st~0_9} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 1637#L265 [889] L265-->L280: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___0~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 1638#L280 [890] L280-->L202-2: Formula: (and (= v_ULTIMATE.start_eval_~tmp___0~0_8 0) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 2)) InVars {ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 1616#L202-2 [800] L202-2-->L202-3: Formula: (> 1 v_~b0_req_up~0_9) InVars {~b0_req_up~0=v_~b0_req_up~0_9} OutVars{~b0_req_up~0=v_~b0_req_up~0_9} AuxVars[] AssignedVars[] 1613#L202-3 [807] L202-3-->L209-1: Formula: (> 1 v_~b1_req_up~0_9) InVars {~b1_req_up~0=v_~b1_req_up~0_9} OutVars{~b1_req_up~0=v_~b1_req_up~0_9} AuxVars[] AssignedVars[] 1603#L209-1 [810] L209-1-->L216-1: Formula: (> v_~d0_req_up~0_9 1) InVars {~d0_req_up~0=v_~d0_req_up~0_9} OutVars{~d0_req_up~0=v_~d0_req_up~0_9} AuxVars[] AssignedVars[] 1604#L216-1 [814] L216-1-->L223-1: Formula: (> v_~d1_req_up~0_9 1) InVars {~d1_req_up~0=v_~d1_req_up~0_9} OutVars{~d1_req_up~0=v_~d1_req_up~0_9} AuxVars[] AssignedVars[] 1699#L223-1 [820] L223-1-->L230-1: Formula: (< 1 v_~z_req_up~0_9) InVars {~z_req_up~0=v_~z_req_up~0_9} OutVars{~z_req_up~0=v_~z_req_up~0_9} AuxVars[] AssignedVars[] 1697#L230-1 [498] L230-1-->L311-2: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 3) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 1696#L311-2 [632] L311-2-->L311-4: Formula: (and (= v_~b0_ev~0_8 1) (= v_~b0_ev~0_9 0)) InVars {~b0_ev~0=v_~b0_ev~0_9} OutVars{~b0_ev~0=v_~b0_ev~0_8} AuxVars[] AssignedVars[~b0_ev~0] 1695#L311-4 [832] L311-4-->L316-3: Formula: (> 0 v_~b1_ev~0_10) InVars {~b1_ev~0=v_~b1_ev~0_10} OutVars{~b1_ev~0=v_~b1_ev~0_10} AuxVars[] AssignedVars[] 1694#L316-3 [838] L316-3-->L321-3: Formula: (< v_~d0_ev~0_10 0) InVars {~d0_ev~0=v_~d0_ev~0_10} OutVars{~d0_ev~0=v_~d0_ev~0_10} AuxVars[] AssignedVars[] 1693#L321-3 [662] L321-3-->L326-3: Formula: (and (= v_~d1_ev~0_8 1) (= 0 v_~d1_ev~0_9)) InVars {~d1_ev~0=v_~d1_ev~0_9} OutVars{~d1_ev~0=v_~d1_ev~0_8} AuxVars[] AssignedVars[~d1_ev~0] 1692#L326-3 [850] L326-3-->L331-3: Formula: (> v_~z_ev~0_10 0) InVars {~z_ev~0=v_~z_ev~0_10} OutVars{~z_ev~0=v_~z_ev~0_10} AuxVars[] AssignedVars[] 1691#L331-3 [570] L331-3-->L97-1: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_4|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_10, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 1690#L97-1 [588] L97-1-->L119-1: Formula: (and (= v_~b0_ev~0_13 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13 1)) InVars {~b0_ev~0=v_~b0_ev~0_13} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13, ~b0_ev~0=v_~b0_ev~0_13} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 1656#L119-1 [891] L119-1-->L380-3: Formula: (and (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20 |v_ULTIMATE.start_is_method1_triggered_#res_8|) (= |v_ULTIMATE.start_is_method1_triggered_#res_8| v_ULTIMATE.start_activate_threads_~tmp~1_14)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_14, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_8|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_8|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 1554#L380-3 [864] L380-3-->L380-5: Formula: (and (= v_~comp_m1_st~0_7 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11, ~comp_m1_st~0=v_~comp_m1_st~0_7} AuxVars[] AssignedVars[~comp_m1_st~0] 1555#L380-5 [868] L380-5-->L344-3: Formula: (< v_~b0_ev~0_20 1) InVars {~b0_ev~0=v_~b0_ev~0_20} OutVars{~b0_ev~0=v_~b0_ev~0_20} AuxVars[] AssignedVars[] 1565#L344-3 [870] L344-3-->L349-3: Formula: (< 1 v_~b1_ev~0_20) InVars {~b1_ev~0=v_~b1_ev~0_20} OutVars{~b1_ev~0=v_~b1_ev~0_20} AuxVars[] AssignedVars[] 1618#L349-3 [656] L349-3-->L354-3: Formula: (and (= v_~d0_ev~0_18 2) (= v_~d0_ev~0_19 1)) InVars {~d0_ev~0=v_~d0_ev~0_19} OutVars{~d0_ev~0=v_~d0_ev~0_18} AuxVars[] AssignedVars[~d0_ev~0] 1580#L354-3 [513] L354-3-->L359-3: Formula: (and (= 1 v_~d1_ev~0_19) (= v_~d1_ev~0_18 2)) InVars {~d1_ev~0=v_~d1_ev~0_19} OutVars{~d1_ev~0=v_~d1_ev~0_18} AuxVars[] AssignedVars[~d1_ev~0] 1581#L359-3 [531] L359-3-->L364-3: Formula: (and (= v_~z_ev~0_15 1) (= v_~z_ev~0_14 2)) InVars {~z_ev~0=v_~z_ev~0_15} OutVars{~z_ev~0=v_~z_ev~0_14} AuxVars[] AssignedVars[~z_ev~0] 1602#L364-3 [568] L364-3-->L258-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_5, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_2|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_#res] 1640#L258-1 [666] L258-1-->L265-1: Formula: (and (= v_~comp_m1_st~0_10 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9 1)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_10} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9, ~comp_m1_st~0=v_~comp_m1_st~0_10} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 1635#L265-1 [892] L265-1-->L397: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_stop_simulation_~tmp~2_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_4|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_~tmp~2] 1636#L397 [880] L397-->L404: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_4 0) (< 0 v_ULTIMATE.start_stop_simulation_~tmp~2_5)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_4, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 1639#L404 [897] L404-->L422-1: Formula: (and (= 0 v_ULTIMATE.start_start_simulation_~tmp~3_9) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= |v_ULTIMATE.start_stop_simulation_#res_5| v_ULTIMATE.start_start_simulation_~tmp~3_9)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_~tmp~3] 1632#L422-1 54.07/20.05 [2019-03-28 12:18:50,044 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.05 [2019-03-28 12:18:50,044 INFO L82 PathProgramCache]: Analyzing trace with hash -1615066075, now seen corresponding path program 1 times 54.07/20.05 [2019-03-28 12:18:50,044 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.05 [2019-03-28 12:18:50,044 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.05 [2019-03-28 12:18:50,045 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:50,045 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:50,046 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:50,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.05 [2019-03-28 12:18:50,061 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.05 [2019-03-28 12:18:50,061 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.05 [2019-03-28 12:18:50,061 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 54.07/20.05 [2019-03-28 12:18:50,062 INFO L799 eck$LassoCheckResult]: stem already infeasible 54.07/20.05 [2019-03-28 12:18:50,062 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.05 [2019-03-28 12:18:50,062 INFO L82 PathProgramCache]: Analyzing trace with hash -352160814, now seen corresponding path program 3 times 54.07/20.05 [2019-03-28 12:18:50,062 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.05 [2019-03-28 12:18:50,062 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.05 [2019-03-28 12:18:50,063 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:50,063 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:50,063 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:50,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.05 [2019-03-28 12:18:50,085 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.05 [2019-03-28 12:18:50,086 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.05 [2019-03-28 12:18:50,086 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 54.07/20.05 [2019-03-28 12:18:50,086 INFO L811 eck$LassoCheckResult]: loop already infeasible 54.07/20.05 [2019-03-28 12:18:50,086 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 54.07/20.05 [2019-03-28 12:18:50,086 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 54.07/20.05 [2019-03-28 12:18:50,087 INFO L87 Difference]: Start difference. First operand 168 states and 408 transitions. cyclomatic complexity: 241 Second operand 3 states. 54.07/20.05 [2019-03-28 12:18:50,201 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 54.07/20.05 [2019-03-28 12:18:50,202 INFO L93 Difference]: Finished difference Result 90 states and 211 transitions. 54.07/20.05 [2019-03-28 12:18:50,202 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 54.07/20.05 [2019-03-28 12:18:50,202 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 90 states and 211 transitions. 54.07/20.05 [2019-03-28 12:18:50,203 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 56 54.07/20.05 [2019-03-28 12:18:50,204 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 90 states to 90 states and 211 transitions. 54.07/20.05 [2019-03-28 12:18:50,204 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 90 54.07/20.05 [2019-03-28 12:18:50,205 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 90 54.07/20.05 [2019-03-28 12:18:50,205 INFO L73 IsDeterministic]: Start isDeterministic. Operand 90 states and 211 transitions. 54.07/20.05 [2019-03-28 12:18:50,205 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 54.07/20.05 [2019-03-28 12:18:50,205 INFO L706 BuchiCegarLoop]: Abstraction has 90 states and 211 transitions. 54.07/20.05 [2019-03-28 12:18:50,205 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90 states and 211 transitions. 54.07/20.05 [2019-03-28 12:18:50,207 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90 to 90. 54.07/20.05 [2019-03-28 12:18:50,208 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 90 states. 54.07/20.05 [2019-03-28 12:18:50,208 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90 states to 90 states and 211 transitions. 54.07/20.05 [2019-03-28 12:18:50,208 INFO L729 BuchiCegarLoop]: Abstraction has 90 states and 211 transitions. 54.07/20.05 [2019-03-28 12:18:50,208 INFO L609 BuchiCegarLoop]: Abstraction has 90 states and 211 transitions. 54.07/20.05 [2019-03-28 12:18:50,209 INFO L442 BuchiCegarLoop]: ======== Iteration 9============ 54.07/20.05 [2019-03-28 12:18:50,209 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 90 states and 211 transitions. 54.07/20.05 [2019-03-28 12:18:50,209 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 56 54.07/20.05 [2019-03-28 12:18:50,210 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 54.07/20.05 [2019-03-28 12:18:50,210 INFO L119 BuchiIsEmpty]: Starting construction of run 54.07/20.05 [2019-03-28 12:18:50,211 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.05 [2019-03-28 12:18:50,211 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.05 [2019-03-28 12:18:50,212 INFO L794 eck$LassoCheckResult]: Stem: 1884#ULTIMATE.startENTRY [885] ULTIMATE.startENTRY-->L202: Formula: (and (= v_~d0_ev~0_23 2) (= 0 v_~z_val~0_13) (= 2 v_~b1_ev~0_23) (= v_~d0_val_t~0_9 1) (= v_~b0_val~0_13 0) (= 1 v_~b1_val_t~0_9) (= 1 v_~d1_req_up~0_12) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_9 0) (= 2 v_~d1_ev~0_23) (= v_~b1_val~0_13 0) (= v_~b0_val_t~0_9 1) (= v_~b0_req_up~0_12 1) (= 0 v_~comp_m1_i~0_7) (= v_~d0_req_up~0_12 1) (= v_~comp_m1_st~0_15 0) (= v_~b0_ev~0_23 2) (= 1 v_~d1_val_t~0_9) (= v_~z_req_up~0_12 0) (= v_~z_val_t~0_10 0) (= 0 v_~d1_val~0_13) (= v_~z_ev~0_19 2) (= v_~b1_req_up~0_12 1) (= 0 v_~d0_val~0_13)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_4|, ~b1_val~0=v_~b1_val~0_13, ~b0_val~0=v_~b0_val~0_13, ~d0_req_up~0=v_~d0_req_up~0_12, ~d0_val~0=v_~d0_val~0_13, ~d1_val_t~0=v_~d1_val_t~0_9, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_9, ~d1_ev~0=v_~d1_ev~0_23, ~d1_val~0=v_~d1_val~0_13, ~b0_req_up~0=v_~b0_req_up~0_12, ~z_ev~0=v_~z_ev~0_19, ~b1_val_t~0=v_~b1_val_t~0_9, ~b1_ev~0=v_~b1_ev~0_23, ULTIMATE.start_main_~__retres1~2=v_ULTIMATE.start_main_~__retres1~2_6, ~z_val~0=v_~z_val~0_13, ~d1_req_up~0=v_~d1_req_up~0_12, ~z_val_t~0=v_~z_val_t~0_10, ~b0_val_t~0=v_~b0_val_t~0_9, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~z_req_up~0=v_~z_req_up~0_12, ~b1_req_up~0=v_~b1_req_up~0_12, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~d0_ev~0=v_~d0_ev~0_23, ~b0_ev~0=v_~b0_ev~0_23, ~d0_val_t~0=v_~d0_val_t~0_9, ~comp_m1_st~0=v_~comp_m1_st~0_15, ~comp_m1_i~0=v_~comp_m1_i~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ~b1_val~0, ~b0_val~0, ~d0_req_up~0, ~d0_val~0, ~d1_val_t~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~d1_ev~0, ~d1_val~0, ~b0_req_up~0, ~z_ev~0, ~b1_val_t~0, ~b1_ev~0, ULTIMATE.start_main_~__retres1~2, ~z_val~0, ~d1_req_up~0, ~z_val_t~0, ~b0_val_t~0, ULTIMATE.start_start_simulation_~tmp~3, ~z_req_up~0, ~b1_req_up~0, ULTIMATE.start_main_#res, ~d0_ev~0, ~b0_ev~0, ~d0_val_t~0, ~comp_m1_st~0, ~comp_m1_i~0] 1885#L202 [566] L202-->L127: Formula: (= 1 v_~b0_req_up~0_4) InVars {~b0_req_up~0=v_~b0_req_up~0_4} OutVars{~b0_req_up~0=v_~b0_req_up~0_4} AuxVars[] AssignedVars[] 1848#L127 [748] L127-->L127-2: Formula: (and (= v_~b0_val~0_3 v_~b0_val_t~0_3) (> v_~b0_val_t~0_3 v_~b0_val~0_4) (= v_~b0_ev~0_3 0)) InVars {~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_4} OutVars{~b0_ev~0=v_~b0_ev~0_3, ~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_3} AuxVars[] AssignedVars[~b0_val~0, ~b0_ev~0] 1849#L127-2 [580] L127-2-->L202-1: Formula: (= v_~b0_req_up~0_5 0) InVars {} OutVars{~b0_req_up~0=v_~b0_req_up~0_5} AuxVars[] AssignedVars[~b0_req_up~0] 1880#L202-1 [545] L202-1-->L142: Formula: (= 1 v_~b1_req_up~0_4) InVars {~b1_req_up~0=v_~b1_req_up~0_4} OutVars{~b1_req_up~0=v_~b1_req_up~0_4} AuxVars[] AssignedVars[] 1865#L142 [752] L142-->L142-2: Formula: (and (= v_~b1_ev~0_3 0) (< v_~b1_val~0_4 v_~b1_val_t~0_3) (= v_~b1_val~0_3 v_~b1_val_t~0_3)) InVars {~b1_val_t~0=v_~b1_val_t~0_3, ~b1_val~0=v_~b1_val~0_4} OutVars{~b1_val_t~0=v_~b1_val_t~0_3, ~b1_ev~0=v_~b1_ev~0_3, ~b1_val~0=v_~b1_val~0_3} AuxVars[] AssignedVars[~b1_val~0, ~b1_ev~0] 1858#L142-2 [521] L142-2-->L209: Formula: (= v_~b1_req_up~0_5 0) InVars {} OutVars{~b1_req_up~0=v_~b1_req_up~0_5} AuxVars[] AssignedVars[~b1_req_up~0] 1859#L209 [624] L209-->L157: Formula: (= v_~d0_req_up~0_4 1) InVars {~d0_req_up~0=v_~d0_req_up~0_4} OutVars{~d0_req_up~0=v_~d0_req_up~0_4} AuxVars[] AssignedVars[] 1835#L157 [604] L157-->L157-2: Formula: (= v_~d0_val_t~0_4 v_~d0_val~0_5) InVars {~d0_val~0=v_~d0_val~0_5, ~d0_val_t~0=v_~d0_val_t~0_4} OutVars{~d0_val~0=v_~d0_val~0_5, ~d0_val_t~0=v_~d0_val_t~0_4} AuxVars[] AssignedVars[] 1826#L157-2 [600] L157-2-->L216: Formula: (= v_~d0_req_up~0_5 0) InVars {} OutVars{~d0_req_up~0=v_~d0_req_up~0_5} AuxVars[] AssignedVars[~d0_req_up~0] 1827#L216 [759] L216-->L223: Formula: (> v_~d1_req_up~0_6 1) InVars {~d1_req_up~0=v_~d1_req_up~0_6} OutVars{~d1_req_up~0=v_~d1_req_up~0_6} AuxVars[] AssignedVars[] 1882#L223 [763] L223-->L230: Formula: (< 1 v_~z_req_up~0_6) InVars {~z_req_up~0=v_~z_req_up~0_6} OutVars{~z_req_up~0=v_~z_req_up~0_6} AuxVars[] AssignedVars[] 1828#L230 [767] L230-->L245-1: Formula: (and (> 1 v_~comp_m1_i~0_4) (= v_~comp_m1_st~0_5 2)) InVars {~comp_m1_i~0=v_~comp_m1_i~0_4} OutVars{~comp_m1_st~0=v_~comp_m1_st~0_5, ~comp_m1_i~0=v_~comp_m1_i~0_4} AuxVars[] AssignedVars[~comp_m1_st~0] 1829#L245-1 [769] L245-1-->L311-1: Formula: (> v_~b0_ev~0_7 0) InVars {~b0_ev~0=v_~b0_ev~0_7} OutVars{~b0_ev~0=v_~b0_ev~0_7} AuxVars[] AssignedVars[] 1847#L311-1 [628] L311-1-->L316-1: Formula: (and (= 0 v_~b1_ev~0_6) (= v_~b1_ev~0_5 1)) InVars {~b1_ev~0=v_~b1_ev~0_6} OutVars{~b1_ev~0=v_~b1_ev~0_5} AuxVars[] AssignedVars[~b1_ev~0] 1876#L316-1 [654] L316-1-->L321-1: Formula: (and (= v_~d0_ev~0_5 1) (= v_~d0_ev~0_6 0)) InVars {~d0_ev~0=v_~d0_ev~0_6} OutVars{~d0_ev~0=v_~d0_ev~0_5} AuxVars[] AssignedVars[~d0_ev~0] 1838#L321-1 [507] L321-1-->L326-1: Formula: (and (= 0 v_~d1_ev~0_6) (= v_~d1_ev~0_5 1)) InVars {~d1_ev~0=v_~d1_ev~0_6} OutVars{~d1_ev~0=v_~d1_ev~0_5} AuxVars[] AssignedVars[~d1_ev~0] 1839#L326-1 [556] L326-1-->L331-1: Formula: (and (= 0 v_~z_ev~0_6) (= v_~z_ev~0_5 1)) InVars {~z_ev~0=v_~z_ev~0_6} OutVars{~z_ev~0=v_~z_ev~0_5} AuxVars[] AssignedVars[~z_ev~0] 1891#L331-1 [583] L331-1-->L97: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_1|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 1904#L97 [591] L97-->L119: Formula: (and (= v_~b0_ev~0_11 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4 1)) InVars {~b0_ev~0=v_~b0_ev~0_11} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4, ~b0_ev~0=v_~b0_ev~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 1863#L119 [886] L119-->L380: Formula: (and (= |v_ULTIMATE.start_is_method1_triggered_#res_7| v_ULTIMATE.start_activate_threads_~tmp~1_13) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19 |v_ULTIMATE.start_is_method1_triggered_#res_7|)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_13, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_7|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_7|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 1860#L380 [615] L380-->L380-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_9) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} AuxVars[] AssignedVars[] 1861#L380-2 [618] L380-2-->L344-1: Formula: (and (= v_~b0_ev~0_15 2) (= v_~b0_ev~0_16 1)) InVars {~b0_ev~0=v_~b0_ev~0_16} OutVars{~b0_ev~0=v_~b0_ev~0_15} AuxVars[] AssignedVars[~b0_ev~0] 1866#L344-1 [791] L344-1-->L349-1: Formula: (> 1 v_~b1_ev~0_17) InVars {~b1_ev~0=v_~b1_ev~0_17} OutVars{~b1_ev~0=v_~b1_ev~0_17} AuxVars[] AssignedVars[] 1874#L349-1 [652] L349-1-->L354-1: Formula: (and (= v_~d0_ev~0_15 2) (= v_~d0_ev~0_16 1)) InVars {~d0_ev~0=v_~d0_ev~0_16} OutVars{~d0_ev~0=v_~d0_ev~0_15} AuxVars[] AssignedVars[~d0_ev~0] 1833#L354-1 [795] L354-1-->L359-1: Formula: (> 1 v_~d1_ev~0_17) InVars {~d1_ev~0=v_~d1_ev~0_17} OutVars{~d1_ev~0=v_~d1_ev~0_17} AuxVars[] AssignedVars[] 1834#L359-1 [797] L359-1-->L422-1: Formula: (> v_~z_ev~0_13 1) InVars {~z_ev~0=v_~z_ev~0_13} OutVars{~z_ev~0=v_~z_ev~0_13} AuxVars[] AssignedVars[] 1890#L422-1 54.07/20.05 [2019-03-28 12:18:50,212 INFO L796 eck$LassoCheckResult]: Loop: 1890#L422-1 [887] L422-1-->L285: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 1) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 1836#L285 [888] L285-->L258: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_13, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res] 1837#L258 [802] L258-->L265: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8 0) (> 0 v_~comp_m1_st~0_9)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_9} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8, ~comp_m1_st~0=v_~comp_m1_st~0_9} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 1895#L265 [889] L265-->L280: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___0~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 1896#L280 [890] L280-->L202-2: Formula: (and (= v_ULTIMATE.start_eval_~tmp___0~0_8 0) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 2)) InVars {ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 1877#L202-2 [800] L202-2-->L202-3: Formula: (> 1 v_~b0_req_up~0_9) InVars {~b0_req_up~0=v_~b0_req_up~0_9} OutVars{~b0_req_up~0=v_~b0_req_up~0_9} AuxVars[] AssignedVars[] 1875#L202-3 [807] L202-3-->L209-1: Formula: (> 1 v_~b1_req_up~0_9) InVars {~b1_req_up~0=v_~b1_req_up~0_9} OutVars{~b1_req_up~0=v_~b1_req_up~0_9} AuxVars[] AssignedVars[] 1870#L209-1 [811] L209-1-->L216-1: Formula: (< v_~d0_req_up~0_9 1) InVars {~d0_req_up~0=v_~d0_req_up~0_9} OutVars{~d0_req_up~0=v_~d0_req_up~0_9} AuxVars[] AssignedVars[] 1864#L216-1 [814] L216-1-->L223-1: Formula: (> v_~d1_req_up~0_9 1) InVars {~d1_req_up~0=v_~d1_req_up~0_9} OutVars{~d1_req_up~0=v_~d1_req_up~0_9} AuxVars[] AssignedVars[] 1832#L223-1 [820] L223-1-->L230-1: Formula: (< 1 v_~z_req_up~0_9) InVars {~z_req_up~0=v_~z_req_up~0_9} OutVars{~z_req_up~0=v_~z_req_up~0_9} AuxVars[] AssignedVars[] 1821#L230-1 [498] L230-1-->L311-2: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 3) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 1822#L311-2 [632] L311-2-->L311-4: Formula: (and (= v_~b0_ev~0_8 1) (= v_~b0_ev~0_9 0)) InVars {~b0_ev~0=v_~b0_ev~0_9} OutVars{~b0_ev~0=v_~b0_ev~0_8} AuxVars[] AssignedVars[~b0_ev~0] 1850#L311-4 [832] L311-4-->L316-3: Formula: (> 0 v_~b1_ev~0_10) InVars {~b1_ev~0=v_~b1_ev~0_10} OutVars{~b1_ev~0=v_~b1_ev~0_10} AuxVars[] AssignedVars[] 1851#L316-3 [838] L316-3-->L321-3: Formula: (< v_~d0_ev~0_10 0) InVars {~d0_ev~0=v_~d0_ev~0_10} OutVars{~d0_ev~0=v_~d0_ev~0_10} AuxVars[] AssignedVars[] 1892#L321-3 [662] L321-3-->L326-3: Formula: (and (= v_~d1_ev~0_8 1) (= 0 v_~d1_ev~0_9)) InVars {~d1_ev~0=v_~d1_ev~0_9} OutVars{~d1_ev~0=v_~d1_ev~0_8} AuxVars[] AssignedVars[~d1_ev~0] 1868#L326-3 [850] L326-3-->L331-3: Formula: (> v_~z_ev~0_10 0) InVars {~z_ev~0=v_~z_ev~0_10} OutVars{~z_ev~0=v_~z_ev~0_10} AuxVars[] AssignedVars[] 1869#L331-3 [570] L331-3-->L97-1: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_4|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_10, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 1899#L97-1 [588] L97-1-->L119-1: Formula: (and (= v_~b0_ev~0_13 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13 1)) InVars {~b0_ev~0=v_~b0_ev~0_13} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13, ~b0_ev~0=v_~b0_ev~0_13} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 1857#L119-1 [891] L119-1-->L380-3: Formula: (and (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20 |v_ULTIMATE.start_is_method1_triggered_#res_8|) (= |v_ULTIMATE.start_is_method1_triggered_#res_8| v_ULTIMATE.start_activate_threads_~tmp~1_14)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_14, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_8|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_8|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 1817#L380-3 [864] L380-3-->L380-5: Formula: (and (= v_~comp_m1_st~0_7 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11, ~comp_m1_st~0=v_~comp_m1_st~0_7} AuxVars[] AssignedVars[~comp_m1_st~0] 1818#L380-5 [868] L380-5-->L344-3: Formula: (< v_~b0_ev~0_20 1) InVars {~b0_ev~0=v_~b0_ev~0_20} OutVars{~b0_ev~0=v_~b0_ev~0_20} AuxVars[] AssignedVars[] 1830#L344-3 [870] L344-3-->L349-3: Formula: (< 1 v_~b1_ev~0_20) InVars {~b1_ev~0=v_~b1_ev~0_20} OutVars{~b1_ev~0=v_~b1_ev~0_20} AuxVars[] AssignedVars[] 1879#L349-3 [656] L349-3-->L354-3: Formula: (and (= v_~d0_ev~0_18 2) (= v_~d0_ev~0_19 1)) InVars {~d0_ev~0=v_~d0_ev~0_19} OutVars{~d0_ev~0=v_~d0_ev~0_18} AuxVars[] AssignedVars[~d0_ev~0] 1845#L354-3 [513] L354-3-->L359-3: Formula: (and (= 1 v_~d1_ev~0_19) (= v_~d1_ev~0_18 2)) InVars {~d1_ev~0=v_~d1_ev~0_19} OutVars{~d1_ev~0=v_~d1_ev~0_18} AuxVars[] AssignedVars[~d1_ev~0] 1846#L359-3 [531] L359-3-->L364-3: Formula: (and (= v_~z_ev~0_15 1) (= v_~z_ev~0_14 2)) InVars {~z_ev~0=v_~z_ev~0_15} OutVars{~z_ev~0=v_~z_ev~0_14} AuxVars[] AssignedVars[~z_ev~0] 1867#L364-3 [568] L364-3-->L258-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_5, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_2|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_#res] 1898#L258-1 [666] L258-1-->L265-1: Formula: (and (= v_~comp_m1_st~0_10 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9 1)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_10} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9, ~comp_m1_st~0=v_~comp_m1_st~0_10} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 1893#L265-1 [892] L265-1-->L397: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_stop_simulation_~tmp~2_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_4|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_~tmp~2] 1894#L397 [880] L397-->L404: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_4 0) (< 0 v_ULTIMATE.start_stop_simulation_~tmp~2_5)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_4, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 1897#L404 [897] L404-->L422-1: Formula: (and (= 0 v_ULTIMATE.start_start_simulation_~tmp~3_9) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= |v_ULTIMATE.start_stop_simulation_#res_5| v_ULTIMATE.start_start_simulation_~tmp~3_9)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_~tmp~3] 1890#L422-1 54.07/20.05 [2019-03-28 12:18:50,213 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.05 [2019-03-28 12:18:50,213 INFO L82 PathProgramCache]: Analyzing trace with hash -798269333, now seen corresponding path program 1 times 54.07/20.05 [2019-03-28 12:18:50,213 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.05 [2019-03-28 12:18:50,213 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.05 [2019-03-28 12:18:50,214 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:50,214 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:50,214 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:50,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.05 [2019-03-28 12:18:50,231 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.05 [2019-03-28 12:18:50,231 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.05 [2019-03-28 12:18:50,231 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 54.07/20.05 [2019-03-28 12:18:50,232 INFO L799 eck$LassoCheckResult]: stem already infeasible 54.07/20.05 [2019-03-28 12:18:50,232 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.05 [2019-03-28 12:18:50,232 INFO L82 PathProgramCache]: Analyzing trace with hash 892603667, now seen corresponding path program 1 times 54.07/20.05 [2019-03-28 12:18:50,232 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.05 [2019-03-28 12:18:50,232 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.05 [2019-03-28 12:18:50,233 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:50,233 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:50,233 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:50,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.05 [2019-03-28 12:18:50,250 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.05 [2019-03-28 12:18:50,251 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.05 [2019-03-28 12:18:50,251 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 54.07/20.05 [2019-03-28 12:18:50,251 INFO L811 eck$LassoCheckResult]: loop already infeasible 54.07/20.05 [2019-03-28 12:18:50,251 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 54.07/20.05 [2019-03-28 12:18:50,252 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 54.07/20.05 [2019-03-28 12:18:50,252 INFO L87 Difference]: Start difference. First operand 90 states and 211 transitions. cyclomatic complexity: 122 Second operand 3 states. 54.07/20.05 [2019-03-28 12:18:50,438 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 54.07/20.05 [2019-03-28 12:18:50,439 INFO L93 Difference]: Finished difference Result 90 states and 209 transitions. 54.07/20.05 [2019-03-28 12:18:50,439 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 54.07/20.05 [2019-03-28 12:18:50,439 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 90 states and 209 transitions. 54.07/20.05 [2019-03-28 12:18:50,440 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 56 54.07/20.05 [2019-03-28 12:18:50,441 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 90 states to 90 states and 209 transitions. 54.07/20.05 [2019-03-28 12:18:50,441 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 90 54.07/20.05 [2019-03-28 12:18:50,442 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 90 54.07/20.05 [2019-03-28 12:18:50,442 INFO L73 IsDeterministic]: Start isDeterministic. Operand 90 states and 209 transitions. 54.07/20.05 [2019-03-28 12:18:50,442 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 54.07/20.05 [2019-03-28 12:18:50,442 INFO L706 BuchiCegarLoop]: Abstraction has 90 states and 209 transitions. 54.07/20.05 [2019-03-28 12:18:50,443 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90 states and 209 transitions. 54.07/20.05 [2019-03-28 12:18:50,444 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90 to 90. 54.07/20.05 [2019-03-28 12:18:50,444 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 90 states. 54.07/20.05 [2019-03-28 12:18:50,445 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90 states to 90 states and 209 transitions. 54.07/20.05 [2019-03-28 12:18:50,445 INFO L729 BuchiCegarLoop]: Abstraction has 90 states and 209 transitions. 54.07/20.05 [2019-03-28 12:18:50,445 INFO L609 BuchiCegarLoop]: Abstraction has 90 states and 209 transitions. 54.07/20.05 [2019-03-28 12:18:50,445 INFO L442 BuchiCegarLoop]: ======== Iteration 10============ 54.07/20.05 [2019-03-28 12:18:50,446 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 90 states and 209 transitions. 54.07/20.05 [2019-03-28 12:18:50,446 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 56 54.07/20.05 [2019-03-28 12:18:50,446 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 54.07/20.05 [2019-03-28 12:18:50,447 INFO L119 BuchiIsEmpty]: Starting construction of run 54.07/20.05 [2019-03-28 12:18:50,447 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.05 [2019-03-28 12:18:50,447 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.05 [2019-03-28 12:18:50,448 INFO L794 eck$LassoCheckResult]: Stem: 2071#ULTIMATE.startENTRY [885] ULTIMATE.startENTRY-->L202: Formula: (and (= v_~d0_ev~0_23 2) (= 0 v_~z_val~0_13) (= 2 v_~b1_ev~0_23) (= v_~d0_val_t~0_9 1) (= v_~b0_val~0_13 0) (= 1 v_~b1_val_t~0_9) (= 1 v_~d1_req_up~0_12) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_9 0) (= 2 v_~d1_ev~0_23) (= v_~b1_val~0_13 0) (= v_~b0_val_t~0_9 1) (= v_~b0_req_up~0_12 1) (= 0 v_~comp_m1_i~0_7) (= v_~d0_req_up~0_12 1) (= v_~comp_m1_st~0_15 0) (= v_~b0_ev~0_23 2) (= 1 v_~d1_val_t~0_9) (= v_~z_req_up~0_12 0) (= v_~z_val_t~0_10 0) (= 0 v_~d1_val~0_13) (= v_~z_ev~0_19 2) (= v_~b1_req_up~0_12 1) (= 0 v_~d0_val~0_13)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_4|, ~b1_val~0=v_~b1_val~0_13, ~b0_val~0=v_~b0_val~0_13, ~d0_req_up~0=v_~d0_req_up~0_12, ~d0_val~0=v_~d0_val~0_13, ~d1_val_t~0=v_~d1_val_t~0_9, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_9, ~d1_ev~0=v_~d1_ev~0_23, ~d1_val~0=v_~d1_val~0_13, ~b0_req_up~0=v_~b0_req_up~0_12, ~z_ev~0=v_~z_ev~0_19, ~b1_val_t~0=v_~b1_val_t~0_9, ~b1_ev~0=v_~b1_ev~0_23, ULTIMATE.start_main_~__retres1~2=v_ULTIMATE.start_main_~__retres1~2_6, ~z_val~0=v_~z_val~0_13, ~d1_req_up~0=v_~d1_req_up~0_12, ~z_val_t~0=v_~z_val_t~0_10, ~b0_val_t~0=v_~b0_val_t~0_9, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~z_req_up~0=v_~z_req_up~0_12, ~b1_req_up~0=v_~b1_req_up~0_12, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~d0_ev~0=v_~d0_ev~0_23, ~b0_ev~0=v_~b0_ev~0_23, ~d0_val_t~0=v_~d0_val_t~0_9, ~comp_m1_st~0=v_~comp_m1_st~0_15, ~comp_m1_i~0=v_~comp_m1_i~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ~b1_val~0, ~b0_val~0, ~d0_req_up~0, ~d0_val~0, ~d1_val_t~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~d1_ev~0, ~d1_val~0, ~b0_req_up~0, ~z_ev~0, ~b1_val_t~0, ~b1_ev~0, ULTIMATE.start_main_~__retres1~2, ~z_val~0, ~d1_req_up~0, ~z_val_t~0, ~b0_val_t~0, ULTIMATE.start_start_simulation_~tmp~3, ~z_req_up~0, ~b1_req_up~0, ULTIMATE.start_main_#res, ~d0_ev~0, ~b0_ev~0, ~d0_val_t~0, ~comp_m1_st~0, ~comp_m1_i~0] 2072#L202 [566] L202-->L127: Formula: (= 1 v_~b0_req_up~0_4) InVars {~b0_req_up~0=v_~b0_req_up~0_4} OutVars{~b0_req_up~0=v_~b0_req_up~0_4} AuxVars[] AssignedVars[] 2035#L127 [748] L127-->L127-2: Formula: (and (= v_~b0_val~0_3 v_~b0_val_t~0_3) (> v_~b0_val_t~0_3 v_~b0_val~0_4) (= v_~b0_ev~0_3 0)) InVars {~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_4} OutVars{~b0_ev~0=v_~b0_ev~0_3, ~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_3} AuxVars[] AssignedVars[~b0_val~0, ~b0_ev~0] 2036#L127-2 [580] L127-2-->L202-1: Formula: (= v_~b0_req_up~0_5 0) InVars {} OutVars{~b0_req_up~0=v_~b0_req_up~0_5} AuxVars[] AssignedVars[~b0_req_up~0] 2067#L202-1 [545] L202-1-->L142: Formula: (= 1 v_~b1_req_up~0_4) InVars {~b1_req_up~0=v_~b1_req_up~0_4} OutVars{~b1_req_up~0=v_~b1_req_up~0_4} AuxVars[] AssignedVars[] 2052#L142 [752] L142-->L142-2: Formula: (and (= v_~b1_ev~0_3 0) (< v_~b1_val~0_4 v_~b1_val_t~0_3) (= v_~b1_val~0_3 v_~b1_val_t~0_3)) InVars {~b1_val_t~0=v_~b1_val_t~0_3, ~b1_val~0=v_~b1_val~0_4} OutVars{~b1_val_t~0=v_~b1_val_t~0_3, ~b1_ev~0=v_~b1_ev~0_3, ~b1_val~0=v_~b1_val~0_3} AuxVars[] AssignedVars[~b1_val~0, ~b1_ev~0] 2043#L142-2 [521] L142-2-->L209: Formula: (= v_~b1_req_up~0_5 0) InVars {} OutVars{~b1_req_up~0=v_~b1_req_up~0_5} AuxVars[] AssignedVars[~b1_req_up~0] 2044#L209 [624] L209-->L157: Formula: (= v_~d0_req_up~0_4 1) InVars {~d0_req_up~0=v_~d0_req_up~0_4} OutVars{~d0_req_up~0=v_~d0_req_up~0_4} AuxVars[] AssignedVars[] 2022#L157 [757] L157-->L157-2: Formula: (and (> v_~d0_val_t~0_3 v_~d0_val~0_4) (= v_~d0_val~0_3 v_~d0_val_t~0_3) (= v_~d0_ev~0_3 0)) InVars {~d0_val~0=v_~d0_val~0_4, ~d0_val_t~0=v_~d0_val_t~0_3} OutVars{~d0_ev~0=v_~d0_ev~0_3, ~d0_val~0=v_~d0_val~0_3, ~d0_val_t~0=v_~d0_val_t~0_3} AuxVars[] AssignedVars[~d0_ev~0, ~d0_val~0] 2013#L157-2 [600] L157-2-->L216: Formula: (= v_~d0_req_up~0_5 0) InVars {} OutVars{~d0_req_up~0=v_~d0_req_up~0_5} AuxVars[] AssignedVars[~d0_req_up~0] 2014#L216 [759] L216-->L223: Formula: (> v_~d1_req_up~0_6 1) InVars {~d1_req_up~0=v_~d1_req_up~0_6} OutVars{~d1_req_up~0=v_~d1_req_up~0_6} AuxVars[] AssignedVars[] 2069#L223 [763] L223-->L230: Formula: (< 1 v_~z_req_up~0_6) InVars {~z_req_up~0=v_~z_req_up~0_6} OutVars{~z_req_up~0=v_~z_req_up~0_6} AuxVars[] AssignedVars[] 2015#L230 [767] L230-->L245-1: Formula: (and (> 1 v_~comp_m1_i~0_4) (= v_~comp_m1_st~0_5 2)) InVars {~comp_m1_i~0=v_~comp_m1_i~0_4} OutVars{~comp_m1_st~0=v_~comp_m1_st~0_5, ~comp_m1_i~0=v_~comp_m1_i~0_4} AuxVars[] AssignedVars[~comp_m1_st~0] 2016#L245-1 [769] L245-1-->L311-1: Formula: (> v_~b0_ev~0_7 0) InVars {~b0_ev~0=v_~b0_ev~0_7} OutVars{~b0_ev~0=v_~b0_ev~0_7} AuxVars[] AssignedVars[] 2032#L311-1 [628] L311-1-->L316-1: Formula: (and (= 0 v_~b1_ev~0_6) (= v_~b1_ev~0_5 1)) InVars {~b1_ev~0=v_~b1_ev~0_6} OutVars{~b1_ev~0=v_~b1_ev~0_5} AuxVars[] AssignedVars[~b1_ev~0] 2063#L316-1 [654] L316-1-->L321-1: Formula: (and (= v_~d0_ev~0_5 1) (= v_~d0_ev~0_6 0)) InVars {~d0_ev~0=v_~d0_ev~0_6} OutVars{~d0_ev~0=v_~d0_ev~0_5} AuxVars[] AssignedVars[~d0_ev~0] 2025#L321-1 [507] L321-1-->L326-1: Formula: (and (= 0 v_~d1_ev~0_6) (= v_~d1_ev~0_5 1)) InVars {~d1_ev~0=v_~d1_ev~0_6} OutVars{~d1_ev~0=v_~d1_ev~0_5} AuxVars[] AssignedVars[~d1_ev~0] 2026#L326-1 [556] L326-1-->L331-1: Formula: (and (= 0 v_~z_ev~0_6) (= v_~z_ev~0_5 1)) InVars {~z_ev~0=v_~z_ev~0_6} OutVars{~z_ev~0=v_~z_ev~0_5} AuxVars[] AssignedVars[~z_ev~0] 2078#L331-1 [583] L331-1-->L97: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_1|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 2091#L97 [591] L97-->L119: Formula: (and (= v_~b0_ev~0_11 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4 1)) InVars {~b0_ev~0=v_~b0_ev~0_11} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4, ~b0_ev~0=v_~b0_ev~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 2050#L119 [886] L119-->L380: Formula: (and (= |v_ULTIMATE.start_is_method1_triggered_#res_7| v_ULTIMATE.start_activate_threads_~tmp~1_13) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19 |v_ULTIMATE.start_is_method1_triggered_#res_7|)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_13, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_7|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_7|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 2047#L380 [615] L380-->L380-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_9) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} AuxVars[] AssignedVars[] 2048#L380-2 [618] L380-2-->L344-1: Formula: (and (= v_~b0_ev~0_15 2) (= v_~b0_ev~0_16 1)) InVars {~b0_ev~0=v_~b0_ev~0_16} OutVars{~b0_ev~0=v_~b0_ev~0_15} AuxVars[] AssignedVars[~b0_ev~0] 2053#L344-1 [791] L344-1-->L349-1: Formula: (> 1 v_~b1_ev~0_17) InVars {~b1_ev~0=v_~b1_ev~0_17} OutVars{~b1_ev~0=v_~b1_ev~0_17} AuxVars[] AssignedVars[] 2061#L349-1 [652] L349-1-->L354-1: Formula: (and (= v_~d0_ev~0_15 2) (= v_~d0_ev~0_16 1)) InVars {~d0_ev~0=v_~d0_ev~0_16} OutVars{~d0_ev~0=v_~d0_ev~0_15} AuxVars[] AssignedVars[~d0_ev~0] 2020#L354-1 [795] L354-1-->L359-1: Formula: (> 1 v_~d1_ev~0_17) InVars {~d1_ev~0=v_~d1_ev~0_17} OutVars{~d1_ev~0=v_~d1_ev~0_17} AuxVars[] AssignedVars[] 2021#L359-1 [797] L359-1-->L422-1: Formula: (> v_~z_ev~0_13 1) InVars {~z_ev~0=v_~z_ev~0_13} OutVars{~z_ev~0=v_~z_ev~0_13} AuxVars[] AssignedVars[] 2077#L422-1 54.07/20.05 [2019-03-28 12:18:50,449 INFO L796 eck$LassoCheckResult]: Loop: 2077#L422-1 [887] L422-1-->L285: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 1) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 2023#L285 [888] L285-->L258: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_13, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res] 2024#L258 [802] L258-->L265: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8 0) (> 0 v_~comp_m1_st~0_9)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_9} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8, ~comp_m1_st~0=v_~comp_m1_st~0_9} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 2082#L265 [889] L265-->L280: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___0~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 2083#L280 [890] L280-->L202-2: Formula: (and (= v_ULTIMATE.start_eval_~tmp___0~0_8 0) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 2)) InVars {ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 2064#L202-2 [800] L202-2-->L202-3: Formula: (> 1 v_~b0_req_up~0_9) InVars {~b0_req_up~0=v_~b0_req_up~0_9} OutVars{~b0_req_up~0=v_~b0_req_up~0_9} AuxVars[] AssignedVars[] 2062#L202-3 [807] L202-3-->L209-1: Formula: (> 1 v_~b1_req_up~0_9) InVars {~b1_req_up~0=v_~b1_req_up~0_9} OutVars{~b1_req_up~0=v_~b1_req_up~0_9} AuxVars[] AssignedVars[] 2055#L209-1 [811] L209-1-->L216-1: Formula: (< v_~d0_req_up~0_9 1) InVars {~d0_req_up~0=v_~d0_req_up~0_9} OutVars{~d0_req_up~0=v_~d0_req_up~0_9} AuxVars[] AssignedVars[] 2051#L216-1 [814] L216-1-->L223-1: Formula: (> v_~d1_req_up~0_9 1) InVars {~d1_req_up~0=v_~d1_req_up~0_9} OutVars{~d1_req_up~0=v_~d1_req_up~0_9} AuxVars[] AssignedVars[] 2019#L223-1 [820] L223-1-->L230-1: Formula: (< 1 v_~z_req_up~0_9) InVars {~z_req_up~0=v_~z_req_up~0_9} OutVars{~z_req_up~0=v_~z_req_up~0_9} AuxVars[] AssignedVars[] 2008#L230-1 [498] L230-1-->L311-2: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 3) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 2009#L311-2 [632] L311-2-->L311-4: Formula: (and (= v_~b0_ev~0_8 1) (= v_~b0_ev~0_9 0)) InVars {~b0_ev~0=v_~b0_ev~0_9} OutVars{~b0_ev~0=v_~b0_ev~0_8} AuxVars[] AssignedVars[~b0_ev~0] 2037#L311-4 [832] L311-4-->L316-3: Formula: (> 0 v_~b1_ev~0_10) InVars {~b1_ev~0=v_~b1_ev~0_10} OutVars{~b1_ev~0=v_~b1_ev~0_10} AuxVars[] AssignedVars[] 2038#L316-3 [838] L316-3-->L321-3: Formula: (< v_~d0_ev~0_10 0) InVars {~d0_ev~0=v_~d0_ev~0_10} OutVars{~d0_ev~0=v_~d0_ev~0_10} AuxVars[] AssignedVars[] 2079#L321-3 [662] L321-3-->L326-3: Formula: (and (= v_~d1_ev~0_8 1) (= 0 v_~d1_ev~0_9)) InVars {~d1_ev~0=v_~d1_ev~0_9} OutVars{~d1_ev~0=v_~d1_ev~0_8} AuxVars[] AssignedVars[~d1_ev~0] 2056#L326-3 [850] L326-3-->L331-3: Formula: (> v_~z_ev~0_10 0) InVars {~z_ev~0=v_~z_ev~0_10} OutVars{~z_ev~0=v_~z_ev~0_10} AuxVars[] AssignedVars[] 2057#L331-3 [570] L331-3-->L97-1: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_4|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_10, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 2086#L97-1 [588] L97-1-->L119-1: Formula: (and (= v_~b0_ev~0_13 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13 1)) InVars {~b0_ev~0=v_~b0_ev~0_13} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13, ~b0_ev~0=v_~b0_ev~0_13} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 2046#L119-1 [891] L119-1-->L380-3: Formula: (and (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20 |v_ULTIMATE.start_is_method1_triggered_#res_8|) (= |v_ULTIMATE.start_is_method1_triggered_#res_8| v_ULTIMATE.start_activate_threads_~tmp~1_14)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_14, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_8|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_8|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 2006#L380-3 [864] L380-3-->L380-5: Formula: (and (= v_~comp_m1_st~0_7 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11, ~comp_m1_st~0=v_~comp_m1_st~0_7} AuxVars[] AssignedVars[~comp_m1_st~0] 2007#L380-5 [868] L380-5-->L344-3: Formula: (< v_~b0_ev~0_20 1) InVars {~b0_ev~0=v_~b0_ev~0_20} OutVars{~b0_ev~0=v_~b0_ev~0_20} AuxVars[] AssignedVars[] 2017#L344-3 [870] L344-3-->L349-3: Formula: (< 1 v_~b1_ev~0_20) InVars {~b1_ev~0=v_~b1_ev~0_20} OutVars{~b1_ev~0=v_~b1_ev~0_20} AuxVars[] AssignedVars[] 2066#L349-3 [656] L349-3-->L354-3: Formula: (and (= v_~d0_ev~0_18 2) (= v_~d0_ev~0_19 1)) InVars {~d0_ev~0=v_~d0_ev~0_19} OutVars{~d0_ev~0=v_~d0_ev~0_18} AuxVars[] AssignedVars[~d0_ev~0] 2033#L354-3 [513] L354-3-->L359-3: Formula: (and (= 1 v_~d1_ev~0_19) (= v_~d1_ev~0_18 2)) InVars {~d1_ev~0=v_~d1_ev~0_19} OutVars{~d1_ev~0=v_~d1_ev~0_18} AuxVars[] AssignedVars[~d1_ev~0] 2034#L359-3 [531] L359-3-->L364-3: Formula: (and (= v_~z_ev~0_15 1) (= v_~z_ev~0_14 2)) InVars {~z_ev~0=v_~z_ev~0_15} OutVars{~z_ev~0=v_~z_ev~0_14} AuxVars[] AssignedVars[~z_ev~0] 2054#L364-3 [568] L364-3-->L258-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_5, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_2|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_#res] 2085#L258-1 [666] L258-1-->L265-1: Formula: (and (= v_~comp_m1_st~0_10 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9 1)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_10} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9, ~comp_m1_st~0=v_~comp_m1_st~0_10} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 2080#L265-1 [892] L265-1-->L397: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_stop_simulation_~tmp~2_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_4|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_~tmp~2] 2081#L397 [880] L397-->L404: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_4 0) (< 0 v_ULTIMATE.start_stop_simulation_~tmp~2_5)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_4, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 2084#L404 [897] L404-->L422-1: Formula: (and (= 0 v_ULTIMATE.start_start_simulation_~tmp~3_9) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= |v_ULTIMATE.start_stop_simulation_#res_5| v_ULTIMATE.start_start_simulation_~tmp~3_9)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_~tmp~3] 2077#L422-1 54.07/20.05 [2019-03-28 12:18:50,449 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.05 [2019-03-28 12:18:50,450 INFO L82 PathProgramCache]: Analyzing trace with hash -1153446716, now seen corresponding path program 1 times 54.07/20.05 [2019-03-28 12:18:50,450 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.05 [2019-03-28 12:18:50,450 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.05 [2019-03-28 12:18:50,451 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:50,451 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:50,451 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:50,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.05 [2019-03-28 12:18:50,467 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.05 [2019-03-28 12:18:50,467 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.05 [2019-03-28 12:18:50,467 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 54.07/20.05 [2019-03-28 12:18:50,468 INFO L799 eck$LassoCheckResult]: stem already infeasible 54.07/20.05 [2019-03-28 12:18:50,468 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.05 [2019-03-28 12:18:50,468 INFO L82 PathProgramCache]: Analyzing trace with hash 892603667, now seen corresponding path program 2 times 54.07/20.05 [2019-03-28 12:18:50,468 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.05 [2019-03-28 12:18:50,468 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.05 [2019-03-28 12:18:50,469 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:50,469 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:50,469 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:50,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.05 [2019-03-28 12:18:50,486 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.05 [2019-03-28 12:18:50,487 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.05 [2019-03-28 12:18:50,487 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 54.07/20.05 [2019-03-28 12:18:50,488 INFO L811 eck$LassoCheckResult]: loop already infeasible 54.07/20.05 [2019-03-28 12:18:50,488 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 54.07/20.05 [2019-03-28 12:18:50,488 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 54.07/20.05 [2019-03-28 12:18:50,488 INFO L87 Difference]: Start difference. First operand 90 states and 209 transitions. cyclomatic complexity: 120 Second operand 3 states. 54.07/20.05 [2019-03-28 12:18:50,620 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 54.07/20.05 [2019-03-28 12:18:50,621 INFO L93 Difference]: Finished difference Result 90 states and 207 transitions. 54.07/20.05 [2019-03-28 12:18:50,621 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 54.07/20.05 [2019-03-28 12:18:50,621 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 90 states and 207 transitions. 54.07/20.05 [2019-03-28 12:18:50,622 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 56 54.07/20.05 [2019-03-28 12:18:50,623 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 90 states to 90 states and 207 transitions. 54.07/20.05 [2019-03-28 12:18:50,623 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 90 54.07/20.05 [2019-03-28 12:18:50,624 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 90 54.07/20.05 [2019-03-28 12:18:50,624 INFO L73 IsDeterministic]: Start isDeterministic. Operand 90 states and 207 transitions. 54.07/20.05 [2019-03-28 12:18:50,624 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 54.07/20.05 [2019-03-28 12:18:50,624 INFO L706 BuchiCegarLoop]: Abstraction has 90 states and 207 transitions. 54.07/20.05 [2019-03-28 12:18:50,624 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90 states and 207 transitions. 54.07/20.05 [2019-03-28 12:18:50,627 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90 to 90. 54.07/20.05 [2019-03-28 12:18:50,627 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 90 states. 54.07/20.05 [2019-03-28 12:18:50,628 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90 states to 90 states and 207 transitions. 54.07/20.05 [2019-03-28 12:18:50,628 INFO L729 BuchiCegarLoop]: Abstraction has 90 states and 207 transitions. 54.07/20.05 [2019-03-28 12:18:50,628 INFO L609 BuchiCegarLoop]: Abstraction has 90 states and 207 transitions. 54.07/20.05 [2019-03-28 12:18:50,628 INFO L442 BuchiCegarLoop]: ======== Iteration 11============ 54.07/20.05 [2019-03-28 12:18:50,628 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 90 states and 207 transitions. 54.07/20.05 [2019-03-28 12:18:50,629 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 56 54.07/20.05 [2019-03-28 12:18:50,629 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 54.07/20.05 [2019-03-28 12:18:50,629 INFO L119 BuchiIsEmpty]: Starting construction of run 54.07/20.05 [2019-03-28 12:18:50,630 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.05 [2019-03-28 12:18:50,630 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.05 [2019-03-28 12:18:50,631 INFO L794 eck$LassoCheckResult]: Stem: 2258#ULTIMATE.startENTRY [885] ULTIMATE.startENTRY-->L202: Formula: (and (= v_~d0_ev~0_23 2) (= 0 v_~z_val~0_13) (= 2 v_~b1_ev~0_23) (= v_~d0_val_t~0_9 1) (= v_~b0_val~0_13 0) (= 1 v_~b1_val_t~0_9) (= 1 v_~d1_req_up~0_12) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_9 0) (= 2 v_~d1_ev~0_23) (= v_~b1_val~0_13 0) (= v_~b0_val_t~0_9 1) (= v_~b0_req_up~0_12 1) (= 0 v_~comp_m1_i~0_7) (= v_~d0_req_up~0_12 1) (= v_~comp_m1_st~0_15 0) (= v_~b0_ev~0_23 2) (= 1 v_~d1_val_t~0_9) (= v_~z_req_up~0_12 0) (= v_~z_val_t~0_10 0) (= 0 v_~d1_val~0_13) (= v_~z_ev~0_19 2) (= v_~b1_req_up~0_12 1) (= 0 v_~d0_val~0_13)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_4|, ~b1_val~0=v_~b1_val~0_13, ~b0_val~0=v_~b0_val~0_13, ~d0_req_up~0=v_~d0_req_up~0_12, ~d0_val~0=v_~d0_val~0_13, ~d1_val_t~0=v_~d1_val_t~0_9, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_9, ~d1_ev~0=v_~d1_ev~0_23, ~d1_val~0=v_~d1_val~0_13, ~b0_req_up~0=v_~b0_req_up~0_12, ~z_ev~0=v_~z_ev~0_19, ~b1_val_t~0=v_~b1_val_t~0_9, ~b1_ev~0=v_~b1_ev~0_23, ULTIMATE.start_main_~__retres1~2=v_ULTIMATE.start_main_~__retres1~2_6, ~z_val~0=v_~z_val~0_13, ~d1_req_up~0=v_~d1_req_up~0_12, ~z_val_t~0=v_~z_val_t~0_10, ~b0_val_t~0=v_~b0_val_t~0_9, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~z_req_up~0=v_~z_req_up~0_12, ~b1_req_up~0=v_~b1_req_up~0_12, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~d0_ev~0=v_~d0_ev~0_23, ~b0_ev~0=v_~b0_ev~0_23, ~d0_val_t~0=v_~d0_val_t~0_9, ~comp_m1_st~0=v_~comp_m1_st~0_15, ~comp_m1_i~0=v_~comp_m1_i~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ~b1_val~0, ~b0_val~0, ~d0_req_up~0, ~d0_val~0, ~d1_val_t~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~d1_ev~0, ~d1_val~0, ~b0_req_up~0, ~z_ev~0, ~b1_val_t~0, ~b1_ev~0, ULTIMATE.start_main_~__retres1~2, ~z_val~0, ~d1_req_up~0, ~z_val_t~0, ~b0_val_t~0, ULTIMATE.start_start_simulation_~tmp~3, ~z_req_up~0, ~b1_req_up~0, ULTIMATE.start_main_#res, ~d0_ev~0, ~b0_ev~0, ~d0_val_t~0, ~comp_m1_st~0, ~comp_m1_i~0] 2259#L202 [566] L202-->L127: Formula: (= 1 v_~b0_req_up~0_4) InVars {~b0_req_up~0=v_~b0_req_up~0_4} OutVars{~b0_req_up~0=v_~b0_req_up~0_4} AuxVars[] AssignedVars[] 2222#L127 [748] L127-->L127-2: Formula: (and (= v_~b0_val~0_3 v_~b0_val_t~0_3) (> v_~b0_val_t~0_3 v_~b0_val~0_4) (= v_~b0_ev~0_3 0)) InVars {~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_4} OutVars{~b0_ev~0=v_~b0_ev~0_3, ~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_3} AuxVars[] AssignedVars[~b0_val~0, ~b0_ev~0] 2223#L127-2 [580] L127-2-->L202-1: Formula: (= v_~b0_req_up~0_5 0) InVars {} OutVars{~b0_req_up~0=v_~b0_req_up~0_5} AuxVars[] AssignedVars[~b0_req_up~0] 2254#L202-1 [545] L202-1-->L142: Formula: (= 1 v_~b1_req_up~0_4) InVars {~b1_req_up~0=v_~b1_req_up~0_4} OutVars{~b1_req_up~0=v_~b1_req_up~0_4} AuxVars[] AssignedVars[] 2239#L142 [752] L142-->L142-2: Formula: (and (= v_~b1_ev~0_3 0) (< v_~b1_val~0_4 v_~b1_val_t~0_3) (= v_~b1_val~0_3 v_~b1_val_t~0_3)) InVars {~b1_val_t~0=v_~b1_val_t~0_3, ~b1_val~0=v_~b1_val~0_4} OutVars{~b1_val_t~0=v_~b1_val_t~0_3, ~b1_ev~0=v_~b1_ev~0_3, ~b1_val~0=v_~b1_val~0_3} AuxVars[] AssignedVars[~b1_val~0, ~b1_ev~0] 2232#L142-2 [521] L142-2-->L209: Formula: (= v_~b1_req_up~0_5 0) InVars {} OutVars{~b1_req_up~0=v_~b1_req_up~0_5} AuxVars[] AssignedVars[~b1_req_up~0] 2233#L209 [624] L209-->L157: Formula: (= v_~d0_req_up~0_4 1) InVars {~d0_req_up~0=v_~d0_req_up~0_4} OutVars{~d0_req_up~0=v_~d0_req_up~0_4} AuxVars[] AssignedVars[] 2209#L157 [757] L157-->L157-2: Formula: (and (> v_~d0_val_t~0_3 v_~d0_val~0_4) (= v_~d0_val~0_3 v_~d0_val_t~0_3) (= v_~d0_ev~0_3 0)) InVars {~d0_val~0=v_~d0_val~0_4, ~d0_val_t~0=v_~d0_val_t~0_3} OutVars{~d0_ev~0=v_~d0_ev~0_3, ~d0_val~0=v_~d0_val~0_3, ~d0_val_t~0=v_~d0_val_t~0_3} AuxVars[] AssignedVars[~d0_ev~0, ~d0_val~0] 2200#L157-2 [600] L157-2-->L216: Formula: (= v_~d0_req_up~0_5 0) InVars {} OutVars{~d0_req_up~0=v_~d0_req_up~0_5} AuxVars[] AssignedVars[~d0_req_up~0] 2201#L216 [758] L216-->L223: Formula: (< v_~d1_req_up~0_6 1) InVars {~d1_req_up~0=v_~d1_req_up~0_6} OutVars{~d1_req_up~0=v_~d1_req_up~0_6} AuxVars[] AssignedVars[] 2256#L223 [763] L223-->L230: Formula: (< 1 v_~z_req_up~0_6) InVars {~z_req_up~0=v_~z_req_up~0_6} OutVars{~z_req_up~0=v_~z_req_up~0_6} AuxVars[] AssignedVars[] 2202#L230 [767] L230-->L245-1: Formula: (and (> 1 v_~comp_m1_i~0_4) (= v_~comp_m1_st~0_5 2)) InVars {~comp_m1_i~0=v_~comp_m1_i~0_4} OutVars{~comp_m1_st~0=v_~comp_m1_st~0_5, ~comp_m1_i~0=v_~comp_m1_i~0_4} AuxVars[] AssignedVars[~comp_m1_st~0] 2203#L245-1 [769] L245-1-->L311-1: Formula: (> v_~b0_ev~0_7 0) InVars {~b0_ev~0=v_~b0_ev~0_7} OutVars{~b0_ev~0=v_~b0_ev~0_7} AuxVars[] AssignedVars[] 2221#L311-1 [628] L311-1-->L316-1: Formula: (and (= 0 v_~b1_ev~0_6) (= v_~b1_ev~0_5 1)) InVars {~b1_ev~0=v_~b1_ev~0_6} OutVars{~b1_ev~0=v_~b1_ev~0_5} AuxVars[] AssignedVars[~b1_ev~0] 2250#L316-1 [654] L316-1-->L321-1: Formula: (and (= v_~d0_ev~0_5 1) (= v_~d0_ev~0_6 0)) InVars {~d0_ev~0=v_~d0_ev~0_6} OutVars{~d0_ev~0=v_~d0_ev~0_5} AuxVars[] AssignedVars[~d0_ev~0] 2212#L321-1 [507] L321-1-->L326-1: Formula: (and (= 0 v_~d1_ev~0_6) (= v_~d1_ev~0_5 1)) InVars {~d1_ev~0=v_~d1_ev~0_6} OutVars{~d1_ev~0=v_~d1_ev~0_5} AuxVars[] AssignedVars[~d1_ev~0] 2213#L326-1 [556] L326-1-->L331-1: Formula: (and (= 0 v_~z_ev~0_6) (= v_~z_ev~0_5 1)) InVars {~z_ev~0=v_~z_ev~0_6} OutVars{~z_ev~0=v_~z_ev~0_5} AuxVars[] AssignedVars[~z_ev~0] 2265#L331-1 [583] L331-1-->L97: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_1|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 2278#L97 [591] L97-->L119: Formula: (and (= v_~b0_ev~0_11 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4 1)) InVars {~b0_ev~0=v_~b0_ev~0_11} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4, ~b0_ev~0=v_~b0_ev~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 2237#L119 [886] L119-->L380: Formula: (and (= |v_ULTIMATE.start_is_method1_triggered_#res_7| v_ULTIMATE.start_activate_threads_~tmp~1_13) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19 |v_ULTIMATE.start_is_method1_triggered_#res_7|)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_13, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_7|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_7|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 2234#L380 [615] L380-->L380-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_9) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} AuxVars[] AssignedVars[] 2235#L380-2 [618] L380-2-->L344-1: Formula: (and (= v_~b0_ev~0_15 2) (= v_~b0_ev~0_16 1)) InVars {~b0_ev~0=v_~b0_ev~0_16} OutVars{~b0_ev~0=v_~b0_ev~0_15} AuxVars[] AssignedVars[~b0_ev~0] 2240#L344-1 [791] L344-1-->L349-1: Formula: (> 1 v_~b1_ev~0_17) InVars {~b1_ev~0=v_~b1_ev~0_17} OutVars{~b1_ev~0=v_~b1_ev~0_17} AuxVars[] AssignedVars[] 2248#L349-1 [652] L349-1-->L354-1: Formula: (and (= v_~d0_ev~0_15 2) (= v_~d0_ev~0_16 1)) InVars {~d0_ev~0=v_~d0_ev~0_16} OutVars{~d0_ev~0=v_~d0_ev~0_15} AuxVars[] AssignedVars[~d0_ev~0] 2207#L354-1 [795] L354-1-->L359-1: Formula: (> 1 v_~d1_ev~0_17) InVars {~d1_ev~0=v_~d1_ev~0_17} OutVars{~d1_ev~0=v_~d1_ev~0_17} AuxVars[] AssignedVars[] 2208#L359-1 [797] L359-1-->L422-1: Formula: (> v_~z_ev~0_13 1) InVars {~z_ev~0=v_~z_ev~0_13} OutVars{~z_ev~0=v_~z_ev~0_13} AuxVars[] AssignedVars[] 2264#L422-1 54.07/20.05 [2019-03-28 12:18:50,632 INFO L796 eck$LassoCheckResult]: Loop: 2264#L422-1 [887] L422-1-->L285: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 1) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 2210#L285 [888] L285-->L258: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_13, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res] 2211#L258 [802] L258-->L265: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8 0) (> 0 v_~comp_m1_st~0_9)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_9} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8, ~comp_m1_st~0=v_~comp_m1_st~0_9} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 2269#L265 [889] L265-->L280: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___0~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 2270#L280 [890] L280-->L202-2: Formula: (and (= v_ULTIMATE.start_eval_~tmp___0~0_8 0) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 2)) InVars {ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 2251#L202-2 [800] L202-2-->L202-3: Formula: (> 1 v_~b0_req_up~0_9) InVars {~b0_req_up~0=v_~b0_req_up~0_9} OutVars{~b0_req_up~0=v_~b0_req_up~0_9} AuxVars[] AssignedVars[] 2249#L202-3 [807] L202-3-->L209-1: Formula: (> 1 v_~b1_req_up~0_9) InVars {~b1_req_up~0=v_~b1_req_up~0_9} OutVars{~b1_req_up~0=v_~b1_req_up~0_9} AuxVars[] AssignedVars[] 2242#L209-1 [811] L209-1-->L216-1: Formula: (< v_~d0_req_up~0_9 1) InVars {~d0_req_up~0=v_~d0_req_up~0_9} OutVars{~d0_req_up~0=v_~d0_req_up~0_9} AuxVars[] AssignedVars[] 2238#L216-1 [815] L216-1-->L223-1: Formula: (< v_~d1_req_up~0_9 1) InVars {~d1_req_up~0=v_~d1_req_up~0_9} OutVars{~d1_req_up~0=v_~d1_req_up~0_9} AuxVars[] AssignedVars[] 2206#L223-1 [820] L223-1-->L230-1: Formula: (< 1 v_~z_req_up~0_9) InVars {~z_req_up~0=v_~z_req_up~0_9} OutVars{~z_req_up~0=v_~z_req_up~0_9} AuxVars[] AssignedVars[] 2195#L230-1 [498] L230-1-->L311-2: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 3) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 2196#L311-2 [632] L311-2-->L311-4: Formula: (and (= v_~b0_ev~0_8 1) (= v_~b0_ev~0_9 0)) InVars {~b0_ev~0=v_~b0_ev~0_9} OutVars{~b0_ev~0=v_~b0_ev~0_8} AuxVars[] AssignedVars[~b0_ev~0] 2224#L311-4 [832] L311-4-->L316-3: Formula: (> 0 v_~b1_ev~0_10) InVars {~b1_ev~0=v_~b1_ev~0_10} OutVars{~b1_ev~0=v_~b1_ev~0_10} AuxVars[] AssignedVars[] 2225#L316-3 [838] L316-3-->L321-3: Formula: (< v_~d0_ev~0_10 0) InVars {~d0_ev~0=v_~d0_ev~0_10} OutVars{~d0_ev~0=v_~d0_ev~0_10} AuxVars[] AssignedVars[] 2266#L321-3 [662] L321-3-->L326-3: Formula: (and (= v_~d1_ev~0_8 1) (= 0 v_~d1_ev~0_9)) InVars {~d1_ev~0=v_~d1_ev~0_9} OutVars{~d1_ev~0=v_~d1_ev~0_8} AuxVars[] AssignedVars[~d1_ev~0] 2243#L326-3 [850] L326-3-->L331-3: Formula: (> v_~z_ev~0_10 0) InVars {~z_ev~0=v_~z_ev~0_10} OutVars{~z_ev~0=v_~z_ev~0_10} AuxVars[] AssignedVars[] 2244#L331-3 [570] L331-3-->L97-1: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_4|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_10, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 2273#L97-1 [588] L97-1-->L119-1: Formula: (and (= v_~b0_ev~0_13 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13 1)) InVars {~b0_ev~0=v_~b0_ev~0_13} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13, ~b0_ev~0=v_~b0_ev~0_13} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 2231#L119-1 [891] L119-1-->L380-3: Formula: (and (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20 |v_ULTIMATE.start_is_method1_triggered_#res_8|) (= |v_ULTIMATE.start_is_method1_triggered_#res_8| v_ULTIMATE.start_activate_threads_~tmp~1_14)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_14, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_8|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_8|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 2191#L380-3 [864] L380-3-->L380-5: Formula: (and (= v_~comp_m1_st~0_7 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11, ~comp_m1_st~0=v_~comp_m1_st~0_7} AuxVars[] AssignedVars[~comp_m1_st~0] 2192#L380-5 [868] L380-5-->L344-3: Formula: (< v_~b0_ev~0_20 1) InVars {~b0_ev~0=v_~b0_ev~0_20} OutVars{~b0_ev~0=v_~b0_ev~0_20} AuxVars[] AssignedVars[] 2204#L344-3 [870] L344-3-->L349-3: Formula: (< 1 v_~b1_ev~0_20) InVars {~b1_ev~0=v_~b1_ev~0_20} OutVars{~b1_ev~0=v_~b1_ev~0_20} AuxVars[] AssignedVars[] 2253#L349-3 [656] L349-3-->L354-3: Formula: (and (= v_~d0_ev~0_18 2) (= v_~d0_ev~0_19 1)) InVars {~d0_ev~0=v_~d0_ev~0_19} OutVars{~d0_ev~0=v_~d0_ev~0_18} AuxVars[] AssignedVars[~d0_ev~0] 2219#L354-3 [513] L354-3-->L359-3: Formula: (and (= 1 v_~d1_ev~0_19) (= v_~d1_ev~0_18 2)) InVars {~d1_ev~0=v_~d1_ev~0_19} OutVars{~d1_ev~0=v_~d1_ev~0_18} AuxVars[] AssignedVars[~d1_ev~0] 2220#L359-3 [531] L359-3-->L364-3: Formula: (and (= v_~z_ev~0_15 1) (= v_~z_ev~0_14 2)) InVars {~z_ev~0=v_~z_ev~0_15} OutVars{~z_ev~0=v_~z_ev~0_14} AuxVars[] AssignedVars[~z_ev~0] 2241#L364-3 [568] L364-3-->L258-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_5, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_2|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_#res] 2272#L258-1 [666] L258-1-->L265-1: Formula: (and (= v_~comp_m1_st~0_10 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9 1)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_10} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9, ~comp_m1_st~0=v_~comp_m1_st~0_10} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 2267#L265-1 [892] L265-1-->L397: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_stop_simulation_~tmp~2_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_4|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_~tmp~2] 2268#L397 [880] L397-->L404: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_4 0) (< 0 v_ULTIMATE.start_stop_simulation_~tmp~2_5)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_4, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 2271#L404 [897] L404-->L422-1: Formula: (and (= 0 v_ULTIMATE.start_start_simulation_~tmp~3_9) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= |v_ULTIMATE.start_stop_simulation_#res_5| v_ULTIMATE.start_start_simulation_~tmp~3_9)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_~tmp~3] 2264#L422-1 54.07/20.05 [2019-03-28 12:18:50,632 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.05 [2019-03-28 12:18:50,632 INFO L82 PathProgramCache]: Analyzing trace with hash 1788210883, now seen corresponding path program 1 times 54.07/20.05 [2019-03-28 12:18:50,632 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.05 [2019-03-28 12:18:50,632 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.05 [2019-03-28 12:18:50,633 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:50,633 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:50,633 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:50,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.05 [2019-03-28 12:18:50,652 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.05 [2019-03-28 12:18:50,652 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.05 [2019-03-28 12:18:50,663 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 54.07/20.05 [2019-03-28 12:18:50,664 INFO L799 eck$LassoCheckResult]: stem already infeasible 54.07/20.05 [2019-03-28 12:18:50,664 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.05 [2019-03-28 12:18:50,664 INFO L82 PathProgramCache]: Analyzing trace with hash -1145452622, now seen corresponding path program 1 times 54.07/20.05 [2019-03-28 12:18:50,664 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.05 [2019-03-28 12:18:50,665 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.05 [2019-03-28 12:18:50,665 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:50,666 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:50,666 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:50,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.05 [2019-03-28 12:18:50,681 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.05 [2019-03-28 12:18:50,681 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.05 [2019-03-28 12:18:50,681 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 54.07/20.05 [2019-03-28 12:18:50,681 INFO L811 eck$LassoCheckResult]: loop already infeasible 54.07/20.05 [2019-03-28 12:18:50,682 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 54.07/20.05 [2019-03-28 12:18:50,682 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 54.07/20.05 [2019-03-28 12:18:50,682 INFO L87 Difference]: Start difference. First operand 90 states and 207 transitions. cyclomatic complexity: 118 Second operand 3 states. 54.07/20.05 [2019-03-28 12:18:50,841 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 54.07/20.05 [2019-03-28 12:18:50,842 INFO L93 Difference]: Finished difference Result 90 states and 206 transitions. 54.07/20.05 [2019-03-28 12:18:50,842 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 54.07/20.05 [2019-03-28 12:18:50,842 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 90 states and 206 transitions. 54.07/20.05 [2019-03-28 12:18:50,843 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 56 54.07/20.05 [2019-03-28 12:18:50,844 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 90 states to 90 states and 206 transitions. 54.07/20.05 [2019-03-28 12:18:50,844 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 90 54.07/20.05 [2019-03-28 12:18:50,845 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 90 54.07/20.05 [2019-03-28 12:18:50,845 INFO L73 IsDeterministic]: Start isDeterministic. Operand 90 states and 206 transitions. 54.07/20.05 [2019-03-28 12:18:50,845 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 54.07/20.05 [2019-03-28 12:18:50,845 INFO L706 BuchiCegarLoop]: Abstraction has 90 states and 206 transitions. 54.07/20.05 [2019-03-28 12:18:50,846 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90 states and 206 transitions. 54.07/20.05 [2019-03-28 12:18:50,847 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90 to 90. 54.07/20.05 [2019-03-28 12:18:50,848 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 90 states. 54.07/20.05 [2019-03-28 12:18:50,848 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90 states to 90 states and 206 transitions. 54.07/20.05 [2019-03-28 12:18:50,848 INFO L729 BuchiCegarLoop]: Abstraction has 90 states and 206 transitions. 54.07/20.05 [2019-03-28 12:18:50,848 INFO L609 BuchiCegarLoop]: Abstraction has 90 states and 206 transitions. 54.07/20.05 [2019-03-28 12:18:50,848 INFO L442 BuchiCegarLoop]: ======== Iteration 12============ 54.07/20.05 [2019-03-28 12:18:50,849 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 90 states and 206 transitions. 54.07/20.05 [2019-03-28 12:18:50,849 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 56 54.07/20.05 [2019-03-28 12:18:50,849 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 54.07/20.05 [2019-03-28 12:18:50,850 INFO L119 BuchiIsEmpty]: Starting construction of run 54.07/20.05 [2019-03-28 12:18:50,850 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.05 [2019-03-28 12:18:50,850 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.05 [2019-03-28 12:18:50,851 INFO L794 eck$LassoCheckResult]: Stem: 2445#ULTIMATE.startENTRY [885] ULTIMATE.startENTRY-->L202: Formula: (and (= v_~d0_ev~0_23 2) (= 0 v_~z_val~0_13) (= 2 v_~b1_ev~0_23) (= v_~d0_val_t~0_9 1) (= v_~b0_val~0_13 0) (= 1 v_~b1_val_t~0_9) (= 1 v_~d1_req_up~0_12) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_9 0) (= 2 v_~d1_ev~0_23) (= v_~b1_val~0_13 0) (= v_~b0_val_t~0_9 1) (= v_~b0_req_up~0_12 1) (= 0 v_~comp_m1_i~0_7) (= v_~d0_req_up~0_12 1) (= v_~comp_m1_st~0_15 0) (= v_~b0_ev~0_23 2) (= 1 v_~d1_val_t~0_9) (= v_~z_req_up~0_12 0) (= v_~z_val_t~0_10 0) (= 0 v_~d1_val~0_13) (= v_~z_ev~0_19 2) (= v_~b1_req_up~0_12 1) (= 0 v_~d0_val~0_13)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_4|, ~b1_val~0=v_~b1_val~0_13, ~b0_val~0=v_~b0_val~0_13, ~d0_req_up~0=v_~d0_req_up~0_12, ~d0_val~0=v_~d0_val~0_13, ~d1_val_t~0=v_~d1_val_t~0_9, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_9, ~d1_ev~0=v_~d1_ev~0_23, ~d1_val~0=v_~d1_val~0_13, ~b0_req_up~0=v_~b0_req_up~0_12, ~z_ev~0=v_~z_ev~0_19, ~b1_val_t~0=v_~b1_val_t~0_9, ~b1_ev~0=v_~b1_ev~0_23, ULTIMATE.start_main_~__retres1~2=v_ULTIMATE.start_main_~__retres1~2_6, ~z_val~0=v_~z_val~0_13, ~d1_req_up~0=v_~d1_req_up~0_12, ~z_val_t~0=v_~z_val_t~0_10, ~b0_val_t~0=v_~b0_val_t~0_9, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~z_req_up~0=v_~z_req_up~0_12, ~b1_req_up~0=v_~b1_req_up~0_12, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~d0_ev~0=v_~d0_ev~0_23, ~b0_ev~0=v_~b0_ev~0_23, ~d0_val_t~0=v_~d0_val_t~0_9, ~comp_m1_st~0=v_~comp_m1_st~0_15, ~comp_m1_i~0=v_~comp_m1_i~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ~b1_val~0, ~b0_val~0, ~d0_req_up~0, ~d0_val~0, ~d1_val_t~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~d1_ev~0, ~d1_val~0, ~b0_req_up~0, ~z_ev~0, ~b1_val_t~0, ~b1_ev~0, ULTIMATE.start_main_~__retres1~2, ~z_val~0, ~d1_req_up~0, ~z_val_t~0, ~b0_val_t~0, ULTIMATE.start_start_simulation_~tmp~3, ~z_req_up~0, ~b1_req_up~0, ULTIMATE.start_main_#res, ~d0_ev~0, ~b0_ev~0, ~d0_val_t~0, ~comp_m1_st~0, ~comp_m1_i~0] 2446#L202 [566] L202-->L127: Formula: (= 1 v_~b0_req_up~0_4) InVars {~b0_req_up~0=v_~b0_req_up~0_4} OutVars{~b0_req_up~0=v_~b0_req_up~0_4} AuxVars[] AssignedVars[] 2409#L127 [748] L127-->L127-2: Formula: (and (= v_~b0_val~0_3 v_~b0_val_t~0_3) (> v_~b0_val_t~0_3 v_~b0_val~0_4) (= v_~b0_ev~0_3 0)) InVars {~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_4} OutVars{~b0_ev~0=v_~b0_ev~0_3, ~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_3} AuxVars[] AssignedVars[~b0_val~0, ~b0_ev~0] 2410#L127-2 [580] L127-2-->L202-1: Formula: (= v_~b0_req_up~0_5 0) InVars {} OutVars{~b0_req_up~0=v_~b0_req_up~0_5} AuxVars[] AssignedVars[~b0_req_up~0] 2441#L202-1 [545] L202-1-->L142: Formula: (= 1 v_~b1_req_up~0_4) InVars {~b1_req_up~0=v_~b1_req_up~0_4} OutVars{~b1_req_up~0=v_~b1_req_up~0_4} AuxVars[] AssignedVars[] 2426#L142 [752] L142-->L142-2: Formula: (and (= v_~b1_ev~0_3 0) (< v_~b1_val~0_4 v_~b1_val_t~0_3) (= v_~b1_val~0_3 v_~b1_val_t~0_3)) InVars {~b1_val_t~0=v_~b1_val_t~0_3, ~b1_val~0=v_~b1_val~0_4} OutVars{~b1_val_t~0=v_~b1_val_t~0_3, ~b1_ev~0=v_~b1_ev~0_3, ~b1_val~0=v_~b1_val~0_3} AuxVars[] AssignedVars[~b1_val~0, ~b1_ev~0] 2419#L142-2 [521] L142-2-->L209: Formula: (= v_~b1_req_up~0_5 0) InVars {} OutVars{~b1_req_up~0=v_~b1_req_up~0_5} AuxVars[] AssignedVars[~b1_req_up~0] 2420#L209 [624] L209-->L157: Formula: (= v_~d0_req_up~0_4 1) InVars {~d0_req_up~0=v_~d0_req_up~0_4} OutVars{~d0_req_up~0=v_~d0_req_up~0_4} AuxVars[] AssignedVars[] 2398#L157 [757] L157-->L157-2: Formula: (and (> v_~d0_val_t~0_3 v_~d0_val~0_4) (= v_~d0_val~0_3 v_~d0_val_t~0_3) (= v_~d0_ev~0_3 0)) InVars {~d0_val~0=v_~d0_val~0_4, ~d0_val_t~0=v_~d0_val_t~0_3} OutVars{~d0_ev~0=v_~d0_ev~0_3, ~d0_val~0=v_~d0_val~0_3, ~d0_val_t~0=v_~d0_val_t~0_3} AuxVars[] AssignedVars[~d0_ev~0, ~d0_val~0] 2387#L157-2 [600] L157-2-->L216: Formula: (= v_~d0_req_up~0_5 0) InVars {} OutVars{~d0_req_up~0=v_~d0_req_up~0_5} AuxVars[] AssignedVars[~d0_req_up~0] 2388#L216 [554] L216-->L172: Formula: (= v_~d1_req_up~0_4 1) InVars {~d1_req_up~0=v_~d1_req_up~0_4} OutVars{~d1_req_up~0=v_~d1_req_up~0_4} AuxVars[] AssignedVars[] 2450#L172 [761] L172-->L172-2: Formula: (and (= v_~d1_val~0_3 v_~d1_val_t~0_3) (< v_~d1_val_t~0_3 v_~d1_val~0_4) (= v_~d1_ev~0_3 0)) InVars {~d1_val_t~0=v_~d1_val_t~0_3, ~d1_val~0=v_~d1_val~0_4} OutVars{~d1_val_t~0=v_~d1_val_t~0_3, ~d1_val~0=v_~d1_val~0_3, ~d1_ev~0=v_~d1_ev~0_3} AuxVars[] AssignedVars[~d1_val~0, ~d1_ev~0] 2444#L172-2 [547] L172-2-->L223: Formula: (= v_~d1_req_up~0_5 0) InVars {} OutVars{~d1_req_up~0=v_~d1_req_up~0_5} AuxVars[] AssignedVars[~d1_req_up~0] 2443#L223 [763] L223-->L230: Formula: (< 1 v_~z_req_up~0_6) InVars {~z_req_up~0=v_~z_req_up~0_6} OutVars{~z_req_up~0=v_~z_req_up~0_6} AuxVars[] AssignedVars[] 2389#L230 [767] L230-->L245-1: Formula: (and (> 1 v_~comp_m1_i~0_4) (= v_~comp_m1_st~0_5 2)) InVars {~comp_m1_i~0=v_~comp_m1_i~0_4} OutVars{~comp_m1_st~0=v_~comp_m1_st~0_5, ~comp_m1_i~0=v_~comp_m1_i~0_4} AuxVars[] AssignedVars[~comp_m1_st~0] 2390#L245-1 [769] L245-1-->L311-1: Formula: (> v_~b0_ev~0_7 0) InVars {~b0_ev~0=v_~b0_ev~0_7} OutVars{~b0_ev~0=v_~b0_ev~0_7} AuxVars[] AssignedVars[] 2406#L311-1 [628] L311-1-->L316-1: Formula: (and (= 0 v_~b1_ev~0_6) (= v_~b1_ev~0_5 1)) InVars {~b1_ev~0=v_~b1_ev~0_6} OutVars{~b1_ev~0=v_~b1_ev~0_5} AuxVars[] AssignedVars[~b1_ev~0] 2437#L316-1 [654] L316-1-->L321-1: Formula: (and (= v_~d0_ev~0_5 1) (= v_~d0_ev~0_6 0)) InVars {~d0_ev~0=v_~d0_ev~0_6} OutVars{~d0_ev~0=v_~d0_ev~0_5} AuxVars[] AssignedVars[~d0_ev~0] 2399#L321-1 [507] L321-1-->L326-1: Formula: (and (= 0 v_~d1_ev~0_6) (= v_~d1_ev~0_5 1)) InVars {~d1_ev~0=v_~d1_ev~0_6} OutVars{~d1_ev~0=v_~d1_ev~0_5} AuxVars[] AssignedVars[~d1_ev~0] 2400#L326-1 [556] L326-1-->L331-1: Formula: (and (= 0 v_~z_ev~0_6) (= v_~z_ev~0_5 1)) InVars {~z_ev~0=v_~z_ev~0_6} OutVars{~z_ev~0=v_~z_ev~0_5} AuxVars[] AssignedVars[~z_ev~0] 2452#L331-1 [583] L331-1-->L97: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_1|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 2465#L97 [591] L97-->L119: Formula: (and (= v_~b0_ev~0_11 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4 1)) InVars {~b0_ev~0=v_~b0_ev~0_11} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4, ~b0_ev~0=v_~b0_ev~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 2424#L119 [886] L119-->L380: Formula: (and (= |v_ULTIMATE.start_is_method1_triggered_#res_7| v_ULTIMATE.start_activate_threads_~tmp~1_13) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19 |v_ULTIMATE.start_is_method1_triggered_#res_7|)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_13, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_7|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_7|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 2421#L380 [615] L380-->L380-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_9) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} AuxVars[] AssignedVars[] 2422#L380-2 [618] L380-2-->L344-1: Formula: (and (= v_~b0_ev~0_15 2) (= v_~b0_ev~0_16 1)) InVars {~b0_ev~0=v_~b0_ev~0_16} OutVars{~b0_ev~0=v_~b0_ev~0_15} AuxVars[] AssignedVars[~b0_ev~0] 2427#L344-1 [791] L344-1-->L349-1: Formula: (> 1 v_~b1_ev~0_17) InVars {~b1_ev~0=v_~b1_ev~0_17} OutVars{~b1_ev~0=v_~b1_ev~0_17} AuxVars[] AssignedVars[] 2435#L349-1 [652] L349-1-->L354-1: Formula: (and (= v_~d0_ev~0_15 2) (= v_~d0_ev~0_16 1)) InVars {~d0_ev~0=v_~d0_ev~0_16} OutVars{~d0_ev~0=v_~d0_ev~0_15} AuxVars[] AssignedVars[~d0_ev~0] 2394#L354-1 [795] L354-1-->L359-1: Formula: (> 1 v_~d1_ev~0_17) InVars {~d1_ev~0=v_~d1_ev~0_17} OutVars{~d1_ev~0=v_~d1_ev~0_17} AuxVars[] AssignedVars[] 2395#L359-1 [797] L359-1-->L422-1: Formula: (> v_~z_ev~0_13 1) InVars {~z_ev~0=v_~z_ev~0_13} OutVars{~z_ev~0=v_~z_ev~0_13} AuxVars[] AssignedVars[] 2451#L422-1 54.07/20.05 [2019-03-28 12:18:50,852 INFO L796 eck$LassoCheckResult]: Loop: 2451#L422-1 [887] L422-1-->L285: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 1) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 2396#L285 [888] L285-->L258: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_13, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res] 2397#L258 [802] L258-->L265: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8 0) (> 0 v_~comp_m1_st~0_9)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_9} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8, ~comp_m1_st~0=v_~comp_m1_st~0_9} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 2456#L265 [889] L265-->L280: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___0~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 2457#L280 [890] L280-->L202-2: Formula: (and (= v_ULTIMATE.start_eval_~tmp___0~0_8 0) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 2)) InVars {ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 2438#L202-2 [800] L202-2-->L202-3: Formula: (> 1 v_~b0_req_up~0_9) InVars {~b0_req_up~0=v_~b0_req_up~0_9} OutVars{~b0_req_up~0=v_~b0_req_up~0_9} AuxVars[] AssignedVars[] 2436#L202-3 [807] L202-3-->L209-1: Formula: (> 1 v_~b1_req_up~0_9) InVars {~b1_req_up~0=v_~b1_req_up~0_9} OutVars{~b1_req_up~0=v_~b1_req_up~0_9} AuxVars[] AssignedVars[] 2429#L209-1 [811] L209-1-->L216-1: Formula: (< v_~d0_req_up~0_9 1) InVars {~d0_req_up~0=v_~d0_req_up~0_9} OutVars{~d0_req_up~0=v_~d0_req_up~0_9} AuxVars[] AssignedVars[] 2425#L216-1 [815] L216-1-->L223-1: Formula: (< v_~d1_req_up~0_9 1) InVars {~d1_req_up~0=v_~d1_req_up~0_9} OutVars{~d1_req_up~0=v_~d1_req_up~0_9} AuxVars[] AssignedVars[] 2393#L223-1 [820] L223-1-->L230-1: Formula: (< 1 v_~z_req_up~0_9) InVars {~z_req_up~0=v_~z_req_up~0_9} OutVars{~z_req_up~0=v_~z_req_up~0_9} AuxVars[] AssignedVars[] 2382#L230-1 [498] L230-1-->L311-2: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 3) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 2383#L311-2 [632] L311-2-->L311-4: Formula: (and (= v_~b0_ev~0_8 1) (= v_~b0_ev~0_9 0)) InVars {~b0_ev~0=v_~b0_ev~0_9} OutVars{~b0_ev~0=v_~b0_ev~0_8} AuxVars[] AssignedVars[~b0_ev~0] 2411#L311-4 [832] L311-4-->L316-3: Formula: (> 0 v_~b1_ev~0_10) InVars {~b1_ev~0=v_~b1_ev~0_10} OutVars{~b1_ev~0=v_~b1_ev~0_10} AuxVars[] AssignedVars[] 2412#L316-3 [838] L316-3-->L321-3: Formula: (< v_~d0_ev~0_10 0) InVars {~d0_ev~0=v_~d0_ev~0_10} OutVars{~d0_ev~0=v_~d0_ev~0_10} AuxVars[] AssignedVars[] 2453#L321-3 [662] L321-3-->L326-3: Formula: (and (= v_~d1_ev~0_8 1) (= 0 v_~d1_ev~0_9)) InVars {~d1_ev~0=v_~d1_ev~0_9} OutVars{~d1_ev~0=v_~d1_ev~0_8} AuxVars[] AssignedVars[~d1_ev~0] 2430#L326-3 [850] L326-3-->L331-3: Formula: (> v_~z_ev~0_10 0) InVars {~z_ev~0=v_~z_ev~0_10} OutVars{~z_ev~0=v_~z_ev~0_10} AuxVars[] AssignedVars[] 2431#L331-3 [570] L331-3-->L97-1: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_4|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_10, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 2460#L97-1 [588] L97-1-->L119-1: Formula: (and (= v_~b0_ev~0_13 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13 1)) InVars {~b0_ev~0=v_~b0_ev~0_13} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13, ~b0_ev~0=v_~b0_ev~0_13} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 2418#L119-1 [891] L119-1-->L380-3: Formula: (and (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20 |v_ULTIMATE.start_is_method1_triggered_#res_8|) (= |v_ULTIMATE.start_is_method1_triggered_#res_8| v_ULTIMATE.start_activate_threads_~tmp~1_14)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_14, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_8|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_8|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 2380#L380-3 [864] L380-3-->L380-5: Formula: (and (= v_~comp_m1_st~0_7 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11, ~comp_m1_st~0=v_~comp_m1_st~0_7} AuxVars[] AssignedVars[~comp_m1_st~0] 2381#L380-5 [868] L380-5-->L344-3: Formula: (< v_~b0_ev~0_20 1) InVars {~b0_ev~0=v_~b0_ev~0_20} OutVars{~b0_ev~0=v_~b0_ev~0_20} AuxVars[] AssignedVars[] 2391#L344-3 [870] L344-3-->L349-3: Formula: (< 1 v_~b1_ev~0_20) InVars {~b1_ev~0=v_~b1_ev~0_20} OutVars{~b1_ev~0=v_~b1_ev~0_20} AuxVars[] AssignedVars[] 2440#L349-3 [656] L349-3-->L354-3: Formula: (and (= v_~d0_ev~0_18 2) (= v_~d0_ev~0_19 1)) InVars {~d0_ev~0=v_~d0_ev~0_19} OutVars{~d0_ev~0=v_~d0_ev~0_18} AuxVars[] AssignedVars[~d0_ev~0] 2407#L354-3 [513] L354-3-->L359-3: Formula: (and (= 1 v_~d1_ev~0_19) (= v_~d1_ev~0_18 2)) InVars {~d1_ev~0=v_~d1_ev~0_19} OutVars{~d1_ev~0=v_~d1_ev~0_18} AuxVars[] AssignedVars[~d1_ev~0] 2408#L359-3 [531] L359-3-->L364-3: Formula: (and (= v_~z_ev~0_15 1) (= v_~z_ev~0_14 2)) InVars {~z_ev~0=v_~z_ev~0_15} OutVars{~z_ev~0=v_~z_ev~0_14} AuxVars[] AssignedVars[~z_ev~0] 2428#L364-3 [568] L364-3-->L258-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_5, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_2|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_#res] 2459#L258-1 [666] L258-1-->L265-1: Formula: (and (= v_~comp_m1_st~0_10 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9 1)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_10} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9, ~comp_m1_st~0=v_~comp_m1_st~0_10} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 2454#L265-1 [892] L265-1-->L397: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_stop_simulation_~tmp~2_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_4|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_~tmp~2] 2455#L397 [880] L397-->L404: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_4 0) (< 0 v_ULTIMATE.start_stop_simulation_~tmp~2_5)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_4, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 2458#L404 [897] L404-->L422-1: Formula: (and (= 0 v_ULTIMATE.start_start_simulation_~tmp~3_9) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= |v_ULTIMATE.start_stop_simulation_#res_5| v_ULTIMATE.start_start_simulation_~tmp~3_9)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_~tmp~3] 2451#L422-1 54.07/20.05 [2019-03-28 12:18:50,852 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.05 [2019-03-28 12:18:50,852 INFO L82 PathProgramCache]: Analyzing trace with hash 1643943553, now seen corresponding path program 1 times 54.07/20.05 [2019-03-28 12:18:50,852 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.05 [2019-03-28 12:18:50,852 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.05 [2019-03-28 12:18:50,853 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:50,853 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:50,854 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:50,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.05 [2019-03-28 12:18:50,871 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.05 [2019-03-28 12:18:50,871 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.05 [2019-03-28 12:18:50,871 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 54.07/20.05 [2019-03-28 12:18:50,871 INFO L799 eck$LassoCheckResult]: stem already infeasible 54.07/20.05 [2019-03-28 12:18:50,872 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.05 [2019-03-28 12:18:50,872 INFO L82 PathProgramCache]: Analyzing trace with hash -1145452622, now seen corresponding path program 2 times 54.07/20.05 [2019-03-28 12:18:50,872 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.05 [2019-03-28 12:18:50,872 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.05 [2019-03-28 12:18:50,873 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:50,873 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:50,873 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:50,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.05 [2019-03-28 12:18:50,888 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.05 [2019-03-28 12:18:50,889 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.05 [2019-03-28 12:18:50,889 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 54.07/20.05 [2019-03-28 12:18:50,889 INFO L811 eck$LassoCheckResult]: loop already infeasible 54.07/20.05 [2019-03-28 12:18:50,889 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 54.07/20.05 [2019-03-28 12:18:50,889 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 54.07/20.05 [2019-03-28 12:18:50,890 INFO L87 Difference]: Start difference. First operand 90 states and 206 transitions. cyclomatic complexity: 117 Second operand 3 states. 54.07/20.05 [2019-03-28 12:18:51,085 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 54.07/20.05 [2019-03-28 12:18:51,086 INFO L93 Difference]: Finished difference Result 90 states and 204 transitions. 54.07/20.05 [2019-03-28 12:18:51,086 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 54.07/20.05 [2019-03-28 12:18:51,086 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 90 states and 204 transitions. 54.07/20.05 [2019-03-28 12:18:51,087 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 56 54.07/20.05 [2019-03-28 12:18:51,088 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 90 states to 90 states and 204 transitions. 54.07/20.05 [2019-03-28 12:18:51,088 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 90 54.07/20.05 [2019-03-28 12:18:51,089 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 90 54.07/20.05 [2019-03-28 12:18:51,089 INFO L73 IsDeterministic]: Start isDeterministic. Operand 90 states and 204 transitions. 54.07/20.05 [2019-03-28 12:18:51,089 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 54.07/20.05 [2019-03-28 12:18:51,089 INFO L706 BuchiCegarLoop]: Abstraction has 90 states and 204 transitions. 54.07/20.05 [2019-03-28 12:18:51,089 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90 states and 204 transitions. 54.07/20.05 [2019-03-28 12:18:51,091 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90 to 90. 54.07/20.05 [2019-03-28 12:18:51,091 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 90 states. 54.07/20.05 [2019-03-28 12:18:51,092 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90 states to 90 states and 204 transitions. 54.07/20.05 [2019-03-28 12:18:51,092 INFO L729 BuchiCegarLoop]: Abstraction has 90 states and 204 transitions. 54.07/20.05 [2019-03-28 12:18:51,092 INFO L609 BuchiCegarLoop]: Abstraction has 90 states and 204 transitions. 54.07/20.05 [2019-03-28 12:18:51,092 INFO L442 BuchiCegarLoop]: ======== Iteration 13============ 54.07/20.05 [2019-03-28 12:18:51,092 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 90 states and 204 transitions. 54.07/20.05 [2019-03-28 12:18:51,093 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 56 54.07/20.05 [2019-03-28 12:18:51,093 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 54.07/20.05 [2019-03-28 12:18:51,093 INFO L119 BuchiIsEmpty]: Starting construction of run 54.07/20.05 [2019-03-28 12:18:51,094 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.05 [2019-03-28 12:18:51,094 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.05 [2019-03-28 12:18:51,095 INFO L794 eck$LassoCheckResult]: Stem: 2632#ULTIMATE.startENTRY [885] ULTIMATE.startENTRY-->L202: Formula: (and (= v_~d0_ev~0_23 2) (= 0 v_~z_val~0_13) (= 2 v_~b1_ev~0_23) (= v_~d0_val_t~0_9 1) (= v_~b0_val~0_13 0) (= 1 v_~b1_val_t~0_9) (= 1 v_~d1_req_up~0_12) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_9 0) (= 2 v_~d1_ev~0_23) (= v_~b1_val~0_13 0) (= v_~b0_val_t~0_9 1) (= v_~b0_req_up~0_12 1) (= 0 v_~comp_m1_i~0_7) (= v_~d0_req_up~0_12 1) (= v_~comp_m1_st~0_15 0) (= v_~b0_ev~0_23 2) (= 1 v_~d1_val_t~0_9) (= v_~z_req_up~0_12 0) (= v_~z_val_t~0_10 0) (= 0 v_~d1_val~0_13) (= v_~z_ev~0_19 2) (= v_~b1_req_up~0_12 1) (= 0 v_~d0_val~0_13)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_4|, ~b1_val~0=v_~b1_val~0_13, ~b0_val~0=v_~b0_val~0_13, ~d0_req_up~0=v_~d0_req_up~0_12, ~d0_val~0=v_~d0_val~0_13, ~d1_val_t~0=v_~d1_val_t~0_9, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_9, ~d1_ev~0=v_~d1_ev~0_23, ~d1_val~0=v_~d1_val~0_13, ~b0_req_up~0=v_~b0_req_up~0_12, ~z_ev~0=v_~z_ev~0_19, ~b1_val_t~0=v_~b1_val_t~0_9, ~b1_ev~0=v_~b1_ev~0_23, ULTIMATE.start_main_~__retres1~2=v_ULTIMATE.start_main_~__retres1~2_6, ~z_val~0=v_~z_val~0_13, ~d1_req_up~0=v_~d1_req_up~0_12, ~z_val_t~0=v_~z_val_t~0_10, ~b0_val_t~0=v_~b0_val_t~0_9, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~z_req_up~0=v_~z_req_up~0_12, ~b1_req_up~0=v_~b1_req_up~0_12, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~d0_ev~0=v_~d0_ev~0_23, ~b0_ev~0=v_~b0_ev~0_23, ~d0_val_t~0=v_~d0_val_t~0_9, ~comp_m1_st~0=v_~comp_m1_st~0_15, ~comp_m1_i~0=v_~comp_m1_i~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ~b1_val~0, ~b0_val~0, ~d0_req_up~0, ~d0_val~0, ~d1_val_t~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~d1_ev~0, ~d1_val~0, ~b0_req_up~0, ~z_ev~0, ~b1_val_t~0, ~b1_ev~0, ULTIMATE.start_main_~__retres1~2, ~z_val~0, ~d1_req_up~0, ~z_val_t~0, ~b0_val_t~0, ULTIMATE.start_start_simulation_~tmp~3, ~z_req_up~0, ~b1_req_up~0, ULTIMATE.start_main_#res, ~d0_ev~0, ~b0_ev~0, ~d0_val_t~0, ~comp_m1_st~0, ~comp_m1_i~0] 2633#L202 [566] L202-->L127: Formula: (= 1 v_~b0_req_up~0_4) InVars {~b0_req_up~0=v_~b0_req_up~0_4} OutVars{~b0_req_up~0=v_~b0_req_up~0_4} AuxVars[] AssignedVars[] 2596#L127 [748] L127-->L127-2: Formula: (and (= v_~b0_val~0_3 v_~b0_val_t~0_3) (> v_~b0_val_t~0_3 v_~b0_val~0_4) (= v_~b0_ev~0_3 0)) InVars {~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_4} OutVars{~b0_ev~0=v_~b0_ev~0_3, ~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_3} AuxVars[] AssignedVars[~b0_val~0, ~b0_ev~0] 2597#L127-2 [580] L127-2-->L202-1: Formula: (= v_~b0_req_up~0_5 0) InVars {} OutVars{~b0_req_up~0=v_~b0_req_up~0_5} AuxVars[] AssignedVars[~b0_req_up~0] 2628#L202-1 [545] L202-1-->L142: Formula: (= 1 v_~b1_req_up~0_4) InVars {~b1_req_up~0=v_~b1_req_up~0_4} OutVars{~b1_req_up~0=v_~b1_req_up~0_4} AuxVars[] AssignedVars[] 2613#L142 [752] L142-->L142-2: Formula: (and (= v_~b1_ev~0_3 0) (< v_~b1_val~0_4 v_~b1_val_t~0_3) (= v_~b1_val~0_3 v_~b1_val_t~0_3)) InVars {~b1_val_t~0=v_~b1_val_t~0_3, ~b1_val~0=v_~b1_val~0_4} OutVars{~b1_val_t~0=v_~b1_val_t~0_3, ~b1_ev~0=v_~b1_ev~0_3, ~b1_val~0=v_~b1_val~0_3} AuxVars[] AssignedVars[~b1_val~0, ~b1_ev~0] 2604#L142-2 [521] L142-2-->L209: Formula: (= v_~b1_req_up~0_5 0) InVars {} OutVars{~b1_req_up~0=v_~b1_req_up~0_5} AuxVars[] AssignedVars[~b1_req_up~0] 2605#L209 [624] L209-->L157: Formula: (= v_~d0_req_up~0_4 1) InVars {~d0_req_up~0=v_~d0_req_up~0_4} OutVars{~d0_req_up~0=v_~d0_req_up~0_4} AuxVars[] AssignedVars[] 2583#L157 [757] L157-->L157-2: Formula: (and (> v_~d0_val_t~0_3 v_~d0_val~0_4) (= v_~d0_val~0_3 v_~d0_val_t~0_3) (= v_~d0_ev~0_3 0)) InVars {~d0_val~0=v_~d0_val~0_4, ~d0_val_t~0=v_~d0_val_t~0_3} OutVars{~d0_ev~0=v_~d0_ev~0_3, ~d0_val~0=v_~d0_val~0_3, ~d0_val_t~0=v_~d0_val_t~0_3} AuxVars[] AssignedVars[~d0_ev~0, ~d0_val~0] 2574#L157-2 [600] L157-2-->L216: Formula: (= v_~d0_req_up~0_5 0) InVars {} OutVars{~d0_req_up~0=v_~d0_req_up~0_5} AuxVars[] AssignedVars[~d0_req_up~0] 2575#L216 [554] L216-->L172: Formula: (= v_~d1_req_up~0_4 1) InVars {~d1_req_up~0=v_~d1_req_up~0_4} OutVars{~d1_req_up~0=v_~d1_req_up~0_4} AuxVars[] AssignedVars[] 2637#L172 [760] L172-->L172-2: Formula: (and (= v_~d1_val~0_3 v_~d1_val_t~0_3) (= v_~d1_ev~0_3 0) (> v_~d1_val_t~0_3 v_~d1_val~0_4)) InVars {~d1_val_t~0=v_~d1_val_t~0_3, ~d1_val~0=v_~d1_val~0_4} OutVars{~d1_val_t~0=v_~d1_val_t~0_3, ~d1_val~0=v_~d1_val~0_3, ~d1_ev~0=v_~d1_ev~0_3} AuxVars[] AssignedVars[~d1_val~0, ~d1_ev~0] 2631#L172-2 [547] L172-2-->L223: Formula: (= v_~d1_req_up~0_5 0) InVars {} OutVars{~d1_req_up~0=v_~d1_req_up~0_5} AuxVars[] AssignedVars[~d1_req_up~0] 2630#L223 [763] L223-->L230: Formula: (< 1 v_~z_req_up~0_6) InVars {~z_req_up~0=v_~z_req_up~0_6} OutVars{~z_req_up~0=v_~z_req_up~0_6} AuxVars[] AssignedVars[] 2576#L230 [767] L230-->L245-1: Formula: (and (> 1 v_~comp_m1_i~0_4) (= v_~comp_m1_st~0_5 2)) InVars {~comp_m1_i~0=v_~comp_m1_i~0_4} OutVars{~comp_m1_st~0=v_~comp_m1_st~0_5, ~comp_m1_i~0=v_~comp_m1_i~0_4} AuxVars[] AssignedVars[~comp_m1_st~0] 2577#L245-1 [769] L245-1-->L311-1: Formula: (> v_~b0_ev~0_7 0) InVars {~b0_ev~0=v_~b0_ev~0_7} OutVars{~b0_ev~0=v_~b0_ev~0_7} AuxVars[] AssignedVars[] 2593#L311-1 [628] L311-1-->L316-1: Formula: (and (= 0 v_~b1_ev~0_6) (= v_~b1_ev~0_5 1)) InVars {~b1_ev~0=v_~b1_ev~0_6} OutVars{~b1_ev~0=v_~b1_ev~0_5} AuxVars[] AssignedVars[~b1_ev~0] 2624#L316-1 [654] L316-1-->L321-1: Formula: (and (= v_~d0_ev~0_5 1) (= v_~d0_ev~0_6 0)) InVars {~d0_ev~0=v_~d0_ev~0_6} OutVars{~d0_ev~0=v_~d0_ev~0_5} AuxVars[] AssignedVars[~d0_ev~0] 2586#L321-1 [507] L321-1-->L326-1: Formula: (and (= 0 v_~d1_ev~0_6) (= v_~d1_ev~0_5 1)) InVars {~d1_ev~0=v_~d1_ev~0_6} OutVars{~d1_ev~0=v_~d1_ev~0_5} AuxVars[] AssignedVars[~d1_ev~0] 2587#L326-1 [556] L326-1-->L331-1: Formula: (and (= 0 v_~z_ev~0_6) (= v_~z_ev~0_5 1)) InVars {~z_ev~0=v_~z_ev~0_6} OutVars{~z_ev~0=v_~z_ev~0_5} AuxVars[] AssignedVars[~z_ev~0] 2639#L331-1 [583] L331-1-->L97: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_1|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 2652#L97 [591] L97-->L119: Formula: (and (= v_~b0_ev~0_11 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4 1)) InVars {~b0_ev~0=v_~b0_ev~0_11} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4, ~b0_ev~0=v_~b0_ev~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 2611#L119 [886] L119-->L380: Formula: (and (= |v_ULTIMATE.start_is_method1_triggered_#res_7| v_ULTIMATE.start_activate_threads_~tmp~1_13) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19 |v_ULTIMATE.start_is_method1_triggered_#res_7|)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_13, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_7|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_7|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 2608#L380 [615] L380-->L380-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_9) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} AuxVars[] AssignedVars[] 2609#L380-2 [618] L380-2-->L344-1: Formula: (and (= v_~b0_ev~0_15 2) (= v_~b0_ev~0_16 1)) InVars {~b0_ev~0=v_~b0_ev~0_16} OutVars{~b0_ev~0=v_~b0_ev~0_15} AuxVars[] AssignedVars[~b0_ev~0] 2614#L344-1 [791] L344-1-->L349-1: Formula: (> 1 v_~b1_ev~0_17) InVars {~b1_ev~0=v_~b1_ev~0_17} OutVars{~b1_ev~0=v_~b1_ev~0_17} AuxVars[] AssignedVars[] 2622#L349-1 [652] L349-1-->L354-1: Formula: (and (= v_~d0_ev~0_15 2) (= v_~d0_ev~0_16 1)) InVars {~d0_ev~0=v_~d0_ev~0_16} OutVars{~d0_ev~0=v_~d0_ev~0_15} AuxVars[] AssignedVars[~d0_ev~0] 2581#L354-1 [795] L354-1-->L359-1: Formula: (> 1 v_~d1_ev~0_17) InVars {~d1_ev~0=v_~d1_ev~0_17} OutVars{~d1_ev~0=v_~d1_ev~0_17} AuxVars[] AssignedVars[] 2582#L359-1 [797] L359-1-->L422-1: Formula: (> v_~z_ev~0_13 1) InVars {~z_ev~0=v_~z_ev~0_13} OutVars{~z_ev~0=v_~z_ev~0_13} AuxVars[] AssignedVars[] 2638#L422-1 54.07/20.05 [2019-03-28 12:18:51,095 INFO L796 eck$LassoCheckResult]: Loop: 2638#L422-1 [887] L422-1-->L285: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 1) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 2584#L285 [888] L285-->L258: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_13, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res] 2585#L258 [802] L258-->L265: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8 0) (> 0 v_~comp_m1_st~0_9)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_9} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8, ~comp_m1_st~0=v_~comp_m1_st~0_9} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 2643#L265 [889] L265-->L280: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___0~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 2644#L280 [890] L280-->L202-2: Formula: (and (= v_ULTIMATE.start_eval_~tmp___0~0_8 0) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 2)) InVars {ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 2625#L202-2 [800] L202-2-->L202-3: Formula: (> 1 v_~b0_req_up~0_9) InVars {~b0_req_up~0=v_~b0_req_up~0_9} OutVars{~b0_req_up~0=v_~b0_req_up~0_9} AuxVars[] AssignedVars[] 2623#L202-3 [807] L202-3-->L209-1: Formula: (> 1 v_~b1_req_up~0_9) InVars {~b1_req_up~0=v_~b1_req_up~0_9} OutVars{~b1_req_up~0=v_~b1_req_up~0_9} AuxVars[] AssignedVars[] 2616#L209-1 [811] L209-1-->L216-1: Formula: (< v_~d0_req_up~0_9 1) InVars {~d0_req_up~0=v_~d0_req_up~0_9} OutVars{~d0_req_up~0=v_~d0_req_up~0_9} AuxVars[] AssignedVars[] 2612#L216-1 [815] L216-1-->L223-1: Formula: (< v_~d1_req_up~0_9 1) InVars {~d1_req_up~0=v_~d1_req_up~0_9} OutVars{~d1_req_up~0=v_~d1_req_up~0_9} AuxVars[] AssignedVars[] 2580#L223-1 [820] L223-1-->L230-1: Formula: (< 1 v_~z_req_up~0_9) InVars {~z_req_up~0=v_~z_req_up~0_9} OutVars{~z_req_up~0=v_~z_req_up~0_9} AuxVars[] AssignedVars[] 2569#L230-1 [498] L230-1-->L311-2: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 3) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 2570#L311-2 [632] L311-2-->L311-4: Formula: (and (= v_~b0_ev~0_8 1) (= v_~b0_ev~0_9 0)) InVars {~b0_ev~0=v_~b0_ev~0_9} OutVars{~b0_ev~0=v_~b0_ev~0_8} AuxVars[] AssignedVars[~b0_ev~0] 2598#L311-4 [832] L311-4-->L316-3: Formula: (> 0 v_~b1_ev~0_10) InVars {~b1_ev~0=v_~b1_ev~0_10} OutVars{~b1_ev~0=v_~b1_ev~0_10} AuxVars[] AssignedVars[] 2599#L316-3 [838] L316-3-->L321-3: Formula: (< v_~d0_ev~0_10 0) InVars {~d0_ev~0=v_~d0_ev~0_10} OutVars{~d0_ev~0=v_~d0_ev~0_10} AuxVars[] AssignedVars[] 2640#L321-3 [662] L321-3-->L326-3: Formula: (and (= v_~d1_ev~0_8 1) (= 0 v_~d1_ev~0_9)) InVars {~d1_ev~0=v_~d1_ev~0_9} OutVars{~d1_ev~0=v_~d1_ev~0_8} AuxVars[] AssignedVars[~d1_ev~0] 2617#L326-3 [850] L326-3-->L331-3: Formula: (> v_~z_ev~0_10 0) InVars {~z_ev~0=v_~z_ev~0_10} OutVars{~z_ev~0=v_~z_ev~0_10} AuxVars[] AssignedVars[] 2618#L331-3 [570] L331-3-->L97-1: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_4|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_10, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 2647#L97-1 [588] L97-1-->L119-1: Formula: (and (= v_~b0_ev~0_13 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13 1)) InVars {~b0_ev~0=v_~b0_ev~0_13} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13, ~b0_ev~0=v_~b0_ev~0_13} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 2607#L119-1 [891] L119-1-->L380-3: Formula: (and (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20 |v_ULTIMATE.start_is_method1_triggered_#res_8|) (= |v_ULTIMATE.start_is_method1_triggered_#res_8| v_ULTIMATE.start_activate_threads_~tmp~1_14)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_14, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_8|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_8|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 2567#L380-3 [864] L380-3-->L380-5: Formula: (and (= v_~comp_m1_st~0_7 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11, ~comp_m1_st~0=v_~comp_m1_st~0_7} AuxVars[] AssignedVars[~comp_m1_st~0] 2568#L380-5 [868] L380-5-->L344-3: Formula: (< v_~b0_ev~0_20 1) InVars {~b0_ev~0=v_~b0_ev~0_20} OutVars{~b0_ev~0=v_~b0_ev~0_20} AuxVars[] AssignedVars[] 2578#L344-3 [870] L344-3-->L349-3: Formula: (< 1 v_~b1_ev~0_20) InVars {~b1_ev~0=v_~b1_ev~0_20} OutVars{~b1_ev~0=v_~b1_ev~0_20} AuxVars[] AssignedVars[] 2627#L349-3 [656] L349-3-->L354-3: Formula: (and (= v_~d0_ev~0_18 2) (= v_~d0_ev~0_19 1)) InVars {~d0_ev~0=v_~d0_ev~0_19} OutVars{~d0_ev~0=v_~d0_ev~0_18} AuxVars[] AssignedVars[~d0_ev~0] 2594#L354-3 [513] L354-3-->L359-3: Formula: (and (= 1 v_~d1_ev~0_19) (= v_~d1_ev~0_18 2)) InVars {~d1_ev~0=v_~d1_ev~0_19} OutVars{~d1_ev~0=v_~d1_ev~0_18} AuxVars[] AssignedVars[~d1_ev~0] 2595#L359-3 [531] L359-3-->L364-3: Formula: (and (= v_~z_ev~0_15 1) (= v_~z_ev~0_14 2)) InVars {~z_ev~0=v_~z_ev~0_15} OutVars{~z_ev~0=v_~z_ev~0_14} AuxVars[] AssignedVars[~z_ev~0] 2615#L364-3 [568] L364-3-->L258-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_5, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_2|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_#res] 2646#L258-1 [666] L258-1-->L265-1: Formula: (and (= v_~comp_m1_st~0_10 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9 1)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_10} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9, ~comp_m1_st~0=v_~comp_m1_st~0_10} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 2641#L265-1 [892] L265-1-->L397: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_stop_simulation_~tmp~2_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_4|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_~tmp~2] 2642#L397 [880] L397-->L404: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_4 0) (< 0 v_ULTIMATE.start_stop_simulation_~tmp~2_5)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_4, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 2645#L404 [897] L404-->L422-1: Formula: (and (= 0 v_ULTIMATE.start_start_simulation_~tmp~3_9) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= |v_ULTIMATE.start_stop_simulation_#res_5| v_ULTIMATE.start_start_simulation_~tmp~3_9)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_~tmp~3] 2638#L422-1 54.07/20.05 [2019-03-28 12:18:51,096 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.05 [2019-03-28 12:18:51,096 INFO L82 PathProgramCache]: Analyzing trace with hash -1653951390, now seen corresponding path program 1 times 54.07/20.05 [2019-03-28 12:18:51,096 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.05 [2019-03-28 12:18:51,096 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.05 [2019-03-28 12:18:51,097 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:51,097 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:51,097 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:51,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.05 [2019-03-28 12:18:51,113 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.05 [2019-03-28 12:18:51,113 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.05 [2019-03-28 12:18:51,114 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 54.07/20.05 [2019-03-28 12:18:51,114 INFO L799 eck$LassoCheckResult]: stem already infeasible 54.07/20.05 [2019-03-28 12:18:51,114 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.05 [2019-03-28 12:18:51,114 INFO L82 PathProgramCache]: Analyzing trace with hash -1145452622, now seen corresponding path program 3 times 54.07/20.05 [2019-03-28 12:18:51,114 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.05 [2019-03-28 12:18:51,114 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.05 [2019-03-28 12:18:51,115 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:51,115 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:51,116 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:51,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.05 [2019-03-28 12:18:51,143 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.05 [2019-03-28 12:18:51,144 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.05 [2019-03-28 12:18:51,144 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 54.07/20.05 [2019-03-28 12:18:51,144 INFO L811 eck$LassoCheckResult]: loop already infeasible 54.07/20.05 [2019-03-28 12:18:51,144 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 54.07/20.05 [2019-03-28 12:18:51,145 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 54.07/20.05 [2019-03-28 12:18:51,145 INFO L87 Difference]: Start difference. First operand 90 states and 204 transitions. cyclomatic complexity: 115 Second operand 3 states. 54.07/20.05 [2019-03-28 12:18:51,379 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 54.07/20.05 [2019-03-28 12:18:51,380 INFO L93 Difference]: Finished difference Result 142 states and 326 transitions. 54.07/20.05 [2019-03-28 12:18:51,380 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 54.07/20.05 [2019-03-28 12:18:51,380 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 142 states and 326 transitions. 54.07/20.05 [2019-03-28 12:18:51,382 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 110 54.07/20.05 [2019-03-28 12:18:51,383 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 142 states to 142 states and 326 transitions. 54.07/20.05 [2019-03-28 12:18:51,383 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 142 54.07/20.05 [2019-03-28 12:18:51,383 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 142 54.07/20.05 [2019-03-28 12:18:51,384 INFO L73 IsDeterministic]: Start isDeterministic. Operand 142 states and 326 transitions. 54.07/20.05 [2019-03-28 12:18:51,384 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 54.07/20.05 [2019-03-28 12:18:51,384 INFO L706 BuchiCegarLoop]: Abstraction has 142 states and 326 transitions. 54.07/20.05 [2019-03-28 12:18:51,384 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 142 states and 326 transitions. 54.07/20.05 [2019-03-28 12:18:51,387 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 142 to 131. 54.07/20.05 [2019-03-28 12:18:51,388 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 131 states. 54.07/20.05 [2019-03-28 12:18:51,388 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 131 states to 131 states and 295 transitions. 54.07/20.05 [2019-03-28 12:18:51,388 INFO L729 BuchiCegarLoop]: Abstraction has 131 states and 295 transitions. 54.07/20.05 [2019-03-28 12:18:51,389 INFO L609 BuchiCegarLoop]: Abstraction has 131 states and 295 transitions. 54.07/20.05 [2019-03-28 12:18:51,389 INFO L442 BuchiCegarLoop]: ======== Iteration 14============ 54.07/20.05 [2019-03-28 12:18:51,389 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 131 states and 295 transitions. 54.07/20.05 [2019-03-28 12:18:51,390 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 99 54.07/20.05 [2019-03-28 12:18:51,390 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 54.07/20.05 [2019-03-28 12:18:51,390 INFO L119 BuchiIsEmpty]: Starting construction of run 54.07/20.05 [2019-03-28 12:18:51,391 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.05 [2019-03-28 12:18:51,391 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.05 [2019-03-28 12:18:51,392 INFO L794 eck$LassoCheckResult]: Stem: 2870#ULTIMATE.startENTRY [885] ULTIMATE.startENTRY-->L202: Formula: (and (= v_~d0_ev~0_23 2) (= 0 v_~z_val~0_13) (= 2 v_~b1_ev~0_23) (= v_~d0_val_t~0_9 1) (= v_~b0_val~0_13 0) (= 1 v_~b1_val_t~0_9) (= 1 v_~d1_req_up~0_12) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_9 0) (= 2 v_~d1_ev~0_23) (= v_~b1_val~0_13 0) (= v_~b0_val_t~0_9 1) (= v_~b0_req_up~0_12 1) (= 0 v_~comp_m1_i~0_7) (= v_~d0_req_up~0_12 1) (= v_~comp_m1_st~0_15 0) (= v_~b0_ev~0_23 2) (= 1 v_~d1_val_t~0_9) (= v_~z_req_up~0_12 0) (= v_~z_val_t~0_10 0) (= 0 v_~d1_val~0_13) (= v_~z_ev~0_19 2) (= v_~b1_req_up~0_12 1) (= 0 v_~d0_val~0_13)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_4|, ~b1_val~0=v_~b1_val~0_13, ~b0_val~0=v_~b0_val~0_13, ~d0_req_up~0=v_~d0_req_up~0_12, ~d0_val~0=v_~d0_val~0_13, ~d1_val_t~0=v_~d1_val_t~0_9, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_9, ~d1_ev~0=v_~d1_ev~0_23, ~d1_val~0=v_~d1_val~0_13, ~b0_req_up~0=v_~b0_req_up~0_12, ~z_ev~0=v_~z_ev~0_19, ~b1_val_t~0=v_~b1_val_t~0_9, ~b1_ev~0=v_~b1_ev~0_23, ULTIMATE.start_main_~__retres1~2=v_ULTIMATE.start_main_~__retres1~2_6, ~z_val~0=v_~z_val~0_13, ~d1_req_up~0=v_~d1_req_up~0_12, ~z_val_t~0=v_~z_val_t~0_10, ~b0_val_t~0=v_~b0_val_t~0_9, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~z_req_up~0=v_~z_req_up~0_12, ~b1_req_up~0=v_~b1_req_up~0_12, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~d0_ev~0=v_~d0_ev~0_23, ~b0_ev~0=v_~b0_ev~0_23, ~d0_val_t~0=v_~d0_val_t~0_9, ~comp_m1_st~0=v_~comp_m1_st~0_15, ~comp_m1_i~0=v_~comp_m1_i~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ~b1_val~0, ~b0_val~0, ~d0_req_up~0, ~d0_val~0, ~d1_val_t~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~d1_ev~0, ~d1_val~0, ~b0_req_up~0, ~z_ev~0, ~b1_val_t~0, ~b1_ev~0, ULTIMATE.start_main_~__retres1~2, ~z_val~0, ~d1_req_up~0, ~z_val_t~0, ~b0_val_t~0, ULTIMATE.start_start_simulation_~tmp~3, ~z_req_up~0, ~b1_req_up~0, ULTIMATE.start_main_#res, ~d0_ev~0, ~b0_ev~0, ~d0_val_t~0, ~comp_m1_st~0, ~comp_m1_i~0] 2871#L202 [566] L202-->L127: Formula: (= 1 v_~b0_req_up~0_4) InVars {~b0_req_up~0=v_~b0_req_up~0_4} OutVars{~b0_req_up~0=v_~b0_req_up~0_4} AuxVars[] AssignedVars[] 2835#L127 [748] L127-->L127-2: Formula: (and (= v_~b0_val~0_3 v_~b0_val_t~0_3) (> v_~b0_val_t~0_3 v_~b0_val~0_4) (= v_~b0_ev~0_3 0)) InVars {~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_4} OutVars{~b0_ev~0=v_~b0_ev~0_3, ~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_3} AuxVars[] AssignedVars[~b0_val~0, ~b0_ev~0] 2836#L127-2 [580] L127-2-->L202-1: Formula: (= v_~b0_req_up~0_5 0) InVars {} OutVars{~b0_req_up~0=v_~b0_req_up~0_5} AuxVars[] AssignedVars[~b0_req_up~0] 2866#L202-1 [545] L202-1-->L142: Formula: (= 1 v_~b1_req_up~0_4) InVars {~b1_req_up~0=v_~b1_req_up~0_4} OutVars{~b1_req_up~0=v_~b1_req_up~0_4} AuxVars[] AssignedVars[] 2852#L142 [752] L142-->L142-2: Formula: (and (= v_~b1_ev~0_3 0) (< v_~b1_val~0_4 v_~b1_val_t~0_3) (= v_~b1_val~0_3 v_~b1_val_t~0_3)) InVars {~b1_val_t~0=v_~b1_val_t~0_3, ~b1_val~0=v_~b1_val~0_4} OutVars{~b1_val_t~0=v_~b1_val_t~0_3, ~b1_ev~0=v_~b1_ev~0_3, ~b1_val~0=v_~b1_val~0_3} AuxVars[] AssignedVars[~b1_val~0, ~b1_ev~0] 2843#L142-2 [521] L142-2-->L209: Formula: (= v_~b1_req_up~0_5 0) InVars {} OutVars{~b1_req_up~0=v_~b1_req_up~0_5} AuxVars[] AssignedVars[~b1_req_up~0] 2844#L209 [624] L209-->L157: Formula: (= v_~d0_req_up~0_4 1) InVars {~d0_req_up~0=v_~d0_req_up~0_4} OutVars{~d0_req_up~0=v_~d0_req_up~0_4} AuxVars[] AssignedVars[] 2822#L157 [757] L157-->L157-2: Formula: (and (> v_~d0_val_t~0_3 v_~d0_val~0_4) (= v_~d0_val~0_3 v_~d0_val_t~0_3) (= v_~d0_ev~0_3 0)) InVars {~d0_val~0=v_~d0_val~0_4, ~d0_val_t~0=v_~d0_val_t~0_3} OutVars{~d0_ev~0=v_~d0_ev~0_3, ~d0_val~0=v_~d0_val~0_3, ~d0_val_t~0=v_~d0_val_t~0_3} AuxVars[] AssignedVars[~d0_ev~0, ~d0_val~0] 2813#L157-2 [600] L157-2-->L216: Formula: (= v_~d0_req_up~0_5 0) InVars {} OutVars{~d0_req_up~0=v_~d0_req_up~0_5} AuxVars[] AssignedVars[~d0_req_up~0] 2814#L216 [554] L216-->L172: Formula: (= v_~d1_req_up~0_4 1) InVars {~d1_req_up~0=v_~d1_req_up~0_4} OutVars{~d1_req_up~0=v_~d1_req_up~0_4} AuxVars[] AssignedVars[] 2875#L172 [760] L172-->L172-2: Formula: (and (= v_~d1_val~0_3 v_~d1_val_t~0_3) (= v_~d1_ev~0_3 0) (> v_~d1_val_t~0_3 v_~d1_val~0_4)) InVars {~d1_val_t~0=v_~d1_val_t~0_3, ~d1_val~0=v_~d1_val~0_4} OutVars{~d1_val_t~0=v_~d1_val_t~0_3, ~d1_val~0=v_~d1_val~0_3, ~d1_ev~0=v_~d1_ev~0_3} AuxVars[] AssignedVars[~d1_val~0, ~d1_ev~0] 2869#L172-2 [547] L172-2-->L223: Formula: (= v_~d1_req_up~0_5 0) InVars {} OutVars{~d1_req_up~0=v_~d1_req_up~0_5} AuxVars[] AssignedVars[~d1_req_up~0] 2868#L223 [762] L223-->L230: Formula: (> 1 v_~z_req_up~0_6) InVars {~z_req_up~0=v_~z_req_up~0_6} OutVars{~z_req_up~0=v_~z_req_up~0_6} AuxVars[] AssignedVars[] 2815#L230 [767] L230-->L245-1: Formula: (and (> 1 v_~comp_m1_i~0_4) (= v_~comp_m1_st~0_5 2)) InVars {~comp_m1_i~0=v_~comp_m1_i~0_4} OutVars{~comp_m1_st~0=v_~comp_m1_st~0_5, ~comp_m1_i~0=v_~comp_m1_i~0_4} AuxVars[] AssignedVars[~comp_m1_st~0] 2816#L245-1 [769] L245-1-->L311-1: Formula: (> v_~b0_ev~0_7 0) InVars {~b0_ev~0=v_~b0_ev~0_7} OutVars{~b0_ev~0=v_~b0_ev~0_7} AuxVars[] AssignedVars[] 2832#L311-1 [628] L311-1-->L316-1: Formula: (and (= 0 v_~b1_ev~0_6) (= v_~b1_ev~0_5 1)) InVars {~b1_ev~0=v_~b1_ev~0_6} OutVars{~b1_ev~0=v_~b1_ev~0_5} AuxVars[] AssignedVars[~b1_ev~0] 2862#L316-1 [654] L316-1-->L321-1: Formula: (and (= v_~d0_ev~0_5 1) (= v_~d0_ev~0_6 0)) InVars {~d0_ev~0=v_~d0_ev~0_6} OutVars{~d0_ev~0=v_~d0_ev~0_5} AuxVars[] AssignedVars[~d0_ev~0] 2825#L321-1 [507] L321-1-->L326-1: Formula: (and (= 0 v_~d1_ev~0_6) (= v_~d1_ev~0_5 1)) InVars {~d1_ev~0=v_~d1_ev~0_6} OutVars{~d1_ev~0=v_~d1_ev~0_5} AuxVars[] AssignedVars[~d1_ev~0] 2826#L326-1 [556] L326-1-->L331-1: Formula: (and (= 0 v_~z_ev~0_6) (= v_~z_ev~0_5 1)) InVars {~z_ev~0=v_~z_ev~0_6} OutVars{~z_ev~0=v_~z_ev~0_5} AuxVars[] AssignedVars[~z_ev~0] 2878#L331-1 [583] L331-1-->L97: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_1|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 2893#L97 [591] L97-->L119: Formula: (and (= v_~b0_ev~0_11 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4 1)) InVars {~b0_ev~0=v_~b0_ev~0_11} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4, ~b0_ev~0=v_~b0_ev~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 2850#L119 [886] L119-->L380: Formula: (and (= |v_ULTIMATE.start_is_method1_triggered_#res_7| v_ULTIMATE.start_activate_threads_~tmp~1_13) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19 |v_ULTIMATE.start_is_method1_triggered_#res_7|)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_13, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_7|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_7|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 2847#L380 [615] L380-->L380-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_9) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} AuxVars[] AssignedVars[] 2848#L380-2 [618] L380-2-->L344-1: Formula: (and (= v_~b0_ev~0_15 2) (= v_~b0_ev~0_16 1)) InVars {~b0_ev~0=v_~b0_ev~0_16} OutVars{~b0_ev~0=v_~b0_ev~0_15} AuxVars[] AssignedVars[~b0_ev~0] 2853#L344-1 [791] L344-1-->L349-1: Formula: (> 1 v_~b1_ev~0_17) InVars {~b1_ev~0=v_~b1_ev~0_17} OutVars{~b1_ev~0=v_~b1_ev~0_17} AuxVars[] AssignedVars[] 2860#L349-1 [652] L349-1-->L354-1: Formula: (and (= v_~d0_ev~0_15 2) (= v_~d0_ev~0_16 1)) InVars {~d0_ev~0=v_~d0_ev~0_16} OutVars{~d0_ev~0=v_~d0_ev~0_15} AuxVars[] AssignedVars[~d0_ev~0] 2820#L354-1 [795] L354-1-->L359-1: Formula: (> 1 v_~d1_ev~0_17) InVars {~d1_ev~0=v_~d1_ev~0_17} OutVars{~d1_ev~0=v_~d1_ev~0_17} AuxVars[] AssignedVars[] 2821#L359-1 [797] L359-1-->L422-1: Formula: (> v_~z_ev~0_13 1) InVars {~z_ev~0=v_~z_ev~0_13} OutVars{~z_ev~0=v_~z_ev~0_13} AuxVars[] AssignedVars[] 2876#L422-1 54.07/20.05 [2019-03-28 12:18:51,392 INFO L796 eck$LassoCheckResult]: Loop: 2876#L422-1 [887] L422-1-->L285: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 1) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 2823#L285 [888] L285-->L258: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_13, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res] 2824#L258 [802] L258-->L265: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8 0) (> 0 v_~comp_m1_st~0_9)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_9} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8, ~comp_m1_st~0=v_~comp_m1_st~0_9} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 2882#L265 [889] L265-->L280: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___0~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 2883#L280 [890] L280-->L202-2: Formula: (and (= v_ULTIMATE.start_eval_~tmp___0~0_8 0) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 2)) InVars {ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 2863#L202-2 [800] L202-2-->L202-3: Formula: (> 1 v_~b0_req_up~0_9) InVars {~b0_req_up~0=v_~b0_req_up~0_9} OutVars{~b0_req_up~0=v_~b0_req_up~0_9} AuxVars[] AssignedVars[] 2861#L202-3 [807] L202-3-->L209-1: Formula: (> 1 v_~b1_req_up~0_9) InVars {~b1_req_up~0=v_~b1_req_up~0_9} OutVars{~b1_req_up~0=v_~b1_req_up~0_9} AuxVars[] AssignedVars[] 2856#L209-1 [811] L209-1-->L216-1: Formula: (< v_~d0_req_up~0_9 1) InVars {~d0_req_up~0=v_~d0_req_up~0_9} OutVars{~d0_req_up~0=v_~d0_req_up~0_9} AuxVars[] AssignedVars[] 2851#L216-1 [815] L216-1-->L223-1: Formula: (< v_~d1_req_up~0_9 1) InVars {~d1_req_up~0=v_~d1_req_up~0_9} OutVars{~d1_req_up~0=v_~d1_req_up~0_9} AuxVars[] AssignedVars[] 2819#L223-1 [821] L223-1-->L230-1: Formula: (> 1 v_~z_req_up~0_9) InVars {~z_req_up~0=v_~z_req_up~0_9} OutVars{~z_req_up~0=v_~z_req_up~0_9} AuxVars[] AssignedVars[] 2830#L230-1 [498] L230-1-->L311-2: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 3) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 2934#L311-2 [632] L311-2-->L311-4: Formula: (and (= v_~b0_ev~0_8 1) (= v_~b0_ev~0_9 0)) InVars {~b0_ev~0=v_~b0_ev~0_9} OutVars{~b0_ev~0=v_~b0_ev~0_8} AuxVars[] AssignedVars[~b0_ev~0] 2933#L311-4 [832] L311-4-->L316-3: Formula: (> 0 v_~b1_ev~0_10) InVars {~b1_ev~0=v_~b1_ev~0_10} OutVars{~b1_ev~0=v_~b1_ev~0_10} AuxVars[] AssignedVars[] 2932#L316-3 [838] L316-3-->L321-3: Formula: (< v_~d0_ev~0_10 0) InVars {~d0_ev~0=v_~d0_ev~0_10} OutVars{~d0_ev~0=v_~d0_ev~0_10} AuxVars[] AssignedVars[] 2931#L321-3 [662] L321-3-->L326-3: Formula: (and (= v_~d1_ev~0_8 1) (= 0 v_~d1_ev~0_9)) InVars {~d1_ev~0=v_~d1_ev~0_9} OutVars{~d1_ev~0=v_~d1_ev~0_8} AuxVars[] AssignedVars[~d1_ev~0] 2930#L326-3 [850] L326-3-->L331-3: Formula: (> v_~z_ev~0_10 0) InVars {~z_ev~0=v_~z_ev~0_10} OutVars{~z_ev~0=v_~z_ev~0_10} AuxVars[] AssignedVars[] 2929#L331-3 [570] L331-3-->L97-1: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_4|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_10, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 2894#L97-1 [588] L97-1-->L119-1: Formula: (and (= v_~b0_ev~0_13 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13 1)) InVars {~b0_ev~0=v_~b0_ev~0_13} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13, ~b0_ev~0=v_~b0_ev~0_13} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 2846#L119-1 [891] L119-1-->L380-3: Formula: (and (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20 |v_ULTIMATE.start_is_method1_triggered_#res_8|) (= |v_ULTIMATE.start_is_method1_triggered_#res_8| v_ULTIMATE.start_activate_threads_~tmp~1_14)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_14, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_8|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_8|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 2806#L380-3 [864] L380-3-->L380-5: Formula: (and (= v_~comp_m1_st~0_7 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11, ~comp_m1_st~0=v_~comp_m1_st~0_7} AuxVars[] AssignedVars[~comp_m1_st~0] 2807#L380-5 [868] L380-5-->L344-3: Formula: (< v_~b0_ev~0_20 1) InVars {~b0_ev~0=v_~b0_ev~0_20} OutVars{~b0_ev~0=v_~b0_ev~0_20} AuxVars[] AssignedVars[] 2817#L344-3 [870] L344-3-->L349-3: Formula: (< 1 v_~b1_ev~0_20) InVars {~b1_ev~0=v_~b1_ev~0_20} OutVars{~b1_ev~0=v_~b1_ev~0_20} AuxVars[] AssignedVars[] 2865#L349-3 [656] L349-3-->L354-3: Formula: (and (= v_~d0_ev~0_18 2) (= v_~d0_ev~0_19 1)) InVars {~d0_ev~0=v_~d0_ev~0_19} OutVars{~d0_ev~0=v_~d0_ev~0_18} AuxVars[] AssignedVars[~d0_ev~0] 2833#L354-3 [513] L354-3-->L359-3: Formula: (and (= 1 v_~d1_ev~0_19) (= v_~d1_ev~0_18 2)) InVars {~d1_ev~0=v_~d1_ev~0_19} OutVars{~d1_ev~0=v_~d1_ev~0_18} AuxVars[] AssignedVars[~d1_ev~0] 2834#L359-3 [531] L359-3-->L364-3: Formula: (and (= v_~z_ev~0_15 1) (= v_~z_ev~0_14 2)) InVars {~z_ev~0=v_~z_ev~0_15} OutVars{~z_ev~0=v_~z_ev~0_14} AuxVars[] AssignedVars[~z_ev~0] 2855#L364-3 [568] L364-3-->L258-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_5, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_2|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_#res] 2885#L258-1 [666] L258-1-->L265-1: Formula: (and (= v_~comp_m1_st~0_10 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9 1)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_10} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9, ~comp_m1_st~0=v_~comp_m1_st~0_10} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 2880#L265-1 [892] L265-1-->L397: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_stop_simulation_~tmp~2_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_4|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_~tmp~2] 2881#L397 [880] L397-->L404: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_4 0) (< 0 v_ULTIMATE.start_stop_simulation_~tmp~2_5)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_4, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 2884#L404 [897] L404-->L422-1: Formula: (and (= 0 v_ULTIMATE.start_start_simulation_~tmp~3_9) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= |v_ULTIMATE.start_stop_simulation_#res_5| v_ULTIMATE.start_start_simulation_~tmp~3_9)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_~tmp~3] 2876#L422-1 54.07/20.05 [2019-03-28 12:18:51,393 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.05 [2019-03-28 12:18:51,393 INFO L82 PathProgramCache]: Analyzing trace with hash -1143417213, now seen corresponding path program 1 times 54.07/20.05 [2019-03-28 12:18:51,393 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.05 [2019-03-28 12:18:51,393 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.05 [2019-03-28 12:18:51,394 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:51,394 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:51,394 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:51,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.05 [2019-03-28 12:18:51,411 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.05 [2019-03-28 12:18:51,411 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.05 [2019-03-28 12:18:51,412 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 54.07/20.05 [2019-03-28 12:18:51,412 INFO L799 eck$LassoCheckResult]: stem already infeasible 54.07/20.05 [2019-03-28 12:18:51,412 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.05 [2019-03-28 12:18:51,412 INFO L82 PathProgramCache]: Analyzing trace with hash -934101709, now seen corresponding path program 1 times 54.07/20.05 [2019-03-28 12:18:51,412 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.05 [2019-03-28 12:18:51,413 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.05 [2019-03-28 12:18:51,413 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:51,414 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:51,414 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:51,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.05 [2019-03-28 12:18:51,429 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.05 [2019-03-28 12:18:51,429 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.05 [2019-03-28 12:18:51,430 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 54.07/20.05 [2019-03-28 12:18:51,430 INFO L811 eck$LassoCheckResult]: loop already infeasible 54.07/20.05 [2019-03-28 12:18:51,430 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 54.07/20.05 [2019-03-28 12:18:51,430 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 54.07/20.05 [2019-03-28 12:18:51,430 INFO L87 Difference]: Start difference. First operand 131 states and 295 transitions. cyclomatic complexity: 165 Second operand 3 states. 54.07/20.05 [2019-03-28 12:18:51,749 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 54.07/20.05 [2019-03-28 12:18:51,750 INFO L93 Difference]: Finished difference Result 246 states and 555 transitions. 54.07/20.05 [2019-03-28 12:18:51,750 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 54.07/20.05 [2019-03-28 12:18:51,751 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 246 states and 555 transitions. 54.07/20.05 [2019-03-28 12:18:51,753 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 198 54.07/20.05 [2019-03-28 12:18:51,755 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 246 states to 246 states and 555 transitions. 54.07/20.05 [2019-03-28 12:18:51,755 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 246 54.07/20.05 [2019-03-28 12:18:51,755 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 246 54.07/20.05 [2019-03-28 12:18:51,755 INFO L73 IsDeterministic]: Start isDeterministic. Operand 246 states and 555 transitions. 54.07/20.05 [2019-03-28 12:18:51,756 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 54.07/20.05 [2019-03-28 12:18:51,756 INFO L706 BuchiCegarLoop]: Abstraction has 246 states and 555 transitions. 54.07/20.05 [2019-03-28 12:18:51,757 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 246 states and 555 transitions. 54.07/20.05 [2019-03-28 12:18:51,762 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 246 to 246. 54.07/20.05 [2019-03-28 12:18:51,763 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 246 states. 54.07/20.05 [2019-03-28 12:18:51,764 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 246 states to 246 states and 555 transitions. 54.07/20.05 [2019-03-28 12:18:51,764 INFO L729 BuchiCegarLoop]: Abstraction has 246 states and 555 transitions. 54.07/20.05 [2019-03-28 12:18:51,764 INFO L609 BuchiCegarLoop]: Abstraction has 246 states and 555 transitions. 54.07/20.05 [2019-03-28 12:18:51,764 INFO L442 BuchiCegarLoop]: ======== Iteration 15============ 54.07/20.05 [2019-03-28 12:18:51,764 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 246 states and 555 transitions. 54.07/20.05 [2019-03-28 12:18:51,765 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 198 54.07/20.05 [2019-03-28 12:18:51,766 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 54.07/20.05 [2019-03-28 12:18:51,766 INFO L119 BuchiIsEmpty]: Starting construction of run 54.07/20.05 [2019-03-28 12:18:51,767 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.05 [2019-03-28 12:18:51,767 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.05 [2019-03-28 12:18:51,767 INFO L794 eck$LassoCheckResult]: Stem: 3260#ULTIMATE.startENTRY [885] ULTIMATE.startENTRY-->L202: Formula: (and (= v_~d0_ev~0_23 2) (= 0 v_~z_val~0_13) (= 2 v_~b1_ev~0_23) (= v_~d0_val_t~0_9 1) (= v_~b0_val~0_13 0) (= 1 v_~b1_val_t~0_9) (= 1 v_~d1_req_up~0_12) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_9 0) (= 2 v_~d1_ev~0_23) (= v_~b1_val~0_13 0) (= v_~b0_val_t~0_9 1) (= v_~b0_req_up~0_12 1) (= 0 v_~comp_m1_i~0_7) (= v_~d0_req_up~0_12 1) (= v_~comp_m1_st~0_15 0) (= v_~b0_ev~0_23 2) (= 1 v_~d1_val_t~0_9) (= v_~z_req_up~0_12 0) (= v_~z_val_t~0_10 0) (= 0 v_~d1_val~0_13) (= v_~z_ev~0_19 2) (= v_~b1_req_up~0_12 1) (= 0 v_~d0_val~0_13)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_4|, ~b1_val~0=v_~b1_val~0_13, ~b0_val~0=v_~b0_val~0_13, ~d0_req_up~0=v_~d0_req_up~0_12, ~d0_val~0=v_~d0_val~0_13, ~d1_val_t~0=v_~d1_val_t~0_9, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_9, ~d1_ev~0=v_~d1_ev~0_23, ~d1_val~0=v_~d1_val~0_13, ~b0_req_up~0=v_~b0_req_up~0_12, ~z_ev~0=v_~z_ev~0_19, ~b1_val_t~0=v_~b1_val_t~0_9, ~b1_ev~0=v_~b1_ev~0_23, ULTIMATE.start_main_~__retres1~2=v_ULTIMATE.start_main_~__retres1~2_6, ~z_val~0=v_~z_val~0_13, ~d1_req_up~0=v_~d1_req_up~0_12, ~z_val_t~0=v_~z_val_t~0_10, ~b0_val_t~0=v_~b0_val_t~0_9, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~z_req_up~0=v_~z_req_up~0_12, ~b1_req_up~0=v_~b1_req_up~0_12, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~d0_ev~0=v_~d0_ev~0_23, ~b0_ev~0=v_~b0_ev~0_23, ~d0_val_t~0=v_~d0_val_t~0_9, ~comp_m1_st~0=v_~comp_m1_st~0_15, ~comp_m1_i~0=v_~comp_m1_i~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ~b1_val~0, ~b0_val~0, ~d0_req_up~0, ~d0_val~0, ~d1_val_t~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~d1_ev~0, ~d1_val~0, ~b0_req_up~0, ~z_ev~0, ~b1_val_t~0, ~b1_ev~0, ULTIMATE.start_main_~__retres1~2, ~z_val~0, ~d1_req_up~0, ~z_val_t~0, ~b0_val_t~0, ULTIMATE.start_start_simulation_~tmp~3, ~z_req_up~0, ~b1_req_up~0, ULTIMATE.start_main_#res, ~d0_ev~0, ~b0_ev~0, ~d0_val_t~0, ~comp_m1_st~0, ~comp_m1_i~0] 3261#L202 [566] L202-->L127: Formula: (= 1 v_~b0_req_up~0_4) InVars {~b0_req_up~0=v_~b0_req_up~0_4} OutVars{~b0_req_up~0=v_~b0_req_up~0_4} AuxVars[] AssignedVars[] 3221#L127 [748] L127-->L127-2: Formula: (and (= v_~b0_val~0_3 v_~b0_val_t~0_3) (> v_~b0_val_t~0_3 v_~b0_val~0_4) (= v_~b0_ev~0_3 0)) InVars {~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_4} OutVars{~b0_ev~0=v_~b0_ev~0_3, ~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_3} AuxVars[] AssignedVars[~b0_val~0, ~b0_ev~0] 3222#L127-2 [580] L127-2-->L202-1: Formula: (= v_~b0_req_up~0_5 0) InVars {} OutVars{~b0_req_up~0=v_~b0_req_up~0_5} AuxVars[] AssignedVars[~b0_req_up~0] 3256#L202-1 [545] L202-1-->L142: Formula: (= 1 v_~b1_req_up~0_4) InVars {~b1_req_up~0=v_~b1_req_up~0_4} OutVars{~b1_req_up~0=v_~b1_req_up~0_4} AuxVars[] AssignedVars[] 3238#L142 [752] L142-->L142-2: Formula: (and (= v_~b1_ev~0_3 0) (< v_~b1_val~0_4 v_~b1_val_t~0_3) (= v_~b1_val~0_3 v_~b1_val_t~0_3)) InVars {~b1_val_t~0=v_~b1_val_t~0_3, ~b1_val~0=v_~b1_val~0_4} OutVars{~b1_val_t~0=v_~b1_val_t~0_3, ~b1_ev~0=v_~b1_ev~0_3, ~b1_val~0=v_~b1_val~0_3} AuxVars[] AssignedVars[~b1_val~0, ~b1_ev~0] 3231#L142-2 [521] L142-2-->L209: Formula: (= v_~b1_req_up~0_5 0) InVars {} OutVars{~b1_req_up~0=v_~b1_req_up~0_5} AuxVars[] AssignedVars[~b1_req_up~0] 3232#L209 [624] L209-->L157: Formula: (= v_~d0_req_up~0_4 1) InVars {~d0_req_up~0=v_~d0_req_up~0_4} OutVars{~d0_req_up~0=v_~d0_req_up~0_4} AuxVars[] AssignedVars[] 3207#L157 [757] L157-->L157-2: Formula: (and (> v_~d0_val_t~0_3 v_~d0_val~0_4) (= v_~d0_val~0_3 v_~d0_val_t~0_3) (= v_~d0_ev~0_3 0)) InVars {~d0_val~0=v_~d0_val~0_4, ~d0_val_t~0=v_~d0_val_t~0_3} OutVars{~d0_ev~0=v_~d0_ev~0_3, ~d0_val~0=v_~d0_val~0_3, ~d0_val_t~0=v_~d0_val_t~0_3} AuxVars[] AssignedVars[~d0_ev~0, ~d0_val~0] 3197#L157-2 [600] L157-2-->L216: Formula: (= v_~d0_req_up~0_5 0) InVars {} OutVars{~d0_req_up~0=v_~d0_req_up~0_5} AuxVars[] AssignedVars[~d0_req_up~0] 3198#L216 [554] L216-->L172: Formula: (= v_~d1_req_up~0_4 1) InVars {~d1_req_up~0=v_~d1_req_up~0_4} OutVars{~d1_req_up~0=v_~d1_req_up~0_4} AuxVars[] AssignedVars[] 3265#L172 [760] L172-->L172-2: Formula: (and (= v_~d1_val~0_3 v_~d1_val_t~0_3) (= v_~d1_ev~0_3 0) (> v_~d1_val_t~0_3 v_~d1_val~0_4)) InVars {~d1_val_t~0=v_~d1_val_t~0_3, ~d1_val~0=v_~d1_val~0_4} OutVars{~d1_val_t~0=v_~d1_val_t~0_3, ~d1_val~0=v_~d1_val~0_3, ~d1_ev~0=v_~d1_ev~0_3} AuxVars[] AssignedVars[~d1_val~0, ~d1_ev~0] 3259#L172-2 [547] L172-2-->L223: Formula: (= v_~d1_req_up~0_5 0) InVars {} OutVars{~d1_req_up~0=v_~d1_req_up~0_5} AuxVars[] AssignedVars[~d1_req_up~0] 3258#L223 [762] L223-->L230: Formula: (> 1 v_~z_req_up~0_6) InVars {~z_req_up~0=v_~z_req_up~0_6} OutVars{~z_req_up~0=v_~z_req_up~0_6} AuxVars[] AssignedVars[] 3199#L230 [767] L230-->L245-1: Formula: (and (> 1 v_~comp_m1_i~0_4) (= v_~comp_m1_st~0_5 2)) InVars {~comp_m1_i~0=v_~comp_m1_i~0_4} OutVars{~comp_m1_st~0=v_~comp_m1_st~0_5, ~comp_m1_i~0=v_~comp_m1_i~0_4} AuxVars[] AssignedVars[~comp_m1_st~0] 3200#L245-1 [608] L245-1-->L311-1: Formula: (and (= v_~b0_ev~0_5 1) (= v_~b0_ev~0_6 0)) InVars {~b0_ev~0=v_~b0_ev~0_6} OutVars{~b0_ev~0=v_~b0_ev~0_5} AuxVars[] AssignedVars[~b0_ev~0] 3219#L311-1 [628] L311-1-->L316-1: Formula: (and (= 0 v_~b1_ev~0_6) (= v_~b1_ev~0_5 1)) InVars {~b1_ev~0=v_~b1_ev~0_6} OutVars{~b1_ev~0=v_~b1_ev~0_5} AuxVars[] AssignedVars[~b1_ev~0] 3279#L316-1 [654] L316-1-->L321-1: Formula: (and (= v_~d0_ev~0_5 1) (= v_~d0_ev~0_6 0)) InVars {~d0_ev~0=v_~d0_ev~0_6} OutVars{~d0_ev~0=v_~d0_ev~0_5} AuxVars[] AssignedVars[~d0_ev~0] 3210#L321-1 [507] L321-1-->L326-1: Formula: (and (= 0 v_~d1_ev~0_6) (= v_~d1_ev~0_5 1)) InVars {~d1_ev~0=v_~d1_ev~0_6} OutVars{~d1_ev~0=v_~d1_ev~0_5} AuxVars[] AssignedVars[~d1_ev~0] 3211#L326-1 [556] L326-1-->L331-1: Formula: (and (= 0 v_~z_ev~0_6) (= v_~z_ev~0_5 1)) InVars {~z_ev~0=v_~z_ev~0_6} OutVars{~z_ev~0=v_~z_ev~0_5} AuxVars[] AssignedVars[~z_ev~0] 3269#L331-1 [583] L331-1-->L97: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_1|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 3293#L97 [591] L97-->L119: Formula: (and (= v_~b0_ev~0_11 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4 1)) InVars {~b0_ev~0=v_~b0_ev~0_11} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4, ~b0_ev~0=v_~b0_ev~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 3295#L119 [886] L119-->L380: Formula: (and (= |v_ULTIMATE.start_is_method1_triggered_#res_7| v_ULTIMATE.start_activate_threads_~tmp~1_13) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19 |v_ULTIMATE.start_is_method1_triggered_#res_7|)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_13, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_7|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_7|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 3298#L380 [615] L380-->L380-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_9) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} AuxVars[] AssignedVars[] 3296#L380-2 [618] L380-2-->L344-1: Formula: (and (= v_~b0_ev~0_15 2) (= v_~b0_ev~0_16 1)) InVars {~b0_ev~0=v_~b0_ev~0_16} OutVars{~b0_ev~0=v_~b0_ev~0_15} AuxVars[] AssignedVars[~b0_ev~0] 3245#L344-1 [791] L344-1-->L349-1: Formula: (> 1 v_~b1_ev~0_17) InVars {~b1_ev~0=v_~b1_ev~0_17} OutVars{~b1_ev~0=v_~b1_ev~0_17} AuxVars[] AssignedVars[] 3246#L349-1 [652] L349-1-->L354-1: Formula: (and (= v_~d0_ev~0_15 2) (= v_~d0_ev~0_16 1)) InVars {~d0_ev~0=v_~d0_ev~0_16} OutVars{~d0_ev~0=v_~d0_ev~0_15} AuxVars[] AssignedVars[~d0_ev~0] 3205#L354-1 [795] L354-1-->L359-1: Formula: (> 1 v_~d1_ev~0_17) InVars {~d1_ev~0=v_~d1_ev~0_17} OutVars{~d1_ev~0=v_~d1_ev~0_17} AuxVars[] AssignedVars[] 3206#L359-1 [797] L359-1-->L422-1: Formula: (> v_~z_ev~0_13 1) InVars {~z_ev~0=v_~z_ev~0_13} OutVars{~z_ev~0=v_~z_ev~0_13} AuxVars[] AssignedVars[] 3266#L422-1 54.07/20.05 [2019-03-28 12:18:51,768 INFO L796 eck$LassoCheckResult]: Loop: 3266#L422-1 [887] L422-1-->L285: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 1) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 3412#L285 [888] L285-->L258: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_13, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res] 3411#L258 [802] L258-->L265: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8 0) (> 0 v_~comp_m1_st~0_9)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_9} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8, ~comp_m1_st~0=v_~comp_m1_st~0_9} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 3328#L265 [889] L265-->L280: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___0~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 3291#L280 [890] L280-->L202-2: Formula: (and (= v_ULTIMATE.start_eval_~tmp___0~0_8 0) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 2)) InVars {ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 3249#L202-2 [800] L202-2-->L202-3: Formula: (> 1 v_~b0_req_up~0_9) InVars {~b0_req_up~0=v_~b0_req_up~0_9} OutVars{~b0_req_up~0=v_~b0_req_up~0_9} AuxVars[] AssignedVars[] 3247#L202-3 [807] L202-3-->L209-1: Formula: (> 1 v_~b1_req_up~0_9) InVars {~b1_req_up~0=v_~b1_req_up~0_9} OutVars{~b1_req_up~0=v_~b1_req_up~0_9} AuxVars[] AssignedVars[] 3241#L209-1 [811] L209-1-->L216-1: Formula: (< v_~d0_req_up~0_9 1) InVars {~d0_req_up~0=v_~d0_req_up~0_9} OutVars{~d0_req_up~0=v_~d0_req_up~0_9} AuxVars[] AssignedVars[] 3237#L216-1 [815] L216-1-->L223-1: Formula: (< v_~d1_req_up~0_9 1) InVars {~d1_req_up~0=v_~d1_req_up~0_9} OutVars{~d1_req_up~0=v_~d1_req_up~0_9} AuxVars[] AssignedVars[] 3204#L223-1 [821] L223-1-->L230-1: Formula: (> 1 v_~z_req_up~0_9) InVars {~z_req_up~0=v_~z_req_up~0_9} OutVars{~z_req_up~0=v_~z_req_up~0_9} AuxVars[] AssignedVars[] 3215#L230-1 [498] L230-1-->L311-2: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 3) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 3329#L311-2 [632] L311-2-->L311-4: Formula: (and (= v_~b0_ev~0_8 1) (= v_~b0_ev~0_9 0)) InVars {~b0_ev~0=v_~b0_ev~0_9} OutVars{~b0_ev~0=v_~b0_ev~0_8} AuxVars[] AssignedVars[~b0_ev~0] 3254#L311-4 [832] L311-4-->L316-3: Formula: (> 0 v_~b1_ev~0_10) InVars {~b1_ev~0=v_~b1_ev~0_10} OutVars{~b1_ev~0=v_~b1_ev~0_10} AuxVars[] AssignedVars[] 3421#L316-3 [838] L316-3-->L321-3: Formula: (< v_~d0_ev~0_10 0) InVars {~d0_ev~0=v_~d0_ev~0_10} OutVars{~d0_ev~0=v_~d0_ev~0_10} AuxVars[] AssignedVars[] 3420#L321-3 [662] L321-3-->L326-3: Formula: (and (= v_~d1_ev~0_8 1) (= 0 v_~d1_ev~0_9)) InVars {~d1_ev~0=v_~d1_ev~0_9} OutVars{~d1_ev~0=v_~d1_ev~0_8} AuxVars[] AssignedVars[~d1_ev~0] 3326#L326-3 [850] L326-3-->L331-3: Formula: (> v_~z_ev~0_10 0) InVars {~z_ev~0=v_~z_ev~0_10} OutVars{~z_ev~0=v_~z_ev~0_10} AuxVars[] AssignedVars[] 3327#L331-3 [570] L331-3-->L97-1: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_4|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_10, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 3403#L97-1 [588] L97-1-->L119-1: Formula: (and (= v_~b0_ev~0_13 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13 1)) InVars {~b0_ev~0=v_~b0_ev~0_13} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13, ~b0_ev~0=v_~b0_ev~0_13} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 3405#L119-1 [891] L119-1-->L380-3: Formula: (and (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20 |v_ULTIMATE.start_is_method1_triggered_#res_8|) (= |v_ULTIMATE.start_is_method1_triggered_#res_8| v_ULTIMATE.start_activate_threads_~tmp~1_14)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_14, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_8|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_8|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 3396#L380-3 [864] L380-3-->L380-5: Formula: (and (= v_~comp_m1_st~0_7 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11, ~comp_m1_st~0=v_~comp_m1_st~0_7} AuxVars[] AssignedVars[~comp_m1_st~0] 3397#L380-5 [869] L380-5-->L344-3: Formula: (> v_~b0_ev~0_20 1) InVars {~b0_ev~0=v_~b0_ev~0_20} OutVars{~b0_ev~0=v_~b0_ev~0_20} AuxVars[] AssignedVars[] 3422#L344-3 [870] L344-3-->L349-3: Formula: (< 1 v_~b1_ev~0_20) InVars {~b1_ev~0=v_~b1_ev~0_20} OutVars{~b1_ev~0=v_~b1_ev~0_20} AuxVars[] AssignedVars[] 3280#L349-3 [656] L349-3-->L354-3: Formula: (and (= v_~d0_ev~0_18 2) (= v_~d0_ev~0_19 1)) InVars {~d0_ev~0=v_~d0_ev~0_19} OutVars{~d0_ev~0=v_~d0_ev~0_18} AuxVars[] AssignedVars[~d0_ev~0] 3281#L354-3 [513] L354-3-->L359-3: Formula: (and (= 1 v_~d1_ev~0_19) (= v_~d1_ev~0_18 2)) InVars {~d1_ev~0=v_~d1_ev~0_19} OutVars{~d1_ev~0=v_~d1_ev~0_18} AuxVars[] AssignedVars[~d1_ev~0] 3419#L359-3 [531] L359-3-->L364-3: Formula: (and (= v_~z_ev~0_15 1) (= v_~z_ev~0_14 2)) InVars {~z_ev~0=v_~z_ev~0_15} OutVars{~z_ev~0=v_~z_ev~0_14} AuxVars[] AssignedVars[~z_ev~0] 3418#L364-3 [568] L364-3-->L258-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_5, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_2|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_#res] 3417#L258-1 [666] L258-1-->L265-1: Formula: (and (= v_~comp_m1_st~0_10 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9 1)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_10} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9, ~comp_m1_st~0=v_~comp_m1_st~0_10} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 3416#L265-1 [892] L265-1-->L397: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_stop_simulation_~tmp~2_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_4|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_~tmp~2] 3415#L397 [880] L397-->L404: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_4 0) (< 0 v_ULTIMATE.start_stop_simulation_~tmp~2_5)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_4, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 3414#L404 [897] L404-->L422-1: Formula: (and (= 0 v_ULTIMATE.start_start_simulation_~tmp~3_9) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= |v_ULTIMATE.start_stop_simulation_#res_5| v_ULTIMATE.start_start_simulation_~tmp~3_9)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_~tmp~3] 3266#L422-1 54.07/20.05 [2019-03-28 12:18:51,768 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.05 [2019-03-28 12:18:51,769 INFO L82 PathProgramCache]: Analyzing trace with hash -1352857212, now seen corresponding path program 1 times 54.07/20.05 [2019-03-28 12:18:51,769 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.05 [2019-03-28 12:18:51,769 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.05 [2019-03-28 12:18:51,770 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:51,770 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:51,770 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:51,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.05 [2019-03-28 12:18:51,789 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.05 [2019-03-28 12:18:51,790 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.05 [2019-03-28 12:18:51,790 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 54.07/20.05 [2019-03-28 12:18:51,790 INFO L799 eck$LassoCheckResult]: stem already infeasible 54.07/20.05 [2019-03-28 12:18:51,790 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.05 [2019-03-28 12:18:51,791 INFO L82 PathProgramCache]: Analyzing trace with hash -1130615214, now seen corresponding path program 1 times 54.07/20.05 [2019-03-28 12:18:51,791 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.05 [2019-03-28 12:18:51,791 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.05 [2019-03-28 12:18:51,792 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:51,792 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:51,792 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:51,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.05 [2019-03-28 12:18:51,805 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.05 [2019-03-28 12:18:51,806 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.05 [2019-03-28 12:18:51,806 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 54.07/20.05 [2019-03-28 12:18:51,806 INFO L811 eck$LassoCheckResult]: loop already infeasible 54.07/20.05 [2019-03-28 12:18:51,806 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 54.07/20.05 [2019-03-28 12:18:51,807 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 54.07/20.05 [2019-03-28 12:18:51,807 INFO L87 Difference]: Start difference. First operand 246 states and 555 transitions. cyclomatic complexity: 310 Second operand 3 states. 54.07/20.05 [2019-03-28 12:18:51,985 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 54.07/20.05 [2019-03-28 12:18:51,985 INFO L93 Difference]: Finished difference Result 444 states and 983 transitions. 54.07/20.05 [2019-03-28 12:18:51,985 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 54.07/20.05 [2019-03-28 12:18:51,986 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 444 states and 983 transitions. 54.07/20.05 [2019-03-28 12:18:51,989 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 396 54.07/20.05 [2019-03-28 12:18:51,992 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 444 states to 444 states and 983 transitions. 54.07/20.05 [2019-03-28 12:18:51,992 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 444 54.07/20.05 [2019-03-28 12:18:51,993 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 444 54.07/20.05 [2019-03-28 12:18:51,993 INFO L73 IsDeterministic]: Start isDeterministic. Operand 444 states and 983 transitions. 54.07/20.05 [2019-03-28 12:18:51,994 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 54.07/20.05 [2019-03-28 12:18:51,994 INFO L706 BuchiCegarLoop]: Abstraction has 444 states and 983 transitions. 54.07/20.05 [2019-03-28 12:18:51,994 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 444 states and 983 transitions. 54.07/20.05 [2019-03-28 12:18:52,003 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 444 to 444. 54.07/20.05 [2019-03-28 12:18:52,003 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 444 states. 54.07/20.05 [2019-03-28 12:18:52,004 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 444 states to 444 states and 983 transitions. 54.07/20.05 [2019-03-28 12:18:52,005 INFO L729 BuchiCegarLoop]: Abstraction has 444 states and 983 transitions. 54.07/20.05 [2019-03-28 12:18:52,005 INFO L609 BuchiCegarLoop]: Abstraction has 444 states and 983 transitions. 54.07/20.05 [2019-03-28 12:18:52,005 INFO L442 BuchiCegarLoop]: ======== Iteration 16============ 54.07/20.05 [2019-03-28 12:18:52,005 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 444 states and 983 transitions. 54.07/20.05 [2019-03-28 12:18:52,007 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 396 54.07/20.05 [2019-03-28 12:18:52,007 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 54.07/20.05 [2019-03-28 12:18:52,008 INFO L119 BuchiIsEmpty]: Starting construction of run 54.07/20.05 [2019-03-28 12:18:52,008 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.05 [2019-03-28 12:18:52,008 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.05 [2019-03-28 12:18:52,009 INFO L794 eck$LassoCheckResult]: Stem: 3956#ULTIMATE.startENTRY [885] ULTIMATE.startENTRY-->L202: Formula: (and (= v_~d0_ev~0_23 2) (= 0 v_~z_val~0_13) (= 2 v_~b1_ev~0_23) (= v_~d0_val_t~0_9 1) (= v_~b0_val~0_13 0) (= 1 v_~b1_val_t~0_9) (= 1 v_~d1_req_up~0_12) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_9 0) (= 2 v_~d1_ev~0_23) (= v_~b1_val~0_13 0) (= v_~b0_val_t~0_9 1) (= v_~b0_req_up~0_12 1) (= 0 v_~comp_m1_i~0_7) (= v_~d0_req_up~0_12 1) (= v_~comp_m1_st~0_15 0) (= v_~b0_ev~0_23 2) (= 1 v_~d1_val_t~0_9) (= v_~z_req_up~0_12 0) (= v_~z_val_t~0_10 0) (= 0 v_~d1_val~0_13) (= v_~z_ev~0_19 2) (= v_~b1_req_up~0_12 1) (= 0 v_~d0_val~0_13)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_4|, ~b1_val~0=v_~b1_val~0_13, ~b0_val~0=v_~b0_val~0_13, ~d0_req_up~0=v_~d0_req_up~0_12, ~d0_val~0=v_~d0_val~0_13, ~d1_val_t~0=v_~d1_val_t~0_9, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_9, ~d1_ev~0=v_~d1_ev~0_23, ~d1_val~0=v_~d1_val~0_13, ~b0_req_up~0=v_~b0_req_up~0_12, ~z_ev~0=v_~z_ev~0_19, ~b1_val_t~0=v_~b1_val_t~0_9, ~b1_ev~0=v_~b1_ev~0_23, ULTIMATE.start_main_~__retres1~2=v_ULTIMATE.start_main_~__retres1~2_6, ~z_val~0=v_~z_val~0_13, ~d1_req_up~0=v_~d1_req_up~0_12, ~z_val_t~0=v_~z_val_t~0_10, ~b0_val_t~0=v_~b0_val_t~0_9, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~z_req_up~0=v_~z_req_up~0_12, ~b1_req_up~0=v_~b1_req_up~0_12, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~d0_ev~0=v_~d0_ev~0_23, ~b0_ev~0=v_~b0_ev~0_23, ~d0_val_t~0=v_~d0_val_t~0_9, ~comp_m1_st~0=v_~comp_m1_st~0_15, ~comp_m1_i~0=v_~comp_m1_i~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ~b1_val~0, ~b0_val~0, ~d0_req_up~0, ~d0_val~0, ~d1_val_t~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~d1_ev~0, ~d1_val~0, ~b0_req_up~0, ~z_ev~0, ~b1_val_t~0, ~b1_ev~0, ULTIMATE.start_main_~__retres1~2, ~z_val~0, ~d1_req_up~0, ~z_val_t~0, ~b0_val_t~0, ULTIMATE.start_start_simulation_~tmp~3, ~z_req_up~0, ~b1_req_up~0, ULTIMATE.start_main_#res, ~d0_ev~0, ~b0_ev~0, ~d0_val_t~0, ~comp_m1_st~0, ~comp_m1_i~0] 3957#L202 [566] L202-->L127: Formula: (= 1 v_~b0_req_up~0_4) InVars {~b0_req_up~0=v_~b0_req_up~0_4} OutVars{~b0_req_up~0=v_~b0_req_up~0_4} AuxVars[] AssignedVars[] 3917#L127 [748] L127-->L127-2: Formula: (and (= v_~b0_val~0_3 v_~b0_val_t~0_3) (> v_~b0_val_t~0_3 v_~b0_val~0_4) (= v_~b0_ev~0_3 0)) InVars {~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_4} OutVars{~b0_ev~0=v_~b0_ev~0_3, ~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_3} AuxVars[] AssignedVars[~b0_val~0, ~b0_ev~0] 3918#L127-2 [580] L127-2-->L202-1: Formula: (= v_~b0_req_up~0_5 0) InVars {} OutVars{~b0_req_up~0=v_~b0_req_up~0_5} AuxVars[] AssignedVars[~b0_req_up~0] 3952#L202-1 [545] L202-1-->L142: Formula: (= 1 v_~b1_req_up~0_4) InVars {~b1_req_up~0=v_~b1_req_up~0_4} OutVars{~b1_req_up~0=v_~b1_req_up~0_4} AuxVars[] AssignedVars[] 3934#L142 [752] L142-->L142-2: Formula: (and (= v_~b1_ev~0_3 0) (< v_~b1_val~0_4 v_~b1_val_t~0_3) (= v_~b1_val~0_3 v_~b1_val_t~0_3)) InVars {~b1_val_t~0=v_~b1_val_t~0_3, ~b1_val~0=v_~b1_val~0_4} OutVars{~b1_val_t~0=v_~b1_val_t~0_3, ~b1_ev~0=v_~b1_ev~0_3, ~b1_val~0=v_~b1_val~0_3} AuxVars[] AssignedVars[~b1_val~0, ~b1_ev~0] 3925#L142-2 [521] L142-2-->L209: Formula: (= v_~b1_req_up~0_5 0) InVars {} OutVars{~b1_req_up~0=v_~b1_req_up~0_5} AuxVars[] AssignedVars[~b1_req_up~0] 3926#L209 [624] L209-->L157: Formula: (= v_~d0_req_up~0_4 1) InVars {~d0_req_up~0=v_~d0_req_up~0_4} OutVars{~d0_req_up~0=v_~d0_req_up~0_4} AuxVars[] AssignedVars[] 3903#L157 [757] L157-->L157-2: Formula: (and (> v_~d0_val_t~0_3 v_~d0_val~0_4) (= v_~d0_val~0_3 v_~d0_val_t~0_3) (= v_~d0_ev~0_3 0)) InVars {~d0_val~0=v_~d0_val~0_4, ~d0_val_t~0=v_~d0_val_t~0_3} OutVars{~d0_ev~0=v_~d0_ev~0_3, ~d0_val~0=v_~d0_val~0_3, ~d0_val_t~0=v_~d0_val_t~0_3} AuxVars[] AssignedVars[~d0_ev~0, ~d0_val~0] 3894#L157-2 [600] L157-2-->L216: Formula: (= v_~d0_req_up~0_5 0) InVars {} OutVars{~d0_req_up~0=v_~d0_req_up~0_5} AuxVars[] AssignedVars[~d0_req_up~0] 3895#L216 [554] L216-->L172: Formula: (= v_~d1_req_up~0_4 1) InVars {~d1_req_up~0=v_~d1_req_up~0_4} OutVars{~d1_req_up~0=v_~d1_req_up~0_4} AuxVars[] AssignedVars[] 3961#L172 [760] L172-->L172-2: Formula: (and (= v_~d1_val~0_3 v_~d1_val_t~0_3) (= v_~d1_ev~0_3 0) (> v_~d1_val_t~0_3 v_~d1_val~0_4)) InVars {~d1_val_t~0=v_~d1_val_t~0_3, ~d1_val~0=v_~d1_val~0_4} OutVars{~d1_val_t~0=v_~d1_val_t~0_3, ~d1_val~0=v_~d1_val~0_3, ~d1_ev~0=v_~d1_ev~0_3} AuxVars[] AssignedVars[~d1_val~0, ~d1_ev~0] 3955#L172-2 [547] L172-2-->L223: Formula: (= v_~d1_req_up~0_5 0) InVars {} OutVars{~d1_req_up~0=v_~d1_req_up~0_5} AuxVars[] AssignedVars[~d1_req_up~0] 3954#L223 [762] L223-->L230: Formula: (> 1 v_~z_req_up~0_6) InVars {~z_req_up~0=v_~z_req_up~0_6} OutVars{~z_req_up~0=v_~z_req_up~0_6} AuxVars[] AssignedVars[] 3896#L230 [767] L230-->L245-1: Formula: (and (> 1 v_~comp_m1_i~0_4) (= v_~comp_m1_st~0_5 2)) InVars {~comp_m1_i~0=v_~comp_m1_i~0_4} OutVars{~comp_m1_st~0=v_~comp_m1_st~0_5, ~comp_m1_i~0=v_~comp_m1_i~0_4} AuxVars[] AssignedVars[~comp_m1_st~0] 3897#L245-1 [608] L245-1-->L311-1: Formula: (and (= v_~b0_ev~0_5 1) (= v_~b0_ev~0_6 0)) InVars {~b0_ev~0=v_~b0_ev~0_6} OutVars{~b0_ev~0=v_~b0_ev~0_5} AuxVars[] AssignedVars[~b0_ev~0] 3913#L311-1 [628] L311-1-->L316-1: Formula: (and (= 0 v_~b1_ev~0_6) (= v_~b1_ev~0_5 1)) InVars {~b1_ev~0=v_~b1_ev~0_6} OutVars{~b1_ev~0=v_~b1_ev~0_5} AuxVars[] AssignedVars[~b1_ev~0] 3979#L316-1 [654] L316-1-->L321-1: Formula: (and (= v_~d0_ev~0_5 1) (= v_~d0_ev~0_6 0)) InVars {~d0_ev~0=v_~d0_ev~0_6} OutVars{~d0_ev~0=v_~d0_ev~0_5} AuxVars[] AssignedVars[~d0_ev~0] 3906#L321-1 [507] L321-1-->L326-1: Formula: (and (= 0 v_~d1_ev~0_6) (= v_~d1_ev~0_5 1)) InVars {~d1_ev~0=v_~d1_ev~0_6} OutVars{~d1_ev~0=v_~d1_ev~0_5} AuxVars[] AssignedVars[~d1_ev~0] 3907#L326-1 [776] L326-1-->L331-1: Formula: (< 0 v_~z_ev~0_7) InVars {~z_ev~0=v_~z_ev~0_7} OutVars{~z_ev~0=v_~z_ev~0_7} AuxVars[] AssignedVars[] 3967#L331-1 [583] L331-1-->L97: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_1|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 3996#L97 [591] L97-->L119: Formula: (and (= v_~b0_ev~0_11 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4 1)) InVars {~b0_ev~0=v_~b0_ev~0_11} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4, ~b0_ev~0=v_~b0_ev~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 3998#L119 [886] L119-->L380: Formula: (and (= |v_ULTIMATE.start_is_method1_triggered_#res_7| v_ULTIMATE.start_activate_threads_~tmp~1_13) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19 |v_ULTIMATE.start_is_method1_triggered_#res_7|)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_13, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_7|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_7|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 4002#L380 [615] L380-->L380-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_9) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} AuxVars[] AssignedVars[] 3999#L380-2 [618] L380-2-->L344-1: Formula: (and (= v_~b0_ev~0_15 2) (= v_~b0_ev~0_16 1)) InVars {~b0_ev~0=v_~b0_ev~0_16} OutVars{~b0_ev~0=v_~b0_ev~0_15} AuxVars[] AssignedVars[~b0_ev~0] 4000#L344-1 [791] L344-1-->L349-1: Formula: (> 1 v_~b1_ev~0_17) InVars {~b1_ev~0=v_~b1_ev~0_17} OutVars{~b1_ev~0=v_~b1_ev~0_17} AuxVars[] AssignedVars[] 4186#L349-1 [652] L349-1-->L354-1: Formula: (and (= v_~d0_ev~0_15 2) (= v_~d0_ev~0_16 1)) InVars {~d0_ev~0=v_~d0_ev~0_16} OutVars{~d0_ev~0=v_~d0_ev~0_15} AuxVars[] AssignedVars[~d0_ev~0] 3901#L354-1 [795] L354-1-->L359-1: Formula: (> 1 v_~d1_ev~0_17) InVars {~d1_ev~0=v_~d1_ev~0_17} OutVars{~d1_ev~0=v_~d1_ev~0_17} AuxVars[] AssignedVars[] 3902#L359-1 [797] L359-1-->L422-1: Formula: (> v_~z_ev~0_13 1) InVars {~z_ev~0=v_~z_ev~0_13} OutVars{~z_ev~0=v_~z_ev~0_13} AuxVars[] AssignedVars[] 4139#L422-1 54.07/20.05 [2019-03-28 12:18:52,010 INFO L796 eck$LassoCheckResult]: Loop: 4139#L422-1 [887] L422-1-->L285: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 1) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 4120#L285 [888] L285-->L258: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_13, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res] 4132#L258 [802] L258-->L265: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8 0) (> 0 v_~comp_m1_st~0_9)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_9} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8, ~comp_m1_st~0=v_~comp_m1_st~0_9} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 4129#L265 [889] L265-->L280: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___0~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 4126#L280 [890] L280-->L202-2: Formula: (and (= v_ULTIMATE.start_eval_~tmp___0~0_8 0) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 2)) InVars {ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 3947#L202-2 [800] L202-2-->L202-3: Formula: (> 1 v_~b0_req_up~0_9) InVars {~b0_req_up~0=v_~b0_req_up~0_9} OutVars{~b0_req_up~0=v_~b0_req_up~0_9} AuxVars[] AssignedVars[] 3944#L202-3 [807] L202-3-->L209-1: Formula: (> 1 v_~b1_req_up~0_9) InVars {~b1_req_up~0=v_~b1_req_up~0_9} OutVars{~b1_req_up~0=v_~b1_req_up~0_9} AuxVars[] AssignedVars[] 3938#L209-1 [811] L209-1-->L216-1: Formula: (< v_~d0_req_up~0_9 1) InVars {~d0_req_up~0=v_~d0_req_up~0_9} OutVars{~d0_req_up~0=v_~d0_req_up~0_9} AuxVars[] AssignedVars[] 3933#L216-1 [815] L216-1-->L223-1: Formula: (< v_~d1_req_up~0_9 1) InVars {~d1_req_up~0=v_~d1_req_up~0_9} OutVars{~d1_req_up~0=v_~d1_req_up~0_9} AuxVars[] AssignedVars[] 4216#L223-1 [821] L223-1-->L230-1: Formula: (> 1 v_~z_req_up~0_9) InVars {~z_req_up~0=v_~z_req_up~0_9} OutVars{~z_req_up~0=v_~z_req_up~0_9} AuxVars[] AssignedVars[] 4062#L230-1 [498] L230-1-->L311-2: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 3) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 4213#L311-2 [632] L311-2-->L311-4: Formula: (and (= v_~b0_ev~0_8 1) (= v_~b0_ev~0_9 0)) InVars {~b0_ev~0=v_~b0_ev~0_9} OutVars{~b0_ev~0=v_~b0_ev~0_8} AuxVars[] AssignedVars[~b0_ev~0] 3950#L311-4 [832] L311-4-->L316-3: Formula: (> 0 v_~b1_ev~0_10) InVars {~b1_ev~0=v_~b1_ev~0_10} OutVars{~b1_ev~0=v_~b1_ev~0_10} AuxVars[] AssignedVars[] 4209#L316-3 [838] L316-3-->L321-3: Formula: (< v_~d0_ev~0_10 0) InVars {~d0_ev~0=v_~d0_ev~0_10} OutVars{~d0_ev~0=v_~d0_ev~0_10} AuxVars[] AssignedVars[] 4207#L321-3 [662] L321-3-->L326-3: Formula: (and (= v_~d1_ev~0_8 1) (= 0 v_~d1_ev~0_9)) InVars {~d1_ev~0=v_~d1_ev~0_9} OutVars{~d1_ev~0=v_~d1_ev~0_8} AuxVars[] AssignedVars[~d1_ev~0] 4033#L326-3 [850] L326-3-->L331-3: Formula: (> v_~z_ev~0_10 0) InVars {~z_ev~0=v_~z_ev~0_10} OutVars{~z_ev~0=v_~z_ev~0_10} AuxVars[] AssignedVars[] 4032#L331-3 [570] L331-3-->L97-1: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_4|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_10, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 4030#L97-1 [588] L97-1-->L119-1: Formula: (and (= v_~b0_ev~0_13 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13 1)) InVars {~b0_ev~0=v_~b0_ev~0_13} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13, ~b0_ev~0=v_~b0_ev~0_13} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 3991#L119-1 [891] L119-1-->L380-3: Formula: (and (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20 |v_ULTIMATE.start_is_method1_triggered_#res_8|) (= |v_ULTIMATE.start_is_method1_triggered_#res_8| v_ULTIMATE.start_activate_threads_~tmp~1_14)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_14, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_8|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_8|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 3992#L380-3 [864] L380-3-->L380-5: Formula: (and (= v_~comp_m1_st~0_7 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11, ~comp_m1_st~0=v_~comp_m1_st~0_7} AuxVars[] AssignedVars[~comp_m1_st~0] 4188#L380-5 [869] L380-5-->L344-3: Formula: (> v_~b0_ev~0_20 1) InVars {~b0_ev~0=v_~b0_ev~0_20} OutVars{~b0_ev~0=v_~b0_ev~0_20} AuxVars[] AssignedVars[] 4187#L344-3 [870] L344-3-->L349-3: Formula: (< 1 v_~b1_ev~0_20) InVars {~b1_ev~0=v_~b1_ev~0_20} OutVars{~b1_ev~0=v_~b1_ev~0_20} AuxVars[] AssignedVars[] 4185#L349-3 [656] L349-3-->L354-3: Formula: (and (= v_~d0_ev~0_18 2) (= v_~d0_ev~0_19 1)) InVars {~d0_ev~0=v_~d0_ev~0_19} OutVars{~d0_ev~0=v_~d0_ev~0_18} AuxVars[] AssignedVars[~d0_ev~0] 4182#L354-3 [513] L354-3-->L359-3: Formula: (and (= 1 v_~d1_ev~0_19) (= v_~d1_ev~0_18 2)) InVars {~d1_ev~0=v_~d1_ev~0_19} OutVars{~d1_ev~0=v_~d1_ev~0_18} AuxVars[] AssignedVars[~d1_ev~0] 4180#L359-3 [876] L359-3-->L364-3: Formula: (> v_~z_ev~0_16 1) InVars {~z_ev~0=v_~z_ev~0_16} OutVars{~z_ev~0=v_~z_ev~0_16} AuxVars[] AssignedVars[] 4177#L364-3 [568] L364-3-->L258-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_5, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_2|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_#res] 4175#L258-1 [666] L258-1-->L265-1: Formula: (and (= v_~comp_m1_st~0_10 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9 1)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_10} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9, ~comp_m1_st~0=v_~comp_m1_st~0_10} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 4173#L265-1 [892] L265-1-->L397: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_stop_simulation_~tmp~2_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_4|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_~tmp~2] 4153#L397 [880] L397-->L404: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_4 0) (< 0 v_ULTIMATE.start_stop_simulation_~tmp~2_5)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_4, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 4142#L404 [897] L404-->L422-1: Formula: (and (= 0 v_ULTIMATE.start_start_simulation_~tmp~3_9) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= |v_ULTIMATE.start_stop_simulation_#res_5| v_ULTIMATE.start_start_simulation_~tmp~3_9)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_~tmp~3] 4139#L422-1 54.07/20.05 [2019-03-28 12:18:52,010 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.05 [2019-03-28 12:18:52,010 INFO L82 PathProgramCache]: Analyzing trace with hash -1636155352, now seen corresponding path program 1 times 54.07/20.05 [2019-03-28 12:18:52,010 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.05 [2019-03-28 12:18:52,010 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.05 [2019-03-28 12:18:52,011 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:52,011 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:52,011 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:52,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.05 [2019-03-28 12:18:52,028 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.05 [2019-03-28 12:18:52,028 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.05 [2019-03-28 12:18:52,029 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 54.07/20.05 [2019-03-28 12:18:52,029 INFO L799 eck$LassoCheckResult]: stem already infeasible 54.07/20.05 [2019-03-28 12:18:52,029 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.05 [2019-03-28 12:18:52,029 INFO L82 PathProgramCache]: Analyzing trace with hash 156507289, now seen corresponding path program 1 times 54.07/20.05 [2019-03-28 12:18:52,029 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.05 [2019-03-28 12:18:52,029 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.05 [2019-03-28 12:18:52,030 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:52,030 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:52,030 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:52,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.05 [2019-03-28 12:18:52,053 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.05 [2019-03-28 12:18:52,053 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.05 [2019-03-28 12:18:52,053 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 54.07/20.05 [2019-03-28 12:18:52,054 INFO L811 eck$LassoCheckResult]: loop already infeasible 54.07/20.05 [2019-03-28 12:18:52,054 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 54.07/20.05 [2019-03-28 12:18:52,054 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 54.07/20.05 [2019-03-28 12:18:52,054 INFO L87 Difference]: Start difference. First operand 444 states and 983 transitions. cyclomatic complexity: 540 Second operand 3 states. 54.07/20.05 [2019-03-28 12:18:52,304 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 54.07/20.05 [2019-03-28 12:18:52,304 INFO L93 Difference]: Finished difference Result 870 states and 1905 transitions. 54.07/20.05 [2019-03-28 12:18:52,304 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 54.07/20.05 [2019-03-28 12:18:52,305 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 870 states and 1905 transitions. 54.07/20.05 [2019-03-28 12:18:52,310 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 792 54.07/20.05 [2019-03-28 12:18:52,316 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 870 states to 870 states and 1905 transitions. 54.07/20.05 [2019-03-28 12:18:52,317 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 870 54.07/20.05 [2019-03-28 12:18:52,318 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 870 54.07/20.05 [2019-03-28 12:18:52,318 INFO L73 IsDeterministic]: Start isDeterministic. Operand 870 states and 1905 transitions. 54.07/20.05 [2019-03-28 12:18:52,320 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 54.07/20.05 [2019-03-28 12:18:52,320 INFO L706 BuchiCegarLoop]: Abstraction has 870 states and 1905 transitions. 54.07/20.05 [2019-03-28 12:18:52,320 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 870 states and 1905 transitions. 54.07/20.05 [2019-03-28 12:18:52,336 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 870 to 870. 54.07/20.05 [2019-03-28 12:18:52,336 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 870 states. 54.07/20.05 [2019-03-28 12:18:52,340 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 870 states to 870 states and 1905 transitions. 54.07/20.05 [2019-03-28 12:18:52,340 INFO L729 BuchiCegarLoop]: Abstraction has 870 states and 1905 transitions. 54.07/20.05 [2019-03-28 12:18:52,340 INFO L609 BuchiCegarLoop]: Abstraction has 870 states and 1905 transitions. 54.07/20.05 [2019-03-28 12:18:52,340 INFO L442 BuchiCegarLoop]: ======== Iteration 17============ 54.07/20.05 [2019-03-28 12:18:52,340 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 870 states and 1905 transitions. 54.07/20.05 [2019-03-28 12:18:52,345 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 792 54.07/20.05 [2019-03-28 12:18:52,345 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 54.07/20.05 [2019-03-28 12:18:52,346 INFO L119 BuchiIsEmpty]: Starting construction of run 54.07/20.05 [2019-03-28 12:18:52,347 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.05 [2019-03-28 12:18:52,347 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.05 [2019-03-28 12:18:52,347 INFO L794 eck$LassoCheckResult]: Stem: 5281#ULTIMATE.startENTRY [885] ULTIMATE.startENTRY-->L202: Formula: (and (= v_~d0_ev~0_23 2) (= 0 v_~z_val~0_13) (= 2 v_~b1_ev~0_23) (= v_~d0_val_t~0_9 1) (= v_~b0_val~0_13 0) (= 1 v_~b1_val_t~0_9) (= 1 v_~d1_req_up~0_12) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_9 0) (= 2 v_~d1_ev~0_23) (= v_~b1_val~0_13 0) (= v_~b0_val_t~0_9 1) (= v_~b0_req_up~0_12 1) (= 0 v_~comp_m1_i~0_7) (= v_~d0_req_up~0_12 1) (= v_~comp_m1_st~0_15 0) (= v_~b0_ev~0_23 2) (= 1 v_~d1_val_t~0_9) (= v_~z_req_up~0_12 0) (= v_~z_val_t~0_10 0) (= 0 v_~d1_val~0_13) (= v_~z_ev~0_19 2) (= v_~b1_req_up~0_12 1) (= 0 v_~d0_val~0_13)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_4|, ~b1_val~0=v_~b1_val~0_13, ~b0_val~0=v_~b0_val~0_13, ~d0_req_up~0=v_~d0_req_up~0_12, ~d0_val~0=v_~d0_val~0_13, ~d1_val_t~0=v_~d1_val_t~0_9, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_9, ~d1_ev~0=v_~d1_ev~0_23, ~d1_val~0=v_~d1_val~0_13, ~b0_req_up~0=v_~b0_req_up~0_12, ~z_ev~0=v_~z_ev~0_19, ~b1_val_t~0=v_~b1_val_t~0_9, ~b1_ev~0=v_~b1_ev~0_23, ULTIMATE.start_main_~__retres1~2=v_ULTIMATE.start_main_~__retres1~2_6, ~z_val~0=v_~z_val~0_13, ~d1_req_up~0=v_~d1_req_up~0_12, ~z_val_t~0=v_~z_val_t~0_10, ~b0_val_t~0=v_~b0_val_t~0_9, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~z_req_up~0=v_~z_req_up~0_12, ~b1_req_up~0=v_~b1_req_up~0_12, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~d0_ev~0=v_~d0_ev~0_23, ~b0_ev~0=v_~b0_ev~0_23, ~d0_val_t~0=v_~d0_val_t~0_9, ~comp_m1_st~0=v_~comp_m1_st~0_15, ~comp_m1_i~0=v_~comp_m1_i~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ~b1_val~0, ~b0_val~0, ~d0_req_up~0, ~d0_val~0, ~d1_val_t~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~d1_ev~0, ~d1_val~0, ~b0_req_up~0, ~z_ev~0, ~b1_val_t~0, ~b1_ev~0, ULTIMATE.start_main_~__retres1~2, ~z_val~0, ~d1_req_up~0, ~z_val_t~0, ~b0_val_t~0, ULTIMATE.start_start_simulation_~tmp~3, ~z_req_up~0, ~b1_req_up~0, ULTIMATE.start_main_#res, ~d0_ev~0, ~b0_ev~0, ~d0_val_t~0, ~comp_m1_st~0, ~comp_m1_i~0] 5282#L202 [566] L202-->L127: Formula: (= 1 v_~b0_req_up~0_4) InVars {~b0_req_up~0=v_~b0_req_up~0_4} OutVars{~b0_req_up~0=v_~b0_req_up~0_4} AuxVars[] AssignedVars[] 5238#L127 [748] L127-->L127-2: Formula: (and (= v_~b0_val~0_3 v_~b0_val_t~0_3) (> v_~b0_val_t~0_3 v_~b0_val~0_4) (= v_~b0_ev~0_3 0)) InVars {~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_4} OutVars{~b0_ev~0=v_~b0_ev~0_3, ~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_3} AuxVars[] AssignedVars[~b0_val~0, ~b0_ev~0] 5239#L127-2 [580] L127-2-->L202-1: Formula: (= v_~b0_req_up~0_5 0) InVars {} OutVars{~b0_req_up~0=v_~b0_req_up~0_5} AuxVars[] AssignedVars[~b0_req_up~0] 5277#L202-1 [545] L202-1-->L142: Formula: (= 1 v_~b1_req_up~0_4) InVars {~b1_req_up~0=v_~b1_req_up~0_4} OutVars{~b1_req_up~0=v_~b1_req_up~0_4} AuxVars[] AssignedVars[] 5257#L142 [752] L142-->L142-2: Formula: (and (= v_~b1_ev~0_3 0) (< v_~b1_val~0_4 v_~b1_val_t~0_3) (= v_~b1_val~0_3 v_~b1_val_t~0_3)) InVars {~b1_val_t~0=v_~b1_val_t~0_3, ~b1_val~0=v_~b1_val~0_4} OutVars{~b1_val_t~0=v_~b1_val_t~0_3, ~b1_ev~0=v_~b1_ev~0_3, ~b1_val~0=v_~b1_val~0_3} AuxVars[] AssignedVars[~b1_val~0, ~b1_ev~0] 5247#L142-2 [521] L142-2-->L209: Formula: (= v_~b1_req_up~0_5 0) InVars {} OutVars{~b1_req_up~0=v_~b1_req_up~0_5} AuxVars[] AssignedVars[~b1_req_up~0] 5248#L209 [624] L209-->L157: Formula: (= v_~d0_req_up~0_4 1) InVars {~d0_req_up~0=v_~d0_req_up~0_4} OutVars{~d0_req_up~0=v_~d0_req_up~0_4} AuxVars[] AssignedVars[] 5224#L157 [757] L157-->L157-2: Formula: (and (> v_~d0_val_t~0_3 v_~d0_val~0_4) (= v_~d0_val~0_3 v_~d0_val_t~0_3) (= v_~d0_ev~0_3 0)) InVars {~d0_val~0=v_~d0_val~0_4, ~d0_val_t~0=v_~d0_val_t~0_3} OutVars{~d0_ev~0=v_~d0_ev~0_3, ~d0_val~0=v_~d0_val~0_3, ~d0_val_t~0=v_~d0_val_t~0_3} AuxVars[] AssignedVars[~d0_ev~0, ~d0_val~0] 5215#L157-2 [600] L157-2-->L216: Formula: (= v_~d0_req_up~0_5 0) InVars {} OutVars{~d0_req_up~0=v_~d0_req_up~0_5} AuxVars[] AssignedVars[~d0_req_up~0] 5216#L216 [554] L216-->L172: Formula: (= v_~d1_req_up~0_4 1) InVars {~d1_req_up~0=v_~d1_req_up~0_4} OutVars{~d1_req_up~0=v_~d1_req_up~0_4} AuxVars[] AssignedVars[] 5286#L172 [760] L172-->L172-2: Formula: (and (= v_~d1_val~0_3 v_~d1_val_t~0_3) (= v_~d1_ev~0_3 0) (> v_~d1_val_t~0_3 v_~d1_val~0_4)) InVars {~d1_val_t~0=v_~d1_val_t~0_3, ~d1_val~0=v_~d1_val~0_4} OutVars{~d1_val_t~0=v_~d1_val_t~0_3, ~d1_val~0=v_~d1_val~0_3, ~d1_ev~0=v_~d1_ev~0_3} AuxVars[] AssignedVars[~d1_val~0, ~d1_ev~0] 5280#L172-2 [547] L172-2-->L223: Formula: (= v_~d1_req_up~0_5 0) InVars {} OutVars{~d1_req_up~0=v_~d1_req_up~0_5} AuxVars[] AssignedVars[~d1_req_up~0] 5279#L223 [762] L223-->L230: Formula: (> 1 v_~z_req_up~0_6) InVars {~z_req_up~0=v_~z_req_up~0_6} OutVars{~z_req_up~0=v_~z_req_up~0_6} AuxVars[] AssignedVars[] 5217#L230 [767] L230-->L245-1: Formula: (and (> 1 v_~comp_m1_i~0_4) (= v_~comp_m1_st~0_5 2)) InVars {~comp_m1_i~0=v_~comp_m1_i~0_4} OutVars{~comp_m1_st~0=v_~comp_m1_st~0_5, ~comp_m1_i~0=v_~comp_m1_i~0_4} AuxVars[] AssignedVars[~comp_m1_st~0] 5218#L245-1 [608] L245-1-->L311-1: Formula: (and (= v_~b0_ev~0_5 1) (= v_~b0_ev~0_6 0)) InVars {~b0_ev~0=v_~b0_ev~0_6} OutVars{~b0_ev~0=v_~b0_ev~0_5} AuxVars[] AssignedVars[~b0_ev~0] 5234#L311-1 [770] L311-1-->L316-1: Formula: (> 0 v_~b1_ev~0_7) InVars {~b1_ev~0=v_~b1_ev~0_7} OutVars{~b1_ev~0=v_~b1_ev~0_7} AuxVars[] AssignedVars[] 5343#L316-1 [654] L316-1-->L321-1: Formula: (and (= v_~d0_ev~0_5 1) (= v_~d0_ev~0_6 0)) InVars {~d0_ev~0=v_~d0_ev~0_6} OutVars{~d0_ev~0=v_~d0_ev~0_5} AuxVars[] AssignedVars[~d0_ev~0] 5341#L321-1 [507] L321-1-->L326-1: Formula: (and (= 0 v_~d1_ev~0_6) (= v_~d1_ev~0_5 1)) InVars {~d1_ev~0=v_~d1_ev~0_6} OutVars{~d1_ev~0=v_~d1_ev~0_5} AuxVars[] AssignedVars[~d1_ev~0] 5339#L326-1 [776] L326-1-->L331-1: Formula: (< 0 v_~z_ev~0_7) InVars {~z_ev~0=v_~z_ev~0_7} OutVars{~z_ev~0=v_~z_ev~0_7} AuxVars[] AssignedVars[] 5337#L331-1 [583] L331-1-->L97: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_1|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 5323#L97 [591] L97-->L119: Formula: (and (= v_~b0_ev~0_11 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4 1)) InVars {~b0_ev~0=v_~b0_ev~0_11} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4, ~b0_ev~0=v_~b0_ev~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 5325#L119 [886] L119-->L380: Formula: (and (= |v_ULTIMATE.start_is_method1_triggered_#res_7| v_ULTIMATE.start_activate_threads_~tmp~1_13) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19 |v_ULTIMATE.start_is_method1_triggered_#res_7|)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_13, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_7|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_7|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 5347#L380 [615] L380-->L380-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_9) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} AuxVars[] AssignedVars[] 5345#L380-2 [618] L380-2-->L344-1: Formula: (and (= v_~b0_ev~0_15 2) (= v_~b0_ev~0_16 1)) InVars {~b0_ev~0=v_~b0_ev~0_16} OutVars{~b0_ev~0=v_~b0_ev~0_15} AuxVars[] AssignedVars[~b0_ev~0] 5346#L344-1 [790] L344-1-->L349-1: Formula: (< 1 v_~b1_ev~0_17) InVars {~b1_ev~0=v_~b1_ev~0_17} OutVars{~b1_ev~0=v_~b1_ev~0_17} AuxVars[] AssignedVars[] 5689#L349-1 [652] L349-1-->L354-1: Formula: (and (= v_~d0_ev~0_15 2) (= v_~d0_ev~0_16 1)) InVars {~d0_ev~0=v_~d0_ev~0_16} OutVars{~d0_ev~0=v_~d0_ev~0_15} AuxVars[] AssignedVars[~d0_ev~0] 5732#L354-1 [795] L354-1-->L359-1: Formula: (> 1 v_~d1_ev~0_17) InVars {~d1_ev~0=v_~d1_ev~0_17} OutVars{~d1_ev~0=v_~d1_ev~0_17} AuxVars[] AssignedVars[] 5730#L359-1 [797] L359-1-->L422-1: Formula: (> v_~z_ev~0_13 1) InVars {~z_ev~0=v_~z_ev~0_13} OutVars{~z_ev~0=v_~z_ev~0_13} AuxVars[] AssignedVars[] 5716#L422-1 54.07/20.05 [2019-03-28 12:18:52,348 INFO L796 eck$LassoCheckResult]: Loop: 5716#L422-1 [887] L422-1-->L285: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 1) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 5617#L285 [888] L285-->L258: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_13, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res] 5671#L258 [802] L258-->L265: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8 0) (> 0 v_~comp_m1_st~0_9)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_9} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8, ~comp_m1_st~0=v_~comp_m1_st~0_9} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 5633#L265 [889] L265-->L280: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___0~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 5626#L280 [890] L280-->L202-2: Formula: (and (= v_ULTIMATE.start_eval_~tmp___0~0_8 0) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 2)) InVars {ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 5627#L202-2 [800] L202-2-->L202-3: Formula: (> 1 v_~b0_req_up~0_9) InVars {~b0_req_up~0=v_~b0_req_up~0_9} OutVars{~b0_req_up~0=v_~b0_req_up~0_9} AuxVars[] AssignedVars[] 5923#L202-3 [807] L202-3-->L209-1: Formula: (> 1 v_~b1_req_up~0_9) InVars {~b1_req_up~0=v_~b1_req_up~0_9} OutVars{~b1_req_up~0=v_~b1_req_up~0_9} AuxVars[] AssignedVars[] 5924#L209-1 [811] L209-1-->L216-1: Formula: (< v_~d0_req_up~0_9 1) InVars {~d0_req_up~0=v_~d0_req_up~0_9} OutVars{~d0_req_up~0=v_~d0_req_up~0_9} AuxVars[] AssignedVars[] 6056#L216-1 [815] L216-1-->L223-1: Formula: (< v_~d1_req_up~0_9 1) InVars {~d1_req_up~0=v_~d1_req_up~0_9} OutVars{~d1_req_up~0=v_~d1_req_up~0_9} AuxVars[] AssignedVars[] 6054#L223-1 [821] L223-1-->L230-1: Formula: (> 1 v_~z_req_up~0_9) InVars {~z_req_up~0=v_~z_req_up~0_9} OutVars{~z_req_up~0=v_~z_req_up~0_9} AuxVars[] AssignedVars[] 5869#L230-1 [498] L230-1-->L311-2: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 3) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 6053#L311-2 [632] L311-2-->L311-4: Formula: (and (= v_~b0_ev~0_8 1) (= v_~b0_ev~0_9 0)) InVars {~b0_ev~0=v_~b0_ev~0_9} OutVars{~b0_ev~0=v_~b0_ev~0_8} AuxVars[] AssignedVars[~b0_ev~0] 5274#L311-4 [833] L311-4-->L316-3: Formula: (< 0 v_~b1_ev~0_10) InVars {~b1_ev~0=v_~b1_ev~0_10} OutVars{~b1_ev~0=v_~b1_ev~0_10} AuxVars[] AssignedVars[] 5387#L316-3 [838] L316-3-->L321-3: Formula: (< v_~d0_ev~0_10 0) InVars {~d0_ev~0=v_~d0_ev~0_10} OutVars{~d0_ev~0=v_~d0_ev~0_10} AuxVars[] AssignedVars[] 5388#L321-3 [662] L321-3-->L326-3: Formula: (and (= v_~d1_ev~0_8 1) (= 0 v_~d1_ev~0_9)) InVars {~d1_ev~0=v_~d1_ev~0_9} OutVars{~d1_ev~0=v_~d1_ev~0_8} AuxVars[] AssignedVars[~d1_ev~0] 6023#L326-3 [850] L326-3-->L331-3: Formula: (> v_~z_ev~0_10 0) InVars {~z_ev~0=v_~z_ev~0_10} OutVars{~z_ev~0=v_~z_ev~0_10} AuxVars[] AssignedVars[] 6022#L331-3 [570] L331-3-->L97-1: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_4|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_10, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 6020#L97-1 [588] L97-1-->L119-1: Formula: (and (= v_~b0_ev~0_13 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13 1)) InVars {~b0_ev~0=v_~b0_ev~0_13} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13, ~b0_ev~0=v_~b0_ev~0_13} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 5250#L119-1 [891] L119-1-->L380-3: Formula: (and (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20 |v_ULTIMATE.start_is_method1_triggered_#res_8|) (= |v_ULTIMATE.start_is_method1_triggered_#res_8| v_ULTIMATE.start_activate_threads_~tmp~1_14)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_14, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_8|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_8|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 5314#L380-3 [864] L380-3-->L380-5: Formula: (and (= v_~comp_m1_st~0_7 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11, ~comp_m1_st~0=v_~comp_m1_st~0_7} AuxVars[] AssignedVars[~comp_m1_st~0] 5371#L380-5 [869] L380-5-->L344-3: Formula: (> v_~b0_ev~0_20 1) InVars {~b0_ev~0=v_~b0_ev~0_20} OutVars{~b0_ev~0=v_~b0_ev~0_20} AuxVars[] AssignedVars[] 5373#L344-3 [870] L344-3-->L349-3: Formula: (< 1 v_~b1_ev~0_20) InVars {~b1_ev~0=v_~b1_ev~0_20} OutVars{~b1_ev~0=v_~b1_ev~0_20} AuxVars[] AssignedVars[] 5723#L349-3 [656] L349-3-->L354-3: Formula: (and (= v_~d0_ev~0_18 2) (= v_~d0_ev~0_19 1)) InVars {~d0_ev~0=v_~d0_ev~0_19} OutVars{~d0_ev~0=v_~d0_ev~0_18} AuxVars[] AssignedVars[~d0_ev~0] 5839#L354-3 [513] L354-3-->L359-3: Formula: (and (= 1 v_~d1_ev~0_19) (= v_~d1_ev~0_18 2)) InVars {~d1_ev~0=v_~d1_ev~0_19} OutVars{~d1_ev~0=v_~d1_ev~0_18} AuxVars[] AssignedVars[~d1_ev~0] 5837#L359-3 [876] L359-3-->L364-3: Formula: (> v_~z_ev~0_16 1) InVars {~z_ev~0=v_~z_ev~0_16} OutVars{~z_ev~0=v_~z_ev~0_16} AuxVars[] AssignedVars[] 5488#L364-3 [568] L364-3-->L258-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_5, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_2|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_#res] 5834#L258-1 [666] L258-1-->L265-1: Formula: (and (= v_~comp_m1_st~0_10 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9 1)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_10} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9, ~comp_m1_st~0=v_~comp_m1_st~0_10} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 5832#L265-1 [892] L265-1-->L397: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_stop_simulation_~tmp~2_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_4|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_~tmp~2] 5827#L397 [880] L397-->L404: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_4 0) (< 0 v_ULTIMATE.start_stop_simulation_~tmp~2_5)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_4, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 5729#L404 [897] L404-->L422-1: Formula: (and (= 0 v_ULTIMATE.start_start_simulation_~tmp~3_9) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= |v_ULTIMATE.start_stop_simulation_#res_5| v_ULTIMATE.start_start_simulation_~tmp~3_9)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_~tmp~3] 5716#L422-1 54.07/20.05 [2019-03-28 12:18:52,348 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.05 [2019-03-28 12:18:52,348 INFO L82 PathProgramCache]: Analyzing trace with hash -349739177, now seen corresponding path program 1 times 54.07/20.05 [2019-03-28 12:18:52,348 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.05 [2019-03-28 12:18:52,349 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.05 [2019-03-28 12:18:52,349 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:52,350 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:52,350 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:52,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.05 [2019-03-28 12:18:52,368 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.05 [2019-03-28 12:18:52,368 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.05 [2019-03-28 12:18:52,368 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 54.07/20.05 [2019-03-28 12:18:52,368 INFO L799 eck$LassoCheckResult]: stem already infeasible 54.07/20.05 [2019-03-28 12:18:52,369 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.05 [2019-03-28 12:18:52,369 INFO L82 PathProgramCache]: Analyzing trace with hash -840565064, now seen corresponding path program 1 times 54.07/20.05 [2019-03-28 12:18:52,369 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.05 [2019-03-28 12:18:52,369 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.05 [2019-03-28 12:18:52,370 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:52,370 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:52,370 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:52,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.05 [2019-03-28 12:18:52,400 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.05 [2019-03-28 12:18:52,401 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.05 [2019-03-28 12:18:52,401 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 54.07/20.05 [2019-03-28 12:18:52,401 INFO L811 eck$LassoCheckResult]: loop already infeasible 54.07/20.05 [2019-03-28 12:18:52,401 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 54.07/20.05 [2019-03-28 12:18:52,401 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 54.07/20.05 [2019-03-28 12:18:52,402 INFO L87 Difference]: Start difference. First operand 870 states and 1905 transitions. cyclomatic complexity: 1036 Second operand 3 states. 54.07/20.05 [2019-03-28 12:18:52,538 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 54.07/20.05 [2019-03-28 12:18:52,539 INFO L93 Difference]: Finished difference Result 540 states and 1125 transitions. 54.07/20.05 [2019-03-28 12:18:52,539 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 54.07/20.05 [2019-03-28 12:18:52,539 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 540 states and 1125 transitions. 54.07/20.05 [2019-03-28 12:18:52,543 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 492 54.07/20.05 [2019-03-28 12:18:52,546 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 540 states to 540 states and 1125 transitions. 54.07/20.05 [2019-03-28 12:18:52,546 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 540 54.07/20.05 [2019-03-28 12:18:52,547 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 540 54.07/20.05 [2019-03-28 12:18:52,547 INFO L73 IsDeterministic]: Start isDeterministic. Operand 540 states and 1125 transitions. 54.07/20.05 [2019-03-28 12:18:52,548 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 54.07/20.05 [2019-03-28 12:18:52,549 INFO L706 BuchiCegarLoop]: Abstraction has 540 states and 1125 transitions. 54.07/20.05 [2019-03-28 12:18:52,549 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 540 states and 1125 transitions. 54.07/20.05 [2019-03-28 12:18:52,558 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 540 to 540. 54.07/20.05 [2019-03-28 12:18:52,558 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 540 states. 54.07/20.05 [2019-03-28 12:18:52,560 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 540 states to 540 states and 1125 transitions. 54.07/20.05 [2019-03-28 12:18:52,560 INFO L729 BuchiCegarLoop]: Abstraction has 540 states and 1125 transitions. 54.07/20.05 [2019-03-28 12:18:52,560 INFO L609 BuchiCegarLoop]: Abstraction has 540 states and 1125 transitions. 54.07/20.05 [2019-03-28 12:18:52,560 INFO L442 BuchiCegarLoop]: ======== Iteration 18============ 54.07/20.05 [2019-03-28 12:18:52,560 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 540 states and 1125 transitions. 54.07/20.05 [2019-03-28 12:18:52,563 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 492 54.07/20.05 [2019-03-28 12:18:52,563 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 54.07/20.05 [2019-03-28 12:18:52,563 INFO L119 BuchiIsEmpty]: Starting construction of run 54.07/20.05 [2019-03-28 12:18:52,564 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.05 [2019-03-28 12:18:52,564 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.05 [2019-03-28 12:18:52,565 INFO L794 eck$LassoCheckResult]: Stem: 6699#ULTIMATE.startENTRY [885] ULTIMATE.startENTRY-->L202: Formula: (and (= v_~d0_ev~0_23 2) (= 0 v_~z_val~0_13) (= 2 v_~b1_ev~0_23) (= v_~d0_val_t~0_9 1) (= v_~b0_val~0_13 0) (= 1 v_~b1_val_t~0_9) (= 1 v_~d1_req_up~0_12) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_9 0) (= 2 v_~d1_ev~0_23) (= v_~b1_val~0_13 0) (= v_~b0_val_t~0_9 1) (= v_~b0_req_up~0_12 1) (= 0 v_~comp_m1_i~0_7) (= v_~d0_req_up~0_12 1) (= v_~comp_m1_st~0_15 0) (= v_~b0_ev~0_23 2) (= 1 v_~d1_val_t~0_9) (= v_~z_req_up~0_12 0) (= v_~z_val_t~0_10 0) (= 0 v_~d1_val~0_13) (= v_~z_ev~0_19 2) (= v_~b1_req_up~0_12 1) (= 0 v_~d0_val~0_13)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_4|, ~b1_val~0=v_~b1_val~0_13, ~b0_val~0=v_~b0_val~0_13, ~d0_req_up~0=v_~d0_req_up~0_12, ~d0_val~0=v_~d0_val~0_13, ~d1_val_t~0=v_~d1_val_t~0_9, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_9, ~d1_ev~0=v_~d1_ev~0_23, ~d1_val~0=v_~d1_val~0_13, ~b0_req_up~0=v_~b0_req_up~0_12, ~z_ev~0=v_~z_ev~0_19, ~b1_val_t~0=v_~b1_val_t~0_9, ~b1_ev~0=v_~b1_ev~0_23, ULTIMATE.start_main_~__retres1~2=v_ULTIMATE.start_main_~__retres1~2_6, ~z_val~0=v_~z_val~0_13, ~d1_req_up~0=v_~d1_req_up~0_12, ~z_val_t~0=v_~z_val_t~0_10, ~b0_val_t~0=v_~b0_val_t~0_9, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~z_req_up~0=v_~z_req_up~0_12, ~b1_req_up~0=v_~b1_req_up~0_12, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~d0_ev~0=v_~d0_ev~0_23, ~b0_ev~0=v_~b0_ev~0_23, ~d0_val_t~0=v_~d0_val_t~0_9, ~comp_m1_st~0=v_~comp_m1_st~0_15, ~comp_m1_i~0=v_~comp_m1_i~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ~b1_val~0, ~b0_val~0, ~d0_req_up~0, ~d0_val~0, ~d1_val_t~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~d1_ev~0, ~d1_val~0, ~b0_req_up~0, ~z_ev~0, ~b1_val_t~0, ~b1_ev~0, ULTIMATE.start_main_~__retres1~2, ~z_val~0, ~d1_req_up~0, ~z_val_t~0, ~b0_val_t~0, ULTIMATE.start_start_simulation_~tmp~3, ~z_req_up~0, ~b1_req_up~0, ULTIMATE.start_main_#res, ~d0_ev~0, ~b0_ev~0, ~d0_val_t~0, ~comp_m1_st~0, ~comp_m1_i~0] 6700#L202 [566] L202-->L127: Formula: (= 1 v_~b0_req_up~0_4) InVars {~b0_req_up~0=v_~b0_req_up~0_4} OutVars{~b0_req_up~0=v_~b0_req_up~0_4} AuxVars[] AssignedVars[] 6656#L127 [748] L127-->L127-2: Formula: (and (= v_~b0_val~0_3 v_~b0_val_t~0_3) (> v_~b0_val_t~0_3 v_~b0_val~0_4) (= v_~b0_ev~0_3 0)) InVars {~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_4} OutVars{~b0_ev~0=v_~b0_ev~0_3, ~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_3} AuxVars[] AssignedVars[~b0_val~0, ~b0_ev~0] 6657#L127-2 [580] L127-2-->L202-1: Formula: (= v_~b0_req_up~0_5 0) InVars {} OutVars{~b0_req_up~0=v_~b0_req_up~0_5} AuxVars[] AssignedVars[~b0_req_up~0] 6695#L202-1 [545] L202-1-->L142: Formula: (= 1 v_~b1_req_up~0_4) InVars {~b1_req_up~0=v_~b1_req_up~0_4} OutVars{~b1_req_up~0=v_~b1_req_up~0_4} AuxVars[] AssignedVars[] 6674#L142 [752] L142-->L142-2: Formula: (and (= v_~b1_ev~0_3 0) (< v_~b1_val~0_4 v_~b1_val_t~0_3) (= v_~b1_val~0_3 v_~b1_val_t~0_3)) InVars {~b1_val_t~0=v_~b1_val_t~0_3, ~b1_val~0=v_~b1_val~0_4} OutVars{~b1_val_t~0=v_~b1_val_t~0_3, ~b1_ev~0=v_~b1_ev~0_3, ~b1_val~0=v_~b1_val~0_3} AuxVars[] AssignedVars[~b1_val~0, ~b1_ev~0] 6667#L142-2 [521] L142-2-->L209: Formula: (= v_~b1_req_up~0_5 0) InVars {} OutVars{~b1_req_up~0=v_~b1_req_up~0_5} AuxVars[] AssignedVars[~b1_req_up~0] 6668#L209 [624] L209-->L157: Formula: (= v_~d0_req_up~0_4 1) InVars {~d0_req_up~0=v_~d0_req_up~0_4} OutVars{~d0_req_up~0=v_~d0_req_up~0_4} AuxVars[] AssignedVars[] 6643#L157 [757] L157-->L157-2: Formula: (and (> v_~d0_val_t~0_3 v_~d0_val~0_4) (= v_~d0_val~0_3 v_~d0_val_t~0_3) (= v_~d0_ev~0_3 0)) InVars {~d0_val~0=v_~d0_val~0_4, ~d0_val_t~0=v_~d0_val_t~0_3} OutVars{~d0_ev~0=v_~d0_ev~0_3, ~d0_val~0=v_~d0_val~0_3, ~d0_val_t~0=v_~d0_val_t~0_3} AuxVars[] AssignedVars[~d0_ev~0, ~d0_val~0] 6632#L157-2 [600] L157-2-->L216: Formula: (= v_~d0_req_up~0_5 0) InVars {} OutVars{~d0_req_up~0=v_~d0_req_up~0_5} AuxVars[] AssignedVars[~d0_req_up~0] 6633#L216 [554] L216-->L172: Formula: (= v_~d1_req_up~0_4 1) InVars {~d1_req_up~0=v_~d1_req_up~0_4} OutVars{~d1_req_up~0=v_~d1_req_up~0_4} AuxVars[] AssignedVars[] 6704#L172 [760] L172-->L172-2: Formula: (and (= v_~d1_val~0_3 v_~d1_val_t~0_3) (= v_~d1_ev~0_3 0) (> v_~d1_val_t~0_3 v_~d1_val~0_4)) InVars {~d1_val_t~0=v_~d1_val_t~0_3, ~d1_val~0=v_~d1_val~0_4} OutVars{~d1_val_t~0=v_~d1_val_t~0_3, ~d1_val~0=v_~d1_val~0_3, ~d1_ev~0=v_~d1_ev~0_3} AuxVars[] AssignedVars[~d1_val~0, ~d1_ev~0] 6698#L172-2 [547] L172-2-->L223: Formula: (= v_~d1_req_up~0_5 0) InVars {} OutVars{~d1_req_up~0=v_~d1_req_up~0_5} AuxVars[] AssignedVars[~d1_req_up~0] 6697#L223 [762] L223-->L230: Formula: (> 1 v_~z_req_up~0_6) InVars {~z_req_up~0=v_~z_req_up~0_6} OutVars{~z_req_up~0=v_~z_req_up~0_6} AuxVars[] AssignedVars[] 6634#L230 [767] L230-->L245-1: Formula: (and (> 1 v_~comp_m1_i~0_4) (= v_~comp_m1_st~0_5 2)) InVars {~comp_m1_i~0=v_~comp_m1_i~0_4} OutVars{~comp_m1_st~0=v_~comp_m1_st~0_5, ~comp_m1_i~0=v_~comp_m1_i~0_4} AuxVars[] AssignedVars[~comp_m1_st~0] 6635#L245-1 [608] L245-1-->L311-1: Formula: (and (= v_~b0_ev~0_5 1) (= v_~b0_ev~0_6 0)) InVars {~b0_ev~0=v_~b0_ev~0_6} OutVars{~b0_ev~0=v_~b0_ev~0_5} AuxVars[] AssignedVars[~b0_ev~0] 6654#L311-1 [628] L311-1-->L316-1: Formula: (and (= 0 v_~b1_ev~0_6) (= v_~b1_ev~0_5 1)) InVars {~b1_ev~0=v_~b1_ev~0_6} OutVars{~b1_ev~0=v_~b1_ev~0_5} AuxVars[] AssignedVars[~b1_ev~0] 6718#L316-1 [654] L316-1-->L321-1: Formula: (and (= v_~d0_ev~0_5 1) (= v_~d0_ev~0_6 0)) InVars {~d0_ev~0=v_~d0_ev~0_6} OutVars{~d0_ev~0=v_~d0_ev~0_5} AuxVars[] AssignedVars[~d0_ev~0] 6647#L321-1 [507] L321-1-->L326-1: Formula: (and (= 0 v_~d1_ev~0_6) (= v_~d1_ev~0_5 1)) InVars {~d1_ev~0=v_~d1_ev~0_6} OutVars{~d1_ev~0=v_~d1_ev~0_5} AuxVars[] AssignedVars[~d1_ev~0] 6648#L326-1 [776] L326-1-->L331-1: Formula: (< 0 v_~z_ev~0_7) InVars {~z_ev~0=v_~z_ev~0_7} OutVars{~z_ev~0=v_~z_ev~0_7} AuxVars[] AssignedVars[] 6707#L331-1 [583] L331-1-->L97: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_1|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 6733#L97 [591] L97-->L119: Formula: (and (= v_~b0_ev~0_11 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4 1)) InVars {~b0_ev~0=v_~b0_ev~0_11} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4, ~b0_ev~0=v_~b0_ev~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 6672#L119 [886] L119-->L380: Formula: (and (= |v_ULTIMATE.start_is_method1_triggered_#res_7| v_ULTIMATE.start_activate_threads_~tmp~1_13) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19 |v_ULTIMATE.start_is_method1_triggered_#res_7|)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_13, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_7|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_7|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 6736#L380 [615] L380-->L380-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_9) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} AuxVars[] AssignedVars[] 6734#L380-2 [618] L380-2-->L344-1: Formula: (and (= v_~b0_ev~0_15 2) (= v_~b0_ev~0_16 1)) InVars {~b0_ev~0=v_~b0_ev~0_16} OutVars{~b0_ev~0=v_~b0_ev~0_15} AuxVars[] AssignedVars[~b0_ev~0] 6682#L344-1 [790] L344-1-->L349-1: Formula: (< 1 v_~b1_ev~0_17) InVars {~b1_ev~0=v_~b1_ev~0_17} OutVars{~b1_ev~0=v_~b1_ev~0_17} AuxVars[] AssignedVars[] 6683#L349-1 [652] L349-1-->L354-1: Formula: (and (= v_~d0_ev~0_15 2) (= v_~d0_ev~0_16 1)) InVars {~d0_ev~0=v_~d0_ev~0_16} OutVars{~d0_ev~0=v_~d0_ev~0_15} AuxVars[] AssignedVars[~d0_ev~0] 6639#L354-1 [795] L354-1-->L359-1: Formula: (> 1 v_~d1_ev~0_17) InVars {~d1_ev~0=v_~d1_ev~0_17} OutVars{~d1_ev~0=v_~d1_ev~0_17} AuxVars[] AssignedVars[] 6640#L359-1 [797] L359-1-->L422-1: Formula: (> v_~z_ev~0_13 1) InVars {~z_ev~0=v_~z_ev~0_13} OutVars{~z_ev~0=v_~z_ev~0_13} AuxVars[] AssignedVars[] 6705#L422-1 54.07/20.05 [2019-03-28 12:18:52,565 INFO L796 eck$LassoCheckResult]: Loop: 6705#L422-1 [887] L422-1-->L285: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 1) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 6823#L285 [888] L285-->L258: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_13, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res] 6821#L258 [802] L258-->L265: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8 0) (> 0 v_~comp_m1_st~0_9)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_9} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8, ~comp_m1_st~0=v_~comp_m1_st~0_9} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 6818#L265 [889] L265-->L280: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___0~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 6810#L280 [890] L280-->L202-2: Formula: (and (= v_ULTIMATE.start_eval_~tmp___0~0_8 0) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 2)) InVars {ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 6803#L202-2 [800] L202-2-->L202-3: Formula: (> 1 v_~b0_req_up~0_9) InVars {~b0_req_up~0=v_~b0_req_up~0_9} OutVars{~b0_req_up~0=v_~b0_req_up~0_9} AuxVars[] AssignedVars[] 6804#L202-3 [807] L202-3-->L209-1: Formula: (> 1 v_~b1_req_up~0_9) InVars {~b1_req_up~0=v_~b1_req_up~0_9} OutVars{~b1_req_up~0=v_~b1_req_up~0_9} AuxVars[] AssignedVars[] 7085#L209-1 [811] L209-1-->L216-1: Formula: (< v_~d0_req_up~0_9 1) InVars {~d0_req_up~0=v_~d0_req_up~0_9} OutVars{~d0_req_up~0=v_~d0_req_up~0_9} AuxVars[] AssignedVars[] 7082#L216-1 [815] L216-1-->L223-1: Formula: (< v_~d1_req_up~0_9 1) InVars {~d1_req_up~0=v_~d1_req_up~0_9} OutVars{~d1_req_up~0=v_~d1_req_up~0_9} AuxVars[] AssignedVars[] 7068#L223-1 [821] L223-1-->L230-1: Formula: (> 1 v_~z_req_up~0_9) InVars {~z_req_up~0=v_~z_req_up~0_9} OutVars{~z_req_up~0=v_~z_req_up~0_9} AuxVars[] AssignedVars[] 7065#L230-1 [498] L230-1-->L311-2: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 3) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 7059#L311-2 [632] L311-2-->L311-4: Formula: (and (= v_~b0_ev~0_8 1) (= v_~b0_ev~0_9 0)) InVars {~b0_ev~0=v_~b0_ev~0_9} OutVars{~b0_ev~0=v_~b0_ev~0_8} AuxVars[] AssignedVars[~b0_ev~0] 7055#L311-4 [833] L311-4-->L316-3: Formula: (< 0 v_~b1_ev~0_10) InVars {~b1_ev~0=v_~b1_ev~0_10} OutVars{~b1_ev~0=v_~b1_ev~0_10} AuxVars[] AssignedVars[] 7053#L316-3 [838] L316-3-->L321-3: Formula: (< v_~d0_ev~0_10 0) InVars {~d0_ev~0=v_~d0_ev~0_10} OutVars{~d0_ev~0=v_~d0_ev~0_10} AuxVars[] AssignedVars[] 7050#L321-3 [662] L321-3-->L326-3: Formula: (and (= v_~d1_ev~0_8 1) (= 0 v_~d1_ev~0_9)) InVars {~d1_ev~0=v_~d1_ev~0_9} OutVars{~d1_ev~0=v_~d1_ev~0_8} AuxVars[] AssignedVars[~d1_ev~0] 7048#L326-3 [850] L326-3-->L331-3: Formula: (> v_~z_ev~0_10 0) InVars {~z_ev~0=v_~z_ev~0_10} OutVars{~z_ev~0=v_~z_ev~0_10} AuxVars[] AssignedVars[] 7047#L331-3 [570] L331-3-->L97-1: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_4|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_10, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 6926#L97-1 [588] L97-1-->L119-1: Formula: (and (= v_~b0_ev~0_13 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13 1)) InVars {~b0_ev~0=v_~b0_ev~0_13} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13, ~b0_ev~0=v_~b0_ev~0_13} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 6920#L119-1 [891] L119-1-->L380-3: Formula: (and (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20 |v_ULTIMATE.start_is_method1_triggered_#res_8|) (= |v_ULTIMATE.start_is_method1_triggered_#res_8| v_ULTIMATE.start_activate_threads_~tmp~1_14)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_14, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_8|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_8|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 6919#L380-3 [864] L380-3-->L380-5: Formula: (and (= v_~comp_m1_st~0_7 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11, ~comp_m1_st~0=v_~comp_m1_st~0_7} AuxVars[] AssignedVars[~comp_m1_st~0] 6887#L380-5 [869] L380-5-->L344-3: Formula: (> v_~b0_ev~0_20 1) InVars {~b0_ev~0=v_~b0_ev~0_20} OutVars{~b0_ev~0=v_~b0_ev~0_20} AuxVars[] AssignedVars[] 6885#L344-3 [870] L344-3-->L349-3: Formula: (< 1 v_~b1_ev~0_20) InVars {~b1_ev~0=v_~b1_ev~0_20} OutVars{~b1_ev~0=v_~b1_ev~0_20} AuxVars[] AssignedVars[] 6883#L349-3 [656] L349-3-->L354-3: Formula: (and (= v_~d0_ev~0_18 2) (= v_~d0_ev~0_19 1)) InVars {~d0_ev~0=v_~d0_ev~0_19} OutVars{~d0_ev~0=v_~d0_ev~0_18} AuxVars[] AssignedVars[~d0_ev~0] 6880#L354-3 [513] L354-3-->L359-3: Formula: (and (= 1 v_~d1_ev~0_19) (= v_~d1_ev~0_18 2)) InVars {~d1_ev~0=v_~d1_ev~0_19} OutVars{~d1_ev~0=v_~d1_ev~0_18} AuxVars[] AssignedVars[~d1_ev~0] 6877#L359-3 [876] L359-3-->L364-3: Formula: (> v_~z_ev~0_16 1) InVars {~z_ev~0=v_~z_ev~0_16} OutVars{~z_ev~0=v_~z_ev~0_16} AuxVars[] AssignedVars[] 6872#L364-3 [568] L364-3-->L258-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_5, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_2|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_#res] 6869#L258-1 [666] L258-1-->L265-1: Formula: (and (= v_~comp_m1_st~0_10 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9 1)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_10} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9, ~comp_m1_st~0=v_~comp_m1_st~0_10} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 6866#L265-1 [892] L265-1-->L397: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_stop_simulation_~tmp~2_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_4|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_~tmp~2] 6843#L397 [880] L397-->L404: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_4 0) (< 0 v_ULTIMATE.start_stop_simulation_~tmp~2_5)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_4, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 6837#L404 [897] L404-->L422-1: Formula: (and (= 0 v_ULTIMATE.start_start_simulation_~tmp~3_9) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= |v_ULTIMATE.start_stop_simulation_#res_5| v_ULTIMATE.start_start_simulation_~tmp~3_9)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_~tmp~3] 6705#L422-1 54.07/20.05 [2019-03-28 12:18:52,565 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.05 [2019-03-28 12:18:52,566 INFO L82 PathProgramCache]: Analyzing trace with hash -1636185143, now seen corresponding path program 1 times 54.07/20.05 [2019-03-28 12:18:52,566 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.05 [2019-03-28 12:18:52,566 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.05 [2019-03-28 12:18:52,567 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:52,567 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:52,567 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:52,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.05 [2019-03-28 12:18:52,583 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.05 [2019-03-28 12:18:52,583 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.05 [2019-03-28 12:18:52,583 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 54.07/20.05 [2019-03-28 12:18:52,583 INFO L799 eck$LassoCheckResult]: stem already infeasible 54.07/20.05 [2019-03-28 12:18:52,584 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.05 [2019-03-28 12:18:52,584 INFO L82 PathProgramCache]: Analyzing trace with hash -840565064, now seen corresponding path program 2 times 54.07/20.05 [2019-03-28 12:18:52,584 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.05 [2019-03-28 12:18:52,584 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.05 [2019-03-28 12:18:52,585 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:52,585 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:52,585 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:52,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.05 [2019-03-28 12:18:52,598 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.05 [2019-03-28 12:18:52,599 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.05 [2019-03-28 12:18:52,599 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 54.07/20.05 [2019-03-28 12:18:52,599 INFO L811 eck$LassoCheckResult]: loop already infeasible 54.07/20.05 [2019-03-28 12:18:52,599 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 54.07/20.05 [2019-03-28 12:18:52,599 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 54.07/20.05 [2019-03-28 12:18:52,600 INFO L87 Difference]: Start difference. First operand 540 states and 1125 transitions. cyclomatic complexity: 586 Second operand 3 states. 54.07/20.05 [2019-03-28 12:18:52,803 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 54.07/20.05 [2019-03-28 12:18:52,804 INFO L93 Difference]: Finished difference Result 616 states and 1261 transitions. 54.07/20.05 [2019-03-28 12:18:52,804 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 54.07/20.05 [2019-03-28 12:18:52,804 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 616 states and 1261 transitions. 54.07/20.05 [2019-03-28 12:18:52,808 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 572 54.07/20.05 [2019-03-28 12:18:52,812 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 616 states to 616 states and 1261 transitions. 54.07/20.05 [2019-03-28 12:18:52,812 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 616 54.07/20.05 [2019-03-28 12:18:52,813 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 616 54.07/20.05 [2019-03-28 12:18:52,813 INFO L73 IsDeterministic]: Start isDeterministic. Operand 616 states and 1261 transitions. 54.07/20.05 [2019-03-28 12:18:52,814 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 54.07/20.05 [2019-03-28 12:18:52,814 INFO L706 BuchiCegarLoop]: Abstraction has 616 states and 1261 transitions. 54.07/20.05 [2019-03-28 12:18:52,815 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 616 states and 1261 transitions. 54.07/20.05 [2019-03-28 12:18:52,828 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 616 to 616. 54.07/20.05 [2019-03-28 12:18:52,829 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 616 states. 54.07/20.05 [2019-03-28 12:18:52,830 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 616 states to 616 states and 1261 transitions. 54.07/20.05 [2019-03-28 12:18:52,831 INFO L729 BuchiCegarLoop]: Abstraction has 616 states and 1261 transitions. 54.07/20.05 [2019-03-28 12:18:52,831 INFO L609 BuchiCegarLoop]: Abstraction has 616 states and 1261 transitions. 54.07/20.05 [2019-03-28 12:18:52,831 INFO L442 BuchiCegarLoop]: ======== Iteration 19============ 54.07/20.05 [2019-03-28 12:18:52,831 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 616 states and 1261 transitions. 54.07/20.05 [2019-03-28 12:18:52,834 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 572 54.07/20.05 [2019-03-28 12:18:52,834 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 54.07/20.05 [2019-03-28 12:18:52,834 INFO L119 BuchiIsEmpty]: Starting construction of run 54.07/20.05 [2019-03-28 12:18:52,835 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.05 [2019-03-28 12:18:52,835 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.05 [2019-03-28 12:18:52,836 INFO L794 eck$LassoCheckResult]: Stem: 7859#ULTIMATE.startENTRY [885] ULTIMATE.startENTRY-->L202: Formula: (and (= v_~d0_ev~0_23 2) (= 0 v_~z_val~0_13) (= 2 v_~b1_ev~0_23) (= v_~d0_val_t~0_9 1) (= v_~b0_val~0_13 0) (= 1 v_~b1_val_t~0_9) (= 1 v_~d1_req_up~0_12) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_9 0) (= 2 v_~d1_ev~0_23) (= v_~b1_val~0_13 0) (= v_~b0_val_t~0_9 1) (= v_~b0_req_up~0_12 1) (= 0 v_~comp_m1_i~0_7) (= v_~d0_req_up~0_12 1) (= v_~comp_m1_st~0_15 0) (= v_~b0_ev~0_23 2) (= 1 v_~d1_val_t~0_9) (= v_~z_req_up~0_12 0) (= v_~z_val_t~0_10 0) (= 0 v_~d1_val~0_13) (= v_~z_ev~0_19 2) (= v_~b1_req_up~0_12 1) (= 0 v_~d0_val~0_13)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_4|, ~b1_val~0=v_~b1_val~0_13, ~b0_val~0=v_~b0_val~0_13, ~d0_req_up~0=v_~d0_req_up~0_12, ~d0_val~0=v_~d0_val~0_13, ~d1_val_t~0=v_~d1_val_t~0_9, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_9, ~d1_ev~0=v_~d1_ev~0_23, ~d1_val~0=v_~d1_val~0_13, ~b0_req_up~0=v_~b0_req_up~0_12, ~z_ev~0=v_~z_ev~0_19, ~b1_val_t~0=v_~b1_val_t~0_9, ~b1_ev~0=v_~b1_ev~0_23, ULTIMATE.start_main_~__retres1~2=v_ULTIMATE.start_main_~__retres1~2_6, ~z_val~0=v_~z_val~0_13, ~d1_req_up~0=v_~d1_req_up~0_12, ~z_val_t~0=v_~z_val_t~0_10, ~b0_val_t~0=v_~b0_val_t~0_9, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~z_req_up~0=v_~z_req_up~0_12, ~b1_req_up~0=v_~b1_req_up~0_12, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~d0_ev~0=v_~d0_ev~0_23, ~b0_ev~0=v_~b0_ev~0_23, ~d0_val_t~0=v_~d0_val_t~0_9, ~comp_m1_st~0=v_~comp_m1_st~0_15, ~comp_m1_i~0=v_~comp_m1_i~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ~b1_val~0, ~b0_val~0, ~d0_req_up~0, ~d0_val~0, ~d1_val_t~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~d1_ev~0, ~d1_val~0, ~b0_req_up~0, ~z_ev~0, ~b1_val_t~0, ~b1_ev~0, ULTIMATE.start_main_~__retres1~2, ~z_val~0, ~d1_req_up~0, ~z_val_t~0, ~b0_val_t~0, ULTIMATE.start_start_simulation_~tmp~3, ~z_req_up~0, ~b1_req_up~0, ULTIMATE.start_main_#res, ~d0_ev~0, ~b0_ev~0, ~d0_val_t~0, ~comp_m1_st~0, ~comp_m1_i~0] 7860#L202 [566] L202-->L127: Formula: (= 1 v_~b0_req_up~0_4) InVars {~b0_req_up~0=v_~b0_req_up~0_4} OutVars{~b0_req_up~0=v_~b0_req_up~0_4} AuxVars[] AssignedVars[] 7819#L127 [748] L127-->L127-2: Formula: (and (= v_~b0_val~0_3 v_~b0_val_t~0_3) (> v_~b0_val_t~0_3 v_~b0_val~0_4) (= v_~b0_ev~0_3 0)) InVars {~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_4} OutVars{~b0_ev~0=v_~b0_ev~0_3, ~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_3} AuxVars[] AssignedVars[~b0_val~0, ~b0_ev~0] 7820#L127-2 [580] L127-2-->L202-1: Formula: (= v_~b0_req_up~0_5 0) InVars {} OutVars{~b0_req_up~0=v_~b0_req_up~0_5} AuxVars[] AssignedVars[~b0_req_up~0] 7855#L202-1 [545] L202-1-->L142: Formula: (= 1 v_~b1_req_up~0_4) InVars {~b1_req_up~0=v_~b1_req_up~0_4} OutVars{~b1_req_up~0=v_~b1_req_up~0_4} AuxVars[] AssignedVars[] 7835#L142 [752] L142-->L142-2: Formula: (and (= v_~b1_ev~0_3 0) (< v_~b1_val~0_4 v_~b1_val_t~0_3) (= v_~b1_val~0_3 v_~b1_val_t~0_3)) InVars {~b1_val_t~0=v_~b1_val_t~0_3, ~b1_val~0=v_~b1_val~0_4} OutVars{~b1_val_t~0=v_~b1_val_t~0_3, ~b1_ev~0=v_~b1_ev~0_3, ~b1_val~0=v_~b1_val~0_3} AuxVars[] AssignedVars[~b1_val~0, ~b1_ev~0] 7828#L142-2 [521] L142-2-->L209: Formula: (= v_~b1_req_up~0_5 0) InVars {} OutVars{~b1_req_up~0=v_~b1_req_up~0_5} AuxVars[] AssignedVars[~b1_req_up~0] 7829#L209 [624] L209-->L157: Formula: (= v_~d0_req_up~0_4 1) InVars {~d0_req_up~0=v_~d0_req_up~0_4} OutVars{~d0_req_up~0=v_~d0_req_up~0_4} AuxVars[] AssignedVars[] 7805#L157 [757] L157-->L157-2: Formula: (and (> v_~d0_val_t~0_3 v_~d0_val~0_4) (= v_~d0_val~0_3 v_~d0_val_t~0_3) (= v_~d0_ev~0_3 0)) InVars {~d0_val~0=v_~d0_val~0_4, ~d0_val_t~0=v_~d0_val_t~0_3} OutVars{~d0_ev~0=v_~d0_ev~0_3, ~d0_val~0=v_~d0_val~0_3, ~d0_val_t~0=v_~d0_val_t~0_3} AuxVars[] AssignedVars[~d0_ev~0, ~d0_val~0] 7795#L157-2 [600] L157-2-->L216: Formula: (= v_~d0_req_up~0_5 0) InVars {} OutVars{~d0_req_up~0=v_~d0_req_up~0_5} AuxVars[] AssignedVars[~d0_req_up~0] 7796#L216 [554] L216-->L172: Formula: (= v_~d1_req_up~0_4 1) InVars {~d1_req_up~0=v_~d1_req_up~0_4} OutVars{~d1_req_up~0=v_~d1_req_up~0_4} AuxVars[] AssignedVars[] 7864#L172 [760] L172-->L172-2: Formula: (and (= v_~d1_val~0_3 v_~d1_val_t~0_3) (= v_~d1_ev~0_3 0) (> v_~d1_val_t~0_3 v_~d1_val~0_4)) InVars {~d1_val_t~0=v_~d1_val_t~0_3, ~d1_val~0=v_~d1_val~0_4} OutVars{~d1_val_t~0=v_~d1_val_t~0_3, ~d1_val~0=v_~d1_val~0_3, ~d1_ev~0=v_~d1_ev~0_3} AuxVars[] AssignedVars[~d1_val~0, ~d1_ev~0] 7858#L172-2 [547] L172-2-->L223: Formula: (= v_~d1_req_up~0_5 0) InVars {} OutVars{~d1_req_up~0=v_~d1_req_up~0_5} AuxVars[] AssignedVars[~d1_req_up~0] 7857#L223 [762] L223-->L230: Formula: (> 1 v_~z_req_up~0_6) InVars {~z_req_up~0=v_~z_req_up~0_6} OutVars{~z_req_up~0=v_~z_req_up~0_6} AuxVars[] AssignedVars[] 7797#L230 [767] L230-->L245-1: Formula: (and (> 1 v_~comp_m1_i~0_4) (= v_~comp_m1_st~0_5 2)) InVars {~comp_m1_i~0=v_~comp_m1_i~0_4} OutVars{~comp_m1_st~0=v_~comp_m1_st~0_5, ~comp_m1_i~0=v_~comp_m1_i~0_4} AuxVars[] AssignedVars[~comp_m1_st~0] 7798#L245-1 [608] L245-1-->L311-1: Formula: (and (= v_~b0_ev~0_5 1) (= v_~b0_ev~0_6 0)) InVars {~b0_ev~0=v_~b0_ev~0_6} OutVars{~b0_ev~0=v_~b0_ev~0_5} AuxVars[] AssignedVars[~b0_ev~0] 7815#L311-1 [628] L311-1-->L316-1: Formula: (and (= 0 v_~b1_ev~0_6) (= v_~b1_ev~0_5 1)) InVars {~b1_ev~0=v_~b1_ev~0_6} OutVars{~b1_ev~0=v_~b1_ev~0_5} AuxVars[] AssignedVars[~b1_ev~0] 7847#L316-1 [654] L316-1-->L321-1: Formula: (and (= v_~d0_ev~0_5 1) (= v_~d0_ev~0_6 0)) InVars {~d0_ev~0=v_~d0_ev~0_6} OutVars{~d0_ev~0=v_~d0_ev~0_5} AuxVars[] AssignedVars[~d0_ev~0] 7808#L321-1 [507] L321-1-->L326-1: Formula: (and (= 0 v_~d1_ev~0_6) (= v_~d1_ev~0_5 1)) InVars {~d1_ev~0=v_~d1_ev~0_6} OutVars{~d1_ev~0=v_~d1_ev~0_5} AuxVars[] AssignedVars[~d1_ev~0] 7809#L326-1 [776] L326-1-->L331-1: Formula: (< 0 v_~z_ev~0_7) InVars {~z_ev~0=v_~z_ev~0_7} OutVars{~z_ev~0=v_~z_ev~0_7} AuxVars[] AssignedVars[] 7867#L331-1 [583] L331-1-->L97: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_1|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 7902#L97 [591] L97-->L119: Formula: (and (= v_~b0_ev~0_11 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4 1)) InVars {~b0_ev~0=v_~b0_ev~0_11} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4, ~b0_ev~0=v_~b0_ev~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 7900#L119 [886] L119-->L380: Formula: (and (= |v_ULTIMATE.start_is_method1_triggered_#res_7| v_ULTIMATE.start_activate_threads_~tmp~1_13) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19 |v_ULTIMATE.start_is_method1_triggered_#res_7|)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_13, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_7|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_7|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 7899#L380 [615] L380-->L380-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_9) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} AuxVars[] AssignedVars[] 7898#L380-2 [618] L380-2-->L344-1: Formula: (and (= v_~b0_ev~0_15 2) (= v_~b0_ev~0_16 1)) InVars {~b0_ev~0=v_~b0_ev~0_16} OutVars{~b0_ev~0=v_~b0_ev~0_15} AuxVars[] AssignedVars[~b0_ev~0] 7843#L344-1 [626] L344-1-->L349-1: Formula: (and (= 1 v_~b1_ev~0_16) (= v_~b1_ev~0_15 2)) InVars {~b1_ev~0=v_~b1_ev~0_16} OutVars{~b1_ev~0=v_~b1_ev~0_15} AuxVars[] AssignedVars[~b1_ev~0] 7844#L349-1 [652] L349-1-->L354-1: Formula: (and (= v_~d0_ev~0_15 2) (= v_~d0_ev~0_16 1)) InVars {~d0_ev~0=v_~d0_ev~0_16} OutVars{~d0_ev~0=v_~d0_ev~0_15} AuxVars[] AssignedVars[~d0_ev~0] 7803#L354-1 [795] L354-1-->L359-1: Formula: (> 1 v_~d1_ev~0_17) InVars {~d1_ev~0=v_~d1_ev~0_17} OutVars{~d1_ev~0=v_~d1_ev~0_17} AuxVars[] AssignedVars[] 7804#L359-1 [797] L359-1-->L422-1: Formula: (> v_~z_ev~0_13 1) InVars {~z_ev~0=v_~z_ev~0_13} OutVars{~z_ev~0=v_~z_ev~0_13} AuxVars[] AssignedVars[] 7865#L422-1 54.07/20.05 [2019-03-28 12:18:52,836 INFO L796 eck$LassoCheckResult]: Loop: 7865#L422-1 [887] L422-1-->L285: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 1) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 8002#L285 [888] L285-->L258: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_13, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res] 7995#L258 [802] L258-->L265: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8 0) (> 0 v_~comp_m1_st~0_9)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_9} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8, ~comp_m1_st~0=v_~comp_m1_st~0_9} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 7991#L265 [889] L265-->L280: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___0~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 7985#L280 [890] L280-->L202-2: Formula: (and (= v_ULTIMATE.start_eval_~tmp___0~0_8 0) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 2)) InVars {ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 7983#L202-2 [800] L202-2-->L202-3: Formula: (> 1 v_~b0_req_up~0_9) InVars {~b0_req_up~0=v_~b0_req_up~0_9} OutVars{~b0_req_up~0=v_~b0_req_up~0_9} AuxVars[] AssignedVars[] 7984#L202-3 [807] L202-3-->L209-1: Formula: (> 1 v_~b1_req_up~0_9) InVars {~b1_req_up~0=v_~b1_req_up~0_9} OutVars{~b1_req_up~0=v_~b1_req_up~0_9} AuxVars[] AssignedVars[] 8122#L209-1 [811] L209-1-->L216-1: Formula: (< v_~d0_req_up~0_9 1) InVars {~d0_req_up~0=v_~d0_req_up~0_9} OutVars{~d0_req_up~0=v_~d0_req_up~0_9} AuxVars[] AssignedVars[] 8116#L216-1 [815] L216-1-->L223-1: Formula: (< v_~d1_req_up~0_9 1) InVars {~d1_req_up~0=v_~d1_req_up~0_9} OutVars{~d1_req_up~0=v_~d1_req_up~0_9} AuxVars[] AssignedVars[] 8111#L223-1 [821] L223-1-->L230-1: Formula: (> 1 v_~z_req_up~0_9) InVars {~z_req_up~0=v_~z_req_up~0_9} OutVars{~z_req_up~0=v_~z_req_up~0_9} AuxVars[] AssignedVars[] 8083#L230-1 [498] L230-1-->L311-2: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 3) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 8104#L311-2 [632] L311-2-->L311-4: Formula: (and (= v_~b0_ev~0_8 1) (= v_~b0_ev~0_9 0)) InVars {~b0_ev~0=v_~b0_ev~0_9} OutVars{~b0_ev~0=v_~b0_ev~0_8} AuxVars[] AssignedVars[~b0_ev~0] 8100#L311-4 [833] L311-4-->L316-3: Formula: (< 0 v_~b1_ev~0_10) InVars {~b1_ev~0=v_~b1_ev~0_10} OutVars{~b1_ev~0=v_~b1_ev~0_10} AuxVars[] AssignedVars[] 8098#L316-3 [838] L316-3-->L321-3: Formula: (< v_~d0_ev~0_10 0) InVars {~d0_ev~0=v_~d0_ev~0_10} OutVars{~d0_ev~0=v_~d0_ev~0_10} AuxVars[] AssignedVars[] 7924#L321-3 [662] L321-3-->L326-3: Formula: (and (= v_~d1_ev~0_8 1) (= 0 v_~d1_ev~0_9)) InVars {~d1_ev~0=v_~d1_ev~0_9} OutVars{~d1_ev~0=v_~d1_ev~0_8} AuxVars[] AssignedVars[~d1_ev~0] 7921#L326-3 [850] L326-3-->L331-3: Formula: (> v_~z_ev~0_10 0) InVars {~z_ev~0=v_~z_ev~0_10} OutVars{~z_ev~0=v_~z_ev~0_10} AuxVars[] AssignedVars[] 7919#L331-3 [570] L331-3-->L97-1: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_4|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_10, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 7920#L97-1 [588] L97-1-->L119-1: Formula: (and (= v_~b0_ev~0_13 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13 1)) InVars {~b0_ev~0=v_~b0_ev~0_13} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13, ~b0_ev~0=v_~b0_ev~0_13} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 7909#L119-1 [891] L119-1-->L380-3: Formula: (and (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20 |v_ULTIMATE.start_is_method1_triggered_#res_8|) (= |v_ULTIMATE.start_is_method1_triggered_#res_8| v_ULTIMATE.start_activate_threads_~tmp~1_14)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_14, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_8|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_8|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 7908#L380-3 [864] L380-3-->L380-5: Formula: (and (= v_~comp_m1_st~0_7 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11, ~comp_m1_st~0=v_~comp_m1_st~0_7} AuxVars[] AssignedVars[~comp_m1_st~0] 7905#L380-5 [869] L380-5-->L344-3: Formula: (> v_~b0_ev~0_20 1) InVars {~b0_ev~0=v_~b0_ev~0_20} OutVars{~b0_ev~0=v_~b0_ev~0_20} AuxVars[] AssignedVars[] 7907#L344-3 [870] L344-3-->L349-3: Formula: (< 1 v_~b1_ev~0_20) InVars {~b1_ev~0=v_~b1_ev~0_20} OutVars{~b1_ev~0=v_~b1_ev~0_20} AuxVars[] AssignedVars[] 8245#L349-3 [656] L349-3-->L354-3: Formula: (and (= v_~d0_ev~0_18 2) (= v_~d0_ev~0_19 1)) InVars {~d0_ev~0=v_~d0_ev~0_19} OutVars{~d0_ev~0=v_~d0_ev~0_18} AuxVars[] AssignedVars[~d0_ev~0] 8241#L354-3 [513] L354-3-->L359-3: Formula: (and (= 1 v_~d1_ev~0_19) (= v_~d1_ev~0_18 2)) InVars {~d1_ev~0=v_~d1_ev~0_19} OutVars{~d1_ev~0=v_~d1_ev~0_18} AuxVars[] AssignedVars[~d1_ev~0] 8239#L359-3 [876] L359-3-->L364-3: Formula: (> v_~z_ev~0_16 1) InVars {~z_ev~0=v_~z_ev~0_16} OutVars{~z_ev~0=v_~z_ev~0_16} AuxVars[] AssignedVars[] 8231#L364-3 [568] L364-3-->L258-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_5, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_2|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_#res] 8225#L258-1 [666] L258-1-->L265-1: Formula: (and (= v_~comp_m1_st~0_10 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9 1)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_10} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9, ~comp_m1_st~0=v_~comp_m1_st~0_10} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 8219#L265-1 [892] L265-1-->L397: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_stop_simulation_~tmp~2_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_4|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_~tmp~2] 8213#L397 [880] L397-->L404: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_4 0) (< 0 v_ULTIMATE.start_stop_simulation_~tmp~2_5)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_4, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 8209#L404 [897] L404-->L422-1: Formula: (and (= 0 v_ULTIMATE.start_start_simulation_~tmp~3_9) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= |v_ULTIMATE.start_stop_simulation_#res_5| v_ULTIMATE.start_start_simulation_~tmp~3_9)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_~tmp~3] 7865#L422-1 54.07/20.05 [2019-03-28 12:18:52,837 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.05 [2019-03-28 12:18:52,837 INFO L82 PathProgramCache]: Analyzing trace with hash -1641070867, now seen corresponding path program 1 times 54.07/20.05 [2019-03-28 12:18:52,837 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.05 [2019-03-28 12:18:52,837 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.05 [2019-03-28 12:18:52,838 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:52,838 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:52,838 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:52,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.05 [2019-03-28 12:18:52,858 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.05 [2019-03-28 12:18:52,858 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.05 [2019-03-28 12:18:52,859 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 54.07/20.05 [2019-03-28 12:18:52,859 INFO L799 eck$LassoCheckResult]: stem already infeasible 54.07/20.05 [2019-03-28 12:18:52,859 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.05 [2019-03-28 12:18:52,859 INFO L82 PathProgramCache]: Analyzing trace with hash -840565064, now seen corresponding path program 3 times 54.07/20.05 [2019-03-28 12:18:52,859 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.05 [2019-03-28 12:18:52,860 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.05 [2019-03-28 12:18:52,860 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:52,860 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:52,861 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:52,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.05 [2019-03-28 12:18:52,873 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.05 [2019-03-28 12:18:52,874 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.05 [2019-03-28 12:18:52,874 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 54.07/20.05 [2019-03-28 12:18:52,874 INFO L811 eck$LassoCheckResult]: loop already infeasible 54.07/20.05 [2019-03-28 12:18:52,874 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 54.07/20.05 [2019-03-28 12:18:52,874 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 54.07/20.05 [2019-03-28 12:18:52,875 INFO L87 Difference]: Start difference. First operand 616 states and 1261 transitions. cyclomatic complexity: 646 Second operand 3 states. 54.07/20.05 [2019-03-28 12:18:53,109 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 54.07/20.05 [2019-03-28 12:18:53,109 INFO L93 Difference]: Finished difference Result 1210 states and 2437 transitions. 54.07/20.05 [2019-03-28 12:18:53,109 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 54.07/20.05 [2019-03-28 12:18:53,110 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1210 states and 2437 transitions. 54.07/20.05 [2019-03-28 12:18:53,117 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1144 54.07/20.05 [2019-03-28 12:18:53,126 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1210 states to 1210 states and 2437 transitions. 54.07/20.05 [2019-03-28 12:18:53,126 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1210 54.07/20.05 [2019-03-28 12:18:53,127 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1210 54.07/20.05 [2019-03-28 12:18:53,127 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1210 states and 2437 transitions. 54.07/20.05 [2019-03-28 12:18:53,130 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 54.07/20.05 [2019-03-28 12:18:53,130 INFO L706 BuchiCegarLoop]: Abstraction has 1210 states and 2437 transitions. 54.07/20.05 [2019-03-28 12:18:53,131 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1210 states and 2437 transitions. 54.07/20.05 [2019-03-28 12:18:53,150 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1210 to 1210. 54.07/20.05 [2019-03-28 12:18:53,150 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1210 states. 54.07/20.05 [2019-03-28 12:18:53,154 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1210 states to 1210 states and 2437 transitions. 54.07/20.05 [2019-03-28 12:18:53,155 INFO L729 BuchiCegarLoop]: Abstraction has 1210 states and 2437 transitions. 54.07/20.05 [2019-03-28 12:18:53,155 INFO L609 BuchiCegarLoop]: Abstraction has 1210 states and 2437 transitions. 54.07/20.05 [2019-03-28 12:18:53,155 INFO L442 BuchiCegarLoop]: ======== Iteration 20============ 54.07/20.05 [2019-03-28 12:18:53,155 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1210 states and 2437 transitions. 54.07/20.05 [2019-03-28 12:18:53,161 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1144 54.07/20.05 [2019-03-28 12:18:53,161 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 54.07/20.05 [2019-03-28 12:18:53,162 INFO L119 BuchiIsEmpty]: Starting construction of run 54.07/20.05 [2019-03-28 12:18:53,163 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.05 [2019-03-28 12:18:53,163 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.05 [2019-03-28 12:18:53,164 INFO L794 eck$LassoCheckResult]: Stem: 9699#ULTIMATE.startENTRY [885] ULTIMATE.startENTRY-->L202: Formula: (and (= v_~d0_ev~0_23 2) (= 0 v_~z_val~0_13) (= 2 v_~b1_ev~0_23) (= v_~d0_val_t~0_9 1) (= v_~b0_val~0_13 0) (= 1 v_~b1_val_t~0_9) (= 1 v_~d1_req_up~0_12) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_9 0) (= 2 v_~d1_ev~0_23) (= v_~b1_val~0_13 0) (= v_~b0_val_t~0_9 1) (= v_~b0_req_up~0_12 1) (= 0 v_~comp_m1_i~0_7) (= v_~d0_req_up~0_12 1) (= v_~comp_m1_st~0_15 0) (= v_~b0_ev~0_23 2) (= 1 v_~d1_val_t~0_9) (= v_~z_req_up~0_12 0) (= v_~z_val_t~0_10 0) (= 0 v_~d1_val~0_13) (= v_~z_ev~0_19 2) (= v_~b1_req_up~0_12 1) (= 0 v_~d0_val~0_13)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_4|, ~b1_val~0=v_~b1_val~0_13, ~b0_val~0=v_~b0_val~0_13, ~d0_req_up~0=v_~d0_req_up~0_12, ~d0_val~0=v_~d0_val~0_13, ~d1_val_t~0=v_~d1_val_t~0_9, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_9, ~d1_ev~0=v_~d1_ev~0_23, ~d1_val~0=v_~d1_val~0_13, ~b0_req_up~0=v_~b0_req_up~0_12, ~z_ev~0=v_~z_ev~0_19, ~b1_val_t~0=v_~b1_val_t~0_9, ~b1_ev~0=v_~b1_ev~0_23, ULTIMATE.start_main_~__retres1~2=v_ULTIMATE.start_main_~__retres1~2_6, ~z_val~0=v_~z_val~0_13, ~d1_req_up~0=v_~d1_req_up~0_12, ~z_val_t~0=v_~z_val_t~0_10, ~b0_val_t~0=v_~b0_val_t~0_9, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~z_req_up~0=v_~z_req_up~0_12, ~b1_req_up~0=v_~b1_req_up~0_12, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~d0_ev~0=v_~d0_ev~0_23, ~b0_ev~0=v_~b0_ev~0_23, ~d0_val_t~0=v_~d0_val_t~0_9, ~comp_m1_st~0=v_~comp_m1_st~0_15, ~comp_m1_i~0=v_~comp_m1_i~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ~b1_val~0, ~b0_val~0, ~d0_req_up~0, ~d0_val~0, ~d1_val_t~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~d1_ev~0, ~d1_val~0, ~b0_req_up~0, ~z_ev~0, ~b1_val_t~0, ~b1_ev~0, ULTIMATE.start_main_~__retres1~2, ~z_val~0, ~d1_req_up~0, ~z_val_t~0, ~b0_val_t~0, ULTIMATE.start_start_simulation_~tmp~3, ~z_req_up~0, ~b1_req_up~0, ULTIMATE.start_main_#res, ~d0_ev~0, ~b0_ev~0, ~d0_val_t~0, ~comp_m1_st~0, ~comp_m1_i~0] 9700#L202 [566] L202-->L127: Formula: (= 1 v_~b0_req_up~0_4) InVars {~b0_req_up~0=v_~b0_req_up~0_4} OutVars{~b0_req_up~0=v_~b0_req_up~0_4} AuxVars[] AssignedVars[] 9654#L127 [748] L127-->L127-2: Formula: (and (= v_~b0_val~0_3 v_~b0_val_t~0_3) (> v_~b0_val_t~0_3 v_~b0_val~0_4) (= v_~b0_ev~0_3 0)) InVars {~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_4} OutVars{~b0_ev~0=v_~b0_ev~0_3, ~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_3} AuxVars[] AssignedVars[~b0_val~0, ~b0_ev~0] 9655#L127-2 [580] L127-2-->L202-1: Formula: (= v_~b0_req_up~0_5 0) InVars {} OutVars{~b0_req_up~0=v_~b0_req_up~0_5} AuxVars[] AssignedVars[~b0_req_up~0] 9695#L202-1 [545] L202-1-->L142: Formula: (= 1 v_~b1_req_up~0_4) InVars {~b1_req_up~0=v_~b1_req_up~0_4} OutVars{~b1_req_up~0=v_~b1_req_up~0_4} AuxVars[] AssignedVars[] 9671#L142 [752] L142-->L142-2: Formula: (and (= v_~b1_ev~0_3 0) (< v_~b1_val~0_4 v_~b1_val_t~0_3) (= v_~b1_val~0_3 v_~b1_val_t~0_3)) InVars {~b1_val_t~0=v_~b1_val_t~0_3, ~b1_val~0=v_~b1_val~0_4} OutVars{~b1_val_t~0=v_~b1_val_t~0_3, ~b1_ev~0=v_~b1_ev~0_3, ~b1_val~0=v_~b1_val~0_3} AuxVars[] AssignedVars[~b1_val~0, ~b1_ev~0] 9663#L142-2 [521] L142-2-->L209: Formula: (= v_~b1_req_up~0_5 0) InVars {} OutVars{~b1_req_up~0=v_~b1_req_up~0_5} AuxVars[] AssignedVars[~b1_req_up~0] 9664#L209 [624] L209-->L157: Formula: (= v_~d0_req_up~0_4 1) InVars {~d0_req_up~0=v_~d0_req_up~0_4} OutVars{~d0_req_up~0=v_~d0_req_up~0_4} AuxVars[] AssignedVars[] 9638#L157 [757] L157-->L157-2: Formula: (and (> v_~d0_val_t~0_3 v_~d0_val~0_4) (= v_~d0_val~0_3 v_~d0_val_t~0_3) (= v_~d0_ev~0_3 0)) InVars {~d0_val~0=v_~d0_val~0_4, ~d0_val_t~0=v_~d0_val_t~0_3} OutVars{~d0_ev~0=v_~d0_ev~0_3, ~d0_val~0=v_~d0_val~0_3, ~d0_val_t~0=v_~d0_val_t~0_3} AuxVars[] AssignedVars[~d0_ev~0, ~d0_val~0] 9628#L157-2 [600] L157-2-->L216: Formula: (= v_~d0_req_up~0_5 0) InVars {} OutVars{~d0_req_up~0=v_~d0_req_up~0_5} AuxVars[] AssignedVars[~d0_req_up~0] 9629#L216 [554] L216-->L172: Formula: (= v_~d1_req_up~0_4 1) InVars {~d1_req_up~0=v_~d1_req_up~0_4} OutVars{~d1_req_up~0=v_~d1_req_up~0_4} AuxVars[] AssignedVars[] 9704#L172 [760] L172-->L172-2: Formula: (and (= v_~d1_val~0_3 v_~d1_val_t~0_3) (= v_~d1_ev~0_3 0) (> v_~d1_val_t~0_3 v_~d1_val~0_4)) InVars {~d1_val_t~0=v_~d1_val_t~0_3, ~d1_val~0=v_~d1_val~0_4} OutVars{~d1_val_t~0=v_~d1_val_t~0_3, ~d1_val~0=v_~d1_val~0_3, ~d1_ev~0=v_~d1_ev~0_3} AuxVars[] AssignedVars[~d1_val~0, ~d1_ev~0] 9698#L172-2 [547] L172-2-->L223: Formula: (= v_~d1_req_up~0_5 0) InVars {} OutVars{~d1_req_up~0=v_~d1_req_up~0_5} AuxVars[] AssignedVars[~d1_req_up~0] 9697#L223 [762] L223-->L230: Formula: (> 1 v_~z_req_up~0_6) InVars {~z_req_up~0=v_~z_req_up~0_6} OutVars{~z_req_up~0=v_~z_req_up~0_6} AuxVars[] AssignedVars[] 9630#L230 [767] L230-->L245-1: Formula: (and (> 1 v_~comp_m1_i~0_4) (= v_~comp_m1_st~0_5 2)) InVars {~comp_m1_i~0=v_~comp_m1_i~0_4} OutVars{~comp_m1_st~0=v_~comp_m1_st~0_5, ~comp_m1_i~0=v_~comp_m1_i~0_4} AuxVars[] AssignedVars[~comp_m1_st~0] 9631#L245-1 [608] L245-1-->L311-1: Formula: (and (= v_~b0_ev~0_5 1) (= v_~b0_ev~0_6 0)) InVars {~b0_ev~0=v_~b0_ev~0_6} OutVars{~b0_ev~0=v_~b0_ev~0_5} AuxVars[] AssignedVars[~b0_ev~0] 9650#L311-1 [628] L311-1-->L316-1: Formula: (and (= 0 v_~b1_ev~0_6) (= v_~b1_ev~0_5 1)) InVars {~b1_ev~0=v_~b1_ev~0_6} OutVars{~b1_ev~0=v_~b1_ev~0_5} AuxVars[] AssignedVars[~b1_ev~0] 9686#L316-1 [654] L316-1-->L321-1: Formula: (and (= v_~d0_ev~0_5 1) (= v_~d0_ev~0_6 0)) InVars {~d0_ev~0=v_~d0_ev~0_6} OutVars{~d0_ev~0=v_~d0_ev~0_5} AuxVars[] AssignedVars[~d0_ev~0] 9641#L321-1 [774] L321-1-->L326-1: Formula: (> 0 v_~d1_ev~0_7) InVars {~d1_ev~0=v_~d1_ev~0_7} OutVars{~d1_ev~0=v_~d1_ev~0_7} AuxVars[] AssignedVars[] 9642#L326-1 [776] L326-1-->L331-1: Formula: (< 0 v_~z_ev~0_7) InVars {~z_ev~0=v_~z_ev~0_7} OutVars{~z_ev~0=v_~z_ev~0_7} AuxVars[] AssignedVars[] 9764#L331-1 [583] L331-1-->L97: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_1|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 9763#L97 [591] L97-->L119: Formula: (and (= v_~b0_ev~0_11 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4 1)) InVars {~b0_ev~0=v_~b0_ev~0_11} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4, ~b0_ev~0=v_~b0_ev~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 9749#L119 [886] L119-->L380: Formula: (and (= |v_ULTIMATE.start_is_method1_triggered_#res_7| v_ULTIMATE.start_activate_threads_~tmp~1_13) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19 |v_ULTIMATE.start_is_method1_triggered_#res_7|)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_13, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_7|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_7|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 9750#L380 [615] L380-->L380-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_9) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} AuxVars[] AssignedVars[] 9745#L380-2 [618] L380-2-->L344-1: Formula: (and (= v_~b0_ev~0_15 2) (= v_~b0_ev~0_16 1)) InVars {~b0_ev~0=v_~b0_ev~0_16} OutVars{~b0_ev~0=v_~b0_ev~0_15} AuxVars[] AssignedVars[~b0_ev~0] 9746#L344-1 [626] L344-1-->L349-1: Formula: (and (= 1 v_~b1_ev~0_16) (= v_~b1_ev~0_15 2)) InVars {~b1_ev~0=v_~b1_ev~0_16} OutVars{~b1_ev~0=v_~b1_ev~0_15} AuxVars[] AssignedVars[~b1_ev~0] 9760#L349-1 [652] L349-1-->L354-1: Formula: (and (= v_~d0_ev~0_15 2) (= v_~d0_ev~0_16 1)) InVars {~d0_ev~0=v_~d0_ev~0_16} OutVars{~d0_ev~0=v_~d0_ev~0_15} AuxVars[] AssignedVars[~d0_ev~0] 9757#L354-1 [794] L354-1-->L359-1: Formula: (< 1 v_~d1_ev~0_17) InVars {~d1_ev~0=v_~d1_ev~0_17} OutVars{~d1_ev~0=v_~d1_ev~0_17} AuxVars[] AssignedVars[] 9637#L359-1 [797] L359-1-->L422-1: Formula: (> v_~z_ev~0_13 1) InVars {~z_ev~0=v_~z_ev~0_13} OutVars{~z_ev~0=v_~z_ev~0_13} AuxVars[] AssignedVars[] 9946#L422-1 54.07/20.05 [2019-03-28 12:18:53,164 INFO L796 eck$LassoCheckResult]: Loop: 9946#L422-1 [887] L422-1-->L285: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 1) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 9942#L285 [888] L285-->L258: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_13, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res] 9941#L258 [802] L258-->L265: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8 0) (> 0 v_~comp_m1_st~0_9)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_9} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8, ~comp_m1_st~0=v_~comp_m1_st~0_9} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 9936#L265 [889] L265-->L280: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___0~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 9930#L280 [890] L280-->L202-2: Formula: (and (= v_ULTIMATE.start_eval_~tmp___0~0_8 0) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 2)) InVars {ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 9926#L202-2 [800] L202-2-->L202-3: Formula: (> 1 v_~b0_req_up~0_9) InVars {~b0_req_up~0=v_~b0_req_up~0_9} OutVars{~b0_req_up~0=v_~b0_req_up~0_9} AuxVars[] AssignedVars[] 9927#L202-3 [807] L202-3-->L209-1: Formula: (> 1 v_~b1_req_up~0_9) InVars {~b1_req_up~0=v_~b1_req_up~0_9} OutVars{~b1_req_up~0=v_~b1_req_up~0_9} AuxVars[] AssignedVars[] 10580#L209-1 [811] L209-1-->L216-1: Formula: (< v_~d0_req_up~0_9 1) InVars {~d0_req_up~0=v_~d0_req_up~0_9} OutVars{~d0_req_up~0=v_~d0_req_up~0_9} AuxVars[] AssignedVars[] 10601#L216-1 [815] L216-1-->L223-1: Formula: (< v_~d1_req_up~0_9 1) InVars {~d1_req_up~0=v_~d1_req_up~0_9} OutVars{~d1_req_up~0=v_~d1_req_up~0_9} AuxVars[] AssignedVars[] 10602#L223-1 [821] L223-1-->L230-1: Formula: (> 1 v_~z_req_up~0_9) InVars {~z_req_up~0=v_~z_req_up~0_9} OutVars{~z_req_up~0=v_~z_req_up~0_9} AuxVars[] AssignedVars[] 10594#L230-1 [498] L230-1-->L311-2: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 3) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 10593#L311-2 [632] L311-2-->L311-4: Formula: (and (= v_~b0_ev~0_8 1) (= v_~b0_ev~0_9 0)) InVars {~b0_ev~0=v_~b0_ev~0_9} OutVars{~b0_ev~0=v_~b0_ev~0_8} AuxVars[] AssignedVars[~b0_ev~0] 10188#L311-4 [833] L311-4-->L316-3: Formula: (< 0 v_~b1_ev~0_10) InVars {~b1_ev~0=v_~b1_ev~0_10} OutVars{~b1_ev~0=v_~b1_ev~0_10} AuxVars[] AssignedVars[] 10204#L316-3 [838] L316-3-->L321-3: Formula: (< v_~d0_ev~0_10 0) InVars {~d0_ev~0=v_~d0_ev~0_10} OutVars{~d0_ev~0=v_~d0_ev~0_10} AuxVars[] AssignedVars[] 10200#L321-3 [845] L321-3-->L326-3: Formula: (< 0 v_~d1_ev~0_10) InVars {~d1_ev~0=v_~d1_ev~0_10} OutVars{~d1_ev~0=v_~d1_ev~0_10} AuxVars[] AssignedVars[] 10194#L326-3 [850] L326-3-->L331-3: Formula: (> v_~z_ev~0_10 0) InVars {~z_ev~0=v_~z_ev~0_10} OutVars{~z_ev~0=v_~z_ev~0_10} AuxVars[] AssignedVars[] 10192#L331-3 [570] L331-3-->L97-1: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_4|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_10, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 10099#L97-1 [588] L97-1-->L119-1: Formula: (and (= v_~b0_ev~0_13 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13 1)) InVars {~b0_ev~0=v_~b0_ev~0_13} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13, ~b0_ev~0=v_~b0_ev~0_13} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 10092#L119-1 [891] L119-1-->L380-3: Formula: (and (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20 |v_ULTIMATE.start_is_method1_triggered_#res_8|) (= |v_ULTIMATE.start_is_method1_triggered_#res_8| v_ULTIMATE.start_activate_threads_~tmp~1_14)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_14, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_8|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_8|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 10090#L380-3 [864] L380-3-->L380-5: Formula: (and (= v_~comp_m1_st~0_7 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11, ~comp_m1_st~0=v_~comp_m1_st~0_7} AuxVars[] AssignedVars[~comp_m1_st~0] 10088#L380-5 [869] L380-5-->L344-3: Formula: (> v_~b0_ev~0_20 1) InVars {~b0_ev~0=v_~b0_ev~0_20} OutVars{~b0_ev~0=v_~b0_ev~0_20} AuxVars[] AssignedVars[] 10071#L344-3 [870] L344-3-->L349-3: Formula: (< 1 v_~b1_ev~0_20) InVars {~b1_ev~0=v_~b1_ev~0_20} OutVars{~b1_ev~0=v_~b1_ev~0_20} AuxVars[] AssignedVars[] 10065#L349-3 [656] L349-3-->L354-3: Formula: (and (= v_~d0_ev~0_18 2) (= v_~d0_ev~0_19 1)) InVars {~d0_ev~0=v_~d0_ev~0_19} OutVars{~d0_ev~0=v_~d0_ev~0_18} AuxVars[] AssignedVars[~d0_ev~0] 9970#L354-3 [513] L354-3-->L359-3: Formula: (and (= 1 v_~d1_ev~0_19) (= v_~d1_ev~0_18 2)) InVars {~d1_ev~0=v_~d1_ev~0_19} OutVars{~d1_ev~0=v_~d1_ev~0_18} AuxVars[] AssignedVars[~d1_ev~0] 9966#L359-3 [876] L359-3-->L364-3: Formula: (> v_~z_ev~0_16 1) InVars {~z_ev~0=v_~z_ev~0_16} OutVars{~z_ev~0=v_~z_ev~0_16} AuxVars[] AssignedVars[] 9960#L364-3 [568] L364-3-->L258-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_5, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_2|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_#res] 9956#L258-1 [666] L258-1-->L265-1: Formula: (and (= v_~comp_m1_st~0_10 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9 1)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_10} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9, ~comp_m1_st~0=v_~comp_m1_st~0_10} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 9952#L265-1 [892] L265-1-->L397: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_stop_simulation_~tmp~2_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_4|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_~tmp~2] 9950#L397 [880] L397-->L404: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_4 0) (< 0 v_ULTIMATE.start_stop_simulation_~tmp~2_5)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_4, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 9948#L404 [897] L404-->L422-1: Formula: (and (= 0 v_ULTIMATE.start_start_simulation_~tmp~3_9) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= |v_ULTIMATE.start_stop_simulation_#res_5| v_ULTIMATE.start_start_simulation_~tmp~3_9)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_~tmp~3] 9946#L422-1 54.07/20.05 [2019-03-28 12:18:53,165 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.05 [2019-03-28 12:18:53,165 INFO L82 PathProgramCache]: Analyzing trace with hash -390746599, now seen corresponding path program 1 times 54.07/20.05 [2019-03-28 12:18:53,165 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.05 [2019-03-28 12:18:53,165 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.05 [2019-03-28 12:18:53,166 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:53,166 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:53,166 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:53,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.05 [2019-03-28 12:18:53,181 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.05 [2019-03-28 12:18:53,182 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.05 [2019-03-28 12:18:53,182 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 54.07/20.05 [2019-03-28 12:18:53,182 INFO L799 eck$LassoCheckResult]: stem already infeasible 54.07/20.05 [2019-03-28 12:18:53,182 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.05 [2019-03-28 12:18:53,183 INFO L82 PathProgramCache]: Analyzing trace with hash 220961057, now seen corresponding path program 1 times 54.07/20.05 [2019-03-28 12:18:53,183 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.05 [2019-03-28 12:18:53,183 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.05 [2019-03-28 12:18:53,184 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:53,184 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:53,184 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.05 [2019-03-28 12:18:53,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.05 [2019-03-28 12:18:53,197 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.05 [2019-03-28 12:18:53,198 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.05 [2019-03-28 12:18:53,198 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 54.07/20.05 [2019-03-28 12:18:53,198 INFO L811 eck$LassoCheckResult]: loop already infeasible 54.07/20.05 [2019-03-28 12:18:53,198 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 54.07/20.05 [2019-03-28 12:18:53,199 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 54.07/20.05 [2019-03-28 12:18:53,199 INFO L87 Difference]: Start difference. First operand 1210 states and 2437 transitions. cyclomatic complexity: 1228 Second operand 3 states. 54.07/20.05 [2019-03-28 12:18:53,323 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 54.07/20.05 [2019-03-28 12:18:53,324 INFO L93 Difference]: Finished difference Result 744 states and 1449 transitions. 54.07/20.05 [2019-03-28 12:18:53,324 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 54.07/20.05 [2019-03-28 12:18:53,324 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 744 states and 1449 transitions. 54.07/20.05 [2019-03-28 12:18:53,329 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 700 54.07/20.05 [2019-03-28 12:18:53,334 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 744 states to 744 states and 1449 transitions. 54.07/20.05 [2019-03-28 12:18:53,334 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 744 54.07/20.05 [2019-03-28 12:18:53,335 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 744 54.07/20.05 [2019-03-28 12:18:53,335 INFO L73 IsDeterministic]: Start isDeterministic. Operand 744 states and 1449 transitions. 54.07/20.05 [2019-03-28 12:18:53,336 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 54.07/20.05 [2019-03-28 12:18:53,336 INFO L706 BuchiCegarLoop]: Abstraction has 744 states and 1449 transitions. 54.07/20.05 [2019-03-28 12:18:53,337 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 744 states and 1449 transitions. 54.07/20.06 [2019-03-28 12:18:53,349 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 744 to 744. 54.07/20.06 [2019-03-28 12:18:53,349 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 744 states. 54.07/20.06 [2019-03-28 12:18:53,351 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 744 states to 744 states and 1449 transitions. 54.07/20.06 [2019-03-28 12:18:53,352 INFO L729 BuchiCegarLoop]: Abstraction has 744 states and 1449 transitions. 54.07/20.06 [2019-03-28 12:18:53,352 INFO L609 BuchiCegarLoop]: Abstraction has 744 states and 1449 transitions. 54.07/20.06 [2019-03-28 12:18:53,352 INFO L442 BuchiCegarLoop]: ======== Iteration 21============ 54.07/20.06 [2019-03-28 12:18:53,352 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 744 states and 1449 transitions. 54.07/20.06 [2019-03-28 12:18:53,355 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 700 54.07/20.06 [2019-03-28 12:18:53,356 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 54.07/20.06 [2019-03-28 12:18:53,356 INFO L119 BuchiIsEmpty]: Starting construction of run 54.07/20.06 [2019-03-28 12:18:53,357 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.06 [2019-03-28 12:18:53,357 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.06 [2019-03-28 12:18:53,357 INFO L794 eck$LassoCheckResult]: Stem: 11654#ULTIMATE.startENTRY [885] ULTIMATE.startENTRY-->L202: Formula: (and (= v_~d0_ev~0_23 2) (= 0 v_~z_val~0_13) (= 2 v_~b1_ev~0_23) (= v_~d0_val_t~0_9 1) (= v_~b0_val~0_13 0) (= 1 v_~b1_val_t~0_9) (= 1 v_~d1_req_up~0_12) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_9 0) (= 2 v_~d1_ev~0_23) (= v_~b1_val~0_13 0) (= v_~b0_val_t~0_9 1) (= v_~b0_req_up~0_12 1) (= 0 v_~comp_m1_i~0_7) (= v_~d0_req_up~0_12 1) (= v_~comp_m1_st~0_15 0) (= v_~b0_ev~0_23 2) (= 1 v_~d1_val_t~0_9) (= v_~z_req_up~0_12 0) (= v_~z_val_t~0_10 0) (= 0 v_~d1_val~0_13) (= v_~z_ev~0_19 2) (= v_~b1_req_up~0_12 1) (= 0 v_~d0_val~0_13)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_4|, ~b1_val~0=v_~b1_val~0_13, ~b0_val~0=v_~b0_val~0_13, ~d0_req_up~0=v_~d0_req_up~0_12, ~d0_val~0=v_~d0_val~0_13, ~d1_val_t~0=v_~d1_val_t~0_9, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_9, ~d1_ev~0=v_~d1_ev~0_23, ~d1_val~0=v_~d1_val~0_13, ~b0_req_up~0=v_~b0_req_up~0_12, ~z_ev~0=v_~z_ev~0_19, ~b1_val_t~0=v_~b1_val_t~0_9, ~b1_ev~0=v_~b1_ev~0_23, ULTIMATE.start_main_~__retres1~2=v_ULTIMATE.start_main_~__retres1~2_6, ~z_val~0=v_~z_val~0_13, ~d1_req_up~0=v_~d1_req_up~0_12, ~z_val_t~0=v_~z_val_t~0_10, ~b0_val_t~0=v_~b0_val_t~0_9, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~z_req_up~0=v_~z_req_up~0_12, ~b1_req_up~0=v_~b1_req_up~0_12, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~d0_ev~0=v_~d0_ev~0_23, ~b0_ev~0=v_~b0_ev~0_23, ~d0_val_t~0=v_~d0_val_t~0_9, ~comp_m1_st~0=v_~comp_m1_st~0_15, ~comp_m1_i~0=v_~comp_m1_i~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ~b1_val~0, ~b0_val~0, ~d0_req_up~0, ~d0_val~0, ~d1_val_t~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~d1_ev~0, ~d1_val~0, ~b0_req_up~0, ~z_ev~0, ~b1_val_t~0, ~b1_ev~0, ULTIMATE.start_main_~__retres1~2, ~z_val~0, ~d1_req_up~0, ~z_val_t~0, ~b0_val_t~0, ULTIMATE.start_start_simulation_~tmp~3, ~z_req_up~0, ~b1_req_up~0, ULTIMATE.start_main_#res, ~d0_ev~0, ~b0_ev~0, ~d0_val_t~0, ~comp_m1_st~0, ~comp_m1_i~0] 11655#L202 [566] L202-->L127: Formula: (= 1 v_~b0_req_up~0_4) InVars {~b0_req_up~0=v_~b0_req_up~0_4} OutVars{~b0_req_up~0=v_~b0_req_up~0_4} AuxVars[] AssignedVars[] 11614#L127 [748] L127-->L127-2: Formula: (and (= v_~b0_val~0_3 v_~b0_val_t~0_3) (> v_~b0_val_t~0_3 v_~b0_val~0_4) (= v_~b0_ev~0_3 0)) InVars {~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_4} OutVars{~b0_ev~0=v_~b0_ev~0_3, ~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_3} AuxVars[] AssignedVars[~b0_val~0, ~b0_ev~0] 11615#L127-2 [580] L127-2-->L202-1: Formula: (= v_~b0_req_up~0_5 0) InVars {} OutVars{~b0_req_up~0=v_~b0_req_up~0_5} AuxVars[] AssignedVars[~b0_req_up~0] 11650#L202-1 [545] L202-1-->L142: Formula: (= 1 v_~b1_req_up~0_4) InVars {~b1_req_up~0=v_~b1_req_up~0_4} OutVars{~b1_req_up~0=v_~b1_req_up~0_4} AuxVars[] AssignedVars[] 11630#L142 [752] L142-->L142-2: Formula: (and (= v_~b1_ev~0_3 0) (< v_~b1_val~0_4 v_~b1_val_t~0_3) (= v_~b1_val~0_3 v_~b1_val_t~0_3)) InVars {~b1_val_t~0=v_~b1_val_t~0_3, ~b1_val~0=v_~b1_val~0_4} OutVars{~b1_val_t~0=v_~b1_val_t~0_3, ~b1_ev~0=v_~b1_ev~0_3, ~b1_val~0=v_~b1_val~0_3} AuxVars[] AssignedVars[~b1_val~0, ~b1_ev~0] 11625#L142-2 [521] L142-2-->L209: Formula: (= v_~b1_req_up~0_5 0) InVars {} OutVars{~b1_req_up~0=v_~b1_req_up~0_5} AuxVars[] AssignedVars[~b1_req_up~0] 11626#L209 [624] L209-->L157: Formula: (= v_~d0_req_up~0_4 1) InVars {~d0_req_up~0=v_~d0_req_up~0_4} OutVars{~d0_req_up~0=v_~d0_req_up~0_4} AuxVars[] AssignedVars[] 11600#L157 [757] L157-->L157-2: Formula: (and (> v_~d0_val_t~0_3 v_~d0_val~0_4) (= v_~d0_val~0_3 v_~d0_val_t~0_3) (= v_~d0_ev~0_3 0)) InVars {~d0_val~0=v_~d0_val~0_4, ~d0_val_t~0=v_~d0_val_t~0_3} OutVars{~d0_ev~0=v_~d0_ev~0_3, ~d0_val~0=v_~d0_val~0_3, ~d0_val_t~0=v_~d0_val_t~0_3} AuxVars[] AssignedVars[~d0_ev~0, ~d0_val~0] 11589#L157-2 [600] L157-2-->L216: Formula: (= v_~d0_req_up~0_5 0) InVars {} OutVars{~d0_req_up~0=v_~d0_req_up~0_5} AuxVars[] AssignedVars[~d0_req_up~0] 11590#L216 [554] L216-->L172: Formula: (= v_~d1_req_up~0_4 1) InVars {~d1_req_up~0=v_~d1_req_up~0_4} OutVars{~d1_req_up~0=v_~d1_req_up~0_4} AuxVars[] AssignedVars[] 11659#L172 [760] L172-->L172-2: Formula: (and (= v_~d1_val~0_3 v_~d1_val_t~0_3) (= v_~d1_ev~0_3 0) (> v_~d1_val_t~0_3 v_~d1_val~0_4)) InVars {~d1_val_t~0=v_~d1_val_t~0_3, ~d1_val~0=v_~d1_val~0_4} OutVars{~d1_val_t~0=v_~d1_val_t~0_3, ~d1_val~0=v_~d1_val~0_3, ~d1_ev~0=v_~d1_ev~0_3} AuxVars[] AssignedVars[~d1_val~0, ~d1_ev~0] 11653#L172-2 [547] L172-2-->L223: Formula: (= v_~d1_req_up~0_5 0) InVars {} OutVars{~d1_req_up~0=v_~d1_req_up~0_5} AuxVars[] AssignedVars[~d1_req_up~0] 11652#L223 [762] L223-->L230: Formula: (> 1 v_~z_req_up~0_6) InVars {~z_req_up~0=v_~z_req_up~0_6} OutVars{~z_req_up~0=v_~z_req_up~0_6} AuxVars[] AssignedVars[] 11591#L230 [767] L230-->L245-1: Formula: (and (> 1 v_~comp_m1_i~0_4) (= v_~comp_m1_st~0_5 2)) InVars {~comp_m1_i~0=v_~comp_m1_i~0_4} OutVars{~comp_m1_st~0=v_~comp_m1_st~0_5, ~comp_m1_i~0=v_~comp_m1_i~0_4} AuxVars[] AssignedVars[~comp_m1_st~0] 11592#L245-1 [608] L245-1-->L311-1: Formula: (and (= v_~b0_ev~0_5 1) (= v_~b0_ev~0_6 0)) InVars {~b0_ev~0=v_~b0_ev~0_6} OutVars{~b0_ev~0=v_~b0_ev~0_5} AuxVars[] AssignedVars[~b0_ev~0] 11612#L311-1 [628] L311-1-->L316-1: Formula: (and (= 0 v_~b1_ev~0_6) (= v_~b1_ev~0_5 1)) InVars {~b1_ev~0=v_~b1_ev~0_6} OutVars{~b1_ev~0=v_~b1_ev~0_5} AuxVars[] AssignedVars[~b1_ev~0] 11675#L316-1 [654] L316-1-->L321-1: Formula: (and (= v_~d0_ev~0_5 1) (= v_~d0_ev~0_6 0)) InVars {~d0_ev~0=v_~d0_ev~0_6} OutVars{~d0_ev~0=v_~d0_ev~0_5} AuxVars[] AssignedVars[~d0_ev~0] 11604#L321-1 [507] L321-1-->L326-1: Formula: (and (= 0 v_~d1_ev~0_6) (= v_~d1_ev~0_5 1)) InVars {~d1_ev~0=v_~d1_ev~0_6} OutVars{~d1_ev~0=v_~d1_ev~0_5} AuxVars[] AssignedVars[~d1_ev~0] 11605#L326-1 [776] L326-1-->L331-1: Formula: (< 0 v_~z_ev~0_7) InVars {~z_ev~0=v_~z_ev~0_7} OutVars{~z_ev~0=v_~z_ev~0_7} AuxVars[] AssignedVars[] 11663#L331-1 [583] L331-1-->L97: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_1|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 11694#L97 [591] L97-->L119: Formula: (and (= v_~b0_ev~0_11 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4 1)) InVars {~b0_ev~0=v_~b0_ev~0_11} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4, ~b0_ev~0=v_~b0_ev~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 11692#L119 [886] L119-->L380: Formula: (and (= |v_ULTIMATE.start_is_method1_triggered_#res_7| v_ULTIMATE.start_activate_threads_~tmp~1_13) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19 |v_ULTIMATE.start_is_method1_triggered_#res_7|)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_13, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_7|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_7|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 11691#L380 [615] L380-->L380-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_9) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} AuxVars[] AssignedVars[] 11690#L380-2 [618] L380-2-->L344-1: Formula: (and (= v_~b0_ev~0_15 2) (= v_~b0_ev~0_16 1)) InVars {~b0_ev~0=v_~b0_ev~0_16} OutVars{~b0_ev~0=v_~b0_ev~0_15} AuxVars[] AssignedVars[~b0_ev~0] 11639#L344-1 [626] L344-1-->L349-1: Formula: (and (= 1 v_~b1_ev~0_16) (= v_~b1_ev~0_15 2)) InVars {~b1_ev~0=v_~b1_ev~0_16} OutVars{~b1_ev~0=v_~b1_ev~0_15} AuxVars[] AssignedVars[~b1_ev~0] 11640#L349-1 [652] L349-1-->L354-1: Formula: (and (= v_~d0_ev~0_15 2) (= v_~d0_ev~0_16 1)) InVars {~d0_ev~0=v_~d0_ev~0_16} OutVars{~d0_ev~0=v_~d0_ev~0_15} AuxVars[] AssignedVars[~d0_ev~0] 11596#L354-1 [794] L354-1-->L359-1: Formula: (< 1 v_~d1_ev~0_17) InVars {~d1_ev~0=v_~d1_ev~0_17} OutVars{~d1_ev~0=v_~d1_ev~0_17} AuxVars[] AssignedVars[] 11597#L359-1 [797] L359-1-->L422-1: Formula: (> v_~z_ev~0_13 1) InVars {~z_ev~0=v_~z_ev~0_13} OutVars{~z_ev~0=v_~z_ev~0_13} AuxVars[] AssignedVars[] 11824#L422-1 54.07/20.06 [2019-03-28 12:18:53,358 INFO L796 eck$LassoCheckResult]: Loop: 11824#L422-1 [887] L422-1-->L285: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 1) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 11821#L285 [888] L285-->L258: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_13, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res] 11817#L258 [802] L258-->L265: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8 0) (> 0 v_~comp_m1_st~0_9)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_9} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8, ~comp_m1_st~0=v_~comp_m1_st~0_9} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 11815#L265 [889] L265-->L280: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___0~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 11812#L280 [890] L280-->L202-2: Formula: (and (= v_ULTIMATE.start_eval_~tmp___0~0_8 0) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 2)) InVars {ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 11809#L202-2 [800] L202-2-->L202-3: Formula: (> 1 v_~b0_req_up~0_9) InVars {~b0_req_up~0=v_~b0_req_up~0_9} OutVars{~b0_req_up~0=v_~b0_req_up~0_9} AuxVars[] AssignedVars[] 11810#L202-3 [807] L202-3-->L209-1: Formula: (> 1 v_~b1_req_up~0_9) InVars {~b1_req_up~0=v_~b1_req_up~0_9} OutVars{~b1_req_up~0=v_~b1_req_up~0_9} AuxVars[] AssignedVars[] 12146#L209-1 [811] L209-1-->L216-1: Formula: (< v_~d0_req_up~0_9 1) InVars {~d0_req_up~0=v_~d0_req_up~0_9} OutVars{~d0_req_up~0=v_~d0_req_up~0_9} AuxVars[] AssignedVars[] 12142#L216-1 [815] L216-1-->L223-1: Formula: (< v_~d1_req_up~0_9 1) InVars {~d1_req_up~0=v_~d1_req_up~0_9} OutVars{~d1_req_up~0=v_~d1_req_up~0_9} AuxVars[] AssignedVars[] 12143#L223-1 [821] L223-1-->L230-1: Formula: (> 1 v_~z_req_up~0_9) InVars {~z_req_up~0=v_~z_req_up~0_9} OutVars{~z_req_up~0=v_~z_req_up~0_9} AuxVars[] AssignedVars[] 11747#L230-1 [498] L230-1-->L311-2: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 3) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 11748#L311-2 [632] L311-2-->L311-4: Formula: (and (= v_~b0_ev~0_8 1) (= v_~b0_ev~0_9 0)) InVars {~b0_ev~0=v_~b0_ev~0_9} OutVars{~b0_ev~0=v_~b0_ev~0_8} AuxVars[] AssignedVars[~b0_ev~0] 11931#L311-4 [833] L311-4-->L316-3: Formula: (< 0 v_~b1_ev~0_10) InVars {~b1_ev~0=v_~b1_ev~0_10} OutVars{~b1_ev~0=v_~b1_ev~0_10} AuxVars[] AssignedVars[] 11930#L316-3 [838] L316-3-->L321-3: Formula: (< v_~d0_ev~0_10 0) InVars {~d0_ev~0=v_~d0_ev~0_10} OutVars{~d0_ev~0=v_~d0_ev~0_10} AuxVars[] AssignedVars[] 11718#L321-3 [845] L321-3-->L326-3: Formula: (< 0 v_~d1_ev~0_10) InVars {~d1_ev~0=v_~d1_ev~0_10} OutVars{~d1_ev~0=v_~d1_ev~0_10} AuxVars[] AssignedVars[] 11714#L326-3 [850] L326-3-->L331-3: Formula: (> v_~z_ev~0_10 0) InVars {~z_ev~0=v_~z_ev~0_10} OutVars{~z_ev~0=v_~z_ev~0_10} AuxVars[] AssignedVars[] 11715#L331-3 [570] L331-3-->L97-1: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_4|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_10, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 11875#L97-1 [588] L97-1-->L119-1: Formula: (and (= v_~b0_ev~0_13 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13 1)) InVars {~b0_ev~0=v_~b0_ev~0_13} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13, ~b0_ev~0=v_~b0_ev~0_13} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 11870#L119-1 [891] L119-1-->L380-3: Formula: (and (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20 |v_ULTIMATE.start_is_method1_triggered_#res_8|) (= |v_ULTIMATE.start_is_method1_triggered_#res_8| v_ULTIMATE.start_activate_threads_~tmp~1_14)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_14, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_8|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_8|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 11866#L380-3 [864] L380-3-->L380-5: Formula: (and (= v_~comp_m1_st~0_7 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11, ~comp_m1_st~0=v_~comp_m1_st~0_7} AuxVars[] AssignedVars[~comp_m1_st~0] 11863#L380-5 [869] L380-5-->L344-3: Formula: (> v_~b0_ev~0_20 1) InVars {~b0_ev~0=v_~b0_ev~0_20} OutVars{~b0_ev~0=v_~b0_ev~0_20} AuxVars[] AssignedVars[] 11856#L344-3 [870] L344-3-->L349-3: Formula: (< 1 v_~b1_ev~0_20) InVars {~b1_ev~0=v_~b1_ev~0_20} OutVars{~b1_ev~0=v_~b1_ev~0_20} AuxVars[] AssignedVars[] 11854#L349-3 [656] L349-3-->L354-3: Formula: (and (= v_~d0_ev~0_18 2) (= v_~d0_ev~0_19 1)) InVars {~d0_ev~0=v_~d0_ev~0_19} OutVars{~d0_ev~0=v_~d0_ev~0_18} AuxVars[] AssignedVars[~d0_ev~0] 11852#L354-3 [513] L354-3-->L359-3: Formula: (and (= 1 v_~d1_ev~0_19) (= v_~d1_ev~0_18 2)) InVars {~d1_ev~0=v_~d1_ev~0_19} OutVars{~d1_ev~0=v_~d1_ev~0_18} AuxVars[] AssignedVars[~d1_ev~0] 11851#L359-3 [876] L359-3-->L364-3: Formula: (> v_~z_ev~0_16 1) InVars {~z_ev~0=v_~z_ev~0_16} OutVars{~z_ev~0=v_~z_ev~0_16} AuxVars[] AssignedVars[] 11840#L364-3 [568] L364-3-->L258-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_5, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_2|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_#res] 11837#L258-1 [666] L258-1-->L265-1: Formula: (and (= v_~comp_m1_st~0_10 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9 1)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_10} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9, ~comp_m1_st~0=v_~comp_m1_st~0_10} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 11834#L265-1 [892] L265-1-->L397: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_stop_simulation_~tmp~2_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_4|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_~tmp~2] 11829#L397 [880] L397-->L404: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_4 0) (< 0 v_ULTIMATE.start_stop_simulation_~tmp~2_5)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_4, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 11826#L404 [897] L404-->L422-1: Formula: (and (= 0 v_ULTIMATE.start_start_simulation_~tmp~3_9) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= |v_ULTIMATE.start_stop_simulation_#res_5| v_ULTIMATE.start_start_simulation_~tmp~3_9)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_~tmp~3] 11824#L422-1 54.07/20.06 [2019-03-28 12:18:53,358 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.06 [2019-03-28 12:18:53,358 INFO L82 PathProgramCache]: Analyzing trace with hash -1641070898, now seen corresponding path program 1 times 54.07/20.06 [2019-03-28 12:18:53,359 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.06 [2019-03-28 12:18:53,359 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.06 [2019-03-28 12:18:53,359 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:18:53,360 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:18:53,360 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:18:53,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.06 [2019-03-28 12:18:53,376 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.06 [2019-03-28 12:18:53,376 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.06 [2019-03-28 12:18:53,376 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 54.07/20.06 [2019-03-28 12:18:53,376 INFO L799 eck$LassoCheckResult]: stem already infeasible 54.07/20.06 [2019-03-28 12:18:53,377 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.06 [2019-03-28 12:18:53,377 INFO L82 PathProgramCache]: Analyzing trace with hash 220961057, now seen corresponding path program 2 times 54.07/20.06 [2019-03-28 12:18:53,377 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.06 [2019-03-28 12:18:53,377 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.06 [2019-03-28 12:18:53,378 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:18:53,378 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:18:53,378 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:18:53,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.06 [2019-03-28 12:18:53,405 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.06 [2019-03-28 12:18:53,405 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.06 [2019-03-28 12:18:53,405 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 54.07/20.06 [2019-03-28 12:18:53,406 INFO L811 eck$LassoCheckResult]: loop already infeasible 54.07/20.06 [2019-03-28 12:18:53,406 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 54.07/20.06 [2019-03-28 12:18:53,406 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 54.07/20.06 [2019-03-28 12:18:53,406 INFO L87 Difference]: Start difference. First operand 744 states and 1449 transitions. cyclomatic complexity: 706 Second operand 3 states. 54.07/20.06 [2019-03-28 12:18:53,578 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 54.07/20.06 [2019-03-28 12:18:53,578 INFO L93 Difference]: Finished difference Result 904 states and 1735 transitions. 54.07/20.06 [2019-03-28 12:18:53,578 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 54.07/20.06 [2019-03-28 12:18:53,579 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 904 states and 1735 transitions. 54.07/20.06 [2019-03-28 12:18:53,584 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 860 54.07/20.06 [2019-03-28 12:18:53,590 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 904 states to 904 states and 1735 transitions. 54.07/20.06 [2019-03-28 12:18:53,590 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 904 54.07/20.06 [2019-03-28 12:18:53,591 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 904 54.07/20.06 [2019-03-28 12:18:53,591 INFO L73 IsDeterministic]: Start isDeterministic. Operand 904 states and 1735 transitions. 54.07/20.06 [2019-03-28 12:18:53,593 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 54.07/20.06 [2019-03-28 12:18:53,593 INFO L706 BuchiCegarLoop]: Abstraction has 904 states and 1735 transitions. 54.07/20.06 [2019-03-28 12:18:53,594 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 904 states and 1735 transitions. 54.07/20.06 [2019-03-28 12:18:53,607 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 904 to 904. 54.07/20.06 [2019-03-28 12:18:53,608 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 904 states. 54.07/20.06 [2019-03-28 12:18:53,610 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 904 states to 904 states and 1735 transitions. 54.07/20.06 [2019-03-28 12:18:53,611 INFO L729 BuchiCegarLoop]: Abstraction has 904 states and 1735 transitions. 54.07/20.06 [2019-03-28 12:18:53,611 INFO L609 BuchiCegarLoop]: Abstraction has 904 states and 1735 transitions. 54.07/20.06 [2019-03-28 12:18:53,611 INFO L442 BuchiCegarLoop]: ======== Iteration 22============ 54.07/20.06 [2019-03-28 12:18:53,611 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 904 states and 1735 transitions. 54.07/20.06 [2019-03-28 12:18:53,615 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 860 54.07/20.06 [2019-03-28 12:18:53,615 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 54.07/20.06 [2019-03-28 12:18:53,616 INFO L119 BuchiIsEmpty]: Starting construction of run 54.07/20.06 [2019-03-28 12:18:53,617 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.06 [2019-03-28 12:18:53,617 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.06 [2019-03-28 12:18:53,617 INFO L794 eck$LassoCheckResult]: Stem: 13311#ULTIMATE.startENTRY [885] ULTIMATE.startENTRY-->L202: Formula: (and (= v_~d0_ev~0_23 2) (= 0 v_~z_val~0_13) (= 2 v_~b1_ev~0_23) (= v_~d0_val_t~0_9 1) (= v_~b0_val~0_13 0) (= 1 v_~b1_val_t~0_9) (= 1 v_~d1_req_up~0_12) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_9 0) (= 2 v_~d1_ev~0_23) (= v_~b1_val~0_13 0) (= v_~b0_val_t~0_9 1) (= v_~b0_req_up~0_12 1) (= 0 v_~comp_m1_i~0_7) (= v_~d0_req_up~0_12 1) (= v_~comp_m1_st~0_15 0) (= v_~b0_ev~0_23 2) (= 1 v_~d1_val_t~0_9) (= v_~z_req_up~0_12 0) (= v_~z_val_t~0_10 0) (= 0 v_~d1_val~0_13) (= v_~z_ev~0_19 2) (= v_~b1_req_up~0_12 1) (= 0 v_~d0_val~0_13)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_4|, ~b1_val~0=v_~b1_val~0_13, ~b0_val~0=v_~b0_val~0_13, ~d0_req_up~0=v_~d0_req_up~0_12, ~d0_val~0=v_~d0_val~0_13, ~d1_val_t~0=v_~d1_val_t~0_9, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_9, ~d1_ev~0=v_~d1_ev~0_23, ~d1_val~0=v_~d1_val~0_13, ~b0_req_up~0=v_~b0_req_up~0_12, ~z_ev~0=v_~z_ev~0_19, ~b1_val_t~0=v_~b1_val_t~0_9, ~b1_ev~0=v_~b1_ev~0_23, ULTIMATE.start_main_~__retres1~2=v_ULTIMATE.start_main_~__retres1~2_6, ~z_val~0=v_~z_val~0_13, ~d1_req_up~0=v_~d1_req_up~0_12, ~z_val_t~0=v_~z_val_t~0_10, ~b0_val_t~0=v_~b0_val_t~0_9, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~z_req_up~0=v_~z_req_up~0_12, ~b1_req_up~0=v_~b1_req_up~0_12, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~d0_ev~0=v_~d0_ev~0_23, ~b0_ev~0=v_~b0_ev~0_23, ~d0_val_t~0=v_~d0_val_t~0_9, ~comp_m1_st~0=v_~comp_m1_st~0_15, ~comp_m1_i~0=v_~comp_m1_i~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ~b1_val~0, ~b0_val~0, ~d0_req_up~0, ~d0_val~0, ~d1_val_t~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~d1_ev~0, ~d1_val~0, ~b0_req_up~0, ~z_ev~0, ~b1_val_t~0, ~b1_ev~0, ULTIMATE.start_main_~__retres1~2, ~z_val~0, ~d1_req_up~0, ~z_val_t~0, ~b0_val_t~0, ULTIMATE.start_start_simulation_~tmp~3, ~z_req_up~0, ~b1_req_up~0, ULTIMATE.start_main_#res, ~d0_ev~0, ~b0_ev~0, ~d0_val_t~0, ~comp_m1_st~0, ~comp_m1_i~0] 13312#L202 [566] L202-->L127: Formula: (= 1 v_~b0_req_up~0_4) InVars {~b0_req_up~0=v_~b0_req_up~0_4} OutVars{~b0_req_up~0=v_~b0_req_up~0_4} AuxVars[] AssignedVars[] 13270#L127 [748] L127-->L127-2: Formula: (and (= v_~b0_val~0_3 v_~b0_val_t~0_3) (> v_~b0_val_t~0_3 v_~b0_val~0_4) (= v_~b0_ev~0_3 0)) InVars {~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_4} OutVars{~b0_ev~0=v_~b0_ev~0_3, ~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_3} AuxVars[] AssignedVars[~b0_val~0, ~b0_ev~0] 13271#L127-2 [580] L127-2-->L202-1: Formula: (= v_~b0_req_up~0_5 0) InVars {} OutVars{~b0_req_up~0=v_~b0_req_up~0_5} AuxVars[] AssignedVars[~b0_req_up~0] 13307#L202-1 [545] L202-1-->L142: Formula: (= 1 v_~b1_req_up~0_4) InVars {~b1_req_up~0=v_~b1_req_up~0_4} OutVars{~b1_req_up~0=v_~b1_req_up~0_4} AuxVars[] AssignedVars[] 13286#L142 [752] L142-->L142-2: Formula: (and (= v_~b1_ev~0_3 0) (< v_~b1_val~0_4 v_~b1_val_t~0_3) (= v_~b1_val~0_3 v_~b1_val_t~0_3)) InVars {~b1_val_t~0=v_~b1_val_t~0_3, ~b1_val~0=v_~b1_val~0_4} OutVars{~b1_val_t~0=v_~b1_val_t~0_3, ~b1_ev~0=v_~b1_ev~0_3, ~b1_val~0=v_~b1_val~0_3} AuxVars[] AssignedVars[~b1_val~0, ~b1_ev~0] 13279#L142-2 [521] L142-2-->L209: Formula: (= v_~b1_req_up~0_5 0) InVars {} OutVars{~b1_req_up~0=v_~b1_req_up~0_5} AuxVars[] AssignedVars[~b1_req_up~0] 13280#L209 [624] L209-->L157: Formula: (= v_~d0_req_up~0_4 1) InVars {~d0_req_up~0=v_~d0_req_up~0_4} OutVars{~d0_req_up~0=v_~d0_req_up~0_4} AuxVars[] AssignedVars[] 13254#L157 [757] L157-->L157-2: Formula: (and (> v_~d0_val_t~0_3 v_~d0_val~0_4) (= v_~d0_val~0_3 v_~d0_val_t~0_3) (= v_~d0_ev~0_3 0)) InVars {~d0_val~0=v_~d0_val~0_4, ~d0_val_t~0=v_~d0_val_t~0_3} OutVars{~d0_ev~0=v_~d0_ev~0_3, ~d0_val~0=v_~d0_val~0_3, ~d0_val_t~0=v_~d0_val_t~0_3} AuxVars[] AssignedVars[~d0_ev~0, ~d0_val~0] 13244#L157-2 [600] L157-2-->L216: Formula: (= v_~d0_req_up~0_5 0) InVars {} OutVars{~d0_req_up~0=v_~d0_req_up~0_5} AuxVars[] AssignedVars[~d0_req_up~0] 13245#L216 [554] L216-->L172: Formula: (= v_~d1_req_up~0_4 1) InVars {~d1_req_up~0=v_~d1_req_up~0_4} OutVars{~d1_req_up~0=v_~d1_req_up~0_4} AuxVars[] AssignedVars[] 13316#L172 [760] L172-->L172-2: Formula: (and (= v_~d1_val~0_3 v_~d1_val_t~0_3) (= v_~d1_ev~0_3 0) (> v_~d1_val_t~0_3 v_~d1_val~0_4)) InVars {~d1_val_t~0=v_~d1_val_t~0_3, ~d1_val~0=v_~d1_val~0_4} OutVars{~d1_val_t~0=v_~d1_val_t~0_3, ~d1_val~0=v_~d1_val~0_3, ~d1_ev~0=v_~d1_ev~0_3} AuxVars[] AssignedVars[~d1_val~0, ~d1_ev~0] 13310#L172-2 [547] L172-2-->L223: Formula: (= v_~d1_req_up~0_5 0) InVars {} OutVars{~d1_req_up~0=v_~d1_req_up~0_5} AuxVars[] AssignedVars[~d1_req_up~0] 13309#L223 [762] L223-->L230: Formula: (> 1 v_~z_req_up~0_6) InVars {~z_req_up~0=v_~z_req_up~0_6} OutVars{~z_req_up~0=v_~z_req_up~0_6} AuxVars[] AssignedVars[] 13246#L230 [767] L230-->L245-1: Formula: (and (> 1 v_~comp_m1_i~0_4) (= v_~comp_m1_st~0_5 2)) InVars {~comp_m1_i~0=v_~comp_m1_i~0_4} OutVars{~comp_m1_st~0=v_~comp_m1_st~0_5, ~comp_m1_i~0=v_~comp_m1_i~0_4} AuxVars[] AssignedVars[~comp_m1_st~0] 13247#L245-1 [608] L245-1-->L311-1: Formula: (and (= v_~b0_ev~0_5 1) (= v_~b0_ev~0_6 0)) InVars {~b0_ev~0=v_~b0_ev~0_6} OutVars{~b0_ev~0=v_~b0_ev~0_5} AuxVars[] AssignedVars[~b0_ev~0] 13266#L311-1 [628] L311-1-->L316-1: Formula: (and (= 0 v_~b1_ev~0_6) (= v_~b1_ev~0_5 1)) InVars {~b1_ev~0=v_~b1_ev~0_6} OutVars{~b1_ev~0=v_~b1_ev~0_5} AuxVars[] AssignedVars[~b1_ev~0] 13299#L316-1 [654] L316-1-->L321-1: Formula: (and (= v_~d0_ev~0_5 1) (= v_~d0_ev~0_6 0)) InVars {~d0_ev~0=v_~d0_ev~0_6} OutVars{~d0_ev~0=v_~d0_ev~0_5} AuxVars[] AssignedVars[~d0_ev~0] 13257#L321-1 [507] L321-1-->L326-1: Formula: (and (= 0 v_~d1_ev~0_6) (= v_~d1_ev~0_5 1)) InVars {~d1_ev~0=v_~d1_ev~0_6} OutVars{~d1_ev~0=v_~d1_ev~0_5} AuxVars[] AssignedVars[~d1_ev~0] 13258#L326-1 [776] L326-1-->L331-1: Formula: (< 0 v_~z_ev~0_7) InVars {~z_ev~0=v_~z_ev~0_7} OutVars{~z_ev~0=v_~z_ev~0_7} AuxVars[] AssignedVars[] 13322#L331-1 [583] L331-1-->L97: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_1|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 13350#L97 [591] L97-->L119: Formula: (and (= v_~b0_ev~0_11 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4 1)) InVars {~b0_ev~0=v_~b0_ev~0_11} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4, ~b0_ev~0=v_~b0_ev~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 13348#L119 [886] L119-->L380: Formula: (and (= |v_ULTIMATE.start_is_method1_triggered_#res_7| v_ULTIMATE.start_activate_threads_~tmp~1_13) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19 |v_ULTIMATE.start_is_method1_triggered_#res_7|)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_13, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_7|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_7|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 13347#L380 [615] L380-->L380-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_9) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} AuxVars[] AssignedVars[] 13346#L380-2 [618] L380-2-->L344-1: Formula: (and (= v_~b0_ev~0_15 2) (= v_~b0_ev~0_16 1)) InVars {~b0_ev~0=v_~b0_ev~0_16} OutVars{~b0_ev~0=v_~b0_ev~0_15} AuxVars[] AssignedVars[~b0_ev~0] 13295#L344-1 [626] L344-1-->L349-1: Formula: (and (= 1 v_~b1_ev~0_16) (= v_~b1_ev~0_15 2)) InVars {~b1_ev~0=v_~b1_ev~0_16} OutVars{~b1_ev~0=v_~b1_ev~0_15} AuxVars[] AssignedVars[~b1_ev~0] 13296#L349-1 [652] L349-1-->L354-1: Formula: (and (= v_~d0_ev~0_15 2) (= v_~d0_ev~0_16 1)) InVars {~d0_ev~0=v_~d0_ev~0_16} OutVars{~d0_ev~0=v_~d0_ev~0_15} AuxVars[] AssignedVars[~d0_ev~0] 13252#L354-1 [502] L354-1-->L359-1: Formula: (and (= 1 v_~d1_ev~0_16) (= v_~d1_ev~0_15 2)) InVars {~d1_ev~0=v_~d1_ev~0_16} OutVars{~d1_ev~0=v_~d1_ev~0_15} AuxVars[] AssignedVars[~d1_ev~0] 13253#L359-1 [797] L359-1-->L422-1: Formula: (> v_~z_ev~0_13 1) InVars {~z_ev~0=v_~z_ev~0_13} OutVars{~z_ev~0=v_~z_ev~0_13} AuxVars[] AssignedVars[] 13434#L422-1 54.07/20.06 [2019-03-28 12:18:53,618 INFO L796 eck$LassoCheckResult]: Loop: 13434#L422-1 [887] L422-1-->L285: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 1) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 13428#L285 [888] L285-->L258: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_13, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res] 13426#L258 [802] L258-->L265: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8 0) (> 0 v_~comp_m1_st~0_9)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_9} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8, ~comp_m1_st~0=v_~comp_m1_st~0_9} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 13424#L265 [889] L265-->L280: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___0~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 13420#L280 [890] L280-->L202-2: Formula: (and (= v_ULTIMATE.start_eval_~tmp___0~0_8 0) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 2)) InVars {ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 13415#L202-2 [800] L202-2-->L202-3: Formula: (> 1 v_~b0_req_up~0_9) InVars {~b0_req_up~0=v_~b0_req_up~0_9} OutVars{~b0_req_up~0=v_~b0_req_up~0_9} AuxVars[] AssignedVars[] 13410#L202-3 [807] L202-3-->L209-1: Formula: (> 1 v_~b1_req_up~0_9) InVars {~b1_req_up~0=v_~b1_req_up~0_9} OutVars{~b1_req_up~0=v_~b1_req_up~0_9} AuxVars[] AssignedVars[] 13411#L209-1 [811] L209-1-->L216-1: Formula: (< v_~d0_req_up~0_9 1) InVars {~d0_req_up~0=v_~d0_req_up~0_9} OutVars{~d0_req_up~0=v_~d0_req_up~0_9} AuxVars[] AssignedVars[] 13892#L216-1 [815] L216-1-->L223-1: Formula: (< v_~d1_req_up~0_9 1) InVars {~d1_req_up~0=v_~d1_req_up~0_9} OutVars{~d1_req_up~0=v_~d1_req_up~0_9} AuxVars[] AssignedVars[] 13893#L223-1 [821] L223-1-->L230-1: Formula: (> 1 v_~z_req_up~0_9) InVars {~z_req_up~0=v_~z_req_up~0_9} OutVars{~z_req_up~0=v_~z_req_up~0_9} AuxVars[] AssignedVars[] 13767#L230-1 [498] L230-1-->L311-2: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 3) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 13900#L311-2 [632] L311-2-->L311-4: Formula: (and (= v_~b0_ev~0_8 1) (= v_~b0_ev~0_9 0)) InVars {~b0_ev~0=v_~b0_ev~0_9} OutVars{~b0_ev~0=v_~b0_ev~0_8} AuxVars[] AssignedVars[~b0_ev~0] 13896#L311-4 [833] L311-4-->L316-3: Formula: (< 0 v_~b1_ev~0_10) InVars {~b1_ev~0=v_~b1_ev~0_10} OutVars{~b1_ev~0=v_~b1_ev~0_10} AuxVars[] AssignedVars[] 13890#L316-3 [838] L316-3-->L321-3: Formula: (< v_~d0_ev~0_10 0) InVars {~d0_ev~0=v_~d0_ev~0_10} OutVars{~d0_ev~0=v_~d0_ev~0_10} AuxVars[] AssignedVars[] 13885#L321-3 [845] L321-3-->L326-3: Formula: (< 0 v_~d1_ev~0_10) InVars {~d1_ev~0=v_~d1_ev~0_10} OutVars{~d1_ev~0=v_~d1_ev~0_10} AuxVars[] AssignedVars[] 13880#L326-3 [850] L326-3-->L331-3: Formula: (> v_~z_ev~0_10 0) InVars {~z_ev~0=v_~z_ev~0_10} OutVars{~z_ev~0=v_~z_ev~0_10} AuxVars[] AssignedVars[] 13879#L331-3 [570] L331-3-->L97-1: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_4|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_10, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 13598#L97-1 [588] L97-1-->L119-1: Formula: (and (= v_~b0_ev~0_13 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13 1)) InVars {~b0_ev~0=v_~b0_ev~0_13} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13, ~b0_ev~0=v_~b0_ev~0_13} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 13592#L119-1 [891] L119-1-->L380-3: Formula: (and (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20 |v_ULTIMATE.start_is_method1_triggered_#res_8|) (= |v_ULTIMATE.start_is_method1_triggered_#res_8| v_ULTIMATE.start_activate_threads_~tmp~1_14)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_14, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_8|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_8|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 13591#L380-3 [864] L380-3-->L380-5: Formula: (and (= v_~comp_m1_st~0_7 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11, ~comp_m1_st~0=v_~comp_m1_st~0_7} AuxVars[] AssignedVars[~comp_m1_st~0] 13527#L380-5 [869] L380-5-->L344-3: Formula: (> v_~b0_ev~0_20 1) InVars {~b0_ev~0=v_~b0_ev~0_20} OutVars{~b0_ev~0=v_~b0_ev~0_20} AuxVars[] AssignedVars[] 13472#L344-3 [870] L344-3-->L349-3: Formula: (< 1 v_~b1_ev~0_20) InVars {~b1_ev~0=v_~b1_ev~0_20} OutVars{~b1_ev~0=v_~b1_ev~0_20} AuxVars[] AssignedVars[] 13465#L349-3 [656] L349-3-->L354-3: Formula: (and (= v_~d0_ev~0_18 2) (= v_~d0_ev~0_19 1)) InVars {~d0_ev~0=v_~d0_ev~0_19} OutVars{~d0_ev~0=v_~d0_ev~0_18} AuxVars[] AssignedVars[~d0_ev~0] 13461#L354-3 [513] L354-3-->L359-3: Formula: (and (= 1 v_~d1_ev~0_19) (= v_~d1_ev~0_18 2)) InVars {~d1_ev~0=v_~d1_ev~0_19} OutVars{~d1_ev~0=v_~d1_ev~0_18} AuxVars[] AssignedVars[~d1_ev~0] 13456#L359-3 [876] L359-3-->L364-3: Formula: (> v_~z_ev~0_16 1) InVars {~z_ev~0=v_~z_ev~0_16} OutVars{~z_ev~0=v_~z_ev~0_16} AuxVars[] AssignedVars[] 13450#L364-3 [568] L364-3-->L258-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_5, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_2|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_#res] 13445#L258-1 [666] L258-1-->L265-1: Formula: (and (= v_~comp_m1_st~0_10 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9 1)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_10} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9, ~comp_m1_st~0=v_~comp_m1_st~0_10} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 13443#L265-1 [892] L265-1-->L397: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_stop_simulation_~tmp~2_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_4|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_~tmp~2] 13442#L397 [880] L397-->L404: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_4 0) (< 0 v_ULTIMATE.start_stop_simulation_~tmp~2_5)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_4, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 13438#L404 [897] L404-->L422-1: Formula: (and (= 0 v_ULTIMATE.start_start_simulation_~tmp~3_9) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= |v_ULTIMATE.start_stop_simulation_#res_5| v_ULTIMATE.start_start_simulation_~tmp~3_9)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_~tmp~3] 13434#L422-1 54.07/20.06 [2019-03-28 12:18:53,618 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.06 [2019-03-28 12:18:53,618 INFO L82 PathProgramCache]: Analyzing trace with hash -1641079950, now seen corresponding path program 1 times 54.07/20.06 [2019-03-28 12:18:53,619 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.06 [2019-03-28 12:18:53,619 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.06 [2019-03-28 12:18:53,619 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:18:53,620 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:18:53,620 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:18:53,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.06 [2019-03-28 12:18:53,640 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.06 [2019-03-28 12:18:53,640 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.06 [2019-03-28 12:18:53,641 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 54.07/20.06 [2019-03-28 12:18:53,641 INFO L799 eck$LassoCheckResult]: stem already infeasible 54.07/20.06 [2019-03-28 12:18:53,641 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.06 [2019-03-28 12:18:53,641 INFO L82 PathProgramCache]: Analyzing trace with hash 220961057, now seen corresponding path program 3 times 54.07/20.06 [2019-03-28 12:18:53,641 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.06 [2019-03-28 12:18:53,641 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.06 [2019-03-28 12:18:53,642 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:18:53,642 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:18:53,643 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:18:53,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.06 [2019-03-28 12:18:53,655 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.06 [2019-03-28 12:18:53,655 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.06 [2019-03-28 12:18:53,655 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 54.07/20.06 [2019-03-28 12:18:53,656 INFO L811 eck$LassoCheckResult]: loop already infeasible 54.07/20.06 [2019-03-28 12:18:53,656 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. 54.07/20.06 [2019-03-28 12:18:53,656 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 54.07/20.06 [2019-03-28 12:18:53,656 INFO L87 Difference]: Start difference. First operand 904 states and 1735 transitions. cyclomatic complexity: 832 Second operand 4 states. 54.07/20.06 [2019-03-28 12:18:53,984 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 54.07/20.06 [2019-03-28 12:18:53,984 INFO L93 Difference]: Finished difference Result 2192 states and 4187 transitions. 54.07/20.06 [2019-03-28 12:18:53,985 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. 54.07/20.06 [2019-03-28 12:18:53,985 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2192 states and 4187 transitions. 54.07/20.06 [2019-03-28 12:18:53,997 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2148 54.07/20.06 [2019-03-28 12:18:54,011 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2192 states to 2192 states and 4187 transitions. 54.07/20.06 [2019-03-28 12:18:54,011 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2192 54.07/20.06 [2019-03-28 12:18:54,013 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2192 54.07/20.06 [2019-03-28 12:18:54,013 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2192 states and 4187 transitions. 54.07/20.06 [2019-03-28 12:18:54,016 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 54.07/20.06 [2019-03-28 12:18:54,016 INFO L706 BuchiCegarLoop]: Abstraction has 2192 states and 4187 transitions. 54.07/20.06 [2019-03-28 12:18:54,017 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2192 states and 4187 transitions. 54.07/20.06 [2019-03-28 12:18:54,038 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2192 to 920. 54.07/20.06 [2019-03-28 12:18:54,038 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 920 states. 54.07/20.06 [2019-03-28 12:18:54,041 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 920 states to 920 states and 1699 transitions. 54.07/20.06 [2019-03-28 12:18:54,041 INFO L729 BuchiCegarLoop]: Abstraction has 920 states and 1699 transitions. 54.07/20.06 [2019-03-28 12:18:54,042 INFO L609 BuchiCegarLoop]: Abstraction has 920 states and 1699 transitions. 54.07/20.06 [2019-03-28 12:18:54,042 INFO L442 BuchiCegarLoop]: ======== Iteration 23============ 54.07/20.06 [2019-03-28 12:18:54,042 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 920 states and 1699 transitions. 54.07/20.06 [2019-03-28 12:18:54,045 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 876 54.07/20.06 [2019-03-28 12:18:54,045 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 54.07/20.06 [2019-03-28 12:18:54,045 INFO L119 BuchiIsEmpty]: Starting construction of run 54.07/20.06 [2019-03-28 12:18:54,046 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.06 [2019-03-28 12:18:54,047 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.06 [2019-03-28 12:18:54,047 INFO L794 eck$LassoCheckResult]: Stem: 16413#ULTIMATE.startENTRY [885] ULTIMATE.startENTRY-->L202: Formula: (and (= v_~d0_ev~0_23 2) (= 0 v_~z_val~0_13) (= 2 v_~b1_ev~0_23) (= v_~d0_val_t~0_9 1) (= v_~b0_val~0_13 0) (= 1 v_~b1_val_t~0_9) (= 1 v_~d1_req_up~0_12) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_9 0) (= 2 v_~d1_ev~0_23) (= v_~b1_val~0_13 0) (= v_~b0_val_t~0_9 1) (= v_~b0_req_up~0_12 1) (= 0 v_~comp_m1_i~0_7) (= v_~d0_req_up~0_12 1) (= v_~comp_m1_st~0_15 0) (= v_~b0_ev~0_23 2) (= 1 v_~d1_val_t~0_9) (= v_~z_req_up~0_12 0) (= v_~z_val_t~0_10 0) (= 0 v_~d1_val~0_13) (= v_~z_ev~0_19 2) (= v_~b1_req_up~0_12 1) (= 0 v_~d0_val~0_13)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_4|, ~b1_val~0=v_~b1_val~0_13, ~b0_val~0=v_~b0_val~0_13, ~d0_req_up~0=v_~d0_req_up~0_12, ~d0_val~0=v_~d0_val~0_13, ~d1_val_t~0=v_~d1_val_t~0_9, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_9, ~d1_ev~0=v_~d1_ev~0_23, ~d1_val~0=v_~d1_val~0_13, ~b0_req_up~0=v_~b0_req_up~0_12, ~z_ev~0=v_~z_ev~0_19, ~b1_val_t~0=v_~b1_val_t~0_9, ~b1_ev~0=v_~b1_ev~0_23, ULTIMATE.start_main_~__retres1~2=v_ULTIMATE.start_main_~__retres1~2_6, ~z_val~0=v_~z_val~0_13, ~d1_req_up~0=v_~d1_req_up~0_12, ~z_val_t~0=v_~z_val_t~0_10, ~b0_val_t~0=v_~b0_val_t~0_9, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~z_req_up~0=v_~z_req_up~0_12, ~b1_req_up~0=v_~b1_req_up~0_12, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~d0_ev~0=v_~d0_ev~0_23, ~b0_ev~0=v_~b0_ev~0_23, ~d0_val_t~0=v_~d0_val_t~0_9, ~comp_m1_st~0=v_~comp_m1_st~0_15, ~comp_m1_i~0=v_~comp_m1_i~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ~b1_val~0, ~b0_val~0, ~d0_req_up~0, ~d0_val~0, ~d1_val_t~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~d1_ev~0, ~d1_val~0, ~b0_req_up~0, ~z_ev~0, ~b1_val_t~0, ~b1_ev~0, ULTIMATE.start_main_~__retres1~2, ~z_val~0, ~d1_req_up~0, ~z_val_t~0, ~b0_val_t~0, ULTIMATE.start_start_simulation_~tmp~3, ~z_req_up~0, ~b1_req_up~0, ULTIMATE.start_main_#res, ~d0_ev~0, ~b0_ev~0, ~d0_val_t~0, ~comp_m1_st~0, ~comp_m1_i~0] 16414#L202 [566] L202-->L127: Formula: (= 1 v_~b0_req_up~0_4) InVars {~b0_req_up~0=v_~b0_req_up~0_4} OutVars{~b0_req_up~0=v_~b0_req_up~0_4} AuxVars[] AssignedVars[] 16375#L127 [748] L127-->L127-2: Formula: (and (= v_~b0_val~0_3 v_~b0_val_t~0_3) (> v_~b0_val_t~0_3 v_~b0_val~0_4) (= v_~b0_ev~0_3 0)) InVars {~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_4} OutVars{~b0_ev~0=v_~b0_ev~0_3, ~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_3} AuxVars[] AssignedVars[~b0_val~0, ~b0_ev~0] 16376#L127-2 [580] L127-2-->L202-1: Formula: (= v_~b0_req_up~0_5 0) InVars {} OutVars{~b0_req_up~0=v_~b0_req_up~0_5} AuxVars[] AssignedVars[~b0_req_up~0] 16409#L202-1 [545] L202-1-->L142: Formula: (= 1 v_~b1_req_up~0_4) InVars {~b1_req_up~0=v_~b1_req_up~0_4} OutVars{~b1_req_up~0=v_~b1_req_up~0_4} AuxVars[] AssignedVars[] 16391#L142 [752] L142-->L142-2: Formula: (and (= v_~b1_ev~0_3 0) (< v_~b1_val~0_4 v_~b1_val_t~0_3) (= v_~b1_val~0_3 v_~b1_val_t~0_3)) InVars {~b1_val_t~0=v_~b1_val_t~0_3, ~b1_val~0=v_~b1_val~0_4} OutVars{~b1_val_t~0=v_~b1_val_t~0_3, ~b1_ev~0=v_~b1_ev~0_3, ~b1_val~0=v_~b1_val~0_3} AuxVars[] AssignedVars[~b1_val~0, ~b1_ev~0] 16384#L142-2 [521] L142-2-->L209: Formula: (= v_~b1_req_up~0_5 0) InVars {} OutVars{~b1_req_up~0=v_~b1_req_up~0_5} AuxVars[] AssignedVars[~b1_req_up~0] 16385#L209 [624] L209-->L157: Formula: (= v_~d0_req_up~0_4 1) InVars {~d0_req_up~0=v_~d0_req_up~0_4} OutVars{~d0_req_up~0=v_~d0_req_up~0_4} AuxVars[] AssignedVars[] 16359#L157 [757] L157-->L157-2: Formula: (and (> v_~d0_val_t~0_3 v_~d0_val~0_4) (= v_~d0_val~0_3 v_~d0_val_t~0_3) (= v_~d0_ev~0_3 0)) InVars {~d0_val~0=v_~d0_val~0_4, ~d0_val_t~0=v_~d0_val_t~0_3} OutVars{~d0_ev~0=v_~d0_ev~0_3, ~d0_val~0=v_~d0_val~0_3, ~d0_val_t~0=v_~d0_val_t~0_3} AuxVars[] AssignedVars[~d0_ev~0, ~d0_val~0] 16350#L157-2 [600] L157-2-->L216: Formula: (= v_~d0_req_up~0_5 0) InVars {} OutVars{~d0_req_up~0=v_~d0_req_up~0_5} AuxVars[] AssignedVars[~d0_req_up~0] 16351#L216 [554] L216-->L172: Formula: (= v_~d1_req_up~0_4 1) InVars {~d1_req_up~0=v_~d1_req_up~0_4} OutVars{~d1_req_up~0=v_~d1_req_up~0_4} AuxVars[] AssignedVars[] 16418#L172 [760] L172-->L172-2: Formula: (and (= v_~d1_val~0_3 v_~d1_val_t~0_3) (= v_~d1_ev~0_3 0) (> v_~d1_val_t~0_3 v_~d1_val~0_4)) InVars {~d1_val_t~0=v_~d1_val_t~0_3, ~d1_val~0=v_~d1_val~0_4} OutVars{~d1_val_t~0=v_~d1_val_t~0_3, ~d1_val~0=v_~d1_val~0_3, ~d1_ev~0=v_~d1_ev~0_3} AuxVars[] AssignedVars[~d1_val~0, ~d1_ev~0] 16412#L172-2 [547] L172-2-->L223: Formula: (= v_~d1_req_up~0_5 0) InVars {} OutVars{~d1_req_up~0=v_~d1_req_up~0_5} AuxVars[] AssignedVars[~d1_req_up~0] 16411#L223 [762] L223-->L230: Formula: (> 1 v_~z_req_up~0_6) InVars {~z_req_up~0=v_~z_req_up~0_6} OutVars{~z_req_up~0=v_~z_req_up~0_6} AuxVars[] AssignedVars[] 16352#L230 [767] L230-->L245-1: Formula: (and (> 1 v_~comp_m1_i~0_4) (= v_~comp_m1_st~0_5 2)) InVars {~comp_m1_i~0=v_~comp_m1_i~0_4} OutVars{~comp_m1_st~0=v_~comp_m1_st~0_5, ~comp_m1_i~0=v_~comp_m1_i~0_4} AuxVars[] AssignedVars[~comp_m1_st~0] 16353#L245-1 [608] L245-1-->L311-1: Formula: (and (= v_~b0_ev~0_5 1) (= v_~b0_ev~0_6 0)) InVars {~b0_ev~0=v_~b0_ev~0_6} OutVars{~b0_ev~0=v_~b0_ev~0_5} AuxVars[] AssignedVars[~b0_ev~0] 16371#L311-1 [628] L311-1-->L316-1: Formula: (and (= 0 v_~b1_ev~0_6) (= v_~b1_ev~0_5 1)) InVars {~b1_ev~0=v_~b1_ev~0_6} OutVars{~b1_ev~0=v_~b1_ev~0_5} AuxVars[] AssignedVars[~b1_ev~0] 16403#L316-1 [654] L316-1-->L321-1: Formula: (and (= v_~d0_ev~0_5 1) (= v_~d0_ev~0_6 0)) InVars {~d0_ev~0=v_~d0_ev~0_6} OutVars{~d0_ev~0=v_~d0_ev~0_5} AuxVars[] AssignedVars[~d0_ev~0] 16362#L321-1 [507] L321-1-->L326-1: Formula: (and (= 0 v_~d1_ev~0_6) (= v_~d1_ev~0_5 1)) InVars {~d1_ev~0=v_~d1_ev~0_6} OutVars{~d1_ev~0=v_~d1_ev~0_5} AuxVars[] AssignedVars[~d1_ev~0] 16363#L326-1 [776] L326-1-->L331-1: Formula: (< 0 v_~z_ev~0_7) InVars {~z_ev~0=v_~z_ev~0_7} OutVars{~z_ev~0=v_~z_ev~0_7} AuxVars[] AssignedVars[] 16425#L331-1 [583] L331-1-->L97: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_1|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 16461#L97 [591] L97-->L119: Formula: (and (= v_~b0_ev~0_11 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4 1)) InVars {~b0_ev~0=v_~b0_ev~0_11} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4, ~b0_ev~0=v_~b0_ev~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 16459#L119 [886] L119-->L380: Formula: (and (= |v_ULTIMATE.start_is_method1_triggered_#res_7| v_ULTIMATE.start_activate_threads_~tmp~1_13) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19 |v_ULTIMATE.start_is_method1_triggered_#res_7|)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_13, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_7|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_7|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 16458#L380 [785] L380-->L380-2: Formula: (and (= v_~comp_m1_st~0_6 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_8)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8, ~comp_m1_st~0=v_~comp_m1_st~0_6} AuxVars[] AssignedVars[~comp_m1_st~0] 16457#L380-2 [618] L380-2-->L344-1: Formula: (and (= v_~b0_ev~0_15 2) (= v_~b0_ev~0_16 1)) InVars {~b0_ev~0=v_~b0_ev~0_16} OutVars{~b0_ev~0=v_~b0_ev~0_15} AuxVars[] AssignedVars[~b0_ev~0] 16399#L344-1 [626] L344-1-->L349-1: Formula: (and (= 1 v_~b1_ev~0_16) (= v_~b1_ev~0_15 2)) InVars {~b1_ev~0=v_~b1_ev~0_16} OutVars{~b1_ev~0=v_~b1_ev~0_15} AuxVars[] AssignedVars[~b1_ev~0] 16400#L349-1 [652] L349-1-->L354-1: Formula: (and (= v_~d0_ev~0_15 2) (= v_~d0_ev~0_16 1)) InVars {~d0_ev~0=v_~d0_ev~0_16} OutVars{~d0_ev~0=v_~d0_ev~0_15} AuxVars[] AssignedVars[~d0_ev~0] 16357#L354-1 [502] L354-1-->L359-1: Formula: (and (= 1 v_~d1_ev~0_16) (= v_~d1_ev~0_15 2)) InVars {~d1_ev~0=v_~d1_ev~0_16} OutVars{~d1_ev~0=v_~d1_ev~0_15} AuxVars[] AssignedVars[~d1_ev~0] 16358#L359-1 [797] L359-1-->L422-1: Formula: (> v_~z_ev~0_13 1) InVars {~z_ev~0=v_~z_ev~0_13} OutVars{~z_ev~0=v_~z_ev~0_13} AuxVars[] AssignedVars[] 17011#L422-1 54.07/20.06 [2019-03-28 12:18:54,048 INFO L796 eck$LassoCheckResult]: Loop: 17011#L422-1 [887] L422-1-->L285: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 1) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 16899#L285 [888] L285-->L258: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_13, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res] 17006#L258 [802] L258-->L265: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8 0) (> 0 v_~comp_m1_st~0_9)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_9} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8, ~comp_m1_st~0=v_~comp_m1_st~0_9} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 17004#L265 [889] L265-->L280: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___0~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 17002#L280 [890] L280-->L202-2: Formula: (and (= v_ULTIMATE.start_eval_~tmp___0~0_8 0) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 2)) InVars {ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 16404#L202-2 [800] L202-2-->L202-3: Formula: (> 1 v_~b0_req_up~0_9) InVars {~b0_req_up~0=v_~b0_req_up~0_9} OutVars{~b0_req_up~0=v_~b0_req_up~0_9} AuxVars[] AssignedVars[] 16401#L202-3 [807] L202-3-->L209-1: Formula: (> 1 v_~b1_req_up~0_9) InVars {~b1_req_up~0=v_~b1_req_up~0_9} OutVars{~b1_req_up~0=v_~b1_req_up~0_9} AuxVars[] AssignedVars[] 16402#L209-1 [811] L209-1-->L216-1: Formula: (< v_~d0_req_up~0_9 1) InVars {~d0_req_up~0=v_~d0_req_up~0_9} OutVars{~d0_req_up~0=v_~d0_req_up~0_9} AuxVars[] AssignedVars[] 17116#L216-1 [815] L216-1-->L223-1: Formula: (< v_~d1_req_up~0_9 1) InVars {~d1_req_up~0=v_~d1_req_up~0_9} OutVars{~d1_req_up~0=v_~d1_req_up~0_9} AuxVars[] AssignedVars[] 17112#L223-1 [821] L223-1-->L230-1: Formula: (> 1 v_~z_req_up~0_9) InVars {~z_req_up~0=v_~z_req_up~0_9} OutVars{~z_req_up~0=v_~z_req_up~0_9} AuxVars[] AssignedVars[] 16831#L230-1 [498] L230-1-->L311-2: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 3) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 17110#L311-2 [632] L311-2-->L311-4: Formula: (and (= v_~b0_ev~0_8 1) (= v_~b0_ev~0_9 0)) InVars {~b0_ev~0=v_~b0_ev~0_9} OutVars{~b0_ev~0=v_~b0_ev~0_8} AuxVars[] AssignedVars[~b0_ev~0] 17104#L311-4 [833] L311-4-->L316-3: Formula: (< 0 v_~b1_ev~0_10) InVars {~b1_ev~0=v_~b1_ev~0_10} OutVars{~b1_ev~0=v_~b1_ev~0_10} AuxVars[] AssignedVars[] 17102#L316-3 [838] L316-3-->L321-3: Formula: (< v_~d0_ev~0_10 0) InVars {~d0_ev~0=v_~d0_ev~0_10} OutVars{~d0_ev~0=v_~d0_ev~0_10} AuxVars[] AssignedVars[] 17100#L321-3 [845] L321-3-->L326-3: Formula: (< 0 v_~d1_ev~0_10) InVars {~d1_ev~0=v_~d1_ev~0_10} OutVars{~d1_ev~0=v_~d1_ev~0_10} AuxVars[] AssignedVars[] 17098#L326-3 [850] L326-3-->L331-3: Formula: (> v_~z_ev~0_10 0) InVars {~z_ev~0=v_~z_ev~0_10} OutVars{~z_ev~0=v_~z_ev~0_10} AuxVars[] AssignedVars[] 17096#L331-3 [570] L331-3-->L97-1: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_4|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_10, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 17093#L97-1 [588] L97-1-->L119-1: Formula: (and (= v_~b0_ev~0_13 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13 1)) InVars {~b0_ev~0=v_~b0_ev~0_13} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13, ~b0_ev~0=v_~b0_ev~0_13} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 17094#L119-1 [891] L119-1-->L380-3: Formula: (and (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20 |v_ULTIMATE.start_is_method1_triggered_#res_8|) (= |v_ULTIMATE.start_is_method1_triggered_#res_8| v_ULTIMATE.start_activate_threads_~tmp~1_14)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_14, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_8|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_8|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 17217#L380-3 [864] L380-3-->L380-5: Formula: (and (= v_~comp_m1_st~0_7 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11, ~comp_m1_st~0=v_~comp_m1_st~0_7} AuxVars[] AssignedVars[~comp_m1_st~0] 17206#L380-5 [869] L380-5-->L344-3: Formula: (> v_~b0_ev~0_20 1) InVars {~b0_ev~0=v_~b0_ev~0_20} OutVars{~b0_ev~0=v_~b0_ev~0_20} AuxVars[] AssignedVars[] 17083#L344-3 [870] L344-3-->L349-3: Formula: (< 1 v_~b1_ev~0_20) InVars {~b1_ev~0=v_~b1_ev~0_20} OutVars{~b1_ev~0=v_~b1_ev~0_20} AuxVars[] AssignedVars[] 17082#L349-3 [656] L349-3-->L354-3: Formula: (and (= v_~d0_ev~0_18 2) (= v_~d0_ev~0_19 1)) InVars {~d0_ev~0=v_~d0_ev~0_19} OutVars{~d0_ev~0=v_~d0_ev~0_18} AuxVars[] AssignedVars[~d0_ev~0] 17080#L354-3 [513] L354-3-->L359-3: Formula: (and (= 1 v_~d1_ev~0_19) (= v_~d1_ev~0_18 2)) InVars {~d1_ev~0=v_~d1_ev~0_19} OutVars{~d1_ev~0=v_~d1_ev~0_18} AuxVars[] AssignedVars[~d1_ev~0] 17077#L359-3 [876] L359-3-->L364-3: Formula: (> v_~z_ev~0_16 1) InVars {~z_ev~0=v_~z_ev~0_16} OutVars{~z_ev~0=v_~z_ev~0_16} AuxVars[] AssignedVars[] 16634#L364-3 [568] L364-3-->L258-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_5, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_2|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_#res] 17054#L258-1 [666] L258-1-->L265-1: Formula: (and (= v_~comp_m1_st~0_10 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9 1)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_10} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9, ~comp_m1_st~0=v_~comp_m1_st~0_10} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 17042#L265-1 [892] L265-1-->L397: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_stop_simulation_~tmp~2_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_4|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_~tmp~2] 17015#L397 [880] L397-->L404: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_4 0) (< 0 v_ULTIMATE.start_stop_simulation_~tmp~2_5)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_4, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 17013#L404 [897] L404-->L422-1: Formula: (and (= 0 v_ULTIMATE.start_start_simulation_~tmp~3_9) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= |v_ULTIMATE.start_stop_simulation_#res_5| v_ULTIMATE.start_start_simulation_~tmp~3_9)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_~tmp~3] 17011#L422-1 54.07/20.06 [2019-03-28 12:18:54,048 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.06 [2019-03-28 12:18:54,049 INFO L82 PathProgramCache]: Analyzing trace with hash -1069091576, now seen corresponding path program 1 times 54.07/20.06 [2019-03-28 12:18:54,049 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.06 [2019-03-28 12:18:54,049 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.06 [2019-03-28 12:18:54,050 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:18:54,050 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:18:54,050 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:18:54,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 54.07/20.06 [2019-03-28 12:18:54,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 54.07/20.06 [2019-03-28 12:18:54,087 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.06 [2019-03-28 12:18:54,087 INFO L82 PathProgramCache]: Analyzing trace with hash 220961057, now seen corresponding path program 4 times 54.07/20.06 [2019-03-28 12:18:54,087 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.06 [2019-03-28 12:18:54,088 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.06 [2019-03-28 12:18:54,088 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:18:54,089 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:18:54,089 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:18:54,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.06 [2019-03-28 12:18:54,103 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.06 [2019-03-28 12:18:54,103 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.06 [2019-03-28 12:18:54,104 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 54.07/20.06 [2019-03-28 12:18:54,104 INFO L811 eck$LassoCheckResult]: loop already infeasible 54.07/20.06 [2019-03-28 12:18:54,104 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 54.07/20.06 [2019-03-28 12:18:54,104 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 54.07/20.06 [2019-03-28 12:18:54,105 INFO L87 Difference]: Start difference. First operand 920 states and 1699 transitions. cyclomatic complexity: 780 Second operand 3 states. 54.07/20.06 [2019-03-28 12:18:54,308 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 54.07/20.06 [2019-03-28 12:18:54,333 INFO L93 Difference]: Finished difference Result 1063 states and 1936 transitions. 54.07/20.06 [2019-03-28 12:18:54,333 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 54.07/20.06 [2019-03-28 12:18:54,334 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1063 states and 1936 transitions. 54.07/20.06 [2019-03-28 12:18:54,338 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1020 54.07/20.06 [2019-03-28 12:18:54,346 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1063 states to 1063 states and 1936 transitions. 54.07/20.06 [2019-03-28 12:18:54,346 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1063 54.07/20.06 [2019-03-28 12:18:54,347 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1063 54.07/20.06 [2019-03-28 12:18:54,347 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1063 states and 1936 transitions. 54.07/20.06 [2019-03-28 12:18:54,349 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 54.07/20.06 [2019-03-28 12:18:54,349 INFO L706 BuchiCegarLoop]: Abstraction has 1063 states and 1936 transitions. 54.07/20.06 [2019-03-28 12:18:54,350 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1063 states and 1936 transitions. 54.07/20.06 [2019-03-28 12:18:54,368 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1063 to 1063. 54.07/20.06 [2019-03-28 12:18:54,368 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1063 states. 54.07/20.06 [2019-03-28 12:18:54,372 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1063 states to 1063 states and 1936 transitions. 54.07/20.06 [2019-03-28 12:18:54,372 INFO L729 BuchiCegarLoop]: Abstraction has 1063 states and 1936 transitions. 54.07/20.06 [2019-03-28 12:18:54,372 INFO L609 BuchiCegarLoop]: Abstraction has 1063 states and 1936 transitions. 54.07/20.06 [2019-03-28 12:18:54,372 INFO L442 BuchiCegarLoop]: ======== Iteration 24============ 54.07/20.06 [2019-03-28 12:18:54,372 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1063 states and 1936 transitions. 54.07/20.06 [2019-03-28 12:18:54,376 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1020 54.07/20.06 [2019-03-28 12:18:54,376 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 54.07/20.06 [2019-03-28 12:18:54,376 INFO L119 BuchiIsEmpty]: Starting construction of run 54.07/20.06 [2019-03-28 12:18:54,377 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.06 [2019-03-28 12:18:54,377 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.06 [2019-03-28 12:18:54,378 INFO L794 eck$LassoCheckResult]: Stem: 18408#ULTIMATE.startENTRY [885] ULTIMATE.startENTRY-->L202: Formula: (and (= v_~d0_ev~0_23 2) (= 0 v_~z_val~0_13) (= 2 v_~b1_ev~0_23) (= v_~d0_val_t~0_9 1) (= v_~b0_val~0_13 0) (= 1 v_~b1_val_t~0_9) (= 1 v_~d1_req_up~0_12) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_9 0) (= 2 v_~d1_ev~0_23) (= v_~b1_val~0_13 0) (= v_~b0_val_t~0_9 1) (= v_~b0_req_up~0_12 1) (= 0 v_~comp_m1_i~0_7) (= v_~d0_req_up~0_12 1) (= v_~comp_m1_st~0_15 0) (= v_~b0_ev~0_23 2) (= 1 v_~d1_val_t~0_9) (= v_~z_req_up~0_12 0) (= v_~z_val_t~0_10 0) (= 0 v_~d1_val~0_13) (= v_~z_ev~0_19 2) (= v_~b1_req_up~0_12 1) (= 0 v_~d0_val~0_13)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_4|, ~b1_val~0=v_~b1_val~0_13, ~b0_val~0=v_~b0_val~0_13, ~d0_req_up~0=v_~d0_req_up~0_12, ~d0_val~0=v_~d0_val~0_13, ~d1_val_t~0=v_~d1_val_t~0_9, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_9, ~d1_ev~0=v_~d1_ev~0_23, ~d1_val~0=v_~d1_val~0_13, ~b0_req_up~0=v_~b0_req_up~0_12, ~z_ev~0=v_~z_ev~0_19, ~b1_val_t~0=v_~b1_val_t~0_9, ~b1_ev~0=v_~b1_ev~0_23, ULTIMATE.start_main_~__retres1~2=v_ULTIMATE.start_main_~__retres1~2_6, ~z_val~0=v_~z_val~0_13, ~d1_req_up~0=v_~d1_req_up~0_12, ~z_val_t~0=v_~z_val_t~0_10, ~b0_val_t~0=v_~b0_val_t~0_9, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~z_req_up~0=v_~z_req_up~0_12, ~b1_req_up~0=v_~b1_req_up~0_12, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~d0_ev~0=v_~d0_ev~0_23, ~b0_ev~0=v_~b0_ev~0_23, ~d0_val_t~0=v_~d0_val_t~0_9, ~comp_m1_st~0=v_~comp_m1_st~0_15, ~comp_m1_i~0=v_~comp_m1_i~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ~b1_val~0, ~b0_val~0, ~d0_req_up~0, ~d0_val~0, ~d1_val_t~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~d1_ev~0, ~d1_val~0, ~b0_req_up~0, ~z_ev~0, ~b1_val_t~0, ~b1_ev~0, ULTIMATE.start_main_~__retres1~2, ~z_val~0, ~d1_req_up~0, ~z_val_t~0, ~b0_val_t~0, ULTIMATE.start_start_simulation_~tmp~3, ~z_req_up~0, ~b1_req_up~0, ULTIMATE.start_main_#res, ~d0_ev~0, ~b0_ev~0, ~d0_val_t~0, ~comp_m1_st~0, ~comp_m1_i~0] 18409#L202 [566] L202-->L127: Formula: (= 1 v_~b0_req_up~0_4) InVars {~b0_req_up~0=v_~b0_req_up~0_4} OutVars{~b0_req_up~0=v_~b0_req_up~0_4} AuxVars[] AssignedVars[] 18365#L127 [748] L127-->L127-2: Formula: (and (= v_~b0_val~0_3 v_~b0_val_t~0_3) (> v_~b0_val_t~0_3 v_~b0_val~0_4) (= v_~b0_ev~0_3 0)) InVars {~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_4} OutVars{~b0_ev~0=v_~b0_ev~0_3, ~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_3} AuxVars[] AssignedVars[~b0_val~0, ~b0_ev~0] 18366#L127-2 [580] L127-2-->L202-1: Formula: (= v_~b0_req_up~0_5 0) InVars {} OutVars{~b0_req_up~0=v_~b0_req_up~0_5} AuxVars[] AssignedVars[~b0_req_up~0] 18404#L202-1 [545] L202-1-->L142: Formula: (= 1 v_~b1_req_up~0_4) InVars {~b1_req_up~0=v_~b1_req_up~0_4} OutVars{~b1_req_up~0=v_~b1_req_up~0_4} AuxVars[] AssignedVars[] 18381#L142 [752] L142-->L142-2: Formula: (and (= v_~b1_ev~0_3 0) (< v_~b1_val~0_4 v_~b1_val_t~0_3) (= v_~b1_val~0_3 v_~b1_val_t~0_3)) InVars {~b1_val_t~0=v_~b1_val_t~0_3, ~b1_val~0=v_~b1_val~0_4} OutVars{~b1_val_t~0=v_~b1_val_t~0_3, ~b1_ev~0=v_~b1_ev~0_3, ~b1_val~0=v_~b1_val~0_3} AuxVars[] AssignedVars[~b1_val~0, ~b1_ev~0] 18374#L142-2 [521] L142-2-->L209: Formula: (= v_~b1_req_up~0_5 0) InVars {} OutVars{~b1_req_up~0=v_~b1_req_up~0_5} AuxVars[] AssignedVars[~b1_req_up~0] 18375#L209 [624] L209-->L157: Formula: (= v_~d0_req_up~0_4 1) InVars {~d0_req_up~0=v_~d0_req_up~0_4} OutVars{~d0_req_up~0=v_~d0_req_up~0_4} AuxVars[] AssignedVars[] 18349#L157 [757] L157-->L157-2: Formula: (and (> v_~d0_val_t~0_3 v_~d0_val~0_4) (= v_~d0_val~0_3 v_~d0_val_t~0_3) (= v_~d0_ev~0_3 0)) InVars {~d0_val~0=v_~d0_val~0_4, ~d0_val_t~0=v_~d0_val_t~0_3} OutVars{~d0_ev~0=v_~d0_ev~0_3, ~d0_val~0=v_~d0_val~0_3, ~d0_val_t~0=v_~d0_val_t~0_3} AuxVars[] AssignedVars[~d0_ev~0, ~d0_val~0] 18339#L157-2 [600] L157-2-->L216: Formula: (= v_~d0_req_up~0_5 0) InVars {} OutVars{~d0_req_up~0=v_~d0_req_up~0_5} AuxVars[] AssignedVars[~d0_req_up~0] 18340#L216 [554] L216-->L172: Formula: (= v_~d1_req_up~0_4 1) InVars {~d1_req_up~0=v_~d1_req_up~0_4} OutVars{~d1_req_up~0=v_~d1_req_up~0_4} AuxVars[] AssignedVars[] 18413#L172 [760] L172-->L172-2: Formula: (and (= v_~d1_val~0_3 v_~d1_val_t~0_3) (= v_~d1_ev~0_3 0) (> v_~d1_val_t~0_3 v_~d1_val~0_4)) InVars {~d1_val_t~0=v_~d1_val_t~0_3, ~d1_val~0=v_~d1_val~0_4} OutVars{~d1_val_t~0=v_~d1_val_t~0_3, ~d1_val~0=v_~d1_val~0_3, ~d1_ev~0=v_~d1_ev~0_3} AuxVars[] AssignedVars[~d1_val~0, ~d1_ev~0] 18407#L172-2 [547] L172-2-->L223: Formula: (= v_~d1_req_up~0_5 0) InVars {} OutVars{~d1_req_up~0=v_~d1_req_up~0_5} AuxVars[] AssignedVars[~d1_req_up~0] 18406#L223 [762] L223-->L230: Formula: (> 1 v_~z_req_up~0_6) InVars {~z_req_up~0=v_~z_req_up~0_6} OutVars{~z_req_up~0=v_~z_req_up~0_6} AuxVars[] AssignedVars[] 18341#L230 [767] L230-->L245-1: Formula: (and (> 1 v_~comp_m1_i~0_4) (= v_~comp_m1_st~0_5 2)) InVars {~comp_m1_i~0=v_~comp_m1_i~0_4} OutVars{~comp_m1_st~0=v_~comp_m1_st~0_5, ~comp_m1_i~0=v_~comp_m1_i~0_4} AuxVars[] AssignedVars[~comp_m1_st~0] 18342#L245-1 [608] L245-1-->L311-1: Formula: (and (= v_~b0_ev~0_5 1) (= v_~b0_ev~0_6 0)) InVars {~b0_ev~0=v_~b0_ev~0_6} OutVars{~b0_ev~0=v_~b0_ev~0_5} AuxVars[] AssignedVars[~b0_ev~0] 18361#L311-1 [628] L311-1-->L316-1: Formula: (and (= 0 v_~b1_ev~0_6) (= v_~b1_ev~0_5 1)) InVars {~b1_ev~0=v_~b1_ev~0_6} OutVars{~b1_ev~0=v_~b1_ev~0_5} AuxVars[] AssignedVars[~b1_ev~0] 18430#L316-1 [654] L316-1-->L321-1: Formula: (and (= v_~d0_ev~0_5 1) (= v_~d0_ev~0_6 0)) InVars {~d0_ev~0=v_~d0_ev~0_6} OutVars{~d0_ev~0=v_~d0_ev~0_5} AuxVars[] AssignedVars[~d0_ev~0] 18352#L321-1 [507] L321-1-->L326-1: Formula: (and (= 0 v_~d1_ev~0_6) (= v_~d1_ev~0_5 1)) InVars {~d1_ev~0=v_~d1_ev~0_6} OutVars{~d1_ev~0=v_~d1_ev~0_5} AuxVars[] AssignedVars[~d1_ev~0] 18353#L326-1 [776] L326-1-->L331-1: Formula: (< 0 v_~z_ev~0_7) InVars {~z_ev~0=v_~z_ev~0_7} OutVars{~z_ev~0=v_~z_ev~0_7} AuxVars[] AssignedVars[] 18419#L331-1 [583] L331-1-->L97: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_1|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 18449#L97 [591] L97-->L119: Formula: (and (= v_~b0_ev~0_11 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4 1)) InVars {~b0_ev~0=v_~b0_ev~0_11} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4, ~b0_ev~0=v_~b0_ev~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 18448#L119 [886] L119-->L380: Formula: (and (= |v_ULTIMATE.start_is_method1_triggered_#res_7| v_ULTIMATE.start_activate_threads_~tmp~1_13) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19 |v_ULTIMATE.start_is_method1_triggered_#res_7|)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_13, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_7|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_7|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 18447#L380 [785] L380-->L380-2: Formula: (and (= v_~comp_m1_st~0_6 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_8)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8, ~comp_m1_st~0=v_~comp_m1_st~0_6} AuxVars[] AssignedVars[~comp_m1_st~0] 18446#L380-2 [789] L380-2-->L344-1: Formula: (< v_~b0_ev~0_17 1) InVars {~b0_ev~0=v_~b0_ev~0_17} OutVars{~b0_ev~0=v_~b0_ev~0_17} AuxVars[] AssignedVars[] 18382#L344-1 [626] L344-1-->L349-1: Formula: (and (= 1 v_~b1_ev~0_16) (= v_~b1_ev~0_15 2)) InVars {~b1_ev~0=v_~b1_ev~0_16} OutVars{~b1_ev~0=v_~b1_ev~0_15} AuxVars[] AssignedVars[~b1_ev~0] 18735#L349-1 [652] L349-1-->L354-1: Formula: (and (= v_~d0_ev~0_15 2) (= v_~d0_ev~0_16 1)) InVars {~d0_ev~0=v_~d0_ev~0_16} OutVars{~d0_ev~0=v_~d0_ev~0_15} AuxVars[] AssignedVars[~d0_ev~0] 18734#L354-1 [502] L354-1-->L359-1: Formula: (and (= 1 v_~d1_ev~0_16) (= v_~d1_ev~0_15 2)) InVars {~d1_ev~0=v_~d1_ev~0_16} OutVars{~d1_ev~0=v_~d1_ev~0_15} AuxVars[] AssignedVars[~d1_ev~0] 18731#L359-1 [797] L359-1-->L422-1: Formula: (> v_~z_ev~0_13 1) InVars {~z_ev~0=v_~z_ev~0_13} OutVars{~z_ev~0=v_~z_ev~0_13} AuxVars[] AssignedVars[] 18727#L422-1 54.07/20.06 [2019-03-28 12:18:54,379 INFO L796 eck$LassoCheckResult]: Loop: 18727#L422-1 [887] L422-1-->L285: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 1) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 18715#L285 [888] L285-->L258: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_13, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res] 18724#L258 [802] L258-->L265: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8 0) (> 0 v_~comp_m1_st~0_9)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_9} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8, ~comp_m1_st~0=v_~comp_m1_st~0_9} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 18722#L265 [889] L265-->L280: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___0~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 18720#L280 [890] L280-->L202-2: Formula: (and (= v_ULTIMATE.start_eval_~tmp___0~0_8 0) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 2)) InVars {ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 18398#L202-2 [800] L202-2-->L202-3: Formula: (> 1 v_~b0_req_up~0_9) InVars {~b0_req_up~0=v_~b0_req_up~0_9} OutVars{~b0_req_up~0=v_~b0_req_up~0_9} AuxVars[] AssignedVars[] 18394#L202-3 [807] L202-3-->L209-1: Formula: (> 1 v_~b1_req_up~0_9) InVars {~b1_req_up~0=v_~b1_req_up~0_9} OutVars{~b1_req_up~0=v_~b1_req_up~0_9} AuxVars[] AssignedVars[] 18395#L209-1 [811] L209-1-->L216-1: Formula: (< v_~d0_req_up~0_9 1) InVars {~d0_req_up~0=v_~d0_req_up~0_9} OutVars{~d0_req_up~0=v_~d0_req_up~0_9} AuxVars[] AssignedVars[] 19133#L216-1 [815] L216-1-->L223-1: Formula: (< v_~d1_req_up~0_9 1) InVars {~d1_req_up~0=v_~d1_req_up~0_9} OutVars{~d1_req_up~0=v_~d1_req_up~0_9} AuxVars[] AssignedVars[] 19134#L223-1 [821] L223-1-->L230-1: Formula: (> 1 v_~z_req_up~0_9) InVars {~z_req_up~0=v_~z_req_up~0_9} OutVars{~z_req_up~0=v_~z_req_up~0_9} AuxVars[] AssignedVars[] 18970#L230-1 [498] L230-1-->L311-2: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 3) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 19288#L311-2 [632] L311-2-->L311-4: Formula: (and (= v_~b0_ev~0_8 1) (= v_~b0_ev~0_9 0)) InVars {~b0_ev~0=v_~b0_ev~0_9} OutVars{~b0_ev~0=v_~b0_ev~0_8} AuxVars[] AssignedVars[~b0_ev~0] 19251#L311-4 [833] L311-4-->L316-3: Formula: (< 0 v_~b1_ev~0_10) InVars {~b1_ev~0=v_~b1_ev~0_10} OutVars{~b1_ev~0=v_~b1_ev~0_10} AuxVars[] AssignedVars[] 19332#L316-3 [838] L316-3-->L321-3: Formula: (< v_~d0_ev~0_10 0) InVars {~d0_ev~0=v_~d0_ev~0_10} OutVars{~d0_ev~0=v_~d0_ev~0_10} AuxVars[] AssignedVars[] 19330#L321-3 [845] L321-3-->L326-3: Formula: (< 0 v_~d1_ev~0_10) InVars {~d1_ev~0=v_~d1_ev~0_10} OutVars{~d1_ev~0=v_~d1_ev~0_10} AuxVars[] AssignedVars[] 19328#L326-3 [850] L326-3-->L331-3: Formula: (> v_~z_ev~0_10 0) InVars {~z_ev~0=v_~z_ev~0_10} OutVars{~z_ev~0=v_~z_ev~0_10} AuxVars[] AssignedVars[] 19324#L331-3 [570] L331-3-->L97-1: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_4|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_10, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 19159#L97-1 [588] L97-1-->L119-1: Formula: (and (= v_~b0_ev~0_13 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13 1)) InVars {~b0_ev~0=v_~b0_ev~0_13} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13, ~b0_ev~0=v_~b0_ev~0_13} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 19157#L119-1 [891] L119-1-->L380-3: Formula: (and (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20 |v_ULTIMATE.start_is_method1_triggered_#res_8|) (= |v_ULTIMATE.start_is_method1_triggered_#res_8| v_ULTIMATE.start_activate_threads_~tmp~1_14)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_14, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_8|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_8|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 19155#L380-3 [864] L380-3-->L380-5: Formula: (and (= v_~comp_m1_st~0_7 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11, ~comp_m1_st~0=v_~comp_m1_st~0_7} AuxVars[] AssignedVars[~comp_m1_st~0] 19153#L380-5 [868] L380-5-->L344-3: Formula: (< v_~b0_ev~0_20 1) InVars {~b0_ev~0=v_~b0_ev~0_20} OutVars{~b0_ev~0=v_~b0_ev~0_20} AuxVars[] AssignedVars[] 18797#L344-3 [870] L344-3-->L349-3: Formula: (< 1 v_~b1_ev~0_20) InVars {~b1_ev~0=v_~b1_ev~0_20} OutVars{~b1_ev~0=v_~b1_ev~0_20} AuxVars[] AssignedVars[] 18794#L349-3 [656] L349-3-->L354-3: Formula: (and (= v_~d0_ev~0_18 2) (= v_~d0_ev~0_19 1)) InVars {~d0_ev~0=v_~d0_ev~0_19} OutVars{~d0_ev~0=v_~d0_ev~0_18} AuxVars[] AssignedVars[~d0_ev~0] 18791#L354-3 [513] L354-3-->L359-3: Formula: (and (= 1 v_~d1_ev~0_19) (= v_~d1_ev~0_18 2)) InVars {~d1_ev~0=v_~d1_ev~0_19} OutVars{~d1_ev~0=v_~d1_ev~0_18} AuxVars[] AssignedVars[~d1_ev~0] 18788#L359-3 [876] L359-3-->L364-3: Formula: (> v_~z_ev~0_16 1) InVars {~z_ev~0=v_~z_ev~0_16} OutVars{~z_ev~0=v_~z_ev~0_16} AuxVars[] AssignedVars[] 18782#L364-3 [568] L364-3-->L258-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_5, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_2|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_#res] 18780#L258-1 [666] L258-1-->L265-1: Formula: (and (= v_~comp_m1_st~0_10 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9 1)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_10} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9, ~comp_m1_st~0=v_~comp_m1_st~0_10} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 18776#L265-1 [892] L265-1-->L397: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_stop_simulation_~tmp~2_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_4|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_~tmp~2] 18774#L397 [880] L397-->L404: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_4 0) (< 0 v_ULTIMATE.start_stop_simulation_~tmp~2_5)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_4, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 18730#L404 [897] L404-->L422-1: Formula: (and (= 0 v_ULTIMATE.start_start_simulation_~tmp~3_9) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= |v_ULTIMATE.start_stop_simulation_#res_5| v_ULTIMATE.start_start_simulation_~tmp~3_9)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_~tmp~3] 18727#L422-1 54.07/20.06 [2019-03-28 12:18:54,379 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.06 [2019-03-28 12:18:54,379 INFO L82 PathProgramCache]: Analyzing trace with hash -911169485, now seen corresponding path program 1 times 54.07/20.06 [2019-03-28 12:18:54,379 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.06 [2019-03-28 12:18:54,380 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.06 [2019-03-28 12:18:54,380 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:18:54,381 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:18:54,381 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:18:54,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.06 [2019-03-28 12:18:54,398 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.06 [2019-03-28 12:18:54,399 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.06 [2019-03-28 12:18:54,399 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 54.07/20.06 [2019-03-28 12:18:54,399 INFO L799 eck$LassoCheckResult]: stem already infeasible 54.07/20.06 [2019-03-28 12:18:54,399 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.06 [2019-03-28 12:18:54,400 INFO L82 PathProgramCache]: Analyzing trace with hash 417474562, now seen corresponding path program 1 times 54.07/20.06 [2019-03-28 12:18:54,400 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.06 [2019-03-28 12:18:54,400 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.06 [2019-03-28 12:18:54,400 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:18:54,401 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:18:54,401 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:18:54,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.06 [2019-03-28 12:18:54,428 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.06 [2019-03-28 12:18:54,428 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.06 [2019-03-28 12:18:54,428 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 54.07/20.06 [2019-03-28 12:18:54,429 INFO L811 eck$LassoCheckResult]: loop already infeasible 54.07/20.06 [2019-03-28 12:18:54,429 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 54.07/20.06 [2019-03-28 12:18:54,429 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 54.07/20.06 [2019-03-28 12:18:54,429 INFO L87 Difference]: Start difference. First operand 1063 states and 1936 transitions. cyclomatic complexity: 874 Second operand 3 states. 54.07/20.06 [2019-03-28 12:18:54,649 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 54.07/20.06 [2019-03-28 12:18:54,649 INFO L93 Difference]: Finished difference Result 1063 states and 1838 transitions. 54.07/20.06 [2019-03-28 12:18:54,650 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 54.07/20.06 [2019-03-28 12:18:54,650 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1063 states and 1838 transitions. 54.07/20.06 [2019-03-28 12:18:54,654 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1020 54.07/20.06 [2019-03-28 12:18:54,660 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1063 states to 1063 states and 1838 transitions. 54.07/20.06 [2019-03-28 12:18:54,661 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1063 54.07/20.06 [2019-03-28 12:18:54,662 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1063 54.07/20.06 [2019-03-28 12:18:54,662 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1063 states and 1838 transitions. 54.07/20.06 [2019-03-28 12:18:54,663 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 54.07/20.06 [2019-03-28 12:18:54,663 INFO L706 BuchiCegarLoop]: Abstraction has 1063 states and 1838 transitions. 54.07/20.06 [2019-03-28 12:18:54,664 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1063 states and 1838 transitions. 54.07/20.06 [2019-03-28 12:18:54,680 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1063 to 1063. 54.07/20.06 [2019-03-28 12:18:54,680 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1063 states. 54.07/20.06 [2019-03-28 12:18:54,683 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1063 states to 1063 states and 1838 transitions. 54.07/20.06 [2019-03-28 12:18:54,683 INFO L729 BuchiCegarLoop]: Abstraction has 1063 states and 1838 transitions. 54.07/20.06 [2019-03-28 12:18:54,683 INFO L609 BuchiCegarLoop]: Abstraction has 1063 states and 1838 transitions. 54.07/20.06 [2019-03-28 12:18:54,683 INFO L442 BuchiCegarLoop]: ======== Iteration 25============ 54.07/20.06 [2019-03-28 12:18:54,683 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1063 states and 1838 transitions. 54.07/20.06 [2019-03-28 12:18:54,686 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1020 54.07/20.06 [2019-03-28 12:18:54,687 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 54.07/20.06 [2019-03-28 12:18:54,687 INFO L119 BuchiIsEmpty]: Starting construction of run 54.07/20.06 [2019-03-28 12:18:54,688 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.06 [2019-03-28 12:18:54,688 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.06 [2019-03-28 12:18:54,689 INFO L794 eck$LassoCheckResult]: Stem: 20537#ULTIMATE.startENTRY [885] ULTIMATE.startENTRY-->L202: Formula: (and (= v_~d0_ev~0_23 2) (= 0 v_~z_val~0_13) (= 2 v_~b1_ev~0_23) (= v_~d0_val_t~0_9 1) (= v_~b0_val~0_13 0) (= 1 v_~b1_val_t~0_9) (= 1 v_~d1_req_up~0_12) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_9 0) (= 2 v_~d1_ev~0_23) (= v_~b1_val~0_13 0) (= v_~b0_val_t~0_9 1) (= v_~b0_req_up~0_12 1) (= 0 v_~comp_m1_i~0_7) (= v_~d0_req_up~0_12 1) (= v_~comp_m1_st~0_15 0) (= v_~b0_ev~0_23 2) (= 1 v_~d1_val_t~0_9) (= v_~z_req_up~0_12 0) (= v_~z_val_t~0_10 0) (= 0 v_~d1_val~0_13) (= v_~z_ev~0_19 2) (= v_~b1_req_up~0_12 1) (= 0 v_~d0_val~0_13)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_4|, ~b1_val~0=v_~b1_val~0_13, ~b0_val~0=v_~b0_val~0_13, ~d0_req_up~0=v_~d0_req_up~0_12, ~d0_val~0=v_~d0_val~0_13, ~d1_val_t~0=v_~d1_val_t~0_9, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_9, ~d1_ev~0=v_~d1_ev~0_23, ~d1_val~0=v_~d1_val~0_13, ~b0_req_up~0=v_~b0_req_up~0_12, ~z_ev~0=v_~z_ev~0_19, ~b1_val_t~0=v_~b1_val_t~0_9, ~b1_ev~0=v_~b1_ev~0_23, ULTIMATE.start_main_~__retres1~2=v_ULTIMATE.start_main_~__retres1~2_6, ~z_val~0=v_~z_val~0_13, ~d1_req_up~0=v_~d1_req_up~0_12, ~z_val_t~0=v_~z_val_t~0_10, ~b0_val_t~0=v_~b0_val_t~0_9, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~z_req_up~0=v_~z_req_up~0_12, ~b1_req_up~0=v_~b1_req_up~0_12, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~d0_ev~0=v_~d0_ev~0_23, ~b0_ev~0=v_~b0_ev~0_23, ~d0_val_t~0=v_~d0_val_t~0_9, ~comp_m1_st~0=v_~comp_m1_st~0_15, ~comp_m1_i~0=v_~comp_m1_i~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ~b1_val~0, ~b0_val~0, ~d0_req_up~0, ~d0_val~0, ~d1_val_t~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~d1_ev~0, ~d1_val~0, ~b0_req_up~0, ~z_ev~0, ~b1_val_t~0, ~b1_ev~0, ULTIMATE.start_main_~__retres1~2, ~z_val~0, ~d1_req_up~0, ~z_val_t~0, ~b0_val_t~0, ULTIMATE.start_start_simulation_~tmp~3, ~z_req_up~0, ~b1_req_up~0, ULTIMATE.start_main_#res, ~d0_ev~0, ~b0_ev~0, ~d0_val_t~0, ~comp_m1_st~0, ~comp_m1_i~0] 20538#L202 [566] L202-->L127: Formula: (= 1 v_~b0_req_up~0_4) InVars {~b0_req_up~0=v_~b0_req_up~0_4} OutVars{~b0_req_up~0=v_~b0_req_up~0_4} AuxVars[] AssignedVars[] 20498#L127 [748] L127-->L127-2: Formula: (and (= v_~b0_val~0_3 v_~b0_val_t~0_3) (> v_~b0_val_t~0_3 v_~b0_val~0_4) (= v_~b0_ev~0_3 0)) InVars {~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_4} OutVars{~b0_ev~0=v_~b0_ev~0_3, ~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_3} AuxVars[] AssignedVars[~b0_val~0, ~b0_ev~0] 20499#L127-2 [580] L127-2-->L202-1: Formula: (= v_~b0_req_up~0_5 0) InVars {} OutVars{~b0_req_up~0=v_~b0_req_up~0_5} AuxVars[] AssignedVars[~b0_req_up~0] 20533#L202-1 [545] L202-1-->L142: Formula: (= 1 v_~b1_req_up~0_4) InVars {~b1_req_up~0=v_~b1_req_up~0_4} OutVars{~b1_req_up~0=v_~b1_req_up~0_4} AuxVars[] AssignedVars[] 20514#L142 [752] L142-->L142-2: Formula: (and (= v_~b1_ev~0_3 0) (< v_~b1_val~0_4 v_~b1_val_t~0_3) (= v_~b1_val~0_3 v_~b1_val_t~0_3)) InVars {~b1_val_t~0=v_~b1_val_t~0_3, ~b1_val~0=v_~b1_val~0_4} OutVars{~b1_val_t~0=v_~b1_val_t~0_3, ~b1_ev~0=v_~b1_ev~0_3, ~b1_val~0=v_~b1_val~0_3} AuxVars[] AssignedVars[~b1_val~0, ~b1_ev~0] 20507#L142-2 [521] L142-2-->L209: Formula: (= v_~b1_req_up~0_5 0) InVars {} OutVars{~b1_req_up~0=v_~b1_req_up~0_5} AuxVars[] AssignedVars[~b1_req_up~0] 20508#L209 [624] L209-->L157: Formula: (= v_~d0_req_up~0_4 1) InVars {~d0_req_up~0=v_~d0_req_up~0_4} OutVars{~d0_req_up~0=v_~d0_req_up~0_4} AuxVars[] AssignedVars[] 20482#L157 [757] L157-->L157-2: Formula: (and (> v_~d0_val_t~0_3 v_~d0_val~0_4) (= v_~d0_val~0_3 v_~d0_val_t~0_3) (= v_~d0_ev~0_3 0)) InVars {~d0_val~0=v_~d0_val~0_4, ~d0_val_t~0=v_~d0_val_t~0_3} OutVars{~d0_ev~0=v_~d0_ev~0_3, ~d0_val~0=v_~d0_val~0_3, ~d0_val_t~0=v_~d0_val_t~0_3} AuxVars[] AssignedVars[~d0_ev~0, ~d0_val~0] 20472#L157-2 [600] L157-2-->L216: Formula: (= v_~d0_req_up~0_5 0) InVars {} OutVars{~d0_req_up~0=v_~d0_req_up~0_5} AuxVars[] AssignedVars[~d0_req_up~0] 20473#L216 [554] L216-->L172: Formula: (= v_~d1_req_up~0_4 1) InVars {~d1_req_up~0=v_~d1_req_up~0_4} OutVars{~d1_req_up~0=v_~d1_req_up~0_4} AuxVars[] AssignedVars[] 20543#L172 [760] L172-->L172-2: Formula: (and (= v_~d1_val~0_3 v_~d1_val_t~0_3) (= v_~d1_ev~0_3 0) (> v_~d1_val_t~0_3 v_~d1_val~0_4)) InVars {~d1_val_t~0=v_~d1_val_t~0_3, ~d1_val~0=v_~d1_val~0_4} OutVars{~d1_val_t~0=v_~d1_val_t~0_3, ~d1_val~0=v_~d1_val~0_3, ~d1_ev~0=v_~d1_ev~0_3} AuxVars[] AssignedVars[~d1_val~0, ~d1_ev~0] 20536#L172-2 [547] L172-2-->L223: Formula: (= v_~d1_req_up~0_5 0) InVars {} OutVars{~d1_req_up~0=v_~d1_req_up~0_5} AuxVars[] AssignedVars[~d1_req_up~0] 20535#L223 [762] L223-->L230: Formula: (> 1 v_~z_req_up~0_6) InVars {~z_req_up~0=v_~z_req_up~0_6} OutVars{~z_req_up~0=v_~z_req_up~0_6} AuxVars[] AssignedVars[] 20474#L230 [767] L230-->L245-1: Formula: (and (> 1 v_~comp_m1_i~0_4) (= v_~comp_m1_st~0_5 2)) InVars {~comp_m1_i~0=v_~comp_m1_i~0_4} OutVars{~comp_m1_st~0=v_~comp_m1_st~0_5, ~comp_m1_i~0=v_~comp_m1_i~0_4} AuxVars[] AssignedVars[~comp_m1_st~0] 20475#L245-1 [608] L245-1-->L311-1: Formula: (and (= v_~b0_ev~0_5 1) (= v_~b0_ev~0_6 0)) InVars {~b0_ev~0=v_~b0_ev~0_6} OutVars{~b0_ev~0=v_~b0_ev~0_5} AuxVars[] AssignedVars[~b0_ev~0] 20494#L311-1 [628] L311-1-->L316-1: Formula: (and (= 0 v_~b1_ev~0_6) (= v_~b1_ev~0_5 1)) InVars {~b1_ev~0=v_~b1_ev~0_6} OutVars{~b1_ev~0=v_~b1_ev~0_5} AuxVars[] AssignedVars[~b1_ev~0] 20559#L316-1 [654] L316-1-->L321-1: Formula: (and (= v_~d0_ev~0_5 1) (= v_~d0_ev~0_6 0)) InVars {~d0_ev~0=v_~d0_ev~0_6} OutVars{~d0_ev~0=v_~d0_ev~0_5} AuxVars[] AssignedVars[~d0_ev~0] 20560#L321-1 [507] L321-1-->L326-1: Formula: (and (= 0 v_~d1_ev~0_6) (= v_~d1_ev~0_5 1)) InVars {~d1_ev~0=v_~d1_ev~0_6} OutVars{~d1_ev~0=v_~d1_ev~0_5} AuxVars[] AssignedVars[~d1_ev~0] 20583#L326-1 [776] L326-1-->L331-1: Formula: (< 0 v_~z_ev~0_7) InVars {~z_ev~0=v_~z_ev~0_7} OutVars{~z_ev~0=v_~z_ev~0_7} AuxVars[] AssignedVars[] 20582#L331-1 [583] L331-1-->L97: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_1|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 20576#L97 [591] L97-->L119: Formula: (and (= v_~b0_ev~0_11 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4 1)) InVars {~b0_ev~0=v_~b0_ev~0_11} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4, ~b0_ev~0=v_~b0_ev~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 20577#L119 [886] L119-->L380: Formula: (and (= |v_ULTIMATE.start_is_method1_triggered_#res_7| v_ULTIMATE.start_activate_threads_~tmp~1_13) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19 |v_ULTIMATE.start_is_method1_triggered_#res_7|)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_13, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_7|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_7|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 20511#L380 [785] L380-->L380-2: Formula: (and (= v_~comp_m1_st~0_6 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_8)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8, ~comp_m1_st~0=v_~comp_m1_st~0_6} AuxVars[] AssignedVars[~comp_m1_st~0] 20512#L380-2 [618] L380-2-->L344-1: Formula: (and (= v_~b0_ev~0_15 2) (= v_~b0_ev~0_16 1)) InVars {~b0_ev~0=v_~b0_ev~0_16} OutVars{~b0_ev~0=v_~b0_ev~0_15} AuxVars[] AssignedVars[~b0_ev~0] 20515#L344-1 [626] L344-1-->L349-1: Formula: (and (= 1 v_~b1_ev~0_16) (= v_~b1_ev~0_15 2)) InVars {~b1_ev~0=v_~b1_ev~0_16} OutVars{~b1_ev~0=v_~b1_ev~0_15} AuxVars[] AssignedVars[~b1_ev~0] 20523#L349-1 [652] L349-1-->L354-1: Formula: (and (= v_~d0_ev~0_15 2) (= v_~d0_ev~0_16 1)) InVars {~d0_ev~0=v_~d0_ev~0_16} OutVars{~d0_ev~0=v_~d0_ev~0_15} AuxVars[] AssignedVars[~d0_ev~0] 20480#L354-1 [502] L354-1-->L359-1: Formula: (and (= 1 v_~d1_ev~0_16) (= v_~d1_ev~0_15 2)) InVars {~d1_ev~0=v_~d1_ev~0_16} OutVars{~d1_ev~0=v_~d1_ev~0_15} AuxVars[] AssignedVars[~d1_ev~0] 20481#L359-1 [797] L359-1-->L422-1: Formula: (> v_~z_ev~0_13 1) InVars {~z_ev~0=v_~z_ev~0_13} OutVars{~z_ev~0=v_~z_ev~0_13} AuxVars[] AssignedVars[] 20545#L422-1 54.07/20.06 [2019-03-28 12:18:54,689 INFO L796 eck$LassoCheckResult]: Loop: 20545#L422-1 [887] L422-1-->L285: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 1) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 20697#L285 [888] L285-->L258: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_13, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res] 20695#L258 [802] L258-->L265: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8 0) (> 0 v_~comp_m1_st~0_9)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_9} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8, ~comp_m1_st~0=v_~comp_m1_st~0_9} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 20690#L265 [889] L265-->L280: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___0~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 20685#L280 [890] L280-->L202-2: Formula: (and (= v_ULTIMATE.start_eval_~tmp___0~0_8 0) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 2)) InVars {ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 20678#L202-2 [800] L202-2-->L202-3: Formula: (> 1 v_~b0_req_up~0_9) InVars {~b0_req_up~0=v_~b0_req_up~0_9} OutVars{~b0_req_up~0=v_~b0_req_up~0_9} AuxVars[] AssignedVars[] 20524#L202-3 [807] L202-3-->L209-1: Formula: (> 1 v_~b1_req_up~0_9) InVars {~b1_req_up~0=v_~b1_req_up~0_9} OutVars{~b1_req_up~0=v_~b1_req_up~0_9} AuxVars[] AssignedVars[] 20525#L209-1 [811] L209-1-->L216-1: Formula: (< v_~d0_req_up~0_9 1) InVars {~d0_req_up~0=v_~d0_req_up~0_9} OutVars{~d0_req_up~0=v_~d0_req_up~0_9} AuxVars[] AssignedVars[] 21382#L216-1 [815] L216-1-->L223-1: Formula: (< v_~d1_req_up~0_9 1) InVars {~d1_req_up~0=v_~d1_req_up~0_9} OutVars{~d1_req_up~0=v_~d1_req_up~0_9} AuxVars[] AssignedVars[] 21378#L223-1 [821] L223-1-->L230-1: Formula: (> 1 v_~z_req_up~0_9) InVars {~z_req_up~0=v_~z_req_up~0_9} OutVars{~z_req_up~0=v_~z_req_up~0_9} AuxVars[] AssignedVars[] 21233#L230-1 [498] L230-1-->L311-2: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 3) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 21376#L311-2 [829] L311-2-->L311-4: Formula: (> v_~b0_ev~0_10 0) InVars {~b0_ev~0=v_~b0_ev~0_10} OutVars{~b0_ev~0=v_~b0_ev~0_10} AuxVars[] AssignedVars[] 21374#L311-4 [833] L311-4-->L316-3: Formula: (< 0 v_~b1_ev~0_10) InVars {~b1_ev~0=v_~b1_ev~0_10} OutVars{~b1_ev~0=v_~b1_ev~0_10} AuxVars[] AssignedVars[] 21372#L316-3 [838] L316-3-->L321-3: Formula: (< v_~d0_ev~0_10 0) InVars {~d0_ev~0=v_~d0_ev~0_10} OutVars{~d0_ev~0=v_~d0_ev~0_10} AuxVars[] AssignedVars[] 21370#L321-3 [845] L321-3-->L326-3: Formula: (< 0 v_~d1_ev~0_10) InVars {~d1_ev~0=v_~d1_ev~0_10} OutVars{~d1_ev~0=v_~d1_ev~0_10} AuxVars[] AssignedVars[] 20614#L326-3 [850] L326-3-->L331-3: Formula: (> v_~z_ev~0_10 0) InVars {~z_ev~0=v_~z_ev~0_10} OutVars{~z_ev~0=v_~z_ev~0_10} AuxVars[] AssignedVars[] 20609#L331-3 [570] L331-3-->L97-1: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_4|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_10, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 20604#L97-1 [588] L97-1-->L119-1: Formula: (and (= v_~b0_ev~0_13 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13 1)) InVars {~b0_ev~0=v_~b0_ev~0_13} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13, ~b0_ev~0=v_~b0_ev~0_13} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 20606#L119-1 [891] L119-1-->L380-3: Formula: (and (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20 |v_ULTIMATE.start_is_method1_triggered_#res_8|) (= |v_ULTIMATE.start_is_method1_triggered_#res_8| v_ULTIMATE.start_activate_threads_~tmp~1_14)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_14, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_8|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_8|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 21470#L380-3 [864] L380-3-->L380-5: Formula: (and (= v_~comp_m1_st~0_7 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11, ~comp_m1_st~0=v_~comp_m1_st~0_7} AuxVars[] AssignedVars[~comp_m1_st~0] 20476#L380-5 [601] L380-5-->L344-3: Formula: (and (= v_~b0_ev~0_19 1) (= v_~b0_ev~0_18 2)) InVars {~b0_ev~0=v_~b0_ev~0_19} OutVars{~b0_ev~0=v_~b0_ev~0_18} AuxVars[] AssignedVars[~b0_ev~0] 20477#L344-3 [870] L344-3-->L349-3: Formula: (< 1 v_~b1_ev~0_20) InVars {~b1_ev~0=v_~b1_ev~0_20} OutVars{~b1_ev~0=v_~b1_ev~0_20} AuxVars[] AssignedVars[] 20588#L349-3 [656] L349-3-->L354-3: Formula: (and (= v_~d0_ev~0_18 2) (= v_~d0_ev~0_19 1)) InVars {~d0_ev~0=v_~d0_ev~0_19} OutVars{~d0_ev~0=v_~d0_ev~0_18} AuxVars[] AssignedVars[~d0_ev~0] 20587#L354-3 [513] L354-3-->L359-3: Formula: (and (= 1 v_~d1_ev~0_19) (= v_~d1_ev~0_18 2)) InVars {~d1_ev~0=v_~d1_ev~0_19} OutVars{~d1_ev~0=v_~d1_ev~0_18} AuxVars[] AssignedVars[~d1_ev~0] 20497#L359-3 [876] L359-3-->L364-3: Formula: (> v_~z_ev~0_16 1) InVars {~z_ev~0=v_~z_ev~0_16} OutVars{~z_ev~0=v_~z_ev~0_16} AuxVars[] AssignedVars[] 20518#L364-3 [568] L364-3-->L258-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_5, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_2|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_#res] 20555#L258-1 [666] L258-1-->L265-1: Formula: (and (= v_~comp_m1_st~0_10 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9 1)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_10} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9, ~comp_m1_st~0=v_~comp_m1_st~0_10} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 21368#L265-1 [892] L265-1-->L397: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_stop_simulation_~tmp~2_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_4|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_~tmp~2] 21366#L397 [880] L397-->L404: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_4 0) (< 0 v_ULTIMATE.start_stop_simulation_~tmp~2_5)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_4, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 20554#L404 [897] L404-->L422-1: Formula: (and (= 0 v_ULTIMATE.start_start_simulation_~tmp~3_9) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= |v_ULTIMATE.start_stop_simulation_#res_5| v_ULTIMATE.start_start_simulation_~tmp~3_9)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_~tmp~3] 20545#L422-1 54.07/20.06 [2019-03-28 12:18:54,689 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.06 [2019-03-28 12:18:54,690 INFO L82 PathProgramCache]: Analyzing trace with hash -1069091576, now seen corresponding path program 2 times 54.07/20.06 [2019-03-28 12:18:54,690 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.06 [2019-03-28 12:18:54,690 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.06 [2019-03-28 12:18:54,691 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:18:54,691 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:18:54,691 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:18:54,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 54.07/20.06 [2019-03-28 12:18:54,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 54.07/20.06 [2019-03-28 12:18:54,707 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.06 [2019-03-28 12:18:54,708 INFO L82 PathProgramCache]: Analyzing trace with hash -1805228494, now seen corresponding path program 1 times 54.07/20.06 [2019-03-28 12:18:54,708 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.06 [2019-03-28 12:18:54,708 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.06 [2019-03-28 12:18:54,709 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:18:54,709 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:18:54,709 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:18:54,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.06 [2019-03-28 12:18:54,722 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.06 [2019-03-28 12:18:54,723 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.06 [2019-03-28 12:18:54,723 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 54.07/20.06 [2019-03-28 12:18:54,723 INFO L811 eck$LassoCheckResult]: loop already infeasible 54.07/20.06 [2019-03-28 12:18:54,723 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 54.07/20.06 [2019-03-28 12:18:54,724 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 54.07/20.06 [2019-03-28 12:18:54,724 INFO L87 Difference]: Start difference. First operand 1063 states and 1838 transitions. cyclomatic complexity: 776 Second operand 3 states. 54.07/20.06 [2019-03-28 12:18:54,966 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 54.07/20.06 [2019-03-28 12:18:54,966 INFO L93 Difference]: Finished difference Result 2090 states and 3467 transitions. 54.07/20.06 [2019-03-28 12:18:54,967 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 54.07/20.06 [2019-03-28 12:18:54,967 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2090 states and 3467 transitions. 54.07/20.06 [2019-03-28 12:18:54,975 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2024 54.07/20.06 [2019-03-28 12:18:54,987 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2090 states to 2090 states and 3467 transitions. 54.07/20.06 [2019-03-28 12:18:54,987 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2090 54.07/20.06 [2019-03-28 12:18:54,988 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2090 54.07/20.06 [2019-03-28 12:18:54,989 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2090 states and 3467 transitions. 54.07/20.06 [2019-03-28 12:18:54,991 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 54.07/20.06 [2019-03-28 12:18:54,991 INFO L706 BuchiCegarLoop]: Abstraction has 2090 states and 3467 transitions. 54.07/20.06 [2019-03-28 12:18:54,993 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2090 states and 3467 transitions. 54.07/20.06 [2019-03-28 12:18:55,024 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2090 to 2090. 54.07/20.06 [2019-03-28 12:18:55,024 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2090 states. 54.07/20.06 [2019-03-28 12:18:55,029 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2090 states to 2090 states and 3467 transitions. 54.07/20.06 [2019-03-28 12:18:55,029 INFO L729 BuchiCegarLoop]: Abstraction has 2090 states and 3467 transitions. 54.07/20.06 [2019-03-28 12:18:55,029 INFO L609 BuchiCegarLoop]: Abstraction has 2090 states and 3467 transitions. 54.07/20.06 [2019-03-28 12:18:55,029 INFO L442 BuchiCegarLoop]: ======== Iteration 26============ 54.07/20.06 [2019-03-28 12:18:55,029 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2090 states and 3467 transitions. 54.07/20.06 [2019-03-28 12:18:55,035 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2024 54.07/20.06 [2019-03-28 12:18:55,035 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 54.07/20.06 [2019-03-28 12:18:55,035 INFO L119 BuchiIsEmpty]: Starting construction of run 54.07/20.06 [2019-03-28 12:18:55,037 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.06 [2019-03-28 12:18:55,037 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.06 [2019-03-28 12:18:55,037 INFO L794 eck$LassoCheckResult]: Stem: 23696#ULTIMATE.startENTRY [885] ULTIMATE.startENTRY-->L202: Formula: (and (= v_~d0_ev~0_23 2) (= 0 v_~z_val~0_13) (= 2 v_~b1_ev~0_23) (= v_~d0_val_t~0_9 1) (= v_~b0_val~0_13 0) (= 1 v_~b1_val_t~0_9) (= 1 v_~d1_req_up~0_12) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_9 0) (= 2 v_~d1_ev~0_23) (= v_~b1_val~0_13 0) (= v_~b0_val_t~0_9 1) (= v_~b0_req_up~0_12 1) (= 0 v_~comp_m1_i~0_7) (= v_~d0_req_up~0_12 1) (= v_~comp_m1_st~0_15 0) (= v_~b0_ev~0_23 2) (= 1 v_~d1_val_t~0_9) (= v_~z_req_up~0_12 0) (= v_~z_val_t~0_10 0) (= 0 v_~d1_val~0_13) (= v_~z_ev~0_19 2) (= v_~b1_req_up~0_12 1) (= 0 v_~d0_val~0_13)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_4|, ~b1_val~0=v_~b1_val~0_13, ~b0_val~0=v_~b0_val~0_13, ~d0_req_up~0=v_~d0_req_up~0_12, ~d0_val~0=v_~d0_val~0_13, ~d1_val_t~0=v_~d1_val_t~0_9, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_9, ~d1_ev~0=v_~d1_ev~0_23, ~d1_val~0=v_~d1_val~0_13, ~b0_req_up~0=v_~b0_req_up~0_12, ~z_ev~0=v_~z_ev~0_19, ~b1_val_t~0=v_~b1_val_t~0_9, ~b1_ev~0=v_~b1_ev~0_23, ULTIMATE.start_main_~__retres1~2=v_ULTIMATE.start_main_~__retres1~2_6, ~z_val~0=v_~z_val~0_13, ~d1_req_up~0=v_~d1_req_up~0_12, ~z_val_t~0=v_~z_val_t~0_10, ~b0_val_t~0=v_~b0_val_t~0_9, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~z_req_up~0=v_~z_req_up~0_12, ~b1_req_up~0=v_~b1_req_up~0_12, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~d0_ev~0=v_~d0_ev~0_23, ~b0_ev~0=v_~b0_ev~0_23, ~d0_val_t~0=v_~d0_val_t~0_9, ~comp_m1_st~0=v_~comp_m1_st~0_15, ~comp_m1_i~0=v_~comp_m1_i~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ~b1_val~0, ~b0_val~0, ~d0_req_up~0, ~d0_val~0, ~d1_val_t~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~d1_ev~0, ~d1_val~0, ~b0_req_up~0, ~z_ev~0, ~b1_val_t~0, ~b1_ev~0, ULTIMATE.start_main_~__retres1~2, ~z_val~0, ~d1_req_up~0, ~z_val_t~0, ~b0_val_t~0, ULTIMATE.start_start_simulation_~tmp~3, ~z_req_up~0, ~b1_req_up~0, ULTIMATE.start_main_#res, ~d0_ev~0, ~b0_ev~0, ~d0_val_t~0, ~comp_m1_st~0, ~comp_m1_i~0] 23697#L202 [566] L202-->L127: Formula: (= 1 v_~b0_req_up~0_4) InVars {~b0_req_up~0=v_~b0_req_up~0_4} OutVars{~b0_req_up~0=v_~b0_req_up~0_4} AuxVars[] AssignedVars[] 23657#L127 [748] L127-->L127-2: Formula: (and (= v_~b0_val~0_3 v_~b0_val_t~0_3) (> v_~b0_val_t~0_3 v_~b0_val~0_4) (= v_~b0_ev~0_3 0)) InVars {~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_4} OutVars{~b0_ev~0=v_~b0_ev~0_3, ~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_3} AuxVars[] AssignedVars[~b0_val~0, ~b0_ev~0] 23658#L127-2 [580] L127-2-->L202-1: Formula: (= v_~b0_req_up~0_5 0) InVars {} OutVars{~b0_req_up~0=v_~b0_req_up~0_5} AuxVars[] AssignedVars[~b0_req_up~0] 23692#L202-1 [545] L202-1-->L142: Formula: (= 1 v_~b1_req_up~0_4) InVars {~b1_req_up~0=v_~b1_req_up~0_4} OutVars{~b1_req_up~0=v_~b1_req_up~0_4} AuxVars[] AssignedVars[] 23673#L142 [752] L142-->L142-2: Formula: (and (= v_~b1_ev~0_3 0) (< v_~b1_val~0_4 v_~b1_val_t~0_3) (= v_~b1_val~0_3 v_~b1_val_t~0_3)) InVars {~b1_val_t~0=v_~b1_val_t~0_3, ~b1_val~0=v_~b1_val~0_4} OutVars{~b1_val_t~0=v_~b1_val_t~0_3, ~b1_ev~0=v_~b1_ev~0_3, ~b1_val~0=v_~b1_val~0_3} AuxVars[] AssignedVars[~b1_val~0, ~b1_ev~0] 23666#L142-2 [521] L142-2-->L209: Formula: (= v_~b1_req_up~0_5 0) InVars {} OutVars{~b1_req_up~0=v_~b1_req_up~0_5} AuxVars[] AssignedVars[~b1_req_up~0] 23667#L209 [624] L209-->L157: Formula: (= v_~d0_req_up~0_4 1) InVars {~d0_req_up~0=v_~d0_req_up~0_4} OutVars{~d0_req_up~0=v_~d0_req_up~0_4} AuxVars[] AssignedVars[] 23641#L157 [757] L157-->L157-2: Formula: (and (> v_~d0_val_t~0_3 v_~d0_val~0_4) (= v_~d0_val~0_3 v_~d0_val_t~0_3) (= v_~d0_ev~0_3 0)) InVars {~d0_val~0=v_~d0_val~0_4, ~d0_val_t~0=v_~d0_val_t~0_3} OutVars{~d0_ev~0=v_~d0_ev~0_3, ~d0_val~0=v_~d0_val~0_3, ~d0_val_t~0=v_~d0_val_t~0_3} AuxVars[] AssignedVars[~d0_ev~0, ~d0_val~0] 23632#L157-2 [600] L157-2-->L216: Formula: (= v_~d0_req_up~0_5 0) InVars {} OutVars{~d0_req_up~0=v_~d0_req_up~0_5} AuxVars[] AssignedVars[~d0_req_up~0] 23633#L216 [554] L216-->L172: Formula: (= v_~d1_req_up~0_4 1) InVars {~d1_req_up~0=v_~d1_req_up~0_4} OutVars{~d1_req_up~0=v_~d1_req_up~0_4} AuxVars[] AssignedVars[] 23701#L172 [760] L172-->L172-2: Formula: (and (= v_~d1_val~0_3 v_~d1_val_t~0_3) (= v_~d1_ev~0_3 0) (> v_~d1_val_t~0_3 v_~d1_val~0_4)) InVars {~d1_val_t~0=v_~d1_val_t~0_3, ~d1_val~0=v_~d1_val~0_4} OutVars{~d1_val_t~0=v_~d1_val_t~0_3, ~d1_val~0=v_~d1_val~0_3, ~d1_ev~0=v_~d1_ev~0_3} AuxVars[] AssignedVars[~d1_val~0, ~d1_ev~0] 23695#L172-2 [547] L172-2-->L223: Formula: (= v_~d1_req_up~0_5 0) InVars {} OutVars{~d1_req_up~0=v_~d1_req_up~0_5} AuxVars[] AssignedVars[~d1_req_up~0] 23694#L223 [762] L223-->L230: Formula: (> 1 v_~z_req_up~0_6) InVars {~z_req_up~0=v_~z_req_up~0_6} OutVars{~z_req_up~0=v_~z_req_up~0_6} AuxVars[] AssignedVars[] 23634#L230 [767] L230-->L245-1: Formula: (and (> 1 v_~comp_m1_i~0_4) (= v_~comp_m1_st~0_5 2)) InVars {~comp_m1_i~0=v_~comp_m1_i~0_4} OutVars{~comp_m1_st~0=v_~comp_m1_st~0_5, ~comp_m1_i~0=v_~comp_m1_i~0_4} AuxVars[] AssignedVars[~comp_m1_st~0] 23635#L245-1 [608] L245-1-->L311-1: Formula: (and (= v_~b0_ev~0_5 1) (= v_~b0_ev~0_6 0)) InVars {~b0_ev~0=v_~b0_ev~0_6} OutVars{~b0_ev~0=v_~b0_ev~0_5} AuxVars[] AssignedVars[~b0_ev~0] 23653#L311-1 [628] L311-1-->L316-1: Formula: (and (= 0 v_~b1_ev~0_6) (= v_~b1_ev~0_5 1)) InVars {~b1_ev~0=v_~b1_ev~0_6} OutVars{~b1_ev~0=v_~b1_ev~0_5} AuxVars[] AssignedVars[~b1_ev~0] 23722#L316-1 [654] L316-1-->L321-1: Formula: (and (= v_~d0_ev~0_5 1) (= v_~d0_ev~0_6 0)) InVars {~d0_ev~0=v_~d0_ev~0_6} OutVars{~d0_ev~0=v_~d0_ev~0_5} AuxVars[] AssignedVars[~d0_ev~0] 23723#L321-1 [507] L321-1-->L326-1: Formula: (and (= 0 v_~d1_ev~0_6) (= v_~d1_ev~0_5 1)) InVars {~d1_ev~0=v_~d1_ev~0_6} OutVars{~d1_ev~0=v_~d1_ev~0_5} AuxVars[] AssignedVars[~d1_ev~0] 23708#L326-1 [776] L326-1-->L331-1: Formula: (< 0 v_~z_ev~0_7) InVars {~z_ev~0=v_~z_ev~0_7} OutVars{~z_ev~0=v_~z_ev~0_7} AuxVars[] AssignedVars[] 23709#L331-1 [583] L331-1-->L97: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_1|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 23739#L97 [591] L97-->L119: Formula: (and (= v_~b0_ev~0_11 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4 1)) InVars {~b0_ev~0=v_~b0_ev~0_11} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4, ~b0_ev~0=v_~b0_ev~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 23740#L119 [886] L119-->L380: Formula: (and (= |v_ULTIMATE.start_is_method1_triggered_#res_7| v_ULTIMATE.start_activate_threads_~tmp~1_13) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19 |v_ULTIMATE.start_is_method1_triggered_#res_7|)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_13, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_7|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_7|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 23670#L380 [785] L380-->L380-2: Formula: (and (= v_~comp_m1_st~0_6 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_8)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8, ~comp_m1_st~0=v_~comp_m1_st~0_6} AuxVars[] AssignedVars[~comp_m1_st~0] 23671#L380-2 [618] L380-2-->L344-1: Formula: (and (= v_~b0_ev~0_15 2) (= v_~b0_ev~0_16 1)) InVars {~b0_ev~0=v_~b0_ev~0_16} OutVars{~b0_ev~0=v_~b0_ev~0_15} AuxVars[] AssignedVars[~b0_ev~0] 23766#L344-1 [626] L344-1-->L349-1: Formula: (and (= 1 v_~b1_ev~0_16) (= v_~b1_ev~0_15 2)) InVars {~b1_ev~0=v_~b1_ev~0_16} OutVars{~b1_ev~0=v_~b1_ev~0_15} AuxVars[] AssignedVars[~b1_ev~0] 23763#L349-1 [652] L349-1-->L354-1: Formula: (and (= v_~d0_ev~0_15 2) (= v_~d0_ev~0_16 1)) InVars {~d0_ev~0=v_~d0_ev~0_16} OutVars{~d0_ev~0=v_~d0_ev~0_15} AuxVars[] AssignedVars[~d0_ev~0] 23764#L354-1 [502] L354-1-->L359-1: Formula: (and (= 1 v_~d1_ev~0_16) (= v_~d1_ev~0_15 2)) InVars {~d1_ev~0=v_~d1_ev~0_16} OutVars{~d1_ev~0=v_~d1_ev~0_15} AuxVars[] AssignedVars[~d1_ev~0] 24777#L359-1 [797] L359-1-->L422-1: Formula: (> v_~z_ev~0_13 1) InVars {~z_ev~0=v_~z_ev~0_13} OutVars{~z_ev~0=v_~z_ev~0_13} AuxVars[] AssignedVars[] 24775#L422-1 54.07/20.06 [2019-03-28 12:18:55,038 INFO L796 eck$LassoCheckResult]: Loop: 24775#L422-1 [887] L422-1-->L285: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 1) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 24769#L285 [888] L285-->L258: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_13, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res] 24774#L258 [802] L258-->L265: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8 0) (> 0 v_~comp_m1_st~0_9)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_9} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8, ~comp_m1_st~0=v_~comp_m1_st~0_9} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 24773#L265 [889] L265-->L280: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___0~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 24771#L280 [890] L280-->L202-2: Formula: (and (= v_ULTIMATE.start_eval_~tmp___0~0_8 0) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 2)) InVars {ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 24772#L202-2 [800] L202-2-->L202-3: Formula: (> 1 v_~b0_req_up~0_9) InVars {~b0_req_up~0=v_~b0_req_up~0_9} OutVars{~b0_req_up~0=v_~b0_req_up~0_9} AuxVars[] AssignedVars[] 25002#L202-3 [807] L202-3-->L209-1: Formula: (> 1 v_~b1_req_up~0_9) InVars {~b1_req_up~0=v_~b1_req_up~0_9} OutVars{~b1_req_up~0=v_~b1_req_up~0_9} AuxVars[] AssignedVars[] 24999#L209-1 [811] L209-1-->L216-1: Formula: (< v_~d0_req_up~0_9 1) InVars {~d0_req_up~0=v_~d0_req_up~0_9} OutVars{~d0_req_up~0=v_~d0_req_up~0_9} AuxVars[] AssignedVars[] 24997#L216-1 [815] L216-1-->L223-1: Formula: (< v_~d1_req_up~0_9 1) InVars {~d1_req_up~0=v_~d1_req_up~0_9} OutVars{~d1_req_up~0=v_~d1_req_up~0_9} AuxVars[] AssignedVars[] 24998#L223-1 [821] L223-1-->L230-1: Formula: (> 1 v_~z_req_up~0_9) InVars {~z_req_up~0=v_~z_req_up~0_9} OutVars{~z_req_up~0=v_~z_req_up~0_9} AuxVars[] AssignedVars[] 24105#L230-1 [498] L230-1-->L311-2: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_7 3) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 25025#L311-2 [829] L311-2-->L311-4: Formula: (> v_~b0_ev~0_10 0) InVars {~b0_ev~0=v_~b0_ev~0_10} OutVars{~b0_ev~0=v_~b0_ev~0_10} AuxVars[] AssignedVars[] 25023#L311-4 [833] L311-4-->L316-3: Formula: (< 0 v_~b1_ev~0_10) InVars {~b1_ev~0=v_~b1_ev~0_10} OutVars{~b1_ev~0=v_~b1_ev~0_10} AuxVars[] AssignedVars[] 25020#L316-3 [647] L316-3-->L321-3: Formula: (and (= v_~d0_ev~0_8 1) (= v_~d0_ev~0_9 0)) InVars {~d0_ev~0=v_~d0_ev~0_9} OutVars{~d0_ev~0=v_~d0_ev~0_8} AuxVars[] AssignedVars[~d0_ev~0] 25018#L321-3 [845] L321-3-->L326-3: Formula: (< 0 v_~d1_ev~0_10) InVars {~d1_ev~0=v_~d1_ev~0_10} OutVars{~d1_ev~0=v_~d1_ev~0_10} AuxVars[] AssignedVars[] 25017#L326-3 [850] L326-3-->L331-3: Formula: (> v_~z_ev~0_10 0) InVars {~z_ev~0=v_~z_ev~0_10} OutVars{~z_ev~0=v_~z_ev~0_10} AuxVars[] AssignedVars[] 25016#L331-3 [570] L331-3-->L97-1: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_4|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_10, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 25014#L97-1 [588] L97-1-->L119-1: Formula: (and (= v_~b0_ev~0_13 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13 1)) InVars {~b0_ev~0=v_~b0_ev~0_13} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_13, ~b0_ev~0=v_~b0_ev~0_13} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 24856#L119-1 [891] L119-1-->L380-3: Formula: (and (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20 |v_ULTIMATE.start_is_method1_triggered_#res_8|) (= |v_ULTIMATE.start_is_method1_triggered_#res_8| v_ULTIMATE.start_activate_threads_~tmp~1_14)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_14, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_8|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_20, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_8|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 24854#L380-3 [864] L380-3-->L380-5: Formula: (and (= v_~comp_m1_st~0_7 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11, ~comp_m1_st~0=v_~comp_m1_st~0_7} AuxVars[] AssignedVars[~comp_m1_st~0] 24851#L380-5 [601] L380-5-->L344-3: Formula: (and (= v_~b0_ev~0_19 1) (= v_~b0_ev~0_18 2)) InVars {~b0_ev~0=v_~b0_ev~0_19} OutVars{~b0_ev~0=v_~b0_ev~0_18} AuxVars[] AssignedVars[~b0_ev~0] 24786#L344-3 [870] L344-3-->L349-3: Formula: (< 1 v_~b1_ev~0_20) InVars {~b1_ev~0=v_~b1_ev~0_20} OutVars{~b1_ev~0=v_~b1_ev~0_20} AuxVars[] AssignedVars[] 24784#L349-3 [656] L349-3-->L354-3: Formula: (and (= v_~d0_ev~0_18 2) (= v_~d0_ev~0_19 1)) InVars {~d0_ev~0=v_~d0_ev~0_19} OutVars{~d0_ev~0=v_~d0_ev~0_18} AuxVars[] AssignedVars[~d0_ev~0] 24783#L354-3 [513] L354-3-->L359-3: Formula: (and (= 1 v_~d1_ev~0_19) (= v_~d1_ev~0_18 2)) InVars {~d1_ev~0=v_~d1_ev~0_19} OutVars{~d1_ev~0=v_~d1_ev~0_18} AuxVars[] AssignedVars[~d1_ev~0] 24781#L359-3 [876] L359-3-->L364-3: Formula: (> v_~z_ev~0_16 1) InVars {~z_ev~0=v_~z_ev~0_16} OutVars{~z_ev~0=v_~z_ev~0_16} AuxVars[] AssignedVars[] 23915#L364-3 [568] L364-3-->L258-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_5, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_2|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_#res] 24780#L258-1 [666] L258-1-->L265-1: Formula: (and (= v_~comp_m1_st~0_10 0) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9 1)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_10} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_9, ~comp_m1_st~0=v_~comp_m1_st~0_10} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 24779#L265-1 [892] L265-1-->L397: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_stop_simulation_~tmp~2_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_9| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_stop_simulation_#t~ret3=|v_ULTIMATE.start_stop_simulation_#t~ret3_4|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_#t~ret3, ULTIMATE.start_stop_simulation_~tmp~2] 24778#L397 [880] L397-->L404: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_4 0) (< 0 v_ULTIMATE.start_stop_simulation_~tmp~2_5)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_4, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_5} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 24776#L404 [897] L404-->L422-1: Formula: (and (= 0 v_ULTIMATE.start_start_simulation_~tmp~3_9) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= |v_ULTIMATE.start_stop_simulation_#res_5| v_ULTIMATE.start_start_simulation_~tmp~3_9)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ULTIMATE.start_stop_simulation_#res, ULTIMATE.start_start_simulation_~tmp~3] 24775#L422-1 54.07/20.06 [2019-03-28 12:18:55,038 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.06 [2019-03-28 12:18:55,038 INFO L82 PathProgramCache]: Analyzing trace with hash -1069091576, now seen corresponding path program 3 times 54.07/20.06 [2019-03-28 12:18:55,039 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.06 [2019-03-28 12:18:55,039 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.06 [2019-03-28 12:18:55,039 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:18:55,040 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:18:55,040 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:18:55,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 54.07/20.06 [2019-03-28 12:18:55,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 54.07/20.06 [2019-03-28 12:18:55,055 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.06 [2019-03-28 12:18:55,055 INFO L82 PathProgramCache]: Analyzing trace with hash 1705624435, now seen corresponding path program 1 times 54.07/20.06 [2019-03-28 12:18:55,055 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.06 [2019-03-28 12:18:55,056 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.06 [2019-03-28 12:18:55,056 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:18:55,056 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:18:55,057 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:18:55,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 54.07/20.06 [2019-03-28 12:18:55,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 54.07/20.06 [2019-03-28 12:18:55,069 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.06 [2019-03-28 12:18:55,070 INFO L82 PathProgramCache]: Analyzing trace with hash 1098084922, now seen corresponding path program 1 times 54.07/20.06 [2019-03-28 12:18:55,070 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.06 [2019-03-28 12:18:55,070 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.06 [2019-03-28 12:18:55,071 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:18:55,071 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:18:55,071 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:18:55,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.06 [2019-03-28 12:18:55,093 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.06 [2019-03-28 12:18:55,093 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.06 [2019-03-28 12:18:55,094 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 54.07/20.06 [2019-03-28 12:18:55,312 WARN L188 SmtUtils]: Spent 211.00 ms on a formula simplification. DAG size of input: 75 DAG size of output: 67 54.07/20.06 [2019-03-28 12:18:55,403 INFO L216 LassoAnalysis]: Preferences: 54.07/20.06 [2019-03-28 12:18:55,404 INFO L124 ssoRankerPreferences]: Compute integeral hull: false 54.07/20.06 [2019-03-28 12:18:55,404 INFO L125 ssoRankerPreferences]: Enable LassoPartitioneer: true 54.07/20.06 [2019-03-28 12:18:55,404 INFO L126 ssoRankerPreferences]: Term annotations enabled: false 54.07/20.06 [2019-03-28 12:18:55,404 INFO L127 ssoRankerPreferences]: Use exernal solver: true 54.07/20.06 [2019-03-28 12:18:55,405 INFO L128 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:4560 -smt2 -in -t:12000 54.07/20.06 [2019-03-28 12:18:55,405 INFO L129 ssoRankerPreferences]: Dump SMT script to file: false 54.07/20.06 [2019-03-28 12:18:55,405 INFO L130 ssoRankerPreferences]: Path of dumped script: 54.07/20.06 [2019-03-28 12:18:55,405 INFO L131 ssoRankerPreferences]: Filename of dumped script: theBenchmark.c_BEv2_Iteration26_Loop 54.07/20.06 [2019-03-28 12:18:55,405 INFO L132 ssoRankerPreferences]: MapElimAlgo: Frank 54.07/20.06 [2019-03-28 12:18:55,405 INFO L282 LassoAnalysis]: Starting lasso preprocessing... 54.07/20.06 [2019-03-28 12:18:55,428 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 54.07/20.06 [2019-03-28 12:18:55,434 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 54.07/20.06 [2019-03-28 12:18:55,436 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 54.07/20.06 [2019-03-28 12:18:55,449 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 54.07/20.06 [2019-03-28 12:18:55,457 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 54.07/20.06 [2019-03-28 12:18:55,460 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 54.07/20.06 [2019-03-28 12:18:55,462 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 54.07/20.06 [2019-03-28 12:18:55,465 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 54.07/20.06 [2019-03-28 12:18:55,472 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 54.07/20.06 [2019-03-28 12:18:55,475 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 54.07/20.06 [2019-03-28 12:18:55,478 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 54.07/20.06 [2019-03-28 12:18:55,480 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 54.07/20.06 [2019-03-28 12:18:55,483 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 54.07/20.06 [2019-03-28 12:18:55,486 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 54.07/20.06 [2019-03-28 12:18:55,489 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 54.07/20.06 [2019-03-28 12:18:55,494 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 54.07/20.06 [2019-03-28 12:18:55,497 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 54.07/20.06 [2019-03-28 12:18:55,503 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 54.07/20.06 [2019-03-28 12:18:55,505 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 54.07/20.06 [2019-03-28 12:18:55,508 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 54.07/20.06 [2019-03-28 12:18:55,510 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 54.07/20.06 [2019-03-28 12:18:55,520 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 54.07/20.06 [2019-03-28 12:18:55,522 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 54.07/20.06 [2019-03-28 12:18:55,738 INFO L300 LassoAnalysis]: Preprocessing complete. 54.07/20.06 [2019-03-28 12:18:55,739 INFO L412 LassoAnalysis]: Checking for nontermination... 54.07/20.06 No working directory specified, using /export/starexec/sandbox/solver/bin/z3 54.07/20.06 Starting monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:4560 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) 54.07/20.06 Waiting until toolchain timeout for monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:4560 -smt2 -in -t:12000 54.07/20.06 [2019-03-28 12:18:55,750 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true 54.07/20.06 [2019-03-28 12:18:55,751 INFO L163 nArgumentSynthesizer]: Using integer mode. 54.07/20.06 [2019-03-28 12:18:55,760 INFO L445 LassoAnalysis]: Proved nontermination for one component. 54.07/20.06 [2019-03-28 12:18:55,760 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret2=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret2=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] 54.07/20.06 No working directory specified, using /export/starexec/sandbox/solver/bin/z3 54.07/20.06 Starting monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:4560 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) 54.07/20.06 Waiting until toolchain timeout for monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:4560 -smt2 -in -t:12000 54.07/20.06 [2019-03-28 12:18:55,793 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true 54.07/20.06 [2019-03-28 12:18:55,794 INFO L163 nArgumentSynthesizer]: Using integer mode. 54.07/20.06 [2019-03-28 12:18:55,798 INFO L445 LassoAnalysis]: Proved nontermination for one component. 54.07/20.06 [2019-03-28 12:18:55,798 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~ret0=0} Honda state: {ULTIMATE.start_eval_#t~ret0=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] 54.07/20.06 No working directory specified, using /export/starexec/sandbox/solver/bin/z3 54.07/20.06 Starting monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:4560 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) 54.07/20.06 Waiting until toolchain timeout for monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:4560 -smt2 -in -t:12000 54.07/20.06 [2019-03-28 12:18:55,827 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true 54.07/20.06 [2019-03-28 12:18:55,827 INFO L163 nArgumentSynthesizer]: Using integer mode. 54.07/20.06 No working directory specified, using /export/starexec/sandbox/solver/bin/z3 54.07/20.06 Starting monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:4560 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) 54.07/20.06 Waiting until toolchain timeout for monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:4560 -smt2 -in -t:12000 54.07/20.06 [2019-03-28 12:18:55,861 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true 54.07/20.06 [2019-03-28 12:18:55,861 INFO L163 nArgumentSynthesizer]: Using integer mode. 54.07/20.06 [2019-03-28 12:18:55,879 INFO L452 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. 54.07/20.06 [2019-03-28 12:18:55,905 INFO L216 LassoAnalysis]: Preferences: 54.07/20.06 [2019-03-28 12:18:55,906 INFO L124 ssoRankerPreferences]: Compute integeral hull: false 54.07/20.06 [2019-03-28 12:18:55,906 INFO L125 ssoRankerPreferences]: Enable LassoPartitioneer: true 54.07/20.06 [2019-03-28 12:18:55,906 INFO L126 ssoRankerPreferences]: Term annotations enabled: false 54.07/20.06 [2019-03-28 12:18:55,906 INFO L127 ssoRankerPreferences]: Use exernal solver: false 54.07/20.06 [2019-03-28 12:18:55,906 INFO L128 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 54.07/20.06 [2019-03-28 12:18:55,906 INFO L129 ssoRankerPreferences]: Dump SMT script to file: false 54.07/20.06 [2019-03-28 12:18:55,906 INFO L130 ssoRankerPreferences]: Path of dumped script: 54.07/20.06 [2019-03-28 12:18:55,906 INFO L131 ssoRankerPreferences]: Filename of dumped script: theBenchmark.c_BEv2_Iteration26_Loop 54.07/20.06 [2019-03-28 12:18:55,907 INFO L132 ssoRankerPreferences]: MapElimAlgo: Frank 54.07/20.06 [2019-03-28 12:18:55,907 INFO L282 LassoAnalysis]: Starting lasso preprocessing... 54.07/20.06 [2019-03-28 12:18:55,910 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 54.07/20.06 [2019-03-28 12:18:55,938 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 54.07/20.06 [2019-03-28 12:18:55,986 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 54.07/20.06 [2019-03-28 12:18:55,996 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 54.07/20.06 [2019-03-28 12:18:55,999 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 54.07/20.06 [2019-03-28 12:18:56,001 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 54.07/20.06 [2019-03-28 12:18:56,005 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 54.07/20.06 [2019-03-28 12:18:56,008 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 54.07/20.06 [2019-03-28 12:18:56,012 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 54.07/20.06 [2019-03-28 12:18:56,016 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 54.07/20.06 [2019-03-28 12:18:56,019 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 54.07/20.06 [2019-03-28 12:18:56,022 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 54.07/20.06 [2019-03-28 12:18:56,025 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 54.07/20.06 [2019-03-28 12:18:56,031 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 54.07/20.06 [2019-03-28 12:18:56,041 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 54.07/20.06 [2019-03-28 12:18:56,050 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 54.07/20.06 [2019-03-28 12:18:56,059 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 54.07/20.06 [2019-03-28 12:18:56,061 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 54.07/20.06 [2019-03-28 12:18:56,067 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 54.07/20.06 [2019-03-28 12:18:56,069 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 54.07/20.06 [2019-03-28 12:18:56,073 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 54.07/20.06 [2019-03-28 12:18:56,076 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 54.07/20.06 [2019-03-28 12:18:56,078 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true 54.07/20.06 [2019-03-28 12:18:56,281 INFO L300 LassoAnalysis]: Preprocessing complete. 54.07/20.06 [2019-03-28 12:18:56,287 INFO L497 LassoAnalysis]: Using template 'affine'. 54.07/20.06 [2019-03-28 12:18:56,289 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: 54.07/20.06 Termination analysis: LINEAR_WITH_GUESSES 54.07/20.06 Number of strict supporting invariants: 0 54.07/20.06 Number of non-strict supporting invariants: 1 54.07/20.06 Consider only non-deceasing supporting invariants: true 54.07/20.06 Simplify termination arguments: true 54.07/20.06 Simplify supporting invariants: trueOverapproximate stem: false 54.07/20.06 [2019-03-28 12:18:56,291 INFO L339 nArgumentSynthesizer]: Template has degree 0. 54.07/20.06 [2019-03-28 12:18:56,291 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. 54.07/20.06 [2019-03-28 12:18:56,292 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts 54.07/20.06 [2019-03-28 12:18:56,292 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts 54.07/20.06 [2019-03-28 12:18:56,292 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. 54.07/20.06 [2019-03-28 12:18:56,294 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. 54.07/20.06 [2019-03-28 12:18:56,294 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. 54.07/20.06 [2019-03-28 12:18:56,296 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. 54.07/20.06 [2019-03-28 12:18:56,297 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: 54.07/20.06 Termination analysis: LINEAR_WITH_GUESSES 54.07/20.06 Number of strict supporting invariants: 0 54.07/20.06 Number of non-strict supporting invariants: 1 54.07/20.06 Consider only non-deceasing supporting invariants: true 54.07/20.06 Simplify termination arguments: true 54.07/20.06 Simplify supporting invariants: trueOverapproximate stem: false 54.07/20.06 [2019-03-28 12:18:56,297 INFO L339 nArgumentSynthesizer]: Template has degree 0. 54.07/20.06 [2019-03-28 12:18:56,297 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. 54.07/20.06 [2019-03-28 12:18:56,298 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts 54.07/20.06 [2019-03-28 12:18:56,298 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts 54.07/20.06 [2019-03-28 12:18:56,298 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. 54.07/20.06 [2019-03-28 12:18:56,299 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. 54.07/20.06 [2019-03-28 12:18:56,299 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. 54.07/20.06 [2019-03-28 12:18:56,303 INFO L421 nArgumentSynthesizer]: Found a termination argument, trying to simplify. 54.07/20.06 [2019-03-28 12:18:56,306 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. 54.07/20.06 [2019-03-28 12:18:56,306 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. 54.07/20.06 [2019-03-28 12:18:56,309 INFO L437 nArgumentSynthesizer]: Simplifying supporting invariants... 54.07/20.06 [2019-03-28 12:18:56,309 INFO L440 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. 54.07/20.06 [2019-03-28 12:18:56,309 INFO L518 LassoAnalysis]: Proved termination. 54.07/20.06 [2019-03-28 12:18:56,310 INFO L520 LassoAnalysis]: Termination argument consisting of: 54.07/20.06 Ranking function f(~d0_ev~0) = -1*~d0_ev~0 + 1 54.07/20.06 Supporting invariants [] 54.07/20.06 [2019-03-28 12:18:56,311 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed 54.07/20.06 [2019-03-28 12:18:56,336 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.06 [2019-03-28 12:18:56,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.06 [2019-03-28 12:18:56,371 INFO L256 TraceCheckSpWp]: Trace formula consists of 134 conjuncts, 2 conjunts are in the unsatisfiable core 54.07/20.06 [2019-03-28 12:18:56,374 INFO L279 TraceCheckSpWp]: Computing forward predicates... 54.07/20.06 [2019-03-28 12:18:56,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.06 [2019-03-28 12:18:56,401 INFO L256 TraceCheckSpWp]: Trace formula consists of 75 conjuncts, 4 conjunts are in the unsatisfiable core 54.07/20.06 [2019-03-28 12:18:56,402 INFO L279 TraceCheckSpWp]: Computing forward predicates... 54.07/20.06 [2019-03-28 12:18:56,437 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.06 [2019-03-28 12:18:56,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.06 [2019-03-28 12:18:56,471 INFO L256 TraceCheckSpWp]: Trace formula consists of 75 conjuncts, 2 conjunts are in the unsatisfiable core 54.07/20.06 [2019-03-28 12:18:56,472 INFO L279 TraceCheckSpWp]: Computing forward predicates... 54.07/20.06 [2019-03-28 12:18:56,514 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.06 [2019-03-28 12:18:56,515 INFO L256 TraceCheckSpWp]: Trace formula consists of 75 conjuncts, 2 conjunts are in the unsatisfiable core 54.07/20.06 [2019-03-28 12:18:56,517 INFO L279 TraceCheckSpWp]: Computing forward predicates... 54.07/20.06 [2019-03-28 12:18:56,520 INFO L98 LoopCannibalizer]: 3 predicates before loop cannibalization 6 predicates after loop cannibalization 54.07/20.06 [2019-03-28 12:18:56,524 INFO L152 lantAutomatonBouncer]: Defining Buchi interpolant automaton with scrooge nondeterminism in stemwith honda bouncer for stem and without honda bouncer for loop.1 stem predicates 6 loop predicates 54.07/20.06 [2019-03-28 12:18:56,525 INFO L69 BuchiDifferenceNCSB]: Start buchiDifferenceNCSB. First operand 2090 states and 3467 transitions. cyclomatic complexity: 1378 Second operand 5 states. 54.07/20.06 [2019-03-28 12:18:58,580 INFO L73 BuchiDifferenceNCSB]: Finished buchiDifferenceNCSB. First operand 2090 states and 3467 transitions. cyclomatic complexity: 1378. Second operand 5 states. Result 18554 states and 30561 transitions. Complement of second has 26 states. 54.07/20.06 [2019-03-28 12:18:58,581 INFO L142 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 16 states 1 stem states 10 non-accepting loop states 4 accepting loop states 54.07/20.06 [2019-03-28 12:18:58,581 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5 states. 54.07/20.06 [2019-03-28 12:18:58,584 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 1319 transitions. 54.07/20.06 [2019-03-28 12:18:58,586 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 16 states and 1319 transitions. Stem has 29 letters. Loop has 30 letters. 54.07/20.06 [2019-03-28 12:18:58,589 INFO L116 BuchiAccepts]: Finished buchiAccepts. 54.07/20.06 [2019-03-28 12:18:58,589 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 16 states and 1319 transitions. Stem has 59 letters. Loop has 30 letters. 54.07/20.06 [2019-03-28 12:18:58,590 INFO L116 BuchiAccepts]: Finished buchiAccepts. 54.07/20.06 [2019-03-28 12:18:58,590 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 16 states and 1319 transitions. Stem has 29 letters. Loop has 60 letters. 54.07/20.06 [2019-03-28 12:18:58,592 INFO L116 BuchiAccepts]: Finished buchiAccepts. 54.07/20.06 [2019-03-28 12:18:58,607 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18554 states and 30561 transitions. 54.07/20.06 [2019-03-28 12:18:58,715 INFO L131 ngComponentsAnalysis]: Automaton has 31 accepting balls. 5992 54.07/20.06 [2019-03-28 12:18:58,793 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18554 states to 11654 states and 18773 transitions. 54.07/20.06 [2019-03-28 12:18:58,793 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8218 54.07/20.06 [2019-03-28 12:18:58,805 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8310 54.07/20.06 [2019-03-28 12:18:58,806 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11654 states and 18773 transitions. 54.07/20.06 [2019-03-28 12:18:58,819 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. 54.07/20.06 [2019-03-28 12:18:58,819 INFO L706 BuchiCegarLoop]: Abstraction has 11654 states and 18773 transitions. 54.07/20.06 [2019-03-28 12:18:58,828 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11654 states and 18773 transitions. 54.07/20.06 [2019-03-28 12:18:59,010 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11654 to 8064. 54.07/20.06 [2019-03-28 12:18:59,010 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8064 states. 54.07/20.06 [2019-03-28 12:18:59,134 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8064 states to 8064 states and 13366 transitions. 54.07/20.06 [2019-03-28 12:18:59,134 INFO L729 BuchiCegarLoop]: Abstraction has 8064 states and 13366 transitions. 54.07/20.06 [2019-03-28 12:18:59,134 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 54.07/20.06 [2019-03-28 12:18:59,134 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 54.07/20.06 [2019-03-28 12:18:59,135 INFO L87 Difference]: Start difference. First operand 8064 states and 13366 transitions. Second operand 3 states. 54.07/20.06 [2019-03-28 12:18:59,287 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 54.07/20.06 [2019-03-28 12:18:59,288 INFO L93 Difference]: Finished difference Result 7422 states and 12215 transitions. 54.07/20.06 [2019-03-28 12:18:59,288 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 54.07/20.06 [2019-03-28 12:18:59,298 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7422 states and 12215 transitions. 54.07/20.06 [2019-03-28 12:18:59,337 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 4124 54.07/20.06 [2019-03-28 12:18:59,365 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7422 states to 7422 states and 12215 transitions. 54.07/20.06 [2019-03-28 12:18:59,365 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4910 54.07/20.06 [2019-03-28 12:18:59,370 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4910 54.07/20.06 [2019-03-28 12:18:59,371 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7422 states and 12215 transitions. 54.07/20.06 [2019-03-28 12:18:59,371 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. 54.07/20.06 [2019-03-28 12:18:59,371 INFO L706 BuchiCegarLoop]: Abstraction has 7422 states and 12215 transitions. 54.07/20.06 [2019-03-28 12:18:59,376 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7422 states and 12215 transitions. 54.07/20.06 [2019-03-28 12:18:59,492 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7422 to 7406. 54.07/20.06 [2019-03-28 12:18:59,493 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7406 states. 54.07/20.06 [2019-03-28 12:18:59,512 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7406 states to 7406 states and 12191 transitions. 54.07/20.06 [2019-03-28 12:18:59,512 INFO L729 BuchiCegarLoop]: Abstraction has 7406 states and 12191 transitions. 54.07/20.06 [2019-03-28 12:18:59,512 INFO L609 BuchiCegarLoop]: Abstraction has 7406 states and 12191 transitions. 54.07/20.06 [2019-03-28 12:18:59,512 INFO L442 BuchiCegarLoop]: ======== Iteration 27============ 54.07/20.06 [2019-03-28 12:18:59,513 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7406 states and 12191 transitions. 54.07/20.06 [2019-03-28 12:18:59,545 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 4124 54.07/20.06 [2019-03-28 12:18:59,545 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 54.07/20.06 [2019-03-28 12:18:59,545 INFO L119 BuchiIsEmpty]: Starting construction of run 54.07/20.06 [2019-03-28 12:18:59,546 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.06 [2019-03-28 12:18:59,546 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] 54.07/20.06 [2019-03-28 12:18:59,546 INFO L794 eck$LassoCheckResult]: Stem: 60298#ULTIMATE.startENTRY [885] ULTIMATE.startENTRY-->L202: Formula: (and (= v_~d0_ev~0_23 2) (= 0 v_~z_val~0_13) (= 2 v_~b1_ev~0_23) (= v_~d0_val_t~0_9 1) (= v_~b0_val~0_13 0) (= 1 v_~b1_val_t~0_9) (= 1 v_~d1_req_up~0_12) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_9 0) (= 2 v_~d1_ev~0_23) (= v_~b1_val~0_13 0) (= v_~b0_val_t~0_9 1) (= v_~b0_req_up~0_12 1) (= 0 v_~comp_m1_i~0_7) (= v_~d0_req_up~0_12 1) (= v_~comp_m1_st~0_15 0) (= v_~b0_ev~0_23 2) (= 1 v_~d1_val_t~0_9) (= v_~z_req_up~0_12 0) (= v_~z_val_t~0_10 0) (= 0 v_~d1_val~0_13) (= v_~z_ev~0_19 2) (= v_~b1_req_up~0_12 1) (= 0 v_~d0_val~0_13)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_4|, ~b1_val~0=v_~b1_val~0_13, ~b0_val~0=v_~b0_val~0_13, ~d0_req_up~0=v_~d0_req_up~0_12, ~d0_val~0=v_~d0_val~0_13, ~d1_val_t~0=v_~d1_val_t~0_9, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_9, ~d1_ev~0=v_~d1_ev~0_23, ~d1_val~0=v_~d1_val~0_13, ~b0_req_up~0=v_~b0_req_up~0_12, ~z_ev~0=v_~z_ev~0_19, ~b1_val_t~0=v_~b1_val_t~0_9, ~b1_ev~0=v_~b1_ev~0_23, ULTIMATE.start_main_~__retres1~2=v_ULTIMATE.start_main_~__retres1~2_6, ~z_val~0=v_~z_val~0_13, ~d1_req_up~0=v_~d1_req_up~0_12, ~z_val_t~0=v_~z_val_t~0_10, ~b0_val_t~0=v_~b0_val_t~0_9, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~z_req_up~0=v_~z_req_up~0_12, ~b1_req_up~0=v_~b1_req_up~0_12, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~d0_ev~0=v_~d0_ev~0_23, ~b0_ev~0=v_~b0_ev~0_23, ~d0_val_t~0=v_~d0_val_t~0_9, ~comp_m1_st~0=v_~comp_m1_st~0_15, ~comp_m1_i~0=v_~comp_m1_i~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ~b1_val~0, ~b0_val~0, ~d0_req_up~0, ~d0_val~0, ~d1_val_t~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~d1_ev~0, ~d1_val~0, ~b0_req_up~0, ~z_ev~0, ~b1_val_t~0, ~b1_ev~0, ULTIMATE.start_main_~__retres1~2, ~z_val~0, ~d1_req_up~0, ~z_val_t~0, ~b0_val_t~0, ULTIMATE.start_start_simulation_~tmp~3, ~z_req_up~0, ~b1_req_up~0, ULTIMATE.start_main_#res, ~d0_ev~0, ~b0_ev~0, ~d0_val_t~0, ~comp_m1_st~0, ~comp_m1_i~0] 60299#L202 [566] L202-->L127: Formula: (= 1 v_~b0_req_up~0_4) InVars {~b0_req_up~0=v_~b0_req_up~0_4} OutVars{~b0_req_up~0=v_~b0_req_up~0_4} AuxVars[] AssignedVars[] 60233#L127 [748] L127-->L127-2: Formula: (and (= v_~b0_val~0_3 v_~b0_val_t~0_3) (> v_~b0_val_t~0_3 v_~b0_val~0_4) (= v_~b0_ev~0_3 0)) InVars {~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_4} OutVars{~b0_ev~0=v_~b0_ev~0_3, ~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_3} AuxVars[] AssignedVars[~b0_val~0, ~b0_ev~0] 60234#L127-2 [580] L127-2-->L202-1: Formula: (= v_~b0_req_up~0_5 0) InVars {} OutVars{~b0_req_up~0=v_~b0_req_up~0_5} AuxVars[] AssignedVars[~b0_req_up~0] 60292#L202-1 [545] L202-1-->L142: Formula: (= 1 v_~b1_req_up~0_4) InVars {~b1_req_up~0=v_~b1_req_up~0_4} OutVars{~b1_req_up~0=v_~b1_req_up~0_4} AuxVars[] AssignedVars[] 60259#L142 [752] L142-->L142-2: Formula: (and (= v_~b1_ev~0_3 0) (< v_~b1_val~0_4 v_~b1_val_t~0_3) (= v_~b1_val~0_3 v_~b1_val_t~0_3)) InVars {~b1_val_t~0=v_~b1_val_t~0_3, ~b1_val~0=v_~b1_val~0_4} OutVars{~b1_val_t~0=v_~b1_val_t~0_3, ~b1_ev~0=v_~b1_ev~0_3, ~b1_val~0=v_~b1_val~0_3} AuxVars[] AssignedVars[~b1_val~0, ~b1_ev~0] 60249#L142-2 [521] L142-2-->L209: Formula: (= v_~b1_req_up~0_5 0) InVars {} OutVars{~b1_req_up~0=v_~b1_req_up~0_5} AuxVars[] AssignedVars[~b1_req_up~0] 60250#L209 [624] L209-->L157: Formula: (= v_~d0_req_up~0_4 1) InVars {~d0_req_up~0=v_~d0_req_up~0_4} OutVars{~d0_req_up~0=v_~d0_req_up~0_4} AuxVars[] AssignedVars[] 60207#L157 [757] L157-->L157-2: Formula: (and (> v_~d0_val_t~0_3 v_~d0_val~0_4) (= v_~d0_val~0_3 v_~d0_val_t~0_3) (= v_~d0_ev~0_3 0)) InVars {~d0_val~0=v_~d0_val~0_4, ~d0_val_t~0=v_~d0_val_t~0_3} OutVars{~d0_ev~0=v_~d0_ev~0_3, ~d0_val~0=v_~d0_val~0_3, ~d0_val_t~0=v_~d0_val_t~0_3} AuxVars[] AssignedVars[~d0_ev~0, ~d0_val~0] 60194#L157-2 [600] L157-2-->L216: Formula: (= v_~d0_req_up~0_5 0) InVars {} OutVars{~d0_req_up~0=v_~d0_req_up~0_5} AuxVars[] AssignedVars[~d0_req_up~0] 60195#L216 [554] L216-->L172: Formula: (= v_~d1_req_up~0_4 1) InVars {~d1_req_up~0=v_~d1_req_up~0_4} OutVars{~d1_req_up~0=v_~d1_req_up~0_4} AuxVars[] AssignedVars[] 60307#L172 [760] L172-->L172-2: Formula: (and (= v_~d1_val~0_3 v_~d1_val_t~0_3) (= v_~d1_ev~0_3 0) (> v_~d1_val_t~0_3 v_~d1_val~0_4)) InVars {~d1_val_t~0=v_~d1_val_t~0_3, ~d1_val~0=v_~d1_val~0_4} OutVars{~d1_val_t~0=v_~d1_val_t~0_3, ~d1_val~0=v_~d1_val~0_3, ~d1_ev~0=v_~d1_ev~0_3} AuxVars[] AssignedVars[~d1_val~0, ~d1_ev~0] 60297#L172-2 [547] L172-2-->L223: Formula: (= v_~d1_req_up~0_5 0) InVars {} OutVars{~d1_req_up~0=v_~d1_req_up~0_5} AuxVars[] AssignedVars[~d1_req_up~0] 60296#L223 [762] L223-->L230: Formula: (> 1 v_~z_req_up~0_6) InVars {~z_req_up~0=v_~z_req_up~0_6} OutVars{~z_req_up~0=v_~z_req_up~0_6} AuxVars[] AssignedVars[] 60196#L230 [767] L230-->L245-1: Formula: (and (> 1 v_~comp_m1_i~0_4) (= v_~comp_m1_st~0_5 2)) InVars {~comp_m1_i~0=v_~comp_m1_i~0_4} OutVars{~comp_m1_st~0=v_~comp_m1_st~0_5, ~comp_m1_i~0=v_~comp_m1_i~0_4} AuxVars[] AssignedVars[~comp_m1_st~0] 60197#L245-1 [608] L245-1-->L311-1: Formula: (and (= v_~b0_ev~0_5 1) (= v_~b0_ev~0_6 0)) InVars {~b0_ev~0=v_~b0_ev~0_6} OutVars{~b0_ev~0=v_~b0_ev~0_5} AuxVars[] AssignedVars[~b0_ev~0] 60227#L311-1 [628] L311-1-->L316-1: Formula: (and (= 0 v_~b1_ev~0_6) (= v_~b1_ev~0_5 1)) InVars {~b1_ev~0=v_~b1_ev~0_6} OutVars{~b1_ev~0=v_~b1_ev~0_5} AuxVars[] AssignedVars[~b1_ev~0] 60340#L316-1 [654] L316-1-->L321-1: Formula: (and (= v_~d0_ev~0_5 1) (= v_~d0_ev~0_6 0)) InVars {~d0_ev~0=v_~d0_ev~0_6} OutVars{~d0_ev~0=v_~d0_ev~0_5} AuxVars[] AssignedVars[~d0_ev~0] 60341#L321-1 [507] L321-1-->L326-1: Formula: (and (= 0 v_~d1_ev~0_6) (= v_~d1_ev~0_5 1)) InVars {~d1_ev~0=v_~d1_ev~0_6} OutVars{~d1_ev~0=v_~d1_ev~0_5} AuxVars[] AssignedVars[~d1_ev~0] 60317#L326-1 [776] L326-1-->L331-1: Formula: (< 0 v_~z_ev~0_7) InVars {~z_ev~0=v_~z_ev~0_7} OutVars{~z_ev~0=v_~z_ev~0_7} AuxVars[] AssignedVars[] 60318#L331-1 [583] L331-1-->L97: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_1|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 60362#L97 [591] L97-->L119: Formula: (and (= v_~b0_ev~0_11 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4 1)) InVars {~b0_ev~0=v_~b0_ev~0_11} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4, ~b0_ev~0=v_~b0_ev~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 60363#L119 [886] L119-->L380: Formula: (and (= |v_ULTIMATE.start_is_method1_triggered_#res_7| v_ULTIMATE.start_activate_threads_~tmp~1_13) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19 |v_ULTIMATE.start_is_method1_triggered_#res_7|)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_13, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_7|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_7|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 60255#L380 [785] L380-->L380-2: Formula: (and (= v_~comp_m1_st~0_6 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_8)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8, ~comp_m1_st~0=v_~comp_m1_st~0_6} AuxVars[] AssignedVars[~comp_m1_st~0] 60256#L380-2 [618] L380-2-->L344-1: Formula: (and (= v_~b0_ev~0_15 2) (= v_~b0_ev~0_16 1)) InVars {~b0_ev~0=v_~b0_ev~0_16} OutVars{~b0_ev~0=v_~b0_ev~0_15} AuxVars[] AssignedVars[~b0_ev~0] 60260#L344-1 [626] L344-1-->L349-1: Formula: (and (= 1 v_~b1_ev~0_16) (= v_~b1_ev~0_15 2)) InVars {~b1_ev~0=v_~b1_ev~0_16} OutVars{~b1_ev~0=v_~b1_ev~0_15} AuxVars[] AssignedVars[~b1_ev~0] 61438#L349-1 [652] L349-1-->L354-1: Formula: (and (= v_~d0_ev~0_15 2) (= v_~d0_ev~0_16 1)) InVars {~d0_ev~0=v_~d0_ev~0_16} OutVars{~d0_ev~0=v_~d0_ev~0_15} AuxVars[] AssignedVars[~d0_ev~0] 61436#L354-1 [502] L354-1-->L359-1: Formula: (and (= 1 v_~d1_ev~0_16) (= v_~d1_ev~0_15 2)) InVars {~d1_ev~0=v_~d1_ev~0_16} OutVars{~d1_ev~0=v_~d1_ev~0_15} AuxVars[] AssignedVars[~d1_ev~0] 61434#L359-1 [797] L359-1-->L422-1: Formula: (> v_~z_ev~0_13 1) InVars {~z_ev~0=v_~z_ev~0_13} OutVars{~z_ev~0=v_~z_ev~0_13} AuxVars[] AssignedVars[] 61429#L422-1 [887] L422-1-->L285: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 1) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 61430#L285 54.07/20.06 [2019-03-28 12:18:59,547 INFO L796 eck$LassoCheckResult]: Loop: 61430#L285 [888] L285-->L258: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_13, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res] 63087#L258 [803] L258-->L265: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8 0) (< 0 v_~comp_m1_st~0_9)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_9} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8, ~comp_m1_st~0=v_~comp_m1_st~0_9} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 63083#L265 [889] L265-->L280: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___0~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 63077#L280 [816] L280-->L280-1: Formula: (> v_ULTIMATE.start_eval_~tmp___0~0_4 0) InVars {ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_4} OutVars{ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_4} AuxVars[] AssignedVars[] 63072#L280-1 [822] L280-1-->L285: Formula: (< 0 v_~comp_m1_st~0_3) InVars {~comp_m1_st~0=v_~comp_m1_st~0_3} OutVars{~comp_m1_st~0=v_~comp_m1_st~0_3} AuxVars[] AssignedVars[] 61430#L285 54.07/20.06 [2019-03-28 12:18:59,547 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.06 [2019-03-28 12:18:59,547 INFO L82 PathProgramCache]: Analyzing trace with hash 1217900399, now seen corresponding path program 1 times 54.07/20.06 [2019-03-28 12:18:59,547 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.06 [2019-03-28 12:18:59,548 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.06 [2019-03-28 12:18:59,549 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:18:59,549 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:18:59,549 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:18:59,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 54.07/20.06 [2019-03-28 12:18:59,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 54.07/20.06 [2019-03-28 12:18:59,567 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.06 [2019-03-28 12:18:59,567 INFO L82 PathProgramCache]: Analyzing trace with hash 873518419, now seen corresponding path program 1 times 54.07/20.06 [2019-03-28 12:18:59,567 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.06 [2019-03-28 12:18:59,567 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.06 [2019-03-28 12:18:59,568 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:18:59,568 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:18:59,568 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:18:59,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.06 [2019-03-28 12:18:59,579 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.06 [2019-03-28 12:18:59,580 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.06 [2019-03-28 12:18:59,580 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 54.07/20.06 [2019-03-28 12:18:59,580 INFO L811 eck$LassoCheckResult]: loop already infeasible 54.07/20.06 [2019-03-28 12:18:59,580 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. 54.07/20.06 [2019-03-28 12:18:59,580 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 54.07/20.06 [2019-03-28 12:18:59,581 INFO L87 Difference]: Start difference. First operand 7406 states and 12191 transitions. cyclomatic complexity: 4804 Second operand 4 states. 54.07/20.06 [2019-03-28 12:18:59,910 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 54.07/20.06 [2019-03-28 12:18:59,910 INFO L93 Difference]: Finished difference Result 15414 states and 25683 transitions. 54.07/20.06 [2019-03-28 12:18:59,911 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. 54.07/20.06 [2019-03-28 12:18:59,919 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15414 states and 25683 transitions. 54.07/20.06 [2019-03-28 12:19:00,001 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 8668 54.07/20.06 [2019-03-28 12:19:00,054 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15414 states to 15414 states and 25683 transitions. 54.07/20.06 [2019-03-28 12:19:00,054 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10154 54.07/20.06 [2019-03-28 12:19:00,065 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10154 54.07/20.06 [2019-03-28 12:19:00,065 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15414 states and 25683 transitions. 54.07/20.06 [2019-03-28 12:19:00,065 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. 54.07/20.06 [2019-03-28 12:19:00,065 INFO L706 BuchiCegarLoop]: Abstraction has 15414 states and 25683 transitions. 54.07/20.06 [2019-03-28 12:19:00,077 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15414 states and 25683 transitions. 54.07/20.06 [2019-03-28 12:19:00,212 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15414 to 7534. 54.07/20.06 [2019-03-28 12:19:00,212 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7534 states. 54.07/20.06 [2019-03-28 12:19:00,231 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7534 states to 7534 states and 12383 transitions. 54.07/20.06 [2019-03-28 12:19:00,231 INFO L729 BuchiCegarLoop]: Abstraction has 7534 states and 12383 transitions. 54.07/20.06 [2019-03-28 12:19:00,231 INFO L609 BuchiCegarLoop]: Abstraction has 7534 states and 12383 transitions. 54.07/20.06 [2019-03-28 12:19:00,231 INFO L442 BuchiCegarLoop]: ======== Iteration 28============ 54.07/20.06 [2019-03-28 12:19:00,231 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7534 states and 12383 transitions. 54.07/20.06 [2019-03-28 12:19:00,260 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 4204 54.07/20.06 [2019-03-28 12:19:00,260 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 54.07/20.06 [2019-03-28 12:19:00,260 INFO L119 BuchiIsEmpty]: Starting construction of run 54.07/20.06 [2019-03-28 12:19:00,261 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.06 [2019-03-28 12:19:00,261 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] 54.07/20.06 [2019-03-28 12:19:00,262 INFO L794 eck$LassoCheckResult]: Stem: 83125#ULTIMATE.startENTRY [885] ULTIMATE.startENTRY-->L202: Formula: (and (= v_~d0_ev~0_23 2) (= 0 v_~z_val~0_13) (= 2 v_~b1_ev~0_23) (= v_~d0_val_t~0_9 1) (= v_~b0_val~0_13 0) (= 1 v_~b1_val_t~0_9) (= 1 v_~d1_req_up~0_12) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_9 0) (= 2 v_~d1_ev~0_23) (= v_~b1_val~0_13 0) (= v_~b0_val_t~0_9 1) (= v_~b0_req_up~0_12 1) (= 0 v_~comp_m1_i~0_7) (= v_~d0_req_up~0_12 1) (= v_~comp_m1_st~0_15 0) (= v_~b0_ev~0_23 2) (= 1 v_~d1_val_t~0_9) (= v_~z_req_up~0_12 0) (= v_~z_val_t~0_10 0) (= 0 v_~d1_val~0_13) (= v_~z_ev~0_19 2) (= v_~b1_req_up~0_12 1) (= 0 v_~d0_val~0_13)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_4|, ~b1_val~0=v_~b1_val~0_13, ~b0_val~0=v_~b0_val~0_13, ~d0_req_up~0=v_~d0_req_up~0_12, ~d0_val~0=v_~d0_val~0_13, ~d1_val_t~0=v_~d1_val_t~0_9, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_9, ~d1_ev~0=v_~d1_ev~0_23, ~d1_val~0=v_~d1_val~0_13, ~b0_req_up~0=v_~b0_req_up~0_12, ~z_ev~0=v_~z_ev~0_19, ~b1_val_t~0=v_~b1_val_t~0_9, ~b1_ev~0=v_~b1_ev~0_23, ULTIMATE.start_main_~__retres1~2=v_ULTIMATE.start_main_~__retres1~2_6, ~z_val~0=v_~z_val~0_13, ~d1_req_up~0=v_~d1_req_up~0_12, ~z_val_t~0=v_~z_val_t~0_10, ~b0_val_t~0=v_~b0_val_t~0_9, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~z_req_up~0=v_~z_req_up~0_12, ~b1_req_up~0=v_~b1_req_up~0_12, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~d0_ev~0=v_~d0_ev~0_23, ~b0_ev~0=v_~b0_ev~0_23, ~d0_val_t~0=v_~d0_val_t~0_9, ~comp_m1_st~0=v_~comp_m1_st~0_15, ~comp_m1_i~0=v_~comp_m1_i~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ~b1_val~0, ~b0_val~0, ~d0_req_up~0, ~d0_val~0, ~d1_val_t~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~d1_ev~0, ~d1_val~0, ~b0_req_up~0, ~z_ev~0, ~b1_val_t~0, ~b1_ev~0, ULTIMATE.start_main_~__retres1~2, ~z_val~0, ~d1_req_up~0, ~z_val_t~0, ~b0_val_t~0, ULTIMATE.start_start_simulation_~tmp~3, ~z_req_up~0, ~b1_req_up~0, ULTIMATE.start_main_#res, ~d0_ev~0, ~b0_ev~0, ~d0_val_t~0, ~comp_m1_st~0, ~comp_m1_i~0] 83126#L202 [566] L202-->L127: Formula: (= 1 v_~b0_req_up~0_4) InVars {~b0_req_up~0=v_~b0_req_up~0_4} OutVars{~b0_req_up~0=v_~b0_req_up~0_4} AuxVars[] AssignedVars[] 83061#L127 [748] L127-->L127-2: Formula: (and (= v_~b0_val~0_3 v_~b0_val_t~0_3) (> v_~b0_val_t~0_3 v_~b0_val~0_4) (= v_~b0_ev~0_3 0)) InVars {~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_4} OutVars{~b0_ev~0=v_~b0_ev~0_3, ~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_3} AuxVars[] AssignedVars[~b0_val~0, ~b0_ev~0] 83062#L127-2 [580] L127-2-->L202-1: Formula: (= v_~b0_req_up~0_5 0) InVars {} OutVars{~b0_req_up~0=v_~b0_req_up~0_5} AuxVars[] AssignedVars[~b0_req_up~0] 83120#L202-1 [545] L202-1-->L142: Formula: (= 1 v_~b1_req_up~0_4) InVars {~b1_req_up~0=v_~b1_req_up~0_4} OutVars{~b1_req_up~0=v_~b1_req_up~0_4} AuxVars[] AssignedVars[] 83087#L142 [752] L142-->L142-2: Formula: (and (= v_~b1_ev~0_3 0) (< v_~b1_val~0_4 v_~b1_val_t~0_3) (= v_~b1_val~0_3 v_~b1_val_t~0_3)) InVars {~b1_val_t~0=v_~b1_val_t~0_3, ~b1_val~0=v_~b1_val~0_4} OutVars{~b1_val_t~0=v_~b1_val_t~0_3, ~b1_ev~0=v_~b1_ev~0_3, ~b1_val~0=v_~b1_val~0_3} AuxVars[] AssignedVars[~b1_val~0, ~b1_ev~0] 83077#L142-2 [521] L142-2-->L209: Formula: (= v_~b1_req_up~0_5 0) InVars {} OutVars{~b1_req_up~0=v_~b1_req_up~0_5} AuxVars[] AssignedVars[~b1_req_up~0] 83078#L209 [624] L209-->L157: Formula: (= v_~d0_req_up~0_4 1) InVars {~d0_req_up~0=v_~d0_req_up~0_4} OutVars{~d0_req_up~0=v_~d0_req_up~0_4} AuxVars[] AssignedVars[] 83036#L157 [757] L157-->L157-2: Formula: (and (> v_~d0_val_t~0_3 v_~d0_val~0_4) (= v_~d0_val~0_3 v_~d0_val_t~0_3) (= v_~d0_ev~0_3 0)) InVars {~d0_val~0=v_~d0_val~0_4, ~d0_val_t~0=v_~d0_val_t~0_3} OutVars{~d0_ev~0=v_~d0_ev~0_3, ~d0_val~0=v_~d0_val~0_3, ~d0_val_t~0=v_~d0_val_t~0_3} AuxVars[] AssignedVars[~d0_ev~0, ~d0_val~0] 83023#L157-2 [600] L157-2-->L216: Formula: (= v_~d0_req_up~0_5 0) InVars {} OutVars{~d0_req_up~0=v_~d0_req_up~0_5} AuxVars[] AssignedVars[~d0_req_up~0] 83024#L216 [554] L216-->L172: Formula: (= v_~d1_req_up~0_4 1) InVars {~d1_req_up~0=v_~d1_req_up~0_4} OutVars{~d1_req_up~0=v_~d1_req_up~0_4} AuxVars[] AssignedVars[] 83134#L172 [760] L172-->L172-2: Formula: (and (= v_~d1_val~0_3 v_~d1_val_t~0_3) (= v_~d1_ev~0_3 0) (> v_~d1_val_t~0_3 v_~d1_val~0_4)) InVars {~d1_val_t~0=v_~d1_val_t~0_3, ~d1_val~0=v_~d1_val~0_4} OutVars{~d1_val_t~0=v_~d1_val_t~0_3, ~d1_val~0=v_~d1_val~0_3, ~d1_ev~0=v_~d1_ev~0_3} AuxVars[] AssignedVars[~d1_val~0, ~d1_ev~0] 83124#L172-2 [547] L172-2-->L223: Formula: (= v_~d1_req_up~0_5 0) InVars {} OutVars{~d1_req_up~0=v_~d1_req_up~0_5} AuxVars[] AssignedVars[~d1_req_up~0] 83123#L223 [762] L223-->L230: Formula: (> 1 v_~z_req_up~0_6) InVars {~z_req_up~0=v_~z_req_up~0_6} OutVars{~z_req_up~0=v_~z_req_up~0_6} AuxVars[] AssignedVars[] 83025#L230 [767] L230-->L245-1: Formula: (and (> 1 v_~comp_m1_i~0_4) (= v_~comp_m1_st~0_5 2)) InVars {~comp_m1_i~0=v_~comp_m1_i~0_4} OutVars{~comp_m1_st~0=v_~comp_m1_st~0_5, ~comp_m1_i~0=v_~comp_m1_i~0_4} AuxVars[] AssignedVars[~comp_m1_st~0] 83026#L245-1 [608] L245-1-->L311-1: Formula: (and (= v_~b0_ev~0_5 1) (= v_~b0_ev~0_6 0)) InVars {~b0_ev~0=v_~b0_ev~0_6} OutVars{~b0_ev~0=v_~b0_ev~0_5} AuxVars[] AssignedVars[~b0_ev~0] 83055#L311-1 [628] L311-1-->L316-1: Formula: (and (= 0 v_~b1_ev~0_6) (= v_~b1_ev~0_5 1)) InVars {~b1_ev~0=v_~b1_ev~0_6} OutVars{~b1_ev~0=v_~b1_ev~0_5} AuxVars[] AssignedVars[~b1_ev~0] 83165#L316-1 [654] L316-1-->L321-1: Formula: (and (= v_~d0_ev~0_5 1) (= v_~d0_ev~0_6 0)) InVars {~d0_ev~0=v_~d0_ev~0_6} OutVars{~d0_ev~0=v_~d0_ev~0_5} AuxVars[] AssignedVars[~d0_ev~0] 83166#L321-1 [507] L321-1-->L326-1: Formula: (and (= 0 v_~d1_ev~0_6) (= v_~d1_ev~0_5 1)) InVars {~d1_ev~0=v_~d1_ev~0_6} OutVars{~d1_ev~0=v_~d1_ev~0_5} AuxVars[] AssignedVars[~d1_ev~0] 83142#L326-1 [776] L326-1-->L331-1: Formula: (< 0 v_~z_ev~0_7) InVars {~z_ev~0=v_~z_ev~0_7} OutVars{~z_ev~0=v_~z_ev~0_7} AuxVars[] AssignedVars[] 83143#L331-1 [583] L331-1-->L97: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_1|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 83190#L97 [591] L97-->L119: Formula: (and (= v_~b0_ev~0_11 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4 1)) InVars {~b0_ev~0=v_~b0_ev~0_11} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4, ~b0_ev~0=v_~b0_ev~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 83191#L119 [886] L119-->L380: Formula: (and (= |v_ULTIMATE.start_is_method1_triggered_#res_7| v_ULTIMATE.start_activate_threads_~tmp~1_13) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19 |v_ULTIMATE.start_is_method1_triggered_#res_7|)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_13, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_7|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_7|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 83083#L380 [785] L380-->L380-2: Formula: (and (= v_~comp_m1_st~0_6 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_8)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8, ~comp_m1_st~0=v_~comp_m1_st~0_6} AuxVars[] AssignedVars[~comp_m1_st~0] 83084#L380-2 [618] L380-2-->L344-1: Formula: (and (= v_~b0_ev~0_15 2) (= v_~b0_ev~0_16 1)) InVars {~b0_ev~0=v_~b0_ev~0_16} OutVars{~b0_ev~0=v_~b0_ev~0_15} AuxVars[] AssignedVars[~b0_ev~0] 83088#L344-1 [626] L344-1-->L349-1: Formula: (and (= 1 v_~b1_ev~0_16) (= v_~b1_ev~0_15 2)) InVars {~b1_ev~0=v_~b1_ev~0_16} OutVars{~b1_ev~0=v_~b1_ev~0_15} AuxVars[] AssignedVars[~b1_ev~0] 83103#L349-1 [652] L349-1-->L354-1: Formula: (and (= v_~d0_ev~0_15 2) (= v_~d0_ev~0_16 1)) InVars {~d0_ev~0=v_~d0_ev~0_16} OutVars{~d0_ev~0=v_~d0_ev~0_15} AuxVars[] AssignedVars[~d0_ev~0] 84234#L354-1 [502] L354-1-->L359-1: Formula: (and (= 1 v_~d1_ev~0_16) (= v_~d1_ev~0_15 2)) InVars {~d1_ev~0=v_~d1_ev~0_16} OutVars{~d1_ev~0=v_~d1_ev~0_15} AuxVars[] AssignedVars[~d1_ev~0] 84233#L359-1 [797] L359-1-->L422-1: Formula: (> v_~z_ev~0_13 1) InVars {~z_ev~0=v_~z_ev~0_13} OutVars{~z_ev~0=v_~z_ev~0_13} AuxVars[] AssignedVars[] 84231#L422-1 [887] L422-1-->L285: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 1) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 84232#L285 54.07/20.06 [2019-03-28 12:19:00,262 INFO L796 eck$LassoCheckResult]: Loop: 84232#L285 [888] L285-->L258: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_13, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res] 88680#L258 [803] L258-->L265: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8 0) (< 0 v_~comp_m1_st~0_9)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_9} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_8, ~comp_m1_st~0=v_~comp_m1_st~0_9} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 88679#L265 [889] L265-->L280: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___0~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 88536#L280 [817] L280-->L280-1: Formula: (< v_ULTIMATE.start_eval_~tmp___0~0_4 0) InVars {ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_4} OutVars{ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_4} AuxVars[] AssignedVars[] 88537#L280-1 [822] L280-1-->L285: Formula: (< 0 v_~comp_m1_st~0_3) InVars {~comp_m1_st~0=v_~comp_m1_st~0_3} OutVars{~comp_m1_st~0=v_~comp_m1_st~0_3} AuxVars[] AssignedVars[] 84232#L285 54.07/20.06 [2019-03-28 12:19:00,262 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.06 [2019-03-28 12:19:00,262 INFO L82 PathProgramCache]: Analyzing trace with hash 1217900399, now seen corresponding path program 2 times 54.07/20.06 [2019-03-28 12:19:00,262 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.06 [2019-03-28 12:19:00,263 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.06 [2019-03-28 12:19:00,263 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:19:00,263 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:19:00,264 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:19:00,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 54.07/20.06 [2019-03-28 12:19:00,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 54.07/20.06 [2019-03-28 12:19:00,280 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.06 [2019-03-28 12:19:00,280 INFO L82 PathProgramCache]: Analyzing trace with hash 873518450, now seen corresponding path program 1 times 54.07/20.06 [2019-03-28 12:19:00,280 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.06 [2019-03-28 12:19:00,280 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.06 [2019-03-28 12:19:00,281 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:19:00,281 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:19:00,281 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:19:00,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.06 [2019-03-28 12:19:00,296 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.06 [2019-03-28 12:19:00,296 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.06 [2019-03-28 12:19:00,296 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 54.07/20.06 [2019-03-28 12:19:00,297 INFO L811 eck$LassoCheckResult]: loop already infeasible 54.07/20.06 [2019-03-28 12:19:00,297 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. 54.07/20.06 [2019-03-28 12:19:00,297 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 54.07/20.06 [2019-03-28 12:19:00,297 INFO L87 Difference]: Start difference. First operand 7534 states and 12383 transitions. cyclomatic complexity: 4868 Second operand 4 states. 54.07/20.06 [2019-03-28 12:19:00,464 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 54.07/20.06 [2019-03-28 12:19:00,464 INFO L93 Difference]: Finished difference Result 7758 states and 12535 transitions. 54.07/20.06 [2019-03-28 12:19:00,466 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. 54.07/20.06 [2019-03-28 12:19:00,475 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7758 states and 12535 transitions. 54.07/20.06 [2019-03-28 12:19:00,510 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 4316 54.07/20.06 [2019-03-28 12:19:00,541 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7758 states to 7758 states and 12535 transitions. 54.07/20.06 [2019-03-28 12:19:00,542 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5126 54.07/20.06 [2019-03-28 12:19:00,546 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5126 54.07/20.06 [2019-03-28 12:19:00,546 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7758 states and 12535 transitions. 54.07/20.06 [2019-03-28 12:19:00,546 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. 54.07/20.06 [2019-03-28 12:19:00,547 INFO L706 BuchiCegarLoop]: Abstraction has 7758 states and 12535 transitions. 54.07/20.06 [2019-03-28 12:19:00,552 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7758 states and 12535 transitions. 54.07/20.06 [2019-03-28 12:19:00,752 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7758 to 7534. 54.07/20.06 [2019-03-28 12:19:00,752 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7534 states. 54.07/20.06 [2019-03-28 12:19:00,770 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7534 states to 7534 states and 12255 transitions. 54.07/20.06 [2019-03-28 12:19:00,770 INFO L729 BuchiCegarLoop]: Abstraction has 7534 states and 12255 transitions. 54.07/20.06 [2019-03-28 12:19:00,770 INFO L609 BuchiCegarLoop]: Abstraction has 7534 states and 12255 transitions. 54.07/20.06 [2019-03-28 12:19:00,771 INFO L442 BuchiCegarLoop]: ======== Iteration 29============ 54.07/20.06 [2019-03-28 12:19:00,771 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7534 states and 12255 transitions. 54.07/20.06 [2019-03-28 12:19:00,795 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 4188 54.07/20.06 [2019-03-28 12:19:00,795 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 54.07/20.06 [2019-03-28 12:19:00,795 INFO L119 BuchiIsEmpty]: Starting construction of run 54.07/20.06 [2019-03-28 12:19:00,795 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.06 [2019-03-28 12:19:00,796 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] 54.07/20.06 [2019-03-28 12:19:00,796 INFO L794 eck$LassoCheckResult]: Stem: 98437#ULTIMATE.startENTRY [885] ULTIMATE.startENTRY-->L202: Formula: (and (= v_~d0_ev~0_23 2) (= 0 v_~z_val~0_13) (= 2 v_~b1_ev~0_23) (= v_~d0_val_t~0_9 1) (= v_~b0_val~0_13 0) (= 1 v_~b1_val_t~0_9) (= 1 v_~d1_req_up~0_12) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_9 0) (= 2 v_~d1_ev~0_23) (= v_~b1_val~0_13 0) (= v_~b0_val_t~0_9 1) (= v_~b0_req_up~0_12 1) (= 0 v_~comp_m1_i~0_7) (= v_~d0_req_up~0_12 1) (= v_~comp_m1_st~0_15 0) (= v_~b0_ev~0_23 2) (= 1 v_~d1_val_t~0_9) (= v_~z_req_up~0_12 0) (= v_~z_val_t~0_10 0) (= 0 v_~d1_val~0_13) (= v_~z_ev~0_19 2) (= v_~b1_req_up~0_12 1) (= 0 v_~d0_val~0_13)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_4|, ~b1_val~0=v_~b1_val~0_13, ~b0_val~0=v_~b0_val~0_13, ~d0_req_up~0=v_~d0_req_up~0_12, ~d0_val~0=v_~d0_val~0_13, ~d1_val_t~0=v_~d1_val_t~0_9, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_9, ~d1_ev~0=v_~d1_ev~0_23, ~d1_val~0=v_~d1_val~0_13, ~b0_req_up~0=v_~b0_req_up~0_12, ~z_ev~0=v_~z_ev~0_19, ~b1_val_t~0=v_~b1_val_t~0_9, ~b1_ev~0=v_~b1_ev~0_23, ULTIMATE.start_main_~__retres1~2=v_ULTIMATE.start_main_~__retres1~2_6, ~z_val~0=v_~z_val~0_13, ~d1_req_up~0=v_~d1_req_up~0_12, ~z_val_t~0=v_~z_val_t~0_10, ~b0_val_t~0=v_~b0_val_t~0_9, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~z_req_up~0=v_~z_req_up~0_12, ~b1_req_up~0=v_~b1_req_up~0_12, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~d0_ev~0=v_~d0_ev~0_23, ~b0_ev~0=v_~b0_ev~0_23, ~d0_val_t~0=v_~d0_val_t~0_9, ~comp_m1_st~0=v_~comp_m1_st~0_15, ~comp_m1_i~0=v_~comp_m1_i~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ~b1_val~0, ~b0_val~0, ~d0_req_up~0, ~d0_val~0, ~d1_val_t~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~d1_ev~0, ~d1_val~0, ~b0_req_up~0, ~z_ev~0, ~b1_val_t~0, ~b1_ev~0, ULTIMATE.start_main_~__retres1~2, ~z_val~0, ~d1_req_up~0, ~z_val_t~0, ~b0_val_t~0, ULTIMATE.start_start_simulation_~tmp~3, ~z_req_up~0, ~b1_req_up~0, ULTIMATE.start_main_#res, ~d0_ev~0, ~b0_ev~0, ~d0_val_t~0, ~comp_m1_st~0, ~comp_m1_i~0] 98438#L202 [566] L202-->L127: Formula: (= 1 v_~b0_req_up~0_4) InVars {~b0_req_up~0=v_~b0_req_up~0_4} OutVars{~b0_req_up~0=v_~b0_req_up~0_4} AuxVars[] AssignedVars[] 98363#L127 [748] L127-->L127-2: Formula: (and (= v_~b0_val~0_3 v_~b0_val_t~0_3) (> v_~b0_val_t~0_3 v_~b0_val~0_4) (= v_~b0_ev~0_3 0)) InVars {~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_4} OutVars{~b0_ev~0=v_~b0_ev~0_3, ~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_3} AuxVars[] AssignedVars[~b0_val~0, ~b0_ev~0] 98364#L127-2 [580] L127-2-->L202-1: Formula: (= v_~b0_req_up~0_5 0) InVars {} OutVars{~b0_req_up~0=v_~b0_req_up~0_5} AuxVars[] AssignedVars[~b0_req_up~0] 98431#L202-1 [545] L202-1-->L142: Formula: (= 1 v_~b1_req_up~0_4) InVars {~b1_req_up~0=v_~b1_req_up~0_4} OutVars{~b1_req_up~0=v_~b1_req_up~0_4} AuxVars[] AssignedVars[] 98391#L142 [752] L142-->L142-2: Formula: (and (= v_~b1_ev~0_3 0) (< v_~b1_val~0_4 v_~b1_val_t~0_3) (= v_~b1_val~0_3 v_~b1_val_t~0_3)) InVars {~b1_val_t~0=v_~b1_val_t~0_3, ~b1_val~0=v_~b1_val~0_4} OutVars{~b1_val_t~0=v_~b1_val_t~0_3, ~b1_ev~0=v_~b1_ev~0_3, ~b1_val~0=v_~b1_val~0_3} AuxVars[] AssignedVars[~b1_val~0, ~b1_ev~0] 98379#L142-2 [521] L142-2-->L209: Formula: (= v_~b1_req_up~0_5 0) InVars {} OutVars{~b1_req_up~0=v_~b1_req_up~0_5} AuxVars[] AssignedVars[~b1_req_up~0] 98380#L209 [624] L209-->L157: Formula: (= v_~d0_req_up~0_4 1) InVars {~d0_req_up~0=v_~d0_req_up~0_4} OutVars{~d0_req_up~0=v_~d0_req_up~0_4} AuxVars[] AssignedVars[] 98337#L157 [757] L157-->L157-2: Formula: (and (> v_~d0_val_t~0_3 v_~d0_val~0_4) (= v_~d0_val~0_3 v_~d0_val_t~0_3) (= v_~d0_ev~0_3 0)) InVars {~d0_val~0=v_~d0_val~0_4, ~d0_val_t~0=v_~d0_val_t~0_3} OutVars{~d0_ev~0=v_~d0_ev~0_3, ~d0_val~0=v_~d0_val~0_3, ~d0_val_t~0=v_~d0_val_t~0_3} AuxVars[] AssignedVars[~d0_ev~0, ~d0_val~0] 98324#L157-2 [600] L157-2-->L216: Formula: (= v_~d0_req_up~0_5 0) InVars {} OutVars{~d0_req_up~0=v_~d0_req_up~0_5} AuxVars[] AssignedVars[~d0_req_up~0] 98325#L216 [554] L216-->L172: Formula: (= v_~d1_req_up~0_4 1) InVars {~d1_req_up~0=v_~d1_req_up~0_4} OutVars{~d1_req_up~0=v_~d1_req_up~0_4} AuxVars[] AssignedVars[] 98447#L172 [760] L172-->L172-2: Formula: (and (= v_~d1_val~0_3 v_~d1_val_t~0_3) (= v_~d1_ev~0_3 0) (> v_~d1_val_t~0_3 v_~d1_val~0_4)) InVars {~d1_val_t~0=v_~d1_val_t~0_3, ~d1_val~0=v_~d1_val~0_4} OutVars{~d1_val_t~0=v_~d1_val_t~0_3, ~d1_val~0=v_~d1_val~0_3, ~d1_ev~0=v_~d1_ev~0_3} AuxVars[] AssignedVars[~d1_val~0, ~d1_ev~0] 98436#L172-2 [547] L172-2-->L223: Formula: (= v_~d1_req_up~0_5 0) InVars {} OutVars{~d1_req_up~0=v_~d1_req_up~0_5} AuxVars[] AssignedVars[~d1_req_up~0] 98435#L223 [762] L223-->L230: Formula: (> 1 v_~z_req_up~0_6) InVars {~z_req_up~0=v_~z_req_up~0_6} OutVars{~z_req_up~0=v_~z_req_up~0_6} AuxVars[] AssignedVars[] 98326#L230 [767] L230-->L245-1: Formula: (and (> 1 v_~comp_m1_i~0_4) (= v_~comp_m1_st~0_5 2)) InVars {~comp_m1_i~0=v_~comp_m1_i~0_4} OutVars{~comp_m1_st~0=v_~comp_m1_st~0_5, ~comp_m1_i~0=v_~comp_m1_i~0_4} AuxVars[] AssignedVars[~comp_m1_st~0] 98327#L245-1 [608] L245-1-->L311-1: Formula: (and (= v_~b0_ev~0_5 1) (= v_~b0_ev~0_6 0)) InVars {~b0_ev~0=v_~b0_ev~0_6} OutVars{~b0_ev~0=v_~b0_ev~0_5} AuxVars[] AssignedVars[~b0_ev~0] 98357#L311-1 [628] L311-1-->L316-1: Formula: (and (= 0 v_~b1_ev~0_6) (= v_~b1_ev~0_5 1)) InVars {~b1_ev~0=v_~b1_ev~0_6} OutVars{~b1_ev~0=v_~b1_ev~0_5} AuxVars[] AssignedVars[~b1_ev~0] 98480#L316-1 [654] L316-1-->L321-1: Formula: (and (= v_~d0_ev~0_5 1) (= v_~d0_ev~0_6 0)) InVars {~d0_ev~0=v_~d0_ev~0_6} OutVars{~d0_ev~0=v_~d0_ev~0_5} AuxVars[] AssignedVars[~d0_ev~0] 98481#L321-1 [507] L321-1-->L326-1: Formula: (and (= 0 v_~d1_ev~0_6) (= v_~d1_ev~0_5 1)) InVars {~d1_ev~0=v_~d1_ev~0_6} OutVars{~d1_ev~0=v_~d1_ev~0_5} AuxVars[] AssignedVars[~d1_ev~0] 98456#L326-1 [776] L326-1-->L331-1: Formula: (< 0 v_~z_ev~0_7) InVars {~z_ev~0=v_~z_ev~0_7} OutVars{~z_ev~0=v_~z_ev~0_7} AuxVars[] AssignedVars[] 98457#L331-1 [583] L331-1-->L97: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_1|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 98499#L97 [591] L97-->L119: Formula: (and (= v_~b0_ev~0_11 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4 1)) InVars {~b0_ev~0=v_~b0_ev~0_11} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4, ~b0_ev~0=v_~b0_ev~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 98500#L119 [886] L119-->L380: Formula: (and (= |v_ULTIMATE.start_is_method1_triggered_#res_7| v_ULTIMATE.start_activate_threads_~tmp~1_13) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19 |v_ULTIMATE.start_is_method1_triggered_#res_7|)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_13, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_7|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_7|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 98385#L380 [785] L380-->L380-2: Formula: (and (= v_~comp_m1_st~0_6 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_8)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8, ~comp_m1_st~0=v_~comp_m1_st~0_6} AuxVars[] AssignedVars[~comp_m1_st~0] 98386#L380-2 [618] L380-2-->L344-1: Formula: (and (= v_~b0_ev~0_15 2) (= v_~b0_ev~0_16 1)) InVars {~b0_ev~0=v_~b0_ev~0_16} OutVars{~b0_ev~0=v_~b0_ev~0_15} AuxVars[] AssignedVars[~b0_ev~0] 98392#L344-1 [626] L344-1-->L349-1: Formula: (and (= 1 v_~b1_ev~0_16) (= v_~b1_ev~0_15 2)) InVars {~b1_ev~0=v_~b1_ev~0_16} OutVars{~b1_ev~0=v_~b1_ev~0_15} AuxVars[] AssignedVars[~b1_ev~0] 98517#L349-1 [652] L349-1-->L354-1: Formula: (and (= v_~d0_ev~0_15 2) (= v_~d0_ev~0_16 1)) InVars {~d0_ev~0=v_~d0_ev~0_16} OutVars{~d0_ev~0=v_~d0_ev~0_15} AuxVars[] AssignedVars[~d0_ev~0] 98518#L354-1 [502] L354-1-->L359-1: Formula: (and (= 1 v_~d1_ev~0_16) (= v_~d1_ev~0_15 2)) InVars {~d1_ev~0=v_~d1_ev~0_16} OutVars{~d1_ev~0=v_~d1_ev~0_15} AuxVars[] AssignedVars[~d1_ev~0] 98989#L359-1 [797] L359-1-->L422-1: Formula: (> v_~z_ev~0_13 1) InVars {~z_ev~0=v_~z_ev~0_13} OutVars{~z_ev~0=v_~z_ev~0_13} AuxVars[] AssignedVars[] 98987#L422-1 [887] L422-1-->L285: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 1) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 98988#L285 54.07/20.06 [2019-03-28 12:19:00,797 INFO L796 eck$LassoCheckResult]: Loop: 98988#L285 [888] L285-->L258: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_13, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res] 102774#L258 [671] L258-->L265: Formula: (and (= 0 v_~comp_m1_st~0_8) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_4 1)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_4, ~comp_m1_st~0=v_~comp_m1_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 102769#L265 [889] L265-->L280: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___0~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 102767#L280 [816] L280-->L280-1: Formula: (> v_ULTIMATE.start_eval_~tmp___0~0_4 0) InVars {ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_4} OutVars{ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_4} AuxVars[] AssignedVars[] 102766#L280-1 [822] L280-1-->L285: Formula: (< 0 v_~comp_m1_st~0_3) InVars {~comp_m1_st~0=v_~comp_m1_st~0_3} OutVars{~comp_m1_st~0=v_~comp_m1_st~0_3} AuxVars[] AssignedVars[] 98988#L285 54.07/20.06 [2019-03-28 12:19:00,797 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.06 [2019-03-28 12:19:00,797 INFO L82 PathProgramCache]: Analyzing trace with hash 1217900399, now seen corresponding path program 3 times 54.07/20.06 [2019-03-28 12:19:00,797 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.06 [2019-03-28 12:19:00,797 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.06 [2019-03-28 12:19:00,798 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:19:00,798 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:19:00,798 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:19:00,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 54.07/20.06 [2019-03-28 12:19:00,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 54.07/20.06 [2019-03-28 12:19:00,813 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.06 [2019-03-28 12:19:00,813 INFO L82 PathProgramCache]: Analyzing trace with hash 869586007, now seen corresponding path program 1 times 54.07/20.06 [2019-03-28 12:19:00,813 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.06 [2019-03-28 12:19:00,814 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.06 [2019-03-28 12:19:00,814 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:19:00,814 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:19:00,815 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:19:00,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 54.07/20.06 [2019-03-28 12:19:00,821 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 54.07/20.06 [2019-03-28 12:19:00,821 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 54.07/20.06 [2019-03-28 12:19:00,822 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 54.07/20.06 [2019-03-28 12:19:00,822 INFO L811 eck$LassoCheckResult]: loop already infeasible 54.07/20.06 [2019-03-28 12:19:00,822 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 54.07/20.06 [2019-03-28 12:19:00,822 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 54.07/20.06 [2019-03-28 12:19:00,823 INFO L87 Difference]: Start difference. First operand 7534 states and 12255 transitions. cyclomatic complexity: 4740 Second operand 3 states. 54.07/20.06 [2019-03-28 12:19:01,035 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 54.07/20.06 [2019-03-28 12:19:01,036 INFO L93 Difference]: Finished difference Result 13493 states and 21501 transitions. 54.07/20.06 [2019-03-28 12:19:01,036 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 54.07/20.06 [2019-03-28 12:19:01,045 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13493 states and 21501 transitions. 54.07/20.06 [2019-03-28 12:19:01,101 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 7604 54.07/20.06 [2019-03-28 12:19:01,147 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13493 states to 13493 states and 21501 transitions. 54.07/20.06 [2019-03-28 12:19:01,147 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8961 54.07/20.06 [2019-03-28 12:19:01,154 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8961 54.07/20.06 [2019-03-28 12:19:01,155 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13493 states and 21501 transitions. 54.07/20.06 [2019-03-28 12:19:01,155 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. 54.07/20.06 [2019-03-28 12:19:01,155 INFO L706 BuchiCegarLoop]: Abstraction has 13493 states and 21501 transitions. 54.07/20.06 [2019-03-28 12:19:01,163 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13493 states and 21501 transitions. 54.07/20.06 [2019-03-28 12:19:01,284 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13493 to 9650. 54.07/20.06 [2019-03-28 12:19:01,284 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9650 states. 54.07/20.06 [2019-03-28 12:19:01,309 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9650 states to 9650 states and 15771 transitions. 54.07/20.06 [2019-03-28 12:19:01,309 INFO L729 BuchiCegarLoop]: Abstraction has 9650 states and 15771 transitions. 54.07/20.06 [2019-03-28 12:19:01,309 INFO L609 BuchiCegarLoop]: Abstraction has 9650 states and 15771 transitions. 54.07/20.06 [2019-03-28 12:19:01,309 INFO L442 BuchiCegarLoop]: ======== Iteration 30============ 54.07/20.06 [2019-03-28 12:19:01,310 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9650 states and 15771 transitions. 54.07/20.06 [2019-03-28 12:19:01,340 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 5476 54.07/20.06 [2019-03-28 12:19:01,340 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 54.07/20.06 [2019-03-28 12:19:01,340 INFO L119 BuchiIsEmpty]: Starting construction of run 54.07/20.06 [2019-03-28 12:19:01,341 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 54.07/20.06 [2019-03-28 12:19:01,341 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1] 54.07/20.06 [2019-03-28 12:19:01,342 INFO L794 eck$LassoCheckResult]: Stem: 119466#ULTIMATE.startENTRY [885] ULTIMATE.startENTRY-->L202: Formula: (and (= v_~d0_ev~0_23 2) (= 0 v_~z_val~0_13) (= 2 v_~b1_ev~0_23) (= v_~d0_val_t~0_9 1) (= v_~b0_val~0_13 0) (= 1 v_~b1_val_t~0_9) (= 1 v_~d1_req_up~0_12) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_9 0) (= 2 v_~d1_ev~0_23) (= v_~b1_val~0_13 0) (= v_~b0_val_t~0_9 1) (= v_~b0_req_up~0_12 1) (= 0 v_~comp_m1_i~0_7) (= v_~d0_req_up~0_12 1) (= v_~comp_m1_st~0_15 0) (= v_~b0_ev~0_23 2) (= 1 v_~d1_val_t~0_9) (= v_~z_req_up~0_12 0) (= v_~z_val_t~0_10 0) (= 0 v_~d1_val~0_13) (= v_~z_ev~0_19 2) (= v_~b1_req_up~0_12 1) (= 0 v_~d0_val~0_13)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret4=|v_ULTIMATE.start_start_simulation_#t~ret4_4|, ~b1_val~0=v_~b1_val~0_13, ~b0_val~0=v_~b0_val~0_13, ~d0_req_up~0=v_~d0_req_up~0_12, ~d0_val~0=v_~d0_val~0_13, ~d1_val_t~0=v_~d1_val_t~0_9, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_9, ~d1_ev~0=v_~d1_ev~0_23, ~d1_val~0=v_~d1_val~0_13, ~b0_req_up~0=v_~b0_req_up~0_12, ~z_ev~0=v_~z_ev~0_19, ~b1_val_t~0=v_~b1_val_t~0_9, ~b1_ev~0=v_~b1_ev~0_23, ULTIMATE.start_main_~__retres1~2=v_ULTIMATE.start_main_~__retres1~2_6, ~z_val~0=v_~z_val~0_13, ~d1_req_up~0=v_~d1_req_up~0_12, ~z_val_t~0=v_~z_val_t~0_10, ~b0_val_t~0=v_~b0_val_t~0_9, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~z_req_up~0=v_~z_req_up~0_12, ~b1_req_up~0=v_~b1_req_up~0_12, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~d0_ev~0=v_~d0_ev~0_23, ~b0_ev~0=v_~b0_ev~0_23, ~d0_val_t~0=v_~d0_val_t~0_9, ~comp_m1_st~0=v_~comp_m1_st~0_15, ~comp_m1_i~0=v_~comp_m1_i~0_7} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret4, ~b1_val~0, ~b0_val~0, ~d0_req_up~0, ~d0_val~0, ~d1_val_t~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~d1_ev~0, ~d1_val~0, ~b0_req_up~0, ~z_ev~0, ~b1_val_t~0, ~b1_ev~0, ULTIMATE.start_main_~__retres1~2, ~z_val~0, ~d1_req_up~0, ~z_val_t~0, ~b0_val_t~0, ULTIMATE.start_start_simulation_~tmp~3, ~z_req_up~0, ~b1_req_up~0, ULTIMATE.start_main_#res, ~d0_ev~0, ~b0_ev~0, ~d0_val_t~0, ~comp_m1_st~0, ~comp_m1_i~0] 119467#L202 [566] L202-->L127: Formula: (= 1 v_~b0_req_up~0_4) InVars {~b0_req_up~0=v_~b0_req_up~0_4} OutVars{~b0_req_up~0=v_~b0_req_up~0_4} AuxVars[] AssignedVars[] 119398#L127 [748] L127-->L127-2: Formula: (and (= v_~b0_val~0_3 v_~b0_val_t~0_3) (> v_~b0_val_t~0_3 v_~b0_val~0_4) (= v_~b0_ev~0_3 0)) InVars {~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_4} OutVars{~b0_ev~0=v_~b0_ev~0_3, ~b0_val_t~0=v_~b0_val_t~0_3, ~b0_val~0=v_~b0_val~0_3} AuxVars[] AssignedVars[~b0_val~0, ~b0_ev~0] 119399#L127-2 [580] L127-2-->L202-1: Formula: (= v_~b0_req_up~0_5 0) InVars {} OutVars{~b0_req_up~0=v_~b0_req_up~0_5} AuxVars[] AssignedVars[~b0_req_up~0] 119460#L202-1 [545] L202-1-->L142: Formula: (= 1 v_~b1_req_up~0_4) InVars {~b1_req_up~0=v_~b1_req_up~0_4} OutVars{~b1_req_up~0=v_~b1_req_up~0_4} AuxVars[] AssignedVars[] 119425#L142 [752] L142-->L142-2: Formula: (and (= v_~b1_ev~0_3 0) (< v_~b1_val~0_4 v_~b1_val_t~0_3) (= v_~b1_val~0_3 v_~b1_val_t~0_3)) InVars {~b1_val_t~0=v_~b1_val_t~0_3, ~b1_val~0=v_~b1_val~0_4} OutVars{~b1_val_t~0=v_~b1_val_t~0_3, ~b1_ev~0=v_~b1_ev~0_3, ~b1_val~0=v_~b1_val~0_3} AuxVars[] AssignedVars[~b1_val~0, ~b1_ev~0] 119414#L142-2 [521] L142-2-->L209: Formula: (= v_~b1_req_up~0_5 0) InVars {} OutVars{~b1_req_up~0=v_~b1_req_up~0_5} AuxVars[] AssignedVars[~b1_req_up~0] 119415#L209 [624] L209-->L157: Formula: (= v_~d0_req_up~0_4 1) InVars {~d0_req_up~0=v_~d0_req_up~0_4} OutVars{~d0_req_up~0=v_~d0_req_up~0_4} AuxVars[] AssignedVars[] 119370#L157 [757] L157-->L157-2: Formula: (and (> v_~d0_val_t~0_3 v_~d0_val~0_4) (= v_~d0_val~0_3 v_~d0_val_t~0_3) (= v_~d0_ev~0_3 0)) InVars {~d0_val~0=v_~d0_val~0_4, ~d0_val_t~0=v_~d0_val_t~0_3} OutVars{~d0_ev~0=v_~d0_ev~0_3, ~d0_val~0=v_~d0_val~0_3, ~d0_val_t~0=v_~d0_val_t~0_3} AuxVars[] AssignedVars[~d0_ev~0, ~d0_val~0] 119357#L157-2 [600] L157-2-->L216: Formula: (= v_~d0_req_up~0_5 0) InVars {} OutVars{~d0_req_up~0=v_~d0_req_up~0_5} AuxVars[] AssignedVars[~d0_req_up~0] 119358#L216 [554] L216-->L172: Formula: (= v_~d1_req_up~0_4 1) InVars {~d1_req_up~0=v_~d1_req_up~0_4} OutVars{~d1_req_up~0=v_~d1_req_up~0_4} AuxVars[] AssignedVars[] 119475#L172 [760] L172-->L172-2: Formula: (and (= v_~d1_val~0_3 v_~d1_val_t~0_3) (= v_~d1_ev~0_3 0) (> v_~d1_val_t~0_3 v_~d1_val~0_4)) InVars {~d1_val_t~0=v_~d1_val_t~0_3, ~d1_val~0=v_~d1_val~0_4} OutVars{~d1_val_t~0=v_~d1_val_t~0_3, ~d1_val~0=v_~d1_val~0_3, ~d1_ev~0=v_~d1_ev~0_3} AuxVars[] AssignedVars[~d1_val~0, ~d1_ev~0] 119465#L172-2 [547] L172-2-->L223: Formula: (= v_~d1_req_up~0_5 0) InVars {} OutVars{~d1_req_up~0=v_~d1_req_up~0_5} AuxVars[] AssignedVars[~d1_req_up~0] 119464#L223 [762] L223-->L230: Formula: (> 1 v_~z_req_up~0_6) InVars {~z_req_up~0=v_~z_req_up~0_6} OutVars{~z_req_up~0=v_~z_req_up~0_6} AuxVars[] AssignedVars[] 119359#L230 [767] L230-->L245-1: Formula: (and (> 1 v_~comp_m1_i~0_4) (= v_~comp_m1_st~0_5 2)) InVars {~comp_m1_i~0=v_~comp_m1_i~0_4} OutVars{~comp_m1_st~0=v_~comp_m1_st~0_5, ~comp_m1_i~0=v_~comp_m1_i~0_4} AuxVars[] AssignedVars[~comp_m1_st~0] 119360#L245-1 [608] L245-1-->L311-1: Formula: (and (= v_~b0_ev~0_5 1) (= v_~b0_ev~0_6 0)) InVars {~b0_ev~0=v_~b0_ev~0_6} OutVars{~b0_ev~0=v_~b0_ev~0_5} AuxVars[] AssignedVars[~b0_ev~0] 119392#L311-1 [628] L311-1-->L316-1: Formula: (and (= 0 v_~b1_ev~0_6) (= v_~b1_ev~0_5 1)) InVars {~b1_ev~0=v_~b1_ev~0_6} OutVars{~b1_ev~0=v_~b1_ev~0_5} AuxVars[] AssignedVars[~b1_ev~0] 119508#L316-1 [654] L316-1-->L321-1: Formula: (and (= v_~d0_ev~0_5 1) (= v_~d0_ev~0_6 0)) InVars {~d0_ev~0=v_~d0_ev~0_6} OutVars{~d0_ev~0=v_~d0_ev~0_5} AuxVars[] AssignedVars[~d0_ev~0] 119509#L321-1 [507] L321-1-->L326-1: Formula: (and (= 0 v_~d1_ev~0_6) (= v_~d1_ev~0_5 1)) InVars {~d1_ev~0=v_~d1_ev~0_6} OutVars{~d1_ev~0=v_~d1_ev~0_5} AuxVars[] AssignedVars[~d1_ev~0] 119562#L326-1 [776] L326-1-->L331-1: Formula: (< 0 v_~z_ev~0_7) InVars {~z_ev~0=v_~z_ev~0_7} OutVars{~z_ev~0=v_~z_ev~0_7} AuxVars[] AssignedVars[] 119560#L331-1 [583] L331-1-->L97: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_1|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_is_method1_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret2] 119557#L97 [591] L97-->L119: Formula: (and (= v_~b0_ev~0_11 1) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4 1)) InVars {~b0_ev~0=v_~b0_ev~0_11} OutVars{ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_4, ~b0_ev~0=v_~b0_ev~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_method1_triggered_~__retres1~0] 119555#L119 [886] L119-->L380: Formula: (and (= |v_ULTIMATE.start_is_method1_triggered_#res_7| v_ULTIMATE.start_activate_threads_~tmp~1_13) (= v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19 |v_ULTIMATE.start_is_method1_triggered_#res_7|)) InVars {ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_13, ULTIMATE.start_is_method1_triggered_#res=|v_ULTIMATE.start_is_method1_triggered_#res_7|, ULTIMATE.start_is_method1_triggered_~__retres1~0=v_ULTIMATE.start_is_method1_triggered_~__retres1~0_19, ULTIMATE.start_activate_threads_#t~ret2=|v_ULTIMATE.start_activate_threads_#t~ret2_7|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_method1_triggered_#res, ULTIMATE.start_activate_threads_#t~ret2] 119551#L380 [785] L380-->L380-2: Formula: (and (= v_~comp_m1_st~0_6 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_8)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_8, ~comp_m1_st~0=v_~comp_m1_st~0_6} AuxVars[] AssignedVars[~comp_m1_st~0] 119549#L380-2 [618] L380-2-->L344-1: Formula: (and (= v_~b0_ev~0_15 2) (= v_~b0_ev~0_16 1)) InVars {~b0_ev~0=v_~b0_ev~0_16} OutVars{~b0_ev~0=v_~b0_ev~0_15} AuxVars[] AssignedVars[~b0_ev~0] 119443#L344-1 [626] L344-1-->L349-1: Formula: (and (= 1 v_~b1_ev~0_16) (= v_~b1_ev~0_15 2)) InVars {~b1_ev~0=v_~b1_ev~0_16} OutVars{~b1_ev~0=v_~b1_ev~0_15} AuxVars[] AssignedVars[~b1_ev~0] 119444#L349-1 [652] L349-1-->L354-1: Formula: (and (= v_~d0_ev~0_15 2) (= v_~d0_ev~0_16 1)) InVars {~d0_ev~0=v_~d0_ev~0_16} OutVars{~d0_ev~0=v_~d0_ev~0_15} AuxVars[] AssignedVars[~d0_ev~0] 120687#L354-1 [502] L354-1-->L359-1: Formula: (and (= 1 v_~d1_ev~0_16) (= v_~d1_ev~0_15 2)) InVars {~d1_ev~0=v_~d1_ev~0_16} OutVars{~d1_ev~0=v_~d1_ev~0_15} AuxVars[] AssignedVars[~d1_ev~0] 120686#L359-1 [797] L359-1-->L422-1: Formula: (> v_~z_ev~0_13 1) InVars {~z_ev~0=v_~z_ev~0_13} OutVars{~z_ev~0=v_~z_ev~0_13} AuxVars[] AssignedVars[] 120684#L422-1 [887] L422-1-->L285: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 1) InVars {} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 120685#L285 54.07/20.06 [2019-03-28 12:19:01,342 INFO L796 eck$LassoCheckResult]: Loop: 120685#L285 [888] L285-->L258: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_13, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1, ULTIMATE.start_exists_runnable_thread_#res] 122899#L258 [671] L258-->L265: Formula: (and (= 0 v_~comp_m1_st~0_8) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_4 1)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_4, ~comp_m1_st~0=v_~comp_m1_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~1] 122898#L265 [889] L265-->L280: Formula: (and (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_eval_~tmp___0~0_7) (= |v_ULTIMATE.start_exists_runnable_thread_#res_8| v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~1=v_ULTIMATE.start_exists_runnable_thread_~__retres1~1_14, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_8|, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp___0~0] 122896#L280 [816] L280-->L280-1: Formula: (> v_ULTIMATE.start_eval_~tmp___0~0_4 0) InVars {ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_4} OutVars{ULTIMATE.start_eval_~tmp___0~0=v_ULTIMATE.start_eval_~tmp___0~0_4} AuxVars[] AssignedVars[] 122895#L280-1 [669] L280-1-->L289: Formula: (and (= v_ULTIMATE.start_eval_~tmp~0_4 |v_ULTIMATE.start_eval_#t~nondet1_3|) (= v_~comp_m1_st~0_12 0)) InVars {~comp_m1_st~0=v_~comp_m1_st~0_12, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_3|} OutVars{ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_2|, ~comp_m1_st~0=v_~comp_m1_st~0_12} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp~0] 122894#L289 [643] L289-->L285: Formula: (= v_ULTIMATE.start_eval_~tmp~0_1 0) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_1} OutVars{ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_1} AuxVars[] AssignedVars[] 120685#L285 54.07/20.06 [2019-03-28 12:19:01,342 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.06 [2019-03-28 12:19:01,342 INFO L82 PathProgramCache]: Analyzing trace with hash 1217900399, now seen corresponding path program 4 times 54.07/20.06 [2019-03-28 12:19:01,342 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.06 [2019-03-28 12:19:01,343 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.06 [2019-03-28 12:19:01,343 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:19:01,343 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:19:01,344 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:19:01,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 54.07/20.06 [2019-03-28 12:19:01,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 54.07/20.06 [2019-03-28 12:19:01,358 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.06 [2019-03-28 12:19:01,358 INFO L82 PathProgramCache]: Analyzing trace with hash 1187358341, now seen corresponding path program 1 times 54.07/20.06 [2019-03-28 12:19:01,358 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.06 [2019-03-28 12:19:01,359 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.06 [2019-03-28 12:19:01,359 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:19:01,359 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:19:01,360 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:19:01,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 54.07/20.06 [2019-03-28 12:19:01,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 54.07/20.06 [2019-03-28 12:19:01,364 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 54.07/20.06 [2019-03-28 12:19:01,364 INFO L82 PathProgramCache]: Analyzing trace with hash -1618244749, now seen corresponding path program 1 times 54.07/20.06 [2019-03-28 12:19:01,364 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 54.07/20.06 [2019-03-28 12:19:01,364 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 54.07/20.06 [2019-03-28 12:19:01,365 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:19:01,365 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:19:01,365 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 54.07/20.06 [2019-03-28 12:19:01,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 54.07/20.06 [2019-03-28 12:19:01,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 54.07/20.06 [2019-03-28 12:19:01,738 WARN L188 SmtUtils]: Spent 316.00 ms on a formula simplification. DAG size of input: 111 DAG size of output: 102 54.07/20.06 [2019-03-28 12:19:01,820 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 28.03 12:19:01 BasicIcfg 54.07/20.06 [2019-03-28 12:19:01,820 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- 54.07/20.06 [2019-03-28 12:19:01,820 INFO L168 Benchmark]: Toolchain (without parser) took 15522.57 ms. Allocated memory was 649.6 MB in the beginning and 1.1 GB in the end (delta: 471.9 MB). Free memory was 563.9 MB in the beginning and 544.7 MB in the end (delta: 19.2 MB). Peak memory consumption was 491.1 MB. Max. memory is 50.3 GB. 54.07/20.06 [2019-03-28 12:19:01,821 INFO L168 Benchmark]: CDTParser took 0.16 ms. Allocated memory is still 649.6 MB. Free memory is still 585.4 MB. There was no memory consumed. Max. memory is 50.3 GB. 54.07/20.06 [2019-03-28 12:19:01,822 INFO L168 Benchmark]: CACSL2BoogieTranslator took 380.09 ms. Allocated memory was 649.6 MB in the beginning and 675.3 MB in the end (delta: 25.7 MB). Free memory was 563.9 MB in the beginning and 636.9 MB in the end (delta: -73.0 MB). Peak memory consumption was 33.0 MB. Max. memory is 50.3 GB. 54.07/20.06 [2019-03-28 12:19:01,822 INFO L168 Benchmark]: Boogie Procedure Inliner took 49.83 ms. Allocated memory is still 675.3 MB. Free memory was 636.9 MB in the beginning and 634.2 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 50.3 GB. 54.07/20.06 [2019-03-28 12:19:01,823 INFO L168 Benchmark]: Boogie Preprocessor took 34.20 ms. Allocated memory is still 675.3 MB. Free memory was 634.2 MB in the beginning and 631.5 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 50.3 GB. 54.07/20.06 [2019-03-28 12:19:01,823 INFO L168 Benchmark]: RCFGBuilder took 535.07 ms. Allocated memory is still 675.3 MB. Free memory was 631.5 MB in the beginning and 590.5 MB in the end (delta: 41.0 MB). Peak memory consumption was 41.0 MB. Max. memory is 50.3 GB. 54.07/20.06 [2019-03-28 12:19:01,824 INFO L168 Benchmark]: BlockEncodingV2 took 172.65 ms. Allocated memory is still 675.3 MB. Free memory was 590.5 MB in the beginning and 570.3 MB in the end (delta: 20.2 MB). Peak memory consumption was 20.2 MB. Max. memory is 50.3 GB. 54.07/20.06 [2019-03-28 12:19:01,824 INFO L168 Benchmark]: TraceAbstraction took 203.75 ms. Allocated memory is still 675.3 MB. Free memory was 570.3 MB in the beginning and 550.0 MB in the end (delta: 20.2 MB). Peak memory consumption was 20.2 MB. Max. memory is 50.3 GB. 54.07/20.06 [2019-03-28 12:19:01,825 INFO L168 Benchmark]: BuchiAutomizer took 14141.57 ms. Allocated memory was 675.3 MB in the beginning and 1.1 GB in the end (delta: 446.2 MB). Free memory was 550.0 MB in the beginning and 544.7 MB in the end (delta: 5.4 MB). Peak memory consumption was 451.5 MB. Max. memory is 50.3 GB. 54.07/20.06 [2019-03-28 12:19:01,829 INFO L337 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### 54.07/20.06 --- Results --- 54.07/20.06 * Results from de.uni_freiburg.informatik.ultimate.plugins.blockencoding: 54.07/20.06 - StatisticsResult: Initial Icfg 54.07/20.06 107 locations, 179 edges 54.07/20.06 - StatisticsResult: Encoded RCFG 54.07/20.06 90 locations, 224 edges 54.07/20.06 * Results from de.uni_freiburg.informatik.ultimate.core: 54.07/20.06 - StatisticsResult: Toolchain Benchmarks 54.07/20.06 Benchmark results are: 54.07/20.06 * CDTParser took 0.16 ms. Allocated memory is still 649.6 MB. Free memory is still 585.4 MB. There was no memory consumed. Max. memory is 50.3 GB. 54.07/20.06 * CACSL2BoogieTranslator took 380.09 ms. Allocated memory was 649.6 MB in the beginning and 675.3 MB in the end (delta: 25.7 MB). Free memory was 563.9 MB in the beginning and 636.9 MB in the end (delta: -73.0 MB). Peak memory consumption was 33.0 MB. Max. memory is 50.3 GB. 54.07/20.06 * Boogie Procedure Inliner took 49.83 ms. Allocated memory is still 675.3 MB. Free memory was 636.9 MB in the beginning and 634.2 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 50.3 GB. 54.07/20.06 * Boogie Preprocessor took 34.20 ms. Allocated memory is still 675.3 MB. Free memory was 634.2 MB in the beginning and 631.5 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 50.3 GB. 54.07/20.06 * RCFGBuilder took 535.07 ms. Allocated memory is still 675.3 MB. Free memory was 631.5 MB in the beginning and 590.5 MB in the end (delta: 41.0 MB). Peak memory consumption was 41.0 MB. Max. memory is 50.3 GB. 54.07/20.06 * BlockEncodingV2 took 172.65 ms. Allocated memory is still 675.3 MB. Free memory was 590.5 MB in the beginning and 570.3 MB in the end (delta: 20.2 MB). Peak memory consumption was 20.2 MB. Max. memory is 50.3 GB. 54.07/20.06 * TraceAbstraction took 203.75 ms. Allocated memory is still 675.3 MB. Free memory was 570.3 MB in the beginning and 550.0 MB in the end (delta: 20.2 MB). Peak memory consumption was 20.2 MB. Max. memory is 50.3 GB. 54.07/20.06 * BuchiAutomizer took 14141.57 ms. Allocated memory was 675.3 MB in the beginning and 1.1 GB in the end (delta: 446.2 MB). Free memory was 550.0 MB in the beginning and 544.7 MB in the end (delta: 5.4 MB). Peak memory consumption was 451.5 MB. Max. memory is 50.3 GB. 54.07/20.06 * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: 54.07/20.06 - AllSpecificationsHoldResult: All specifications hold 54.07/20.06 We were not able to verify any specifiation because the program does not contain any specification. 54.07/20.06 - InvariantResult [Line: 198]: Loop Invariant 54.07/20.06 Derived loop invariant: 1 54.07/20.06 - InvariantResult [Line: 245]: Loop Invariant 54.07/20.06 Derived loop invariant: 1 54.07/20.06 - InvariantResult [Line: 344]: Loop Invariant 54.07/20.06 Derived loop invariant: 1 54.07/20.06 - InvariantResult [Line: 275]: Loop Invariant 54.07/20.06 Derived loop invariant: 1 54.07/20.06 - InvariantResult [Line: 257]: Loop Invariant 54.07/20.06 Derived loop invariant: 1 54.07/20.06 - InvariantResult [Line: 201]: Loop Invariant 54.07/20.06 Derived loop invariant: 1 54.07/20.06 - InvariantResult [Line: 257]: Loop Invariant 54.07/20.06 Derived loop invariant: 1 54.07/20.06 - InvariantResult [Line: 311]: Loop Invariant 54.07/20.06 Derived loop invariant: 1 54.07/20.06 - InvariantResult [Line: 393]: Loop Invariant 54.07/20.06 Derived loop invariant: 1 54.07/20.06 - InvariantResult [Line: 340]: Loop Invariant 54.07/20.06 Derived loop invariant: 1 54.07/20.06 - InvariantResult [Line: 307]: Loop Invariant 54.07/20.06 Derived loop invariant: 1 54.07/20.06 - InvariantResult [Line: 340]: Loop Invariant 54.07/20.06 Derived loop invariant: 1 54.07/20.06 - InvariantResult [Line: 344]: Loop Invariant 54.07/20.06 Derived loop invariant: 1 54.07/20.06 - InvariantResult [Line: 201]: Loop Invariant 54.07/20.06 Derived loop invariant: 1 54.07/20.06 - InvariantResult [Line: 201]: Loop Invariant 54.07/20.06 Derived loop invariant: 1 54.07/20.06 - InvariantResult [Line: 201]: Loop Invariant 54.07/20.06 Derived loop invariant: 1 54.07/20.06 - InvariantResult [Line: 201]: Loop Invariant 54.07/20.06 Derived loop invariant: 1 54.07/20.06 - InvariantResult [Line: 307]: Loop Invariant 54.07/20.06 Derived loop invariant: 1 54.07/20.06 - InvariantResult [Line: 201]: Loop Invariant 54.07/20.06 Derived loop invariant: 1 54.07/20.06 - InvariantResult [Line: -1]: Loop Invariant 54.07/20.06 Derived loop invariant: 1 54.07/20.06 - InvariantResult [Line: 96]: Loop Invariant 54.07/20.06 Derived loop invariant: 1 54.07/20.06 - InvariantResult [Line: 96]: Loop Invariant 54.07/20.06 Derived loop invariant: 1 54.07/20.06 - InvariantResult [Line: 201]: Loop Invariant 54.07/20.06 Derived loop invariant: 1 54.07/20.06 - InvariantResult [Line: 201]: Loop Invariant 54.07/20.06 Derived loop invariant: 1 54.07/20.06 - InvariantResult [Line: 280]: Loop Invariant 54.07/20.06 Derived loop invariant: 1 54.07/20.06 - StatisticsResult: Ultimate Automizer benchmark data 54.07/20.06 CFG has 1 procedures, 90 locations, 0 error locations. SAFE Result, 0.1s OverallTime, 0 OverallIterations, 0 TraceHistogramMax, 0.0s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: No data available, PredicateUnifierStatistics: No data available, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=90occurred in iteration=0, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: No data available, HoareAnnotationStatistics: 0.0s HoareAnnotationTime, 25 LocationsWithAnnotation, 25 PreInvPairs, 25 NumberOfFragments, 25 HoareAnnotationTreeSize, 25 FomulaSimplifications, 0 FormulaSimplificationTreeSizeReduction, 0.0s HoareSimplificationTime, 25 FomulaSimplificationsInter, 0 FormulaSimplificationTreeSizeReductionInter, 0.0s HoareSimplificationTimeInter, RefinementEngineStatistics: No data available, ReuseStatistics: No data available 54.07/20.06 - StatisticsResult: Constructed decomposition of program 54.07/20.06 Your program was decomposed into 30 terminating modules (29 trivial, 0 deterministic, 1 nondeterministic) and one nonterminating remainder module.One nondeterministic module has affine ranking function -1 * d0_ev + 1 and consists of 16 locations. 29 modules have a trivial ranking function, the largest among these consists of 4 locations. The remainder module has 9650 locations. 54.07/20.06 - StatisticsResult: Timing statistics 54.07/20.06 BüchiAutomizer plugin needed 14.0s and 30 iterations. TraceHistogramMax:1. Analysis of lassos took 3.1s. Construction of modules took 5.2s. Büchi inclusion checks took 3.2s. Highest rank in rank-based complementation 3. Minimization of det autom 25. Minimization of nondet autom 5. Automata minimization 1.3s AutomataMinimizationTime, 30 MinimizatonAttempts, 16836 StatesRemovedByMinimization, 7 NontrivialMinimizations. Non-live state removal took 0.7s Buchi closure took 0.0s. Biggest automaton had 9650 states and ocurred in iteration 29. Nontrivial modules had stage [1, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 2751 SDtfs, 5335 SDslu, 5093 SDs, 0 SdLazy, 6961 SolverSat, 267 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 5.2s Time LassoAnalysisResults: nont1 unkn0 SFLI5 SFLT0 conc0 concLT1 SILN0 SILU0 SILI23 SILT0 lasso0 LassoPreprocessingBenchmarks: Lassos: inital80 mio100 ax100 hnf100 lsp13 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq209 hnf86 smp100 dnf100 smp100 tf110 neg100 sie100 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 8ms VariablesStem: 0 VariablesLoop: 0 DisjunctsStem: 1 DisjunctsLoop: 1 SupportingInvariants: 0 MotzkinApplications: 2 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 2 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 1 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s 54.07/20.06 - TerminationAnalysisResult: Nontermination possible 54.07/20.06 Buchi Automizer proved that your program is nonterminating for some inputs 54.07/20.06 - FixpointNonTerminationResult [Line: 275]: Nontermination argument in form of an infinite program execution. 54.07/20.06 Nontermination argument in form of an infinite execution 54.07/20.06 State at position 0 is 54.07/20.06 {} 54.07/20.06 State at position 1 is 54.07/20.06 {org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@f549866=0, b1_val_t=1, \result=0, d0_val=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@26362fa2=0, __retres1=1, z_val=0, tmp=0, b0_val_t=1, kernel_st=1, d1_ev=2, comp_m1_i=0, b1_val=1, d1_req_up=0, tmp___0=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4cdb5431=0, z_val_t=0, b1_req_up=0, __retres1=1, d0_ev=2, z_ev=2, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@471f226c=0, b1_ev=2, comp_m1_st=0, b0_req_up=0, z_req_up=0, \result=1, d1_val=1, b0_ev=2, tmp=1, d0_val_t=1, d1_val_t=1, b0_val=1, __retres1=0, d0_req_up=0, \result=1} 54.07/20.06 - StatisticsResult: NonterminationArgumentStatistics 54.07/20.06 Fixpoint 54.07/20.06 - NonterminatingLassoResult [Line: 275]: Nonterminating execution 54.07/20.06 Found a nonterminating execution for the following lasso shaped sequence of statements. 54.07/20.06 Stem: 54.07/20.06 [L14] int b0_val ; 54.07/20.06 [L15] int b0_val_t ; 54.07/20.06 [L16] int b0_ev ; 54.07/20.06 [L17] int b0_req_up ; 54.07/20.06 [L18] int b1_val ; 54.07/20.06 [L19] int b1_val_t ; 54.07/20.06 [L20] int b1_ev ; 54.07/20.06 [L21] int b1_req_up ; 54.07/20.06 [L22] int d0_val ; 54.07/20.06 [L23] int d0_val_t ; 54.07/20.06 [L24] int d0_ev ; 54.07/20.06 [L25] int d0_req_up ; 54.07/20.06 [L26] int d1_val ; 54.07/20.06 [L27] int d1_val_t ; 54.07/20.06 [L28] int d1_ev ; 54.07/20.06 [L29] int d1_req_up ; 54.07/20.06 [L30] int z_val ; 54.07/20.06 [L31] int z_val_t ; 54.07/20.06 [L32] int z_ev ; 54.07/20.06 [L33] int z_req_up ; 54.07/20.06 [L34] int comp_m1_st ; 54.07/20.06 [L35] int comp_m1_i ; 54.07/20.06 [L484] int __retres1 ; 54.07/20.06 [L455] b0_val = 0 54.07/20.06 [L456] b0_ev = 2 54.07/20.06 [L457] b0_req_up = 0 54.07/20.06 [L458] b1_val = 0 54.07/20.06 [L459] b1_ev = 2 54.07/20.06 [L460] b1_req_up = 0 54.07/20.06 [L461] d0_val = 0 54.07/20.06 [L462] d0_ev = 2 54.07/20.06 [L463] d0_req_up = 0 54.07/20.06 [L464] d1_val = 0 54.07/20.06 [L465] d1_ev = 2 54.07/20.06 [L466] d1_req_up = 0 54.07/20.06 [L467] z_val = 0 54.07/20.06 [L468] z_ev = 2 54.07/20.06 [L469] z_req_up = 0 54.07/20.06 [L470] b0_val_t = 1 54.07/20.06 [L471] b0_req_up = 1 54.07/20.06 [L472] b1_val_t = 1 54.07/20.06 [L473] b1_req_up = 1 54.07/20.06 [L474] d0_val_t = 1 54.07/20.06 [L475] d0_req_up = 1 54.07/20.06 [L476] d1_val_t = 1 54.07/20.06 [L477] d1_req_up = 1 54.07/20.06 [L478] comp_m1_i = 0 54.07/20.06 [L409] int kernel_st ; 54.07/20.06 [L410] int tmp ; 54.07/20.06 [L414] kernel_st = 0 54.07/20.06 [L202] COND TRUE (int )b0_req_up == 1 54.07/20.06 [L127] COND TRUE (int )b0_val != (int )b0_val_t 54.07/20.06 [L128] b0_val = b0_val_t 54.07/20.06 [L129] b0_ev = 0 54.07/20.06 [L133] b0_req_up = 0 54.07/20.06 [L209] COND TRUE (int )b1_req_up == 1 54.07/20.06 [L142] COND TRUE (int )b1_val != (int )b1_val_t 54.07/20.06 [L143] b1_val = b1_val_t 54.07/20.06 [L144] b1_ev = 0 54.07/20.06 [L148] b1_req_up = 0 54.07/20.06 [L216] COND TRUE (int )d0_req_up == 1 54.07/20.06 [L157] COND TRUE (int )d0_val != (int )d0_val_t 54.07/20.06 [L158] d0_val = d0_val_t 54.07/20.06 [L159] d0_ev = 0 54.07/20.06 [L163] d0_req_up = 0 54.07/20.06 [L223] COND TRUE (int )d1_req_up == 1 54.07/20.06 [L172] COND TRUE (int )d1_val != (int )d1_val_t 54.07/20.06 [L173] d1_val = d1_val_t 54.07/20.06 [L174] d1_ev = 0 54.07/20.06 [L178] d1_req_up = 0 54.07/20.06 [L230] COND FALSE !((int )z_req_up == 1) 54.07/20.06 [L245] COND FALSE !((int )comp_m1_i == 1) 54.07/20.06 [L248] comp_m1_st = 2 54.07/20.06 [L311] COND TRUE (int )b0_ev == 0 54.07/20.06 [L312] b0_ev = 1 54.07/20.06 [L316] COND TRUE (int )b1_ev == 0 54.07/20.06 [L317] b1_ev = 1 54.07/20.06 [L321] COND TRUE (int )d0_ev == 0 54.07/20.06 [L322] d0_ev = 1 54.07/20.06 [L326] COND TRUE (int )d1_ev == 0 54.07/20.06 [L327] d1_ev = 1 54.07/20.06 [L331] COND FALSE !((int )z_ev == 0) 54.07/20.06 [L374] int tmp ; 54.07/20.06 [L94] int __retres1 ; 54.07/20.06 [L97] COND TRUE (int )b0_ev == 1 54.07/20.06 [L98] __retres1 = 1 54.07/20.06 [L120] return (__retres1); 54.07/20.06 [L378] tmp = is_method1_triggered() 54.07/20.06 [L380] COND TRUE \read(tmp) 54.07/20.06 [L381] comp_m1_st = 0 54.07/20.06 [L344] COND TRUE (int )b0_ev == 1 54.07/20.06 [L345] b0_ev = 2 54.07/20.06 [L349] COND TRUE (int )b1_ev == 1 54.07/20.06 [L350] b1_ev = 2 54.07/20.06 [L354] COND TRUE (int )d0_ev == 1 54.07/20.06 [L355] d0_ev = 2 54.07/20.06 [L359] COND TRUE (int )d1_ev == 1 54.07/20.06 [L360] d1_ev = 2 54.07/20.06 [L364] COND FALSE !((int )z_ev == 1) 54.07/20.06 [L422] COND TRUE 1 54.07/20.06 [L425] kernel_st = 1 54.07/20.06 [L270] int tmp ; 54.07/20.06 [L271] int tmp___0 ; 54.07/20.06 Loop: 54.07/20.06 [L275] COND TRUE 1 54.07/20.06 [L255] int __retres1 ; 54.07/20.06 [L258] COND TRUE (int )comp_m1_st == 0 54.07/20.06 [L259] __retres1 = 1 54.07/20.06 [L266] return (__retres1); 54.07/20.06 [L278] tmp___0 = exists_runnable_thread() 54.07/20.06 [L280] COND TRUE \read(tmp___0) 54.07/20.06 [L285] COND TRUE (int )comp_m1_st == 0 54.07/20.06 [L287] tmp = __VERIFIER_nondet_int() 54.07/20.06 [L289] COND FALSE !(\read(tmp)) 54.07/20.06 End of lasso representation. 54.07/20.06 RESULT: Ultimate proved your program to be incorrect! 54.07/20.06 !SESSION 2019-03-28 12:18:42.971 ----------------------------------------------- 54.07/20.06 eclipse.buildId=unknown 54.07/20.06 java.version=1.8.0_181 54.07/20.06 java.vendor=Oracle Corporation 54.07/20.06 BootLoader constants: OS=linux, ARCH=x86_64, WS=gtk, NL=en_US 54.07/20.06 Framework arguments: -tc ./../AutomizerAndBuchiAutomizerCInlineWithBlockEncoding.xml -s ./../termcomp2017.epf -i /export/starexec/sandbox/benchmark/theBenchmark.c 54.07/20.06 Command-line arguments: -os linux -ws gtk -arch x86_64 -consoleLog -data @user.home/.ultimate -tc ./../AutomizerAndBuchiAutomizerCInlineWithBlockEncoding.xml -s ./../termcomp2017.epf -data /export/starexec/sandbox/tmp -i /export/starexec/sandbox/benchmark/theBenchmark.c 54.07/20.06 54.07/20.06 !ENTRY org.eclipse.core.resources 2 10035 2019-03-28 12:19:02.076 54.07/20.06 !MESSAGE The workspace will exit with unsaved changes in this session. 54.07/20.06 Received shutdown request... 54.07/20.06 Ultimate: 54.07/20.06 GTK+ Version Check 54.07/20.06 EOF