31.95/12.14 NO 31.95/12.14 31.95/12.15 Ultimate: Cannot open display: 31.95/12.15 This is Ultimate 0.1.24-8dc7c08-m 31.95/12.15 [2019-03-28 12:20:15,503 INFO L170 SettingsManager]: Resetting all preferences to default values... 31.95/12.15 [2019-03-28 12:20:15,505 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values 31.95/12.15 [2019-03-28 12:20:15,516 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... 31.95/12.15 [2019-03-28 12:20:15,517 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values 31.95/12.15 [2019-03-28 12:20:15,518 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values 31.95/12.15 [2019-03-28 12:20:15,519 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values 31.95/12.15 [2019-03-28 12:20:15,521 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values 31.95/12.15 [2019-03-28 12:20:15,522 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values 31.95/12.15 [2019-03-28 12:20:15,523 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values 31.95/12.15 [2019-03-28 12:20:15,524 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... 31.95/12.15 [2019-03-28 12:20:15,524 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values 31.95/12.15 [2019-03-28 12:20:15,525 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values 31.95/12.15 [2019-03-28 12:20:15,526 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values 31.95/12.15 [2019-03-28 12:20:15,527 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values 31.95/12.15 [2019-03-28 12:20:15,528 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values 31.95/12.15 [2019-03-28 12:20:15,529 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values 31.95/12.15 [2019-03-28 12:20:15,531 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values 31.95/12.15 [2019-03-28 12:20:15,533 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values 31.95/12.15 [2019-03-28 12:20:15,534 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values 31.95/12.15 [2019-03-28 12:20:15,535 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values 31.95/12.15 [2019-03-28 12:20:15,537 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values 31.95/12.15 [2019-03-28 12:20:15,539 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 31.95/12.15 [2019-03-28 12:20:15,539 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... 31.95/12.15 [2019-03-28 12:20:15,539 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values 31.95/12.15 [2019-03-28 12:20:15,540 INFO L174 SettingsManager]: Resetting IcfgToChc preferences to default values 31.95/12.15 [2019-03-28 12:20:15,541 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values 31.95/12.15 [2019-03-28 12:20:15,541 INFO L177 SettingsManager]: ReqToTest provides no preferences, ignoring... 31.95/12.15 [2019-03-28 12:20:15,542 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values 31.95/12.15 [2019-03-28 12:20:15,542 INFO L174 SettingsManager]: Resetting ChcSmtPrinter preferences to default values 31.95/12.15 [2019-03-28 12:20:15,543 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values 31.95/12.15 [2019-03-28 12:20:15,544 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values 31.95/12.15 [2019-03-28 12:20:15,545 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... 31.95/12.15 [2019-03-28 12:20:15,545 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values 31.95/12.15 [2019-03-28 12:20:15,546 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... 31.95/12.15 [2019-03-28 12:20:15,546 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... 31.95/12.15 [2019-03-28 12:20:15,546 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values 31.95/12.15 [2019-03-28 12:20:15,547 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values 31.95/12.15 [2019-03-28 12:20:15,548 INFO L181 SettingsManager]: Finished resetting all preferences to default values... 31.95/12.15 [2019-03-28 12:20:15,548 INFO L98 SettingsManager]: Beginning loading settings from /export/starexec/sandbox/solver/bin/./../termcomp2017.epf 31.95/12.15 [2019-03-28 12:20:15,563 INFO L110 SettingsManager]: Loading preferences was successful 31.95/12.15 [2019-03-28 12:20:15,563 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: 31.95/12.15 [2019-03-28 12:20:15,565 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: 31.95/12.15 [2019-03-28 12:20:15,565 INFO L133 SettingsManager]: * Rewrite not-equals=true 31.95/12.15 [2019-03-28 12:20:15,565 INFO L133 SettingsManager]: * Create parallel compositions if possible=false 31.95/12.15 [2019-03-28 12:20:15,565 INFO L133 SettingsManager]: * Minimize states using LBE with the strategy=SINGLE 31.95/12.15 [2019-03-28 12:20:15,565 INFO L133 SettingsManager]: * Use SBE=true 31.95/12.15 [2019-03-28 12:20:15,566 INFO L131 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: 31.95/12.15 [2019-03-28 12:20:15,566 INFO L133 SettingsManager]: * Use old map elimination=false 31.95/12.15 [2019-03-28 12:20:15,566 INFO L133 SettingsManager]: * Use external solver (rank synthesis)=false 31.95/12.15 [2019-03-28 12:20:15,566 INFO L133 SettingsManager]: * Buchi interpolant automaton construction strategy=DANDELION 31.95/12.15 [2019-03-28 12:20:15,566 INFO L133 SettingsManager]: * Use only trivial implications for array writes=true 31.95/12.15 [2019-03-28 12:20:15,567 INFO L133 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES 31.95/12.15 [2019-03-28 12:20:15,567 INFO L133 SettingsManager]: * Construct termination proof for TermComp=true 31.95/12.15 [2019-03-28 12:20:15,567 INFO L133 SettingsManager]: * Command for external solver (GNTA synthesis)=z3 SMTLIB2_COMPLIANT=true -memory:4560 -smt2 -in -t:12000 31.95/12.15 [2019-03-28 12:20:15,567 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: 31.95/12.15 [2019-03-28 12:20:15,567 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false 31.95/12.15 [2019-03-28 12:20:15,567 INFO L133 SettingsManager]: * Check division by zero=IGNORE 31.95/12.15 [2019-03-28 12:20:15,568 INFO L133 SettingsManager]: * Check if freed pointer was valid=false 31.95/12.15 [2019-03-28 12:20:15,568 INFO L133 SettingsManager]: * Assume nondeterminstic values are in range=false 31.95/12.15 [2019-03-28 12:20:15,568 INFO L133 SettingsManager]: * How to treat unsigned ints differently from normal ones=IGNORE 31.95/12.15 [2019-03-28 12:20:15,568 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: 31.95/12.15 [2019-03-28 12:20:15,568 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements 31.95/12.15 [2019-03-28 12:20:15,569 INFO L133 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump 31.95/12.15 [2019-03-28 12:20:15,569 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:4560 -smt2 -in -t:5000 31.95/12.15 [2019-03-28 12:20:15,569 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: 31.95/12.15 [2019-03-28 12:20:15,569 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles 31.95/12.15 [2019-03-28 12:20:15,569 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL 31.95/12.15 [2019-03-28 12:20:15,570 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true 31.95/12.15 [2019-03-28 12:20:15,596 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp 31.95/12.15 [2019-03-28 12:20:15,610 INFO L259 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized 31.95/12.15 [2019-03-28 12:20:15,614 INFO L215 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. 31.95/12.15 [2019-03-28 12:20:15,615 INFO L271 PluginConnector]: Initializing CDTParser... 31.95/12.15 [2019-03-28 12:20:15,616 INFO L276 PluginConnector]: CDTParser initialized 31.95/12.15 [2019-03-28 12:20:15,617 INFO L430 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /export/starexec/sandbox/benchmark/theBenchmark.c 31.95/12.15 [2019-03-28 12:20:15,719 INFO L221 CDTParser]: Created temporary CDT project at /export/starexec/sandbox/tmp/8f39ad306556425cbd8e590f06b85521/FLAG7ad2a2083 31.95/12.15 [2019-03-28 12:20:16,079 INFO L307 CDTParser]: Found 1 translation units. 31.95/12.15 [2019-03-28 12:20:16,080 INFO L161 CDTParser]: Scanning /export/starexec/sandbox/benchmark/theBenchmark.c 31.95/12.15 [2019-03-28 12:20:16,089 INFO L355 CDTParser]: About to delete temporary CDT project at /export/starexec/sandbox/tmp/8f39ad306556425cbd8e590f06b85521/FLAG7ad2a2083 31.95/12.15 [2019-03-28 12:20:16,473 INFO L363 CDTParser]: Successfully deleted /export/starexec/sandbox/tmp/8f39ad306556425cbd8e590f06b85521 31.95/12.15 [2019-03-28 12:20:16,484 INFO L297 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### 31.95/12.15 [2019-03-28 12:20:16,486 INFO L131 ToolchainWalker]: Walking toolchain with 7 elements. 31.95/12.15 [2019-03-28 12:20:16,487 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- 31.95/12.15 [2019-03-28 12:20:16,487 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... 31.95/12.15 [2019-03-28 12:20:16,491 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized 31.95/12.15 [2019-03-28 12:20:16,492 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.03 12:20:16" (1/1) ... 31.95/12.15 [2019-03-28 12:20:16,495 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@571fe538 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:20:16, skipping insertion in model container 31.95/12.15 [2019-03-28 12:20:16,495 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.03 12:20:16" (1/1) ... 31.95/12.15 [2019-03-28 12:20:16,503 INFO L145 MainTranslator]: Starting translation in SV-COMP mode 31.95/12.15 [2019-03-28 12:20:16,532 INFO L176 MainTranslator]: Built tables and reachable declarations 31.95/12.15 [2019-03-28 12:20:16,787 INFO L206 PostProcessor]: Analyzing one entry point: main 31.95/12.15 [2019-03-28 12:20:16,794 INFO L191 MainTranslator]: Completed pre-run 31.95/12.15 [2019-03-28 12:20:16,831 INFO L206 PostProcessor]: Analyzing one entry point: main 31.95/12.15 [2019-03-28 12:20:16,851 INFO L195 MainTranslator]: Completed translation 31.95/12.15 [2019-03-28 12:20:16,851 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:20:16 WrapperNode 31.95/12.15 [2019-03-28 12:20:16,852 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- 31.95/12.15 [2019-03-28 12:20:16,853 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- 31.95/12.15 [2019-03-28 12:20:16,853 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... 31.95/12.15 [2019-03-28 12:20:16,853 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized 31.95/12.15 [2019-03-28 12:20:16,863 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:20:16" (1/1) ... 31.95/12.15 [2019-03-28 12:20:16,871 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:20:16" (1/1) ... 31.95/12.15 [2019-03-28 12:20:16,903 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- 31.95/12.15 [2019-03-28 12:20:16,904 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- 31.95/12.15 [2019-03-28 12:20:16,904 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... 31.95/12.15 [2019-03-28 12:20:16,904 INFO L276 PluginConnector]: Boogie Preprocessor initialized 31.95/12.15 [2019-03-28 12:20:16,914 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:20:16" (1/1) ... 31.95/12.15 [2019-03-28 12:20:16,915 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:20:16" (1/1) ... 31.95/12.15 [2019-03-28 12:20:16,917 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:20:16" (1/1) ... 31.95/12.15 [2019-03-28 12:20:16,917 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:20:16" (1/1) ... 31.95/12.15 [2019-03-28 12:20:16,923 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:20:16" (1/1) ... 31.95/12.15 [2019-03-28 12:20:16,933 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:20:16" (1/1) ... 31.95/12.15 [2019-03-28 12:20:16,935 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:20:16" (1/1) ... 31.95/12.15 [2019-03-28 12:20:16,939 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- 31.95/12.15 [2019-03-28 12:20:16,939 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- 31.95/12.15 [2019-03-28 12:20:16,939 INFO L271 PluginConnector]: Initializing RCFGBuilder... 31.95/12.15 [2019-03-28 12:20:16,939 INFO L276 PluginConnector]: RCFGBuilder initialized 31.95/12.15 [2019-03-28 12:20:16,941 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:20:16" (1/1) ... 31.95/12.15 No working directory specified, using /export/starexec/sandbox/solver/bin/z3 31.95/12.15 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:4560 -smt2 -in -t:5000 (exit command is (exit), workingDir is null) 31.95/12.15 Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:4560 -smt2 -in -t:5000 31.95/12.15 [2019-03-28 12:20:17,012 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start 31.95/12.15 [2019-03-28 12:20:17,012 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start 31.95/12.15 [2019-03-28 12:20:17,473 INFO L281 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) 31.95/12.15 [2019-03-28 12:20:17,473 INFO L286 CfgBuilder]: Removed 73 assue(true) statements. 31.95/12.15 [2019-03-28 12:20:17,475 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.03 12:20:17 BoogieIcfgContainer 31.95/12.15 [2019-03-28 12:20:17,475 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- 31.95/12.15 [2019-03-28 12:20:17,476 INFO L113 PluginConnector]: ------------------------BlockEncodingV2---------------------------- 31.95/12.15 [2019-03-28 12:20:17,476 INFO L271 PluginConnector]: Initializing BlockEncodingV2... 31.95/12.15 [2019-03-28 12:20:17,478 INFO L276 PluginConnector]: BlockEncodingV2 initialized 31.95/12.15 [2019-03-28 12:20:17,479 INFO L185 PluginConnector]: Executing the observer BlockEncodingObserver from plugin BlockEncodingV2 for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.03 12:20:17" (1/1) ... 31.95/12.15 [2019-03-28 12:20:17,501 INFO L313 BlockEncoder]: Initial Icfg 121 locations, 189 edges 31.95/12.15 [2019-03-28 12:20:17,503 INFO L258 BlockEncoder]: Using Remove infeasible edges 31.95/12.15 [2019-03-28 12:20:17,504 INFO L263 BlockEncoder]: Using Maximize final states 31.95/12.15 [2019-03-28 12:20:17,504 INFO L270 BlockEncoder]: Using Minimize states even if more edges are added than removed.=false 31.95/12.15 [2019-03-28 12:20:17,505 INFO L276 BlockEncoder]: Using Minimize states using LBE with the strategy=SINGLE 31.95/12.15 [2019-03-28 12:20:17,507 INFO L296 BlockEncoder]: Using Remove sink states 31.95/12.15 [2019-03-28 12:20:17,508 INFO L171 BlockEncoder]: Using Apply optimizations until nothing changes=true 31.95/12.15 [2019-03-28 12:20:17,508 INFO L179 BlockEncoder]: Using Rewrite not-equals 31.95/12.15 [2019-03-28 12:20:17,554 INFO L185 BlockEncoder]: Using Use SBE 31.95/12.15 [2019-03-28 12:20:17,597 INFO L200 BlockEncoder]: SBE split 59 edges 31.95/12.15 [2019-03-28 12:20:17,604 INFO L70 emoveInfeasibleEdges]: Removed 11 edges and 0 locations because of local infeasibility 31.95/12.15 [2019-03-28 12:20:17,606 INFO L71 MaximizeFinalStates]: 0 new accepting states 31.95/12.15 [2019-03-28 12:20:17,648 INFO L100 BaseMinimizeStates]: Removed 48 edges and 24 locations by large block encoding 31.95/12.15 [2019-03-28 12:20:17,651 INFO L70 RemoveSinkStates]: Removed 4 edges and 3 locations by removing sink states 31.95/12.15 [2019-03-28 12:20:17,653 INFO L70 emoveInfeasibleEdges]: Removed 0 edges and 0 locations because of local infeasibility 31.95/12.15 [2019-03-28 12:20:17,653 INFO L71 MaximizeFinalStates]: 0 new accepting states 31.95/12.15 [2019-03-28 12:20:17,656 INFO L100 BaseMinimizeStates]: Removed 2 edges and 1 locations by large block encoding 31.95/12.15 [2019-03-28 12:20:17,656 INFO L70 RemoveSinkStates]: Removed 0 edges and 0 locations by removing sink states 31.95/12.15 [2019-03-28 12:20:17,657 INFO L70 emoveInfeasibleEdges]: Removed 0 edges and 0 locations because of local infeasibility 31.95/12.15 [2019-03-28 12:20:17,657 INFO L71 MaximizeFinalStates]: 0 new accepting states 31.95/12.15 [2019-03-28 12:20:17,658 INFO L100 BaseMinimizeStates]: Removed 0 edges and 0 locations by large block encoding 31.95/12.15 [2019-03-28 12:20:17,658 INFO L70 RemoveSinkStates]: Removed 0 edges and 0 locations by removing sink states 31.95/12.15 [2019-03-28 12:20:17,659 INFO L313 BlockEncoder]: Encoded RCFG 93 locations, 208 edges 31.95/12.15 [2019-03-28 12:20:17,660 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.blockencoding CFG 28.03 12:20:17 BasicIcfg 31.95/12.15 [2019-03-28 12:20:17,660 INFO L132 PluginConnector]: ------------------------ END BlockEncodingV2---------------------------- 31.95/12.15 [2019-03-28 12:20:17,661 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- 31.95/12.15 [2019-03-28 12:20:17,661 INFO L271 PluginConnector]: Initializing TraceAbstraction... 31.95/12.15 [2019-03-28 12:20:17,664 INFO L276 PluginConnector]: TraceAbstraction initialized 31.95/12.15 [2019-03-28 12:20:17,665 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 28.03 12:20:16" (1/4) ... 31.95/12.15 [2019-03-28 12:20:17,665 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@42c66075 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.03 12:20:17, skipping insertion in model container 31.95/12.15 [2019-03-28 12:20:17,666 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:20:16" (2/4) ... 31.95/12.15 [2019-03-28 12:20:17,666 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@42c66075 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.03 12:20:17, skipping insertion in model container 31.95/12.15 [2019-03-28 12:20:17,666 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.03 12:20:17" (3/4) ... 31.95/12.15 [2019-03-28 12:20:17,667 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@42c66075 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.03 12:20:17, skipping insertion in model container 31.95/12.15 [2019-03-28 12:20:17,667 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.blockencoding CFG 28.03 12:20:17" (4/4) ... 31.95/12.15 [2019-03-28 12:20:17,669 INFO L112 eAbstractionObserver]: Analyzing ICFG theBenchmark.c_BEv2 31.95/12.15 [2019-03-28 12:20:17,679 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:ForwardPredicates Determinization: PREDICATE_ABSTRACTION 31.95/12.15 [2019-03-28 12:20:17,687 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 0 error locations. 31.95/12.15 [2019-03-28 12:20:17,704 INFO L257 AbstractCegarLoop]: Starting to check reachability of 0 error locations. 31.95/12.15 [2019-03-28 12:20:17,734 INFO L133 ementStrategyFactory]: Using default assertion order modulation 31.95/12.15 [2019-03-28 12:20:17,734 INFO L382 AbstractCegarLoop]: Interprodecural is true 31.95/12.15 [2019-03-28 12:20:17,735 INFO L383 AbstractCegarLoop]: Hoare is true 31.95/12.15 [2019-03-28 12:20:17,735 INFO L384 AbstractCegarLoop]: Compute interpolants for ForwardPredicates 31.95/12.15 [2019-03-28 12:20:17,735 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE 31.95/12.15 [2019-03-28 12:20:17,735 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION 31.95/12.15 [2019-03-28 12:20:17,735 INFO L387 AbstractCegarLoop]: Difference is false 31.95/12.15 [2019-03-28 12:20:17,735 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA 31.95/12.15 [2019-03-28 12:20:17,736 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== 31.95/12.15 [2019-03-28 12:20:17,751 INFO L276 IsEmpty]: Start isEmpty. Operand 93 states. 31.95/12.15 [2019-03-28 12:20:17,759 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. 31.95/12.15 [2019-03-28 12:20:17,765 INFO L343 DoubleDeckerVisitor]: Before removal of dead ends 93 states. 31.95/12.15 [2019-03-28 12:20:17,849 INFO L451 ceAbstractionStarter]: At program point L250-1(lines 236 258) the Hoare annotation is: true 31.95/12.15 [2019-03-28 12:20:17,849 INFO L451 ceAbstractionStarter]: At program point L250-3(lines 236 258) the Hoare annotation is: true 31.95/12.15 [2019-03-28 12:20:17,849 INFO L448 ceAbstractionStarter]: For program point L151-1(lines 150 163) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,849 INFO L451 ceAbstractionStarter]: At program point L201(lines 191 229) the Hoare annotation is: true 31.95/12.15 [2019-03-28 12:20:17,850 INFO L451 ceAbstractionStarter]: At program point L135(lines 123 137) the Hoare annotation is: true 31.95/12.15 [2019-03-28 12:20:17,850 INFO L451 ceAbstractionStarter]: At program point L135-1(lines 123 137) the Hoare annotation is: true 31.95/12.15 [2019-03-28 12:20:17,850 INFO L451 ceAbstractionStarter]: At program point L135-2(lines 123 137) the Hoare annotation is: true 31.95/12.15 [2019-03-28 12:20:17,850 INFO L451 ceAbstractionStarter]: At program point L135-3(lines 123 137) the Hoare annotation is: true 31.95/12.15 [2019-03-28 12:20:17,850 INFO L451 ceAbstractionStarter]: At program point ULTIMATE.startENTRY(line -1) the Hoare annotation is: true 31.95/12.15 [2019-03-28 12:20:17,851 INFO L448 ceAbstractionStarter]: For program point L218(lines 218 225) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,851 INFO L451 ceAbstractionStarter]: At program point L375(lines 364 377) the Hoare annotation is: true 31.95/12.15 [2019-03-28 12:20:17,851 INFO L451 ceAbstractionStarter]: At program point L144(lines 151 155) the Hoare annotation is: true 31.95/12.15 [2019-03-28 12:20:17,851 INFO L451 ceAbstractionStarter]: At program point L12(lines 1 449) the Hoare annotation is: true 31.95/12.15 [2019-03-28 12:20:17,852 INFO L448 ceAbstractionStarter]: For program point L268-1(lines 262 280) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,852 INFO L448 ceAbstractionStarter]: For program point L169(lines 169 179) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,852 INFO L448 ceAbstractionStarter]: For program point L268-3(lines 262 280) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,852 INFO L448 ceAbstractionStarter]: For program point L169-1(lines 169 179) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,852 INFO L448 ceAbstractionStarter]: For program point L169-2(lines 169 179) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,852 INFO L448 ceAbstractionStarter]: For program point L368(lines 368 373) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,853 INFO L448 ceAbstractionStarter]: For program point L245-1(lines 239 257) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,853 INFO L448 ceAbstractionStarter]: For program point L245-3(lines 239 257) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,853 INFO L448 ceAbstractionStarter]: For program point L336-1(lines 330 348) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,853 INFO L448 ceAbstractionStarter]: For program point L204(lines 204 211) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,853 INFO L448 ceAbstractionStarter]: For program point L105(lines 105 114) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,853 INFO L451 ceAbstractionStarter]: At program point L394-1(lines 259 431) the Hoare annotation is: true 31.95/12.15 [2019-03-28 12:20:17,854 INFO L448 ceAbstractionStarter]: For program point L72(lines 72 80) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,854 INFO L448 ceAbstractionStarter]: For program point L105-2(lines 105 114) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,854 INFO L448 ceAbstractionStarter]: For program point L105-3(lines 105 114) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,854 INFO L451 ceAbstractionStarter]: At program point L196(lines 196 200) the Hoare annotation is: true 31.95/12.15 [2019-03-28 12:20:17,854 INFO L448 ceAbstractionStarter]: For program point L105-5(lines 105 114) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,854 INFO L448 ceAbstractionStarter]: For program point L196-1(lines 191 229) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,855 INFO L448 ceAbstractionStarter]: For program point L105-6(lines 105 114) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,855 INFO L448 ceAbstractionStarter]: For program point L105-8(lines 105 114) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,855 INFO L448 ceAbstractionStarter]: For program point L105-9(lines 105 114) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,855 INFO L448 ceAbstractionStarter]: For program point L31(lines 31 39) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,855 INFO L448 ceAbstractionStarter]: For program point L105-11(lines 105 114) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,855 INFO L448 ceAbstractionStarter]: For program point L106(lines 106 111) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,855 INFO L448 ceAbstractionStarter]: For program point L106-1(lines 106 111) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,856 INFO L448 ceAbstractionStarter]: For program point L106-2(lines 106 111) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,856 INFO L448 ceAbstractionStarter]: For program point L106-3(lines 106 111) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,856 INFO L448 ceAbstractionStarter]: For program point L263-1(lines 262 280) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,856 INFO L448 ceAbstractionStarter]: For program point L263-3(lines 262 280) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,856 INFO L451 ceAbstractionStarter]: At program point L156-1(lines 240 244) the Hoare annotation is: true 31.95/12.15 [2019-03-28 12:20:17,857 INFO L451 ceAbstractionStarter]: At program point L181(lines 168 183) the Hoare annotation is: true 31.95/12.15 [2019-03-28 12:20:17,857 INFO L451 ceAbstractionStarter]: At program point L181-1(lines 168 183) the Hoare annotation is: true 31.95/12.15 [2019-03-28 12:20:17,857 INFO L451 ceAbstractionStarter]: At program point L181-2(lines 168 183) the Hoare annotation is: true 31.95/12.15 [2019-03-28 12:20:17,857 INFO L448 ceAbstractionStarter]: For program point L173(lines 173 178) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,857 INFO L448 ceAbstractionStarter]: For program point L173-1(lines 173 178) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,857 INFO L448 ceAbstractionStarter]: For program point L173-2(lines 173 178) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,857 INFO L451 ceAbstractionStarter]: At program point L413(lines 413 422) the Hoare annotation is: true 31.95/12.15 [2019-03-28 12:20:17,858 INFO L448 ceAbstractionStarter]: For program point L124(lines 124 133) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,858 INFO L451 ceAbstractionStarter]: At program point L413-1(lines 413 422) the Hoare annotation is: true 31.95/12.15 [2019-03-28 12:20:17,858 INFO L448 ceAbstractionStarter]: For program point L124-2(lines 124 133) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,858 INFO L451 ceAbstractionStarter]: At program point L58(lines 30 66) the Hoare annotation is: true 31.95/12.15 [2019-03-28 12:20:17,858 INFO L448 ceAbstractionStarter]: For program point L124-3(lines 124 133) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,858 INFO L451 ceAbstractionStarter]: At program point L215(lines 191 229) the Hoare annotation is: true 31.95/12.15 [2019-03-28 12:20:17,859 INFO L448 ceAbstractionStarter]: For program point L124-5(lines 124 133) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,859 INFO L448 ceAbstractionStarter]: For program point L124-6(lines 124 133) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,859 INFO L451 ceAbstractionStarter]: At program point L116(lines 104 118) the Hoare annotation is: true 31.95/12.15 [2019-03-28 12:20:17,859 INFO L448 ceAbstractionStarter]: For program point L124-8(lines 124 133) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,859 INFO L451 ceAbstractionStarter]: At program point L116-1(lines 104 118) the Hoare annotation is: true 31.95/12.15 [2019-03-28 12:20:17,859 INFO L448 ceAbstractionStarter]: For program point L124-9(lines 124 133) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,860 INFO L451 ceAbstractionStarter]: At program point L116-2(lines 104 118) the Hoare annotation is: true 31.95/12.15 [2019-03-28 12:20:17,860 INFO L451 ceAbstractionStarter]: At program point L116-3(lines 104 118) the Hoare annotation is: true 31.95/12.15 [2019-03-28 12:20:17,860 INFO L448 ceAbstractionStarter]: For program point L124-11(lines 124 133) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,860 INFO L448 ceAbstractionStarter]: For program point L240-1(lines 239 257) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,860 INFO L448 ceAbstractionStarter]: For program point L240-2(lines 240 244) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,860 INFO L451 ceAbstractionStarter]: At program point L273-3(lines 259 281) the Hoare annotation is: true 31.95/12.15 [2019-03-28 12:20:17,861 INFO L448 ceAbstractionStarter]: For program point L240-4(lines 239 257) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,861 INFO L448 ceAbstractionStarter]: For program point L75(lines 75 79) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,861 INFO L448 ceAbstractionStarter]: For program point L298(lines 298 302) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,861 INFO L448 ceAbstractionStarter]: For program point L331-1(lines 330 348) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,861 INFO L451 ceAbstractionStarter]: At program point L298-2(lines 263 267) the Hoare annotation is: true 31.95/12.15 [2019-03-28 12:20:17,861 INFO L448 ceAbstractionStarter]: For program point L298-3(lines 298 302) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,861 INFO L451 ceAbstractionStarter]: At program point L298-5(lines 1 449) the Hoare annotation is: true 31.95/12.15 [2019-03-28 12:20:17,862 INFO L448 ceAbstractionStarter]: For program point L298-6(lines 298 302) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,862 INFO L448 ceAbstractionStarter]: For program point L290(lines 290 294) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,862 INFO L448 ceAbstractionStarter]: For program point L34(lines 34 38) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,862 INFO L451 ceAbstractionStarter]: At program point L298-8(lines 263 267) the Hoare annotation is: true 31.95/12.15 [2019-03-28 12:20:17,862 INFO L448 ceAbstractionStarter]: For program point L298-9(lines 298 302) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,862 INFO L448 ceAbstractionStarter]: For program point L290-2(lines 290 294) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,862 INFO L448 ceAbstractionStarter]: For program point L290-3(lines 290 294) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,863 INFO L451 ceAbstractionStarter]: At program point L298-11(lines 331 335) the Hoare annotation is: true 31.95/12.15 [2019-03-28 12:20:17,863 INFO L448 ceAbstractionStarter]: For program point L125(lines 125 130) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,863 INFO L448 ceAbstractionStarter]: For program point L290-5(lines 290 294) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,863 INFO L448 ceAbstractionStarter]: For program point L290-6(lines 290 294) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,863 INFO L448 ceAbstractionStarter]: For program point L125-1(lines 125 130) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,863 INFO L448 ceAbstractionStarter]: For program point L125-2(lines 125 130) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,863 INFO L448 ceAbstractionStarter]: For program point L290-8(lines 290 294) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,864 INFO L448 ceAbstractionStarter]: For program point L125-3(lines 125 130) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,864 INFO L448 ceAbstractionStarter]: For program point L290-9(lines 290 294) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,864 INFO L448 ceAbstractionStarter]: For program point L290-11(lines 290 294) no Hoare annotation was computed. 31.95/12.15 [2019-03-28 12:20:17,864 INFO L451 ceAbstractionStarter]: At program point L35(lines 30 66) the Hoare annotation is: true 31.95/12.15 [2019-03-28 12:20:17,874 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.03 12:20:17 BasicIcfg 31.95/12.15 [2019-03-28 12:20:17,875 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- 31.95/12.15 [2019-03-28 12:20:17,875 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- 31.95/12.15 [2019-03-28 12:20:17,875 INFO L271 PluginConnector]: Initializing BuchiAutomizer... 31.95/12.15 [2019-03-28 12:20:17,879 INFO L276 PluginConnector]: BuchiAutomizer initialized 31.95/12.15 [2019-03-28 12:20:17,880 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis 31.95/12.15 [2019-03-28 12:20:17,880 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 28.03 12:20:16" (1/5) ... 31.95/12.15 [2019-03-28 12:20:17,881 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@f86bfa2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.03 12:20:17, skipping insertion in model container 31.95/12.15 [2019-03-28 12:20:17,881 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis 31.95/12.15 [2019-03-28 12:20:17,881 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.03 12:20:16" (2/5) ... 31.95/12.15 [2019-03-28 12:20:17,881 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@f86bfa2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.03 12:20:17, skipping insertion in model container 31.95/12.15 [2019-03-28 12:20:17,881 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis 31.95/12.15 [2019-03-28 12:20:17,881 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.03 12:20:17" (3/5) ... 31.95/12.15 [2019-03-28 12:20:17,882 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@f86bfa2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 28.03 12:20:17, skipping insertion in model container 31.95/12.15 [2019-03-28 12:20:17,882 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis 31.95/12.15 [2019-03-28 12:20:17,882 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.blockencoding CFG 28.03 12:20:17" (4/5) ... 31.95/12.15 [2019-03-28 12:20:17,882 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@f86bfa2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 28.03 12:20:17, skipping insertion in model container 31.95/12.15 [2019-03-28 12:20:17,883 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis 31.95/12.15 [2019-03-28 12:20:17,883 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.03 12:20:17" (5/5) ... 31.95/12.15 [2019-03-28 12:20:17,884 INFO L375 chiAutomizerObserver]: Analyzing ICFG theBenchmark.c_BEv2 31.95/12.15 [2019-03-28 12:20:17,909 INFO L133 ementStrategyFactory]: Using default assertion order modulation 31.95/12.15 [2019-03-28 12:20:17,909 INFO L374 BuchiCegarLoop]: Interprodecural is true 31.95/12.15 [2019-03-28 12:20:17,910 INFO L375 BuchiCegarLoop]: Hoare is true 31.95/12.15 [2019-03-28 12:20:17,910 INFO L376 BuchiCegarLoop]: Compute interpolants for ForwardPredicates 31.95/12.15 [2019-03-28 12:20:17,910 INFO L377 BuchiCegarLoop]: Backedges is STRAIGHT_LINE 31.95/12.15 [2019-03-28 12:20:17,910 INFO L378 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION 31.95/12.15 [2019-03-28 12:20:17,910 INFO L379 BuchiCegarLoop]: Difference is false 31.95/12.15 [2019-03-28 12:20:17,910 INFO L380 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA 31.95/12.15 [2019-03-28 12:20:17,910 INFO L383 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== 31.95/12.15 [2019-03-28 12:20:17,915 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 93 states. 31.95/12.15 [2019-03-28 12:20:17,940 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 72 31.95/12.15 [2019-03-28 12:20:17,941 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 31.95/12.15 [2019-03-28 12:20:17,941 INFO L119 BuchiIsEmpty]: Starting construction of run 31.95/12.15 [2019-03-28 12:20:17,950 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 31.95/12.15 [2019-03-28 12:20:17,950 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 31.95/12.15 [2019-03-28 12:20:17,950 INFO L442 BuchiCegarLoop]: ======== Iteration 1============ 31.95/12.15 [2019-03-28 12:20:17,950 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 93 states. 31.95/12.15 [2019-03-28 12:20:17,956 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 72 31.95/12.15 [2019-03-28 12:20:17,956 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 31.95/12.15 [2019-03-28 12:20:17,956 INFO L119 BuchiIsEmpty]: Starting construction of run 31.95/12.15 [2019-03-28 12:20:17,958 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 31.95/12.15 [2019-03-28 12:20:17,958 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 31.95/12.15 [2019-03-28 12:20:17,964 INFO L794 eck$LassoCheckResult]: Stem: 38#ULTIMATE.startENTRYtrue [871] ULTIMATE.startENTRY-->L144: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~m_pc~0_16 0) (= 0 v_~m_st~0_19) (= 2 v_~E_1~0_28) (= v_~M_E~0_27 2) (= v_~T1_E~0_18 2) (= v_~t1_pc~0_16 0) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= 0 v_~t1_st~0_19)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ULTIMATE.start_start_simulation_#t~ret6=|v_ULTIMATE.start_start_simulation_#t~ret6_4|, ~t1_st~0=v_~t1_st~0_19, ~t1_pc~0=v_~t1_pc~0_16, ~M_E~0=v_~M_E~0_27, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~E_1~0=v_~E_1~0_28, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~T1_E~0=v_~T1_E~0_18, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_19, ~m_pc~0=v_~m_pc~0_16, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_start_simulation_#t~ret6, ~t1_st~0, ~t1_pc~0, ~M_E~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_~kernel_st~0, ~E_1~0, ULTIMATE.start_main_#res, ~T1_E~0, ~t1_i~0, ~m_st~0, ~m_pc~0, ULTIMATE.start_main_~__retres1~3] 42#L144true [557] L144-->L151-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 53#L151-1true [755] L151-1-->L156-1: Formula: (and (> 1 v_~t1_i~0_4) (= v_~t1_st~0_3 2)) InVars {~t1_i~0=v_~t1_i~0_4} OutVars{~t1_st~0=v_~t1_st~0_3, ~t1_i~0=v_~t1_i~0_4} AuxVars[] AssignedVars[~t1_st~0] 66#L156-1true [681] L156-1-->L240-1: Formula: (and (= 0 v_~M_E~0_3) (= v_~M_E~0_2 1)) InVars {~M_E~0=v_~M_E~0_3} OutVars{~M_E~0=v_~M_E~0_2} AuxVars[] AssignedVars[~M_E~0] 64#L240-1true [585] L240-1-->L245-1: Formula: (and (= v_~T1_E~0_2 1) (= 0 v_~T1_E~0_3)) InVars {~T1_E~0=v_~T1_E~0_3} OutVars{~T1_E~0=v_~T1_E~0_2} AuxVars[] AssignedVars[~T1_E~0] 15#L245-1true [761] L245-1-->L250-1: Formula: (< v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 62#L250-1true [679] L250-1-->L105: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_1|, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 76#L105true [601] L105-->L106: Formula: (= v_~m_pc~0_2 1) InVars {~m_pc~0=v_~m_pc~0_2} OutVars{~m_pc~0=v_~m_pc~0_2} AuxVars[] AssignedVars[] 37#L106true [549] L106-->L116: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_4 1) (= 1 v_~M_E~0_8)) InVars {~M_E~0=v_~M_E~0_8} OutVars{~M_E~0=v_~M_E~0_8, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_4} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 78#L116true [872] L116-->L290: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_24 |v_ULTIMATE.start_is_master_triggered_#res_13|) (= |v_ULTIMATE.start_is_master_triggered_#res_13| v_ULTIMATE.start_activate_threads_~tmp~1_24)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_24} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_24, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_24, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_13|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 58#L290true [767] L290-->L290-2: Formula: (and (= v_~m_st~0_4 0) (> 0 v_ULTIMATE.start_activate_threads_~tmp~1_5)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} OutVars{~m_st~0=v_~m_st~0_4, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} AuxVars[] AssignedVars[~m_st~0] 50#L290-2true [569] L290-2-->L124: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 8#L124true [769] L124-->L124-2: Formula: (> v_~t1_pc~0_7 1) InVars {~t1_pc~0=v_~t1_pc~0_7} OutVars{~t1_pc~0=v_~t1_pc~0_7} AuxVars[] AssignedVars[] 3#L124-2true [632] L124-2-->L135: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 9#L135true [873] L135-->L298: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_24 |v_ULTIMATE.start_is_transmit1_triggered_#res_13|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25 |v_ULTIMATE.start_is_transmit1_triggered_#res_13|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_24, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_13|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 81#L298true [773] L298-->L298-2: Formula: (and (= v_~t1_st~0_6 0) (> 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_8)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_8} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_8, ~t1_st~0=v_~t1_st~0_6} AuxVars[] AssignedVars[~t1_st~0] 44#L298-2true [775] L298-2-->L263-1: Formula: (< v_~M_E~0_14 1) InVars {~M_E~0=v_~M_E~0_14} OutVars{~M_E~0=v_~M_E~0_14} AuxVars[] AssignedVars[] 6#L263-1true [777] L263-1-->L268-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 51#L268-1true [779] L268-1-->L394-1: Formula: (> 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 82#L394-1true 31.95/12.15 [2019-03-28 12:20:17,966 INFO L796 eck$LassoCheckResult]: Loop: 82#L394-1true [874] L394-1-->L215: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 19#L215true [875] L215-->L169: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_22, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 35#L169true [545] L169-->L181: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_8 1) (= v_~m_st~0_7 0)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 83#L181true [876] L181-->L196: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 94#L196true [878] L196-->L240-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 92#L240-2true [626] L240-2-->L240-4: Formula: (and (= v_~M_E~0_5 1) (= 0 v_~M_E~0_6)) InVars {~M_E~0=v_~M_E~0_6} OutVars{~M_E~0=v_~M_E~0_5} AuxVars[] AssignedVars[~M_E~0] 87#L240-4true [786] L240-4-->L245-3: Formula: (< 0 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 11#L245-3true [641] L245-3-->L250-3: Formula: (and (= v_~E_1~0_6 0) (= v_~E_1~0_5 1)) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_5} AuxVars[] AssignedVars[~E_1~0] 57#L250-3true [676] L250-3-->L105-6: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_4, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_4|, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_2|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 90#L105-6true [794] L105-6-->L105-8: Formula: (> v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 86#L105-8true [619] L105-8-->L116-2: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 72#L116-2true [883] L116-2-->L290-6: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_27 |v_ULTIMATE.start_is_master_triggered_#res_16|) (= |v_ULTIMATE.start_is_master_triggered_#res_16| v_ULTIMATE.start_activate_threads_~tmp~1_27)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_27} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_27, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_27, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_16|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 29#L290-6true [532] L290-6-->L290-8: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 26#L290-8true [524] L290-8-->L124-6: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 16#L124-6true [649] L124-6-->L125-2: Formula: (= v_~t1_pc~0_8 1) InVars {~t1_pc~0=v_~t1_pc~0_8} OutVars{~t1_pc~0=v_~t1_pc~0_8} AuxVars[] AssignedVars[] 28#L125-2true [528] L125-2-->L135-2: Formula: (and (= 1 v_~E_1~0_10) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_10 1)) InVars {~E_1~0=v_~E_1~0_10} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_10, ~E_1~0=v_~E_1~0_10} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 5#L135-2true [885] L135-2-->L298-6: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_27 |v_ULTIMATE.start_is_transmit1_triggered_#res_15|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27 |v_ULTIMATE.start_is_transmit1_triggered_#res_15|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_27, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_16|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_15|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 63#L298-6true [584] L298-6-->L298-8: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 60#L298-8true [581] L298-8-->L263-3: Formula: (and (= v_~M_E~0_16 1) (= v_~M_E~0_15 2)) InVars {~M_E~0=v_~M_E~0_16} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[~M_E~0] 23#L263-3true [832] L263-3-->L268-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 36#L268-3true [834] L268-3-->L273-3: Formula: (< 1 v_~E_1~0_17) InVars {~E_1~0=v_~E_1~0_17} OutVars{~E_1~0=v_~E_1~0_17} AuxVars[] AssignedVars[] 93#L273-3true [628] L273-3-->L169-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 34#L169-1true [543] L169-1-->L181-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_7 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{~m_st~0=v_~m_st~0_6, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 47#L181-1true [886] L181-1-->L413: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24} OutVars{ULTIMATE.start_start_simulation_#t~ret6=|v_ULTIMATE.start_start_simulation_#t~ret6_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret6, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_~tmp~3] 17#L413true [842] L413-->L413-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 21#L413-1true [659] L413-1-->L169-2: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret5=|v_ULTIMATE.start_stop_simulation_#t~ret5_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret5, ULTIMATE.start_stop_simulation_#res] 31#L169-2true [536] L169-2-->L181-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18 1) (= 0 v_~m_st~0_14)) InVars {~m_st~0=v_~m_st~0_14} OutVars{~m_st~0=v_~m_st~0_14, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 45#L181-2true [888] L181-2-->L368: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_stop_simulation_#t~ret5=|v_ULTIMATE.start_stop_simulation_#t~ret5_4|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret5] 91#L368true [691] L368-->L375: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 70#L375true [894] L375-->L394-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 82#L394-1true 31.95/12.15 [2019-03-28 12:20:17,972 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 31.95/12.15 [2019-03-28 12:20:17,972 INFO L82 PathProgramCache]: Analyzing trace with hash -1901196518, now seen corresponding path program 1 times 31.95/12.15 [2019-03-28 12:20:17,974 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 31.95/12.15 [2019-03-28 12:20:17,975 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 31.95/12.15 [2019-03-28 12:20:17,995 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:17,995 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:17,995 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:18,027 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 31.95/12.15 [2019-03-28 12:20:18,074 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 31.95/12.15 [2019-03-28 12:20:18,076 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 31.95/12.15 [2019-03-28 12:20:18,076 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 31.95/12.15 [2019-03-28 12:20:18,081 INFO L799 eck$LassoCheckResult]: stem already infeasible 31.95/12.15 [2019-03-28 12:20:18,082 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 31.95/12.15 [2019-03-28 12:20:18,082 INFO L82 PathProgramCache]: Analyzing trace with hash 315452392, now seen corresponding path program 1 times 31.95/12.15 [2019-03-28 12:20:18,082 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 31.95/12.15 [2019-03-28 12:20:18,082 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 31.95/12.15 [2019-03-28 12:20:18,083 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:18,083 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:18,083 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:18,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 31.95/12.15 [2019-03-28 12:20:18,130 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 31.95/12.15 [2019-03-28 12:20:18,130 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 31.95/12.15 [2019-03-28 12:20:18,130 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 31.95/12.15 [2019-03-28 12:20:18,132 INFO L811 eck$LassoCheckResult]: loop already infeasible 31.95/12.15 [2019-03-28 12:20:18,147 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 31.95/12.15 [2019-03-28 12:20:18,147 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 31.95/12.15 [2019-03-28 12:20:18,149 INFO L87 Difference]: Start difference. First operand 93 states. Second operand 3 states. 31.95/12.15 [2019-03-28 12:20:18,338 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 31.95/12.15 [2019-03-28 12:20:18,338 INFO L93 Difference]: Finished difference Result 93 states and 207 transitions. 31.95/12.15 [2019-03-28 12:20:18,339 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 31.95/12.15 [2019-03-28 12:20:18,343 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 93 states and 207 transitions. 31.95/12.15 [2019-03-28 12:20:18,347 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 72 31.95/12.15 [2019-03-28 12:20:18,353 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 93 states to 93 states and 207 transitions. 31.95/12.15 [2019-03-28 12:20:18,355 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 93 31.95/12.15 [2019-03-28 12:20:18,355 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 93 31.95/12.15 [2019-03-28 12:20:18,356 INFO L73 IsDeterministic]: Start isDeterministic. Operand 93 states and 207 transitions. 31.95/12.15 [2019-03-28 12:20:18,357 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 31.95/12.15 [2019-03-28 12:20:18,357 INFO L706 BuchiCegarLoop]: Abstraction has 93 states and 207 transitions. 31.95/12.15 [2019-03-28 12:20:18,377 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states and 207 transitions. 31.95/12.15 [2019-03-28 12:20:18,393 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 93. 31.95/12.15 [2019-03-28 12:20:18,394 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 93 states. 31.95/12.15 [2019-03-28 12:20:18,395 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 93 states to 93 states and 207 transitions. 31.95/12.15 [2019-03-28 12:20:18,397 INFO L729 BuchiCegarLoop]: Abstraction has 93 states and 207 transitions. 31.95/12.15 [2019-03-28 12:20:18,397 INFO L609 BuchiCegarLoop]: Abstraction has 93 states and 207 transitions. 31.95/12.15 [2019-03-28 12:20:18,397 INFO L442 BuchiCegarLoop]: ======== Iteration 2============ 31.95/12.15 [2019-03-28 12:20:18,397 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 93 states and 207 transitions. 31.95/12.15 [2019-03-28 12:20:18,399 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 72 31.95/12.15 [2019-03-28 12:20:18,399 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 31.95/12.15 [2019-03-28 12:20:18,399 INFO L119 BuchiIsEmpty]: Starting construction of run 31.95/12.15 [2019-03-28 12:20:18,401 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 31.95/12.15 [2019-03-28 12:20:18,401 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 31.95/12.15 [2019-03-28 12:20:18,402 INFO L794 eck$LassoCheckResult]: Stem: 260#ULTIMATE.startENTRY [871] ULTIMATE.startENTRY-->L144: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~m_pc~0_16 0) (= 0 v_~m_st~0_19) (= 2 v_~E_1~0_28) (= v_~M_E~0_27 2) (= v_~T1_E~0_18 2) (= v_~t1_pc~0_16 0) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= 0 v_~t1_st~0_19)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ULTIMATE.start_start_simulation_#t~ret6=|v_ULTIMATE.start_start_simulation_#t~ret6_4|, ~t1_st~0=v_~t1_st~0_19, ~t1_pc~0=v_~t1_pc~0_16, ~M_E~0=v_~M_E~0_27, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~E_1~0=v_~E_1~0_28, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~T1_E~0=v_~T1_E~0_18, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_19, ~m_pc~0=v_~m_pc~0_16, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_start_simulation_#t~ret6, ~t1_st~0, ~t1_pc~0, ~M_E~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_~kernel_st~0, ~E_1~0, ULTIMATE.start_main_#res, ~T1_E~0, ~t1_i~0, ~m_st~0, ~m_pc~0, ULTIMATE.start_main_~__retres1~3] 261#L144 [557] L144-->L151-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 267#L151-1 [754] L151-1-->L156-1: Formula: (and (< 1 v_~t1_i~0_4) (= v_~t1_st~0_3 2)) InVars {~t1_i~0=v_~t1_i~0_4} OutVars{~t1_st~0=v_~t1_st~0_3, ~t1_i~0=v_~t1_i~0_4} AuxVars[] AssignedVars[~t1_st~0] 275#L156-1 [681] L156-1-->L240-1: Formula: (and (= 0 v_~M_E~0_3) (= v_~M_E~0_2 1)) InVars {~M_E~0=v_~M_E~0_3} OutVars{~M_E~0=v_~M_E~0_2} AuxVars[] AssignedVars[~M_E~0] 282#L240-1 [585] L240-1-->L245-1: Formula: (and (= v_~T1_E~0_2 1) (= 0 v_~T1_E~0_3)) InVars {~T1_E~0=v_~T1_E~0_3} OutVars{~T1_E~0=v_~T1_E~0_2} AuxVars[] AssignedVars[~T1_E~0] 224#L245-1 [761] L245-1-->L250-1: Formula: (< v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 225#L250-1 [679] L250-1-->L105: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_1|, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 281#L105 [601] L105-->L106: Formula: (= v_~m_pc~0_2 1) InVars {~m_pc~0=v_~m_pc~0_2} OutVars{~m_pc~0=v_~m_pc~0_2} AuxVars[] AssignedVars[] 257#L106 [549] L106-->L116: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_4 1) (= 1 v_~M_E~0_8)) InVars {~M_E~0=v_~M_E~0_8} OutVars{~M_E~0=v_~M_E~0_8, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_4} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 258#L116 [872] L116-->L290: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_24 |v_ULTIMATE.start_is_master_triggered_#res_13|) (= |v_ULTIMATE.start_is_master_triggered_#res_13| v_ULTIMATE.start_activate_threads_~tmp~1_24)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_24} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_24, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_24, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_13|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 280#L290 [767] L290-->L290-2: Formula: (and (= v_~m_st~0_4 0) (> 0 v_ULTIMATE.start_activate_threads_~tmp~1_5)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} OutVars{~m_st~0=v_~m_st~0_4, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} AuxVars[] AssignedVars[~m_st~0] 273#L290-2 [569] L290-2-->L124: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 207#L124 [769] L124-->L124-2: Formula: (> v_~t1_pc~0_7 1) InVars {~t1_pc~0=v_~t1_pc~0_7} OutVars{~t1_pc~0=v_~t1_pc~0_7} AuxVars[] AssignedVars[] 199#L124-2 [632] L124-2-->L135: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 200#L135 [873] L135-->L298: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_24 |v_ULTIMATE.start_is_transmit1_triggered_#res_13|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25 |v_ULTIMATE.start_is_transmit1_triggered_#res_13|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_24, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_13|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 212#L298 [773] L298-->L298-2: Formula: (and (= v_~t1_st~0_6 0) (> 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_8)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_8} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_8, ~t1_st~0=v_~t1_st~0_6} AuxVars[] AssignedVars[~t1_st~0] 268#L298-2 [775] L298-2-->L263-1: Formula: (< v_~M_E~0_14 1) InVars {~M_E~0=v_~M_E~0_14} OutVars{~M_E~0=v_~M_E~0_14} AuxVars[] AssignedVars[] 205#L263-1 [777] L263-1-->L268-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 206#L268-1 [779] L268-1-->L394-1: Formula: (> 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 274#L394-1 31.95/12.15 [2019-03-28 12:20:18,403 INFO L796 eck$LassoCheckResult]: Loop: 274#L394-1 [874] L394-1-->L215: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 220#L215 [875] L215-->L169: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_22, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 236#L169 [545] L169-->L181: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_8 1) (= v_~m_st~0_7 0)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 255#L181 [876] L181-->L196: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 286#L196 [878] L196-->L240-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 289#L240-2 [626] L240-2-->L240-4: Formula: (and (= v_~M_E~0_5 1) (= 0 v_~M_E~0_6)) InVars {~M_E~0=v_~M_E~0_6} OutVars{~M_E~0=v_~M_E~0_5} AuxVars[] AssignedVars[~M_E~0] 287#L240-4 [786] L240-4-->L245-3: Formula: (< 0 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 213#L245-3 [641] L245-3-->L250-3: Formula: (and (= v_~E_1~0_6 0) (= v_~E_1~0_5 1)) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_5} AuxVars[] AssignedVars[~E_1~0] 214#L250-3 [676] L250-3-->L105-6: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_4, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_4|, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_2|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 277#L105-6 [624] L105-6-->L106-2: Formula: (= v_~m_pc~0_4 1) InVars {~m_pc~0=v_~m_pc~0_4} OutVars{~m_pc~0=v_~m_pc~0_4} AuxVars[] AssignedVars[] 215#L106-2 [511] L106-2-->L116-2: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_10 1) (= v_~M_E~0_10 1)) InVars {~M_E~0=v_~M_E~0_10} OutVars{~M_E~0=v_~M_E~0_10, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_10} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 217#L116-2 [883] L116-2-->L290-6: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_27 |v_ULTIMATE.start_is_master_triggered_#res_16|) (= |v_ULTIMATE.start_is_master_triggered_#res_16| v_ULTIMATE.start_activate_threads_~tmp~1_27)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_27} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_27, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_27, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_16|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 247#L290-6 [532] L290-6-->L290-8: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 244#L290-8 [524] L290-8-->L124-6: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 226#L124-6 [818] L124-6-->L124-8: Formula: (< v_~t1_pc~0_9 1) InVars {~t1_pc~0=v_~t1_pc~0_9} OutVars{~t1_pc~0=v_~t1_pc~0_9} AuxVars[] AssignedVars[] 227#L124-8 [606] L124-8-->L135-2: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 201#L135-2 [885] L135-2-->L298-6: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_27 |v_ULTIMATE.start_is_transmit1_triggered_#res_15|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27 |v_ULTIMATE.start_is_transmit1_triggered_#res_15|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_27, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_16|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_15|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 202#L298-6 [584] L298-6-->L298-8: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 279#L298-8 [581] L298-8-->L263-3: Formula: (and (= v_~M_E~0_16 1) (= v_~M_E~0_15 2)) InVars {~M_E~0=v_~M_E~0_16} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[~M_E~0] 239#L263-3 [832] L263-3-->L268-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 240#L268-3 [834] L268-3-->L273-3: Formula: (< 1 v_~E_1~0_17) InVars {~E_1~0=v_~E_1~0_17} OutVars{~E_1~0=v_~E_1~0_17} AuxVars[] AssignedVars[] 254#L273-3 [628] L273-3-->L169-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 251#L169-1 [543] L169-1-->L181-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_7 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{~m_st~0=v_~m_st~0_6, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 253#L181-1 [886] L181-1-->L413: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24} OutVars{ULTIMATE.start_start_simulation_#t~ret6=|v_ULTIMATE.start_start_simulation_#t~ret6_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret6, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_~tmp~3] 229#L413 [842] L413-->L413-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 231#L413-1 [659] L413-1-->L169-2: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret5=|v_ULTIMATE.start_stop_simulation_#t~ret5_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret5, ULTIMATE.start_stop_simulation_#res] 235#L169-2 [536] L169-2-->L181-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18 1) (= 0 v_~m_st~0_14)) InVars {~m_st~0=v_~m_st~0_14} OutVars{~m_st~0=v_~m_st~0_14, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 248#L181-2 [888] L181-2-->L368: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_stop_simulation_#t~ret5=|v_ULTIMATE.start_stop_simulation_#t~ret5_4|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret5] 269#L368 [691] L368-->L375: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 284#L375 [894] L375-->L394-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 274#L394-1 31.95/12.15 [2019-03-28 12:20:18,404 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 31.95/12.15 [2019-03-28 12:20:18,404 INFO L82 PathProgramCache]: Analyzing trace with hash 1040461081, now seen corresponding path program 1 times 31.95/12.15 [2019-03-28 12:20:18,404 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 31.95/12.15 [2019-03-28 12:20:18,404 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 31.95/12.15 [2019-03-28 12:20:18,405 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:18,406 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:18,406 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:18,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 31.95/12.15 [2019-03-28 12:20:18,424 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 31.95/12.15 [2019-03-28 12:20:18,424 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 31.95/12.15 [2019-03-28 12:20:18,425 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 31.95/12.15 [2019-03-28 12:20:18,425 INFO L799 eck$LassoCheckResult]: stem already infeasible 31.95/12.15 [2019-03-28 12:20:18,425 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 31.95/12.15 [2019-03-28 12:20:18,425 INFO L82 PathProgramCache]: Analyzing trace with hash 1192873007, now seen corresponding path program 1 times 31.95/12.15 [2019-03-28 12:20:18,426 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 31.95/12.15 [2019-03-28 12:20:18,426 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 31.95/12.15 [2019-03-28 12:20:18,427 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:18,427 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:18,427 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:18,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 31.95/12.15 [2019-03-28 12:20:18,472 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 31.95/12.15 [2019-03-28 12:20:18,472 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 31.95/12.15 [2019-03-28 12:20:18,472 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 31.95/12.15 [2019-03-28 12:20:18,473 INFO L811 eck$LassoCheckResult]: loop already infeasible 31.95/12.15 [2019-03-28 12:20:18,473 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 31.95/12.15 [2019-03-28 12:20:18,473 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 31.95/12.15 [2019-03-28 12:20:18,473 INFO L87 Difference]: Start difference. First operand 93 states and 207 transitions. cyclomatic complexity: 115 Second operand 3 states. 31.95/12.15 [2019-03-28 12:20:18,633 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 31.95/12.15 [2019-03-28 12:20:18,634 INFO L93 Difference]: Finished difference Result 93 states and 206 transitions. 31.95/12.15 [2019-03-28 12:20:18,634 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 31.95/12.15 [2019-03-28 12:20:18,635 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 93 states and 206 transitions. 31.95/12.15 [2019-03-28 12:20:18,637 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 72 31.95/12.15 [2019-03-28 12:20:18,639 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 93 states to 93 states and 206 transitions. 31.95/12.15 [2019-03-28 12:20:18,639 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 93 31.95/12.15 [2019-03-28 12:20:18,639 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 93 31.95/12.15 [2019-03-28 12:20:18,640 INFO L73 IsDeterministic]: Start isDeterministic. Operand 93 states and 206 transitions. 31.95/12.15 [2019-03-28 12:20:18,640 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 31.95/12.15 [2019-03-28 12:20:18,641 INFO L706 BuchiCegarLoop]: Abstraction has 93 states and 206 transitions. 31.95/12.15 [2019-03-28 12:20:18,641 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states and 206 transitions. 31.95/12.15 [2019-03-28 12:20:18,648 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 93. 31.95/12.15 [2019-03-28 12:20:18,648 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 93 states. 31.95/12.15 [2019-03-28 12:20:18,649 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 93 states to 93 states and 206 transitions. 31.95/12.15 [2019-03-28 12:20:18,649 INFO L729 BuchiCegarLoop]: Abstraction has 93 states and 206 transitions. 31.95/12.15 [2019-03-28 12:20:18,649 INFO L609 BuchiCegarLoop]: Abstraction has 93 states and 206 transitions. 31.95/12.15 [2019-03-28 12:20:18,649 INFO L442 BuchiCegarLoop]: ======== Iteration 3============ 31.95/12.15 [2019-03-28 12:20:18,649 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 93 states and 206 transitions. 31.95/12.15 [2019-03-28 12:20:18,651 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 72 31.95/12.15 [2019-03-28 12:20:18,651 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 31.95/12.15 [2019-03-28 12:20:18,651 INFO L119 BuchiIsEmpty]: Starting construction of run 31.95/12.15 [2019-03-28 12:20:18,652 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 31.95/12.15 [2019-03-28 12:20:18,652 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 31.95/12.15 [2019-03-28 12:20:18,654 INFO L794 eck$LassoCheckResult]: Stem: 454#ULTIMATE.startENTRY [871] ULTIMATE.startENTRY-->L144: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~m_pc~0_16 0) (= 0 v_~m_st~0_19) (= 2 v_~E_1~0_28) (= v_~M_E~0_27 2) (= v_~T1_E~0_18 2) (= v_~t1_pc~0_16 0) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= 0 v_~t1_st~0_19)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ULTIMATE.start_start_simulation_#t~ret6=|v_ULTIMATE.start_start_simulation_#t~ret6_4|, ~t1_st~0=v_~t1_st~0_19, ~t1_pc~0=v_~t1_pc~0_16, ~M_E~0=v_~M_E~0_27, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~E_1~0=v_~E_1~0_28, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~T1_E~0=v_~T1_E~0_18, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_19, ~m_pc~0=v_~m_pc~0_16, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_start_simulation_#t~ret6, ~t1_st~0, ~t1_pc~0, ~M_E~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_~kernel_st~0, ~E_1~0, ULTIMATE.start_main_#res, ~T1_E~0, ~t1_i~0, ~m_st~0, ~m_pc~0, ULTIMATE.start_main_~__retres1~3] 455#L144 [557] L144-->L151-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 461#L151-1 [672] L151-1-->L156-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 469#L156-1 [681] L156-1-->L240-1: Formula: (and (= 0 v_~M_E~0_3) (= v_~M_E~0_2 1)) InVars {~M_E~0=v_~M_E~0_3} OutVars{~M_E~0=v_~M_E~0_2} AuxVars[] AssignedVars[~M_E~0] 476#L240-1 [585] L240-1-->L245-1: Formula: (and (= v_~T1_E~0_2 1) (= 0 v_~T1_E~0_3)) InVars {~T1_E~0=v_~T1_E~0_3} OutVars{~T1_E~0=v_~T1_E~0_2} AuxVars[] AssignedVars[~T1_E~0] 418#L245-1 [761] L245-1-->L250-1: Formula: (< v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 419#L250-1 [679] L250-1-->L105: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_1|, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 475#L105 [601] L105-->L106: Formula: (= v_~m_pc~0_2 1) InVars {~m_pc~0=v_~m_pc~0_2} OutVars{~m_pc~0=v_~m_pc~0_2} AuxVars[] AssignedVars[] 451#L106 [549] L106-->L116: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_4 1) (= 1 v_~M_E~0_8)) InVars {~M_E~0=v_~M_E~0_8} OutVars{~M_E~0=v_~M_E~0_8, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_4} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 452#L116 [872] L116-->L290: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_24 |v_ULTIMATE.start_is_master_triggered_#res_13|) (= |v_ULTIMATE.start_is_master_triggered_#res_13| v_ULTIMATE.start_activate_threads_~tmp~1_24)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_24} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_24, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_24, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_13|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 472#L290 [767] L290-->L290-2: Formula: (and (= v_~m_st~0_4 0) (> 0 v_ULTIMATE.start_activate_threads_~tmp~1_5)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} OutVars{~m_st~0=v_~m_st~0_4, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} AuxVars[] AssignedVars[~m_st~0] 467#L290-2 [569] L290-2-->L124: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 401#L124 [769] L124-->L124-2: Formula: (> v_~t1_pc~0_7 1) InVars {~t1_pc~0=v_~t1_pc~0_7} OutVars{~t1_pc~0=v_~t1_pc~0_7} AuxVars[] AssignedVars[] 391#L124-2 [632] L124-2-->L135: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 392#L135 [873] L135-->L298: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_24 |v_ULTIMATE.start_is_transmit1_triggered_#res_13|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25 |v_ULTIMATE.start_is_transmit1_triggered_#res_13|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_24, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_13|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 403#L298 [773] L298-->L298-2: Formula: (and (= v_~t1_st~0_6 0) (> 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_8)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_8} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_8, ~t1_st~0=v_~t1_st~0_6} AuxVars[] AssignedVars[~t1_st~0] 462#L298-2 [775] L298-2-->L263-1: Formula: (< v_~M_E~0_14 1) InVars {~M_E~0=v_~M_E~0_14} OutVars{~M_E~0=v_~M_E~0_14} AuxVars[] AssignedVars[] 397#L263-1 [777] L263-1-->L268-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 398#L268-1 [779] L268-1-->L394-1: Formula: (> 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 468#L394-1 31.95/12.15 [2019-03-28 12:20:18,655 INFO L796 eck$LassoCheckResult]: Loop: 468#L394-1 [874] L394-1-->L215: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 414#L215 [875] L215-->L169: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_22, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 428#L169 [545] L169-->L181: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_8 1) (= v_~m_st~0_7 0)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 448#L181 [876] L181-->L196: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 480#L196 [878] L196-->L240-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 483#L240-2 [626] L240-2-->L240-4: Formula: (and (= v_~M_E~0_5 1) (= 0 v_~M_E~0_6)) InVars {~M_E~0=v_~M_E~0_6} OutVars{~M_E~0=v_~M_E~0_5} AuxVars[] AssignedVars[~M_E~0] 481#L240-4 [786] L240-4-->L245-3: Formula: (< 0 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 407#L245-3 [641] L245-3-->L250-3: Formula: (and (= v_~E_1~0_6 0) (= v_~E_1~0_5 1)) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_5} AuxVars[] AssignedVars[~E_1~0] 408#L250-3 [676] L250-3-->L105-6: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_4, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_4|, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_2|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 471#L105-6 [624] L105-6-->L106-2: Formula: (= v_~m_pc~0_4 1) InVars {~m_pc~0=v_~m_pc~0_4} OutVars{~m_pc~0=v_~m_pc~0_4} AuxVars[] AssignedVars[] 409#L106-2 [511] L106-2-->L116-2: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_10 1) (= v_~M_E~0_10 1)) InVars {~M_E~0=v_~M_E~0_10} OutVars{~M_E~0=v_~M_E~0_10, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_10} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 411#L116-2 [883] L116-2-->L290-6: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_27 |v_ULTIMATE.start_is_master_triggered_#res_16|) (= |v_ULTIMATE.start_is_master_triggered_#res_16| v_ULTIMATE.start_activate_threads_~tmp~1_27)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_27} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_27, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_27, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_16|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 441#L290-6 [532] L290-6-->L290-8: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 440#L290-8 [524] L290-8-->L124-6: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 420#L124-6 [818] L124-6-->L124-8: Formula: (< v_~t1_pc~0_9 1) InVars {~t1_pc~0=v_~t1_pc~0_9} OutVars{~t1_pc~0=v_~t1_pc~0_9} AuxVars[] AssignedVars[] 421#L124-8 [606] L124-8-->L135-2: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 395#L135-2 [885] L135-2-->L298-6: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_27 |v_ULTIMATE.start_is_transmit1_triggered_#res_15|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27 |v_ULTIMATE.start_is_transmit1_triggered_#res_15|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_27, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_16|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_15|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 396#L298-6 [584] L298-6-->L298-8: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 474#L298-8 [581] L298-8-->L263-3: Formula: (and (= v_~M_E~0_16 1) (= v_~M_E~0_15 2)) InVars {~M_E~0=v_~M_E~0_16} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[~M_E~0] 436#L263-3 [832] L263-3-->L268-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 437#L268-3 [834] L268-3-->L273-3: Formula: (< 1 v_~E_1~0_17) InVars {~E_1~0=v_~E_1~0_17} OutVars{~E_1~0=v_~E_1~0_17} AuxVars[] AssignedVars[] 450#L273-3 [628] L273-3-->L169-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 445#L169-1 [543] L169-1-->L181-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_7 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{~m_st~0=v_~m_st~0_6, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 447#L181-1 [886] L181-1-->L413: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24} OutVars{ULTIMATE.start_start_simulation_#t~ret6=|v_ULTIMATE.start_start_simulation_#t~ret6_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret6, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_~tmp~3] 423#L413 [842] L413-->L413-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 425#L413-1 [659] L413-1-->L169-2: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret5=|v_ULTIMATE.start_stop_simulation_#t~ret5_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret5, ULTIMATE.start_stop_simulation_#res] 430#L169-2 [536] L169-2-->L181-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18 1) (= 0 v_~m_st~0_14)) InVars {~m_st~0=v_~m_st~0_14} OutVars{~m_st~0=v_~m_st~0_14, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 442#L181-2 [888] L181-2-->L368: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_stop_simulation_#t~ret5=|v_ULTIMATE.start_stop_simulation_#t~ret5_4|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret5] 463#L368 [691] L368-->L375: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 478#L375 [894] L375-->L394-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 468#L394-1 31.95/12.15 [2019-03-28 12:20:18,655 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 31.95/12.15 [2019-03-28 12:20:18,655 INFO L82 PathProgramCache]: Analyzing trace with hash 1738215623, now seen corresponding path program 1 times 31.95/12.15 [2019-03-28 12:20:18,655 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 31.95/12.15 [2019-03-28 12:20:18,655 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 31.95/12.15 [2019-03-28 12:20:18,656 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:18,656 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:18,657 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:18,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 31.95/12.15 [2019-03-28 12:20:18,675 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 31.95/12.15 [2019-03-28 12:20:18,675 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 31.95/12.15 [2019-03-28 12:20:18,675 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 31.95/12.15 [2019-03-28 12:20:18,676 INFO L799 eck$LassoCheckResult]: stem already infeasible 31.95/12.15 [2019-03-28 12:20:18,676 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 31.95/12.15 [2019-03-28 12:20:18,677 INFO L82 PathProgramCache]: Analyzing trace with hash 1192873007, now seen corresponding path program 2 times 31.95/12.15 [2019-03-28 12:20:18,677 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 31.95/12.15 [2019-03-28 12:20:18,677 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 31.95/12.15 [2019-03-28 12:20:18,678 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:18,678 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:18,678 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:18,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 31.95/12.15 [2019-03-28 12:20:18,705 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 31.95/12.15 [2019-03-28 12:20:18,705 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 31.95/12.15 [2019-03-28 12:20:18,705 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 31.95/12.15 [2019-03-28 12:20:18,706 INFO L811 eck$LassoCheckResult]: loop already infeasible 31.95/12.15 [2019-03-28 12:20:18,706 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 31.95/12.15 [2019-03-28 12:20:18,706 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 31.95/12.15 [2019-03-28 12:20:18,706 INFO L87 Difference]: Start difference. First operand 93 states and 206 transitions. cyclomatic complexity: 114 Second operand 3 states. 31.95/12.15 [2019-03-28 12:20:18,976 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 31.95/12.15 [2019-03-28 12:20:18,976 INFO L93 Difference]: Finished difference Result 163 states and 343 transitions. 31.95/12.15 [2019-03-28 12:20:18,976 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 31.95/12.15 [2019-03-28 12:20:18,977 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 163 states and 343 transitions. 31.95/12.15 [2019-03-28 12:20:18,979 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 142 31.95/12.15 [2019-03-28 12:20:18,981 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 163 states to 163 states and 343 transitions. 31.95/12.15 [2019-03-28 12:20:18,981 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 163 31.95/12.15 [2019-03-28 12:20:18,982 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 163 31.95/12.15 [2019-03-28 12:20:18,982 INFO L73 IsDeterministic]: Start isDeterministic. Operand 163 states and 343 transitions. 31.95/12.15 [2019-03-28 12:20:18,983 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 31.95/12.15 [2019-03-28 12:20:18,983 INFO L706 BuchiCegarLoop]: Abstraction has 163 states and 343 transitions. 31.95/12.15 [2019-03-28 12:20:18,984 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 163 states and 343 transitions. 31.95/12.15 [2019-03-28 12:20:18,993 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 163 to 163. 31.95/12.15 [2019-03-28 12:20:18,994 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 163 states. 31.95/12.15 [2019-03-28 12:20:18,995 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 163 states to 163 states and 343 transitions. 31.95/12.15 [2019-03-28 12:20:18,995 INFO L729 BuchiCegarLoop]: Abstraction has 163 states and 343 transitions. 31.95/12.15 [2019-03-28 12:20:18,995 INFO L609 BuchiCegarLoop]: Abstraction has 163 states and 343 transitions. 31.95/12.15 [2019-03-28 12:20:18,995 INFO L442 BuchiCegarLoop]: ======== Iteration 4============ 31.95/12.15 [2019-03-28 12:20:18,995 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 163 states and 343 transitions. 31.95/12.15 [2019-03-28 12:20:18,997 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 142 31.95/12.15 [2019-03-28 12:20:18,997 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 31.95/12.15 [2019-03-28 12:20:18,997 INFO L119 BuchiIsEmpty]: Starting construction of run 31.95/12.15 [2019-03-28 12:20:18,999 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 31.95/12.15 [2019-03-28 12:20:18,999 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 31.95/12.15 [2019-03-28 12:20:18,999 INFO L794 eck$LassoCheckResult]: Stem: 717#ULTIMATE.startENTRY [871] ULTIMATE.startENTRY-->L144: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~m_pc~0_16 0) (= 0 v_~m_st~0_19) (= 2 v_~E_1~0_28) (= v_~M_E~0_27 2) (= v_~T1_E~0_18 2) (= v_~t1_pc~0_16 0) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= 0 v_~t1_st~0_19)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ULTIMATE.start_start_simulation_#t~ret6=|v_ULTIMATE.start_start_simulation_#t~ret6_4|, ~t1_st~0=v_~t1_st~0_19, ~t1_pc~0=v_~t1_pc~0_16, ~M_E~0=v_~M_E~0_27, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~E_1~0=v_~E_1~0_28, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~T1_E~0=v_~T1_E~0_18, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_19, ~m_pc~0=v_~m_pc~0_16, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_start_simulation_#t~ret6, ~t1_st~0, ~t1_pc~0, ~M_E~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_~kernel_st~0, ~E_1~0, ULTIMATE.start_main_#res, ~T1_E~0, ~t1_i~0, ~m_st~0, ~m_pc~0, ULTIMATE.start_main_~__retres1~3] 718#L144 [557] L144-->L151-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 724#L151-1 [672] L151-1-->L156-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 733#L156-1 [757] L156-1-->L240-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 741#L240-1 [585] L240-1-->L245-1: Formula: (and (= v_~T1_E~0_2 1) (= 0 v_~T1_E~0_3)) InVars {~T1_E~0=v_~T1_E~0_3} OutVars{~T1_E~0=v_~T1_E~0_2} AuxVars[] AssignedVars[~T1_E~0] 681#L245-1 [761] L245-1-->L250-1: Formula: (< v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 682#L250-1 [679] L250-1-->L105: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_1|, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 739#L105 [763] L105-->L105-2: Formula: (> v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 716#L105-2 [594] L105-2-->L116: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 744#L116 [872] L116-->L290: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_24 |v_ULTIMATE.start_is_master_triggered_#res_13|) (= |v_ULTIMATE.start_is_master_triggered_#res_13| v_ULTIMATE.start_activate_threads_~tmp~1_24)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_24} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_24, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_24, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_13|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 738#L290 [767] L290-->L290-2: Formula: (and (= v_~m_st~0_4 0) (> 0 v_ULTIMATE.start_activate_threads_~tmp~1_5)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} OutVars{~m_st~0=v_~m_st~0_4, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} AuxVars[] AssignedVars[~m_st~0] 731#L290-2 [569] L290-2-->L124: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 665#L124 [769] L124-->L124-2: Formula: (> v_~t1_pc~0_7 1) InVars {~t1_pc~0=v_~t1_pc~0_7} OutVars{~t1_pc~0=v_~t1_pc~0_7} AuxVars[] AssignedVars[] 657#L124-2 [632] L124-2-->L135: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 658#L135 [873] L135-->L298: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_24 |v_ULTIMATE.start_is_transmit1_triggered_#res_13|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25 |v_ULTIMATE.start_is_transmit1_triggered_#res_13|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_24, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_13|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 671#L298 [773] L298-->L298-2: Formula: (and (= v_~t1_st~0_6 0) (> 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_8)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_8} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_8, ~t1_st~0=v_~t1_st~0_6} AuxVars[] AssignedVars[~t1_st~0] 725#L298-2 [774] L298-2-->L263-1: Formula: (> v_~M_E~0_14 1) InVars {~M_E~0=v_~M_E~0_14} OutVars{~M_E~0=v_~M_E~0_14} AuxVars[] AssignedVars[] 663#L263-1 [777] L263-1-->L268-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 664#L268-1 [779] L268-1-->L394-1: Formula: (> 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 732#L394-1 31.95/12.15 [2019-03-28 12:20:19,000 INFO L796 eck$LassoCheckResult]: Loop: 732#L394-1 [874] L394-1-->L215: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 678#L215 [875] L215-->L169: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_22, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 691#L169 [545] L169-->L181: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_8 1) (= v_~m_st~0_7 0)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 712#L181 [876] L181-->L196: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 748#L196 [878] L196-->L240-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 753#L240-2 [783] L240-2-->L240-4: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 751#L240-4 [786] L240-4-->L245-3: Formula: (< 0 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 672#L245-3 [641] L245-3-->L250-3: Formula: (and (= v_~E_1~0_6 0) (= v_~E_1~0_5 1)) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_5} AuxVars[] AssignedVars[~E_1~0] 673#L250-3 [676] L250-3-->L105-6: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_4, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_4|, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_2|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 735#L105-6 [794] L105-6-->L105-8: Formula: (> v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 675#L105-8 [619] L105-8-->L116-2: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 745#L116-2 [883] L116-2-->L290-6: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_27 |v_ULTIMATE.start_is_master_triggered_#res_16|) (= |v_ULTIMATE.start_is_master_triggered_#res_16| v_ULTIMATE.start_activate_threads_~tmp~1_27)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_27} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_27, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_27, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_16|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 704#L290-6 [532] L290-6-->L290-8: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 705#L290-8 [524] L290-8-->L124-6: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 767#L124-6 [649] L124-6-->L125-2: Formula: (= v_~t1_pc~0_8 1) InVars {~t1_pc~0=v_~t1_pc~0_8} OutVars{~t1_pc~0=v_~t1_pc~0_8} AuxVars[] AssignedVars[] 765#L125-2 [528] L125-2-->L135-2: Formula: (and (= 1 v_~E_1~0_10) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_10 1)) InVars {~E_1~0=v_~E_1~0_10} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_10, ~E_1~0=v_~E_1~0_10} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 764#L135-2 [885] L135-2-->L298-6: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_27 |v_ULTIMATE.start_is_transmit1_triggered_#res_15|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27 |v_ULTIMATE.start_is_transmit1_triggered_#res_15|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_27, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_16|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_15|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 740#L298-6 [584] L298-6-->L298-8: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 737#L298-8 [829] L298-8-->L263-3: Formula: (> v_~M_E~0_17 1) InVars {~M_E~0=v_~M_E~0_17} OutVars{~M_E~0=v_~M_E~0_17} AuxVars[] AssignedVars[] 696#L263-3 [832] L263-3-->L268-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 697#L268-3 [834] L268-3-->L273-3: Formula: (< 1 v_~E_1~0_17) InVars {~E_1~0=v_~E_1~0_17} OutVars{~E_1~0=v_~E_1~0_17} AuxVars[] AssignedVars[] 714#L273-3 [628] L273-3-->L169-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 709#L169-1 [543] L169-1-->L181-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_7 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{~m_st~0=v_~m_st~0_6, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 711#L181-1 [886] L181-1-->L413: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24} OutVars{ULTIMATE.start_start_simulation_#t~ret6=|v_ULTIMATE.start_start_simulation_#t~ret6_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret6, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_~tmp~3] 686#L413 [842] L413-->L413-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 688#L413-1 [659] L413-1-->L169-2: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret5=|v_ULTIMATE.start_stop_simulation_#t~ret5_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret5, ULTIMATE.start_stop_simulation_#res] 693#L169-2 [536] L169-2-->L181-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18 1) (= 0 v_~m_st~0_14)) InVars {~m_st~0=v_~m_st~0_14} OutVars{~m_st~0=v_~m_st~0_14, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 706#L181-2 [888] L181-2-->L368: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_stop_simulation_#t~ret5=|v_ULTIMATE.start_stop_simulation_#t~ret5_4|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret5] 726#L368 [691] L368-->L375: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 743#L375 [894] L375-->L394-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 732#L394-1 31.95/12.15 [2019-03-28 12:20:19,001 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 31.95/12.15 [2019-03-28 12:20:19,001 INFO L82 PathProgramCache]: Analyzing trace with hash 1770454341, now seen corresponding path program 1 times 31.95/12.15 [2019-03-28 12:20:19,001 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 31.95/12.15 [2019-03-28 12:20:19,001 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 31.95/12.15 [2019-03-28 12:20:19,002 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:19,003 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:19,003 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:19,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 31.95/12.15 [2019-03-28 12:20:19,020 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 31.95/12.15 [2019-03-28 12:20:19,020 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 31.95/12.15 [2019-03-28 12:20:19,020 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 31.95/12.15 [2019-03-28 12:20:19,021 INFO L799 eck$LassoCheckResult]: stem already infeasible 31.95/12.15 [2019-03-28 12:20:19,021 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 31.95/12.15 [2019-03-28 12:20:19,021 INFO L82 PathProgramCache]: Analyzing trace with hash -1736124019, now seen corresponding path program 1 times 31.95/12.15 [2019-03-28 12:20:19,021 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 31.95/12.15 [2019-03-28 12:20:19,021 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 31.95/12.15 [2019-03-28 12:20:19,022 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:19,022 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:19,022 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:19,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 31.95/12.15 [2019-03-28 12:20:19,046 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 31.95/12.15 [2019-03-28 12:20:19,046 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 31.95/12.15 [2019-03-28 12:20:19,047 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 31.95/12.15 [2019-03-28 12:20:19,047 INFO L811 eck$LassoCheckResult]: loop already infeasible 31.95/12.15 [2019-03-28 12:20:19,048 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 31.95/12.15 [2019-03-28 12:20:19,048 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 31.95/12.15 [2019-03-28 12:20:19,048 INFO L87 Difference]: Start difference. First operand 163 states and 343 transitions. cyclomatic complexity: 181 Second operand 3 states. 31.95/12.15 [2019-03-28 12:20:19,190 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 31.95/12.15 [2019-03-28 12:20:19,190 INFO L93 Difference]: Finished difference Result 163 states and 327 transitions. 31.95/12.15 [2019-03-28 12:20:19,190 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 31.95/12.15 [2019-03-28 12:20:19,191 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 163 states and 327 transitions. 31.95/12.15 [2019-03-28 12:20:19,192 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 142 31.95/12.15 [2019-03-28 12:20:19,194 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 163 states to 163 states and 327 transitions. 31.95/12.15 [2019-03-28 12:20:19,195 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 163 31.95/12.15 [2019-03-28 12:20:19,195 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 163 31.95/12.15 [2019-03-28 12:20:19,195 INFO L73 IsDeterministic]: Start isDeterministic. Operand 163 states and 327 transitions. 31.95/12.15 [2019-03-28 12:20:19,196 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 31.95/12.15 [2019-03-28 12:20:19,197 INFO L706 BuchiCegarLoop]: Abstraction has 163 states and 327 transitions. 31.95/12.15 [2019-03-28 12:20:19,197 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 163 states and 327 transitions. 31.95/12.15 [2019-03-28 12:20:19,205 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 163 to 163. 31.95/12.15 [2019-03-28 12:20:19,205 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 163 states. 31.95/12.15 [2019-03-28 12:20:19,206 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 163 states to 163 states and 327 transitions. 31.95/12.15 [2019-03-28 12:20:19,206 INFO L729 BuchiCegarLoop]: Abstraction has 163 states and 327 transitions. 31.95/12.15 [2019-03-28 12:20:19,206 INFO L609 BuchiCegarLoop]: Abstraction has 163 states and 327 transitions. 31.95/12.15 [2019-03-28 12:20:19,206 INFO L442 BuchiCegarLoop]: ======== Iteration 5============ 31.95/12.15 [2019-03-28 12:20:19,207 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 163 states and 327 transitions. 31.95/12.15 [2019-03-28 12:20:19,208 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 142 31.95/12.15 [2019-03-28 12:20:19,208 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 31.95/12.15 [2019-03-28 12:20:19,208 INFO L119 BuchiIsEmpty]: Starting construction of run 31.95/12.15 [2019-03-28 12:20:19,209 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 31.95/12.15 [2019-03-28 12:20:19,209 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 31.95/12.15 [2019-03-28 12:20:19,210 INFO L794 eck$LassoCheckResult]: Stem: 1050#ULTIMATE.startENTRY [871] ULTIMATE.startENTRY-->L144: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~m_pc~0_16 0) (= 0 v_~m_st~0_19) (= 2 v_~E_1~0_28) (= v_~M_E~0_27 2) (= v_~T1_E~0_18 2) (= v_~t1_pc~0_16 0) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= 0 v_~t1_st~0_19)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ULTIMATE.start_start_simulation_#t~ret6=|v_ULTIMATE.start_start_simulation_#t~ret6_4|, ~t1_st~0=v_~t1_st~0_19, ~t1_pc~0=v_~t1_pc~0_16, ~M_E~0=v_~M_E~0_27, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~E_1~0=v_~E_1~0_28, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~T1_E~0=v_~T1_E~0_18, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_19, ~m_pc~0=v_~m_pc~0_16, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_start_simulation_#t~ret6, ~t1_st~0, ~t1_pc~0, ~M_E~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_~kernel_st~0, ~E_1~0, ULTIMATE.start_main_#res, ~T1_E~0, ~t1_i~0, ~m_st~0, ~m_pc~0, ULTIMATE.start_main_~__retres1~3] 1051#L144 [557] L144-->L151-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 1057#L151-1 [672] L151-1-->L156-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 1066#L156-1 [757] L156-1-->L240-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 1073#L240-1 [759] L240-1-->L245-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 1015#L245-1 [761] L245-1-->L250-1: Formula: (< v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 1016#L250-1 [679] L250-1-->L105: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_1|, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 1072#L105 [763] L105-->L105-2: Formula: (> v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 1049#L105-2 [594] L105-2-->L116: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 1076#L116 [872] L116-->L290: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_24 |v_ULTIMATE.start_is_master_triggered_#res_13|) (= |v_ULTIMATE.start_is_master_triggered_#res_13| v_ULTIMATE.start_activate_threads_~tmp~1_24)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_24} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_24, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_24, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_13|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 1069#L290 [767] L290-->L290-2: Formula: (and (= v_~m_st~0_4 0) (> 0 v_ULTIMATE.start_activate_threads_~tmp~1_5)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} OutVars{~m_st~0=v_~m_st~0_4, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} AuxVars[] AssignedVars[~m_st~0] 1064#L290-2 [569] L290-2-->L124: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 999#L124 [769] L124-->L124-2: Formula: (> v_~t1_pc~0_7 1) InVars {~t1_pc~0=v_~t1_pc~0_7} OutVars{~t1_pc~0=v_~t1_pc~0_7} AuxVars[] AssignedVars[] 989#L124-2 [632] L124-2-->L135: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 990#L135 [873] L135-->L298: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_24 |v_ULTIMATE.start_is_transmit1_triggered_#res_13|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25 |v_ULTIMATE.start_is_transmit1_triggered_#res_13|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_24, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_13|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 1001#L298 [773] L298-->L298-2: Formula: (and (= v_~t1_st~0_6 0) (> 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_8)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_8} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_8, ~t1_st~0=v_~t1_st~0_6} AuxVars[] AssignedVars[~t1_st~0] 1058#L298-2 [774] L298-2-->L263-1: Formula: (> v_~M_E~0_14 1) InVars {~M_E~0=v_~M_E~0_14} OutVars{~M_E~0=v_~M_E~0_14} AuxVars[] AssignedVars[] 995#L263-1 [777] L263-1-->L268-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 996#L268-1 [779] L268-1-->L394-1: Formula: (> 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 1065#L394-1 31.95/12.15 [2019-03-28 12:20:19,211 INFO L796 eck$LassoCheckResult]: Loop: 1065#L394-1 [874] L394-1-->L215: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 1012#L215 [875] L215-->L169: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_22, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 1025#L169 [545] L169-->L181: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_8 1) (= v_~m_st~0_7 0)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 1045#L181 [876] L181-->L196: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 1080#L196 [878] L196-->L240-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 1083#L240-2 [783] L240-2-->L240-4: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 1081#L240-4 [786] L240-4-->L245-3: Formula: (< 0 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 1006#L245-3 [641] L245-3-->L250-3: Formula: (and (= v_~E_1~0_6 0) (= v_~E_1~0_5 1)) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_5} AuxVars[] AssignedVars[~E_1~0] 1007#L250-3 [676] L250-3-->L105-6: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_4, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_4|, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_2|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 1068#L105-6 [794] L105-6-->L105-8: Formula: (> v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 1009#L105-8 [619] L105-8-->L116-2: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 1077#L116-2 [883] L116-2-->L290-6: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_27 |v_ULTIMATE.start_is_master_triggered_#res_16|) (= |v_ULTIMATE.start_is_master_triggered_#res_16| v_ULTIMATE.start_activate_threads_~tmp~1_27)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_27} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_27, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_27, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_16|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 1038#L290-6 [532] L290-6-->L290-8: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 1035#L290-8 [524] L290-8-->L124-6: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 1017#L124-6 [818] L124-6-->L124-8: Formula: (< v_~t1_pc~0_9 1) InVars {~t1_pc~0=v_~t1_pc~0_9} OutVars{~t1_pc~0=v_~t1_pc~0_9} AuxVars[] AssignedVars[] 1018#L124-8 [606] L124-8-->L135-2: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 993#L135-2 [885] L135-2-->L298-6: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_27 |v_ULTIMATE.start_is_transmit1_triggered_#res_15|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27 |v_ULTIMATE.start_is_transmit1_triggered_#res_15|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_27, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_16|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_15|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 994#L298-6 [584] L298-6-->L298-8: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 1071#L298-8 [829] L298-8-->L263-3: Formula: (> v_~M_E~0_17 1) InVars {~M_E~0=v_~M_E~0_17} OutVars{~M_E~0=v_~M_E~0_17} AuxVars[] AssignedVars[] 1030#L263-3 [832] L263-3-->L268-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 1031#L268-3 [834] L268-3-->L273-3: Formula: (< 1 v_~E_1~0_17) InVars {~E_1~0=v_~E_1~0_17} OutVars{~E_1~0=v_~E_1~0_17} AuxVars[] AssignedVars[] 1047#L273-3 [628] L273-3-->L169-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 1042#L169-1 [543] L169-1-->L181-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_7 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{~m_st~0=v_~m_st~0_6, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 1044#L181-1 [886] L181-1-->L413: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24} OutVars{ULTIMATE.start_start_simulation_#t~ret6=|v_ULTIMATE.start_start_simulation_#t~ret6_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret6, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_~tmp~3] 1020#L413 [842] L413-->L413-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 1022#L413-1 [659] L413-1-->L169-2: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret5=|v_ULTIMATE.start_stop_simulation_#t~ret5_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret5, ULTIMATE.start_stop_simulation_#res] 1027#L169-2 [536] L169-2-->L181-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18 1) (= 0 v_~m_st~0_14)) InVars {~m_st~0=v_~m_st~0_14} OutVars{~m_st~0=v_~m_st~0_14, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 1039#L181-2 [888] L181-2-->L368: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_stop_simulation_#t~ret5=|v_ULTIMATE.start_stop_simulation_#t~ret5_4|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret5] 1059#L368 [691] L368-->L375: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 1075#L375 [894] L375-->L394-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 1065#L394-1 31.95/12.15 [2019-03-28 12:20:19,211 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 31.95/12.15 [2019-03-28 12:20:19,211 INFO L82 PathProgramCache]: Analyzing trace with hash 2091464051, now seen corresponding path program 1 times 31.95/12.15 [2019-03-28 12:20:19,212 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 31.95/12.15 [2019-03-28 12:20:19,212 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 31.95/12.15 [2019-03-28 12:20:19,213 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:19,213 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:19,213 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:19,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 31.95/12.15 [2019-03-28 12:20:19,232 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 31.95/12.15 [2019-03-28 12:20:19,232 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 31.95/12.15 [2019-03-28 12:20:19,232 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 31.95/12.15 [2019-03-28 12:20:19,232 INFO L799 eck$LassoCheckResult]: stem already infeasible 31.95/12.15 [2019-03-28 12:20:19,233 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 31.95/12.15 [2019-03-28 12:20:19,233 INFO L82 PathProgramCache]: Analyzing trace with hash -492129902, now seen corresponding path program 1 times 31.95/12.15 [2019-03-28 12:20:19,233 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 31.95/12.15 [2019-03-28 12:20:19,233 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 31.95/12.15 [2019-03-28 12:20:19,234 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:19,234 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:19,234 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:19,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 31.95/12.15 [2019-03-28 12:20:19,254 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 31.95/12.15 [2019-03-28 12:20:19,255 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 31.95/12.15 [2019-03-28 12:20:19,255 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 31.95/12.15 [2019-03-28 12:20:19,255 INFO L811 eck$LassoCheckResult]: loop already infeasible 31.95/12.15 [2019-03-28 12:20:19,255 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 31.95/12.15 [2019-03-28 12:20:19,256 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 31.95/12.15 [2019-03-28 12:20:19,256 INFO L87 Difference]: Start difference. First operand 163 states and 327 transitions. cyclomatic complexity: 165 Second operand 3 states. 31.95/12.15 [2019-03-28 12:20:19,380 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 31.95/12.15 [2019-03-28 12:20:19,380 INFO L93 Difference]: Finished difference Result 171 states and 313 transitions. 31.95/12.15 [2019-03-28 12:20:19,381 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 31.95/12.15 [2019-03-28 12:20:19,381 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 171 states and 313 transitions. 31.95/12.15 [2019-03-28 12:20:19,383 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 150 31.95/12.15 [2019-03-28 12:20:19,384 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 171 states to 171 states and 313 transitions. 31.95/12.15 [2019-03-28 12:20:19,385 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 171 31.95/12.15 [2019-03-28 12:20:19,385 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 171 31.95/12.15 [2019-03-28 12:20:19,385 INFO L73 IsDeterministic]: Start isDeterministic. Operand 171 states and 313 transitions. 31.95/12.15 [2019-03-28 12:20:19,386 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 31.95/12.15 [2019-03-28 12:20:19,386 INFO L706 BuchiCegarLoop]: Abstraction has 171 states and 313 transitions. 31.95/12.15 [2019-03-28 12:20:19,386 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 171 states and 313 transitions. 31.95/12.15 [2019-03-28 12:20:19,392 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 171 to 163. 31.95/12.15 [2019-03-28 12:20:19,392 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 163 states. 31.95/12.15 [2019-03-28 12:20:19,393 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 163 states to 163 states and 301 transitions. 31.95/12.15 [2019-03-28 12:20:19,393 INFO L729 BuchiCegarLoop]: Abstraction has 163 states and 301 transitions. 31.95/12.15 [2019-03-28 12:20:19,393 INFO L609 BuchiCegarLoop]: Abstraction has 163 states and 301 transitions. 31.95/12.15 [2019-03-28 12:20:19,394 INFO L442 BuchiCegarLoop]: ======== Iteration 6============ 31.95/12.15 [2019-03-28 12:20:19,394 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 163 states and 301 transitions. 31.95/12.15 [2019-03-28 12:20:19,395 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 142 31.95/12.15 [2019-03-28 12:20:19,395 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 31.95/12.15 [2019-03-28 12:20:19,395 INFO L119 BuchiIsEmpty]: Starting construction of run 31.95/12.15 [2019-03-28 12:20:19,396 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 31.95/12.15 [2019-03-28 12:20:19,396 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 31.95/12.15 [2019-03-28 12:20:19,397 INFO L794 eck$LassoCheckResult]: Stem: 1395#ULTIMATE.startENTRY [871] ULTIMATE.startENTRY-->L144: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~m_pc~0_16 0) (= 0 v_~m_st~0_19) (= 2 v_~E_1~0_28) (= v_~M_E~0_27 2) (= v_~T1_E~0_18 2) (= v_~t1_pc~0_16 0) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= 0 v_~t1_st~0_19)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ULTIMATE.start_start_simulation_#t~ret6=|v_ULTIMATE.start_start_simulation_#t~ret6_4|, ~t1_st~0=v_~t1_st~0_19, ~t1_pc~0=v_~t1_pc~0_16, ~M_E~0=v_~M_E~0_27, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~E_1~0=v_~E_1~0_28, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~T1_E~0=v_~T1_E~0_18, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_19, ~m_pc~0=v_~m_pc~0_16, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_start_simulation_#t~ret6, ~t1_st~0, ~t1_pc~0, ~M_E~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_~kernel_st~0, ~E_1~0, ULTIMATE.start_main_#res, ~T1_E~0, ~t1_i~0, ~m_st~0, ~m_pc~0, ULTIMATE.start_main_~__retres1~3] 1396#L144 [557] L144-->L151-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 1402#L151-1 [672] L151-1-->L156-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 1413#L156-1 [757] L156-1-->L240-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 1420#L240-1 [759] L240-1-->L245-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 1357#L245-1 [760] L245-1-->L250-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 1358#L250-1 [679] L250-1-->L105: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_1|, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 1419#L105 [763] L105-->L105-2: Formula: (> v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 1394#L105-2 [594] L105-2-->L116: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 1424#L116 [872] L116-->L290: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_24 |v_ULTIMATE.start_is_master_triggered_#res_13|) (= |v_ULTIMATE.start_is_master_triggered_#res_13| v_ULTIMATE.start_activate_threads_~tmp~1_24)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_24} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_24, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_24, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_13|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 1418#L290 [767] L290-->L290-2: Formula: (and (= v_~m_st~0_4 0) (> 0 v_ULTIMATE.start_activate_threads_~tmp~1_5)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} OutVars{~m_st~0=v_~m_st~0_4, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} AuxVars[] AssignedVars[~m_st~0] 1411#L290-2 [569] L290-2-->L124: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 1341#L124 [769] L124-->L124-2: Formula: (> v_~t1_pc~0_7 1) InVars {~t1_pc~0=v_~t1_pc~0_7} OutVars{~t1_pc~0=v_~t1_pc~0_7} AuxVars[] AssignedVars[] 1333#L124-2 [632] L124-2-->L135: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 1334#L135 [873] L135-->L298: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_24 |v_ULTIMATE.start_is_transmit1_triggered_#res_13|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25 |v_ULTIMATE.start_is_transmit1_triggered_#res_13|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_24, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_13|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 1343#L298 [773] L298-->L298-2: Formula: (and (= v_~t1_st~0_6 0) (> 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_8)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_8} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_8, ~t1_st~0=v_~t1_st~0_6} AuxVars[] AssignedVars[~t1_st~0] 1404#L298-2 [774] L298-2-->L263-1: Formula: (> v_~M_E~0_14 1) InVars {~M_E~0=v_~M_E~0_14} OutVars{~M_E~0=v_~M_E~0_14} AuxVars[] AssignedVars[] 1339#L263-1 [777] L263-1-->L268-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 1340#L268-1 [778] L268-1-->L394-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 1412#L394-1 31.95/12.15 [2019-03-28 12:20:19,398 INFO L796 eck$LassoCheckResult]: Loop: 1412#L394-1 [874] L394-1-->L215: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 1456#L215 [875] L215-->L169: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_22, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 1454#L169 [545] L169-->L181: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_8 1) (= v_~m_st~0_7 0)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 1451#L181 [876] L181-->L196: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 1440#L196 [878] L196-->L240-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 1439#L240-2 [783] L240-2-->L240-4: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 1435#L240-4 [786] L240-4-->L245-3: Formula: (< 0 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 1348#L245-3 [789] L245-3-->L250-3: Formula: (> v_~E_1~0_7 0) InVars {~E_1~0=v_~E_1~0_7} OutVars{~E_1~0=v_~E_1~0_7} AuxVars[] AssignedVars[] 1349#L250-3 [676] L250-3-->L105-6: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_4, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_4|, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_2|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 1415#L105-6 [794] L105-6-->L105-8: Formula: (> v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 1351#L105-8 [619] L105-8-->L116-2: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 1434#L116-2 [883] L116-2-->L290-6: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_27 |v_ULTIMATE.start_is_master_triggered_#res_16|) (= |v_ULTIMATE.start_is_master_triggered_#res_16| v_ULTIMATE.start_activate_threads_~tmp~1_27)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_27} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_27, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_27, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_16|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 1382#L290-6 [532] L290-6-->L290-8: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 1383#L290-8 [524] L290-8-->L124-6: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 1359#L124-6 [818] L124-6-->L124-8: Formula: (< v_~t1_pc~0_9 1) InVars {~t1_pc~0=v_~t1_pc~0_9} OutVars{~t1_pc~0=v_~t1_pc~0_9} AuxVars[] AssignedVars[] 1360#L124-8 [606] L124-8-->L135-2: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 1335#L135-2 [885] L135-2-->L298-6: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_27 |v_ULTIMATE.start_is_transmit1_triggered_#res_15|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27 |v_ULTIMATE.start_is_transmit1_triggered_#res_15|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_27, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_16|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_15|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 1336#L298-6 [584] L298-6-->L298-8: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 1417#L298-8 [829] L298-8-->L263-3: Formula: (> v_~M_E~0_17 1) InVars {~M_E~0=v_~M_E~0_17} OutVars{~M_E~0=v_~M_E~0_17} AuxVars[] AssignedVars[] 1373#L263-3 [832] L263-3-->L268-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 1374#L268-3 [834] L268-3-->L273-3: Formula: (< 1 v_~E_1~0_17) InVars {~E_1~0=v_~E_1~0_17} OutVars{~E_1~0=v_~E_1~0_17} AuxVars[] AssignedVars[] 1390#L273-3 [628] L273-3-->L169-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 1387#L169-1 [543] L169-1-->L181-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_7 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{~m_st~0=v_~m_st~0_6, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 1389#L181-1 [886] L181-1-->L413: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24} OutVars{ULTIMATE.start_start_simulation_#t~ret6=|v_ULTIMATE.start_start_simulation_#t~ret6_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret6, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_~tmp~3] 1362#L413 [842] L413-->L413-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 1364#L413-1 [659] L413-1-->L169-2: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret5=|v_ULTIMATE.start_stop_simulation_#t~ret5_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret5, ULTIMATE.start_stop_simulation_#res] 1370#L169-2 [536] L169-2-->L181-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18 1) (= 0 v_~m_st~0_14)) InVars {~m_st~0=v_~m_st~0_14} OutVars{~m_st~0=v_~m_st~0_14, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 1384#L181-2 [888] L181-2-->L368: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_stop_simulation_#t~ret5=|v_ULTIMATE.start_stop_simulation_#t~ret5_4|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret5] 1405#L368 [691] L368-->L375: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 1423#L375 [894] L375-->L394-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 1412#L394-1 31.95/12.15 [2019-03-28 12:20:19,398 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 31.95/12.15 [2019-03-28 12:20:19,398 INFO L82 PathProgramCache]: Analyzing trace with hash -1697944621, now seen corresponding path program 1 times 31.95/12.15 [2019-03-28 12:20:19,398 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 31.95/12.15 [2019-03-28 12:20:19,398 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 31.95/12.15 [2019-03-28 12:20:19,399 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:19,399 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:19,400 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:19,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 31.95/12.15 [2019-03-28 12:20:19,422 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 31.95/12.15 [2019-03-28 12:20:19,423 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 31.95/12.15 [2019-03-28 12:20:19,423 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 31.95/12.15 [2019-03-28 12:20:19,423 INFO L799 eck$LassoCheckResult]: stem already infeasible 31.95/12.15 [2019-03-28 12:20:19,423 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 31.95/12.15 [2019-03-28 12:20:19,423 INFO L82 PathProgramCache]: Analyzing trace with hash -950580442, now seen corresponding path program 1 times 31.95/12.15 [2019-03-28 12:20:19,424 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 31.95/12.15 [2019-03-28 12:20:19,424 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 31.95/12.15 [2019-03-28 12:20:19,425 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:19,425 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:19,425 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:19,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 31.95/12.15 [2019-03-28 12:20:19,445 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 31.95/12.15 [2019-03-28 12:20:19,445 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 31.95/12.15 [2019-03-28 12:20:19,445 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 31.95/12.15 [2019-03-28 12:20:19,446 INFO L811 eck$LassoCheckResult]: loop already infeasible 31.95/12.15 [2019-03-28 12:20:19,446 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 31.95/12.15 [2019-03-28 12:20:19,446 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 31.95/12.15 [2019-03-28 12:20:19,446 INFO L87 Difference]: Start difference. First operand 163 states and 301 transitions. cyclomatic complexity: 139 Second operand 3 states. 31.95/12.15 [2019-03-28 12:20:19,622 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 31.95/12.15 [2019-03-28 12:20:19,623 INFO L93 Difference]: Finished difference Result 289 states and 525 transitions. 31.95/12.15 [2019-03-28 12:20:19,623 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 31.95/12.15 [2019-03-28 12:20:19,623 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 289 states and 525 transitions. 31.95/12.15 [2019-03-28 12:20:19,626 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 269 31.95/12.15 [2019-03-28 12:20:19,628 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 289 states to 289 states and 525 transitions. 31.95/12.15 [2019-03-28 12:20:19,628 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 289 31.95/12.15 [2019-03-28 12:20:19,629 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 289 31.95/12.15 [2019-03-28 12:20:19,629 INFO L73 IsDeterministic]: Start isDeterministic. Operand 289 states and 525 transitions. 31.95/12.15 [2019-03-28 12:20:19,630 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 31.95/12.15 [2019-03-28 12:20:19,630 INFO L706 BuchiCegarLoop]: Abstraction has 289 states and 525 transitions. 31.95/12.15 [2019-03-28 12:20:19,630 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 289 states and 525 transitions. 31.95/12.15 [2019-03-28 12:20:19,637 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 289 to 267. 31.95/12.15 [2019-03-28 12:20:19,638 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 267 states. 31.95/12.15 [2019-03-28 12:20:19,639 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 267 states to 267 states and 487 transitions. 31.95/12.15 [2019-03-28 12:20:19,639 INFO L729 BuchiCegarLoop]: Abstraction has 267 states and 487 transitions. 31.95/12.15 [2019-03-28 12:20:19,639 INFO L609 BuchiCegarLoop]: Abstraction has 267 states and 487 transitions. 31.95/12.15 [2019-03-28 12:20:19,639 INFO L442 BuchiCegarLoop]: ======== Iteration 7============ 31.95/12.15 [2019-03-28 12:20:19,639 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 267 states and 487 transitions. 31.95/12.15 [2019-03-28 12:20:19,641 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 247 31.95/12.15 [2019-03-28 12:20:19,641 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 31.95/12.15 [2019-03-28 12:20:19,642 INFO L119 BuchiIsEmpty]: Starting construction of run 31.95/12.15 [2019-03-28 12:20:19,642 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 31.95/12.15 [2019-03-28 12:20:19,642 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 31.95/12.15 [2019-03-28 12:20:19,643 INFO L794 eck$LassoCheckResult]: Stem: 1855#ULTIMATE.startENTRY [871] ULTIMATE.startENTRY-->L144: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~m_pc~0_16 0) (= 0 v_~m_st~0_19) (= 2 v_~E_1~0_28) (= v_~M_E~0_27 2) (= v_~T1_E~0_18 2) (= v_~t1_pc~0_16 0) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= 0 v_~t1_st~0_19)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ULTIMATE.start_start_simulation_#t~ret6=|v_ULTIMATE.start_start_simulation_#t~ret6_4|, ~t1_st~0=v_~t1_st~0_19, ~t1_pc~0=v_~t1_pc~0_16, ~M_E~0=v_~M_E~0_27, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~E_1~0=v_~E_1~0_28, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~T1_E~0=v_~T1_E~0_18, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_19, ~m_pc~0=v_~m_pc~0_16, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_start_simulation_#t~ret6, ~t1_st~0, ~t1_pc~0, ~M_E~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_~kernel_st~0, ~E_1~0, ULTIMATE.start_main_#res, ~T1_E~0, ~t1_i~0, ~m_st~0, ~m_pc~0, ULTIMATE.start_main_~__retres1~3] 1856#L144 [557] L144-->L151-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 1862#L151-1 [672] L151-1-->L156-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 1873#L156-1 [757] L156-1-->L240-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 1883#L240-1 [759] L240-1-->L245-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 1817#L245-1 [760] L245-1-->L250-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 1818#L250-1 [679] L250-1-->L105: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_1|, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 1880#L105 [762] L105-->L105-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 1888#L105-2 [594] L105-2-->L116: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 1889#L116 [872] L116-->L290: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_24 |v_ULTIMATE.start_is_master_triggered_#res_13|) (= |v_ULTIMATE.start_is_master_triggered_#res_13| v_ULTIMATE.start_activate_threads_~tmp~1_24)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_24} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_24, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_24, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_13|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 1879#L290 [767] L290-->L290-2: Formula: (and (= v_~m_st~0_4 0) (> 0 v_ULTIMATE.start_activate_threads_~tmp~1_5)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} OutVars{~m_st~0=v_~m_st~0_4, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} AuxVars[] AssignedVars[~m_st~0] 1871#L290-2 [569] L290-2-->L124: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 1801#L124 [769] L124-->L124-2: Formula: (> v_~t1_pc~0_7 1) InVars {~t1_pc~0=v_~t1_pc~0_7} OutVars{~t1_pc~0=v_~t1_pc~0_7} AuxVars[] AssignedVars[] 1793#L124-2 [632] L124-2-->L135: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 1794#L135 [873] L135-->L298: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_24 |v_ULTIMATE.start_is_transmit1_triggered_#res_13|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25 |v_ULTIMATE.start_is_transmit1_triggered_#res_13|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_24, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_13|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 1807#L298 [773] L298-->L298-2: Formula: (and (= v_~t1_st~0_6 0) (> 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_8)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_8} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_8, ~t1_st~0=v_~t1_st~0_6} AuxVars[] AssignedVars[~t1_st~0] 1864#L298-2 [774] L298-2-->L263-1: Formula: (> v_~M_E~0_14 1) InVars {~M_E~0=v_~M_E~0_14} OutVars{~M_E~0=v_~M_E~0_14} AuxVars[] AssignedVars[] 1799#L263-1 [777] L263-1-->L268-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 1800#L268-1 [778] L268-1-->L394-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 1872#L394-1 31.95/12.15 [2019-03-28 12:20:19,644 INFO L796 eck$LassoCheckResult]: Loop: 1872#L394-1 [874] L394-1-->L215: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 1814#L215 [875] L215-->L169: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_22, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 1852#L169 [545] L169-->L181: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_8 1) (= v_~m_st~0_7 0)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 1853#L181 [876] L181-->L196: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 1898#L196 [878] L196-->L240-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 2025#L240-2 [783] L240-2-->L240-4: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 2024#L240-4 [786] L240-4-->L245-3: Formula: (< 0 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 2023#L245-3 [789] L245-3-->L250-3: Formula: (> v_~E_1~0_7 0) InVars {~E_1~0=v_~E_1~0_7} OutVars{~E_1~0=v_~E_1~0_7} AuxVars[] AssignedVars[] 1875#L250-3 [676] L250-3-->L105-6: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_4, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_4|, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_2|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 1876#L105-6 [795] L105-6-->L105-8: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 1900#L105-8 [619] L105-8-->L116-2: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 1901#L116-2 [883] L116-2-->L290-6: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_27 |v_ULTIMATE.start_is_master_triggered_#res_16|) (= |v_ULTIMATE.start_is_master_triggered_#res_16| v_ULTIMATE.start_activate_threads_~tmp~1_27)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_27} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_27, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_27, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_16|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 2022#L290-6 [532] L290-6-->L290-8: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 1839#L290-8 [524] L290-8-->L124-6: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 1819#L124-6 [818] L124-6-->L124-8: Formula: (< v_~t1_pc~0_9 1) InVars {~t1_pc~0=v_~t1_pc~0_9} OutVars{~t1_pc~0=v_~t1_pc~0_9} AuxVars[] AssignedVars[] 1820#L124-8 [606] L124-8-->L135-2: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 1795#L135-2 [885] L135-2-->L298-6: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_27 |v_ULTIMATE.start_is_transmit1_triggered_#res_15|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27 |v_ULTIMATE.start_is_transmit1_triggered_#res_15|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_27, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_16|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_15|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 1796#L298-6 [584] L298-6-->L298-8: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 1878#L298-8 [829] L298-8-->L263-3: Formula: (> v_~M_E~0_17 1) InVars {~M_E~0=v_~M_E~0_17} OutVars{~M_E~0=v_~M_E~0_17} AuxVars[] AssignedVars[] 1834#L263-3 [832] L263-3-->L268-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 1835#L268-3 [834] L268-3-->L273-3: Formula: (< 1 v_~E_1~0_17) InVars {~E_1~0=v_~E_1~0_17} OutVars{~E_1~0=v_~E_1~0_17} AuxVars[] AssignedVars[] 1851#L273-3 [628] L273-3-->L169-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 1848#L169-1 [543] L169-1-->L181-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_7 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{~m_st~0=v_~m_st~0_6, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 1850#L181-1 [886] L181-1-->L413: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24} OutVars{ULTIMATE.start_start_simulation_#t~ret6=|v_ULTIMATE.start_start_simulation_#t~ret6_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret6, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_~tmp~3] 1822#L413 [842] L413-->L413-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 1824#L413-1 [659] L413-1-->L169-2: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret5=|v_ULTIMATE.start_stop_simulation_#t~ret5_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret5, ULTIMATE.start_stop_simulation_#res] 1831#L169-2 [536] L169-2-->L181-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18 1) (= 0 v_~m_st~0_14)) InVars {~m_st~0=v_~m_st~0_14} OutVars{~m_st~0=v_~m_st~0_14, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 1844#L181-2 [888] L181-2-->L368: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_stop_simulation_#t~ret5=|v_ULTIMATE.start_stop_simulation_#t~ret5_4|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret5] 1865#L368 [691] L368-->L375: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 1887#L375 [894] L375-->L394-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 1872#L394-1 31.95/12.15 [2019-03-28 12:20:19,644 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 31.95/12.15 [2019-03-28 12:20:19,644 INFO L82 PathProgramCache]: Analyzing trace with hash -1827027340, now seen corresponding path program 1 times 31.95/12.15 [2019-03-28 12:20:19,645 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 31.95/12.15 [2019-03-28 12:20:19,645 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 31.95/12.15 [2019-03-28 12:20:19,646 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:19,646 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:19,646 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:19,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 31.95/12.15 [2019-03-28 12:20:19,670 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 31.95/12.15 [2019-03-28 12:20:19,670 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 31.95/12.15 [2019-03-28 12:20:19,670 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 31.95/12.15 [2019-03-28 12:20:19,671 INFO L799 eck$LassoCheckResult]: stem already infeasible 31.95/12.15 [2019-03-28 12:20:19,671 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 31.95/12.15 [2019-03-28 12:20:19,671 INFO L82 PathProgramCache]: Analyzing trace with hash -739229529, now seen corresponding path program 1 times 31.95/12.15 [2019-03-28 12:20:19,671 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 31.95/12.15 [2019-03-28 12:20:19,671 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 31.95/12.15 [2019-03-28 12:20:19,672 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:19,672 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:19,672 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:19,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 31.95/12.15 [2019-03-28 12:20:19,693 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 31.95/12.15 [2019-03-28 12:20:19,693 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 31.95/12.15 [2019-03-28 12:20:19,694 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 31.95/12.15 [2019-03-28 12:20:19,694 INFO L811 eck$LassoCheckResult]: loop already infeasible 31.95/12.15 [2019-03-28 12:20:19,694 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. 31.95/12.15 [2019-03-28 12:20:19,694 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 31.95/12.15 [2019-03-28 12:20:19,695 INFO L87 Difference]: Start difference. First operand 267 states and 487 transitions. cyclomatic complexity: 221 Second operand 4 states. 31.95/12.15 [2019-03-28 12:20:19,839 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 31.95/12.15 [2019-03-28 12:20:19,839 INFO L93 Difference]: Finished difference Result 267 states and 477 transitions. 31.95/12.15 [2019-03-28 12:20:19,839 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. 31.95/12.15 [2019-03-28 12:20:19,840 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 267 states and 477 transitions. 31.95/12.15 [2019-03-28 12:20:19,842 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 247 31.95/12.15 [2019-03-28 12:20:19,844 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 267 states to 267 states and 477 transitions. 31.95/12.15 [2019-03-28 12:20:19,844 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 267 31.95/12.15 [2019-03-28 12:20:19,845 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 267 31.95/12.15 [2019-03-28 12:20:19,845 INFO L73 IsDeterministic]: Start isDeterministic. Operand 267 states and 477 transitions. 31.95/12.15 [2019-03-28 12:20:19,845 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 31.95/12.15 [2019-03-28 12:20:19,846 INFO L706 BuchiCegarLoop]: Abstraction has 267 states and 477 transitions. 31.95/12.15 [2019-03-28 12:20:19,846 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 267 states and 477 transitions. 31.95/12.15 [2019-03-28 12:20:19,851 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 267 to 267. 31.95/12.15 [2019-03-28 12:20:19,851 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 267 states. 31.95/12.15 [2019-03-28 12:20:19,853 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 267 states to 267 states and 477 transitions. 31.95/12.15 [2019-03-28 12:20:19,853 INFO L729 BuchiCegarLoop]: Abstraction has 267 states and 477 transitions. 31.95/12.15 [2019-03-28 12:20:19,853 INFO L609 BuchiCegarLoop]: Abstraction has 267 states and 477 transitions. 31.95/12.15 [2019-03-28 12:20:19,853 INFO L442 BuchiCegarLoop]: ======== Iteration 8============ 31.95/12.15 [2019-03-28 12:20:19,853 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 267 states and 477 transitions. 31.95/12.15 [2019-03-28 12:20:19,855 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 247 31.95/12.15 [2019-03-28 12:20:19,855 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 31.95/12.15 [2019-03-28 12:20:19,855 INFO L119 BuchiIsEmpty]: Starting construction of run 31.95/12.15 [2019-03-28 12:20:19,856 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 31.95/12.15 [2019-03-28 12:20:19,856 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 31.95/12.15 [2019-03-28 12:20:19,856 INFO L794 eck$LassoCheckResult]: Stem: 2400#ULTIMATE.startENTRY [871] ULTIMATE.startENTRY-->L144: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~m_pc~0_16 0) (= 0 v_~m_st~0_19) (= 2 v_~E_1~0_28) (= v_~M_E~0_27 2) (= v_~T1_E~0_18 2) (= v_~t1_pc~0_16 0) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= 0 v_~t1_st~0_19)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ULTIMATE.start_start_simulation_#t~ret6=|v_ULTIMATE.start_start_simulation_#t~ret6_4|, ~t1_st~0=v_~t1_st~0_19, ~t1_pc~0=v_~t1_pc~0_16, ~M_E~0=v_~M_E~0_27, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~E_1~0=v_~E_1~0_28, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~T1_E~0=v_~T1_E~0_18, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_19, ~m_pc~0=v_~m_pc~0_16, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_start_simulation_#t~ret6, ~t1_st~0, ~t1_pc~0, ~M_E~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_~kernel_st~0, ~E_1~0, ULTIMATE.start_main_#res, ~T1_E~0, ~t1_i~0, ~m_st~0, ~m_pc~0, ULTIMATE.start_main_~__retres1~3] 2401#L144 [557] L144-->L151-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 2407#L151-1 [672] L151-1-->L156-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 2418#L156-1 [757] L156-1-->L240-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 2425#L240-1 [759] L240-1-->L245-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 2362#L245-1 [760] L245-1-->L250-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 2363#L250-1 [679] L250-1-->L105: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_1|, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 2424#L105 [762] L105-->L105-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 2429#L105-2 [594] L105-2-->L116: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 2430#L116 [872] L116-->L290: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_24 |v_ULTIMATE.start_is_master_triggered_#res_13|) (= |v_ULTIMATE.start_is_master_triggered_#res_13| v_ULTIMATE.start_activate_threads_~tmp~1_24)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_24} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_24, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_24, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_13|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 2421#L290 [766] L290-->L290-2: Formula: (and (= v_~m_st~0_4 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_5)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} OutVars{~m_st~0=v_~m_st~0_4, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_5} AuxVars[] AssignedVars[~m_st~0] 2416#L290-2 [569] L290-2-->L124: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 2346#L124 [769] L124-->L124-2: Formula: (> v_~t1_pc~0_7 1) InVars {~t1_pc~0=v_~t1_pc~0_7} OutVars{~t1_pc~0=v_~t1_pc~0_7} AuxVars[] AssignedVars[] 2336#L124-2 [632] L124-2-->L135: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 2337#L135 [873] L135-->L298: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_24 |v_ULTIMATE.start_is_transmit1_triggered_#res_13|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25 |v_ULTIMATE.start_is_transmit1_triggered_#res_13|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_24, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_13|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 2348#L298 [773] L298-->L298-2: Formula: (and (= v_~t1_st~0_6 0) (> 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_8)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_8} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_8, ~t1_st~0=v_~t1_st~0_6} AuxVars[] AssignedVars[~t1_st~0] 2409#L298-2 [774] L298-2-->L263-1: Formula: (> v_~M_E~0_14 1) InVars {~M_E~0=v_~M_E~0_14} OutVars{~M_E~0=v_~M_E~0_14} AuxVars[] AssignedVars[] 2342#L263-1 [777] L263-1-->L268-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 2343#L268-1 [778] L268-1-->L394-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 2417#L394-1 31.95/12.15 [2019-03-28 12:20:19,857 INFO L796 eck$LassoCheckResult]: Loop: 2417#L394-1 [874] L394-1-->L215: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 2565#L215 [875] L215-->L169: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_22, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 2562#L169 [545] L169-->L181: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_8 1) (= v_~m_st~0_7 0)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 2557#L181 [876] L181-->L196: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 2442#L196 [878] L196-->L240-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 2443#L240-2 [783] L240-2-->L240-4: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 2437#L240-4 [786] L240-4-->L245-3: Formula: (< 0 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 2353#L245-3 [789] L245-3-->L250-3: Formula: (> v_~E_1~0_7 0) InVars {~E_1~0=v_~E_1~0_7} OutVars{~E_1~0=v_~E_1~0_7} AuxVars[] AssignedVars[] 2354#L250-3 [676] L250-3-->L105-6: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_4, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_4|, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_2|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 2420#L105-6 [795] L105-6-->L105-8: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 2439#L105-8 [619] L105-8-->L116-2: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 2602#L116-2 [883] L116-2-->L290-6: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_27 |v_ULTIMATE.start_is_master_triggered_#res_16|) (= |v_ULTIMATE.start_is_master_triggered_#res_16| v_ULTIMATE.start_activate_threads_~tmp~1_27)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_27} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_27, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_27, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_16|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 2601#L290-6 [532] L290-6-->L290-8: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 2600#L290-8 [524] L290-8-->L124-6: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 2598#L124-6 [818] L124-6-->L124-8: Formula: (< v_~t1_pc~0_9 1) InVars {~t1_pc~0=v_~t1_pc~0_9} OutVars{~t1_pc~0=v_~t1_pc~0_9} AuxVars[] AssignedVars[] 2597#L124-8 [606] L124-8-->L135-2: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 2340#L135-2 [885] L135-2-->L298-6: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_27 |v_ULTIMATE.start_is_transmit1_triggered_#res_15|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27 |v_ULTIMATE.start_is_transmit1_triggered_#res_15|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_27, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_16|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_15|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 2341#L298-6 [584] L298-6-->L298-8: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 2423#L298-8 [829] L298-8-->L263-3: Formula: (> v_~M_E~0_17 1) InVars {~M_E~0=v_~M_E~0_17} OutVars{~M_E~0=v_~M_E~0_17} AuxVars[] AssignedVars[] 2381#L263-3 [832] L263-3-->L268-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 2382#L268-3 [834] L268-3-->L273-3: Formula: (< 1 v_~E_1~0_17) InVars {~E_1~0=v_~E_1~0_17} OutVars{~E_1~0=v_~E_1~0_17} AuxVars[] AssignedVars[] 2399#L273-3 [628] L273-3-->L169-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 2394#L169-1 [543] L169-1-->L181-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_7 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{~m_st~0=v_~m_st~0_6, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 2396#L181-1 [886] L181-1-->L413: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24} OutVars{ULTIMATE.start_start_simulation_#t~ret6=|v_ULTIMATE.start_start_simulation_#t~ret6_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret6, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_~tmp~3] 2367#L413 [842] L413-->L413-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 2369#L413-1 [659] L413-1-->L169-2: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret5=|v_ULTIMATE.start_stop_simulation_#t~ret5_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret5, ULTIMATE.start_stop_simulation_#res] 2575#L169-2 [536] L169-2-->L181-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18 1) (= 0 v_~m_st~0_14)) InVars {~m_st~0=v_~m_st~0_14} OutVars{~m_st~0=v_~m_st~0_14, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 2573#L181-2 [888] L181-2-->L368: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_stop_simulation_#t~ret5=|v_ULTIMATE.start_stop_simulation_#t~ret5_4|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret5] 2572#L368 [691] L368-->L375: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 2570#L375 [894] L375-->L394-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 2417#L394-1 31.95/12.15 [2019-03-28 12:20:19,857 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 31.95/12.15 [2019-03-28 12:20:19,858 INFO L82 PathProgramCache]: Analyzing trace with hash -19572877, now seen corresponding path program 1 times 31.95/12.15 [2019-03-28 12:20:19,858 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 31.95/12.15 [2019-03-28 12:20:19,858 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 31.95/12.15 [2019-03-28 12:20:19,859 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:19,859 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:19,859 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:19,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 31.95/12.15 [2019-03-28 12:20:19,889 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 31.95/12.15 [2019-03-28 12:20:19,889 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 31.95/12.15 [2019-03-28 12:20:19,889 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 31.95/12.15 [2019-03-28 12:20:19,890 INFO L799 eck$LassoCheckResult]: stem already infeasible 31.95/12.15 [2019-03-28 12:20:19,890 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 31.95/12.15 [2019-03-28 12:20:19,890 INFO L82 PathProgramCache]: Analyzing trace with hash -739229529, now seen corresponding path program 2 times 31.95/12.15 [2019-03-28 12:20:19,890 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 31.95/12.15 [2019-03-28 12:20:19,890 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 31.95/12.15 [2019-03-28 12:20:19,892 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:19,892 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:19,892 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:19,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 31.95/12.15 [2019-03-28 12:20:19,915 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 31.95/12.15 [2019-03-28 12:20:19,915 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 31.95/12.15 [2019-03-28 12:20:19,916 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 31.95/12.15 [2019-03-28 12:20:19,916 INFO L811 eck$LassoCheckResult]: loop already infeasible 31.95/12.15 [2019-03-28 12:20:19,916 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. 31.95/12.15 [2019-03-28 12:20:19,916 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 31.95/12.15 [2019-03-28 12:20:19,917 INFO L87 Difference]: Start difference. First operand 267 states and 477 transitions. cyclomatic complexity: 211 Second operand 4 states. 31.95/12.15 [2019-03-28 12:20:20,199 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 31.95/12.15 [2019-03-28 12:20:20,199 INFO L93 Difference]: Finished difference Result 467 states and 842 transitions. 31.95/12.15 [2019-03-28 12:20:20,200 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. 31.95/12.15 [2019-03-28 12:20:20,200 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 467 states and 842 transitions. 31.95/12.15 [2019-03-28 12:20:20,203 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 447 31.95/12.15 [2019-03-28 12:20:20,207 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 467 states to 467 states and 842 transitions. 31.95/12.15 [2019-03-28 12:20:20,207 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 467 31.95/12.15 [2019-03-28 12:20:20,207 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 467 31.95/12.15 [2019-03-28 12:20:20,208 INFO L73 IsDeterministic]: Start isDeterministic. Operand 467 states and 842 transitions. 31.95/12.15 [2019-03-28 12:20:20,209 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 31.95/12.15 [2019-03-28 12:20:20,209 INFO L706 BuchiCegarLoop]: Abstraction has 467 states and 842 transitions. 31.95/12.15 [2019-03-28 12:20:20,209 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 467 states and 842 transitions. 31.95/12.15 [2019-03-28 12:20:20,215 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 467 to 273. 31.95/12.15 [2019-03-28 12:20:20,215 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 273 states. 31.95/12.15 [2019-03-28 12:20:20,216 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 273 states to 273 states and 476 transitions. 31.95/12.15 [2019-03-28 12:20:20,216 INFO L729 BuchiCegarLoop]: Abstraction has 273 states and 476 transitions. 31.95/12.15 [2019-03-28 12:20:20,216 INFO L609 BuchiCegarLoop]: Abstraction has 273 states and 476 transitions. 31.95/12.15 [2019-03-28 12:20:20,216 INFO L442 BuchiCegarLoop]: ======== Iteration 9============ 31.95/12.15 [2019-03-28 12:20:20,216 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 273 states and 476 transitions. 31.95/12.15 [2019-03-28 12:20:20,218 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 253 31.95/12.15 [2019-03-28 12:20:20,218 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 31.95/12.15 [2019-03-28 12:20:20,218 INFO L119 BuchiIsEmpty]: Starting construction of run 31.95/12.15 [2019-03-28 12:20:20,219 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 31.95/12.15 [2019-03-28 12:20:20,219 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 31.95/12.15 [2019-03-28 12:20:20,220 INFO L794 eck$LassoCheckResult]: Stem: 3145#ULTIMATE.startENTRY [871] ULTIMATE.startENTRY-->L144: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~m_pc~0_16 0) (= 0 v_~m_st~0_19) (= 2 v_~E_1~0_28) (= v_~M_E~0_27 2) (= v_~T1_E~0_18 2) (= v_~t1_pc~0_16 0) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= 0 v_~t1_st~0_19)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ULTIMATE.start_start_simulation_#t~ret6=|v_ULTIMATE.start_start_simulation_#t~ret6_4|, ~t1_st~0=v_~t1_st~0_19, ~t1_pc~0=v_~t1_pc~0_16, ~M_E~0=v_~M_E~0_27, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~E_1~0=v_~E_1~0_28, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~T1_E~0=v_~T1_E~0_18, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_19, ~m_pc~0=v_~m_pc~0_16, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_start_simulation_#t~ret6, ~t1_st~0, ~t1_pc~0, ~M_E~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_~kernel_st~0, ~E_1~0, ULTIMATE.start_main_#res, ~T1_E~0, ~t1_i~0, ~m_st~0, ~m_pc~0, ULTIMATE.start_main_~__retres1~3] 3146#L144 [557] L144-->L151-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 3152#L151-1 [672] L151-1-->L156-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 3164#L156-1 [757] L156-1-->L240-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 3173#L240-1 [759] L240-1-->L245-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 3107#L245-1 [760] L245-1-->L250-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 3108#L250-1 [679] L250-1-->L105: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_1|, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 3172#L105 [762] L105-->L105-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 3179#L105-2 [594] L105-2-->L116: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 3180#L116 [872] L116-->L290: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_24 |v_ULTIMATE.start_is_master_triggered_#res_13|) (= |v_ULTIMATE.start_is_master_triggered_#res_13| v_ULTIMATE.start_activate_threads_~tmp~1_24)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_24} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_24, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_24, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_13|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 3168#L290 [578] L290-->L290-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_9) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} AuxVars[] AssignedVars[] 3162#L290-2 [569] L290-2-->L124: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 3091#L124 [769] L124-->L124-2: Formula: (> v_~t1_pc~0_7 1) InVars {~t1_pc~0=v_~t1_pc~0_7} OutVars{~t1_pc~0=v_~t1_pc~0_7} AuxVars[] AssignedVars[] 3081#L124-2 [632] L124-2-->L135: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 3082#L135 [873] L135-->L298: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_24 |v_ULTIMATE.start_is_transmit1_triggered_#res_13|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25 |v_ULTIMATE.start_is_transmit1_triggered_#res_13|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_24, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_13|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 3093#L298 [773] L298-->L298-2: Formula: (and (= v_~t1_st~0_6 0) (> 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_8)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_8} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_8, ~t1_st~0=v_~t1_st~0_6} AuxVars[] AssignedVars[~t1_st~0] 3153#L298-2 [774] L298-2-->L263-1: Formula: (> v_~M_E~0_14 1) InVars {~M_E~0=v_~M_E~0_14} OutVars{~M_E~0=v_~M_E~0_14} AuxVars[] AssignedVars[] 3087#L263-1 [777] L263-1-->L268-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 3088#L268-1 [778] L268-1-->L394-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 3163#L394-1 31.95/12.15 [2019-03-28 12:20:20,220 INFO L796 eck$LassoCheckResult]: Loop: 3163#L394-1 [874] L394-1-->L215: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 3276#L215 [875] L215-->L169: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_22, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 3141#L169 [545] L169-->L181: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_8 1) (= v_~m_st~0_7 0)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 3142#L181 [876] L181-->L196: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 3185#L196 [878] L196-->L240-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 3273#L240-2 [783] L240-2-->L240-4: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 3320#L240-4 [786] L240-4-->L245-3: Formula: (< 0 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 3318#L245-3 [789] L245-3-->L250-3: Formula: (> v_~E_1~0_7 0) InVars {~E_1~0=v_~E_1~0_7} OutVars{~E_1~0=v_~E_1~0_7} AuxVars[] AssignedVars[] 3317#L250-3 [676] L250-3-->L105-6: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_4, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_4|, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_2|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 3316#L105-6 [795] L105-6-->L105-8: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 3313#L105-8 [619] L105-8-->L116-2: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 3311#L116-2 [883] L116-2-->L290-6: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_27 |v_ULTIMATE.start_is_master_triggered_#res_16|) (= |v_ULTIMATE.start_is_master_triggered_#res_16| v_ULTIMATE.start_activate_threads_~tmp~1_27)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_27} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_27, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_27, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_16|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 3309#L290-6 [532] L290-6-->L290-8: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 3308#L290-8 [524] L290-8-->L124-6: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 3303#L124-6 [818] L124-6-->L124-8: Formula: (< v_~t1_pc~0_9 1) InVars {~t1_pc~0=v_~t1_pc~0_9} OutVars{~t1_pc~0=v_~t1_pc~0_9} AuxVars[] AssignedVars[] 3301#L124-8 [606] L124-8-->L135-2: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 3299#L135-2 [885] L135-2-->L298-6: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_27 |v_ULTIMATE.start_is_transmit1_triggered_#res_15|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27 |v_ULTIMATE.start_is_transmit1_triggered_#res_15|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_27, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_16|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_15|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 3298#L298-6 [584] L298-6-->L298-8: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 3297#L298-8 [829] L298-8-->L263-3: Formula: (> v_~M_E~0_17 1) InVars {~M_E~0=v_~M_E~0_17} OutVars{~M_E~0=v_~M_E~0_17} AuxVars[] AssignedVars[] 3294#L263-3 [832] L263-3-->L268-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 3293#L268-3 [834] L268-3-->L273-3: Formula: (< 1 v_~E_1~0_17) InVars {~E_1~0=v_~E_1~0_17} OutVars{~E_1~0=v_~E_1~0_17} AuxVars[] AssignedVars[] 3292#L273-3 [628] L273-3-->L169-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 3291#L169-1 [543] L169-1-->L181-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_7 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{~m_st~0=v_~m_st~0_6, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 3289#L181-1 [886] L181-1-->L413: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24} OutVars{ULTIMATE.start_start_simulation_#t~ret6=|v_ULTIMATE.start_start_simulation_#t~ret6_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret6, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_~tmp~3] 3288#L413 [842] L413-->L413-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 3286#L413-1 [659] L413-1-->L169-2: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret5=|v_ULTIMATE.start_stop_simulation_#t~ret5_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret5, ULTIMATE.start_stop_simulation_#res] 3285#L169-2 [536] L169-2-->L181-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18 1) (= 0 v_~m_st~0_14)) InVars {~m_st~0=v_~m_st~0_14} OutVars{~m_st~0=v_~m_st~0_14, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 3283#L181-2 [888] L181-2-->L368: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_stop_simulation_#t~ret5=|v_ULTIMATE.start_stop_simulation_#t~ret5_4|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret5] 3282#L368 [691] L368-->L375: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 3280#L375 [894] L375-->L394-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 3163#L394-1 31.95/12.15 [2019-03-28 12:20:20,221 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 31.95/12.15 [2019-03-28 12:20:20,221 INFO L82 PathProgramCache]: Analyzing trace with hash 479449783, now seen corresponding path program 1 times 31.95/12.15 [2019-03-28 12:20:20,221 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 31.95/12.15 [2019-03-28 12:20:20,221 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 31.95/12.15 [2019-03-28 12:20:20,222 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:20,222 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:20,222 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:20,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 31.95/12.15 [2019-03-28 12:20:20,244 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 31.95/12.15 [2019-03-28 12:20:20,245 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 31.95/12.15 [2019-03-28 12:20:20,245 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 31.95/12.15 [2019-03-28 12:20:20,245 INFO L799 eck$LassoCheckResult]: stem already infeasible 31.95/12.15 [2019-03-28 12:20:20,245 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 31.95/12.15 [2019-03-28 12:20:20,245 INFO L82 PathProgramCache]: Analyzing trace with hash -739229529, now seen corresponding path program 3 times 31.95/12.15 [2019-03-28 12:20:20,245 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 31.95/12.15 [2019-03-28 12:20:20,246 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 31.95/12.15 [2019-03-28 12:20:20,246 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:20,247 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:20,247 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:20,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 31.95/12.15 [2019-03-28 12:20:20,275 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 31.95/12.15 [2019-03-28 12:20:20,276 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 31.95/12.15 [2019-03-28 12:20:20,276 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 31.95/12.15 [2019-03-28 12:20:20,276 INFO L811 eck$LassoCheckResult]: loop already infeasible 31.95/12.15 [2019-03-28 12:20:20,276 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 31.95/12.15 [2019-03-28 12:20:20,277 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 31.95/12.15 [2019-03-28 12:20:20,277 INFO L87 Difference]: Start difference. First operand 273 states and 476 transitions. cyclomatic complexity: 204 Second operand 3 states. 31.95/12.15 [2019-03-28 12:20:20,446 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 31.95/12.15 [2019-03-28 12:20:20,447 INFO L93 Difference]: Finished difference Result 516 states and 884 transitions. 31.95/12.15 [2019-03-28 12:20:20,447 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 31.95/12.15 [2019-03-28 12:20:20,447 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 516 states and 884 transitions. 31.95/12.15 [2019-03-28 12:20:20,451 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 497 31.95/12.15 [2019-03-28 12:20:20,455 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 516 states to 516 states and 884 transitions. 31.95/12.15 [2019-03-28 12:20:20,455 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 516 31.95/12.15 [2019-03-28 12:20:20,455 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 516 31.95/12.15 [2019-03-28 12:20:20,455 INFO L73 IsDeterministic]: Start isDeterministic. Operand 516 states and 884 transitions. 31.95/12.15 [2019-03-28 12:20:20,456 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 31.95/12.15 [2019-03-28 12:20:20,457 INFO L706 BuchiCegarLoop]: Abstraction has 516 states and 884 transitions. 31.95/12.15 [2019-03-28 12:20:20,457 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 516 states and 884 transitions. 31.95/12.15 [2019-03-28 12:20:20,466 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 516 to 512. 31.95/12.15 [2019-03-28 12:20:20,466 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 512 states. 31.95/12.15 [2019-03-28 12:20:20,468 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 512 states to 512 states and 880 transitions. 31.95/12.15 [2019-03-28 12:20:20,468 INFO L729 BuchiCegarLoop]: Abstraction has 512 states and 880 transitions. 31.95/12.15 [2019-03-28 12:20:20,468 INFO L609 BuchiCegarLoop]: Abstraction has 512 states and 880 transitions. 31.95/12.15 [2019-03-28 12:20:20,468 INFO L442 BuchiCegarLoop]: ======== Iteration 10============ 31.95/12.15 [2019-03-28 12:20:20,468 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 512 states and 880 transitions. 31.95/12.15 [2019-03-28 12:20:20,471 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 493 31.95/12.15 [2019-03-28 12:20:20,471 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 31.95/12.15 [2019-03-28 12:20:20,471 INFO L119 BuchiIsEmpty]: Starting construction of run 31.95/12.15 [2019-03-28 12:20:20,472 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 31.95/12.15 [2019-03-28 12:20:20,472 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 31.95/12.15 [2019-03-28 12:20:20,473 INFO L794 eck$LassoCheckResult]: Stem: 3942#ULTIMATE.startENTRY [871] ULTIMATE.startENTRY-->L144: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~m_pc~0_16 0) (= 0 v_~m_st~0_19) (= 2 v_~E_1~0_28) (= v_~M_E~0_27 2) (= v_~T1_E~0_18 2) (= v_~t1_pc~0_16 0) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= 0 v_~t1_st~0_19)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ULTIMATE.start_start_simulation_#t~ret6=|v_ULTIMATE.start_start_simulation_#t~ret6_4|, ~t1_st~0=v_~t1_st~0_19, ~t1_pc~0=v_~t1_pc~0_16, ~M_E~0=v_~M_E~0_27, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~E_1~0=v_~E_1~0_28, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~T1_E~0=v_~T1_E~0_18, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_19, ~m_pc~0=v_~m_pc~0_16, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_start_simulation_#t~ret6, ~t1_st~0, ~t1_pc~0, ~M_E~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_~kernel_st~0, ~E_1~0, ULTIMATE.start_main_#res, ~T1_E~0, ~t1_i~0, ~m_st~0, ~m_pc~0, ULTIMATE.start_main_~__retres1~3] 3943#L144 [557] L144-->L151-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 3949#L151-1 [672] L151-1-->L156-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 3962#L156-1 [757] L156-1-->L240-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 3970#L240-1 [759] L240-1-->L245-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 3903#L245-1 [760] L245-1-->L250-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 3904#L250-1 [679] L250-1-->L105: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_1|, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 3969#L105 [762] L105-->L105-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 3975#L105-2 [594] L105-2-->L116: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 3976#L116 [872] L116-->L290: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_24 |v_ULTIMATE.start_is_master_triggered_#res_13|) (= |v_ULTIMATE.start_is_master_triggered_#res_13| v_ULTIMATE.start_activate_threads_~tmp~1_24)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_24} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_24, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_24, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_13|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 3966#L290 [578] L290-->L290-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_9) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} AuxVars[] AssignedVars[] 3960#L290-2 [569] L290-2-->L124: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 3888#L124 [768] L124-->L124-2: Formula: (< v_~t1_pc~0_7 1) InVars {~t1_pc~0=v_~t1_pc~0_7} OutVars{~t1_pc~0=v_~t1_pc~0_7} AuxVars[] AssignedVars[] 3878#L124-2 [632] L124-2-->L135: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 3879#L135 [873] L135-->L298: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_24 |v_ULTIMATE.start_is_transmit1_triggered_#res_13|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25 |v_ULTIMATE.start_is_transmit1_triggered_#res_13|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_24, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_13|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 3889#L298 [773] L298-->L298-2: Formula: (and (= v_~t1_st~0_6 0) (> 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_8)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_8} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_8, ~t1_st~0=v_~t1_st~0_6} AuxVars[] AssignedVars[~t1_st~0] 3950#L298-2 [774] L298-2-->L263-1: Formula: (> v_~M_E~0_14 1) InVars {~M_E~0=v_~M_E~0_14} OutVars{~M_E~0=v_~M_E~0_14} AuxVars[] AssignedVars[] 3884#L263-1 [777] L263-1-->L268-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 3885#L268-1 [778] L268-1-->L394-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 3961#L394-1 31.95/12.15 [2019-03-28 12:20:20,474 INFO L796 eck$LassoCheckResult]: Loop: 3961#L394-1 [874] L394-1-->L215: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 4309#L215 [875] L215-->L169: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_22, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 3937#L169 [545] L169-->L181: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_8 1) (= v_~m_st~0_7 0)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 3938#L181 [876] L181-->L196: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 3983#L196 [878] L196-->L240-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 3990#L240-2 [783] L240-2-->L240-4: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 4383#L240-4 [786] L240-4-->L245-3: Formula: (< 0 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 4381#L245-3 [789] L245-3-->L250-3: Formula: (> v_~E_1~0_7 0) InVars {~E_1~0=v_~E_1~0_7} OutVars{~E_1~0=v_~E_1~0_7} AuxVars[] AssignedVars[] 4379#L250-3 [676] L250-3-->L105-6: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_4, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_4|, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_2|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 4378#L105-6 [795] L105-6-->L105-8: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 4369#L105-8 [619] L105-8-->L116-2: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 4374#L116-2 [883] L116-2-->L290-6: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_27 |v_ULTIMATE.start_is_master_triggered_#res_16|) (= |v_ULTIMATE.start_is_master_triggered_#res_16| v_ULTIMATE.start_activate_threads_~tmp~1_27)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_27} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_27, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_27, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_16|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 4373#L290-6 [532] L290-6-->L290-8: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 4356#L290-8 [524] L290-8-->L124-6: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 4348#L124-6 [818] L124-6-->L124-8: Formula: (< v_~t1_pc~0_9 1) InVars {~t1_pc~0=v_~t1_pc~0_9} OutVars{~t1_pc~0=v_~t1_pc~0_9} AuxVars[] AssignedVars[] 4347#L124-8 [606] L124-8-->L135-2: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 4345#L135-2 [885] L135-2-->L298-6: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_27 |v_ULTIMATE.start_is_transmit1_triggered_#res_15|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27 |v_ULTIMATE.start_is_transmit1_triggered_#res_15|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_27, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_16|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_15|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 4343#L298-6 [584] L298-6-->L298-8: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 4342#L298-8 [829] L298-8-->L263-3: Formula: (> v_~M_E~0_17 1) InVars {~M_E~0=v_~M_E~0_17} OutVars{~M_E~0=v_~M_E~0_17} AuxVars[] AssignedVars[] 4339#L263-3 [832] L263-3-->L268-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 4338#L268-3 [834] L268-3-->L273-3: Formula: (< 1 v_~E_1~0_17) InVars {~E_1~0=v_~E_1~0_17} OutVars{~E_1~0=v_~E_1~0_17} AuxVars[] AssignedVars[] 4337#L273-3 [628] L273-3-->L169-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 4336#L169-1 [543] L169-1-->L181-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_7 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{~m_st~0=v_~m_st~0_6, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 4334#L181-1 [886] L181-1-->L413: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24} OutVars{ULTIMATE.start_start_simulation_#t~ret6=|v_ULTIMATE.start_start_simulation_#t~ret6_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret6, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_~tmp~3] 4332#L413 [842] L413-->L413-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 4330#L413-1 [659] L413-1-->L169-2: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret5=|v_ULTIMATE.start_stop_simulation_#t~ret5_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret5, ULTIMATE.start_stop_simulation_#res] 4327#L169-2 [536] L169-2-->L181-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18 1) (= 0 v_~m_st~0_14)) InVars {~m_st~0=v_~m_st~0_14} OutVars{~m_st~0=v_~m_st~0_14, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 4324#L181-2 [888] L181-2-->L368: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_stop_simulation_#t~ret5=|v_ULTIMATE.start_stop_simulation_#t~ret5_4|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret5] 4312#L368 [691] L368-->L375: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 4311#L375 [894] L375-->L394-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 3961#L394-1 31.95/12.15 [2019-03-28 12:20:20,474 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 31.95/12.15 [2019-03-28 12:20:20,474 INFO L82 PathProgramCache]: Analyzing trace with hash -408053898, now seen corresponding path program 1 times 31.95/12.15 [2019-03-28 12:20:20,474 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 31.95/12.15 [2019-03-28 12:20:20,474 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 31.95/12.15 [2019-03-28 12:20:20,475 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:20,475 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:20,475 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:20,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 31.95/12.15 [2019-03-28 12:20:20,510 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 31.95/12.15 [2019-03-28 12:20:20,510 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 31.95/12.15 [2019-03-28 12:20:20,510 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 31.95/12.15 [2019-03-28 12:20:20,511 INFO L799 eck$LassoCheckResult]: stem already infeasible 31.95/12.15 [2019-03-28 12:20:20,511 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 31.95/12.15 [2019-03-28 12:20:20,511 INFO L82 PathProgramCache]: Analyzing trace with hash -739229529, now seen corresponding path program 4 times 31.95/12.15 [2019-03-28 12:20:20,511 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 31.95/12.15 [2019-03-28 12:20:20,511 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 31.95/12.15 [2019-03-28 12:20:20,512 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:20,512 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:20,512 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:20,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 31.95/12.15 [2019-03-28 12:20:20,537 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 31.95/12.15 [2019-03-28 12:20:20,538 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 31.95/12.15 [2019-03-28 12:20:20,538 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 31.95/12.15 [2019-03-28 12:20:20,538 INFO L811 eck$LassoCheckResult]: loop already infeasible 31.95/12.15 [2019-03-28 12:20:20,538 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. 31.95/12.15 [2019-03-28 12:20:20,538 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 31.95/12.15 [2019-03-28 12:20:20,539 INFO L87 Difference]: Start difference. First operand 512 states and 880 transitions. cyclomatic complexity: 369 Second operand 6 states. 31.95/12.15 [2019-03-28 12:20:20,779 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 31.95/12.15 [2019-03-28 12:20:20,780 INFO L93 Difference]: Finished difference Result 512 states and 861 transitions. 31.95/12.15 [2019-03-28 12:20:20,780 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. 31.95/12.15 [2019-03-28 12:20:20,780 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 512 states and 861 transitions. 31.95/12.15 [2019-03-28 12:20:20,783 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 493 31.95/12.15 [2019-03-28 12:20:20,787 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 512 states to 512 states and 861 transitions. 31.95/12.15 [2019-03-28 12:20:20,788 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 512 31.95/12.15 [2019-03-28 12:20:20,788 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 512 31.95/12.15 [2019-03-28 12:20:20,788 INFO L73 IsDeterministic]: Start isDeterministic. Operand 512 states and 861 transitions. 31.95/12.15 [2019-03-28 12:20:20,789 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 31.95/12.15 [2019-03-28 12:20:20,789 INFO L706 BuchiCegarLoop]: Abstraction has 512 states and 861 transitions. 31.95/12.15 [2019-03-28 12:20:20,790 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 512 states and 861 transitions. 31.95/12.15 [2019-03-28 12:20:20,798 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 512 to 512. 31.95/12.15 [2019-03-28 12:20:20,799 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 512 states. 31.95/12.15 [2019-03-28 12:20:20,800 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 512 states to 512 states and 861 transitions. 31.95/12.15 [2019-03-28 12:20:20,800 INFO L729 BuchiCegarLoop]: Abstraction has 512 states and 861 transitions. 31.95/12.15 [2019-03-28 12:20:20,800 INFO L609 BuchiCegarLoop]: Abstraction has 512 states and 861 transitions. 31.95/12.15 [2019-03-28 12:20:20,800 INFO L442 BuchiCegarLoop]: ======== Iteration 11============ 31.95/12.15 [2019-03-28 12:20:20,801 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 512 states and 861 transitions. 31.95/12.15 [2019-03-28 12:20:20,803 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 493 31.95/12.15 [2019-03-28 12:20:20,804 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 31.95/12.15 [2019-03-28 12:20:20,804 INFO L119 BuchiIsEmpty]: Starting construction of run 31.95/12.15 [2019-03-28 12:20:20,805 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 31.95/12.15 [2019-03-28 12:20:20,805 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 31.95/12.15 [2019-03-28 12:20:20,805 INFO L794 eck$LassoCheckResult]: Stem: 4985#ULTIMATE.startENTRY [871] ULTIMATE.startENTRY-->L144: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~m_pc~0_16 0) (= 0 v_~m_st~0_19) (= 2 v_~E_1~0_28) (= v_~M_E~0_27 2) (= v_~T1_E~0_18 2) (= v_~t1_pc~0_16 0) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= 0 v_~t1_st~0_19)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ULTIMATE.start_start_simulation_#t~ret6=|v_ULTIMATE.start_start_simulation_#t~ret6_4|, ~t1_st~0=v_~t1_st~0_19, ~t1_pc~0=v_~t1_pc~0_16, ~M_E~0=v_~M_E~0_27, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~E_1~0=v_~E_1~0_28, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~T1_E~0=v_~T1_E~0_18, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_19, ~m_pc~0=v_~m_pc~0_16, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_start_simulation_#t~ret6, ~t1_st~0, ~t1_pc~0, ~M_E~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_~kernel_st~0, ~E_1~0, ULTIMATE.start_main_#res, ~T1_E~0, ~t1_i~0, ~m_st~0, ~m_pc~0, ULTIMATE.start_main_~__retres1~3] 4986#L144 [557] L144-->L151-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 4993#L151-1 [672] L151-1-->L156-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 5004#L156-1 [757] L156-1-->L240-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 5013#L240-1 [759] L240-1-->L245-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 4947#L245-1 [760] L245-1-->L250-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 4948#L250-1 [679] L250-1-->L105: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_1|, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 5011#L105 [762] L105-->L105-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 5016#L105-2 [594] L105-2-->L116: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 5017#L116 [872] L116-->L290: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_24 |v_ULTIMATE.start_is_master_triggered_#res_13|) (= |v_ULTIMATE.start_is_master_triggered_#res_13| v_ULTIMATE.start_activate_threads_~tmp~1_24)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_24} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_24, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_24, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_13|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 5008#L290 [578] L290-->L290-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_9) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} AuxVars[] AssignedVars[] 5002#L290-2 [569] L290-2-->L124: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 4932#L124 [768] L124-->L124-2: Formula: (< v_~t1_pc~0_7 1) InVars {~t1_pc~0=v_~t1_pc~0_7} OutVars{~t1_pc~0=v_~t1_pc~0_7} AuxVars[] AssignedVars[] 4922#L124-2 [632] L124-2-->L135: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 4923#L135 [873] L135-->L298: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_24 |v_ULTIMATE.start_is_transmit1_triggered_#res_13|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25 |v_ULTIMATE.start_is_transmit1_triggered_#res_13|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_24, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_13|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 4933#L298 [772] L298-->L298-2: Formula: (and (= v_~t1_st~0_6 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_8)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_8} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_8, ~t1_st~0=v_~t1_st~0_6} AuxVars[] AssignedVars[~t1_st~0] 4994#L298-2 [774] L298-2-->L263-1: Formula: (> v_~M_E~0_14 1) InVars {~M_E~0=v_~M_E~0_14} OutVars{~M_E~0=v_~M_E~0_14} AuxVars[] AssignedVars[] 4928#L263-1 [777] L263-1-->L268-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 4929#L268-1 [778] L268-1-->L394-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 5003#L394-1 31.95/12.15 [2019-03-28 12:20:20,806 INFO L796 eck$LassoCheckResult]: Loop: 5003#L394-1 [874] L394-1-->L215: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 4944#L215 [875] L215-->L169: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_22, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 4956#L169 [545] L169-->L181: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_8 1) (= v_~m_st~0_7 0)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 4982#L181 [876] L181-->L196: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 5024#L196 [878] L196-->L240-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 5032#L240-2 [783] L240-2-->L240-4: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 5432#L240-4 [786] L240-4-->L245-3: Formula: (< 0 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 5431#L245-3 [789] L245-3-->L250-3: Formula: (> v_~E_1~0_7 0) InVars {~E_1~0=v_~E_1~0_7} OutVars{~E_1~0=v_~E_1~0_7} AuxVars[] AssignedVars[] 5430#L250-3 [676] L250-3-->L105-6: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_4, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_4|, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_2|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 5429#L105-6 [795] L105-6-->L105-8: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 5372#L105-8 [619] L105-8-->L116-2: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 5428#L116-2 [883] L116-2-->L290-6: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_27 |v_ULTIMATE.start_is_master_triggered_#res_16|) (= |v_ULTIMATE.start_is_master_triggered_#res_16| v_ULTIMATE.start_activate_threads_~tmp~1_27)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_27} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_27, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_27, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_16|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 5426#L290-6 [532] L290-6-->L290-8: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 5423#L290-8 [524] L290-8-->L124-6: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 5388#L124-6 [818] L124-6-->L124-8: Formula: (< v_~t1_pc~0_9 1) InVars {~t1_pc~0=v_~t1_pc~0_9} OutVars{~t1_pc~0=v_~t1_pc~0_9} AuxVars[] AssignedVars[] 5385#L124-8 [606] L124-8-->L135-2: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 5383#L135-2 [885] L135-2-->L298-6: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_27 |v_ULTIMATE.start_is_transmit1_triggered_#res_15|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27 |v_ULTIMATE.start_is_transmit1_triggered_#res_15|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_27, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_16|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_15|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 5382#L298-6 [584] L298-6-->L298-8: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 5381#L298-8 [829] L298-8-->L263-3: Formula: (> v_~M_E~0_17 1) InVars {~M_E~0=v_~M_E~0_17} OutVars{~M_E~0=v_~M_E~0_17} AuxVars[] AssignedVars[] 5217#L263-3 [832] L263-3-->L268-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 5380#L268-3 [834] L268-3-->L273-3: Formula: (< 1 v_~E_1~0_17) InVars {~E_1~0=v_~E_1~0_17} OutVars{~E_1~0=v_~E_1~0_17} AuxVars[] AssignedVars[] 5378#L273-3 [628] L273-3-->L169-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 5377#L169-1 [543] L169-1-->L181-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_7 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{~m_st~0=v_~m_st~0_6, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 5373#L181-1 [886] L181-1-->L413: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24} OutVars{ULTIMATE.start_start_simulation_#t~ret6=|v_ULTIMATE.start_start_simulation_#t~ret6_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret6, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_~tmp~3] 4951#L413 [842] L413-->L413-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 4953#L413-1 [659] L413-1-->L169-2: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret5=|v_ULTIMATE.start_stop_simulation_#t~ret5_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret5, ULTIMATE.start_stop_simulation_#res] 5375#L169-2 [536] L169-2-->L181-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18 1) (= 0 v_~m_st~0_14)) InVars {~m_st~0=v_~m_st~0_14} OutVars{~m_st~0=v_~m_st~0_14, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 5370#L181-2 [888] L181-2-->L368: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_stop_simulation_#t~ret5=|v_ULTIMATE.start_stop_simulation_#t~ret5_4|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret5] 5369#L368 [691] L368-->L375: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 5015#L375 [894] L375-->L394-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 5003#L394-1 31.95/12.15 [2019-03-28 12:20:20,807 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 31.95/12.15 [2019-03-28 12:20:20,807 INFO L82 PathProgramCache]: Analyzing trace with hash -408083689, now seen corresponding path program 1 times 31.95/12.15 [2019-03-28 12:20:20,807 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 31.95/12.15 [2019-03-28 12:20:20,807 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 31.95/12.15 [2019-03-28 12:20:20,808 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:20,808 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:20,808 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:20,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 31.95/12.15 [2019-03-28 12:20:20,871 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 31.95/12.15 [2019-03-28 12:20:20,872 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 31.95/12.15 [2019-03-28 12:20:20,872 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 31.95/12.15 [2019-03-28 12:20:20,872 INFO L799 eck$LassoCheckResult]: stem already infeasible 31.95/12.15 [2019-03-28 12:20:20,873 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 31.95/12.15 [2019-03-28 12:20:20,873 INFO L82 PathProgramCache]: Analyzing trace with hash -739229529, now seen corresponding path program 5 times 31.95/12.15 [2019-03-28 12:20:20,873 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 31.95/12.15 [2019-03-28 12:20:20,873 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 31.95/12.15 [2019-03-28 12:20:20,874 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:20,874 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:20,874 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:20,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 31.95/12.15 [2019-03-28 12:20:20,904 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 31.95/12.15 [2019-03-28 12:20:20,904 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 31.95/12.15 [2019-03-28 12:20:20,905 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 31.95/12.15 [2019-03-28 12:20:20,905 INFO L811 eck$LassoCheckResult]: loop already infeasible 31.95/12.15 [2019-03-28 12:20:20,905 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. 31.95/12.15 [2019-03-28 12:20:20,905 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 31.95/12.15 [2019-03-28 12:20:20,905 INFO L87 Difference]: Start difference. First operand 512 states and 861 transitions. cyclomatic complexity: 350 Second operand 6 states. 31.95/12.15 [2019-03-28 12:20:21,536 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 31.95/12.15 [2019-03-28 12:20:21,536 INFO L93 Difference]: Finished difference Result 1132 states and 1956 transitions. 31.95/12.15 [2019-03-28 12:20:21,537 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. 31.95/12.15 [2019-03-28 12:20:21,537 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1132 states and 1956 transitions. 31.95/12.15 [2019-03-28 12:20:21,543 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1113 31.95/12.15 [2019-03-28 12:20:21,551 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1132 states to 1132 states and 1956 transitions. 31.95/12.15 [2019-03-28 12:20:21,551 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1132 31.95/12.15 [2019-03-28 12:20:21,553 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1132 31.95/12.15 [2019-03-28 12:20:21,553 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1132 states and 1956 transitions. 31.95/12.15 [2019-03-28 12:20:21,555 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 31.95/12.15 [2019-03-28 12:20:21,555 INFO L706 BuchiCegarLoop]: Abstraction has 1132 states and 1956 transitions. 31.95/12.15 [2019-03-28 12:20:21,556 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1132 states and 1956 transitions. 31.95/12.15 [2019-03-28 12:20:21,567 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1132 to 516. 31.95/12.15 [2019-03-28 12:20:21,567 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 516 states. 31.95/12.15 [2019-03-28 12:20:21,568 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 516 states to 516 states and 848 transitions. 31.95/12.15 [2019-03-28 12:20:21,569 INFO L729 BuchiCegarLoop]: Abstraction has 516 states and 848 transitions. 31.95/12.15 [2019-03-28 12:20:21,569 INFO L609 BuchiCegarLoop]: Abstraction has 516 states and 848 transitions. 31.95/12.15 [2019-03-28 12:20:21,569 INFO L442 BuchiCegarLoop]: ======== Iteration 12============ 31.95/12.15 [2019-03-28 12:20:21,569 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 516 states and 848 transitions. 31.95/12.15 [2019-03-28 12:20:21,571 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 497 31.95/12.15 [2019-03-28 12:20:21,571 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 31.95/12.15 [2019-03-28 12:20:21,572 INFO L119 BuchiIsEmpty]: Starting construction of run 31.95/12.15 [2019-03-28 12:20:21,572 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 31.95/12.15 [2019-03-28 12:20:21,572 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 31.95/12.15 [2019-03-28 12:20:21,573 INFO L794 eck$LassoCheckResult]: Stem: 6660#ULTIMATE.startENTRY [871] ULTIMATE.startENTRY-->L144: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~m_pc~0_16 0) (= 0 v_~m_st~0_19) (= 2 v_~E_1~0_28) (= v_~M_E~0_27 2) (= v_~T1_E~0_18 2) (= v_~t1_pc~0_16 0) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= 0 v_~t1_st~0_19)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ULTIMATE.start_start_simulation_#t~ret6=|v_ULTIMATE.start_start_simulation_#t~ret6_4|, ~t1_st~0=v_~t1_st~0_19, ~t1_pc~0=v_~t1_pc~0_16, ~M_E~0=v_~M_E~0_27, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~E_1~0=v_~E_1~0_28, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~T1_E~0=v_~T1_E~0_18, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_19, ~m_pc~0=v_~m_pc~0_16, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_start_simulation_#t~ret6, ~t1_st~0, ~t1_pc~0, ~M_E~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_~kernel_st~0, ~E_1~0, ULTIMATE.start_main_#res, ~T1_E~0, ~t1_i~0, ~m_st~0, ~m_pc~0, ULTIMATE.start_main_~__retres1~3] 6661#L144 [557] L144-->L151-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 6667#L151-1 [672] L151-1-->L156-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 6679#L156-1 [757] L156-1-->L240-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 6690#L240-1 [759] L240-1-->L245-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 6621#L245-1 [760] L245-1-->L250-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 6622#L250-1 [679] L250-1-->L105: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_1|, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 6688#L105 [762] L105-->L105-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 6695#L105-2 [594] L105-2-->L116: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 6696#L116 [872] L116-->L290: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_24 |v_ULTIMATE.start_is_master_triggered_#res_13|) (= |v_ULTIMATE.start_is_master_triggered_#res_13| v_ULTIMATE.start_activate_threads_~tmp~1_24)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_24} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_24, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_24, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_13|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 6687#L290 [578] L290-->L290-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_9) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} AuxVars[] AssignedVars[] 6677#L290-2 [569] L290-2-->L124: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 6606#L124 [768] L124-->L124-2: Formula: (< v_~t1_pc~0_7 1) InVars {~t1_pc~0=v_~t1_pc~0_7} OutVars{~t1_pc~0=v_~t1_pc~0_7} AuxVars[] AssignedVars[] 6598#L124-2 [632] L124-2-->L135: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 6599#L135 [873] L135-->L298: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_24 |v_ULTIMATE.start_is_transmit1_triggered_#res_13|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25 |v_ULTIMATE.start_is_transmit1_triggered_#res_13|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_24, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_13|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 6607#L298 [611] L298-->L298-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_9) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} AuxVars[] AssignedVars[] 6669#L298-2 [774] L298-2-->L263-1: Formula: (> v_~M_E~0_14 1) InVars {~M_E~0=v_~M_E~0_14} OutVars{~M_E~0=v_~M_E~0_14} AuxVars[] AssignedVars[] 6604#L263-1 [777] L263-1-->L268-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 6605#L268-1 [778] L268-1-->L394-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 6678#L394-1 31.95/12.15 [2019-03-28 12:20:21,574 INFO L796 eck$LassoCheckResult]: Loop: 6678#L394-1 [874] L394-1-->L215: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 6926#L215 [875] L215-->L169: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_22, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 6925#L169 [545] L169-->L181: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_8 1) (= v_~m_st~0_7 0)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 6923#L181 [876] L181-->L196: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 6921#L196 [878] L196-->L240-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 6922#L240-2 [783] L240-2-->L240-4: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 7016#L240-4 [786] L240-4-->L245-3: Formula: (< 0 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 7015#L245-3 [789] L245-3-->L250-3: Formula: (> v_~E_1~0_7 0) InVars {~E_1~0=v_~E_1~0_7} OutVars{~E_1~0=v_~E_1~0_7} AuxVars[] AssignedVars[] 7006#L250-3 [676] L250-3-->L105-6: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_4, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_4|, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_2|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 6774#L105-6 [795] L105-6-->L105-8: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 6772#L105-8 [619] L105-8-->L116-2: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 6770#L116-2 [883] L116-2-->L290-6: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_27 |v_ULTIMATE.start_is_master_triggered_#res_16|) (= |v_ULTIMATE.start_is_master_triggered_#res_16| v_ULTIMATE.start_activate_threads_~tmp~1_27)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_27} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_27, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_27, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_16|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 6768#L290-6 [532] L290-6-->L290-8: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 6765#L290-8 [524] L290-8-->L124-6: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 6759#L124-6 [818] L124-6-->L124-8: Formula: (< v_~t1_pc~0_9 1) InVars {~t1_pc~0=v_~t1_pc~0_9} OutVars{~t1_pc~0=v_~t1_pc~0_9} AuxVars[] AssignedVars[] 6753#L124-8 [606] L124-8-->L135-2: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 6754#L135-2 [885] L135-2-->L298-6: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_27 |v_ULTIMATE.start_is_transmit1_triggered_#res_15|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27 |v_ULTIMATE.start_is_transmit1_triggered_#res_15|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_27, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_16|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_15|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 6745#L298-6 [584] L298-6-->L298-8: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 6746#L298-8 [829] L298-8-->L263-3: Formula: (> v_~M_E~0_17 1) InVars {~M_E~0=v_~M_E~0_17} OutVars{~M_E~0=v_~M_E~0_17} AuxVars[] AssignedVars[] 6868#L263-3 [832] L263-3-->L268-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 6941#L268-3 [834] L268-3-->L273-3: Formula: (< 1 v_~E_1~0_17) InVars {~E_1~0=v_~E_1~0_17} OutVars{~E_1~0=v_~E_1~0_17} AuxVars[] AssignedVars[] 6940#L273-3 [628] L273-3-->L169-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 6939#L169-1 [543] L169-1-->L181-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_7 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{~m_st~0=v_~m_st~0_6, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 6937#L181-1 [886] L181-1-->L413: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24} OutVars{ULTIMATE.start_start_simulation_#t~ret6=|v_ULTIMATE.start_start_simulation_#t~ret6_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret6, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_~tmp~3] 6936#L413 [842] L413-->L413-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 6934#L413-1 [659] L413-1-->L169-2: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret5=|v_ULTIMATE.start_stop_simulation_#t~ret5_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret5, ULTIMATE.start_stop_simulation_#res] 6933#L169-2 [536] L169-2-->L181-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18 1) (= 0 v_~m_st~0_14)) InVars {~m_st~0=v_~m_st~0_14} OutVars{~m_st~0=v_~m_st~0_14, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 6931#L181-2 [888] L181-2-->L368: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_stop_simulation_#t~ret5=|v_ULTIMATE.start_stop_simulation_#t~ret5_4|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret5] 6930#L368 [691] L368-->L375: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 6929#L375 [894] L375-->L394-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 6678#L394-1 31.95/12.15 [2019-03-28 12:20:21,574 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 31.95/12.15 [2019-03-28 12:20:21,574 INFO L82 PathProgramCache]: Analyzing trace with hash -412880040, now seen corresponding path program 1 times 31.95/12.15 [2019-03-28 12:20:21,574 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 31.95/12.15 [2019-03-28 12:20:21,574 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 31.95/12.15 [2019-03-28 12:20:21,575 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:21,575 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:21,576 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:21,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 31.95/12.15 [2019-03-28 12:20:21,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 31.95/12.15 [2019-03-28 12:20:21,606 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 31.95/12.15 [2019-03-28 12:20:21,606 INFO L82 PathProgramCache]: Analyzing trace with hash -739229529, now seen corresponding path program 6 times 31.95/12.15 [2019-03-28 12:20:21,606 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 31.95/12.15 [2019-03-28 12:20:21,606 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 31.95/12.15 [2019-03-28 12:20:21,607 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:21,607 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:21,607 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:21,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 31.95/12.15 [2019-03-28 12:20:21,636 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 31.95/12.15 [2019-03-28 12:20:21,636 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 31.95/12.15 [2019-03-28 12:20:21,636 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 31.95/12.15 [2019-03-28 12:20:21,636 INFO L811 eck$LassoCheckResult]: loop already infeasible 31.95/12.15 [2019-03-28 12:20:21,637 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. 31.95/12.15 [2019-03-28 12:20:21,637 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 31.95/12.15 [2019-03-28 12:20:21,637 INFO L87 Difference]: Start difference. First operand 516 states and 848 transitions. cyclomatic complexity: 333 Second operand 4 states. 31.95/12.15 [2019-03-28 12:20:21,874 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 31.95/12.15 [2019-03-28 12:20:21,874 INFO L93 Difference]: Finished difference Result 865 states and 1417 transitions. 31.95/12.15 [2019-03-28 12:20:21,874 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. 31.95/12.15 [2019-03-28 12:20:21,875 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 865 states and 1417 transitions. 31.95/12.15 [2019-03-28 12:20:21,879 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 846 31.95/12.15 [2019-03-28 12:20:21,884 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 865 states to 865 states and 1417 transitions. 31.95/12.15 [2019-03-28 12:20:21,885 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 865 31.95/12.15 [2019-03-28 12:20:21,885 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 865 31.95/12.15 [2019-03-28 12:20:21,886 INFO L73 IsDeterministic]: Start isDeterministic. Operand 865 states and 1417 transitions. 31.95/12.15 [2019-03-28 12:20:21,887 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 31.95/12.15 [2019-03-28 12:20:21,887 INFO L706 BuchiCegarLoop]: Abstraction has 865 states and 1417 transitions. 31.95/12.15 [2019-03-28 12:20:21,888 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 865 states and 1417 transitions. 31.95/12.15 [2019-03-28 12:20:21,897 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 865 to 532. 31.95/12.15 [2019-03-28 12:20:21,897 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 532 states. 31.95/12.15 [2019-03-28 12:20:21,899 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 532 states to 532 states and 872 transitions. 31.95/12.15 [2019-03-28 12:20:21,899 INFO L729 BuchiCegarLoop]: Abstraction has 532 states and 872 transitions. 31.95/12.15 [2019-03-28 12:20:21,899 INFO L609 BuchiCegarLoop]: Abstraction has 532 states and 872 transitions. 31.95/12.15 [2019-03-28 12:20:21,899 INFO L442 BuchiCegarLoop]: ======== Iteration 13============ 31.95/12.15 [2019-03-28 12:20:21,899 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 532 states and 872 transitions. 31.95/12.15 [2019-03-28 12:20:21,902 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 513 31.95/12.15 [2019-03-28 12:20:21,902 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 31.95/12.15 [2019-03-28 12:20:21,902 INFO L119 BuchiIsEmpty]: Starting construction of run 31.95/12.15 [2019-03-28 12:20:21,903 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 31.95/12.15 [2019-03-28 12:20:21,903 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 31.95/12.15 [2019-03-28 12:20:21,903 INFO L794 eck$LassoCheckResult]: Stem: 8050#ULTIMATE.startENTRY [871] ULTIMATE.startENTRY-->L144: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~m_pc~0_16 0) (= 0 v_~m_st~0_19) (= 2 v_~E_1~0_28) (= v_~M_E~0_27 2) (= v_~T1_E~0_18 2) (= v_~t1_pc~0_16 0) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= 0 v_~t1_st~0_19)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ULTIMATE.start_start_simulation_#t~ret6=|v_ULTIMATE.start_start_simulation_#t~ret6_4|, ~t1_st~0=v_~t1_st~0_19, ~t1_pc~0=v_~t1_pc~0_16, ~M_E~0=v_~M_E~0_27, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~E_1~0=v_~E_1~0_28, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~T1_E~0=v_~T1_E~0_18, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_19, ~m_pc~0=v_~m_pc~0_16, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_start_simulation_#t~ret6, ~t1_st~0, ~t1_pc~0, ~M_E~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_~kernel_st~0, ~E_1~0, ULTIMATE.start_main_#res, ~T1_E~0, ~t1_i~0, ~m_st~0, ~m_pc~0, ULTIMATE.start_main_~__retres1~3] 8051#L144 [557] L144-->L151-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 8057#L151-1 [672] L151-1-->L156-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 8070#L156-1 [757] L156-1-->L240-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 8080#L240-1 [759] L240-1-->L245-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 8011#L245-1 [760] L245-1-->L250-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 8012#L250-1 [679] L250-1-->L105: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_1|, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 8078#L105 [762] L105-->L105-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 8087#L105-2 [594] L105-2-->L116: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 8088#L116 [872] L116-->L290: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_24 |v_ULTIMATE.start_is_master_triggered_#res_13|) (= |v_ULTIMATE.start_is_master_triggered_#res_13| v_ULTIMATE.start_activate_threads_~tmp~1_24)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_24} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_24, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_24, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_13|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 8074#L290 [578] L290-->L290-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_9) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} AuxVars[] AssignedVars[] 8068#L290-2 [569] L290-2-->L124: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 7996#L124 [768] L124-->L124-2: Formula: (< v_~t1_pc~0_7 1) InVars {~t1_pc~0=v_~t1_pc~0_7} OutVars{~t1_pc~0=v_~t1_pc~0_7} AuxVars[] AssignedVars[] 7986#L124-2 [632] L124-2-->L135: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 7987#L135 [873] L135-->L298: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_24 |v_ULTIMATE.start_is_transmit1_triggered_#res_13|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25 |v_ULTIMATE.start_is_transmit1_triggered_#res_13|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_24, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_13|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 7997#L298 [611] L298-->L298-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_9) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} AuxVars[] AssignedVars[] 8058#L298-2 [774] L298-2-->L263-1: Formula: (> v_~M_E~0_14 1) InVars {~M_E~0=v_~M_E~0_14} OutVars{~M_E~0=v_~M_E~0_14} AuxVars[] AssignedVars[] 7992#L263-1 [777] L263-1-->L268-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 7993#L268-1 [778] L268-1-->L394-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 8069#L394-1 31.95/12.15 [2019-03-28 12:20:21,904 INFO L796 eck$LassoCheckResult]: Loop: 8069#L394-1 [874] L394-1-->L215: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 8267#L215 [875] L215-->L169: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_22, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 8265#L169 [780] L169-->L173: Formula: (< v_~m_st~0_9 0) InVars {~m_st~0=v_~m_st~0_9} OutVars{~m_st~0=v_~m_st~0_9} AuxVars[] AssignedVars[] 8261#L173 [784] L173-->L181: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_12 0) (> 0 v_~t1_st~0_11)) InVars {~t1_st~0=v_~t1_st~0_11} OutVars{~t1_st~0=v_~t1_st~0_11, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_12} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 8253#L181 [876] L181-->L196: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 8250#L196 [878] L196-->L240-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 8247#L240-2 [783] L240-2-->L240-4: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 8248#L240-4 [786] L240-4-->L245-3: Formula: (< 0 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 8002#L245-3 [789] L245-3-->L250-3: Formula: (> v_~E_1~0_7 0) InVars {~E_1~0=v_~E_1~0_7} OutVars{~E_1~0=v_~E_1~0_7} AuxVars[] AssignedVars[] 8003#L250-3 [676] L250-3-->L105-6: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_4, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_4|, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_2|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 8073#L105-6 [795] L105-6-->L105-8: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 8101#L105-8 [619] L105-8-->L116-2: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 8102#L116-2 [883] L116-2-->L290-6: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_27 |v_ULTIMATE.start_is_master_triggered_#res_16|) (= |v_ULTIMATE.start_is_master_triggered_#res_16| v_ULTIMATE.start_activate_threads_~tmp~1_27)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_27} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_27, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_27, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_16|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 8315#L290-6 [532] L290-6-->L290-8: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 8314#L290-8 [524] L290-8-->L124-6: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 8300#L124-6 [818] L124-6-->L124-8: Formula: (< v_~t1_pc~0_9 1) InVars {~t1_pc~0=v_~t1_pc~0_9} OutVars{~t1_pc~0=v_~t1_pc~0_9} AuxVars[] AssignedVars[] 8297#L124-8 [606] L124-8-->L135-2: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 8295#L135-2 [885] L135-2-->L298-6: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_27 |v_ULTIMATE.start_is_transmit1_triggered_#res_15|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27 |v_ULTIMATE.start_is_transmit1_triggered_#res_15|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_27, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_16|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_15|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 8293#L298-6 [584] L298-6-->L298-8: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 8291#L298-8 [829] L298-8-->L263-3: Formula: (> v_~M_E~0_17 1) InVars {~M_E~0=v_~M_E~0_17} OutVars{~M_E~0=v_~M_E~0_17} AuxVars[] AssignedVars[] 8288#L263-3 [832] L263-3-->L268-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 8287#L268-3 [834] L268-3-->L273-3: Formula: (< 1 v_~E_1~0_17) InVars {~E_1~0=v_~E_1~0_17} OutVars{~E_1~0=v_~E_1~0_17} AuxVars[] AssignedVars[] 8286#L273-3 [628] L273-3-->L169-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 8285#L169-1 [543] L169-1-->L181-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_7 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{~m_st~0=v_~m_st~0_6, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 8282#L181-1 [886] L181-1-->L413: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24} OutVars{ULTIMATE.start_start_simulation_#t~ret6=|v_ULTIMATE.start_start_simulation_#t~ret6_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret6, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_~tmp~3] 8280#L413 [842] L413-->L413-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 8278#L413-1 [659] L413-1-->L169-2: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret5=|v_ULTIMATE.start_stop_simulation_#t~ret5_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret5, ULTIMATE.start_stop_simulation_#res] 8277#L169-2 [536] L169-2-->L181-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18 1) (= 0 v_~m_st~0_14)) InVars {~m_st~0=v_~m_st~0_14} OutVars{~m_st~0=v_~m_st~0_14, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 8275#L181-2 [888] L181-2-->L368: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_stop_simulation_#t~ret5=|v_ULTIMATE.start_stop_simulation_#t~ret5_4|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret5] 8273#L368 [691] L368-->L375: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 8270#L375 [894] L375-->L394-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 8069#L394-1 31.95/12.15 [2019-03-28 12:20:21,904 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 31.95/12.15 [2019-03-28 12:20:21,905 INFO L82 PathProgramCache]: Analyzing trace with hash -412880040, now seen corresponding path program 2 times 31.95/12.15 [2019-03-28 12:20:21,905 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 31.95/12.15 [2019-03-28 12:20:21,905 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 31.95/12.15 [2019-03-28 12:20:21,906 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:21,906 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:21,906 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:21,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 31.95/12.15 [2019-03-28 12:20:21,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 31.95/12.15 [2019-03-28 12:20:21,916 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 31.95/12.15 [2019-03-28 12:20:21,917 INFO L82 PathProgramCache]: Analyzing trace with hash 689973152, now seen corresponding path program 1 times 31.95/12.15 [2019-03-28 12:20:21,917 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 31.95/12.15 [2019-03-28 12:20:21,917 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 31.95/12.15 [2019-03-28 12:20:21,918 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:21,918 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:21,918 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:21,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 31.95/12.15 [2019-03-28 12:20:21,938 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 31.95/12.15 [2019-03-28 12:20:21,939 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 31.95/12.15 [2019-03-28 12:20:21,939 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 31.95/12.15 [2019-03-28 12:20:21,939 INFO L811 eck$LassoCheckResult]: loop already infeasible 31.95/12.15 [2019-03-28 12:20:21,939 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 31.95/12.15 [2019-03-28 12:20:21,939 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 31.95/12.15 [2019-03-28 12:20:21,940 INFO L87 Difference]: Start difference. First operand 532 states and 872 transitions. cyclomatic complexity: 341 Second operand 3 states. 31.95/12.15 [2019-03-28 12:20:22,145 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 31.95/12.15 [2019-03-28 12:20:22,145 INFO L93 Difference]: Finished difference Result 951 states and 1505 transitions. 31.95/12.15 [2019-03-28 12:20:22,146 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 31.95/12.15 [2019-03-28 12:20:22,146 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 951 states and 1505 transitions. 31.95/12.15 [2019-03-28 12:20:22,151 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 932 31.95/12.15 [2019-03-28 12:20:22,157 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 951 states to 951 states and 1505 transitions. 31.95/12.15 [2019-03-28 12:20:22,157 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 951 31.95/12.15 [2019-03-28 12:20:22,158 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 951 31.95/12.15 [2019-03-28 12:20:22,158 INFO L73 IsDeterministic]: Start isDeterministic. Operand 951 states and 1505 transitions. 31.95/12.15 [2019-03-28 12:20:22,160 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 31.95/12.15 [2019-03-28 12:20:22,160 INFO L706 BuchiCegarLoop]: Abstraction has 951 states and 1505 transitions. 31.95/12.15 [2019-03-28 12:20:22,161 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 951 states and 1505 transitions. 31.95/12.15 [2019-03-28 12:20:22,176 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 951 to 951. 31.95/12.15 [2019-03-28 12:20:22,176 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 951 states. 31.95/12.15 [2019-03-28 12:20:22,178 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 951 states to 951 states and 1505 transitions. 31.95/12.15 [2019-03-28 12:20:22,179 INFO L729 BuchiCegarLoop]: Abstraction has 951 states and 1505 transitions. 31.95/12.15 [2019-03-28 12:20:22,179 INFO L609 BuchiCegarLoop]: Abstraction has 951 states and 1505 transitions. 31.95/12.15 [2019-03-28 12:20:22,179 INFO L442 BuchiCegarLoop]: ======== Iteration 14============ 31.95/12.15 [2019-03-28 12:20:22,179 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 951 states and 1505 transitions. 31.95/12.15 [2019-03-28 12:20:22,183 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 932 31.95/12.15 [2019-03-28 12:20:22,184 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 31.95/12.15 [2019-03-28 12:20:22,184 INFO L119 BuchiIsEmpty]: Starting construction of run 31.95/12.15 [2019-03-28 12:20:22,185 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 31.95/12.15 [2019-03-28 12:20:22,185 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 31.95/12.15 [2019-03-28 12:20:22,185 INFO L794 eck$LassoCheckResult]: Stem: 9537#ULTIMATE.startENTRY [871] ULTIMATE.startENTRY-->L144: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~m_pc~0_16 0) (= 0 v_~m_st~0_19) (= 2 v_~E_1~0_28) (= v_~M_E~0_27 2) (= v_~T1_E~0_18 2) (= v_~t1_pc~0_16 0) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= 0 v_~t1_st~0_19)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ULTIMATE.start_start_simulation_#t~ret6=|v_ULTIMATE.start_start_simulation_#t~ret6_4|, ~t1_st~0=v_~t1_st~0_19, ~t1_pc~0=v_~t1_pc~0_16, ~M_E~0=v_~M_E~0_27, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~E_1~0=v_~E_1~0_28, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~T1_E~0=v_~T1_E~0_18, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_19, ~m_pc~0=v_~m_pc~0_16, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_start_simulation_#t~ret6, ~t1_st~0, ~t1_pc~0, ~M_E~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_~kernel_st~0, ~E_1~0, ULTIMATE.start_main_#res, ~T1_E~0, ~t1_i~0, ~m_st~0, ~m_pc~0, ULTIMATE.start_main_~__retres1~3] 9538#L144 [557] L144-->L151-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 9544#L151-1 [672] L151-1-->L156-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 9559#L156-1 [757] L156-1-->L240-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 9572#L240-1 [759] L240-1-->L245-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 9500#L245-1 [760] L245-1-->L250-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 9501#L250-1 [679] L250-1-->L105: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_1|, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 9571#L105 [762] L105-->L105-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 9577#L105-2 [594] L105-2-->L116: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 9578#L116 [872] L116-->L290: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_24 |v_ULTIMATE.start_is_master_triggered_#res_13|) (= |v_ULTIMATE.start_is_master_triggered_#res_13| v_ULTIMATE.start_activate_threads_~tmp~1_24)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_24} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_24, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_24, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_13|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 9565#L290 [578] L290-->L290-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_9) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} AuxVars[] AssignedVars[] 9556#L290-2 [569] L290-2-->L124: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 9485#L124 [768] L124-->L124-2: Formula: (< v_~t1_pc~0_7 1) InVars {~t1_pc~0=v_~t1_pc~0_7} OutVars{~t1_pc~0=v_~t1_pc~0_7} AuxVars[] AssignedVars[] 9475#L124-2 [632] L124-2-->L135: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 9476#L135 [873] L135-->L298: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_24 |v_ULTIMATE.start_is_transmit1_triggered_#res_13|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25 |v_ULTIMATE.start_is_transmit1_triggered_#res_13|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_24, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_13|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 9486#L298 [611] L298-->L298-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_9) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} AuxVars[] AssignedVars[] 9546#L298-2 [774] L298-2-->L263-1: Formula: (> v_~M_E~0_14 1) InVars {~M_E~0=v_~M_E~0_14} OutVars{~M_E~0=v_~M_E~0_14} AuxVars[] AssignedVars[] 9481#L263-1 [777] L263-1-->L268-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 9482#L268-1 [778] L268-1-->L394-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 9557#L394-1 31.95/12.15 [2019-03-28 12:20:22,186 INFO L796 eck$LassoCheckResult]: Loop: 9557#L394-1 [874] L394-1-->L215: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 9983#L215 [875] L215-->L169: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_22, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 9979#L169 [781] L169-->L173: Formula: (> v_~m_st~0_9 0) InVars {~m_st~0=v_~m_st~0_9} OutVars{~m_st~0=v_~m_st~0_9} AuxVars[] AssignedVars[] 9977#L173 [784] L173-->L181: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_12 0) (> 0 v_~t1_st~0_11)) InVars {~t1_st~0=v_~t1_st~0_11} OutVars{~t1_st~0=v_~t1_st~0_11, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_12} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 9978#L181 [876] L181-->L196: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 10418#L196 [878] L196-->L240-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 10416#L240-2 [783] L240-2-->L240-4: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 10415#L240-4 [786] L240-4-->L245-3: Formula: (< 0 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 10394#L245-3 [789] L245-3-->L250-3: Formula: (> v_~E_1~0_7 0) InVars {~E_1~0=v_~E_1~0_7} OutVars{~E_1~0=v_~E_1~0_7} AuxVars[] AssignedVars[] 10393#L250-3 [676] L250-3-->L105-6: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_4, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_4|, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_2|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 10201#L105-6 [795] L105-6-->L105-8: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 10199#L105-8 [619] L105-8-->L116-2: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 10198#L116-2 [883] L116-2-->L290-6: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_27 |v_ULTIMATE.start_is_master_triggered_#res_16|) (= |v_ULTIMATE.start_is_master_triggered_#res_16| v_ULTIMATE.start_activate_threads_~tmp~1_27)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_27} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_27, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_27, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_16|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 10197#L290-6 [532] L290-6-->L290-8: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 10145#L290-8 [524] L290-8-->L124-6: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 10074#L124-6 [818] L124-6-->L124-8: Formula: (< v_~t1_pc~0_9 1) InVars {~t1_pc~0=v_~t1_pc~0_9} OutVars{~t1_pc~0=v_~t1_pc~0_9} AuxVars[] AssignedVars[] 10069#L124-8 [606] L124-8-->L135-2: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 10060#L135-2 [885] L135-2-->L298-6: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_27 |v_ULTIMATE.start_is_transmit1_triggered_#res_15|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27 |v_ULTIMATE.start_is_transmit1_triggered_#res_15|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_27, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_16|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_15|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 10056#L298-6 [584] L298-6-->L298-8: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 10055#L298-8 [829] L298-8-->L263-3: Formula: (> v_~M_E~0_17 1) InVars {~M_E~0=v_~M_E~0_17} OutVars{~M_E~0=v_~M_E~0_17} AuxVars[] AssignedVars[] 10047#L263-3 [832] L263-3-->L268-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 10042#L268-3 [834] L268-3-->L273-3: Formula: (< 1 v_~E_1~0_17) InVars {~E_1~0=v_~E_1~0_17} OutVars{~E_1~0=v_~E_1~0_17} AuxVars[] AssignedVars[] 10034#L273-3 [628] L273-3-->L169-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 10022#L169-1 [543] L169-1-->L181-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_7 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{~m_st~0=v_~m_st~0_6, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 10019#L181-1 [886] L181-1-->L413: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24} OutVars{ULTIMATE.start_start_simulation_#t~ret6=|v_ULTIMATE.start_start_simulation_#t~ret6_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret6, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_~tmp~3] 10016#L413 [842] L413-->L413-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 10006#L413-1 [659] L413-1-->L169-2: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret5=|v_ULTIMATE.start_stop_simulation_#t~ret5_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret5, ULTIMATE.start_stop_simulation_#res] 10001#L169-2 [536] L169-2-->L181-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18 1) (= 0 v_~m_st~0_14)) InVars {~m_st~0=v_~m_st~0_14} OutVars{~m_st~0=v_~m_st~0_14, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 9995#L181-2 [888] L181-2-->L368: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_stop_simulation_#t~ret5=|v_ULTIMATE.start_stop_simulation_#t~ret5_4|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret5] 9992#L368 [691] L368-->L375: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 9987#L375 [894] L375-->L394-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 9557#L394-1 31.95/12.15 [2019-03-28 12:20:22,186 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 31.95/12.15 [2019-03-28 12:20:22,186 INFO L82 PathProgramCache]: Analyzing trace with hash -412880040, now seen corresponding path program 3 times 31.95/12.15 [2019-03-28 12:20:22,186 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 31.95/12.15 [2019-03-28 12:20:22,187 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 31.95/12.15 [2019-03-28 12:20:22,187 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:22,188 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:22,188 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:22,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 31.95/12.15 [2019-03-28 12:20:22,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 31.95/12.15 [2019-03-28 12:20:22,198 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 31.95/12.15 [2019-03-28 12:20:22,198 INFO L82 PathProgramCache]: Analyzing trace with hash 1383074849, now seen corresponding path program 1 times 31.95/12.15 [2019-03-28 12:20:22,198 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 31.95/12.15 [2019-03-28 12:20:22,198 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 31.95/12.15 [2019-03-28 12:20:22,199 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:22,199 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:22,199 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:22,203 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 31.95/12.15 [2019-03-28 12:20:22,221 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 31.95/12.15 [2019-03-28 12:20:22,221 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 31.95/12.15 [2019-03-28 12:20:22,222 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 31.95/12.15 [2019-03-28 12:20:22,222 INFO L811 eck$LassoCheckResult]: loop already infeasible 31.95/12.15 [2019-03-28 12:20:22,222 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 31.95/12.15 [2019-03-28 12:20:22,222 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 31.95/12.15 [2019-03-28 12:20:22,223 INFO L87 Difference]: Start difference. First operand 951 states and 1505 transitions. cyclomatic complexity: 556 Second operand 3 states. 31.95/12.15 [2019-03-28 12:20:22,410 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 31.95/12.15 [2019-03-28 12:20:22,411 INFO L93 Difference]: Finished difference Result 1227 states and 1888 transitions. 31.95/12.15 [2019-03-28 12:20:22,411 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 31.95/12.15 [2019-03-28 12:20:22,411 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1227 states and 1888 transitions. 31.95/12.15 [2019-03-28 12:20:22,418 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1191 31.95/12.15 [2019-03-28 12:20:22,425 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1227 states to 1227 states and 1888 transitions. 31.95/12.15 [2019-03-28 12:20:22,425 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1227 31.95/12.15 [2019-03-28 12:20:22,426 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1227 31.95/12.15 [2019-03-28 12:20:22,426 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1227 states and 1888 transitions. 31.95/12.15 [2019-03-28 12:20:22,428 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 31.95/12.15 [2019-03-28 12:20:22,428 INFO L706 BuchiCegarLoop]: Abstraction has 1227 states and 1888 transitions. 31.95/12.15 [2019-03-28 12:20:22,429 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1227 states and 1888 transitions. 31.95/12.15 [2019-03-28 12:20:22,448 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1227 to 1210. 31.95/12.15 [2019-03-28 12:20:22,448 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1210 states. 31.95/12.15 [2019-03-28 12:20:22,451 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1210 states to 1210 states and 1866 transitions. 31.95/12.15 [2019-03-28 12:20:22,452 INFO L729 BuchiCegarLoop]: Abstraction has 1210 states and 1866 transitions. 31.95/12.15 [2019-03-28 12:20:22,452 INFO L609 BuchiCegarLoop]: Abstraction has 1210 states and 1866 transitions. 31.95/12.15 [2019-03-28 12:20:22,452 INFO L442 BuchiCegarLoop]: ======== Iteration 15============ 31.95/12.15 [2019-03-28 12:20:22,452 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1210 states and 1866 transitions. 31.95/12.15 [2019-03-28 12:20:22,457 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1174 31.95/12.15 [2019-03-28 12:20:22,457 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 31.95/12.15 [2019-03-28 12:20:22,457 INFO L119 BuchiIsEmpty]: Starting construction of run 31.95/12.15 [2019-03-28 12:20:22,458 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 31.95/12.15 [2019-03-28 12:20:22,458 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 31.95/12.15 [2019-03-28 12:20:22,459 INFO L794 eck$LassoCheckResult]: Stem: 11722#ULTIMATE.startENTRY [871] ULTIMATE.startENTRY-->L144: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~m_pc~0_16 0) (= 0 v_~m_st~0_19) (= 2 v_~E_1~0_28) (= v_~M_E~0_27 2) (= v_~T1_E~0_18 2) (= v_~t1_pc~0_16 0) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= 0 v_~t1_st~0_19)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ULTIMATE.start_start_simulation_#t~ret6=|v_ULTIMATE.start_start_simulation_#t~ret6_4|, ~t1_st~0=v_~t1_st~0_19, ~t1_pc~0=v_~t1_pc~0_16, ~M_E~0=v_~M_E~0_27, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~E_1~0=v_~E_1~0_28, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~T1_E~0=v_~T1_E~0_18, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_19, ~m_pc~0=v_~m_pc~0_16, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_start_simulation_#t~ret6, ~t1_st~0, ~t1_pc~0, ~M_E~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_~kernel_st~0, ~E_1~0, ULTIMATE.start_main_#res, ~T1_E~0, ~t1_i~0, ~m_st~0, ~m_pc~0, ULTIMATE.start_main_~__retres1~3] 11723#L144 [753] L144-->L151-1: Formula: (and (> v_~m_i~0_4 1) (= v_~m_st~0_3 2)) InVars {~m_i~0=v_~m_i~0_4} OutVars{~m_st~0=v_~m_st~0_3, ~m_i~0=v_~m_i~0_4} AuxVars[] AssignedVars[~m_st~0] 11729#L151-1 [672] L151-1-->L156-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 11746#L156-1 [757] L156-1-->L240-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 11759#L240-1 [759] L240-1-->L245-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 11686#L245-1 [760] L245-1-->L250-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 11687#L250-1 [679] L250-1-->L105: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_1|, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 11758#L105 [762] L105-->L105-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 11763#L105-2 [594] L105-2-->L116: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 11764#L116 [872] L116-->L290: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_24 |v_ULTIMATE.start_is_master_triggered_#res_13|) (= |v_ULTIMATE.start_is_master_triggered_#res_13| v_ULTIMATE.start_activate_threads_~tmp~1_24)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_24} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_24, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_24, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_13|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 11751#L290 [578] L290-->L290-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_9) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} AuxVars[] AssignedVars[] 11743#L290-2 [569] L290-2-->L124: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 11744#L124 [768] L124-->L124-2: Formula: (< v_~t1_pc~0_7 1) InVars {~t1_pc~0=v_~t1_pc~0_7} OutVars{~t1_pc~0=v_~t1_pc~0_7} AuxVars[] AssignedVars[] 11659#L124-2 [632] L124-2-->L135: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 11660#L135 [873] L135-->L298: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_24 |v_ULTIMATE.start_is_transmit1_triggered_#res_13|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25 |v_ULTIMATE.start_is_transmit1_triggered_#res_13|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_24, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_13|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 11772#L298 [611] L298-->L298-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_9) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} AuxVars[] AssignedVars[] 11773#L298-2 [774] L298-2-->L263-1: Formula: (> v_~M_E~0_14 1) InVars {~M_E~0=v_~M_E~0_14} OutVars{~M_E~0=v_~M_E~0_14} AuxVars[] AssignedVars[] 11665#L263-1 [777] L263-1-->L268-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 11666#L268-1 [778] L268-1-->L394-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 11745#L394-1 31.95/12.15 [2019-03-28 12:20:22,459 INFO L796 eck$LassoCheckResult]: Loop: 11745#L394-1 [874] L394-1-->L215: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 11696#L215 [875] L215-->L169: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_22, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 11697#L169 [781] L169-->L173: Formula: (> v_~m_st~0_9 0) InVars {~m_st~0=v_~m_st~0_9} OutVars{~m_st~0=v_~m_st~0_9} AuxVars[] AssignedVars[] 11720#L173 [784] L173-->L181: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_12 0) (> 0 v_~t1_st~0_11)) InVars {~t1_st~0=v_~t1_st~0_11} OutVars{~t1_st~0=v_~t1_st~0_11, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_12} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 12777#L181 [876] L181-->L196: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 12866#L196 [878] L196-->L240-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 11782#L240-2 [783] L240-2-->L240-4: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 11778#L240-4 [786] L240-4-->L245-3: Formula: (< 0 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 11677#L245-3 [789] L245-3-->L250-3: Formula: (> v_~E_1~0_7 0) InVars {~E_1~0=v_~E_1~0_7} OutVars{~E_1~0=v_~E_1~0_7} AuxVars[] AssignedVars[] 11678#L250-3 [676] L250-3-->L105-6: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_4, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_4|, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_2|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 11750#L105-6 [795] L105-6-->L105-8: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 11777#L105-8 [619] L105-8-->L116-2: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 11765#L116-2 [883] L116-2-->L290-6: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_27 |v_ULTIMATE.start_is_master_triggered_#res_16|) (= |v_ULTIMATE.start_is_master_triggered_#res_16| v_ULTIMATE.start_activate_threads_~tmp~1_27)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_27} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_27, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_27, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_16|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 11714#L290-6 [532] L290-6-->L290-8: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 11709#L290-8 [524] L290-8-->L124-6: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 11688#L124-6 [818] L124-6-->L124-8: Formula: (< v_~t1_pc~0_9 1) InVars {~t1_pc~0=v_~t1_pc~0_9} OutVars{~t1_pc~0=v_~t1_pc~0_9} AuxVars[] AssignedVars[] 11689#L124-8 [606] L124-8-->L135-2: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 11663#L135-2 [885] L135-2-->L298-6: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_27 |v_ULTIMATE.start_is_transmit1_triggered_#res_15|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27 |v_ULTIMATE.start_is_transmit1_triggered_#res_15|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_27, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_16|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_15|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 11664#L298-6 [584] L298-6-->L298-8: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 11753#L298-8 [829] L298-8-->L263-3: Formula: (> v_~M_E~0_17 1) InVars {~M_E~0=v_~M_E~0_17} OutVars{~M_E~0=v_~M_E~0_17} AuxVars[] AssignedVars[] 11754#L263-3 [832] L263-3-->L268-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 12868#L268-3 [834] L268-3-->L273-3: Formula: (< 1 v_~E_1~0_17) InVars {~E_1~0=v_~E_1~0_17} OutVars{~E_1~0=v_~E_1~0_17} AuxVars[] AssignedVars[] 12867#L273-3 [628] L273-3-->L169-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 11718#L169-1 [838] L169-1-->L173-1: Formula: (> v_~m_st~0_8 0) InVars {~m_st~0=v_~m_st~0_8} OutVars{~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[] 11719#L173-1 [674] L173-1-->L181-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_9 1) (= v_~t1_st~0_8 0)) InVars {~t1_st~0=v_~t1_st~0_8} OutVars{~t1_st~0=v_~t1_st~0_8, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_9} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 11749#L181-1 [886] L181-1-->L413: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24} OutVars{ULTIMATE.start_start_simulation_#t~ret6=|v_ULTIMATE.start_start_simulation_#t~ret6_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret6, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_~tmp~3] 12589#L413 [842] L413-->L413-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 11700#L413-1 [659] L413-1-->L169-2: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret5=|v_ULTIMATE.start_stop_simulation_#t~ret5_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret5, ULTIMATE.start_stop_simulation_#res] 11701#L169-2 [846] L169-2-->L173-2: Formula: (< 0 v_~m_st~0_15) InVars {~m_st~0=v_~m_st~0_15} OutVars{~m_st~0=v_~m_st~0_15} AuxVars[] AssignedVars[] 11716#L173-2 [850] L173-2-->L181-2: Formula: (and (< 0 v_~t1_st~0_15) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_20 0)) InVars {~t1_st~0=v_~t1_st~0_15} OutVars{~t1_st~0=v_~t1_st~0_15, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_20} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 11734#L181-2 [888] L181-2-->L368: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_stop_simulation_#t~ret5=|v_ULTIMATE.start_stop_simulation_#t~ret5_4|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret5] 11735#L368 [691] L368-->L375: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 11762#L375 [894] L375-->L394-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 11745#L394-1 31.95/12.15 [2019-03-28 12:20:22,460 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 31.95/12.15 [2019-03-28 12:20:22,460 INFO L82 PathProgramCache]: Analyzing trace with hash 1729434388, now seen corresponding path program 1 times 31.95/12.15 [2019-03-28 12:20:22,460 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 31.95/12.15 [2019-03-28 12:20:22,460 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 31.95/12.15 [2019-03-28 12:20:22,461 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:22,461 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:22,461 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:22,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 31.95/12.15 [2019-03-28 12:20:22,473 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 31.95/12.15 [2019-03-28 12:20:22,473 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 31.95/12.15 [2019-03-28 12:20:22,473 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 31.95/12.15 [2019-03-28 12:20:22,473 INFO L799 eck$LassoCheckResult]: stem already infeasible 31.95/12.15 [2019-03-28 12:20:22,474 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 31.95/12.15 [2019-03-28 12:20:22,474 INFO L82 PathProgramCache]: Analyzing trace with hash -1447573390, now seen corresponding path program 1 times 31.95/12.15 [2019-03-28 12:20:22,474 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 31.95/12.15 [2019-03-28 12:20:22,474 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 31.95/12.15 [2019-03-28 12:20:22,475 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:22,475 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:22,475 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:22,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 31.95/12.15 [2019-03-28 12:20:22,496 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 31.95/12.15 [2019-03-28 12:20:22,496 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 31.95/12.15 [2019-03-28 12:20:22,497 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 31.95/12.15 [2019-03-28 12:20:22,497 INFO L811 eck$LassoCheckResult]: loop already infeasible 31.95/12.15 [2019-03-28 12:20:22,497 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 31.95/12.15 [2019-03-28 12:20:22,497 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 31.95/12.15 [2019-03-28 12:20:22,497 INFO L87 Difference]: Start difference. First operand 1210 states and 1866 transitions. cyclomatic complexity: 659 Second operand 3 states. 31.95/12.15 [2019-03-28 12:20:22,604 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 31.95/12.15 [2019-03-28 12:20:22,604 INFO L93 Difference]: Finished difference Result 1210 states and 1865 transitions. 31.95/12.15 [2019-03-28 12:20:22,605 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 31.95/12.15 [2019-03-28 12:20:22,605 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1210 states and 1865 transitions. 31.95/12.15 [2019-03-28 12:20:22,612 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1174 31.95/12.15 [2019-03-28 12:20:22,619 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1210 states to 1210 states and 1865 transitions. 31.95/12.15 [2019-03-28 12:20:22,619 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1210 31.95/12.15 [2019-03-28 12:20:22,620 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1210 31.95/12.15 [2019-03-28 12:20:22,620 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1210 states and 1865 transitions. 31.95/12.15 [2019-03-28 12:20:22,622 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 31.95/12.15 [2019-03-28 12:20:22,622 INFO L706 BuchiCegarLoop]: Abstraction has 1210 states and 1865 transitions. 31.95/12.15 [2019-03-28 12:20:22,623 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1210 states and 1865 transitions. 31.95/12.15 [2019-03-28 12:20:22,641 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1210 to 1210. 31.95/12.15 [2019-03-28 12:20:22,642 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1210 states. 31.95/12.15 [2019-03-28 12:20:22,645 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1210 states to 1210 states and 1865 transitions. 31.95/12.15 [2019-03-28 12:20:22,646 INFO L729 BuchiCegarLoop]: Abstraction has 1210 states and 1865 transitions. 31.95/12.15 [2019-03-28 12:20:22,646 INFO L609 BuchiCegarLoop]: Abstraction has 1210 states and 1865 transitions. 31.95/12.15 [2019-03-28 12:20:22,646 INFO L442 BuchiCegarLoop]: ======== Iteration 16============ 31.95/12.15 [2019-03-28 12:20:22,646 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1210 states and 1865 transitions. 31.95/12.15 [2019-03-28 12:20:22,652 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1174 31.95/12.15 [2019-03-28 12:20:22,652 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 31.95/12.15 [2019-03-28 12:20:22,652 INFO L119 BuchiIsEmpty]: Starting construction of run 31.95/12.15 [2019-03-28 12:20:22,653 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 31.95/12.15 [2019-03-28 12:20:22,653 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 31.95/12.15 [2019-03-28 12:20:22,654 INFO L794 eck$LassoCheckResult]: Stem: 14150#ULTIMATE.startENTRY [871] ULTIMATE.startENTRY-->L144: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~m_pc~0_16 0) (= 0 v_~m_st~0_19) (= 2 v_~E_1~0_28) (= v_~M_E~0_27 2) (= v_~T1_E~0_18 2) (= v_~t1_pc~0_16 0) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= 0 v_~t1_st~0_19)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ULTIMATE.start_start_simulation_#t~ret6=|v_ULTIMATE.start_start_simulation_#t~ret6_4|, ~t1_st~0=v_~t1_st~0_19, ~t1_pc~0=v_~t1_pc~0_16, ~M_E~0=v_~M_E~0_27, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~E_1~0=v_~E_1~0_28, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~T1_E~0=v_~T1_E~0_18, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_19, ~m_pc~0=v_~m_pc~0_16, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_start_simulation_#t~ret6, ~t1_st~0, ~t1_pc~0, ~M_E~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_~kernel_st~0, ~E_1~0, ULTIMATE.start_main_#res, ~T1_E~0, ~t1_i~0, ~m_st~0, ~m_pc~0, ULTIMATE.start_main_~__retres1~3] 14151#L144 [752] L144-->L151-1: Formula: (and (= v_~m_st~0_3 2) (< v_~m_i~0_4 1)) InVars {~m_i~0=v_~m_i~0_4} OutVars{~m_st~0=v_~m_st~0_3, ~m_i~0=v_~m_i~0_4} AuxVars[] AssignedVars[~m_st~0] 14158#L151-1 [672] L151-1-->L156-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 14726#L156-1 [757] L156-1-->L240-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 14724#L240-1 [759] L240-1-->L245-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 14722#L245-1 [760] L245-1-->L250-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 14184#L250-1 [679] L250-1-->L105: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_1|, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 14185#L105 [762] L105-->L105-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 14194#L105-2 [594] L105-2-->L116: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 14195#L116 [872] L116-->L290: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_24 |v_ULTIMATE.start_is_master_triggered_#res_13|) (= |v_ULTIMATE.start_is_master_triggered_#res_13| v_ULTIMATE.start_activate_threads_~tmp~1_24)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_24} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_24, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_24, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_13|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 14641#L290 [578] L290-->L290-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_9) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} AuxVars[] AssignedVars[] 14639#L290-2 [569] L290-2-->L124: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 14096#L124 [768] L124-->L124-2: Formula: (< v_~t1_pc~0_7 1) InVars {~t1_pc~0=v_~t1_pc~0_7} OutVars{~t1_pc~0=v_~t1_pc~0_7} AuxVars[] AssignedVars[] 14097#L124-2 [632] L124-2-->L135: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 14098#L135 [873] L135-->L298: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_24 |v_ULTIMATE.start_is_transmit1_triggered_#res_13|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25 |v_ULTIMATE.start_is_transmit1_triggered_#res_13|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_24, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_13|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 14099#L298 [611] L298-->L298-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_9) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} AuxVars[] AssignedVars[] 14160#L298-2 [774] L298-2-->L263-1: Formula: (> v_~M_E~0_14 1) InVars {~M_E~0=v_~M_E~0_14} OutVars{~M_E~0=v_~M_E~0_14} AuxVars[] AssignedVars[] 14092#L263-1 [777] L263-1-->L268-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 14093#L268-1 [778] L268-1-->L394-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 14172#L394-1 31.95/12.15 [2019-03-28 12:20:22,655 INFO L796 eck$LassoCheckResult]: Loop: 14172#L394-1 [874] L394-1-->L215: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 15101#L215 [875] L215-->L169: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_22, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 15098#L169 [781] L169-->L173: Formula: (> v_~m_st~0_9 0) InVars {~m_st~0=v_~m_st~0_9} OutVars{~m_st~0=v_~m_st~0_9} AuxVars[] AssignedVars[] 14618#L173 [784] L173-->L181: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_12 0) (> 0 v_~t1_st~0_11)) InVars {~t1_st~0=v_~t1_st~0_11} OutVars{~t1_st~0=v_~t1_st~0_11, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_12} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 15091#L181 [876] L181-->L196: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 15084#L196 [878] L196-->L240-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 15079#L240-2 [783] L240-2-->L240-4: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 15076#L240-4 [786] L240-4-->L245-3: Formula: (< 0 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 15073#L245-3 [789] L245-3-->L250-3: Formula: (> v_~E_1~0_7 0) InVars {~E_1~0=v_~E_1~0_7} OutVars{~E_1~0=v_~E_1~0_7} AuxVars[] AssignedVars[] 15070#L250-3 [676] L250-3-->L105-6: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_4, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_4|, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_2|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 15067#L105-6 [795] L105-6-->L105-8: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 14930#L105-8 [619] L105-8-->L116-2: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 15064#L116-2 [883] L116-2-->L290-6: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_27 |v_ULTIMATE.start_is_master_triggered_#res_16|) (= |v_ULTIMATE.start_is_master_triggered_#res_16| v_ULTIMATE.start_activate_threads_~tmp~1_27)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_27} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_27, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_27, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_16|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 15061#L290-6 [532] L290-6-->L290-8: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 15058#L290-8 [524] L290-8-->L124-6: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 15047#L124-6 [818] L124-6-->L124-8: Formula: (< v_~t1_pc~0_9 1) InVars {~t1_pc~0=v_~t1_pc~0_9} OutVars{~t1_pc~0=v_~t1_pc~0_9} AuxVars[] AssignedVars[] 15045#L124-8 [606] L124-8-->L135-2: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 15043#L135-2 [885] L135-2-->L298-6: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_27 |v_ULTIMATE.start_is_transmit1_triggered_#res_15|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27 |v_ULTIMATE.start_is_transmit1_triggered_#res_15|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_27, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_16|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_15|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 15041#L298-6 [584] L298-6-->L298-8: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 15039#L298-8 [829] L298-8-->L263-3: Formula: (> v_~M_E~0_17 1) InVars {~M_E~0=v_~M_E~0_17} OutVars{~M_E~0=v_~M_E~0_17} AuxVars[] AssignedVars[] 15038#L263-3 [832] L263-3-->L268-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 15029#L268-3 [834] L268-3-->L273-3: Formula: (< 1 v_~E_1~0_17) InVars {~E_1~0=v_~E_1~0_17} OutVars{~E_1~0=v_~E_1~0_17} AuxVars[] AssignedVars[] 15030#L273-3 [628] L273-3-->L169-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 15023#L169-1 [838] L169-1-->L173-1: Formula: (> v_~m_st~0_8 0) InVars {~m_st~0=v_~m_st~0_8} OutVars{~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[] 15022#L173-1 [674] L173-1-->L181-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_9 1) (= v_~t1_st~0_8 0)) InVars {~t1_st~0=v_~t1_st~0_8} OutVars{~t1_st~0=v_~t1_st~0_8, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_9} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 15021#L181-1 [886] L181-1-->L413: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24} OutVars{ULTIMATE.start_start_simulation_#t~ret6=|v_ULTIMATE.start_start_simulation_#t~ret6_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret6, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_~tmp~3] 15018#L413 [842] L413-->L413-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 15020#L413-1 [659] L413-1-->L169-2: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret5=|v_ULTIMATE.start_stop_simulation_#t~ret5_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret5, ULTIMATE.start_stop_simulation_#res] 14142#L169-2 [846] L169-2-->L173-2: Formula: (< 0 v_~m_st~0_15) InVars {~m_st~0=v_~m_st~0_15} OutVars{~m_st~0=v_~m_st~0_15} AuxVars[] AssignedVars[] 14143#L173-2 [850] L173-2-->L181-2: Formula: (and (< 0 v_~t1_st~0_15) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_20 0)) InVars {~t1_st~0=v_~t1_st~0_15} OutVars{~t1_st~0=v_~t1_st~0_15, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_20} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 15288#L181-2 [888] L181-2-->L368: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_stop_simulation_#t~ret5=|v_ULTIMATE.start_stop_simulation_#t~ret5_4|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret5] 15283#L368 [691] L368-->L375: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 15280#L375 [894] L375-->L394-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 14172#L394-1 31.95/12.15 [2019-03-28 12:20:22,655 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 31.95/12.15 [2019-03-28 12:20:22,655 INFO L82 PathProgramCache]: Analyzing trace with hash -1568460555, now seen corresponding path program 1 times 31.95/12.15 [2019-03-28 12:20:22,655 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 31.95/12.15 [2019-03-28 12:20:22,656 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 31.95/12.15 [2019-03-28 12:20:22,657 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:22,657 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:22,657 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:22,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 31.95/12.15 [2019-03-28 12:20:22,667 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 31.95/12.15 [2019-03-28 12:20:22,667 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 31.95/12.15 [2019-03-28 12:20:22,667 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 31.95/12.15 [2019-03-28 12:20:22,668 INFO L799 eck$LassoCheckResult]: stem already infeasible 31.95/12.15 [2019-03-28 12:20:22,668 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 31.95/12.15 [2019-03-28 12:20:22,668 INFO L82 PathProgramCache]: Analyzing trace with hash -1447573390, now seen corresponding path program 2 times 31.95/12.15 [2019-03-28 12:20:22,668 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 31.95/12.15 [2019-03-28 12:20:22,668 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 31.95/12.15 [2019-03-28 12:20:22,669 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:22,669 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:22,669 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.15 [2019-03-28 12:20:22,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 31.95/12.15 [2019-03-28 12:20:22,697 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. 31.95/12.15 [2019-03-28 12:20:22,697 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 31.95/12.15 [2019-03-28 12:20:22,697 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 31.95/12.15 [2019-03-28 12:20:22,698 INFO L811 eck$LassoCheckResult]: loop already infeasible 31.95/12.15 [2019-03-28 12:20:22,698 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 31.95/12.16 [2019-03-28 12:20:22,698 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 31.95/12.16 [2019-03-28 12:20:22,698 INFO L87 Difference]: Start difference. First operand 1210 states and 1865 transitions. cyclomatic complexity: 658 Second operand 3 states. 31.95/12.16 [2019-03-28 12:20:22,823 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 31.95/12.16 [2019-03-28 12:20:22,823 INFO L93 Difference]: Finished difference Result 1193 states and 1847 transitions. 31.95/12.16 [2019-03-28 12:20:22,824 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 31.95/12.16 [2019-03-28 12:20:22,824 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1193 states and 1847 transitions. 31.95/12.16 [2019-03-28 12:20:22,831 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1174 31.95/12.16 [2019-03-28 12:20:22,837 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1193 states to 1193 states and 1847 transitions. 31.95/12.16 [2019-03-28 12:20:22,838 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1193 31.95/12.16 [2019-03-28 12:20:22,839 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1193 31.95/12.16 [2019-03-28 12:20:22,839 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1193 states and 1847 transitions. 31.95/12.16 [2019-03-28 12:20:22,841 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 31.95/12.16 [2019-03-28 12:20:22,841 INFO L706 BuchiCegarLoop]: Abstraction has 1193 states and 1847 transitions. 31.95/12.16 [2019-03-28 12:20:22,842 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1193 states and 1847 transitions. 31.95/12.16 [2019-03-28 12:20:22,861 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1193 to 1193. 31.95/12.16 [2019-03-28 12:20:22,861 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1193 states. 31.95/12.16 [2019-03-28 12:20:22,864 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1193 states to 1193 states and 1847 transitions. 31.95/12.16 [2019-03-28 12:20:22,864 INFO L729 BuchiCegarLoop]: Abstraction has 1193 states and 1847 transitions. 31.95/12.16 [2019-03-28 12:20:22,864 INFO L609 BuchiCegarLoop]: Abstraction has 1193 states and 1847 transitions. 31.95/12.16 [2019-03-28 12:20:22,864 INFO L442 BuchiCegarLoop]: ======== Iteration 17============ 31.95/12.16 [2019-03-28 12:20:22,865 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1193 states and 1847 transitions. 31.95/12.16 [2019-03-28 12:20:22,870 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1174 31.95/12.16 [2019-03-28 12:20:22,870 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 31.95/12.16 [2019-03-28 12:20:22,870 INFO L119 BuchiIsEmpty]: Starting construction of run 31.95/12.16 [2019-03-28 12:20:22,872 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 31.95/12.16 [2019-03-28 12:20:22,872 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 31.95/12.16 [2019-03-28 12:20:22,873 INFO L794 eck$LassoCheckResult]: Stem: 16556#ULTIMATE.startENTRY [871] ULTIMATE.startENTRY-->L144: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~m_pc~0_16 0) (= 0 v_~m_st~0_19) (= 2 v_~E_1~0_28) (= v_~M_E~0_27 2) (= v_~T1_E~0_18 2) (= v_~t1_pc~0_16 0) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= 0 v_~t1_st~0_19)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ULTIMATE.start_start_simulation_#t~ret6=|v_ULTIMATE.start_start_simulation_#t~ret6_4|, ~t1_st~0=v_~t1_st~0_19, ~t1_pc~0=v_~t1_pc~0_16, ~M_E~0=v_~M_E~0_27, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~E_1~0=v_~E_1~0_28, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~T1_E~0=v_~T1_E~0_18, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_19, ~m_pc~0=v_~m_pc~0_16, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_start_simulation_#t~ret6, ~t1_st~0, ~t1_pc~0, ~M_E~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_~kernel_st~0, ~E_1~0, ULTIMATE.start_main_#res, ~T1_E~0, ~t1_i~0, ~m_st~0, ~m_pc~0, ULTIMATE.start_main_~__retres1~3] 16557#L144 [557] L144-->L151-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 16564#L151-1 [672] L151-1-->L156-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 16579#L156-1 [757] L156-1-->L240-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 16595#L240-1 [759] L240-1-->L245-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 16521#L245-1 [760] L245-1-->L250-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 16522#L250-1 [679] L250-1-->L105: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_1|, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 16594#L105 [762] L105-->L105-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 16606#L105-2 [594] L105-2-->L116: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 16607#L116 [872] L116-->L290: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_24 |v_ULTIMATE.start_is_master_triggered_#res_13|) (= |v_ULTIMATE.start_is_master_triggered_#res_13| v_ULTIMATE.start_activate_threads_~tmp~1_24)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_24} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_24, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_24, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_13|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 16587#L290 [578] L290-->L290-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_9) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} AuxVars[] AssignedVars[] 16576#L290-2 [569] L290-2-->L124: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 16506#L124 [768] L124-->L124-2: Formula: (< v_~t1_pc~0_7 1) InVars {~t1_pc~0=v_~t1_pc~0_7} OutVars{~t1_pc~0=v_~t1_pc~0_7} AuxVars[] AssignedVars[] 16496#L124-2 [632] L124-2-->L135: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 16497#L135 [873] L135-->L298: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_24 |v_ULTIMATE.start_is_transmit1_triggered_#res_13|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25 |v_ULTIMATE.start_is_transmit1_triggered_#res_13|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_24, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_13|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 16507#L298 [611] L298-->L298-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_9) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} AuxVars[] AssignedVars[] 16565#L298-2 [774] L298-2-->L263-1: Formula: (> v_~M_E~0_14 1) InVars {~M_E~0=v_~M_E~0_14} OutVars{~M_E~0=v_~M_E~0_14} AuxVars[] AssignedVars[] 16502#L263-1 [777] L263-1-->L268-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 16503#L268-1 [778] L268-1-->L394-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 16577#L394-1 31.95/12.16 [2019-03-28 12:20:22,874 INFO L796 eck$LassoCheckResult]: Loop: 16577#L394-1 [874] L394-1-->L215: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 17305#L215 [875] L215-->L169: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_22, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 17301#L169 [545] L169-->L181: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_8 1) (= v_~m_st~0_7 0)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 17299#L181 [876] L181-->L196: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 17296#L196 [790] L196-->L196-1: Formula: (> v_ULTIMATE.start_eval_~tmp~0_4 0) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} OutVars{ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} AuxVars[] AssignedVars[] 17290#L196-1 [622] L196-1-->L204: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_2 |v_ULTIMATE.start_eval_#t~nondet1_3|) (= 0 v_~m_st~0_10)) InVars {~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_3|} OutVars{ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_2|, ~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_1~0] 16528#L204 [796] L204-->L31: Formula: (and (> v_ULTIMATE.start_eval_~tmp_ndt_1~0_4 0) (= v_~m_st~0_11 1)) InVars {ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_4} OutVars{~m_st~0=v_~m_st~0_11, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_4} AuxVars[] AssignedVars[~m_st~0] 16529#L31 [608] L31-->L58: Formula: (= v_~m_pc~0_8 0) InVars {~m_pc~0=v_~m_pc~0_8} OutVars{~m_pc~0=v_~m_pc~0_8} AuxVars[] AssignedVars[] 17092#L58 [879] L58-->L105-3: Formula: (= 1 v_~E_1~0_29) InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_25, ~E_1~0=v_~E_1~0_29, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_25, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_25, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_14|, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_14|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_14|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ~E_1~0, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 17090#L105-3 [815] L105-3-->L105-5: Formula: (< v_~m_pc~0_13 1) InVars {~m_pc~0=v_~m_pc~0_13} OutVars{~m_pc~0=v_~m_pc~0_13} AuxVars[] AssignedVars[] 16520#L105-5 [631] L105-5-->L116-1: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_22 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_22} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 16628#L116-1 [882] L116-1-->L290-3: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_15| v_ULTIMATE.start_activate_threads_~tmp~1_26) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_26 |v_ULTIMATE.start_is_master_triggered_#res_15|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_26} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_26, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_26, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_15|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_15|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 16575#L290-3 [566] L290-3-->L290-5: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_23) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_23} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_23} AuxVars[] AssignedVars[] 16551#L290-5 [540] L290-5-->L124-3: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_19, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 16535#L124-3 [826] L124-3-->L124-5: Formula: (< v_~t1_pc~0_13 1) InVars {~t1_pc~0=v_~t1_pc~0_13} OutVars{~t1_pc~0=v_~t1_pc~0_13} AuxVars[] AssignedVars[] 16536#L124-5 [658] L124-5-->L135-1: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_23 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_23} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 17381#L135-1 [884] L135-1-->L298-3: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_26 |v_ULTIMATE.start_is_transmit1_triggered_#res_14|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_26 |v_ULTIMATE.start_is_transmit1_triggered_#res_14|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_26} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_26, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_26, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_15|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_14|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 17380#L298-3 [560] L298-3-->L298-5: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_23 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_23} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_23} AuxVars[] AssignedVars[] 17377#L298-5 [556] L298-5-->L35: Formula: (= v_~E_1~0_26 2) InVars {} OutVars{~E_1~0=v_~E_1~0_26} AuxVars[] AssignedVars[~E_1~0] 16624#L35 [880] L35-->L201: Formula: (and (= v_~m_pc~0_17 1) (= 2 v_~m_st~0_20)) InVars {} OutVars{~m_st~0=v_~m_st~0_20, ~m_pc~0=v_~m_pc~0_17} AuxVars[] AssignedVars[~m_st~0, ~m_pc~0] 16625#L201 [798] L201-->L215: Formula: (< v_~t1_st~0_5 0) InVars {~t1_st~0=v_~t1_st~0_5} OutVars{~t1_st~0=v_~t1_st~0_5} AuxVars[] AssignedVars[] 17369#L215 [875] L215-->L169: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_22, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 17366#L169 [781] L169-->L173: Formula: (> v_~m_st~0_9 0) InVars {~m_st~0=v_~m_st~0_9} OutVars{~m_st~0=v_~m_st~0_9} AuxVars[] AssignedVars[] 16850#L173 [784] L173-->L181: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_12 0) (> 0 v_~t1_st~0_11)) InVars {~t1_st~0=v_~t1_st~0_11} OutVars{~t1_st~0=v_~t1_st~0_11, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_12} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 17360#L181 [876] L181-->L196: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 17356#L196 [878] L196-->L240-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 17353#L240-2 [783] L240-2-->L240-4: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 17350#L240-4 [786] L240-4-->L245-3: Formula: (< 0 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 17347#L245-3 [789] L245-3-->L250-3: Formula: (> v_~E_1~0_7 0) InVars {~E_1~0=v_~E_1~0_7} OutVars{~E_1~0=v_~E_1~0_7} AuxVars[] AssignedVars[] 17344#L250-3 [676] L250-3-->L105-6: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_4, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_4|, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_2|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 17340#L105-6 [794] L105-6-->L105-8: Formula: (> v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 16515#L105-8 [619] L105-8-->L116-2: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 17367#L116-2 [883] L116-2-->L290-6: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_27 |v_ULTIMATE.start_is_master_triggered_#res_16|) (= |v_ULTIMATE.start_is_master_triggered_#res_16| v_ULTIMATE.start_activate_threads_~tmp~1_27)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_27} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_27, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_27, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_16|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 17364#L290-6 [532] L290-6-->L290-8: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 17361#L290-8 [524] L290-8-->L124-6: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 17358#L124-6 [818] L124-6-->L124-8: Formula: (< v_~t1_pc~0_9 1) InVars {~t1_pc~0=v_~t1_pc~0_9} OutVars{~t1_pc~0=v_~t1_pc~0_9} AuxVars[] AssignedVars[] 17321#L124-8 [606] L124-8-->L135-2: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 17351#L135-2 [885] L135-2-->L298-6: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_27 |v_ULTIMATE.start_is_transmit1_triggered_#res_15|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27 |v_ULTIMATE.start_is_transmit1_triggered_#res_15|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_27, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_16|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_15|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 17348#L298-6 [584] L298-6-->L298-8: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 17345#L298-8 [829] L298-8-->L263-3: Formula: (> v_~M_E~0_17 1) InVars {~M_E~0=v_~M_E~0_17} OutVars{~M_E~0=v_~M_E~0_17} AuxVars[] AssignedVars[] 17118#L263-3 [832] L263-3-->L268-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 17335#L268-3 [834] L268-3-->L273-3: Formula: (< 1 v_~E_1~0_17) InVars {~E_1~0=v_~E_1~0_17} OutVars{~E_1~0=v_~E_1~0_17} AuxVars[] AssignedVars[] 17334#L273-3 [628] L273-3-->L169-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 17332#L169-1 [838] L169-1-->L173-1: Formula: (> v_~m_st~0_8 0) InVars {~m_st~0=v_~m_st~0_8} OutVars{~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[] 16779#L173-1 [674] L173-1-->L181-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_9 1) (= v_~t1_st~0_8 0)) InVars {~t1_st~0=v_~t1_st~0_8} OutVars{~t1_st~0=v_~t1_st~0_8, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_9} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 17327#L181-1 [886] L181-1-->L413: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24} OutVars{ULTIMATE.start_start_simulation_#t~ret6=|v_ULTIMATE.start_start_simulation_#t~ret6_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret6, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_~tmp~3] 16867#L413 [887] L413-->L105-9: Formula: (and (= 0 v_ULTIMATE.start_start_simulation_~tmp~3_9) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_15 4) (= v_~M_E~0_28 1)) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_9} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_28, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_15, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_28, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_28, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_17|, ~M_E~0=v_~M_E~0_28, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_17|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_17|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_9} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ~M_E~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 16797#L105-9 [615] L105-9-->L106-3: Formula: (= v_~m_pc~0_6 1) InVars {~m_pc~0=v_~m_pc~0_6} OutVars{~m_pc~0=v_~m_pc~0_6} AuxVars[] AssignedVars[] 16788#L106-3 [508] L106-3-->L116-3: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_16 1) (= v_~M_E~0_19 1)) InVars {~M_E~0=v_~M_E~0_19} OutVars{~M_E~0=v_~M_E~0_19, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_16} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 16783#L116-3 [889] L116-3-->L290-9: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_29 |v_ULTIMATE.start_is_master_triggered_#res_18|) (= |v_ULTIMATE.start_is_master_triggered_#res_18| v_ULTIMATE.start_activate_threads_~tmp~1_29)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_29, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_18|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_18|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 16760#L290-9 [855] L290-9-->L290-11: Formula: (and (= v_~m_st~0_12 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_17)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_17} OutVars{~m_st~0=v_~m_st~0_12, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_17} AuxVars[] AssignedVars[~m_st~0] 16758#L290-11 [552] L290-11-->L124-9: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_13, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 16755#L124-9 [857] L124-9-->L124-11: Formula: (< v_~t1_pc~0_11 1) InVars {~t1_pc~0=v_~t1_pc~0_11} OutVars{~t1_pc~0=v_~t1_pc~0_11} AuxVars[] AssignedVars[] 16703#L124-11 [592] L124-11-->L135-3: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_17 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_17} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 16750#L135-3 [892] L135-3-->L298-9: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_28 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_29 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_28} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_28, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_29, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_18|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 16745#L298-9 [573] L298-9-->L298-11: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_20 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_20} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_20} AuxVars[] AssignedVars[] 16739#L298-11 [864] L298-11-->L331-1: Formula: (< v_~M_E~0_25 1) InVars {~M_E~0=v_~M_E~0_25} OutVars{~M_E~0=v_~M_E~0_25} AuxVars[] AssignedVars[] 16733#L331-1 [867] L331-1-->L336-1: Formula: (> v_~T1_E~0_16 1) InVars {~T1_E~0=v_~T1_E~0_16} OutVars{~T1_E~0=v_~T1_E~0_16} AuxVars[] AssignedVars[] 16728#L336-1 [869] L336-1-->L413-1: Formula: (< 1 v_~E_1~0_25) InVars {~E_1~0=v_~E_1~0_25} OutVars{~E_1~0=v_~E_1~0_25} AuxVars[] AssignedVars[] 16721#L413-1 [659] L413-1-->L169-2: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret5=|v_ULTIMATE.start_stop_simulation_#t~ret5_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret5, ULTIMATE.start_stop_simulation_#res] 16715#L169-2 [536] L169-2-->L181-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18 1) (= 0 v_~m_st~0_14)) InVars {~m_st~0=v_~m_st~0_14} OutVars{~m_st~0=v_~m_st~0_14, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 16709#L181-2 [888] L181-2-->L368: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_stop_simulation_#t~ret5=|v_ULTIMATE.start_stop_simulation_#t~ret5_4|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret5] 16706#L368 [691] L368-->L375: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 16700#L375 [894] L375-->L394-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 16697#L394-1 [874] L394-1-->L215: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 16666#L215 [875] L215-->L169: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_22, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 16690#L169 [780] L169-->L173: Formula: (< v_~m_st~0_9 0) InVars {~m_st~0=v_~m_st~0_9} OutVars{~m_st~0=v_~m_st~0_9} AuxVars[] AssignedVars[] 16691#L173 [784] L173-->L181: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_12 0) (> 0 v_~t1_st~0_11)) InVars {~t1_st~0=v_~t1_st~0_11} OutVars{~t1_st~0=v_~t1_st~0_11, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_12} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 17008#L181 [876] L181-->L196: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 16895#L196 [878] L196-->L240-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 16897#L240-2 [626] L240-2-->L240-4: Formula: (and (= v_~M_E~0_5 1) (= 0 v_~M_E~0_6)) InVars {~M_E~0=v_~M_E~0_6} OutVars{~M_E~0=v_~M_E~0_5} AuxVars[] AssignedVars[~M_E~0] 17278#L240-4 [786] L240-4-->L245-3: Formula: (< 0 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 17276#L245-3 [789] L245-3-->L250-3: Formula: (> v_~E_1~0_7 0) InVars {~E_1~0=v_~E_1~0_7} OutVars{~E_1~0=v_~E_1~0_7} AuxVars[] AssignedVars[] 17275#L250-3 [676] L250-3-->L105-6: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_4, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_4|, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_2|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 16801#L105-6 [624] L105-6-->L106-2: Formula: (= v_~m_pc~0_4 1) InVars {~m_pc~0=v_~m_pc~0_4} OutVars{~m_pc~0=v_~m_pc~0_4} AuxVars[] AssignedVars[] 16794#L106-2 [511] L106-2-->L116-2: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_10 1) (= v_~M_E~0_10 1)) InVars {~M_E~0=v_~M_E~0_10} OutVars{~M_E~0=v_~M_E~0_10, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_10} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 16786#L116-2 [883] L116-2-->L290-6: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_27 |v_ULTIMATE.start_is_master_triggered_#res_16|) (= |v_ULTIMATE.start_is_master_triggered_#res_16| v_ULTIMATE.start_activate_threads_~tmp~1_27)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_27} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_27, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_27, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_16|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 16775#L290-6 [813] L290-6-->L290-8: Formula: (and (= v_~m_st~0_5 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{~m_st~0=v_~m_st~0_5, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} AuxVars[] AssignedVars[~m_st~0] 16772#L290-8 [524] L290-8-->L124-6: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 16770#L124-6 [818] L124-6-->L124-8: Formula: (< v_~t1_pc~0_9 1) InVars {~t1_pc~0=v_~t1_pc~0_9} OutVars{~t1_pc~0=v_~t1_pc~0_9} AuxVars[] AssignedVars[] 16726#L124-8 [606] L124-8-->L135-2: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 16764#L135-2 [885] L135-2-->L298-6: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_27 |v_ULTIMATE.start_is_transmit1_triggered_#res_15|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27 |v_ULTIMATE.start_is_transmit1_triggered_#res_15|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_27, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_16|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_15|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 16759#L298-6 [584] L298-6-->L298-8: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 16756#L298-8 [828] L298-8-->L263-3: Formula: (< v_~M_E~0_17 1) InVars {~M_E~0=v_~M_E~0_17} OutVars{~M_E~0=v_~M_E~0_17} AuxVars[] AssignedVars[] 16753#L263-3 [832] L263-3-->L268-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 16751#L268-3 [834] L268-3-->L273-3: Formula: (< 1 v_~E_1~0_17) InVars {~E_1~0=v_~E_1~0_17} OutVars{~E_1~0=v_~E_1~0_17} AuxVars[] AssignedVars[] 16746#L273-3 [628] L273-3-->L169-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 16741#L169-1 [543] L169-1-->L181-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_7 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{~m_st~0=v_~m_st~0_6, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 16734#L181-1 [886] L181-1-->L413: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24} OutVars{ULTIMATE.start_start_simulation_#t~ret6=|v_ULTIMATE.start_start_simulation_#t~ret6_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret6, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_~tmp~3] 16729#L413 [887] L413-->L105-9: Formula: (and (= 0 v_ULTIMATE.start_start_simulation_~tmp~3_9) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_15 4) (= v_~M_E~0_28 1)) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_9} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_28, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_15, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_28, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_28, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_17|, ~M_E~0=v_~M_E~0_28, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_17|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_17|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_9} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ~M_E~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 16730#L105-9 [844] L105-9-->L105-11: Formula: (< v_~m_pc~0_7 1) InVars {~m_pc~0=v_~m_pc~0_7} OutVars{~m_pc~0=v_~m_pc~0_7} AuxVars[] AssignedVars[] 16771#L105-11 [563] L105-11-->L116-3: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_17 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_17} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 17300#L116-3 [889] L116-3-->L290-9: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_29 |v_ULTIMATE.start_is_master_triggered_#res_18|) (= |v_ULTIMATE.start_is_master_triggered_#res_18| v_ULTIMATE.start_activate_threads_~tmp~1_29)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_29, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_18|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_18|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 17297#L290-9 [554] L290-9-->L290-11: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_18) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_18} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_18} AuxVars[] AssignedVars[] 17293#L290-11 [552] L290-11-->L124-9: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_13, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 17191#L124-9 [857] L124-9-->L124-11: Formula: (< v_~t1_pc~0_11 1) InVars {~t1_pc~0=v_~t1_pc~0_11} OutVars{~t1_pc~0=v_~t1_pc~0_11} AuxVars[] AssignedVars[] 17189#L124-11 [592] L124-11-->L135-3: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_17 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_17} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 17187#L135-3 [892] L135-3-->L298-9: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_28 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_29 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_28} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_28, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_29, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_18|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 17186#L298-9 [573] L298-9-->L298-11: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_20 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_20} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_20} AuxVars[] AssignedVars[] 17183#L298-11 [865] L298-11-->L331-1: Formula: (> v_~M_E~0_25 1) InVars {~M_E~0=v_~M_E~0_25} OutVars{~M_E~0=v_~M_E~0_25} AuxVars[] AssignedVars[] 17184#L331-1 [867] L331-1-->L336-1: Formula: (> v_~T1_E~0_16 1) InVars {~T1_E~0=v_~T1_E~0_16} OutVars{~T1_E~0=v_~T1_E~0_16} AuxVars[] AssignedVars[] 17343#L336-1 [869] L336-1-->L413-1: Formula: (< 1 v_~E_1~0_25) InVars {~E_1~0=v_~E_1~0_25} OutVars{~E_1~0=v_~E_1~0_25} AuxVars[] AssignedVars[] 17339#L413-1 [659] L413-1-->L169-2: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret5=|v_ULTIMATE.start_stop_simulation_#t~ret5_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret5, ULTIMATE.start_stop_simulation_#res] 17315#L169-2 [536] L169-2-->L181-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18 1) (= 0 v_~m_st~0_14)) InVars {~m_st~0=v_~m_st~0_14} OutVars{~m_st~0=v_~m_st~0_14, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 17314#L181-2 [888] L181-2-->L368: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_stop_simulation_#t~ret5=|v_ULTIMATE.start_stop_simulation_#t~ret5_4|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret5] 17312#L368 [691] L368-->L375: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 17309#L375 [894] L375-->L394-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 16577#L394-1 31.95/12.16 [2019-03-28 12:20:22,875 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 31.95/12.16 [2019-03-28 12:20:22,875 INFO L82 PathProgramCache]: Analyzing trace with hash -412880040, now seen corresponding path program 4 times 31.95/12.16 [2019-03-28 12:20:22,875 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 31.95/12.16 [2019-03-28 12:20:22,875 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 31.95/12.16 [2019-03-28 12:20:22,876 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.16 [2019-03-28 12:20:22,876 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 31.95/12.16 [2019-03-28 12:20:22,876 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.16 [2019-03-28 12:20:22,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 31.95/12.16 [2019-03-28 12:20:22,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 31.95/12.16 [2019-03-28 12:20:22,886 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 31.95/12.16 [2019-03-28 12:20:22,887 INFO L82 PathProgramCache]: Analyzing trace with hash 444068865, now seen corresponding path program 1 times 31.95/12.16 [2019-03-28 12:20:22,887 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 31.95/12.16 [2019-03-28 12:20:22,887 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 31.95/12.16 [2019-03-28 12:20:22,888 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.16 [2019-03-28 12:20:22,888 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 31.95/12.16 [2019-03-28 12:20:22,888 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.16 [2019-03-28 12:20:22,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 31.95/12.16 [2019-03-28 12:20:22,921 INFO L134 CoverageAnalysis]: Checked inductivity of 49 backedges. 19 proven. 0 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. 31.95/12.16 [2019-03-28 12:20:22,921 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 31.95/12.16 [2019-03-28 12:20:22,921 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 31.95/12.16 [2019-03-28 12:20:22,922 INFO L811 eck$LassoCheckResult]: loop already infeasible 31.95/12.16 [2019-03-28 12:20:22,922 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 31.95/12.16 [2019-03-28 12:20:22,922 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 31.95/12.16 [2019-03-28 12:20:22,922 INFO L87 Difference]: Start difference. First operand 1193 states and 1847 transitions. cyclomatic complexity: 657 Second operand 3 states. 31.95/12.16 [2019-03-28 12:20:23,020 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 31.95/12.16 [2019-03-28 12:20:23,020 INFO L93 Difference]: Finished difference Result 1177 states and 1799 transitions. 31.95/12.16 [2019-03-28 12:20:23,021 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 31.95/12.16 [2019-03-28 12:20:23,021 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1177 states and 1799 transitions. 31.95/12.16 [2019-03-28 12:20:23,028 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1158 31.95/12.16 [2019-03-28 12:20:23,035 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1177 states to 1177 states and 1799 transitions. 31.95/12.16 [2019-03-28 12:20:23,035 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1177 31.95/12.16 [2019-03-28 12:20:23,036 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1177 31.95/12.16 [2019-03-28 12:20:23,036 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1177 states and 1799 transitions. 31.95/12.16 [2019-03-28 12:20:23,038 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 31.95/12.16 [2019-03-28 12:20:23,039 INFO L706 BuchiCegarLoop]: Abstraction has 1177 states and 1799 transitions. 31.95/12.16 [2019-03-28 12:20:23,039 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1177 states and 1799 transitions. 31.95/12.16 [2019-03-28 12:20:23,057 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1177 to 1177. 31.95/12.16 [2019-03-28 12:20:23,058 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1177 states. 31.95/12.16 [2019-03-28 12:20:23,061 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1177 states to 1177 states and 1799 transitions. 31.95/12.16 [2019-03-28 12:20:23,061 INFO L729 BuchiCegarLoop]: Abstraction has 1177 states and 1799 transitions. 31.95/12.16 [2019-03-28 12:20:23,061 INFO L609 BuchiCegarLoop]: Abstraction has 1177 states and 1799 transitions. 31.95/12.16 [2019-03-28 12:20:23,061 INFO L442 BuchiCegarLoop]: ======== Iteration 18============ 31.95/12.16 [2019-03-28 12:20:23,061 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1177 states and 1799 transitions. 31.95/12.16 [2019-03-28 12:20:23,065 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1158 31.95/12.16 [2019-03-28 12:20:23,065 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 31.95/12.16 [2019-03-28 12:20:23,065 INFO L119 BuchiIsEmpty]: Starting construction of run 31.95/12.16 [2019-03-28 12:20:23,067 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 31.95/12.16 [2019-03-28 12:20:23,067 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 31.95/12.16 [2019-03-28 12:20:23,067 INFO L794 eck$LassoCheckResult]: Stem: 18931#ULTIMATE.startENTRY [871] ULTIMATE.startENTRY-->L144: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~m_pc~0_16 0) (= 0 v_~m_st~0_19) (= 2 v_~E_1~0_28) (= v_~M_E~0_27 2) (= v_~T1_E~0_18 2) (= v_~t1_pc~0_16 0) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= 0 v_~t1_st~0_19)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ULTIMATE.start_start_simulation_#t~ret6=|v_ULTIMATE.start_start_simulation_#t~ret6_4|, ~t1_st~0=v_~t1_st~0_19, ~t1_pc~0=v_~t1_pc~0_16, ~M_E~0=v_~M_E~0_27, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~E_1~0=v_~E_1~0_28, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~T1_E~0=v_~T1_E~0_18, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_19, ~m_pc~0=v_~m_pc~0_16, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_start_simulation_#t~ret6, ~t1_st~0, ~t1_pc~0, ~M_E~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_~kernel_st~0, ~E_1~0, ULTIMATE.start_main_#res, ~T1_E~0, ~t1_i~0, ~m_st~0, ~m_pc~0, ULTIMATE.start_main_~__retres1~3] 18932#L144 [557] L144-->L151-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 18938#L151-1 [672] L151-1-->L156-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 18952#L156-1 [757] L156-1-->L240-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 18963#L240-1 [759] L240-1-->L245-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 18895#L245-1 [760] L245-1-->L250-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 18896#L250-1 [679] L250-1-->L105: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_1|, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 18962#L105 [762] L105-->L105-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 18972#L105-2 [594] L105-2-->L116: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 18973#L116 [872] L116-->L290: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_24 |v_ULTIMATE.start_is_master_triggered_#res_13|) (= |v_ULTIMATE.start_is_master_triggered_#res_13| v_ULTIMATE.start_activate_threads_~tmp~1_24)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_24} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_24, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_24, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_13|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 18959#L290 [578] L290-->L290-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_9) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} AuxVars[] AssignedVars[] 18950#L290-2 [569] L290-2-->L124: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 18882#L124 [768] L124-->L124-2: Formula: (< v_~t1_pc~0_7 1) InVars {~t1_pc~0=v_~t1_pc~0_7} OutVars{~t1_pc~0=v_~t1_pc~0_7} AuxVars[] AssignedVars[] 18874#L124-2 [632] L124-2-->L135: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 18875#L135 [873] L135-->L298: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_24 |v_ULTIMATE.start_is_transmit1_triggered_#res_13|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25 |v_ULTIMATE.start_is_transmit1_triggered_#res_13|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_24, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_13|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 18887#L298 [611] L298-->L298-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_9) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} AuxVars[] AssignedVars[] 18940#L298-2 [774] L298-2-->L263-1: Formula: (> v_~M_E~0_14 1) InVars {~M_E~0=v_~M_E~0_14} OutVars{~M_E~0=v_~M_E~0_14} AuxVars[] AssignedVars[] 18880#L263-1 [777] L263-1-->L268-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 18881#L268-1 [778] L268-1-->L394-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 18951#L394-1 31.95/12.16 [2019-03-28 12:20:23,069 INFO L796 eck$LassoCheckResult]: Loop: 18951#L394-1 [874] L394-1-->L215: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 19072#L215 [875] L215-->L169: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_22, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 19049#L169 [545] L169-->L181: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_8 1) (= v_~m_st~0_7 0)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 19040#L181 [876] L181-->L196: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 19035#L196 [790] L196-->L196-1: Formula: (> v_ULTIMATE.start_eval_~tmp~0_4 0) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} OutVars{ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} AuxVars[] AssignedVars[] 19027#L196-1 [622] L196-1-->L204: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_2 |v_ULTIMATE.start_eval_#t~nondet1_3|) (= 0 v_~m_st~0_10)) InVars {~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_3|} OutVars{ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_2|, ~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_1~0] 18902#L204 [796] L204-->L31: Formula: (and (> v_ULTIMATE.start_eval_~tmp_ndt_1~0_4 0) (= v_~m_st~0_11 1)) InVars {ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_4} OutVars{~m_st~0=v_~m_st~0_11, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_4} AuxVars[] AssignedVars[~m_st~0] 18903#L31 [608] L31-->L58: Formula: (= v_~m_pc~0_8 0) InVars {~m_pc~0=v_~m_pc~0_8} OutVars{~m_pc~0=v_~m_pc~0_8} AuxVars[] AssignedVars[] 18872#L58 [879] L58-->L105-3: Formula: (= 1 v_~E_1~0_29) InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_25, ~E_1~0=v_~E_1~0_29, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_25, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_25, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_14|, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_14|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_14|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ~E_1~0, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 18873#L105-3 [815] L105-3-->L105-5: Formula: (< v_~m_pc~0_13 1) InVars {~m_pc~0=v_~m_pc~0_13} OutVars{~m_pc~0=v_~m_pc~0_13} AuxVars[] AssignedVars[] 19552#L105-5 [631] L105-5-->L116-1: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_22 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_22} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 19549#L116-1 [882] L116-1-->L290-3: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_15| v_ULTIMATE.start_activate_threads_~tmp~1_26) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_26 |v_ULTIMATE.start_is_master_triggered_#res_15|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_26} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_26, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_26, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_15|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_15|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 19547#L290-3 [566] L290-3-->L290-5: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_23) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_23} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_23} AuxVars[] AssignedVars[] 19545#L290-5 [540] L290-5-->L124-3: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_19, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 19543#L124-3 [826] L124-3-->L124-5: Formula: (< v_~t1_pc~0_13 1) InVars {~t1_pc~0=v_~t1_pc~0_13} OutVars{~t1_pc~0=v_~t1_pc~0_13} AuxVars[] AssignedVars[] 18990#L124-5 [658] L124-5-->L135-1: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_23 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_23} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 19542#L135-1 [884] L135-1-->L298-3: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_26 |v_ULTIMATE.start_is_transmit1_triggered_#res_14|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_26 |v_ULTIMATE.start_is_transmit1_triggered_#res_14|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_26} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_26, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_26, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_15|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_14|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 19541#L298-3 [560] L298-3-->L298-5: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_23 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_23} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_23} AuxVars[] AssignedVars[] 18936#L298-5 [556] L298-5-->L35: Formula: (= v_~E_1~0_26 2) InVars {} OutVars{~E_1~0=v_~E_1~0_26} AuxVars[] AssignedVars[~E_1~0] 18937#L35 [880] L35-->L201: Formula: (and (= v_~m_pc~0_17 1) (= 2 v_~m_st~0_20)) InVars {} OutVars{~m_st~0=v_~m_st~0_20, ~m_pc~0=v_~m_pc~0_17} AuxVars[] AssignedVars[~m_st~0, ~m_pc~0] 18985#L201 [798] L201-->L215: Formula: (< v_~t1_st~0_5 0) InVars {~t1_st~0=v_~t1_st~0_5} OutVars{~t1_st~0=v_~t1_st~0_5} AuxVars[] AssignedVars[] 19569#L215 [875] L215-->L169: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_22, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 19701#L169 [781] L169-->L173: Formula: (> v_~m_st~0_9 0) InVars {~m_st~0=v_~m_st~0_9} OutVars{~m_st~0=v_~m_st~0_9} AuxVars[] AssignedVars[] 19044#L173 [784] L173-->L181: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_12 0) (> 0 v_~t1_st~0_11)) InVars {~t1_st~0=v_~t1_st~0_11} OutVars{~t1_st~0=v_~t1_st~0_11, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_12} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 19694#L181 [876] L181-->L196: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 19691#L196 [878] L196-->L240-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 19687#L240-2 [783] L240-2-->L240-4: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 19685#L240-4 [786] L240-4-->L245-3: Formula: (< 0 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 19681#L245-3 [789] L245-3-->L250-3: Formula: (> v_~E_1~0_7 0) InVars {~E_1~0=v_~E_1~0_7} OutVars{~E_1~0=v_~E_1~0_7} AuxVars[] AssignedVars[] 19678#L250-3 [676] L250-3-->L105-6: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_4, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_4|, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_2|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 19672#L105-6 [624] L105-6-->L106-2: Formula: (= v_~m_pc~0_4 1) InVars {~m_pc~0=v_~m_pc~0_4} OutVars{~m_pc~0=v_~m_pc~0_4} AuxVars[] AssignedVars[] 18890#L106-2 [800] L106-2-->L105-8: Formula: (> v_~M_E~0_11 1) InVars {~M_E~0=v_~M_E~0_11} OutVars{~M_E~0=v_~M_E~0_11} AuxVars[] AssignedVars[] 18891#L105-8 [619] L105-8-->L116-2: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 19761#L116-2 [883] L116-2-->L290-6: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_27 |v_ULTIMATE.start_is_master_triggered_#res_16|) (= |v_ULTIMATE.start_is_master_triggered_#res_16| v_ULTIMATE.start_activate_threads_~tmp~1_27)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_27} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_27, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_27, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_16|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 19760#L290-6 [532] L290-6-->L290-8: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 19758#L290-8 [524] L290-8-->L124-6: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 19756#L124-6 [818] L124-6-->L124-8: Formula: (< v_~t1_pc~0_9 1) InVars {~t1_pc~0=v_~t1_pc~0_9} OutVars{~t1_pc~0=v_~t1_pc~0_9} AuxVars[] AssignedVars[] 19495#L124-8 [606] L124-8-->L135-2: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 19753#L135-2 [885] L135-2-->L298-6: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_27 |v_ULTIMATE.start_is_transmit1_triggered_#res_15|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27 |v_ULTIMATE.start_is_transmit1_triggered_#res_15|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_27, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_16|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_15|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 19752#L298-6 [584] L298-6-->L298-8: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 19749#L298-8 [829] L298-8-->L263-3: Formula: (> v_~M_E~0_17 1) InVars {~M_E~0=v_~M_E~0_17} OutVars{~M_E~0=v_~M_E~0_17} AuxVars[] AssignedVars[] 19730#L263-3 [832] L263-3-->L268-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 19747#L268-3 [834] L268-3-->L273-3: Formula: (< 1 v_~E_1~0_17) InVars {~E_1~0=v_~E_1~0_17} OutVars{~E_1~0=v_~E_1~0_17} AuxVars[] AssignedVars[] 19746#L273-3 [628] L273-3-->L169-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 19744#L169-1 [838] L169-1-->L173-1: Formula: (> v_~m_st~0_8 0) InVars {~m_st~0=v_~m_st~0_8} OutVars{~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[] 19094#L173-1 [674] L173-1-->L181-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_9 1) (= v_~t1_st~0_8 0)) InVars {~t1_st~0=v_~t1_st~0_8} OutVars{~t1_st~0=v_~t1_st~0_8, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_9} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 19718#L181-1 [886] L181-1-->L413: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24} OutVars{ULTIMATE.start_start_simulation_#t~ret6=|v_ULTIMATE.start_start_simulation_#t~ret6_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret6, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_~tmp~3] 19717#L413 [887] L413-->L105-9: Formula: (and (= 0 v_ULTIMATE.start_start_simulation_~tmp~3_9) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_15 4) (= v_~M_E~0_28 1)) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_9} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_28, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_15, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_28, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_28, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_17|, ~M_E~0=v_~M_E~0_28, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_17|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_17|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_9} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ~M_E~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 19633#L105-9 [615] L105-9-->L106-3: Formula: (= v_~m_pc~0_6 1) InVars {~m_pc~0=v_~m_pc~0_6} OutVars{~m_pc~0=v_~m_pc~0_6} AuxVars[] AssignedVars[] 18883#L106-3 [508] L106-3-->L116-3: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_16 1) (= v_~M_E~0_19 1)) InVars {~M_E~0=v_~M_E~0_19} OutVars{~M_E~0=v_~M_E~0_19, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_16} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 18886#L116-3 [889] L116-3-->L290-9: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_29 |v_ULTIMATE.start_is_master_triggered_#res_18|) (= |v_ULTIMATE.start_is_master_triggered_#res_18| v_ULTIMATE.start_activate_threads_~tmp~1_29)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_29, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_18|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_18|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 19205#L290-9 [855] L290-9-->L290-11: Formula: (and (= v_~m_st~0_12 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_17)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_17} OutVars{~m_st~0=v_~m_st~0_12, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_17} AuxVars[] AssignedVars[~m_st~0] 19204#L290-11 [552] L290-11-->L124-9: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_13, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 19105#L124-9 [857] L124-9-->L124-11: Formula: (< v_~t1_pc~0_11 1) InVars {~t1_pc~0=v_~t1_pc~0_11} OutVars{~t1_pc~0=v_~t1_pc~0_11} AuxVars[] AssignedVars[] 19103#L124-11 [592] L124-11-->L135-3: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_17 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_17} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 19101#L135-3 [892] L135-3-->L298-9: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_28 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_29 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_28} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_28, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_29, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_18|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 19099#L298-9 [573] L298-9-->L298-11: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_20 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_20} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_20} AuxVars[] AssignedVars[] 19096#L298-11 [864] L298-11-->L331-1: Formula: (< v_~M_E~0_25 1) InVars {~M_E~0=v_~M_E~0_25} OutVars{~M_E~0=v_~M_E~0_25} AuxVars[] AssignedVars[] 19097#L331-1 [867] L331-1-->L336-1: Formula: (> v_~T1_E~0_16 1) InVars {~T1_E~0=v_~T1_E~0_16} OutVars{~T1_E~0=v_~T1_E~0_16} AuxVars[] AssignedVars[] 19304#L336-1 [869] L336-1-->L413-1: Formula: (< 1 v_~E_1~0_25) InVars {~E_1~0=v_~E_1~0_25} OutVars{~E_1~0=v_~E_1~0_25} AuxVars[] AssignedVars[] 19303#L413-1 [659] L413-1-->L169-2: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret5=|v_ULTIMATE.start_stop_simulation_#t~ret5_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret5, ULTIMATE.start_stop_simulation_#res] 19300#L169-2 [536] L169-2-->L181-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18 1) (= 0 v_~m_st~0_14)) InVars {~m_st~0=v_~m_st~0_14} OutVars{~m_st~0=v_~m_st~0_14, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 19299#L181-2 [888] L181-2-->L368: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_stop_simulation_#t~ret5=|v_ULTIMATE.start_stop_simulation_#t~ret5_4|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret5] 19298#L368 [691] L368-->L375: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 19297#L375 [894] L375-->L394-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 19296#L394-1 [874] L394-1-->L215: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 19284#L215 [875] L215-->L169: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_22, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 19293#L169 [780] L169-->L173: Formula: (< v_~m_st~0_9 0) InVars {~m_st~0=v_~m_st~0_9} OutVars{~m_st~0=v_~m_st~0_9} AuxVars[] AssignedVars[] 19294#L173 [784] L173-->L181: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_12 0) (> 0 v_~t1_st~0_11)) InVars {~t1_st~0=v_~t1_st~0_11} OutVars{~t1_st~0=v_~t1_st~0_11, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_12} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 19566#L181 [876] L181-->L196: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 19567#L196 [878] L196-->L240-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 19666#L240-2 [626] L240-2-->L240-4: Formula: (and (= v_~M_E~0_5 1) (= 0 v_~M_E~0_6)) InVars {~M_E~0=v_~M_E~0_6} OutVars{~M_E~0=v_~M_E~0_5} AuxVars[] AssignedVars[~M_E~0] 19663#L240-4 [786] L240-4-->L245-3: Formula: (< 0 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 19661#L245-3 [789] L245-3-->L250-3: Formula: (> v_~E_1~0_7 0) InVars {~E_1~0=v_~E_1~0_7} OutVars{~E_1~0=v_~E_1~0_7} AuxVars[] AssignedVars[] 19658#L250-3 [676] L250-3-->L105-6: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_4, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_4|, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_2|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 19654#L105-6 [624] L105-6-->L106-2: Formula: (= v_~m_pc~0_4 1) InVars {~m_pc~0=v_~m_pc~0_4} OutVars{~m_pc~0=v_~m_pc~0_4} AuxVars[] AssignedVars[] 19650#L106-2 [511] L106-2-->L116-2: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_10 1) (= v_~M_E~0_10 1)) InVars {~M_E~0=v_~M_E~0_10} OutVars{~M_E~0=v_~M_E~0_10, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_10} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 19600#L116-2 [883] L116-2-->L290-6: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_27 |v_ULTIMATE.start_is_master_triggered_#res_16|) (= |v_ULTIMATE.start_is_master_triggered_#res_16| v_ULTIMATE.start_activate_threads_~tmp~1_27)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_27} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_27, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_27, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_16|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 19601#L290-6 [813] L290-6-->L290-8: Formula: (and (= v_~m_st~0_5 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{~m_st~0=v_~m_st~0_5, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} AuxVars[] AssignedVars[~m_st~0] 19317#L290-8 [524] L290-8-->L124-6: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 19316#L124-6 [818] L124-6-->L124-8: Formula: (< v_~t1_pc~0_9 1) InVars {~t1_pc~0=v_~t1_pc~0_9} OutVars{~t1_pc~0=v_~t1_pc~0_9} AuxVars[] AssignedVars[] 19157#L124-8 [606] L124-8-->L135-2: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 19315#L135-2 [885] L135-2-->L298-6: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_27 |v_ULTIMATE.start_is_transmit1_triggered_#res_15|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27 |v_ULTIMATE.start_is_transmit1_triggered_#res_15|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_27, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_16|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_15|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 19314#L298-6 [584] L298-6-->L298-8: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 19313#L298-8 [828] L298-8-->L263-3: Formula: (< v_~M_E~0_17 1) InVars {~M_E~0=v_~M_E~0_17} OutVars{~M_E~0=v_~M_E~0_17} AuxVars[] AssignedVars[] 19312#L263-3 [832] L263-3-->L268-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 19311#L268-3 [834] L268-3-->L273-3: Formula: (< 1 v_~E_1~0_17) InVars {~E_1~0=v_~E_1~0_17} OutVars{~E_1~0=v_~E_1~0_17} AuxVars[] AssignedVars[] 19310#L273-3 [628] L273-3-->L169-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 19307#L169-1 [543] L169-1-->L181-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_7 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{~m_st~0=v_~m_st~0_6, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 19306#L181-1 [886] L181-1-->L413: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24} OutVars{ULTIMATE.start_start_simulation_#t~ret6=|v_ULTIMATE.start_start_simulation_#t~ret6_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret6, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_~tmp~3] 19305#L413 [887] L413-->L105-9: Formula: (and (= 0 v_ULTIMATE.start_start_simulation_~tmp~3_9) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_15 4) (= v_~M_E~0_28 1)) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_9} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_28, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_15, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_28, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_28, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_17|, ~M_E~0=v_~M_E~0_28, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_17|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_17|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_9} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ~M_E~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 19090#L105-9 [844] L105-9-->L105-11: Formula: (< v_~m_pc~0_7 1) InVars {~m_pc~0=v_~m_pc~0_7} OutVars{~m_pc~0=v_~m_pc~0_7} AuxVars[] AssignedVars[] 19213#L105-11 [563] L105-11-->L116-3: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_17 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_17} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 19588#L116-3 [889] L116-3-->L290-9: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_29 |v_ULTIMATE.start_is_master_triggered_#res_18|) (= |v_ULTIMATE.start_is_master_triggered_#res_18| v_ULTIMATE.start_activate_threads_~tmp~1_29)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_29, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_18|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_18|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 19584#L290-9 [554] L290-9-->L290-11: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_18) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_18} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_18} AuxVars[] AssignedVars[] 19582#L290-11 [552] L290-11-->L124-9: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_13, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 19580#L124-9 [857] L124-9-->L124-11: Formula: (< v_~t1_pc~0_11 1) InVars {~t1_pc~0=v_~t1_pc~0_11} OutVars{~t1_pc~0=v_~t1_pc~0_11} AuxVars[] AssignedVars[] 19230#L124-11 [592] L124-11-->L135-3: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_17 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_17} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 19574#L135-3 [892] L135-3-->L298-9: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_28 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_29 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_28} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_28, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_29, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_18|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 19570#L298-9 [573] L298-9-->L298-11: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_20 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_20} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_20} AuxVars[] AssignedVars[] 19563#L298-11 [865] L298-11-->L331-1: Formula: (> v_~M_E~0_25 1) InVars {~M_E~0=v_~M_E~0_25} OutVars{~M_E~0=v_~M_E~0_25} AuxVars[] AssignedVars[] 19562#L331-1 [867] L331-1-->L336-1: Formula: (> v_~T1_E~0_16 1) InVars {~T1_E~0=v_~T1_E~0_16} OutVars{~T1_E~0=v_~T1_E~0_16} AuxVars[] AssignedVars[] 19554#L336-1 [869] L336-1-->L413-1: Formula: (< 1 v_~E_1~0_25) InVars {~E_1~0=v_~E_1~0_25} OutVars{~E_1~0=v_~E_1~0_25} AuxVars[] AssignedVars[] 19553#L413-1 [659] L413-1-->L169-2: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret5=|v_ULTIMATE.start_stop_simulation_#t~ret5_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret5, ULTIMATE.start_stop_simulation_#res] 19550#L169-2 [536] L169-2-->L181-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18 1) (= 0 v_~m_st~0_14)) InVars {~m_st~0=v_~m_st~0_14} OutVars{~m_st~0=v_~m_st~0_14, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 19548#L181-2 [888] L181-2-->L368: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_stop_simulation_#t~ret5=|v_ULTIMATE.start_stop_simulation_#t~ret5_4|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret5] 19546#L368 [691] L368-->L375: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 19544#L375 [894] L375-->L394-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 18951#L394-1 31.95/12.16 [2019-03-28 12:20:23,070 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 31.95/12.16 [2019-03-28 12:20:23,070 INFO L82 PathProgramCache]: Analyzing trace with hash -412880040, now seen corresponding path program 5 times 31.95/12.16 [2019-03-28 12:20:23,070 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 31.95/12.16 [2019-03-28 12:20:23,070 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 31.95/12.16 [2019-03-28 12:20:23,071 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.16 [2019-03-28 12:20:23,071 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 31.95/12.16 [2019-03-28 12:20:23,071 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.16 [2019-03-28 12:20:23,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 31.95/12.16 [2019-03-28 12:20:23,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 31.95/12.16 [2019-03-28 12:20:23,081 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 31.95/12.16 [2019-03-28 12:20:23,081 INFO L82 PathProgramCache]: Analyzing trace with hash 82361315, now seen corresponding path program 1 times 31.95/12.16 [2019-03-28 12:20:23,081 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 31.95/12.16 [2019-03-28 12:20:23,081 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 31.95/12.16 [2019-03-28 12:20:23,082 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.16 [2019-03-28 12:20:23,082 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 31.95/12.16 [2019-03-28 12:20:23,082 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 31.95/12.16 [2019-03-28 12:20:23,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 31.95/12.16 [2019-03-28 12:20:23,118 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 32 proven. 0 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. 31.95/12.16 [2019-03-28 12:20:23,119 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 31.95/12.16 [2019-03-28 12:20:23,119 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 31.95/12.16 [2019-03-28 12:20:23,119 INFO L811 eck$LassoCheckResult]: loop already infeasible 31.95/12.16 [2019-03-28 12:20:23,120 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 31.95/12.16 [2019-03-28 12:20:23,120 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 31.95/12.16 [2019-03-28 12:20:23,120 INFO L87 Difference]: Start difference. First operand 1177 states and 1799 transitions. cyclomatic complexity: 625 Second operand 3 states. 31.95/12.16 [2019-03-28 12:20:23,300 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 31.95/12.16 [2019-03-28 12:20:23,300 INFO L93 Difference]: Finished difference Result 2219 states and 3207 transitions. 31.95/12.16 [2019-03-28 12:20:23,300 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 31.95/12.16 [2019-03-28 12:20:23,301 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2219 states and 3207 transitions. 31.95/12.16 [2019-03-28 12:20:23,310 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2200 31.95/12.16 [2019-03-28 12:20:23,322 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2219 states to 2219 states and 3207 transitions. 31.95/12.16 [2019-03-28 12:20:23,322 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2219 31.95/12.16 [2019-03-28 12:20:23,324 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2219 31.95/12.16 [2019-03-28 12:20:23,324 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2219 states and 3207 transitions. 31.95/12.16 [2019-03-28 12:20:23,328 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 31.95/12.16 [2019-03-28 12:20:23,328 INFO L706 BuchiCegarLoop]: Abstraction has 2219 states and 3207 transitions. 31.95/12.16 [2019-03-28 12:20:23,329 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2219 states and 3207 transitions. 31.95/12.16 [2019-03-28 12:20:23,364 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2219 to 2219. 31.95/12.16 [2019-03-28 12:20:23,364 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2219 states. 31.95/12.16 [2019-03-28 12:20:23,370 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2219 states to 2219 states and 3207 transitions. 31.95/12.16 [2019-03-28 12:20:23,370 INFO L729 BuchiCegarLoop]: Abstraction has 2219 states and 3207 transitions. 31.95/12.16 [2019-03-28 12:20:23,370 INFO L609 BuchiCegarLoop]: Abstraction has 2219 states and 3207 transitions. 31.95/12.16 [2019-03-28 12:20:23,370 INFO L442 BuchiCegarLoop]: ======== Iteration 19============ 31.95/12.16 [2019-03-28 12:20:23,371 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2219 states and 3207 transitions. 31.95/12.16 [2019-03-28 12:20:23,376 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2200 31.95/12.16 [2019-03-28 12:20:23,377 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 31.95/12.16 [2019-03-28 12:20:23,377 INFO L119 BuchiIsEmpty]: Starting construction of run 31.95/12.16 [2019-03-28 12:20:23,378 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 31.95/12.16 [2019-03-28 12:20:23,379 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 31.95/12.16 [2019-03-28 12:20:23,379 INFO L794 eck$LassoCheckResult]: Stem: 22335#ULTIMATE.startENTRY [871] ULTIMATE.startENTRY-->L144: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~m_pc~0_16 0) (= 0 v_~m_st~0_19) (= 2 v_~E_1~0_28) (= v_~M_E~0_27 2) (= v_~T1_E~0_18 2) (= v_~t1_pc~0_16 0) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= 0 v_~t1_st~0_19)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ULTIMATE.start_start_simulation_#t~ret6=|v_ULTIMATE.start_start_simulation_#t~ret6_4|, ~t1_st~0=v_~t1_st~0_19, ~t1_pc~0=v_~t1_pc~0_16, ~M_E~0=v_~M_E~0_27, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~E_1~0=v_~E_1~0_28, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~T1_E~0=v_~T1_E~0_18, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_19, ~m_pc~0=v_~m_pc~0_16, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_start_simulation_#t~ret6, ~t1_st~0, ~t1_pc~0, ~M_E~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_~kernel_st~0, ~E_1~0, ULTIMATE.start_main_#res, ~T1_E~0, ~t1_i~0, ~m_st~0, ~m_pc~0, ULTIMATE.start_main_~__retres1~3] 22336#L144 [557] L144-->L151-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 22343#L151-1 [672] L151-1-->L156-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 22359#L156-1 [757] L156-1-->L240-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 22373#L240-1 [759] L240-1-->L245-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 22296#L245-1 [760] L245-1-->L250-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 22297#L250-1 [679] L250-1-->L105: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_1|, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 22372#L105 [762] L105-->L105-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 22384#L105-2 [594] L105-2-->L116: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 22385#L116 [872] L116-->L290: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_24 |v_ULTIMATE.start_is_master_triggered_#res_13|) (= |v_ULTIMATE.start_is_master_triggered_#res_13| v_ULTIMATE.start_activate_threads_~tmp~1_24)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_24} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_24, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_24, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_13|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 22369#L290 [578] L290-->L290-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_9) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} AuxVars[] AssignedVars[] 22355#L290-2 [569] L290-2-->L124: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 22284#L124 [768] L124-->L124-2: Formula: (< v_~t1_pc~0_7 1) InVars {~t1_pc~0=v_~t1_pc~0_7} OutVars{~t1_pc~0=v_~t1_pc~0_7} AuxVars[] AssignedVars[] 22276#L124-2 [632] L124-2-->L135: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 22277#L135 [873] L135-->L298: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_24 |v_ULTIMATE.start_is_transmit1_triggered_#res_13|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25 |v_ULTIMATE.start_is_transmit1_triggered_#res_13|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_24, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_13|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 22289#L298 [611] L298-->L298-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_9) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} AuxVars[] AssignedVars[] 22344#L298-2 [774] L298-2-->L263-1: Formula: (> v_~M_E~0_14 1) InVars {~M_E~0=v_~M_E~0_14} OutVars{~M_E~0=v_~M_E~0_14} AuxVars[] AssignedVars[] 22282#L263-1 [777] L263-1-->L268-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 22283#L268-1 [778] L268-1-->L394-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 22358#L394-1 31.95/12.16 [2019-03-28 12:20:23,381 INFO L796 eck$LassoCheckResult]: Loop: 22358#L394-1 [874] L394-1-->L215: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 22480#L215 [875] L215-->L169: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_22, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 22481#L169 [545] L169-->L181: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_8 1) (= v_~m_st~0_7 0)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 22530#L181 [876] L181-->L196: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 23293#L196 [790] L196-->L196-1: Formula: (> v_ULTIMATE.start_eval_~tmp~0_4 0) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} OutVars{ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} AuxVars[] AssignedVars[] 23289#L196-1 [622] L196-1-->L204: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_2 |v_ULTIMATE.start_eval_#t~nondet1_3|) (= 0 v_~m_st~0_10)) InVars {~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_3|} OutVars{ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_2|, ~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_1~0] 23285#L204 [796] L204-->L31: Formula: (and (> v_ULTIMATE.start_eval_~tmp_ndt_1~0_4 0) (= v_~m_st~0_11 1)) InVars {ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_4} OutVars{~m_st~0=v_~m_st~0_11, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_4} AuxVars[] AssignedVars[~m_st~0] 23286#L31 [608] L31-->L58: Formula: (= v_~m_pc~0_8 0) InVars {~m_pc~0=v_~m_pc~0_8} OutVars{~m_pc~0=v_~m_pc~0_8} AuxVars[] AssignedVars[] 23204#L58 [879] L58-->L105-3: Formula: (= 1 v_~E_1~0_29) InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_25, ~E_1~0=v_~E_1~0_29, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_25, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_25, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_14|, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_14|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_14|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ~E_1~0, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 23337#L105-3 [815] L105-3-->L105-5: Formula: (< v_~m_pc~0_13 1) InVars {~m_pc~0=v_~m_pc~0_13} OutVars{~m_pc~0=v_~m_pc~0_13} AuxVars[] AssignedVars[] 23336#L105-5 [631] L105-5-->L116-1: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_22 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_22} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 23216#L116-1 [882] L116-1-->L290-3: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_15| v_ULTIMATE.start_activate_threads_~tmp~1_26) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_26 |v_ULTIMATE.start_is_master_triggered_#res_15|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_26} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_26, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_26, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_15|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_15|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 23214#L290-3 [566] L290-3-->L290-5: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_23) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_23} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_23} AuxVars[] AssignedVars[] 23212#L290-5 [540] L290-5-->L124-3: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_19, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 23210#L124-3 [826] L124-3-->L124-5: Formula: (< v_~t1_pc~0_13 1) InVars {~t1_pc~0=v_~t1_pc~0_13} OutVars{~t1_pc~0=v_~t1_pc~0_13} AuxVars[] AssignedVars[] 23165#L124-5 [658] L124-5-->L135-1: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_23 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_23} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 23208#L135-1 [884] L135-1-->L298-3: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_26 |v_ULTIMATE.start_is_transmit1_triggered_#res_14|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_26 |v_ULTIMATE.start_is_transmit1_triggered_#res_14|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_26} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_26, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_26, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_15|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_14|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 23206#L298-3 [560] L298-3-->L298-5: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_23 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_23} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_23} AuxVars[] AssignedVars[] 23205#L298-5 [556] L298-5-->L35: Formula: (= v_~E_1~0_26 2) InVars {} OutVars{~E_1~0=v_~E_1~0_26} AuxVars[] AssignedVars[~E_1~0] 23197#L35 [880] L35-->L201: Formula: (and (= v_~m_pc~0_17 1) (= 2 v_~m_st~0_20)) InVars {} OutVars{~m_st~0=v_~m_st~0_20, ~m_pc~0=v_~m_pc~0_17} AuxVars[] AssignedVars[~m_st~0, ~m_pc~0] 22493#L201 [799] L201-->L215: Formula: (> v_~t1_st~0_5 0) InVars {~t1_st~0=v_~t1_st~0_5} OutVars{~t1_st~0=v_~t1_st~0_5} AuxVars[] AssignedVars[] 23193#L215 [875] L215-->L169: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_22, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 23668#L169 [781] L169-->L173: Formula: (> v_~m_st~0_9 0) InVars {~m_st~0=v_~m_st~0_9} OutVars{~m_st~0=v_~m_st~0_9} AuxVars[] AssignedVars[] 22465#L173 [785] L173-->L181: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_12 0) (< 0 v_~t1_st~0_11)) InVars {~t1_st~0=v_~t1_st~0_11} OutVars{~t1_st~0=v_~t1_st~0_11, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_12} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 23663#L181 [876] L181-->L196: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 23661#L196 [878] L196-->L240-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 23659#L240-2 [783] L240-2-->L240-4: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 23657#L240-4 [786] L240-4-->L245-3: Formula: (< 0 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 23656#L245-3 [789] L245-3-->L250-3: Formula: (> v_~E_1~0_7 0) InVars {~E_1~0=v_~E_1~0_7} OutVars{~E_1~0=v_~E_1~0_7} AuxVars[] AssignedVars[] 23655#L250-3 [676] L250-3-->L105-6: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_4, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_4|, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_2|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 23652#L105-6 [624] L105-6-->L106-2: Formula: (= v_~m_pc~0_4 1) InVars {~m_pc~0=v_~m_pc~0_4} OutVars{~m_pc~0=v_~m_pc~0_4} AuxVars[] AssignedVars[] 23650#L106-2 [800] L106-2-->L105-8: Formula: (> v_~M_E~0_11 1) InVars {~M_E~0=v_~M_E~0_11} OutVars{~M_E~0=v_~M_E~0_11} AuxVars[] AssignedVars[] 23584#L105-8 [619] L105-8-->L116-2: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 23648#L116-2 [883] L116-2-->L290-6: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_27 |v_ULTIMATE.start_is_master_triggered_#res_16|) (= |v_ULTIMATE.start_is_master_triggered_#res_16| v_ULTIMATE.start_activate_threads_~tmp~1_27)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_27} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_27, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_27, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_16|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 23647#L290-6 [532] L290-6-->L290-8: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 23645#L290-8 [524] L290-8-->L124-6: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 23644#L124-6 [818] L124-6-->L124-8: Formula: (< v_~t1_pc~0_9 1) InVars {~t1_pc~0=v_~t1_pc~0_9} OutVars{~t1_pc~0=v_~t1_pc~0_9} AuxVars[] AssignedVars[] 23004#L124-8 [606] L124-8-->L135-2: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 23643#L135-2 [885] L135-2-->L298-6: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_27 |v_ULTIMATE.start_is_transmit1_triggered_#res_15|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27 |v_ULTIMATE.start_is_transmit1_triggered_#res_15|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_27, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_16|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_15|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 23642#L298-6 [584] L298-6-->L298-8: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 23641#L298-8 [829] L298-8-->L263-3: Formula: (> v_~M_E~0_17 1) InVars {~M_E~0=v_~M_E~0_17} OutVars{~M_E~0=v_~M_E~0_17} AuxVars[] AssignedVars[] 23625#L263-3 [832] L263-3-->L268-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 23617#L268-3 [834] L268-3-->L273-3: Formula: (< 1 v_~E_1~0_17) InVars {~E_1~0=v_~E_1~0_17} OutVars{~E_1~0=v_~E_1~0_17} AuxVars[] AssignedVars[] 23614#L273-3 [628] L273-3-->L169-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 23613#L169-1 [838] L169-1-->L173-1: Formula: (> v_~m_st~0_8 0) InVars {~m_st~0=v_~m_st~0_8} OutVars{~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[] 22948#L173-1 [674] L173-1-->L181-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_9 1) (= v_~t1_st~0_8 0)) InVars {~t1_st~0=v_~t1_st~0_8} OutVars{~t1_st~0=v_~t1_st~0_8, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_9} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 23580#L181-1 [886] L181-1-->L413: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24} OutVars{ULTIMATE.start_start_simulation_#t~ret6=|v_ULTIMATE.start_start_simulation_#t~ret6_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret6, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_~tmp~3] 23504#L413 [887] L413-->L105-9: Formula: (and (= 0 v_ULTIMATE.start_start_simulation_~tmp~3_9) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_15 4) (= v_~M_E~0_28 1)) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_9} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_28, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_15, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_28, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_28, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_17|, ~M_E~0=v_~M_E~0_28, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_17|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_17|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_9} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ~M_E~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 23505#L105-9 [615] L105-9-->L106-3: Formula: (= v_~m_pc~0_6 1) InVars {~m_pc~0=v_~m_pc~0_6} OutVars{~m_pc~0=v_~m_pc~0_6} AuxVars[] AssignedVars[] 23477#L106-3 [508] L106-3-->L116-3: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_16 1) (= v_~M_E~0_19 1)) InVars {~M_E~0=v_~M_E~0_19} OutVars{~M_E~0=v_~M_E~0_19, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_16} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 23480#L116-3 [889] L116-3-->L290-9: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_29 |v_ULTIMATE.start_is_master_triggered_#res_18|) (= |v_ULTIMATE.start_is_master_triggered_#res_18| v_ULTIMATE.start_activate_threads_~tmp~1_29)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_29, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_18|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_18|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 22821#L290-9 [855] L290-9-->L290-11: Formula: (and (= v_~m_st~0_12 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_17)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_17} OutVars{~m_st~0=v_~m_st~0_12, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_17} AuxVars[] AssignedVars[~m_st~0] 22818#L290-11 [552] L290-11-->L124-9: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_13, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 22816#L124-9 [857] L124-9-->L124-11: Formula: (< v_~t1_pc~0_11 1) InVars {~t1_pc~0=v_~t1_pc~0_11} OutVars{~t1_pc~0=v_~t1_pc~0_11} AuxVars[] AssignedVars[] 22788#L124-11 [592] L124-11-->L135-3: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_17 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_17} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 22813#L135-3 [892] L135-3-->L298-9: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_28 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_29 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_28} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_28, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_29, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_18|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 22809#L298-9 [573] L298-9-->L298-11: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_20 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_20} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_20} AuxVars[] AssignedVars[] 22806#L298-11 [864] L298-11-->L331-1: Formula: (< v_~M_E~0_25 1) InVars {~M_E~0=v_~M_E~0_25} OutVars{~M_E~0=v_~M_E~0_25} AuxVars[] AssignedVars[] 22803#L331-1 [867] L331-1-->L336-1: Formula: (> v_~T1_E~0_16 1) InVars {~T1_E~0=v_~T1_E~0_16} OutVars{~T1_E~0=v_~T1_E~0_16} AuxVars[] AssignedVars[] 22763#L336-1 [869] L336-1-->L413-1: Formula: (< 1 v_~E_1~0_25) InVars {~E_1~0=v_~E_1~0_25} OutVars{~E_1~0=v_~E_1~0_25} AuxVars[] AssignedVars[] 22759#L413-1 [659] L413-1-->L169-2: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret5=|v_ULTIMATE.start_stop_simulation_#t~ret5_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret5, ULTIMATE.start_stop_simulation_#res] 22755#L169-2 [536] L169-2-->L181-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18 1) (= 0 v_~m_st~0_14)) InVars {~m_st~0=v_~m_st~0_14} OutVars{~m_st~0=v_~m_st~0_14, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 22753#L181-2 [888] L181-2-->L368: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_stop_simulation_#t~ret5=|v_ULTIMATE.start_stop_simulation_#t~ret5_4|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret5] 22751#L368 [691] L368-->L375: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 22749#L375 [894] L375-->L394-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 22748#L394-1 [874] L394-1-->L215: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 22488#L215 [875] L215-->L169: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_22, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 22745#L169 [780] L169-->L173: Formula: (< v_~m_st~0_9 0) InVars {~m_st~0=v_~m_st~0_9} OutVars{~m_st~0=v_~m_st~0_9} AuxVars[] AssignedVars[] 22746#L173 [785] L173-->L181: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_12 0) (< 0 v_~t1_st~0_11)) InVars {~t1_st~0=v_~t1_st~0_11} OutVars{~t1_st~0=v_~t1_st~0_11, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_12} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 23569#L181 [876] L181-->L196: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 23568#L196 [878] L196-->L240-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 23567#L240-2 [626] L240-2-->L240-4: Formula: (and (= v_~M_E~0_5 1) (= 0 v_~M_E~0_6)) InVars {~M_E~0=v_~M_E~0_6} OutVars{~M_E~0=v_~M_E~0_5} AuxVars[] AssignedVars[~M_E~0] 23565#L240-4 [786] L240-4-->L245-3: Formula: (< 0 v_~T1_E~0_7) InVars {~T1_E~0=v_~T1_E~0_7} OutVars{~T1_E~0=v_~T1_E~0_7} AuxVars[] AssignedVars[] 23563#L245-3 [789] L245-3-->L250-3: Formula: (> v_~E_1~0_7 0) InVars {~E_1~0=v_~E_1~0_7} OutVars{~E_1~0=v_~E_1~0_7} AuxVars[] AssignedVars[] 23561#L250-3 [676] L250-3-->L105-6: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_6, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_4, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_4|, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_2|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 23558#L105-6 [624] L105-6-->L106-2: Formula: (= v_~m_pc~0_4 1) InVars {~m_pc~0=v_~m_pc~0_4} OutVars{~m_pc~0=v_~m_pc~0_4} AuxVars[] AssignedVars[] 23553#L106-2 [511] L106-2-->L116-2: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_10 1) (= v_~M_E~0_10 1)) InVars {~M_E~0=v_~M_E~0_10} OutVars{~M_E~0=v_~M_E~0_10, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_10} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 23551#L116-2 [883] L116-2-->L290-6: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_27 |v_ULTIMATE.start_is_master_triggered_#res_16|) (= |v_ULTIMATE.start_is_master_triggered_#res_16| v_ULTIMATE.start_activate_threads_~tmp~1_27)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_27} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_27, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_27, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_16|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 23548#L290-6 [813] L290-6-->L290-8: Formula: (and (= v_~m_st~0_5 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{~m_st~0=v_~m_st~0_5, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} AuxVars[] AssignedVars[~m_st~0] 22944#L290-8 [524] L290-8-->L124-6: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 22790#L124-6 [818] L124-6-->L124-8: Formula: (< v_~t1_pc~0_9 1) InVars {~t1_pc~0=v_~t1_pc~0_9} OutVars{~t1_pc~0=v_~t1_pc~0_9} AuxVars[] AssignedVars[] 22789#L124-8 [606] L124-8-->L135-2: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 22785#L135-2 [885] L135-2-->L298-6: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_27 |v_ULTIMATE.start_is_transmit1_triggered_#res_15|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27 |v_ULTIMATE.start_is_transmit1_triggered_#res_15|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_27, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_27, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_16|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_15|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 22783#L298-6 [584] L298-6-->L298-8: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 22780#L298-8 [828] L298-8-->L263-3: Formula: (< v_~M_E~0_17 1) InVars {~M_E~0=v_~M_E~0_17} OutVars{~M_E~0=v_~M_E~0_17} AuxVars[] AssignedVars[] 22778#L263-3 [832] L263-3-->L268-3: Formula: (> v_~T1_E~0_13 1) InVars {~T1_E~0=v_~T1_E~0_13} OutVars{~T1_E~0=v_~T1_E~0_13} AuxVars[] AssignedVars[] 22774#L268-3 [834] L268-3-->L273-3: Formula: (< 1 v_~E_1~0_17) InVars {~E_1~0=v_~E_1~0_17} OutVars{~E_1~0=v_~E_1~0_17} AuxVars[] AssignedVars[] 22772#L273-3 [628] L273-3-->L169-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_1|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_1} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 22769#L169-1 [543] L169-1-->L181-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_7 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{~m_st~0=v_~m_st~0_6, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 22766#L181-1 [886] L181-1-->L413: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24} OutVars{ULTIMATE.start_start_simulation_#t~ret6=|v_ULTIMATE.start_start_simulation_#t~ret6_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_24, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret6, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_~tmp~3] 22764#L413 [887] L413-->L105-9: Formula: (and (= 0 v_ULTIMATE.start_start_simulation_~tmp~3_9) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_15 4) (= v_~M_E~0_28 1)) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_9} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_28, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_15, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_28, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_28, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_17|, ~M_E~0=v_~M_E~0_28, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_17|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_17|, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_9} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ~M_E~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 22620#L105-9 [844] L105-9-->L105-11: Formula: (< v_~m_pc~0_7 1) InVars {~m_pc~0=v_~m_pc~0_7} OutVars{~m_pc~0=v_~m_pc~0_7} AuxVars[] AssignedVars[] 22616#L105-11 [563] L105-11-->L116-3: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_17 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_17} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 22617#L116-3 [889] L116-3-->L290-9: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_29 |v_ULTIMATE.start_is_master_triggered_#res_18|) (= |v_ULTIMATE.start_is_master_triggered_#res_18| v_ULTIMATE.start_activate_threads_~tmp~1_29)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_29, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_29, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_18|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_18|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 22606#L290-9 [554] L290-9-->L290-11: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_18) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_18} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_18} AuxVars[] AssignedVars[] 22607#L290-11 [552] L290-11-->L124-9: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_13, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_7|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 22595#L124-9 [857] L124-9-->L124-11: Formula: (< v_~t1_pc~0_11 1) InVars {~t1_pc~0=v_~t1_pc~0_11} OutVars{~t1_pc~0=v_~t1_pc~0_11} AuxVars[] AssignedVars[] 22594#L124-11 [592] L124-11-->L135-3: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_17 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_17} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 22593#L135-3 [892] L135-3-->L298-9: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_28 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_29 |v_ULTIMATE.start_is_transmit1_triggered_#res_16|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_28} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_28, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_29, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_18|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_16|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 22592#L298-9 [573] L298-9-->L298-11: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_20 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_20} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_20} AuxVars[] AssignedVars[] 22590#L298-11 [865] L298-11-->L331-1: Formula: (> v_~M_E~0_25 1) InVars {~M_E~0=v_~M_E~0_25} OutVars{~M_E~0=v_~M_E~0_25} AuxVars[] AssignedVars[] 22560#L331-1 [867] L331-1-->L336-1: Formula: (> v_~T1_E~0_16 1) InVars {~T1_E~0=v_~T1_E~0_16} OutVars{~T1_E~0=v_~T1_E~0_16} AuxVars[] AssignedVars[] 22557#L336-1 [869] L336-1-->L413-1: Formula: (< 1 v_~E_1~0_25) InVars {~E_1~0=v_~E_1~0_25} OutVars{~E_1~0=v_~E_1~0_25} AuxVars[] AssignedVars[] 22554#L413-1 [659] L413-1-->L169-2: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_15, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_7|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_stop_simulation_#t~ret5=|v_ULTIMATE.start_stop_simulation_#t~ret5_1|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret5, ULTIMATE.start_stop_simulation_#res] 22549#L169-2 [536] L169-2-->L181-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18 1) (= 0 v_~m_st~0_14)) InVars {~m_st~0=v_~m_st~0_14} OutVars{~m_st~0=v_~m_st~0_14, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_18} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 22543#L181-2 [888] L181-2-->L368: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_25, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_stop_simulation_#t~ret5=|v_ULTIMATE.start_stop_simulation_#t~ret5_4|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_stop_simulation_#t~ret5] 22539#L368 [691] L368-->L375: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 22536#L375 [894] L375-->L394-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_6|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_stop_simulation_#res] 22358#L394-1 32.00/12.16 [2019-03-28 12:20:23,381 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 32.00/12.16 [2019-03-28 12:20:23,382 INFO L82 PathProgramCache]: Analyzing trace with hash -412880040, now seen corresponding path program 6 times 32.00/12.16 [2019-03-28 12:20:23,382 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 32.00/12.16 [2019-03-28 12:20:23,382 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 32.00/12.16 [2019-03-28 12:20:23,383 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 32.00/12.16 [2019-03-28 12:20:23,383 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 32.00/12.16 [2019-03-28 12:20:23,383 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 32.00/12.16 [2019-03-28 12:20:23,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 32.00/12.16 [2019-03-28 12:20:23,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 32.00/12.16 [2019-03-28 12:20:23,392 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 32.00/12.16 [2019-03-28 12:20:23,392 INFO L82 PathProgramCache]: Analyzing trace with hash 1984835874, now seen corresponding path program 1 times 32.00/12.16 [2019-03-28 12:20:23,392 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 32.00/12.16 [2019-03-28 12:20:23,392 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 32.00/12.16 [2019-03-28 12:20:23,393 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 32.00/12.16 [2019-03-28 12:20:23,393 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY 32.00/12.16 [2019-03-28 12:20:23,393 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 32.00/12.16 [2019-03-28 12:20:23,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat 32.00/12.16 [2019-03-28 12:20:23,428 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 32 proven. 0 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. 32.00/12.16 [2019-03-28 12:20:23,428 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. 32.00/12.16 [2019-03-28 12:20:23,428 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 32.00/12.16 [2019-03-28 12:20:23,429 INFO L811 eck$LassoCheckResult]: loop already infeasible 32.00/12.16 [2019-03-28 12:20:23,429 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. 32.00/12.16 [2019-03-28 12:20:23,429 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 32.00/12.16 [2019-03-28 12:20:23,429 INFO L87 Difference]: Start difference. First operand 2219 states and 3207 transitions. cyclomatic complexity: 996 Second operand 3 states. 32.00/12.16 [2019-03-28 12:20:23,623 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. 32.00/12.16 [2019-03-28 12:20:23,623 INFO L93 Difference]: Finished difference Result 2188 states and 2977 transitions. 32.00/12.16 [2019-03-28 12:20:23,623 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 32.00/12.16 [2019-03-28 12:20:23,624 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2188 states and 2977 transitions. 32.00/12.16 [2019-03-28 12:20:23,631 INFO L131 ngComponentsAnalysis]: Automaton has 15 accepting balls. 2144 32.00/12.16 [2019-03-28 12:20:23,643 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2188 states to 2188 states and 2977 transitions. 32.00/12.16 [2019-03-28 12:20:23,643 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2188 32.00/12.16 [2019-03-28 12:20:23,645 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2188 32.00/12.16 [2019-03-28 12:20:23,645 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2188 states and 2977 transitions. 32.00/12.16 [2019-03-28 12:20:23,647 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. 32.00/12.16 [2019-03-28 12:20:23,647 INFO L706 BuchiCegarLoop]: Abstraction has 2188 states and 2977 transitions. 32.00/12.16 [2019-03-28 12:20:23,649 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2188 states and 2977 transitions. 32.00/12.16 [2019-03-28 12:20:23,683 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2188 to 2188. 32.00/12.16 [2019-03-28 12:20:23,683 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2188 states. 32.00/12.16 [2019-03-28 12:20:23,688 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2188 states to 2188 states and 2977 transitions. 32.00/12.16 [2019-03-28 12:20:23,689 INFO L729 BuchiCegarLoop]: Abstraction has 2188 states and 2977 transitions. 32.00/12.16 [2019-03-28 12:20:23,689 INFO L609 BuchiCegarLoop]: Abstraction has 2188 states and 2977 transitions. 32.00/12.16 [2019-03-28 12:20:23,689 INFO L442 BuchiCegarLoop]: ======== Iteration 20============ 32.00/12.16 [2019-03-28 12:20:23,689 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2188 states and 2977 transitions. 32.00/12.16 [2019-03-28 12:20:23,694 INFO L131 ngComponentsAnalysis]: Automaton has 15 accepting balls. 2144 32.00/12.16 [2019-03-28 12:20:23,695 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false 32.00/12.16 [2019-03-28 12:20:23,695 INFO L119 BuchiIsEmpty]: Starting construction of run 32.00/12.16 [2019-03-28 12:20:23,695 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] 32.00/12.16 [2019-03-28 12:20:23,695 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] 32.00/12.16 [2019-03-28 12:20:23,696 INFO L794 eck$LassoCheckResult]: Stem: 26745#ULTIMATE.startENTRY [871] ULTIMATE.startENTRY-->L144: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~m_pc~0_16 0) (= 0 v_~m_st~0_19) (= 2 v_~E_1~0_28) (= v_~M_E~0_27 2) (= v_~T1_E~0_18 2) (= v_~t1_pc~0_16 0) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= 0 v_~t1_st~0_19)) InVars {} OutVars{ULTIMATE.start_start_simulation_#t~ret7=|v_ULTIMATE.start_start_simulation_#t~ret7_4|, ULTIMATE.start_start_simulation_#t~ret6=|v_ULTIMATE.start_start_simulation_#t~ret6_4|, ~t1_st~0=v_~t1_st~0_19, ~t1_pc~0=v_~t1_pc~0_16, ~M_E~0=v_~M_E~0_27, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~E_1~0=v_~E_1~0_28, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~T1_E~0=v_~T1_E~0_18, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_19, ~m_pc~0=v_~m_pc~0_16, ULTIMATE.start_main_~__retres1~3=v_ULTIMATE.start_main_~__retres1~3_6} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_#t~ret7, ULTIMATE.start_start_simulation_#t~ret6, ~t1_st~0, ~t1_pc~0, ~M_E~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ULTIMATE.start_start_simulation_~kernel_st~0, ~E_1~0, ULTIMATE.start_main_#res, ~T1_E~0, ~t1_i~0, ~m_st~0, ~m_pc~0, ULTIMATE.start_main_~__retres1~3] 26746#L144 [557] L144-->L151-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 26752#L151-1 [672] L151-1-->L156-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 26766#L156-1 [757] L156-1-->L240-1: Formula: (< 0 v_~M_E~0_4) InVars {~M_E~0=v_~M_E~0_4} OutVars{~M_E~0=v_~M_E~0_4} AuxVars[] AssignedVars[] 26777#L240-1 [759] L240-1-->L245-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 26709#L245-1 [760] L245-1-->L250-1: Formula: (> v_~E_1~0_4 0) InVars {~E_1~0=v_~E_1~0_4} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[] 26710#L250-1 [679] L250-1-->L105: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_1, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_1, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_1, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_1|, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_1|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_master_triggered_#res] 26775#L105 [762] L105-->L105-2: Formula: (< v_~m_pc~0_3 1) InVars {~m_pc~0=v_~m_pc~0_3} OutVars{~m_pc~0=v_~m_pc~0_3} AuxVars[] AssignedVars[] 26785#L105-2 [594] L105-2-->L116: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_5 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_5} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 26786#L116 [872] L116-->L290: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_24 |v_ULTIMATE.start_is_master_triggered_#res_13|) (= |v_ULTIMATE.start_is_master_triggered_#res_13| v_ULTIMATE.start_activate_threads_~tmp~1_24)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_24} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_24, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_24, ULTIMATE.start_activate_threads_#t~ret3=|v_ULTIMATE.start_activate_threads_#t~ret3_13|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret3, ULTIMATE.start_is_master_triggered_#res] 26772#L290 [578] L290-->L290-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_9) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_9} AuxVars[] AssignedVars[] 26764#L290-2 [569] L290-2-->L124: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_1, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 26697#L124 [768] L124-->L124-2: Formula: (< v_~t1_pc~0_7 1) InVars {~t1_pc~0=v_~t1_pc~0_7} OutVars{~t1_pc~0=v_~t1_pc~0_7} AuxVars[] AssignedVars[] 26689#L124-2 [632] L124-2-->L135: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_5} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 26690#L135 [873] L135-->L298: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_24 |v_ULTIMATE.start_is_transmit1_triggered_#res_13|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25 |v_ULTIMATE.start_is_transmit1_triggered_#res_13|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_25, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_24, ULTIMATE.start_activate_threads_#t~ret4=|v_ULTIMATE.start_activate_threads_#t~ret4_13|, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_13|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret4, ULTIMATE.start_is_transmit1_triggered_#res] 26702#L298 [611] L298-->L298-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp___0~0_9) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_9} AuxVars[] AssignedVars[] 26753#L298-2 [774] L298-2-->L263-1: Formula: (> v_~M_E~0_14 1) InVars {~M_E~0=v_~M_E~0_14} OutVars{~M_E~0=v_~M_E~0_14} AuxVars[] AssignedVars[] 26695#L263-1 [777] L263-1-->L268-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 26696#L268-1 [778] L268-1-->L394-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 26765#L394-1 [874] L394-1-->L215: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 26875#L215 32.00/12.16 [2019-03-28 12:20:23,696 INFO L796 eck$LassoCheckResult]: Loop: 26875#L215 [875] L215-->L169: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_22, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2, ULTIMATE.start_exists_runnable_thread_#res] 26871#L169 [545] L169-->L181: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_8 1) (= v_~m_st~0_7 0)) InVars {~m_st~0=v_~m_st~0_7} OutVars{~m_st~0=v_~m_st~0_7, ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~2] 26866#L181 [876] L181-->L196: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~2=v_ULTIMATE.start_exists_runnable_thread_~__retres1~2_23, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 26863#L196 [790] L196-->L196-1: Formula: (> v_ULTIMATE.start_eval_~tmp~0_4 0) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} OutVars{ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} AuxVars[] AssignedVars[] 26857#L196-1 [622] L196-1-->L204: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_2 |v_ULTIMATE.start_eval_#t~nondet1_3|) (= 0 v_~m_st~0_10)) InVars {~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_3|} OutVars{ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_2|, ~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_1~0] 26858#L204 [654] L204-->L201: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} AuxVars[] AssignedVars[] 26860#L201 [643] L201-->L218: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_3 |v_ULTIMATE.start_eval_#t~nondet2_3|) (= 0 v_~t1_st~0_16)) InVars {~t1_st~0=v_~t1_st~0_16, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_3|} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_2|, ~t1_st~0=v_~t1_st~0_16, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_3} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_2~0] 26878#L218 [588] L218-->L215: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_1 0) InVars {ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_1} OutVars{ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_1} AuxVars[] AssignedVars[] 26875#L215 32.00/12.16 [2019-03-28 12:20:23,696 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 32.00/12.16 [2019-03-28 12:20:23,697 INFO L82 PathProgramCache]: Analyzing trace with hash 85621522, now seen corresponding path program 1 times 32.00/12.16 [2019-03-28 12:20:23,697 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 32.00/12.16 [2019-03-28 12:20:23,697 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 32.00/12.16 [2019-03-28 12:20:23,698 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 32.00/12.16 [2019-03-28 12:20:23,698 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 32.00/12.16 [2019-03-28 12:20:23,698 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 32.00/12.16 [2019-03-28 12:20:23,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 32.00/12.16 [2019-03-28 12:20:23,704 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 32.00/12.16 [2019-03-28 12:20:23,707 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 32.00/12.16 [2019-03-28 12:20:23,707 INFO L82 PathProgramCache]: Analyzing trace with hash 1149460682, now seen corresponding path program 1 times 32.00/12.16 [2019-03-28 12:20:23,707 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 32.00/12.16 [2019-03-28 12:20:23,707 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 32.00/12.16 [2019-03-28 12:20:23,708 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 32.00/12.16 [2019-03-28 12:20:23,708 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 32.00/12.16 [2019-03-28 12:20:23,708 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 32.00/12.16 [2019-03-28 12:20:23,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 32.00/12.16 [2019-03-28 12:20:23,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 32.00/12.16 [2019-03-28 12:20:23,714 INFO L144 PredicateUnifier]: Initialized classic predicate unifier 32.00/12.16 [2019-03-28 12:20:23,714 INFO L82 PathProgramCache]: Analyzing trace with hash 1233009371, now seen corresponding path program 1 times 32.00/12.16 [2019-03-28 12:20:23,714 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS 32.00/12.16 [2019-03-28 12:20:23,714 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy 32.00/12.16 [2019-03-28 12:20:23,715 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 32.00/12.16 [2019-03-28 12:20:23,715 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY 32.00/12.16 [2019-03-28 12:20:23,715 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY 32.00/12.16 [2019-03-28 12:20:23,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 32.00/12.16 [2019-03-28 12:20:23,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat 32.00/12.16 [2019-03-28 12:20:24,034 WARN L188 SmtUtils]: Spent 235.00 ms on a formula simplification. DAG size of input: 52 DAG size of output: 42 32.00/12.16 [2019-03-28 12:20:24,127 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 28.03 12:20:24 BasicIcfg 32.00/12.16 [2019-03-28 12:20:24,128 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- 32.00/12.16 [2019-03-28 12:20:24,128 INFO L168 Benchmark]: Toolchain (without parser) took 7643.25 ms. Allocated memory was 649.6 MB in the beginning and 853.5 MB in the end (delta: 203.9 MB). Free memory was 563.9 MB in the beginning and 466.8 MB in the end (delta: 97.0 MB). Peak memory consumption was 301.0 MB. Max. memory is 50.3 GB. 32.00/12.16 [2019-03-28 12:20:24,129 INFO L168 Benchmark]: CDTParser took 0.19 ms. Allocated memory is still 649.6 MB. Free memory is still 590.9 MB. There was no memory consumed. Max. memory is 50.3 GB. 32.00/12.16 [2019-03-28 12:20:24,130 INFO L168 Benchmark]: CACSL2BoogieTranslator took 365.13 ms. Allocated memory was 649.6 MB in the beginning and 650.6 MB in the end (delta: 1.0 MB). Free memory was 563.9 MB in the beginning and 612.6 MB in the end (delta: -48.8 MB). Peak memory consumption was 31.8 MB. Max. memory is 50.3 GB. 32.00/12.16 [2019-03-28 12:20:24,130 INFO L168 Benchmark]: Boogie Procedure Inliner took 51.24 ms. Allocated memory is still 650.6 MB. Free memory was 612.6 MB in the beginning and 609.9 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 50.3 GB. 32.00/12.16 [2019-03-28 12:20:24,131 INFO L168 Benchmark]: Boogie Preprocessor took 34.85 ms. Allocated memory is still 650.6 MB. Free memory was 609.9 MB in the beginning and 607.3 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 50.3 GB. 32.00/12.16 [2019-03-28 12:20:24,131 INFO L168 Benchmark]: RCFGBuilder took 536.06 ms. Allocated memory is still 650.6 MB. Free memory was 607.3 MB in the beginning and 560.8 MB in the end (delta: 46.4 MB). Peak memory consumption was 46.4 MB. Max. memory is 50.3 GB. 32.00/12.16 [2019-03-28 12:20:24,132 INFO L168 Benchmark]: BlockEncodingV2 took 184.34 ms. Allocated memory is still 650.6 MB. Free memory was 560.8 MB in the beginning and 543.3 MB in the end (delta: 17.5 MB). Peak memory consumption was 17.5 MB. Max. memory is 50.3 GB. 32.00/12.16 [2019-03-28 12:20:24,132 INFO L168 Benchmark]: TraceAbstraction took 214.04 ms. Allocated memory is still 650.6 MB. Free memory was 543.3 MB in the beginning and 521.7 MB in the end (delta: 21.6 MB). Peak memory consumption was 21.6 MB. Max. memory is 50.3 GB. 32.00/12.16 [2019-03-28 12:20:24,133 INFO L168 Benchmark]: BuchiAutomizer took 6252.39 ms. Allocated memory was 650.6 MB in the beginning and 853.5 MB in the end (delta: 202.9 MB). Free memory was 521.7 MB in the beginning and 466.8 MB in the end (delta: 54.8 MB). Peak memory consumption was 257.7 MB. Max. memory is 50.3 GB. 32.00/12.16 [2019-03-28 12:20:24,137 INFO L337 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### 32.00/12.16 --- Results --- 32.00/12.16 * Results from de.uni_freiburg.informatik.ultimate.plugins.blockencoding: 32.00/12.16 - StatisticsResult: Initial Icfg 32.00/12.16 121 locations, 189 edges 32.00/12.16 - StatisticsResult: Encoded RCFG 32.00/12.16 93 locations, 208 edges 32.00/12.16 * Results from de.uni_freiburg.informatik.ultimate.core: 32.00/12.16 - StatisticsResult: Toolchain Benchmarks 32.00/12.16 Benchmark results are: 32.00/12.16 * CDTParser took 0.19 ms. Allocated memory is still 649.6 MB. Free memory is still 590.9 MB. There was no memory consumed. Max. memory is 50.3 GB. 32.00/12.16 * CACSL2BoogieTranslator took 365.13 ms. Allocated memory was 649.6 MB in the beginning and 650.6 MB in the end (delta: 1.0 MB). Free memory was 563.9 MB in the beginning and 612.6 MB in the end (delta: -48.8 MB). Peak memory consumption was 31.8 MB. Max. memory is 50.3 GB. 32.00/12.16 * Boogie Procedure Inliner took 51.24 ms. Allocated memory is still 650.6 MB. Free memory was 612.6 MB in the beginning and 609.9 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 50.3 GB. 32.00/12.16 * Boogie Preprocessor took 34.85 ms. Allocated memory is still 650.6 MB. Free memory was 609.9 MB in the beginning and 607.3 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 50.3 GB. 32.00/12.16 * RCFGBuilder took 536.06 ms. Allocated memory is still 650.6 MB. Free memory was 607.3 MB in the beginning and 560.8 MB in the end (delta: 46.4 MB). Peak memory consumption was 46.4 MB. Max. memory is 50.3 GB. 32.00/12.16 * BlockEncodingV2 took 184.34 ms. Allocated memory is still 650.6 MB. Free memory was 560.8 MB in the beginning and 543.3 MB in the end (delta: 17.5 MB). Peak memory consumption was 17.5 MB. Max. memory is 50.3 GB. 32.00/12.16 * TraceAbstraction took 214.04 ms. Allocated memory is still 650.6 MB. Free memory was 543.3 MB in the beginning and 521.7 MB in the end (delta: 21.6 MB). Peak memory consumption was 21.6 MB. Max. memory is 50.3 GB. 32.00/12.16 * BuchiAutomizer took 6252.39 ms. Allocated memory was 650.6 MB in the beginning and 853.5 MB in the end (delta: 202.9 MB). Free memory was 521.7 MB in the beginning and 466.8 MB in the end (delta: 54.8 MB). Peak memory consumption was 257.7 MB. Max. memory is 50.3 GB. 32.00/12.16 * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: 32.00/12.16 - AllSpecificationsHoldResult: All specifications hold 32.00/12.16 We were not able to verify any specifiation because the program does not contain any specification. 32.00/12.16 - InvariantResult [Line: 30]: Loop Invariant 32.00/12.16 Derived loop invariant: 1 32.00/12.16 - InvariantResult [Line: 123]: Loop Invariant 32.00/12.16 Derived loop invariant: 1 32.00/12.16 - InvariantResult [Line: 1]: Loop Invariant 32.00/12.16 Derived loop invariant: 1 32.00/12.16 - InvariantResult [Line: 151]: Loop Invariant 32.00/12.16 Derived loop invariant: 1 32.00/12.16 - InvariantResult [Line: 123]: Loop Invariant 32.00/12.16 Derived loop invariant: 1 32.00/12.16 - InvariantResult [Line: 123]: Loop Invariant 32.00/12.16 Derived loop invariant: 1 32.00/12.16 - InvariantResult [Line: 263]: Loop Invariant 32.00/12.16 Derived loop invariant: 1 32.00/12.16 - InvariantResult [Line: 168]: Loop Invariant 32.00/12.16 Derived loop invariant: 1 32.00/12.16 - InvariantResult [Line: 191]: Loop Invariant 32.00/12.16 Derived loop invariant: 1 32.00/12.16 - InvariantResult [Line: 168]: Loop Invariant 32.00/12.16 Derived loop invariant: 1 32.00/12.16 - InvariantResult [Line: 331]: Loop Invariant 32.00/12.16 Derived loop invariant: 1 32.00/12.16 - InvariantResult [Line: 413]: Loop Invariant 32.00/12.16 Derived loop invariant: 1 32.00/12.16 - InvariantResult [Line: 1]: Loop Invariant 32.00/12.16 Derived loop invariant: 1 32.00/12.16 - InvariantResult [Line: 236]: Loop Invariant 32.00/12.16 Derived loop invariant: 1 32.00/12.16 - InvariantResult [Line: 413]: Loop Invariant 32.00/12.16 Derived loop invariant: 1 32.00/12.16 - InvariantResult [Line: 191]: Loop Invariant 32.00/12.16 Derived loop invariant: 1 32.00/12.16 - InvariantResult [Line: 263]: Loop Invariant 32.00/12.16 Derived loop invariant: 1 32.00/12.16 - InvariantResult [Line: 236]: Loop Invariant 32.00/12.16 Derived loop invariant: 1 32.00/12.16 - InvariantResult [Line: 123]: Loop Invariant 32.00/12.16 Derived loop invariant: 1 32.00/12.16 - InvariantResult [Line: 240]: Loop Invariant 32.00/12.16 Derived loop invariant: 1 32.00/12.16 - InvariantResult [Line: 104]: Loop Invariant 32.00/12.16 Derived loop invariant: 1 32.00/12.16 - InvariantResult [Line: 364]: Loop Invariant 32.00/12.16 Derived loop invariant: 1 32.00/12.16 - InvariantResult [Line: 104]: Loop Invariant 32.00/12.16 Derived loop invariant: 1 32.00/12.16 - InvariantResult [Line: 104]: Loop Invariant 32.00/12.16 Derived loop invariant: 1 32.00/12.16 - InvariantResult [Line: 104]: Loop Invariant 32.00/12.16 Derived loop invariant: 1 32.00/12.16 - InvariantResult [Line: 259]: Loop Invariant 32.00/12.16 Derived loop invariant: 1 32.00/12.16 - InvariantResult [Line: 168]: Loop Invariant 32.00/12.16 Derived loop invariant: 1 32.00/12.16 - InvariantResult [Line: -1]: Loop Invariant 32.00/12.16 Derived loop invariant: 1 32.00/12.16 - InvariantResult [Line: 30]: Loop Invariant 32.00/12.16 Derived loop invariant: 1 32.00/12.16 - InvariantResult [Line: 259]: Loop Invariant 32.00/12.16 Derived loop invariant: 1 32.00/12.16 - InvariantResult [Line: 196]: Loop Invariant 32.00/12.16 Derived loop invariant: 1 32.00/12.16 - StatisticsResult: Ultimate Automizer benchmark data 32.00/12.16 CFG has 1 procedures, 93 locations, 0 error locations. SAFE Result, 0.1s OverallTime, 0 OverallIterations, 0 TraceHistogramMax, 0.0s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: No data available, PredicateUnifierStatistics: No data available, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=93occurred in iteration=0, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: No data available, HoareAnnotationStatistics: 0.0s HoareAnnotationTime, 31 LocationsWithAnnotation, 31 PreInvPairs, 31 NumberOfFragments, 31 HoareAnnotationTreeSize, 31 FomulaSimplifications, 0 FormulaSimplificationTreeSizeReduction, 0.0s HoareSimplificationTime, 31 FomulaSimplificationsInter, 0 FormulaSimplificationTreeSizeReductionInter, 0.0s HoareSimplificationTimeInter, RefinementEngineStatistics: No data available, ReuseStatistics: No data available 32.00/12.16 - StatisticsResult: Constructed decomposition of program 32.00/12.16 Your program was decomposed into 19 terminating modules (19 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.19 modules have a trivial ranking function, the largest among these consists of 6 locations. The remainder module has 2188 locations. 32.00/12.16 - StatisticsResult: Timing statistics 32.00/12.16 BüchiAutomizer plugin needed 6.2s and 20 iterations. TraceHistogramMax:3. Analysis of lassos took 1.5s. Construction of modules took 2.6s. Büchi inclusion checks took 1.2s. Highest rank in rank-based complementation 0. Minimization of det autom 19. Minimization of nondet autom 0. Automata minimization 0.3s AutomataMinimizationTime, 19 MinimizatonAttempts, 1194 StatesRemovedByMinimization, 7 NontrivialMinimizations. Non-live state removal took 0.1s Buchi closure took 0.0s. Biggest automaton had 2219 states and ocurred in iteration 18. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 1518 SDtfs, 4400 SDslu, 2192 SDs, 0 SdLazy, 3343 SolverSat, 221 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 2.6s Time LassoAnalysisResults: nont1 unkn0 SFLI6 SFLT0 conc0 concLT0 SILN0 SILU0 SILI13 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s 32.00/12.16 - TerminationAnalysisResult: Nontermination possible 32.00/12.16 Buchi Automizer proved that your program is nonterminating for some inputs 32.00/12.16 - FixpointNonTerminationResult [Line: 191]: Nontermination argument in form of an infinite program execution. 32.00/12.16 Nontermination argument in form of an infinite execution 32.00/12.16 State at position 0 is 32.00/12.16 {} 32.00/12.16 State at position 1 is 32.00/12.16 {org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7ed8fdbf=0, \result=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6a05b471=0, tmp=1, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@564a0ad=0, kernel_st=1, __retres1=0, tmp___0=0, t1_pc=0, __retres1=1, T1_E=2, \result=0, E_1=2, tmp_ndt_1=0, M_E=2, tmp_ndt_2=0, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@55c59d6c=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@31b197b=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3e8df4e2=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1fdd355d=0, t1_st=0, m_st=0, tmp___0=0, tmp=0, __retres1=0, t1_i=1, m_pc=0, \result=1} 32.00/12.16 - StatisticsResult: NonterminationArgumentStatistics 32.00/12.16 Fixpoint 32.00/12.16 - NonterminatingLassoResult [Line: 191]: Nonterminating execution 32.00/12.16 Found a nonterminating execution for the following lasso shaped sequence of statements. 32.00/12.16 Stem: 32.00/12.16 [L15] int m_pc = 0; 32.00/12.16 [L16] int t1_pc = 0; 32.00/12.16 [L17] int m_st ; 32.00/12.16 [L18] int t1_st ; 32.00/12.16 [L19] int m_i ; 32.00/12.16 [L20] int t1_i ; 32.00/12.16 [L21] int M_E = 2; 32.00/12.16 [L22] int T1_E = 2; 32.00/12.16 [L23] int E_1 = 2; 32.00/12.16 [L439] int __retres1 ; 32.00/12.16 [L354] m_i = 1 32.00/12.16 [L355] t1_i = 1 32.00/12.16 [L380] int kernel_st ; 32.00/12.16 [L381] int tmp ; 32.00/12.16 [L382] int tmp___0 ; 32.00/12.16 [L386] kernel_st = 0 32.00/12.16 [L151] COND TRUE m_i == 1 32.00/12.16 [L152] m_st = 0 32.00/12.16 [L156] COND TRUE t1_i == 1 32.00/12.16 [L157] t1_st = 0 32.00/12.16 [L240] COND FALSE !(M_E == 0) 32.00/12.16 [L245] COND FALSE !(T1_E == 0) 32.00/12.16 [L250] COND FALSE !(E_1 == 0) 32.00/12.16 [L283] int tmp ; 32.00/12.16 [L284] int tmp___0 ; 32.00/12.16 [L102] int __retres1 ; 32.00/12.16 [L105] COND FALSE !(m_pc == 1) 32.00/12.16 [L115] __retres1 = 0 32.00/12.16 [L117] return (__retres1); 32.00/12.16 [L288] tmp = is_master_triggered() 32.00/12.16 [L290] COND FALSE !(\read(tmp)) 32.00/12.16 [L121] int __retres1 ; 32.00/12.16 [L124] COND FALSE !(t1_pc == 1) 32.00/12.16 [L134] __retres1 = 0 32.00/12.16 [L136] return (__retres1); 32.00/12.16 [L296] tmp___0 = is_transmit1_triggered() 32.00/12.16 [L298] COND FALSE !(\read(tmp___0)) 32.00/12.16 [L263] COND FALSE !(M_E == 1) 32.00/12.16 [L268] COND FALSE !(T1_E == 1) 32.00/12.16 [L273] COND FALSE !(E_1 == 1) 32.00/12.16 [L394] COND TRUE 1 32.00/12.16 [L397] kernel_st = 1 32.00/12.16 [L187] int tmp ; 32.00/12.16 Loop: 32.00/12.16 [L191] COND TRUE 1 32.00/12.16 [L166] int __retres1 ; 32.00/12.16 [L169] COND TRUE m_st == 0 32.00/12.16 [L170] __retres1 = 1 32.00/12.16 [L182] return (__retres1); 32.00/12.16 [L194] tmp = exists_runnable_thread() 32.00/12.16 [L196] COND TRUE \read(tmp) 32.00/12.16 [L201] COND TRUE m_st == 0 32.00/12.16 [L202] int tmp_ndt_1; 32.00/12.16 [L203] tmp_ndt_1 = __VERIFIER_nondet_int() 32.00/12.16 [L204] COND FALSE !(\read(tmp_ndt_1)) 32.00/12.16 [L215] COND TRUE t1_st == 0 32.00/12.16 [L216] int tmp_ndt_2; 32.00/12.16 [L217] tmp_ndt_2 = __VERIFIER_nondet_int() 32.00/12.16 [L218] COND FALSE !(\read(tmp_ndt_2)) 32.00/12.16 End of lasso representation. 32.00/12.16 RESULT: Ultimate proved your program to be incorrect! 32.00/12.16 !SESSION 2019-03-28 12:20:13.178 ----------------------------------------------- 32.00/12.16 eclipse.buildId=unknown 32.00/12.16 java.version=1.8.0_181 32.00/12.16 java.vendor=Oracle Corporation 32.00/12.16 BootLoader constants: OS=linux, ARCH=x86_64, WS=gtk, NL=en_US 32.00/12.16 Framework arguments: -tc ./../AutomizerAndBuchiAutomizerCInlineWithBlockEncoding.xml -s ./../termcomp2017.epf -i /export/starexec/sandbox/benchmark/theBenchmark.c 32.00/12.16 Command-line arguments: -os linux -ws gtk -arch x86_64 -consoleLog -data @user.home/.ultimate -tc ./../AutomizerAndBuchiAutomizerCInlineWithBlockEncoding.xml -s ./../termcomp2017.epf -data /export/starexec/sandbox/tmp -i /export/starexec/sandbox/benchmark/theBenchmark.c 32.00/12.16 32.00/12.16 !ENTRY org.eclipse.core.resources 2 10035 2019-03-28 12:20:24.383 32.00/12.16 !MESSAGE The workspace will exit with unsaved changes in this session. 32.00/12.16 Received shutdown request... 32.00/12.16 Ultimate: 32.00/12.16 GTK+ Version Check 32.00/12.16 EOF