17.11/6.04	YES
17.50/6.06	proof of /export/starexec/sandbox2/benchmark/theBenchmark.c
17.50/6.06	# AProVE Commit ID: 48fb2092695e11cc9f56e44b17a92a5f88ffb256 marcel 20180622 unpublished dirty
17.50/6.06	
17.50/6.06	
17.50/6.06	Termination of the given C Problem could be proven:
17.50/6.06	
17.50/6.06	(0) C Problem
17.50/6.06	(1) CToLLVMProof [EQUIVALENT, 162 ms]
17.50/6.06	(2) LLVM problem
17.50/6.06	(3) LLVMToTerminationGraphProof [EQUIVALENT, 1473 ms]
17.50/6.06	(4) LLVM Symbolic Execution Graph
17.50/6.06	(5) SymbolicExecutionGraphToSCCProof [SOUND, 0 ms]
17.50/6.06	(6) AND
17.50/6.06	    (7) LLVM Symbolic Execution SCC
17.50/6.06	        (8) SCC2IRS [SOUND, 105 ms]
17.50/6.06	        (9) IntTRS
17.50/6.06	        (10) IntTRSCompressionProof [EQUIVALENT, 0 ms]
17.50/6.06	        (11) IntTRS
17.50/6.06	        (12) RankingReductionPairProof [EQUIVALENT, 20 ms]
17.50/6.06	        (13) YES
17.50/6.06	    (14) LLVM Symbolic Execution SCC
17.50/6.06	        (15) SCC2IRS [SOUND, 69 ms]
17.50/6.06	        (16) IntTRS
17.50/6.06	        (17) IntTRSCompressionProof [EQUIVALENT, 1 ms]
17.50/6.06	        (18) IntTRS
17.50/6.06	        (19) RankingReductionPairProof [EQUIVALENT, 0 ms]
17.50/6.06	        (20) YES
17.50/6.06	
17.50/6.06	
17.50/6.06	----------------------------------------
17.50/6.06	
17.50/6.06	(0)
17.50/6.06	Obligation:
17.50/6.06	c file /export/starexec/sandbox2/benchmark/theBenchmark.c
17.50/6.06	----------------------------------------
17.50/6.06	
17.50/6.06	(1) CToLLVMProof (EQUIVALENT)
17.50/6.06	Compiled c-file /export/starexec/sandbox2/benchmark/theBenchmark.c to LLVM.
17.50/6.06	----------------------------------------
17.50/6.06	
17.50/6.06	(2)
17.50/6.06	Obligation:
17.50/6.06	LLVM Problem
17.50/6.06	
17.50/6.06	Aliases:
17.50/6.06	
17.50/6.06	Data layout:
17.50/6.06	
17.50/6.06	"e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
17.50/6.06	
17.50/6.06	Machine:
17.50/6.06	
17.50/6.06	"x86_64-pc-linux-gnu"
17.50/6.06	
17.50/6.06	Type definitions:
17.50/6.06	
17.50/6.06	Global variables:
17.50/6.06	
17.50/6.06	Function declarations and definitions:
17.50/6.06	
17.50/6.06	*BasicFunctionTypename: "__VERIFIER_nondet_int" returnParam: i32 parameters: () variableLength: false visibilityType: DEFAULT callingConvention: ccc
17.50/6.06	*BasicFunctionTypename: "main" linkageType: EXTERNALLY_VISIBLE returnParam: i32 parameters: () variableLength: false visibilityType: DEFAULT callingConvention: ccc
17.50/6.06		0:
17.50/6.06			%1 = alloca i32, align 4
17.50/6.06			%y = alloca i32, align 4
17.50/6.06			%z = alloca i32, align 4
17.50/6.06			%x = alloca i32, align 4
17.50/6.06			store 0, %1
17.50/6.06			%2 = call i32 @__VERIFIER_nondet_int()
17.50/6.06			store %2, %y
17.50/6.06			%3 = call i32 @__VERIFIER_nondet_int()
17.50/6.06			store %3, %z
17.50/6.06			%4 = call i32 @__VERIFIER_nondet_int()
17.50/6.06			%5 = icmp ne %4 0
17.50/6.06			br %5, %6, %7
17.50/6.06		6:
17.50/6.06			store 1, %x
17.50/6.06			br %8
17.50/6.06		7:
17.50/6.06			store -1, %x
17.50/6.06			br %8
17.50/6.06		8:
17.50/6.06			%9 = load %x
17.50/6.06			%10 = icmp sgt %9 0
17.50/6.06			br %10, %11, %14
17.50/6.06		11:
17.50/6.06			%12 = load %x
17.50/6.06			%13 = add %12 1
17.50/6.06			store %13, %x
17.50/6.06			br %17
17.50/6.06		14:
17.50/6.06			%15 = load %x
17.50/6.06			%16 = add %15 -1
17.50/6.06			store %16, %x
17.50/6.06			br %17
17.50/6.06		17:
17.50/6.06			%18 = load %x
17.50/6.06			%19 = icmp sgt %18 0
17.50/6.06			br %19, %20, %23
17.50/6.06		20:
17.50/6.06			%21 = load %x
17.50/6.06			%22 = add %21 1
17.50/6.06			store %22, %x
17.50/6.06			br %26
17.50/6.06		23:
17.50/6.06			%24 = load %x
17.50/6.06			%25 = add %24 -1
17.50/6.06			store %25, %x
17.50/6.06			br %26
17.50/6.06		26:
17.50/6.06			%27 = load %x
17.50/6.06			%28 = icmp sgt %27 0
17.50/6.06			br %28, %29, %32
17.50/6.06		29:
17.50/6.06			%30 = load %x
17.50/6.06			%31 = add %30 1
17.50/6.06			store %31, %x
17.50/6.06			br %35
17.50/6.06		32:
17.50/6.06			%33 = load %x
17.50/6.06			%34 = add %33 -1
17.50/6.06			store %34, %x
17.50/6.06			br %35
17.50/6.06		35:
17.50/6.06			%36 = load %x
17.50/6.06			%37 = icmp sgt %36 0
17.50/6.06			br %37, %38, %41
17.50/6.06		38:
17.50/6.06			%39 = load %x
17.50/6.06			%40 = add %39 1
17.50/6.06			store %40, %x
17.50/6.06			br %44
17.50/6.06		41:
17.50/6.06			%42 = load %x
17.50/6.06			%43 = add %42 -1
17.50/6.06			store %43, %x
17.50/6.06			br %44
17.50/6.06		44:
17.50/6.06			%45 = load %x
17.50/6.06			%46 = icmp sgt %45 0
17.50/6.06			br %46, %47, %50
17.50/6.06		47:
17.50/6.06			%48 = load %x
17.50/6.06			%49 = add %48 1
17.50/6.06			store %49, %x
17.50/6.06			br %53
17.50/6.06		50:
17.50/6.06			%51 = load %x
17.50/6.06			%52 = add %51 -1
17.50/6.06			store %52, %x
17.50/6.06			br %53
17.50/6.06		53:
17.50/6.06			%54 = load %x
17.50/6.06			%55 = icmp sgt %54 0
17.50/6.06			br %55, %56, %59
17.50/6.06		56:
17.50/6.06			%57 = load %x
17.50/6.06			%58 = add %57 1
17.50/6.06			store %58, %x
17.50/6.06			br %62
17.50/6.06		59:
17.50/6.06			%60 = load %x
17.50/6.06			%61 = add %60 -1
17.50/6.06			store %61, %x
17.50/6.06			br %62
17.50/6.06		62:
17.50/6.06			%63 = load %x
17.50/6.06			%64 = icmp sgt %63 0
17.50/6.06			br %64, %65, %68
17.50/6.06		65:
17.50/6.06			%66 = load %x
17.50/6.06			%67 = add %66 1
17.50/6.06			store %67, %x
17.50/6.06			br %71
17.50/6.06		68:
17.50/6.06			%69 = load %x
17.50/6.06			%70 = add %69 -1
17.50/6.06			store %70, %x
17.50/6.06			br %71
17.50/6.06		71:
17.50/6.06			%72 = load %x
17.50/6.06			%73 = icmp sgt %72 0
17.50/6.06			br %73, %74, %77
17.50/6.06		74:
17.50/6.06			%75 = load %x
17.50/6.06			%76 = add %75 1
17.50/6.06			store %76, %x
17.50/6.06			br %80
17.50/6.06		77:
17.50/6.06			%78 = load %x
17.50/6.06			%79 = add %78 -1
17.50/6.06			store %79, %x
17.50/6.06			br %80
17.50/6.06		80:
17.50/6.06			br %81
17.50/6.06		81:
17.50/6.06			%82 = load %y
17.50/6.06			%83 = icmp slt %82 100
17.50/6.06			br %83, %84, %87
17.50/6.06		84:
17.50/6.06			%85 = load %z
17.50/6.06			%86 = icmp slt %85 100
17.50/6.06			br %87
17.50/6.06		87:
17.50/6.06			%88 = phi [0, %81], [%86, %84]
17.50/6.06			br %88, %89, %96
17.50/6.06		89:
17.50/6.06			%90 = load %y
17.50/6.06			%91 = load %x
17.50/6.06			%92 = add %90 %91
17.50/6.06			store %92, %y
17.50/6.06			%93 = load %z
17.50/6.06			%94 = load %x
17.50/6.06			%95 = sub %93 %94
17.50/6.06			store %95, %z
17.50/6.06			br %81
17.50/6.06		96:
17.50/6.06			ret 0
17.50/6.06	
17.50/6.06	
17.50/6.06	Analyze Termination of all function calls matching the pattern:
17.50/6.06	main()
17.50/6.06	----------------------------------------
17.50/6.06	
17.50/6.06	(3) LLVMToTerminationGraphProof (EQUIVALENT)
17.50/6.06	Constructed symbolic execution graph for LLVM program and proved memory safety.
17.50/6.06	----------------------------------------
17.50/6.06	
17.50/6.06	(4)
17.50/6.06	Obligation:
17.50/6.06	SE Graph
17.50/6.06	----------------------------------------
17.50/6.06	
17.50/6.06	(5) SymbolicExecutionGraphToSCCProof (SOUND)
17.50/6.06	Splitted symbolic execution graph to 2 SCCs.
17.50/6.06	----------------------------------------
17.50/6.06	
17.50/6.06	(6)
17.50/6.06	Complex Obligation (AND)
17.50/6.06	
17.50/6.06	----------------------------------------
17.50/6.06	
17.50/6.06	(7)
17.50/6.06	Obligation:
17.50/6.06	SCC
17.50/6.06	----------------------------------------
17.50/6.06	
17.50/6.06	(8) SCC2IRS (SOUND)
17.50/6.06	Transformed LLVM symbolic execution graph SCC into a rewrite problem. Log: 
17.50/6.06	Generated rules. Obtained 18 rulesP rules:
17.50/6.06	f_648(v939, v940, v941, v942, v943, v944, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, v958, 1, v957, v955, v959, v960, v961, v962, v963, 3, 9, 99, 90, 108, 4) -> f_651(v939, v940, v941, v942, v943, v944, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, v958, 1, v957, v955, v959, v960, v961, v962, v963, 3, 9, 99, 90, 108, 4) :|: 0 = 0
17.50/6.06	f_651(v939, v940, v941, v942, v943, v944, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, v958, 1, v957, v955, v959, v960, v961, v962, v963, 3, 9, 99, 90, 108, 4) -> f_654(v939, v940, v941, v942, v943, v944, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, v958, 1, v957, v955, v959, v960, v961, v962, v963, 3, 9, 99, 90, 108, 4) :|: TRUE
17.50/6.06	f_654(v939, v940, v941, v942, v943, v944, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, v958, 1, v957, v955, v959, v960, v961, v962, v963, 3, 9, 99, 90, 108, 4) -> f_657(v939, v940, v941, v942, v943, v944, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, v958, 1, v959, v955, v957, v960, v961, v962, v963, 3, 9, 99, 90, 108, 4) :|: 0 = 0
17.50/6.06	f_657(v939, v940, v941, v942, v943, v944, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, v958, 1, v959, v955, v957, v960, v961, v962, v963, 3, 9, 99, 90, 108, 4) -> f_660(v939, v940, v941, v942, v943, v944, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, v958, 1, v959, v955, v957, v960, v961, v962, v963, 3, 9, 99, 90, 4) :|: v959 < 100 && v957 <= 90
17.50/6.06	f_660(v939, v940, v941, v942, v943, v944, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, v958, 1, v959, v955, v957, v960, v961, v962, v963, 3, 9, 99, 90, 4) -> f_663(v939, v940, v941, v942, v943, v944, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, v958, 1, v959, v955, v957, v960, v961, v962, v963, 3, 9, 99, 90, 4) :|: 0 = 0
17.50/6.06	f_663(v939, v940, v941, v942, v943, v944, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, v958, 1, v959, v955, v957, v960, v961, v962, v963, 3, 9, 99, 90, 4) -> f_666(v939, v940, v941, v942, v943, v944, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, v958, 1, v959, v955, v957, v960, v961, v962, v963, 3, 9, 99, 90, 4) :|: 0 = 0
17.50/6.06	f_666(v939, v940, v941, v942, v943, v944, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, v958, 1, v959, v955, v957, v960, v961, v962, v963, 3, 9, 99, 90, 4) -> f_669(v939, v940, v941, v942, v943, v944, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, v958, 1, v959, v955, v957, v960, v961, v962, v963, 3, 9, 99, 90, 4) :|: TRUE
17.50/6.06	f_669(v939, v940, v941, v942, v943, v944, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, v958, 1, v959, v955, v957, v960, v961, v962, v963, 3, 9, 99, 90, 4) -> f_672(v939, v940, v941, v942, v943, v944, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, v958, 1, v959, v957, v960, v961, v962, v963, 3, 9, 99, 90, 4) :|: 0 = 0
17.50/6.06	f_672(v939, v940, v941, v942, v943, v944, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, v958, 1, v959, v957, v960, v961, v962, v963, 3, 9, 99, 90, 4) -> f_674(v939, v940, v941, v942, v943, v944, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, v958, 1, v959, v957, v960, v961, v962, v963, 3, 9, 99, 90, 4) :|: 0 = 0
17.50/6.06	f_674(v939, v940, v941, v942, v943, v944, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, v958, 1, v959, v957, v960, v961, v962, v963, 3, 9, 99, 90, 4) -> f_676(v939, v940, v941, v942, v943, v944, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, v958, 1, v959, v1269, v957, v960, v961, v962, v963, 3, 9, 99, 90, 4, 81) :|: 9 + v1269 = v958 && v1269 <= 81
17.50/6.06	f_676(v939, v940, v941, v942, v943, v944, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, v958, 1, v959, v1269, v957, v960, v961, v962, v963, 3, 9, 99, 90, 4, 81) -> f_678(v939, v940, v941, v942, v943, v944, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, v958, 1, v959, v1269, v957, v960, v961, v962, v963, 3, 9, 99, 90, 4, 81) :|: TRUE
17.50/6.06	f_678(v939, v940, v941, v942, v943, v944, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, v958, 1, v959, v1269, v957, v960, v961, v962, v963, 3, 9, 99, 90, 4, 81) -> f_680(v939, v940, v941, v942, v943, v944, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, v958, 1, v959, v1269, v960, v961, v962, v963, 3, 9, 99, 90, 4, 81) :|: 0 = 0
17.50/6.06	f_680(v939, v940, v941, v942, v943, v944, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, v958, 1, v959, v1269, v960, v961, v962, v963, 3, 9, 99, 90, 4, 81) -> f_682(v939, v940, v941, v942, v943, v944, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, v958, 1, v959, v1269, v960, v961, v962, v963, 3, 9, 99, 90, 4, 81) :|: 0 = 0
17.50/6.06	f_682(v939, v940, v941, v942, v943, v944, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, v958, 1, v959, v1269, v960, v961, v962, v963, 3, 9, 99, 90, 4, 81) -> f_684(v939, v940, v941, v942, v943, v944, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, v958, 1, v959, v1269, v1273, v960, v961, v962, v963, 3, 9, 99, 90, 4, 81, 108) :|: v1273 = 9 + v959 && v1273 <= 108
17.50/6.06	f_684(v939, v940, v941, v942, v943, v944, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, v958, 1, v959, v1269, v1273, v960, v961, v962, v963, 3, 9, 99, 90, 4, 81, 108) -> f_686(v939, v940, v941, v942, v943, v944, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, v958, 1, v959, v1269, v1273, v960, v961, v962, v963, 3, 9, 99, 90, 4, 81, 108) :|: TRUE
17.50/6.06	f_686(v939, v940, v941, v942, v943, v944, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, v958, 1, v959, v1269, v1273, v960, v961, v962, v963, 3, 9, 99, 90, 4, 81, 108) -> f_688(v939, v940, v941, v942, v943, v944, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, v958, 1, v959, v1269, v1273, v960, v961, v962, v963, 3, 9, 99, 90, 4, 81, 108) :|: TRUE
17.50/6.06	f_688(v939, v940, v941, v942, v943, v944, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, v958, 1, v959, v1269, v1273, v960, v961, v962, v963, 3, 9, 99, 90, 4, 81, 108) -> f_646(v939, v940, v941, v942, v943, v944, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, v958, 1, v959, v1269, v1273, v960, v961, v962, v963, 3, 9, 99, 90, 108, 4) :|: TRUE
17.50/6.06	f_646(v939, v940, v941, v942, v943, v944, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, v955, 1, v957, v958, v959, v960, v961, v962, v963, 3, 9, 99, 90, 108, 4) -> f_648(v939, v940, v941, v942, v943, v944, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, v958, 1, v957, v955, v959, v960, v961, v962, v963, 3, 9, 99, 90, 108, 4) :|: 0 = 0
17.50/6.06	Combined rules. Obtained 1 rulesP rules:
17.50/6.06	f_648(v939:0, v940:0, v941:0, v942:0, v943:0, v944:0, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, 9 + v1269:0, 1, v957:0, v955:0, v959:0, v960:0, v961:0, v962:0, v963:0, 3, 9, 99, 90, 108, 4) -> f_648(v939:0, v940:0, v941:0, v942:0, v943:0, v944:0, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, v1269:0, 1, v959:0, 9 + v1269:0, 9 + v959:0, v960:0, v961:0, v962:0, v963:0, 3, 9, 99, 90, 108, 4) :|: v957:0 < 91 && v959:0 < 100 && v1269:0 < 82
17.50/6.06	Filtered unneeded arguments:
17.50/6.06	   f_648(x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, x16, x17, x18, x19, x20, x21, x22, x23, x24, x25, x26, x27, x28, x29, x30, x31) -> f_648(x17, x19, x21)
17.50/6.06	Removed division, modulo operations, cleaned up constraints. Obtained 1 rules.P rules:
17.50/6.06	f_648(sum~cons_9~v1269:0, v957:0, v959:0) -> f_648(v1269:0, v959:0, 9 + v959:0) :|: v959:0 < 100 && v1269:0 < 82 && v957:0 < 91 && sum~cons_9~v1269:0 = 9 + v1269:0
17.50/6.06	
17.50/6.06	----------------------------------------
17.50/6.06	
17.50/6.06	(9)
17.50/6.06	Obligation:
17.50/6.06	Rules:
17.50/6.06	f_648(sum~cons_9~v1269:0, v957:0, v959:0) -> f_648(v1269:0, v959:0, 9 + v959:0) :|: v959:0 < 100 && v1269:0 < 82 && v957:0 < 91 && sum~cons_9~v1269:0 = 9 + v1269:0
17.50/6.06	
17.50/6.06	----------------------------------------
17.50/6.06	
17.50/6.06	(10) IntTRSCompressionProof (EQUIVALENT)
17.50/6.06	Compressed rules.
17.50/6.06	----------------------------------------
17.50/6.06	
17.50/6.06	(11)
17.50/6.06	Obligation:
17.50/6.06	Rules:
17.50/6.06	f_648(sum~cons_9~v1269:0:0, v957:0:0, v959:0:0) -> f_648(v1269:0:0, v959:0:0, 9 + v959:0:0) :|: v959:0:0 < 100 && v1269:0:0 < 82 && v957:0:0 < 91 && sum~cons_9~v1269:0:0 = 9 + v1269:0:0
17.50/6.06	
17.50/6.06	----------------------------------------
17.50/6.06	
17.50/6.06	(12) RankingReductionPairProof (EQUIVALENT)
17.50/6.06	Interpretation:
17.50/6.06	[ f_648 ] = -1/9*f_648_3
17.50/6.06	
17.50/6.06	The following rules are decreasing:
17.50/6.06	f_648(sum~cons_9~v1269:0:0, v957:0:0, v959:0:0) -> f_648(v1269:0:0, v959:0:0, 9 + v959:0:0) :|: v959:0:0 < 100 && v1269:0:0 < 82 && v957:0:0 < 91 && sum~cons_9~v1269:0:0 = 9 + v1269:0:0
17.50/6.06	
17.50/6.06	The following rules are bounded:
17.50/6.06	f_648(sum~cons_9~v1269:0:0, v957:0:0, v959:0:0) -> f_648(v1269:0:0, v959:0:0, 9 + v959:0:0) :|: v959:0:0 < 100 && v1269:0:0 < 82 && v957:0:0 < 91 && sum~cons_9~v1269:0:0 = 9 + v1269:0:0
17.50/6.06	
17.50/6.06	
17.50/6.06	----------------------------------------
17.50/6.06	
17.50/6.06	(13)
17.50/6.06	YES
17.50/6.06	
17.50/6.06	----------------------------------------
17.50/6.06	
17.50/6.06	(14)
17.50/6.06	Obligation:
17.50/6.06	SCC
17.50/6.06	----------------------------------------
17.50/6.06	
17.50/6.06	(15) SCC2IRS (SOUND)
17.50/6.06	Transformed LLVM symbolic execution graph SCC into a rewrite problem. Log: 
17.50/6.06	Generated rules. Obtained 18 rulesP rules:
17.50/6.06	f_647(v891, v892, v893, v894, v895, v896, v897, 1, 2, 3, 4, 5, 6, 7, 8, 9, v909, v908, v907, v910, v911, v912, v913, v914, 0, 99, 108, 90) -> f_649(v891, v892, v893, v894, v895, v896, v897, 1, 2, 3, 4, 5, 6, 7, 8, 9, v909, v908, v907, v910, v911, v912, v913, v914, 0, 99, 90) :|: v909 < 100 && v907 <= 90
17.50/6.06	f_649(v891, v892, v893, v894, v895, v896, v897, 1, 2, 3, 4, 5, 6, 7, 8, 9, v909, v908, v907, v910, v911, v912, v913, v914, 0, 99, 90) -> f_652(v891, v892, v893, v894, v895, v896, v897, 1, 2, 3, 4, 5, 6, 7, 8, 9, v909, v908, v907, v910, v911, v912, v913, v914, 0, 99, 90) :|: 0 = 0
17.50/6.06	f_652(v891, v892, v893, v894, v895, v896, v897, 1, 2, 3, 4, 5, 6, 7, 8, 9, v909, v908, v907, v910, v911, v912, v913, v914, 0, 99, 90) -> f_655(v891, v892, v893, v894, v895, v896, v897, 1, 2, 3, 4, 5, 6, 7, 8, 9, v909, v908, v907, v910, v911, v912, v913, v914, 0, 99, 90) :|: TRUE
17.50/6.06	f_655(v891, v892, v893, v894, v895, v896, v897, 1, 2, 3, 4, 5, 6, 7, 8, 9, v909, v908, v907, v910, v911, v912, v913, v914, 0, 99, 90) -> f_658(v891, v892, v893, v894, v895, v896, v897, 1, 2, 3, 4, 5, 6, 7, 8, 9, v909, v910, v907, v908, v911, v912, v913, v914, 0, 99, 90) :|: 0 = 0
17.50/6.06	f_658(v891, v892, v893, v894, v895, v896, v897, 1, 2, 3, 4, 5, 6, 7, 8, 9, v909, v910, v907, v908, v911, v912, v913, v914, 0, 99, 90) -> f_662(v891, v892, v893, v894, v895, v896, v897, 1, 2, 3, 4, 5, 6, 7, 8, 9, v909, v910, v907, v908, v911, v912, v913, v914, 0, 99, 90) :|: 0 = 0
17.50/6.06	f_662(v891, v892, v893, v894, v895, v896, v897, 1, 2, 3, 4, 5, 6, 7, 8, 9, v909, v910, v907, v908, v911, v912, v913, v914, 0, 99, 90) -> f_665(v891, v892, v893, v894, v895, v896, v897, 1, 2, 3, 4, 5, 6, 7, 8, 9, v909, v910, v907, v908, v911, v912, v913, v914, 0, 99, 90) :|: 0 = 0
17.50/6.06	f_665(v891, v892, v893, v894, v895, v896, v897, 1, 2, 3, 4, 5, 6, 7, 8, 9, v909, v910, v907, v908, v911, v912, v913, v914, 0, 99, 90) -> f_668(v891, v892, v893, v894, v895, v896, v897, 1, 2, 3, 4, 5, 6, 7, 8, 9, v909, v910, v907, v908, v911, v912, v913, v914, 0, 99, 90) :|: TRUE
17.50/6.06	f_668(v891, v892, v893, v894, v895, v896, v897, 1, 2, 3, 4, 5, 6, 7, 8, 9, v909, v910, v907, v908, v911, v912, v913, v914, 0, 99, 90) -> f_671(v891, v892, v893, v894, v895, v896, v897, 1, 2, 3, 4, 5, 6, 7, 8, 9, v909, v910, v908, v911, v912, v913, v914, 0, 99, 90) :|: 0 = 0
17.50/6.06	f_671(v891, v892, v893, v894, v895, v896, v897, 1, 2, 3, 4, 5, 6, 7, 8, 9, v909, v910, v908, v911, v912, v913, v914, 0, 99, 90) -> f_673(v891, v892, v893, v894, v895, v896, v897, 1, 2, 3, 4, 5, 6, 7, 8, 9, v909, v910, v908, v911, v912, v913, v914, 0, 99, 90) :|: 0 = 0
17.50/6.06	f_673(v891, v892, v893, v894, v895, v896, v897, 1, 2, 3, 4, 5, 6, 7, 8, 9, v909, v910, v908, v911, v912, v913, v914, 0, 99, 90) -> f_675(v891, v892, v893, v894, v895, v896, v897, 1, 2, 3, 4, 5, 6, 7, 8, 9, v909, v910, v1268, v908, v911, v912, v913, v914, 0, 99, 90, 108) :|: v1268 = 9 + v909 && v1268 <= 108
17.50/6.06	f_675(v891, v892, v893, v894, v895, v896, v897, 1, 2, 3, 4, 5, 6, 7, 8, 9, v909, v910, v1268, v908, v911, v912, v913, v914, 0, 99, 90, 108) -> f_677(v891, v892, v893, v894, v895, v896, v897, 1, 2, 3, 4, 5, 6, 7, 8, 9, v909, v910, v1268, v908, v911, v912, v913, v914, 0, 99, 90, 108) :|: TRUE
17.50/6.06	f_677(v891, v892, v893, v894, v895, v896, v897, 1, 2, 3, 4, 5, 6, 7, 8, 9, v909, v910, v1268, v908, v911, v912, v913, v914, 0, 99, 90, 108) -> f_679(v891, v892, v893, v894, v895, v896, v897, 1, 2, 3, 4, 5, 6, 7, 8, 9, v909, v910, v1268, v911, v912, v913, v914, 0, 99, 90, 108) :|: 0 = 0
17.50/6.06	f_679(v891, v892, v893, v894, v895, v896, v897, 1, 2, 3, 4, 5, 6, 7, 8, 9, v909, v910, v1268, v911, v912, v913, v914, 0, 99, 90, 108) -> f_681(v891, v892, v893, v894, v895, v896, v897, 1, 2, 3, 4, 5, 6, 7, 8, 9, v909, v910, v1268, v911, v912, v913, v914, 0, 99, 90, 108) :|: 0 = 0
17.50/6.06	f_681(v891, v892, v893, v894, v895, v896, v897, 1, 2, 3, 4, 5, 6, 7, 8, 9, v909, v910, v1268, v911, v912, v913, v914, 0, 99, 90, 108) -> f_683(v891, v892, v893, v894, v895, v896, v897, 1, 2, 3, 4, 5, 6, 7, 8, 9, v909, v910, v1268, v1272, v911, v912, v913, v914, 0, 99, 90, 108, 81) :|: 9 + v1272 = v910 && v1272 <= 81
17.50/6.06	f_683(v891, v892, v893, v894, v895, v896, v897, 1, 2, 3, 4, 5, 6, 7, 8, 9, v909, v910, v1268, v1272, v911, v912, v913, v914, 0, 99, 90, 108, 81) -> f_685(v891, v892, v893, v894, v895, v896, v897, 1, 2, 3, 4, 5, 6, 7, 8, 9, v909, v910, v1268, v1272, v911, v912, v913, v914, 0, 99, 90, 108, 81) :|: TRUE
17.50/6.06	f_685(v891, v892, v893, v894, v895, v896, v897, 1, 2, 3, 4, 5, 6, 7, 8, 9, v909, v910, v1268, v1272, v911, v912, v913, v914, 0, 99, 90, 108, 81) -> f_687(v891, v892, v893, v894, v895, v896, v897, 1, 2, 3, 4, 5, 6, 7, 8, 9, v909, v910, v1268, v1272, v911, v912, v913, v914, 0, 99, 90, 108, 81) :|: TRUE
17.50/6.06	f_687(v891, v892, v893, v894, v895, v896, v897, 1, 2, 3, 4, 5, 6, 7, 8, 9, v909, v910, v1268, v1272, v911, v912, v913, v914, 0, 99, 90, 108, 81) -> f_644(v891, v892, v893, v894, v895, v896, v897, 1, 2, 3, 4, 5, 6, 7, 8, 9, v909, v910, v1268, v1272, v911, v912, v913, v914, 0, 99, 108, 90) :|: TRUE
17.50/6.06	f_644(v891, v892, v893, v894, v895, v896, v897, 1, 2, 3, 4, 5, 6, 7, 8, 9, v907, v908, v909, v910, v911, v912, v913, v914, 0, 99, 108, 90) -> f_647(v891, v892, v893, v894, v895, v896, v897, 1, 2, 3, 4, 5, 6, 7, 8, 9, v909, v908, v907, v910, v911, v912, v913, v914, 0, 99, 108, 90) :|: 0 = 0
17.50/6.06	Combined rules. Obtained 1 rulesP rules:
17.50/6.06	f_647(v891:0, v892:0, v893:0, v894:0, v895:0, v896:0, v897:0, 1, 2, 3, 4, 5, 6, 7, 8, 9, v909:0, v908:0, v907:0, 9 + v1272:0, v911:0, v912:0, v913:0, v914:0, 0, 99, 108, 90) -> f_647(v891:0, v892:0, v893:0, v894:0, v895:0, v896:0, v897:0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 9 + v909:0, 9 + v1272:0, v909:0, v1272:0, v911:0, v912:0, v913:0, v914:0, 0, 99, 108, 90) :|: v907:0 < 91 && v909:0 < 100 && v1272:0 < 82
17.50/6.06	Filtered unneeded arguments:
17.50/6.06	   f_647(x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, x16, x17, x18, x19, x20, x21, x22, x23, x24, x25, x26, x27, x28) -> f_647(x17, x19, x20)
17.50/6.06	Removed division, modulo operations, cleaned up constraints. Obtained 1 rules.P rules:
17.50/6.06	f_647(v909:0, v907:0, sum~cons_9~v1272:0) -> f_647(9 + v909:0, v909:0, v1272:0) :|: v909:0 < 100 && v1272:0 < 82 && v907:0 < 91 && sum~cons_9~v1272:0 = 9 + v1272:0
17.50/6.06	
17.50/6.06	----------------------------------------
17.50/6.06	
17.50/6.06	(16)
17.50/6.06	Obligation:
17.50/6.06	Rules:
17.50/6.06	f_647(v909:0, v907:0, sum~cons_9~v1272:0) -> f_647(9 + v909:0, v909:0, v1272:0) :|: v909:0 < 100 && v1272:0 < 82 && v907:0 < 91 && sum~cons_9~v1272:0 = 9 + v1272:0
17.50/6.06	
17.50/6.06	----------------------------------------
17.50/6.06	
17.50/6.06	(17) IntTRSCompressionProof (EQUIVALENT)
17.50/6.06	Compressed rules.
17.50/6.06	----------------------------------------
17.50/6.06	
17.50/6.06	(18)
17.50/6.06	Obligation:
17.50/6.06	Rules:
17.50/6.06	f_647(v909:0:0, v907:0:0, sum~cons_9~v1272:0:0) -> f_647(9 + v909:0:0, v909:0:0, v1272:0:0) :|: v909:0:0 < 100 && v1272:0:0 < 82 && v907:0:0 < 91 && sum~cons_9~v1272:0:0 = 9 + v1272:0:0
17.50/6.06	
17.50/6.06	----------------------------------------
17.50/6.06	
17.50/6.06	(19) RankingReductionPairProof (EQUIVALENT)
17.50/6.06	Interpretation:
17.50/6.06	[ f_647 ] = -1/9*f_647_1
17.50/6.06	
17.50/6.06	The following rules are decreasing:
17.50/6.06	f_647(v909:0:0, v907:0:0, sum~cons_9~v1272:0:0) -> f_647(9 + v909:0:0, v909:0:0, v1272:0:0) :|: v909:0:0 < 100 && v1272:0:0 < 82 && v907:0:0 < 91 && sum~cons_9~v1272:0:0 = 9 + v1272:0:0
17.50/6.06	
17.50/6.06	The following rules are bounded:
17.50/6.06	f_647(v909:0:0, v907:0:0, sum~cons_9~v1272:0:0) -> f_647(9 + v909:0:0, v909:0:0, v1272:0:0) :|: v909:0:0 < 100 && v1272:0:0 < 82 && v907:0:0 < 91 && sum~cons_9~v1272:0:0 = 9 + v1272:0:0
17.50/6.06	
17.50/6.06	
17.50/6.06	----------------------------------------
17.50/6.06	
17.50/6.06	(20)
17.50/6.06	YES
17.71/6.17	EOF