81.81/32.74	YES
81.81/32.75	proof of /export/starexec/sandbox/benchmark/theBenchmark.c
81.81/32.75	# AProVE Commit ID: 48fb2092695e11cc9f56e44b17a92a5f88ffb256 marcel 20180622 unpublished dirty
81.81/32.75	
81.81/32.75	
81.81/32.75	Termination of the given C Problem could be proven:
81.81/32.75	
81.81/32.75	(0) C Problem
81.81/32.75	(1) CToLLVMProof [EQUIVALENT, 130 ms]
81.81/32.75	(2) LLVM problem
81.81/32.75	(3) LLVMToTerminationGraphProof [EQUIVALENT, 24.2 s]
81.81/32.75	(4) LLVM Symbolic Execution Graph
81.81/32.75	(5) SymbolicExecutionGraphToSCCProof [SOUND, 0 ms]
81.81/32.75	(6) AND
81.81/32.75	    (7) LLVM Symbolic Execution SCC
81.81/32.75	        (8) SCC2IRS [SOUND, 113 ms]
81.81/32.75	        (9) IntTRS
81.81/32.75	        (10) IntTRSCompressionProof [EQUIVALENT, 0 ms]
81.81/32.75	        (11) IntTRS
81.81/32.75	        (12) RankingReductionPairProof [EQUIVALENT, 25 ms]
81.81/32.75	        (13) YES
81.81/32.75	    (14) LLVM Symbolic Execution SCC
81.81/32.75	        (15) SCC2IRS [SOUND, 93 ms]
81.81/32.75	        (16) IntTRS
81.81/32.75	        (17) IRS2T2 [EQUIVALENT, 0 ms]
81.81/32.75	        (18) T2IntSys
81.81/32.75	        (19) T2 [EQUIVALENT, 833 ms]
81.81/32.75	        (20) YES
81.81/32.75	    (21) LLVM Symbolic Execution SCC
81.81/32.75	        (22) SCC2IRS [SOUND, 45 ms]
81.81/32.75	        (23) IntTRS
81.81/32.75	        (24) IRS2T2 [EQUIVALENT, 0 ms]
81.81/32.75	        (25) T2IntSys
81.81/32.76	        (26) T2 [EQUIVALENT, 382 ms]
81.81/32.76	        (27) YES
81.81/32.76	    (28) LLVM Symbolic Execution SCC
81.81/32.76	        (29) SCC2IRS [SOUND, 49 ms]
81.81/32.76	        (30) IntTRS
81.81/32.76	        (31) IntTRSCompressionProof [EQUIVALENT, 0 ms]
81.81/32.76	        (32) IntTRS
81.81/32.76	        (33) RankingReductionPairProof [EQUIVALENT, 10 ms]
81.81/32.76	        (34) YES
81.81/32.76	
81.81/32.76	
81.81/32.76	----------------------------------------
81.81/32.76	
81.81/32.76	(0)
81.81/32.76	Obligation:
81.81/32.76	c file /export/starexec/sandbox/benchmark/theBenchmark.c
81.81/32.76	----------------------------------------
81.81/32.76	
81.81/32.76	(1) CToLLVMProof (EQUIVALENT)
81.81/32.76	Compiled c-file /export/starexec/sandbox/benchmark/theBenchmark.c to LLVM.
81.81/32.76	----------------------------------------
81.81/32.76	
81.81/32.76	(2)
81.81/32.76	Obligation:
81.81/32.76	LLVM Problem
81.81/32.76	
81.81/32.76	Aliases:
81.81/32.76	
81.81/32.76	Data layout:
81.81/32.76	
81.81/32.76	"e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
81.81/32.76	
81.81/32.76	Machine:
81.81/32.76	
81.81/32.76	"x86_64-pc-linux-gnu"
81.81/32.76	
81.81/32.76	Type definitions:
81.81/32.76	
81.81/32.76	Global variables:
81.81/32.76	
81.81/32.76	Function declarations and definitions:
81.81/32.76	
81.81/32.76	*BasicFunctionTypename: "__VERIFIER_nondet_int" returnParam: i32 parameters: () variableLength: false visibilityType: DEFAULT callingConvention: ccc
81.81/32.76	*BasicFunctionTypename: "cstrncpy" linkageType: EXTERNALLY_VISIBLE returnParam: *i8 parameters: (dst *i8, src *i8, n i64) variableLength: false visibilityType: DEFAULT callingConvention: ccc
81.81/32.76		0:
81.81/32.76			%1 = alloca *i8, align 8
81.81/32.76			%2 = alloca *i8, align 8
81.81/32.76			%3 = alloca i64, align 8
81.81/32.76			%d = alloca *i8, align 8
81.81/32.76			%s = alloca *i8, align 8
81.81/32.76			store %dst, %1
81.81/32.76			store %src, %2
81.81/32.76			store %n, %3
81.81/32.76			%4 = load %3
81.81/32.76			%5 = icmp ne %4 0
81.81/32.76			br %5, %6, %32
81.81/32.76		6:
81.81/32.76			%7 = load %1
81.81/32.76			store %7, %d
81.81/32.76			%8 = load %2
81.81/32.76			store %8, %s
81.81/32.76			br %9
81.81/32.76		9:
81.81/32.76			%10 = load %s
81.81/32.76			%11 = getelementptr %10, 1
81.81/32.76			store %11, %s
81.81/32.76			%12 = load %10
81.81/32.76			%13 = load %d
81.81/32.76			%14 = getelementptr %13, 1
81.81/32.76			store %14, %d
81.81/32.76			store %12, %13
81.81/32.76			%15 = sext i8 %12 to i32
81.81/32.76			%16 = icmp eq %15 0
81.81/32.76			br %16, %17, %26
81.81/32.76		17:
81.81/32.76			br %18
81.81/32.76		18:
81.81/32.76			%19 = load %3
81.81/32.76			%20 = add %19 -1
81.81/32.76			store %20, %3
81.81/32.76			%21 = icmp ne %20 0
81.81/32.76			br %21, %22, %25
81.81/32.76		22:
81.81/32.76			%23 = load %d
81.81/32.76			%24 = getelementptr %23, 1
81.81/32.76			store %24, %d
81.81/32.76			store 0, %23
81.81/32.76			br %18
81.81/32.76		25:
81.81/32.76			br %31
81.81/32.76		26:
81.81/32.76			br %27
81.81/32.76		27:
81.81/32.76			%28 = load %3
81.81/32.76			%29 = add %28 -1
81.81/32.76			store %29, %3
81.81/32.76			%30 = icmp ne %29 0
81.81/32.76			br %30, %9, %31
81.81/32.76		31:
81.81/32.76			br %32
81.81/32.76		32:
81.81/32.76			%33 = load %1
81.81/32.76			ret %33
81.81/32.76	
81.81/32.76	*BasicFunctionTypename: "main" linkageType: EXTERNALLY_VISIBLE returnParam: i32 parameters: () variableLength: false visibilityType: DEFAULT callingConvention: ccc
81.81/32.76		0:
81.81/32.76			%1 = alloca i32, align 4
81.81/32.76			%length = alloca i32, align 4
81.81/32.76			%n = alloca i32, align 4
81.81/32.76			%nondetArea = alloca *i8, align 8
81.81/32.76			%nondetString = alloca *i8, align 8
81.81/32.76			store 0, %1
81.81/32.76			%2 = call i32 @__VERIFIER_nondet_int()
81.81/32.76			store %2, %length
81.81/32.76			%3 = call i32 @__VERIFIER_nondet_int()
81.81/32.76			store %3, %n
81.81/32.76			%4 = load %length
81.81/32.76			%5 = icmp slt %4 1
81.81/32.76			br %5, %6, %7
81.81/32.76		6:
81.81/32.76			store 1, %length
81.81/32.76			br %7
81.81/32.76		7:
81.81/32.76			%8 = load %n
81.81/32.76			%9 = icmp slt %8 1
81.81/32.76			br %9, %10, %11
81.81/32.76		10:
81.81/32.76			store 1, %n
81.81/32.76			br %11
81.81/32.76		11:
81.81/32.76			%12 = load %n
81.81/32.76			%13 = sext i32 %12 to i64
81.81/32.76			%14 = mul %13 1
81.81/32.76			%15 = alloca i8, numElementsLit: %14
81.81/32.76			store %15, %nondetArea
81.81/32.76			%16 = load %length
81.81/32.76			%17 = sext i32 %16 to i64
81.81/32.76			%18 = mul %17 1
81.81/32.76			%19 = alloca i8, numElementsLit: %18
81.81/32.76			store %19, %nondetString
81.81/32.76			%20 = load %length
81.81/32.76			%21 = sub %20 1
81.81/32.76			%22 = sext i32 %21 to i64
81.81/32.76			%23 = load %nondetString
81.81/32.76			%24 = getelementptr %23, %22
81.81/32.76			store 0, %24
81.81/32.76			%25 = load %nondetArea
81.81/32.76			%26 = load %nondetString
81.81/32.76			%27 = load %n
81.81/32.76			%28 = sext i32 %27 to i64
81.81/32.76			%29 = call *i8 @cstrncpy(*i8 %25, *i8 %26, i64 %28)
81.81/32.76			ret 0
81.81/32.76	
81.81/32.76	
81.81/32.76	Analyze Termination of all function calls matching the pattern:
81.81/32.76	main()
81.81/32.76	----------------------------------------
81.81/32.76	
81.81/32.76	(3) LLVMToTerminationGraphProof (EQUIVALENT)
81.81/32.76	Constructed symbolic execution graph for LLVM program and proved memory safety.
81.81/32.76	----------------------------------------
81.81/32.76	
81.81/32.76	(4)
81.81/32.76	Obligation:
81.81/32.76	SE Graph
81.81/32.76	----------------------------------------
81.81/32.76	
81.81/32.76	(5) SymbolicExecutionGraphToSCCProof (SOUND)
81.81/32.76	Splitted symbolic execution graph to 4 SCCs.
81.81/32.76	----------------------------------------
81.81/32.76	
81.81/32.76	(6)
81.81/32.76	Complex Obligation (AND)
81.81/32.76	
81.81/32.76	----------------------------------------
81.81/32.76	
81.81/32.76	(7)
81.81/32.76	Obligation:
81.81/32.76	SCC
81.81/32.76	----------------------------------------
81.81/32.76	
81.81/32.76	(8) SCC2IRS (SOUND)
81.81/32.76	Transformed LLVM symbolic execution graph SCC into a rewrite problem. Log: 
81.81/32.76	Generated rules. Obtained 12 rulesP rules:
81.81/32.76	f_947(v4787, v4788, v4789, v4790, v4791, v4792, v4793, v4794, 1, v4796, v4797, 0, v4799, v4800, v4801, v4802, v4804, v4805, v4806, v4807, v4815, v4808, v4816, v4809, v4817, v4810, v4818, v4811, v4819, v4820, v4814, v4821, v4822, v4823, v4824, v4825, v4830, v4829, v4831, v4828, v4826, v4832, v4827, v4812, v4813, 3, 7, 2, 4, 8) -> f_948(v4787, v4788, v4789, v4790, v4791, v4792, v4793, v4794, 1, v4796, v4797, 0, v4799, v4800, v4801, v4802, v4804, v4849, v4805, v4806, v4807, v4815, v4808, v4816, v4809, v4817, v4810, v4818, v4811, v4819, v4820, v4814, v4821, v4822, v4823, v4824, v4825, v4830, v4829, v4831, v4828, v4826, v4832, v4827, v4812, v4813, 3, 7, 2, 4, 8) :|: 1 + v4849 = v4804 && 0 <= v4849
81.81/32.76	f_948(v4787, v4788, v4789, v4790, v4791, v4792, v4793, v4794, 1, v4796, v4797, 0, v4799, v4800, v4801, v4802, v4804, v4849, v4805, v4806, v4807, v4815, v4808, v4816, v4809, v4817, v4810, v4818, v4811, v4819, v4820, v4814, v4821, v4822, v4823, v4824, v4825, v4830, v4829, v4831, v4828, v4826, v4832, v4827, v4812, v4813, 3, 7, 2, 4, 8) -> f_949(v4787, v4788, v4789, v4790, v4791, v4792, v4793, v4794, 1, v4796, v4797, 0, v4799, v4800, v4801, v4802, v4804, v4849, v4805, v4806, v4807, v4815, v4808, v4816, v4809, v4817, v4810, v4818, v4811, v4819, v4820, v4814, v4821, v4822, v4823, v4824, v4825, v4830, v4829, v4831, v4828, v4826, v4832, v4827, v4812, v4813, 3, 7, 2, 4, 8) :|: TRUE
81.81/32.76	f_949(v4787, v4788, v4789, v4790, v4791, v4792, v4793, v4794, 1, v4796, v4797, 0, v4799, v4800, v4801, v4802, v4804, v4849, v4805, v4806, v4807, v4815, v4808, v4816, v4809, v4817, v4810, v4818, v4811, v4819, v4820, v4814, v4821, v4822, v4823, v4824, v4825, v4830, v4829, v4831, v4828, v4826, v4832, v4827, v4812, v4813, 3, 7, 2, 4, 8) -> f_950(v4787, v4788, v4789, v4790, v4791, v4792, v4793, v4794, 1, v4796, v4797, 0, v4799, v4800, v4801, v4802, v4804, v4849, v4805, v4806, v4807, v4815, v4808, v4816, v4809, v4817, v4810, v4818, v4811, v4819, v4820, v4814, v4821, v4822, v4823, v4824, v4825, v4830, v4829, v4831, v4828, v4826, v4832, v4827, v4812, v4813, 3, 7, 2, 4, 8) :|: v4849 != 0 && 2 <= v4804 && 4 <= v4801 && 3 <= v4802 && 4 <= v4820
81.81/32.76	f_950(v4787, v4788, v4789, v4790, v4791, v4792, v4793, v4794, 1, v4796, v4797, 0, v4799, v4800, v4801, v4802, v4804, v4849, v4805, v4806, v4807, v4815, v4808, v4816, v4809, v4817, v4810, v4818, v4811, v4819, v4820, v4814, v4821, v4822, v4823, v4824, v4825, v4830, v4829, v4831, v4828, v4826, v4832, v4827, v4812, v4813, 3, 7, 2, 4, 8) -> f_952(v4787, v4788, v4789, v4790, v4791, v4792, v4793, v4794, 1, v4796, v4797, 0, v4799, v4800, v4801, v4802, v4804, v4849, v4805, v4806, v4807, v4815, v4808, v4816, v4809, v4817, v4810, v4818, v4811, v4819, v4820, v4814, v4821, v4822, v4823, v4824, v4825, v4830, v4829, v4831, v4828, v4826, v4832, v4827, v4812, v4813, 3, 7, 2, 4, 8) :|: 0 = 0
81.81/32.76	f_952(v4787, v4788, v4789, v4790, v4791, v4792, v4793, v4794, 1, v4796, v4797, 0, v4799, v4800, v4801, v4802, v4804, v4849, v4805, v4806, v4807, v4815, v4808, v4816, v4809, v4817, v4810, v4818, v4811, v4819, v4820, v4814, v4821, v4822, v4823, v4824, v4825, v4830, v4829, v4831, v4828, v4826, v4832, v4827, v4812, v4813, 3, 7, 2, 4, 8) -> f_954(v4787, v4788, v4789, v4790, v4791, v4792, v4793, v4794, 1, v4796, v4797, 0, v4799, v4800, v4801, v4802, v4804, v4849, v4805, v4806, v4807, v4815, v4808, v4816, v4809, v4817, v4810, v4818, v4811, v4819, v4820, v4814, v4821, v4822, v4823, v4824, v4825, v4830, v4829, v4831, v4828, v4826, v4832, v4827, v4812, v4813, 3, 7, 2, 4, 8) :|: TRUE
81.81/32.76	f_954(v4787, v4788, v4789, v4790, v4791, v4792, v4793, v4794, 1, v4796, v4797, 0, v4799, v4800, v4801, v4802, v4804, v4849, v4805, v4806, v4807, v4815, v4808, v4816, v4809, v4817, v4810, v4818, v4811, v4819, v4820, v4814, v4821, v4822, v4823, v4824, v4825, v4830, v4829, v4831, v4828, v4826, v4832, v4827, v4812, v4813, 3, 7, 2, 4, 8) -> f_956(v4787, v4788, v4789, v4790, v4791, v4792, v4793, v4794, 1, v4796, v4797, 0, v4799, v4800, v4801, v4802, v4804, v4849, v4806, v4807, v4815, v4808, v4816, v4809, v4817, v4810, v4818, v4811, v4819, v4820, v4814, v4821, v4822, v4823, v4824, v4825, v4830, v4829, v4831, v4828, v4826, v4832, v4827, v4805, v4812, v4813, 3, 7, 2, 4, 8) :|: 0 = 0
81.81/32.76	f_956(v4787, v4788, v4789, v4790, v4791, v4792, v4793, v4794, 1, v4796, v4797, 0, v4799, v4800, v4801, v4802, v4804, v4849, v4806, v4807, v4815, v4808, v4816, v4809, v4817, v4810, v4818, v4811, v4819, v4820, v4814, v4821, v4822, v4823, v4824, v4825, v4830, v4829, v4831, v4828, v4826, v4832, v4827, v4805, v4812, v4813, 3, 7, 2, 4, 8) -> f_958(v4787, v4788, v4789, v4790, v4791, v4792, v4793, v4794, 1, v4796, v4797, 0, v4799, v4800, v4801, v4802, v4804, v4849, v4806, v5050, v4807, v4815, v4808, v4816, v4809, v4817, v4810, v4818, v4811, v4819, v4820, v4814, v4821, v4822, v4823, v4824, v4825, v4830, v4829, v4831, v4828, v4826, v4832, v4827, v4805, v4812, v4813, 3, 7, 2, 4, 8, 5) :|: v5050 = 1 + v4806 && 5 <= v5050
81.81/32.76	f_958(v4787, v4788, v4789, v4790, v4791, v4792, v4793, v4794, 1, v4796, v4797, 0, v4799, v4800, v4801, v4802, v4804, v4849, v4806, v5050, v4807, v4815, v4808, v4816, v4809, v4817, v4810, v4818, v4811, v4819, v4820, v4814, v4821, v4822, v4823, v4824, v4825, v4830, v4829, v4831, v4828, v4826, v4832, v4827, v4805, v4812, v4813, 3, 7, 2, 4, 8, 5) -> f_960(v4787, v4788, v4789, v4790, v4791, v4792, v4793, v4794, 1, v4796, v4797, 0, v4799, v4800, v4801, v4802, v4804, v4849, v4806, v5050, v4807, v4815, v4808, v4816, v4809, v4817, v4810, v4818, v4811, v4819, v4820, v4814, v4821, v4822, v4823, v4824, v4825, v4830, v4829, v4831, v4828, v4826, v4832, v4827, v4805, v4812, v4813, 3, 7, 2, 4, 8, 5) :|: TRUE
81.81/32.76	f_960(v4787, v4788, v4789, v4790, v4791, v4792, v4793, v4794, 1, v4796, v4797, 0, v4799, v4800, v4801, v4802, v4804, v4849, v4806, v5050, v4807, v4815, v4808, v4816, v4809, v4817, v4810, v4818, v4811, v4819, v4820, v4814, v4821, v4822, v4823, v4824, v4825, v4830, v4829, v4831, v4828, v4826, v4832, v4827, v4805, v4812, v4813, 3, 7, 2, 4, 8, 5) -> f_962(v4787, v4788, v4789, v4790, v4791, v4792, v4793, v4794, 1, v4796, v4797, 0, v4799, v4800, v4801, v4802, v4804, v4849, v4806, v5050, v4807, v4815, v4808, v4816, v4809, v4817, v4810, v4818, v4811, v4819, v4820, v4814, v4821, v4822, v4823, v4824, v4825, v4830, v4829, v4831, v4828, v4826, v4832, v4827, v4805, v4812, v4813, 3, 7, 2, 4, 8, 5) :|: TRUE
81.81/32.76	f_962(v4787, v4788, v4789, v4790, v4791, v4792, v4793, v4794, 1, v4796, v4797, 0, v4799, v4800, v4801, v4802, v4804, v4849, v4806, v5050, v4807, v4815, v4808, v4816, v4809, v4817, v4810, v4818, v4811, v4819, v4820, v4814, v4821, v4822, v4823, v4824, v4825, v4830, v4829, v4831, v4828, v4826, v4832, v4827, v4805, v4812, v4813, 3, 7, 2, 4, 8, 5) -> f_964(v4787, v4788, v4789, v4790, v4791, v4792, v4793, v4794, 1, v4796, v4797, 0, v4799, v4800, v4801, v4802, v4804, v4849, v4806, v5050, v4807, v4815, v4808, v4816, v4809, v4817, v4810, v4818, v4811, v4819, v4820, v4814, v4821, v4822, v4823, v4824, v4825, v4830, v4829, v4831, v4828, v4826, v4832, v4827, v4805, v4812, v4813, 3, 7, 2, 4, 8, 5) :|: TRUE
81.81/32.76	f_964(v4787, v4788, v4789, v4790, v4791, v4792, v4793, v4794, 1, v4796, v4797, 0, v4799, v4800, v4801, v4802, v4804, v4849, v4806, v5050, v4807, v4815, v4808, v4816, v4809, v4817, v4810, v4818, v4811, v4819, v4820, v4814, v4821, v4822, v4823, v4824, v4825, v4830, v4829, v4831, v4828, v4826, v4832, v4827, v4805, v4812, v4813, 3, 7, 2, 4, 8, 5) -> f_946(v4787, v4788, v4789, v4790, v4791, v4792, v4793, v4794, 1, v4796, v4797, 0, v4799, v4800, v4801, v4802, v4804, v4849, v4806, v5050, v4807, v4815, v4808, v4816, v4809, v4817, v4810, v4818, v4811, v4819, v4820, v4814, v4821, v4822, v4823, v4824, v4825, v4830, v4829, v4831, v4828, v4826, v4832, v4827, v4812, v4813, 3, 7, 2, 4, 8) :|: TRUE
81.81/32.76	f_946(v4787, v4788, v4789, v4790, v4791, v4792, v4793, v4794, 1, v4796, v4797, 0, v4799, v4800, v4801, v4802, v4803, v4804, v4805, v4806, v4807, v4815, v4808, v4816, v4809, v4817, v4810, v4818, v4811, v4819, v4820, v4814, v4821, v4822, v4823, v4824, v4825, v4830, v4829, v4831, v4828, v4826, v4832, v4827, v4812, v4813, 3, 7, 2, 4, 8) -> f_947(v4787, v4788, v4789, v4790, v4791, v4792, v4793, v4794, 1, v4796, v4797, 0, v4799, v4800, v4801, v4802, v4804, v4805, v4806, v4807, v4815, v4808, v4816, v4809, v4817, v4810, v4818, v4811, v4819, v4820, v4814, v4821, v4822, v4823, v4824, v4825, v4830, v4829, v4831, v4828, v4826, v4832, v4827, v4812, v4813, 3, 7, 2, 4, 8) :|: 0 = 0
81.81/32.76	Combined rules. Obtained 1 rulesP rules:
81.81/32.76	f_947(v4787:0, v4788:0, v4789:0, v4790:0, v4791:0, v4792:0, v4793:0, v4794:0, 1, v4796:0, v4797:0, 0, v4799:0, v4800:0, v4801:0, v4802:0, 1 + v4849:0, v4805:0, v4806:0, v4807:0, v4815:0, v4808:0, v4816:0, v4809:0, v4817:0, v4810:0, v4818:0, v4811:0, v4819:0, v4820:0, v4814:0, v4821:0, v4822:0, v4823:0, v4824:0, v4825:0, v4830:0, v4829:0, v4831:0, v4828:0, v4826:0, v4832:0, v4827:0, v4812:0, v4813:0, 3, 7, 2, 4, 8) -> f_947(v4787:0, v4788:0, v4789:0, v4790:0, v4791:0, v4792:0, v4793:0, v4794:0, 1, v4796:0, v4797:0, 0, v4799:0, v4800:0, v4801:0, v4802:0, v4849:0, v4806:0, 1 + v4806:0, v4807:0, v4815:0, v4808:0, v4816:0, v4809:0, v4817:0, v4810:0, v4818:0, v4811:0, v4819:0, v4820:0, v4814:0, v4821:0, v4822:0, v4823:0, v4824:0, v4825:0, v4830:0, v4829:0, v4831:0, v4828:0, v4826:0, v4832:0, v4827:0, v4812:0, v4813:0, 3, 7, 2, 4, 8) :|: v4849:0 > 0 && v4801:0 > 3 && v4802:0 > 2 && v4806:0 > 3 && v4820:0 > 3
81.81/32.76	Filtered unneeded arguments:
81.81/32.76	   f_947(x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, x16, x17, x18, x19, x20, x21, x22, x23, x24, x25, x26, x27, x28, x29, x30, x31, x32, x33, x34, x35, x36, x37, x38, x39, x40, x41, x42, x43, x44, x45, x46, x47, x48, x49, x50) -> f_947(x15, x16, x17, x19, x30)
81.81/32.76	Removed division, modulo operations, cleaned up constraints. Obtained 1 rules.P rules:
81.81/32.76	f_947(v4801:0, v4802:0, sum~cons_1~v4849:0, v4806:0, v4820:0) -> f_947(v4801:0, v4802:0, v4849:0, 1 + v4806:0, v4820:0) :|: v4801:0 > 3 && v4849:0 > 0 && v4802:0 > 2 && v4820:0 > 3 && v4806:0 > 3 && sum~cons_1~v4849:0 = 1 + v4849:0
81.81/32.76	
81.81/32.76	----------------------------------------
81.81/32.76	
81.81/32.76	(9)
81.81/32.76	Obligation:
81.81/32.76	Rules:
81.81/32.76	f_947(v4801:0, v4802:0, sum~cons_1~v4849:0, v4806:0, v4820:0) -> f_947(v4801:0, v4802:0, v4849:0, 1 + v4806:0, v4820:0) :|: v4801:0 > 3 && v4849:0 > 0 && v4802:0 > 2 && v4820:0 > 3 && v4806:0 > 3 && sum~cons_1~v4849:0 = 1 + v4849:0
81.81/32.76	
81.81/32.76	----------------------------------------
81.81/32.76	
81.81/32.76	(10) IntTRSCompressionProof (EQUIVALENT)
81.81/32.76	Compressed rules.
81.81/32.76	----------------------------------------
81.81/32.76	
81.81/32.76	(11)
81.81/32.76	Obligation:
81.81/32.76	Rules:
81.81/32.76	f_947(v4801:0:0, v4802:0:0, sum~cons_1~v4849:0:0, v4806:0:0, v4820:0:0) -> f_947(v4801:0:0, v4802:0:0, v4849:0:0, 1 + v4806:0:0, v4820:0:0) :|: v4820:0:0 > 3 && v4806:0:0 > 3 && v4802:0:0 > 2 && v4849:0:0 > 0 && v4801:0:0 > 3 && sum~cons_1~v4849:0:0 = 1 + v4849:0:0
81.81/32.76	
81.81/32.76	----------------------------------------
81.81/32.76	
81.81/32.76	(12) RankingReductionPairProof (EQUIVALENT)
81.81/32.76	Interpretation:
81.81/32.76	[ f_947 ] = f_947_3
81.81/32.76	
81.81/32.76	The following rules are decreasing:
81.81/32.76	f_947(v4801:0:0, v4802:0:0, sum~cons_1~v4849:0:0, v4806:0:0, v4820:0:0) -> f_947(v4801:0:0, v4802:0:0, v4849:0:0, 1 + v4806:0:0, v4820:0:0) :|: v4820:0:0 > 3 && v4806:0:0 > 3 && v4802:0:0 > 2 && v4849:0:0 > 0 && v4801:0:0 > 3 && sum~cons_1~v4849:0:0 = 1 + v4849:0:0
81.81/32.76	
81.81/32.76	The following rules are bounded:
81.81/32.76	f_947(v4801:0:0, v4802:0:0, sum~cons_1~v4849:0:0, v4806:0:0, v4820:0:0) -> f_947(v4801:0:0, v4802:0:0, v4849:0:0, 1 + v4806:0:0, v4820:0:0) :|: v4820:0:0 > 3 && v4806:0:0 > 3 && v4802:0:0 > 2 && v4849:0:0 > 0 && v4801:0:0 > 3 && sum~cons_1~v4849:0:0 = 1 + v4849:0:0
81.81/32.76	
81.81/32.76	
81.81/32.76	----------------------------------------
81.81/32.76	
81.81/32.76	(13)
81.81/32.76	YES
81.81/32.76	
81.81/32.76	----------------------------------------
81.81/32.76	
81.81/32.76	(14)
81.81/32.76	Obligation:
81.81/32.76	SCC
81.81/32.76	----------------------------------------
81.81/32.76	
81.81/32.76	(15) SCC2IRS (SOUND)
81.81/32.76	Transformed LLVM symbolic execution graph SCC into a rewrite problem. Log: 
81.81/32.76	Generated rules. Obtained 20 rulesP rules:
81.81/32.76	f_899(v4062, v4063, v4064, v4065, v4066, v4067, v4068, v4069, 1, v4072, v4073, v4074, v4075, 0, v4077, v4078, v4079, v4087, v4080, v4088, v4081, v4089, v4082, v4090, v4083, v4091, v4092, v4086, v4093, v4094, v4095, v4096, v4097, v4100, v4071, v4084, v4098, v4101, v4099, v4085, 3, 7, 2, 4, 8) -> f_900(v4062, v4063, v4064, v4065, v4066, v4067, v4068, v4069, 1, v4072, v4102, v4073, v4074, v4075, 0, v4077, v4078, v4079, v4087, v4080, v4088, v4081, v4089, v4082, v4090, v4083, v4091, v4092, v4086, v4093, v4094, v4095, v4096, v4097, v4100, v4071, v4084, v4098, v4101, v4099, v4085, 3, 7, 2, 4, 8) :|: v4102 = 1 + v4072 && 4 <= v4102
81.81/32.76	f_900(v4062, v4063, v4064, v4065, v4066, v4067, v4068, v4069, 1, v4072, v4102, v4073, v4074, v4075, 0, v4077, v4078, v4079, v4087, v4080, v4088, v4081, v4089, v4082, v4090, v4083, v4091, v4092, v4086, v4093, v4094, v4095, v4096, v4097, v4100, v4071, v4084, v4098, v4101, v4099, v4085, 3, 7, 2, 4, 8) -> f_901(v4062, v4063, v4064, v4065, v4066, v4067, v4068, v4069, 1, v4072, v4102, v4073, v4074, v4075, 0, v4077, v4078, v4079, v4087, v4080, v4088, v4081, v4089, v4082, v4090, v4083, v4091, v4092, v4086, v4093, v4094, v4095, v4096, v4097, v4100, v4071, v4084, v4098, v4101, v4099, v4085, 3, 7, 2, 4, 8) :|: TRUE
81.81/32.76	f_901(v4062, v4063, v4064, v4065, v4066, v4067, v4068, v4069, 1, v4072, v4102, v4073, v4074, v4075, 0, v4077, v4078, v4079, v4087, v4080, v4088, v4081, v4089, v4082, v4090, v4083, v4091, v4092, v4086, v4093, v4094, v4095, v4096, v4097, v4100, v4071, v4084, v4098, v4101, v4099, v4085, 3, 7, 2, 4, 8) -> f_902(v4062, v4063, v4064, v4065, v4066, v4067, v4068, v4069, 1, v4072, v4102, v4104, v4074, v4075, v4073, 0, v4077, v4078, v4079, v4087, v4080, v4088, v4081, v4089, v4082, v4090, v4083, v4091, v4092, v4086, v4093, v4094, v4095, v4096, v4097, v4100, v4071, v4084, v4098, v4101, v4099, v4085, 3, 7, 2, 4, 8) :|: TRUE
81.81/32.76	f_902(v4062, v4063, v4064, v4065, v4066, v4067, v4068, v4069, 1, v4072, v4102, v4104, v4074, v4075, v4073, 0, v4077, v4078, v4079, v4087, v4080, v4088, v4081, v4089, v4082, v4090, v4083, v4091, v4092, v4086, v4093, v4094, v4095, v4096, v4097, v4100, v4071, v4084, v4098, v4101, v4099, v4085, 3, 7, 2, 4, 8) -> f_903(v4062, v4063, v4064, v4065, v4066, v4067, v4068, v4069, 1, v4072, v4102, v4104, v4075, v4073, 0, v4077, v4078, v4079, v4087, v4080, v4088, v4081, v4089, v4082, v4090, v4083, v4091, v4092, v4086, v4093, v4094, v4095, v4096, v4097, v4100, v4071, v4074, v4084, v4098, v4101, v4099, v4085, 3, 7, 2, 4, 8) :|: 0 = 0
81.81/32.76	f_903(v4062, v4063, v4064, v4065, v4066, v4067, v4068, v4069, 1, v4072, v4102, v4104, v4075, v4073, 0, v4077, v4078, v4079, v4087, v4080, v4088, v4081, v4089, v4082, v4090, v4083, v4091, v4092, v4086, v4093, v4094, v4095, v4096, v4097, v4100, v4071, v4074, v4084, v4098, v4101, v4099, v4085, 3, 7, 2, 4, 8) -> f_904(v4062, v4063, v4064, v4065, v4066, v4067, v4068, v4069, 1, v4072, v4102, v4104, v4075, v4106, v4073, 0, v4077, v4078, v4079, v4087, v4080, v4088, v4081, v4089, v4082, v4090, v4083, v4091, v4092, v4086, v4093, v4094, v4095, v4096, v4097, v4100, v4071, v4074, v4084, v4098, v4101, v4099, v4085, 3, 7, 2, 4, 8) :|: v4106 = 1 + v4075 && 4 <= v4106
81.81/32.76	f_904(v4062, v4063, v4064, v4065, v4066, v4067, v4068, v4069, 1, v4072, v4102, v4104, v4075, v4106, v4073, 0, v4077, v4078, v4079, v4087, v4080, v4088, v4081, v4089, v4082, v4090, v4083, v4091, v4092, v4086, v4093, v4094, v4095, v4096, v4097, v4100, v4071, v4074, v4084, v4098, v4101, v4099, v4085, 3, 7, 2, 4, 8) -> f_905(v4062, v4063, v4064, v4065, v4066, v4067, v4068, v4069, 1, v4072, v4102, v4104, v4075, v4106, v4073, 0, v4077, v4078, v4079, v4087, v4080, v4088, v4081, v4089, v4082, v4090, v4083, v4091, v4092, v4086, v4093, v4094, v4095, v4096, v4097, v4100, v4071, v4074, v4084, v4098, v4101, v4099, v4085, 3, 7, 2, 4, 8) :|: TRUE
81.81/32.76	f_905(v4062, v4063, v4064, v4065, v4066, v4067, v4068, v4069, 1, v4072, v4102, v4104, v4075, v4106, v4073, 0, v4077, v4078, v4079, v4087, v4080, v4088, v4081, v4089, v4082, v4090, v4083, v4091, v4092, v4086, v4093, v4094, v4095, v4096, v4097, v4100, v4071, v4074, v4084, v4098, v4101, v4099, v4085, 3, 7, 2, 4, 8) -> f_906(v4062, v4063, v4064, v4065, v4066, v4067, v4068, v4069, 1, v4072, v4102, v4104, v4075, v4106, v4073, 0, v4077, v4078, v4079, v4087, v4080, v4088, v4081, v4089, v4082, v4090, v4083, v4091, v4092, v4086, v4093, v4094, v4095, v4096, v4097, v4100, v4071, v4074, v4084, v4098, v4101, v4099, v4085, 3, 7, 2, 4, 8) :|: TRUE
81.81/32.76	f_906(v4062, v4063, v4064, v4065, v4066, v4067, v4068, v4069, 1, v4072, v4102, v4104, v4075, v4106, v4073, 0, v4077, v4078, v4079, v4087, v4080, v4088, v4081, v4089, v4082, v4090, v4083, v4091, v4092, v4086, v4093, v4094, v4095, v4096, v4097, v4100, v4071, v4074, v4084, v4098, v4101, v4099, v4085, 3, 7, 2, 4, 8) -> f_907(v4062, v4063, v4064, v4065, v4066, v4067, v4068, v4069, 1, v4072, v4102, v4104, v4075, v4106, 0, v4077, v4078, v4079, v4087, v4080, v4088, v4081, v4089, v4082, v4090, v4083, v4091, v4092, v4086, v4093, v4094, v4095, v4096, v4097, v4100, v4071, v4073, v4074, v4084, v4098, v4101, v4099, v4085, 3, 7, 2, 4, 8) :|: 0 = 0
81.81/32.76	f_907(v4062, v4063, v4064, v4065, v4066, v4067, v4068, v4069, 1, v4072, v4102, v4104, v4075, v4106, 0, v4077, v4078, v4079, v4087, v4080, v4088, v4081, v4089, v4082, v4090, v4083, v4091, v4092, v4086, v4093, v4094, v4095, v4096, v4097, v4100, v4071, v4073, v4074, v4084, v4098, v4101, v4099, v4085, 3, 7, 2, 4, 8) -> f_909(v4062, v4063, v4064, v4065, v4066, v4067, v4068, v4069, 1, v4072, v4102, v4104, v4075, v4106, 0, v4077, v4078, v4079, v4087, v4080, v4088, v4081, v4089, v4082, v4090, v4083, v4091, v4092, v4086, v4093, v4094, v4095, v4096, v4097, v4100, v4071, v4073, v4074, v4084, v4098, v4101, v4099, v4085, 3, 7, 2, 4, 8) :|: v4104 != 0 && v4072 < v4086 && 4 <= v4086
81.81/32.76	f_909(v4062, v4063, v4064, v4065, v4066, v4067, v4068, v4069, 1, v4072, v4102, v4104, v4075, v4106, 0, v4077, v4078, v4079, v4087, v4080, v4088, v4081, v4089, v4082, v4090, v4083, v4091, v4092, v4086, v4093, v4094, v4095, v4096, v4097, v4100, v4071, v4073, v4074, v4084, v4098, v4101, v4099, v4085, 3, 7, 2, 4, 8) -> f_911(v4062, v4063, v4064, v4065, v4066, v4067, v4068, v4069, 1, v4072, v4102, v4104, v4075, v4106, 0, v4077, v4078, v4079, v4087, v4080, v4088, v4081, v4089, v4082, v4090, v4083, v4091, v4092, v4086, v4093, v4094, v4095, v4096, v4097, v4100, v4071, v4073, v4074, v4084, v4098, v4101, v4099, v4085, 3, 7, 2, 4, 8) :|: 0 = 0
81.81/32.76	f_911(v4062, v4063, v4064, v4065, v4066, v4067, v4068, v4069, 1, v4072, v4102, v4104, v4075, v4106, 0, v4077, v4078, v4079, v4087, v4080, v4088, v4081, v4089, v4082, v4090, v4083, v4091, v4092, v4086, v4093, v4094, v4095, v4096, v4097, v4100, v4071, v4073, v4074, v4084, v4098, v4101, v4099, v4085, 3, 7, 2, 4, 8) -> f_913(v4062, v4063, v4064, v4065, v4066, v4067, v4068, v4069, 1, v4072, v4102, v4104, v4075, v4106, 0, v4077, v4078, v4079, v4087, v4080, v4088, v4081, v4089, v4082, v4090, v4083, v4091, v4092, v4086, v4093, v4094, v4095, v4096, v4097, v4100, v4071, v4073, v4074, v4084, v4098, v4101, v4099, v4085, 3, 7, 2, 4, 8) :|: TRUE
81.81/32.76	f_913(v4062, v4063, v4064, v4065, v4066, v4067, v4068, v4069, 1, v4072, v4102, v4104, v4075, v4106, 0, v4077, v4078, v4079, v4087, v4080, v4088, v4081, v4089, v4082, v4090, v4083, v4091, v4092, v4086, v4093, v4094, v4095, v4096, v4097, v4100, v4071, v4073, v4074, v4084, v4098, v4101, v4099, v4085, 3, 7, 2, 4, 8) -> f_915(v4062, v4063, v4064, v4065, v4066, v4067, v4068, v4069, 1, v4072, v4102, v4104, v4075, v4106, 0, v4077, v4078, v4079, v4087, v4080, v4088, v4081, v4089, v4082, v4090, v4083, v4091, v4092, v4086, v4093, v4094, v4095, v4096, v4097, v4100, v4071, v4073, v4074, v4084, v4098, v4101, v4099, v4085, 3, 7, 2, 4, 8) :|: TRUE
81.81/32.76	f_915(v4062, v4063, v4064, v4065, v4066, v4067, v4068, v4069, 1, v4072, v4102, v4104, v4075, v4106, 0, v4077, v4078, v4079, v4087, v4080, v4088, v4081, v4089, v4082, v4090, v4083, v4091, v4092, v4086, v4093, v4094, v4095, v4096, v4097, v4100, v4071, v4073, v4074, v4084, v4098, v4101, v4099, v4085, 3, 7, 2, 4, 8) -> f_917(v4062, v4063, v4064, v4065, v4066, v4067, v4068, v4069, 1, v4072, v4102, v4104, v4075, v4106, 0, v4078, v4079, v4087, v4080, v4088, v4081, v4089, v4082, v4090, v4083, v4091, v4092, v4086, v4093, v4094, v4095, v4096, v4097, v4100, v4071, v4073, v4074, v4084, v4098, v4101, v4099, v4085, 3, 7, 2, 4, 8) :|: 0 = 0
81.81/32.76	f_917(v4062, v4063, v4064, v4065, v4066, v4067, v4068, v4069, 1, v4072, v4102, v4104, v4075, v4106, 0, v4078, v4079, v4087, v4080, v4088, v4081, v4089, v4082, v4090, v4083, v4091, v4092, v4086, v4093, v4094, v4095, v4096, v4097, v4100, v4071, v4073, v4074, v4084, v4098, v4101, v4099, v4085, 3, 7, 2, 4, 8) -> f_919(v4062, v4063, v4064, v4065, v4066, v4067, v4068, v4069, 1, v4072, v4102, v4104, v4075, v4106, 0, v4078, v4248, v4079, v4087, v4080, v4088, v4081, v4089, v4082, v4090, v4083, v4091, v4092, v4086, v4093, v4094, v4095, v4096, v4097, v4100, v4071, v4073, v4074, v4084, v4098, v4101, v4099, v4085, 3, 7, 2, 4, 8) :|: 1 + v4248 = v4078 && 0 <= v4248
81.81/32.76	f_919(v4062, v4063, v4064, v4065, v4066, v4067, v4068, v4069, 1, v4072, v4102, v4104, v4075, v4106, 0, v4078, v4248, v4079, v4087, v4080, v4088, v4081, v4089, v4082, v4090, v4083, v4091, v4092, v4086, v4093, v4094, v4095, v4096, v4097, v4100, v4071, v4073, v4074, v4084, v4098, v4101, v4099, v4085, 3, 7, 2, 4, 8) -> f_921(v4062, v4063, v4064, v4065, v4066, v4067, v4068, v4069, 1, v4072, v4102, v4104, v4075, v4106, 0, v4078, v4248, v4079, v4087, v4080, v4088, v4081, v4089, v4082, v4090, v4083, v4091, v4092, v4086, v4093, v4094, v4095, v4096, v4097, v4100, v4071, v4073, v4074, v4084, v4098, v4101, v4099, v4085, 3, 7, 2, 4, 8) :|: TRUE
81.81/32.76	f_921(v4062, v4063, v4064, v4065, v4066, v4067, v4068, v4069, 1, v4072, v4102, v4104, v4075, v4106, 0, v4078, v4248, v4079, v4087, v4080, v4088, v4081, v4089, v4082, v4090, v4083, v4091, v4092, v4086, v4093, v4094, v4095, v4096, v4097, v4100, v4071, v4073, v4074, v4084, v4098, v4101, v4099, v4085, 3, 7, 2, 4, 8) -> f_924(v4062, v4063, v4064, v4065, v4066, v4067, v4068, v4069, 1, v4072, v4102, v4104, v4075, v4106, 0, v4078, v4248, v4079, v4087, v4080, v4088, v4081, v4089, v4082, v4090, v4083, v4091, v4092, v4086, v4093, v4094, v4095, v4096, v4097, v4100, v4071, v4073, v4074, v4084, v4098, v4101, v4099, v4085, 3, 7, 2, 4, 8) :|: v4248 != 0 && 2 <= v4078 && 4 <= v4092
81.81/32.76	f_924(v4062, v4063, v4064, v4065, v4066, v4067, v4068, v4069, 1, v4072, v4102, v4104, v4075, v4106, 0, v4078, v4248, v4079, v4087, v4080, v4088, v4081, v4089, v4082, v4090, v4083, v4091, v4092, v4086, v4093, v4094, v4095, v4096, v4097, v4100, v4071, v4073, v4074, v4084, v4098, v4101, v4099, v4085, 3, 7, 2, 4, 8) -> f_928(v4062, v4063, v4064, v4065, v4066, v4067, v4068, v4069, 1, v4072, v4102, v4104, v4075, v4106, 0, v4078, v4248, v4079, v4087, v4080, v4088, v4081, v4089, v4082, v4090, v4083, v4091, v4092, v4086, v4093, v4094, v4095, v4096, v4097, v4100, v4071, v4073, v4074, v4084, v4098, v4101, v4099, v4085, 3, 7, 2, 4, 8) :|: 0 = 0
81.81/32.76	f_928(v4062, v4063, v4064, v4065, v4066, v4067, v4068, v4069, 1, v4072, v4102, v4104, v4075, v4106, 0, v4078, v4248, v4079, v4087, v4080, v4088, v4081, v4089, v4082, v4090, v4083, v4091, v4092, v4086, v4093, v4094, v4095, v4096, v4097, v4100, v4071, v4073, v4074, v4084, v4098, v4101, v4099, v4085, 3, 7, 2, 4, 8) -> f_932(v4062, v4063, v4064, v4065, v4066, v4067, v4068, v4069, 1, v4072, v4102, v4104, v4075, v4106, 0, v4078, v4248, v4079, v4087, v4080, v4088, v4081, v4089, v4082, v4090, v4083, v4091, v4092, v4086, v4093, v4094, v4095, v4096, v4097, v4100, v4071, v4073, v4074, v4084, v4098, v4101, v4099, v4085, 3, 7, 2, 4, 8) :|: TRUE
81.81/32.76	f_932(v4062, v4063, v4064, v4065, v4066, v4067, v4068, v4069, 1, v4072, v4102, v4104, v4075, v4106, 0, v4078, v4248, v4079, v4087, v4080, v4088, v4081, v4089, v4082, v4090, v4083, v4091, v4092, v4086, v4093, v4094, v4095, v4096, v4097, v4100, v4071, v4073, v4074, v4084, v4098, v4101, v4099, v4085, 3, 7, 2, 4, 8) -> f_898(v4062, v4063, v4064, v4065, v4066, v4067, v4068, v4069, 1, v4072, v4102, v4104, v4075, v4106, 0, v4078, v4248, v4079, v4087, v4080, v4088, v4081, v4089, v4082, v4090, v4083, v4091, v4092, v4086, v4093, v4094, v4095, v4096, v4097, v4100, v4084, v4098, v4101, v4099, v4085, 3, 7, 2, 4, 8) :|: TRUE
81.81/32.76	f_898(v4062, v4063, v4064, v4065, v4066, v4067, v4068, v4069, 1, v4071, v4072, v4073, v4074, v4075, 0, v4077, v4078, v4079, v4087, v4080, v4088, v4081, v4089, v4082, v4090, v4083, v4091, v4092, v4086, v4093, v4094, v4095, v4096, v4097, v4100, v4084, v4098, v4101, v4099, v4085, 3, 7, 2, 4, 8) -> f_899(v4062, v4063, v4064, v4065, v4066, v4067, v4068, v4069, 1, v4072, v4073, v4074, v4075, 0, v4077, v4078, v4079, v4087, v4080, v4088, v4081, v4089, v4082, v4090, v4083, v4091, v4092, v4086, v4093, v4094, v4095, v4096, v4097, v4100, v4071, v4084, v4098, v4101, v4099, v4085, 3, 7, 2, 4, 8) :|: 0 = 0
81.81/32.76	Combined rules. Obtained 2 rulesP rules:
81.81/32.76	f_899(v4062:0, v4063:0, v4064:0, v4065:0, v4066:0, v4067:0, v4068:0, v4069:0, 1, v4072:0, v4073:0, v4074:0, v4075:0, 0, v4077:0, 1 + v4248:0, v4079:0, v4087:0, v4080:0, v4088:0, v4081:0, v4089:0, v4082:0, v4090:0, v4083:0, v4091:0, v4092:0, v4086:0, v4093:0, v4094:0, v4095:0, v4096:0, v4097:0, v4100:0, v4071:0, v4084:0, v4098:0, v4101:0, v4099:0, v4085:0, 3, 7, 2, 4, 8) -> f_899(v4062:0, v4063:0, v4064:0, v4065:0, v4066:0, v4067:0, v4068:0, v4069:0, 1, 1 + v4072:0, v4104:0, v4075:0, 1 + v4075:0, 0, 1 + v4248:0, v4248:0, v4079:0, v4087:0, v4080:0, v4088:0, v4081:0, v4089:0, v4082:0, v4090:0, v4083:0, v4091:0, v4092:0, v4086:0, v4093:0, v4094:0, v4095:0, v4096:0, v4097:0, v4100:0, v4072:0, v4084:0, v4098:0, v4101:0, v4099:0, v4085:0, 3, 7, 2, 4, 8) :|: v4248:0 > 0 && v4072:0 > 2 && v4075:0 > 2 && v4086:0 > v4072:0 && v4104:0 < 0 && v4086:0 > 3 && v4092:0 > 3
81.81/32.76	f_899(v4062:0, v4063:0, v4064:0, v4065:0, v4066:0, v4067:0, v4068:0, v4069:0, 1, v4072:0, v4073:0, v4074:0, v4075:0, 0, v4077:0, 1 + v4248:0, v4079:0, v4087:0, v4080:0, v4088:0, v4081:0, v4089:0, v4082:0, v4090:0, v4083:0, v4091:0, v4092:0, v4086:0, v4093:0, v4094:0, v4095:0, v4096:0, v4097:0, v4100:0, v4071:0, v4084:0, v4098:0, v4101:0, v4099:0, v4085:0, 3, 7, 2, 4, 8) -> f_899(v4062:0, v4063:0, v4064:0, v4065:0, v4066:0, v4067:0, v4068:0, v4069:0, 1, 1 + v4072:0, v4104:0, v4075:0, 1 + v4075:0, 0, 1 + v4248:0, v4248:0, v4079:0, v4087:0, v4080:0, v4088:0, v4081:0, v4089:0, v4082:0, v4090:0, v4083:0, v4091:0, v4092:0, v4086:0, v4093:0, v4094:0, v4095:0, v4096:0, v4097:0, v4100:0, v4072:0, v4084:0, v4098:0, v4101:0, v4099:0, v4085:0, 3, 7, 2, 4, 8) :|: v4248:0 > 0 && v4072:0 > 2 && v4075:0 > 2 && v4086:0 > v4072:0 && v4104:0 > 0 && v4086:0 > 3 && v4092:0 > 3
81.81/32.76	Filtered unneeded arguments:
81.81/32.76	   f_899(x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, x16, x17, x18, x19, x20, x21, x22, x23, x24, x25, x26, x27, x28, x29, x30, x31, x32, x33, x34, x35, x36, x37, x38, x39, x40, x41, x42, x43, x44, x45) -> f_899(x10, x13, x16, x27, x28)
81.81/32.76	Removed division, modulo operations, cleaned up constraints. Obtained 1 rules.P rules:
81.81/32.76	f_899(v4072:0, v4075:0, sum~cons_1~v4248:0, v4092:0, v4086:0) -> f_899(1 + v4072:0, 1 + v4075:0, v4248:0, v4092:0, v4086:0) :|: v4072:0 > 2 && v4248:0 > 0 && v4075:0 > 2 && v4086:0 > v4072:0 && v4092:0 > 3 && v4086:0 > 3 && sum~cons_1~v4248:0 = 1 + v4248:0
81.81/32.76	
81.81/32.76	----------------------------------------
81.81/32.76	
81.81/32.76	(16)
81.81/32.76	Obligation:
81.81/32.76	Rules:
81.81/32.76	f_899(v4072:0, v4075:0, sum~cons_1~v4248:0, v4092:0, v4086:0) -> f_899(1 + v4072:0, 1 + v4075:0, v4248:0, v4092:0, v4086:0) :|: v4072:0 > 2 && v4248:0 > 0 && v4075:0 > 2 && v4086:0 > v4072:0 && v4092:0 > 3 && v4086:0 > 3 && sum~cons_1~v4248:0 = 1 + v4248:0
81.81/32.76	
81.81/32.76	----------------------------------------
81.81/32.76	
81.81/32.76	(17) IRS2T2 (EQUIVALENT)
81.81/32.76	Transformed input IRS into an integer transition system.Used the following mapping from defined symbols to location IDs:
81.81/32.76	
81.81/32.76	   (f_899_5,1)
81.81/32.76	
81.81/32.76	----------------------------------------
81.81/32.76	
81.81/32.76	(18)
81.81/32.76	Obligation:
81.81/32.76	START: 0;
81.81/32.76	
81.81/32.76	FROM: 0;
81.81/32.76	TO: 1;
81.81/32.76	
81.81/32.76	FROM: 1;
81.81/32.76	oldX0 := x0;
81.81/32.76	oldX1 := x1;
81.81/32.76	oldX2 := x2;
81.81/32.76	oldX3 := x3;
81.81/32.76	oldX4 := x4;
81.81/32.76	oldX5 := oldX2 - 1;
81.81/32.76	assume(oldX0 > 2 && oldX5 > 0 && oldX1 > 2 && oldX4 > oldX0 && oldX3 > 3 && oldX4 > 3 && oldX2 = 1 + oldX5);
81.81/32.76	x0 := 1 + oldX0;
81.81/32.76	x1 := 1 + oldX1;
81.81/32.76	x2 := oldX2 - 1;
81.81/32.76	x3 := oldX3;
81.81/32.76	x4 := oldX4;
81.81/32.76	TO: 1;
81.81/32.76	
81.81/32.76	
81.81/32.76	----------------------------------------
81.81/32.76	
81.81/32.76	(19) T2 (EQUIVALENT)
81.81/32.76	Initially, performed program simplifications using lexicographic rank functions:
81.81/32.76	 * Removed transitions 1, 3, 4 using the following rank functions:
81.81/32.76	    - Rank function 1:
81.81/32.76	      RF for loc. 5: 1-x0+x2+x4
81.81/32.76	      RF for loc. 6: -x0+x2+x4
81.81/32.76	      Bound for (chained) transitions 3: 3
81.81/32.76	    - Rank function 2:
81.81/32.76	      RF for loc. 5: 2*x2
81.81/32.76	      RF for loc. 6: -1+2*x2
81.81/32.76	      Bound for (chained) transitions 4: 3
81.81/32.76	    - Rank function 3:
81.81/32.76	      RF for loc. 5: 0
81.81/32.76	      RF for loc. 6: -1
81.81/32.76	      Bound for (chained) transitions 1: 0
81.81/32.76	
81.81/32.76	----------------------------------------
81.81/32.76	
81.81/32.76	(20)
81.81/32.76	YES
81.81/32.76	
81.81/32.76	----------------------------------------
81.81/32.76	
81.81/32.76	(21)
81.81/32.76	Obligation:
81.81/32.76	SCC
81.81/32.76	----------------------------------------
81.81/32.76	
81.81/32.76	(22) SCC2IRS (SOUND)
81.81/32.76	Transformed LLVM symbolic execution graph SCC into a rewrite problem. Log: 
81.81/32.76	Generated rules. Obtained 12 rulesP rules:
81.81/32.76	f_812(v2394, v2395, v2396, v2397, v2398, v2399, v2400, v2401, 1, v2403, 0, v2405, v2407, v2408, v2409, v2410, v2418, v2411, v2419, v2412, v2420, v2413, v2421, v2414, v2422, v2423, v2417, v2424, v2425, v2426, v2427, v2428, v2415, v2429, v2416, 3, 7, 2, 4, 8) -> f_816(v2394, v2395, v2396, v2397, v2398, v2399, v2400, v2401, 1, v2403, 0, v2405, v2407, v2805, v2408, v2409, v2410, v2418, v2411, v2419, v2412, v2420, v2413, v2421, v2414, v2422, v2423, v2417, v2424, v2425, v2426, v2427, v2428, v2415, v2429, v2416, 3, 7, 2, 4, 8) :|: 1 + v2805 = v2407 && 0 <= v2805
81.81/32.76	f_816(v2394, v2395, v2396, v2397, v2398, v2399, v2400, v2401, 1, v2403, 0, v2405, v2407, v2805, v2408, v2409, v2410, v2418, v2411, v2419, v2412, v2420, v2413, v2421, v2414, v2422, v2423, v2417, v2424, v2425, v2426, v2427, v2428, v2415, v2429, v2416, 3, 7, 2, 4, 8) -> f_820(v2394, v2395, v2396, v2397, v2398, v2399, v2400, v2401, 1, v2403, 0, v2405, v2407, v2805, v2408, v2409, v2410, v2418, v2411, v2419, v2412, v2420, v2413, v2421, v2414, v2422, v2423, v2417, v2424, v2425, v2426, v2427, v2428, v2415, v2429, v2416, 3, 7, 2, 4, 8) :|: TRUE
81.81/32.76	f_820(v2394, v2395, v2396, v2397, v2398, v2399, v2400, v2401, 1, v2403, 0, v2405, v2407, v2805, v2408, v2409, v2410, v2418, v2411, v2419, v2412, v2420, v2413, v2421, v2414, v2422, v2423, v2417, v2424, v2425, v2426, v2427, v2428, v2415, v2429, v2416, 3, 7, 2, 4, 8) -> f_824(v2394, v2395, v2396, v2397, v2398, v2399, v2400, v2401, 1, v2403, 0, v2405, v2407, v2805, v2408, v2409, v2410, v2418, v2411, v2419, v2412, v2420, v2413, v2421, v2414, v2422, v2423, v2417, v2424, v2425, v2426, v2427, v2428, v2415, v2429, v2416, 3, 7, 2, 4, 8) :|: v2805 != 0 && 2 <= v2407 && 4 <= v2423
81.81/32.76	f_824(v2394, v2395, v2396, v2397, v2398, v2399, v2400, v2401, 1, v2403, 0, v2405, v2407, v2805, v2408, v2409, v2410, v2418, v2411, v2419, v2412, v2420, v2413, v2421, v2414, v2422, v2423, v2417, v2424, v2425, v2426, v2427, v2428, v2415, v2429, v2416, 3, 7, 2, 4, 8) -> f_829(v2394, v2395, v2396, v2397, v2398, v2399, v2400, v2401, 1, v2403, 0, v2405, v2407, v2805, v2408, v2409, v2410, v2418, v2411, v2419, v2412, v2420, v2413, v2421, v2414, v2422, v2423, v2417, v2424, v2425, v2426, v2427, v2428, v2415, v2429, v2416, 3, 7, 2, 4, 8) :|: 0 = 0
81.81/32.76	f_829(v2394, v2395, v2396, v2397, v2398, v2399, v2400, v2401, 1, v2403, 0, v2405, v2407, v2805, v2408, v2409, v2410, v2418, v2411, v2419, v2412, v2420, v2413, v2421, v2414, v2422, v2423, v2417, v2424, v2425, v2426, v2427, v2428, v2415, v2429, v2416, 3, 7, 2, 4, 8) -> f_834(v2394, v2395, v2396, v2397, v2398, v2399, v2400, v2401, 1, v2403, 0, v2405, v2407, v2805, v2408, v2409, v2410, v2418, v2411, v2419, v2412, v2420, v2413, v2421, v2414, v2422, v2423, v2417, v2424, v2425, v2426, v2427, v2428, v2415, v2429, v2416, 3, 7, 2, 4, 8) :|: TRUE
81.81/32.76	f_834(v2394, v2395, v2396, v2397, v2398, v2399, v2400, v2401, 1, v2403, 0, v2405, v2407, v2805, v2408, v2409, v2410, v2418, v2411, v2419, v2412, v2420, v2413, v2421, v2414, v2422, v2423, v2417, v2424, v2425, v2426, v2427, v2428, v2415, v2429, v2416, 3, 7, 2, 4, 8) -> f_839(v2394, v2395, v2396, v2397, v2398, v2399, v2400, v2401, 1, v2403, 0, v2405, v2407, v2805, v2409, v2410, v2418, v2411, v2419, v2412, v2420, v2413, v2421, v2414, v2422, v2423, v2417, v2424, v2425, v2426, v2427, v2428, v2408, v2415, v2429, v2416, 3, 7, 2, 4, 8) :|: 0 = 0
81.81/32.76	f_839(v2394, v2395, v2396, v2397, v2398, v2399, v2400, v2401, 1, v2403, 0, v2405, v2407, v2805, v2409, v2410, v2418, v2411, v2419, v2412, v2420, v2413, v2421, v2414, v2422, v2423, v2417, v2424, v2425, v2426, v2427, v2428, v2408, v2415, v2429, v2416, 3, 7, 2, 4, 8) -> f_844(v2394, v2395, v2396, v2397, v2398, v2399, v2400, v2401, 1, v2403, 0, v2405, v2407, v2805, v2409, v3061, v2410, v2418, v2411, v2419, v2412, v2420, v2413, v2421, v2414, v2422, v2423, v2417, v2424, v2425, v2426, v2427, v2428, v2408, v2415, v2429, v2416, 3, 7, 2, 4, 8, 5) :|: v3061 = 1 + v2409 && 5 <= v3061
81.81/32.76	f_844(v2394, v2395, v2396, v2397, v2398, v2399, v2400, v2401, 1, v2403, 0, v2405, v2407, v2805, v2409, v3061, v2410, v2418, v2411, v2419, v2412, v2420, v2413, v2421, v2414, v2422, v2423, v2417, v2424, v2425, v2426, v2427, v2428, v2408, v2415, v2429, v2416, 3, 7, 2, 4, 8, 5) -> f_849(v2394, v2395, v2396, v2397, v2398, v2399, v2400, v2401, 1, v2403, 0, v2405, v2407, v2805, v2409, v3061, v2410, v2418, v2411, v2419, v2412, v2420, v2413, v2421, v2414, v2422, v2423, v2417, v2424, v2425, v2426, v2427, v2428, v2408, v2415, v2429, v2416, 3, 7, 2, 4, 8, 5) :|: TRUE
81.81/32.76	f_849(v2394, v2395, v2396, v2397, v2398, v2399, v2400, v2401, 1, v2403, 0, v2405, v2407, v2805, v2409, v3061, v2410, v2418, v2411, v2419, v2412, v2420, v2413, v2421, v2414, v2422, v2423, v2417, v2424, v2425, v2426, v2427, v2428, v2408, v2415, v2429, v2416, 3, 7, 2, 4, 8, 5) -> f_853(v2394, v2395, v2396, v2397, v2398, v2399, v2400, v2401, 1, v2403, 0, v2405, v2407, v2805, v2409, v3061, v2410, v2418, v2411, v2419, v2412, v2420, v2413, v2421, v2414, v2422, v2423, v2417, v2424, v2425, v2426, v2427, v2428, v2408, v2415, v2429, v2416, 3, 7, 2, 4, 8, 5) :|: TRUE
81.81/32.76	f_853(v2394, v2395, v2396, v2397, v2398, v2399, v2400, v2401, 1, v2403, 0, v2405, v2407, v2805, v2409, v3061, v2410, v2418, v2411, v2419, v2412, v2420, v2413, v2421, v2414, v2422, v2423, v2417, v2424, v2425, v2426, v2427, v2428, v2408, v2415, v2429, v2416, 3, 7, 2, 4, 8, 5) -> f_858(v2394, v2395, v2396, v2397, v2398, v2399, v2400, v2401, 1, v2403, 0, v2405, v2407, v2805, v2409, v3061, v2410, v2418, v2411, v2419, v2412, v2420, v2413, v2421, v2414, v2422, v2423, v2417, v2424, v2425, v2426, v2427, v2428, v2408, v2415, v2429, v2416, 3, 7, 2, 4, 8, 5) :|: TRUE
81.81/32.76	f_858(v2394, v2395, v2396, v2397, v2398, v2399, v2400, v2401, 1, v2403, 0, v2405, v2407, v2805, v2409, v3061, v2410, v2418, v2411, v2419, v2412, v2420, v2413, v2421, v2414, v2422, v2423, v2417, v2424, v2425, v2426, v2427, v2428, v2408, v2415, v2429, v2416, 3, 7, 2, 4, 8, 5) -> f_805(v2394, v2395, v2396, v2397, v2398, v2399, v2400, v2401, 1, v2403, 0, v2405, v2407, v2805, v2409, v3061, v2410, v2418, v2411, v2419, v2412, v2420, v2413, v2421, v2414, v2422, v2423, v2417, v2424, v2425, v2426, v2427, v2428, v2415, v2429, v2416, 3, 7, 2, 4, 8) :|: TRUE
81.81/32.76	f_805(v2394, v2395, v2396, v2397, v2398, v2399, v2400, v2401, 1, v2403, 0, v2405, v2406, v2407, v2408, v2409, v2410, v2418, v2411, v2419, v2412, v2420, v2413, v2421, v2414, v2422, v2423, v2417, v2424, v2425, v2426, v2427, v2428, v2415, v2429, v2416, 3, 7, 2, 4, 8) -> f_812(v2394, v2395, v2396, v2397, v2398, v2399, v2400, v2401, 1, v2403, 0, v2405, v2407, v2408, v2409, v2410, v2418, v2411, v2419, v2412, v2420, v2413, v2421, v2414, v2422, v2423, v2417, v2424, v2425, v2426, v2427, v2428, v2415, v2429, v2416, 3, 7, 2, 4, 8) :|: 0 = 0
81.81/32.76	Combined rules. Obtained 1 rulesP rules:
81.81/32.76	f_812(v2394:0, v2395:0, v2396:0, v2397:0, v2398:0, v2399:0, v2400:0, v2401:0, 1, v2403:0, 0, v2405:0, 1 + v2805:0, v2408:0, v2409:0, v2410:0, v2418:0, v2411:0, v2419:0, v2412:0, v2420:0, v2413:0, v2421:0, v2414:0, v2422:0, v2423:0, v2417:0, v2424:0, v2425:0, v2426:0, v2427:0, v2428:0, v2415:0, v2429:0, v2416:0, 3, 7, 2, 4, 8) -> f_812(v2394:0, v2395:0, v2396:0, v2397:0, v2398:0, v2399:0, v2400:0, v2401:0, 1, v2403:0, 0, v2405:0, v2805:0, v2409:0, 1 + v2409:0, v2410:0, v2418:0, v2411:0, v2419:0, v2412:0, v2420:0, v2413:0, v2421:0, v2414:0, v2422:0, v2423:0, v2417:0, v2424:0, v2425:0, v2426:0, v2427:0, v2428:0, v2415:0, v2429:0, v2416:0, 3, 7, 2, 4, 8) :|: v2805:0 > 0 && v2409:0 > 3 && v2423:0 > 3
81.81/32.76	Filtered unneeded arguments:
81.81/32.76	   f_812(x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, x16, x17, x18, x19, x20, x21, x22, x23, x24, x25, x26, x27, x28, x29, x30, x31, x32, x33, x34, x35, x36, x37, x38, x39, x40) -> f_812(x13, x15, x26)
81.81/32.76	Removed division, modulo operations, cleaned up constraints. Obtained 1 rules.P rules:
81.81/32.76	f_812(sum~cons_1~v2805:0, v2409:0, v2423:0) -> f_812(v2805:0, 1 + v2409:0, v2423:0) :|: v2409:0 > 3 && v2423:0 > 3 && v2805:0 > 0 && sum~cons_1~v2805:0 = 1 + v2805:0
81.81/32.76	
81.81/32.76	----------------------------------------
81.81/32.76	
81.81/32.76	(23)
81.81/32.76	Obligation:
81.81/32.76	Rules:
81.81/32.76	f_812(sum~cons_1~v2805:0, v2409:0, v2423:0) -> f_812(v2805:0, 1 + v2409:0, v2423:0) :|: v2409:0 > 3 && v2423:0 > 3 && v2805:0 > 0 && sum~cons_1~v2805:0 = 1 + v2805:0
81.81/32.76	
81.81/32.76	----------------------------------------
81.81/32.76	
81.81/32.76	(24) IRS2T2 (EQUIVALENT)
81.81/32.76	Transformed input IRS into an integer transition system.Used the following mapping from defined symbols to location IDs:
81.81/32.76	
81.81/32.76	   (f_812_3,1)
81.81/32.76	
81.81/32.76	----------------------------------------
81.81/32.76	
81.81/32.76	(25)
81.81/32.76	Obligation:
81.81/32.76	START: 0;
81.81/32.76	
81.81/32.76	FROM: 0;
81.81/32.76	TO: 1;
81.81/32.76	
81.81/32.76	FROM: 1;
81.81/32.76	oldX0 := x0;
81.81/32.76	oldX1 := x1;
81.81/32.76	oldX2 := x2;
81.81/32.76	oldX3 := oldX0 - 1;
81.81/32.76	assume(oldX1 > 3 && oldX2 > 3 && oldX3 > 0 && oldX0 = 1 + oldX3);
81.81/32.76	x0 := oldX0 - 1;
81.81/32.76	x1 := 1 + oldX1;
81.81/32.76	x2 := oldX2;
81.81/32.76	TO: 1;
81.81/32.76	
81.81/32.76	
81.81/32.76	----------------------------------------
81.81/32.76	
81.81/32.76	(26) T2 (EQUIVALENT)
81.81/32.76	Initially, performed program simplifications using lexicographic rank functions:
81.81/32.76	 * Removed transitions 1, 3, 4 using the following rank functions:
81.81/32.76	    - Rank function 1:
81.81/32.76	      RF for loc. 5: 1+2*x0
81.81/32.76	      RF for loc. 6: 2*x0
81.81/32.76	      Bound for (chained) transitions 4: 4
81.81/32.76	    - Rank function 2:
81.81/32.76	      RF for loc. 5: 1+2*x0
81.81/32.76	      RF for loc. 6: 2*x0
81.81/32.76	      Bound for (chained) transitions 3: 4
81.81/32.76	    - Rank function 3:
81.81/32.76	      RF for loc. 5: 1
81.81/32.76	      RF for loc. 6: 0
81.81/32.76	      Bound for (chained) transitions 1: 1
81.81/32.76	
81.81/32.76	----------------------------------------
81.81/32.76	
81.81/32.76	(27)
81.81/32.76	YES
81.81/32.76	
81.81/32.76	----------------------------------------
81.81/32.76	
81.81/32.76	(28)
81.81/32.76	Obligation:
81.81/32.76	SCC
81.81/32.76	----------------------------------------
81.81/32.76	
81.81/32.76	(29) SCC2IRS (SOUND)
81.81/32.76	Transformed LLVM symbolic execution graph SCC into a rewrite problem. Log: 
81.81/32.76	Generated rules. Obtained 12 rulesP rules:
81.81/32.76	f_733(v1652, v1653, v1654, v1655, v1656, v1657, v1658, v1659, 1, v1661, 0, v1663, v1665, v1666, v1667, v1668, v1674, v1669, v1675, v1670, v1676, v1671, v1677, v1672, v1678, v1679, v1680, v1681, v1682, v1683, v1684, v1673, 3, 7, 2, 4, 8) -> f_739(v1652, v1653, v1654, v1655, v1656, v1657, v1658, v1659, 1, v1661, 0, v1663, v1665, v1724, v1666, v1667, v1668, v1674, v1669, v1675, v1670, v1676, v1671, v1677, v1672, v1678, v1679, v1680, v1681, v1682, v1683, v1684, v1673, 3, 7, 2, 4, 8) :|: 1 + v1724 = v1665 && 0 <= v1724
81.81/32.76	f_739(v1652, v1653, v1654, v1655, v1656, v1657, v1658, v1659, 1, v1661, 0, v1663, v1665, v1724, v1666, v1667, v1668, v1674, v1669, v1675, v1670, v1676, v1671, v1677, v1672, v1678, v1679, v1680, v1681, v1682, v1683, v1684, v1673, 3, 7, 2, 4, 8) -> f_745(v1652, v1653, v1654, v1655, v1656, v1657, v1658, v1659, 1, v1661, 0, v1663, v1665, v1724, v1666, v1667, v1668, v1674, v1669, v1675, v1670, v1676, v1671, v1677, v1672, v1678, v1679, v1680, v1681, v1682, v1683, v1684, v1673, 3, 7, 2, 4, 8) :|: TRUE
81.81/32.76	f_745(v1652, v1653, v1654, v1655, v1656, v1657, v1658, v1659, 1, v1661, 0, v1663, v1665, v1724, v1666, v1667, v1668, v1674, v1669, v1675, v1670, v1676, v1671, v1677, v1672, v1678, v1679, v1680, v1681, v1682, v1683, v1684, v1673, 3, 7, 2, 4, 8) -> f_752(v1652, v1653, v1654, v1655, v1656, v1657, v1658, v1659, 1, v1661, 0, v1663, v1665, v1724, v1666, v1667, v1668, v1674, v1669, v1675, v1670, v1676, v1671, v1677, v1672, v1678, v1679, v1680, v1681, v1682, v1683, v1684, v1673, 3, 7, 2, 4, 8) :|: v1724 != 0 && 2 <= v1665 && 3 <= v1679 && 3 <= v1654
81.81/32.76	f_752(v1652, v1653, v1654, v1655, v1656, v1657, v1658, v1659, 1, v1661, 0, v1663, v1665, v1724, v1666, v1667, v1668, v1674, v1669, v1675, v1670, v1676, v1671, v1677, v1672, v1678, v1679, v1680, v1681, v1682, v1683, v1684, v1673, 3, 7, 2, 4, 8) -> f_760(v1652, v1653, v1654, v1655, v1656, v1657, v1658, v1659, 1, v1661, 0, v1663, v1665, v1724, v1666, v1667, v1668, v1674, v1669, v1675, v1670, v1676, v1671, v1677, v1672, v1678, v1679, v1680, v1681, v1682, v1683, v1684, v1673, 3, 7, 2, 4, 8) :|: 0 = 0
81.81/32.76	f_760(v1652, v1653, v1654, v1655, v1656, v1657, v1658, v1659, 1, v1661, 0, v1663, v1665, v1724, v1666, v1667, v1668, v1674, v1669, v1675, v1670, v1676, v1671, v1677, v1672, v1678, v1679, v1680, v1681, v1682, v1683, v1684, v1673, 3, 7, 2, 4, 8) -> f_768(v1652, v1653, v1654, v1655, v1656, v1657, v1658, v1659, 1, v1661, 0, v1663, v1665, v1724, v1666, v1667, v1668, v1674, v1669, v1675, v1670, v1676, v1671, v1677, v1672, v1678, v1679, v1680, v1681, v1682, v1683, v1684, v1673, 3, 7, 2, 4, 8) :|: TRUE
81.81/32.76	f_768(v1652, v1653, v1654, v1655, v1656, v1657, v1658, v1659, 1, v1661, 0, v1663, v1665, v1724, v1666, v1667, v1668, v1674, v1669, v1675, v1670, v1676, v1671, v1677, v1672, v1678, v1679, v1680, v1681, v1682, v1683, v1684, v1673, 3, 7, 2, 4, 8) -> f_776(v1652, v1653, v1654, v1655, v1656, v1657, v1658, v1659, 1, v1661, 0, v1663, v1665, v1724, v1667, v1668, v1674, v1669, v1675, v1670, v1676, v1671, v1677, v1672, v1678, v1679, v1680, v1681, v1682, v1683, v1684, v1666, v1673, 3, 7, 2, 4, 8) :|: 0 = 0
81.81/32.76	f_776(v1652, v1653, v1654, v1655, v1656, v1657, v1658, v1659, 1, v1661, 0, v1663, v1665, v1724, v1667, v1668, v1674, v1669, v1675, v1670, v1676, v1671, v1677, v1672, v1678, v1679, v1680, v1681, v1682, v1683, v1684, v1666, v1673, 3, 7, 2, 4, 8) -> f_784(v1652, v1653, v1654, v1655, v1656, v1657, v1658, v1659, 1, v1661, 0, v1663, v1665, v1724, v1667, v2285, v1668, v1674, v1669, v1675, v1670, v1676, v1671, v1677, v1672, v1678, v1679, v1680, v1681, v1682, v1683, v1684, v1666, v1673, 3, 7, 2, 4, 8) :|: v2285 = 1 + v1667 && 4 <= v2285
81.81/32.76	f_784(v1652, v1653, v1654, v1655, v1656, v1657, v1658, v1659, 1, v1661, 0, v1663, v1665, v1724, v1667, v2285, v1668, v1674, v1669, v1675, v1670, v1676, v1671, v1677, v1672, v1678, v1679, v1680, v1681, v1682, v1683, v1684, v1666, v1673, 3, 7, 2, 4, 8) -> f_793(v1652, v1653, v1654, v1655, v1656, v1657, v1658, v1659, 1, v1661, 0, v1663, v1665, v1724, v1667, v2285, v1668, v1674, v1669, v1675, v1670, v1676, v1671, v1677, v1672, v1678, v1679, v1680, v1681, v1682, v1683, v1684, v1666, v1673, 3, 7, 2, 4, 8) :|: TRUE
81.81/32.76	f_793(v1652, v1653, v1654, v1655, v1656, v1657, v1658, v1659, 1, v1661, 0, v1663, v1665, v1724, v1667, v2285, v1668, v1674, v1669, v1675, v1670, v1676, v1671, v1677, v1672, v1678, v1679, v1680, v1681, v1682, v1683, v1684, v1666, v1673, 3, 7, 2, 4, 8) -> f_802(v1652, v1653, v1654, v1655, v1656, v1657, v1658, v1659, 1, v1661, 0, v1663, v1665, v1724, v1667, v2285, v1668, v1674, v1669, v1675, v1670, v1676, v1671, v1677, v1672, v1678, v1679, v1680, v1681, v1682, v1683, v1684, v1666, v1673, 3, 7, 2, 4, 8) :|: TRUE
81.81/32.76	f_802(v1652, v1653, v1654, v1655, v1656, v1657, v1658, v1659, 1, v1661, 0, v1663, v1665, v1724, v1667, v2285, v1668, v1674, v1669, v1675, v1670, v1676, v1671, v1677, v1672, v1678, v1679, v1680, v1681, v1682, v1683, v1684, v1666, v1673, 3, 7, 2, 4, 8) -> f_811(v1652, v1653, v1654, v1655, v1656, v1657, v1658, v1659, 1, v1661, 0, v1663, v1665, v1724, v1667, v2285, v1668, v1674, v1669, v1675, v1670, v1676, v1671, v1677, v1672, v1678, v1679, v1680, v1681, v1682, v1683, v1684, v1666, v1673, 3, 7, 2, 4, 8) :|: TRUE
81.81/32.76	f_811(v1652, v1653, v1654, v1655, v1656, v1657, v1658, v1659, 1, v1661, 0, v1663, v1665, v1724, v1667, v2285, v1668, v1674, v1669, v1675, v1670, v1676, v1671, v1677, v1672, v1678, v1679, v1680, v1681, v1682, v1683, v1684, v1666, v1673, 3, 7, 2, 4, 8) -> f_728(v1652, v1653, v1654, v1655, v1656, v1657, v1658, v1659, 1, v1661, 0, v1663, v1665, v1724, v1667, v2285, v1668, v1674, v1669, v1675, v1670, v1676, v1671, v1677, v1672, v1678, v1679, v1680, v1681, v1682, v1683, v1684, v1673, 3, 7, 2, 4, 8) :|: TRUE
81.81/32.76	f_728(v1652, v1653, v1654, v1655, v1656, v1657, v1658, v1659, 1, v1661, 0, v1663, v1664, v1665, v1666, v1667, v1668, v1674, v1669, v1675, v1670, v1676, v1671, v1677, v1672, v1678, v1679, v1680, v1681, v1682, v1683, v1684, v1673, 3, 7, 2, 4, 8) -> f_733(v1652, v1653, v1654, v1655, v1656, v1657, v1658, v1659, 1, v1661, 0, v1663, v1665, v1666, v1667, v1668, v1674, v1669, v1675, v1670, v1676, v1671, v1677, v1672, v1678, v1679, v1680, v1681, v1682, v1683, v1684, v1673, 3, 7, 2, 4, 8) :|: 0 = 0
81.81/32.76	Combined rules. Obtained 1 rulesP rules:
81.81/32.76	f_733(v1652:0, v1653:0, v1654:0, v1655:0, v1656:0, v1657:0, v1658:0, v1659:0, 1, v1661:0, 0, v1663:0, 1 + v1724:0, v1666:0, v1667:0, v1668:0, v1674:0, v1669:0, v1675:0, v1670:0, v1676:0, v1671:0, v1677:0, v1672:0, v1678:0, v1679:0, v1680:0, v1681:0, v1682:0, v1683:0, v1684:0, v1673:0, 3, 7, 2, 4, 8) -> f_733(v1652:0, v1653:0, v1654:0, v1655:0, v1656:0, v1657:0, v1658:0, v1659:0, 1, v1661:0, 0, v1663:0, v1724:0, v1667:0, 1 + v1667:0, v1668:0, v1674:0, v1669:0, v1675:0, v1670:0, v1676:0, v1671:0, v1677:0, v1672:0, v1678:0, v1679:0, v1680:0, v1681:0, v1682:0, v1683:0, v1684:0, v1673:0, 3, 7, 2, 4, 8) :|: v1724:0 > 0 && v1679:0 > 2 && v1667:0 > 2 && v1654:0 > 2
81.81/32.76	Filtered unneeded arguments:
81.81/32.76	   f_733(x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, x16, x17, x18, x19, x20, x21, x22, x23, x24, x25, x26, x27, x28, x29, x30, x31, x32, x33, x34, x35, x36, x37) -> f_733(x3, x13, x15, x26)
81.81/32.76	Removed division, modulo operations, cleaned up constraints. Obtained 1 rules.P rules:
81.81/32.76	f_733(v1654:0, sum~cons_1~v1724:0, v1667:0, v1679:0) -> f_733(v1654:0, v1724:0, 1 + v1667:0, v1679:0) :|: v1679:0 > 2 && v1724:0 > 0 && v1654:0 > 2 && v1667:0 > 2 && sum~cons_1~v1724:0 = 1 + v1724:0
81.81/32.76	
81.81/32.76	----------------------------------------
81.81/32.76	
81.81/32.76	(30)
81.81/32.76	Obligation:
81.81/32.76	Rules:
81.81/32.76	f_733(v1654:0, sum~cons_1~v1724:0, v1667:0, v1679:0) -> f_733(v1654:0, v1724:0, 1 + v1667:0, v1679:0) :|: v1679:0 > 2 && v1724:0 > 0 && v1654:0 > 2 && v1667:0 > 2 && sum~cons_1~v1724:0 = 1 + v1724:0
81.81/32.76	
81.81/32.76	----------------------------------------
81.81/32.76	
81.81/32.76	(31) IntTRSCompressionProof (EQUIVALENT)
81.81/32.76	Compressed rules.
81.81/32.76	----------------------------------------
81.81/32.76	
81.81/32.76	(32)
81.81/32.76	Obligation:
81.81/32.76	Rules:
81.81/32.76	f_733(v1654:0:0, sum~cons_1~v1724:0:0, v1667:0:0, v1679:0:0) -> f_733(v1654:0:0, v1724:0:0, 1 + v1667:0:0, v1679:0:0) :|: v1654:0:0 > 2 && v1667:0:0 > 2 && v1724:0:0 > 0 && v1679:0:0 > 2 && sum~cons_1~v1724:0:0 = 1 + v1724:0:0
81.81/32.76	
81.81/32.76	----------------------------------------
81.81/32.76	
81.81/32.76	(33) RankingReductionPairProof (EQUIVALENT)
81.81/32.76	Interpretation:
81.81/32.76	[ f_733 ] = f_733_2
81.81/32.76	
81.81/32.76	The following rules are decreasing:
81.81/32.76	f_733(v1654:0:0, sum~cons_1~v1724:0:0, v1667:0:0, v1679:0:0) -> f_733(v1654:0:0, v1724:0:0, 1 + v1667:0:0, v1679:0:0) :|: v1654:0:0 > 2 && v1667:0:0 > 2 && v1724:0:0 > 0 && v1679:0:0 > 2 && sum~cons_1~v1724:0:0 = 1 + v1724:0:0
81.81/32.76	
81.81/32.76	The following rules are bounded:
81.81/32.76	f_733(v1654:0:0, sum~cons_1~v1724:0:0, v1667:0:0, v1679:0:0) -> f_733(v1654:0:0, v1724:0:0, 1 + v1667:0:0, v1679:0:0) :|: v1654:0:0 > 2 && v1667:0:0 > 2 && v1724:0:0 > 0 && v1679:0:0 > 2 && sum~cons_1~v1724:0:0 = 1 + v1724:0:0
81.81/32.76	
81.81/32.76	
81.81/32.76	----------------------------------------
81.81/32.76	
81.81/32.76	(34)
81.81/32.76	YES
82.07/32.81	EOF