44.37/13.79 YES 44.37/13.80 proof of /export/starexec/sandbox/benchmark/theBenchmark.c 44.37/13.80 # AProVE Commit ID: 48fb2092695e11cc9f56e44b17a92a5f88ffb256 marcel 20180622 unpublished dirty 44.37/13.80 44.37/13.80 44.37/13.80 Termination of the given C Problem could be proven: 44.37/13.80 44.37/13.80 (0) C Problem 44.37/13.80 (1) CToLLVMProof [EQUIVALENT, 175 ms] 44.37/13.80 (2) LLVM problem 44.37/13.80 (3) LLVMToTerminationGraphProof [EQUIVALENT, 7768 ms] 44.37/13.80 (4) LLVM Symbolic Execution Graph 44.37/13.80 (5) SymbolicExecutionGraphToSCCProof [SOUND, 0 ms] 44.37/13.80 (6) AND 44.37/13.80 (7) LLVM Symbolic Execution SCC 44.37/13.80 (8) SCC2IRS [SOUND, 117 ms] 44.37/13.80 (9) IntTRS 44.37/13.80 (10) IntTRSCompressionProof [EQUIVALENT, 0 ms] 44.37/13.80 (11) IntTRS 44.37/13.80 (12) RankingReductionPairProof [EQUIVALENT, 28 ms] 44.37/13.80 (13) YES 44.37/13.80 (14) LLVM Symbolic Execution SCC 44.37/13.80 (15) SCC2IRS [SOUND, 103 ms] 44.37/13.80 (16) IntTRS 44.37/13.80 (17) IntTRSCompressionProof [EQUIVALENT, 0 ms] 44.37/13.80 (18) IntTRS 44.37/13.80 (19) RankingReductionPairProof [EQUIVALENT, 9 ms] 44.37/13.80 (20) YES 44.37/13.80 (21) LLVM Symbolic Execution SCC 44.37/13.80 (22) SCC2IRS [SOUND, 107 ms] 44.37/13.80 (23) IntTRS 44.37/13.80 (24) IntTRSCompressionProof [EQUIVALENT, 0 ms] 44.37/13.80 (25) IntTRS 44.37/13.80 (26) RankingReductionPairProof [EQUIVALENT, 0 ms] 44.37/13.80 (27) YES 44.37/13.80 44.37/13.80 44.37/13.80 ---------------------------------------- 44.37/13.80 44.37/13.80 (0) 44.37/13.80 Obligation: 44.37/13.80 c file /export/starexec/sandbox/benchmark/theBenchmark.c 44.37/13.80 ---------------------------------------- 44.37/13.80 44.37/13.80 (1) CToLLVMProof (EQUIVALENT) 44.37/13.80 Compiled c-file /export/starexec/sandbox/benchmark/theBenchmark.c to LLVM. 44.37/13.80 ---------------------------------------- 44.37/13.80 44.37/13.80 (2) 44.37/13.80 Obligation: 44.37/13.80 LLVM Problem 44.37/13.80 44.37/13.80 Aliases: 44.37/13.80 44.37/13.80 Data layout: 44.37/13.80 44.37/13.80 "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" 44.37/13.80 44.37/13.80 Machine: 44.37/13.80 44.37/13.80 "x86_64-pc-linux-gnu" 44.37/13.80 44.37/13.80 Type definitions: 44.37/13.80 44.37/13.80 Global variables: 44.37/13.80 44.37/13.80 Function declarations and definitions: 44.37/13.80 44.37/13.80 *BasicFunctionTypename: "__VERIFIER_nondet_int" returnParam: i32 parameters: () variableLength: false visibilityType: DEFAULT callingConvention: ccc 44.37/13.80 *BasicFunctionTypename: "test_fun" linkageType: EXTERNALLY_VISIBLE returnParam: i32 parameters: (x i32, y i32) variableLength: false visibilityType: DEFAULT callingConvention: ccc 44.37/13.80 0: 44.37/13.80 %1 = alloca i32, align 4 44.37/13.80 %2 = alloca i32, align 4 44.37/13.80 %x_ref = alloca *i32, align 8 44.37/13.80 %y_ref = alloca *i32, align 8 44.37/13.80 %c = alloca *i32, align 8 44.37/13.80 store %x, %1 44.37/13.80 store %y, %2 44.37/13.80 %3 = alloca i8, numElementsLit: 4 44.37/13.80 %4 = bitcast *i8 %3 to *i32 44.37/13.80 store %4, %x_ref 44.37/13.80 %5 = alloca i8, numElementsLit: 4 44.37/13.80 %6 = bitcast *i8 %5 to *i32 44.37/13.80 store %6, %y_ref 44.37/13.80 %7 = alloca i8, numElementsLit: 4 44.37/13.80 %8 = bitcast *i8 %7 to *i32 44.37/13.80 store %8, %c 44.37/13.80 %9 = load %1 44.37/13.80 %10 = load %x_ref 44.37/13.80 store %9, %10 44.37/13.80 %11 = load %2 44.37/13.80 %12 = load %y_ref 44.37/13.80 store %11, %12 44.37/13.80 %13 = load %c 44.37/13.80 store 0, %13 44.37/13.80 br %14 44.37/13.80 14: 44.37/13.80 %15 = load %x_ref 44.37/13.80 %16 = load %15 44.37/13.80 %17 = icmp sgt %16 0 44.37/13.80 br %17, %22, %18 44.37/13.80 18: 44.37/13.80 %19 = load %y_ref 44.37/13.80 %20 = load %19 44.37/13.80 %21 = icmp sgt %20 0 44.37/13.80 br %22 44.37/13.80 22: 44.37/13.80 %23 = phi [1, %14], [%21, %18] 44.37/13.80 br %23, %24, %49 44.37/13.80 24: 44.37/13.80 %25 = load %x_ref 44.37/13.80 %26 = load %25 44.37/13.80 %27 = icmp sgt %26 0 44.37/13.80 br %27, %28, %33 44.37/13.80 28: 44.37/13.80 %29 = load %x_ref 44.37/13.80 %30 = load %29 44.37/13.80 %31 = sub %30 1 44.37/13.80 %32 = load %x_ref 44.37/13.80 store %31, %32 44.37/13.81 br %44 44.37/13.81 33: 44.37/13.81 %34 = load %y_ref 44.37/13.81 %35 = load %34 44.37/13.81 %36 = icmp sgt %35 0 44.37/13.81 br %36, %37, %42 44.37/13.81 37: 44.37/13.81 %38 = load %y_ref 44.37/13.81 %39 = load %38 44.37/13.81 %40 = sub %39 1 44.37/13.81 %41 = load %y_ref 44.37/13.81 store %40, %41 44.37/13.81 br %43 44.37/13.81 42: 44.37/13.81 br %43 44.37/13.81 43: 44.37/13.81 br %44 44.37/13.81 44: 44.37/13.81 %45 = load %c 44.37/13.81 %46 = load %45 44.37/13.81 %47 = add %46 1 44.37/13.81 %48 = load %c 44.37/13.81 store %47, %48 44.37/13.81 br %14 44.37/13.81 49: 44.37/13.81 %50 = load %c 44.37/13.81 %51 = load %50 44.37/13.81 ret %51 44.37/13.81 44.37/13.81 *BasicFunctionTypename: "main" linkageType: EXTERNALLY_VISIBLE returnParam: i32 parameters: () variableLength: false visibilityType: DEFAULT callingConvention: ccc 44.37/13.81 0: 44.37/13.81 %1 = alloca i32, align 4 44.37/13.81 store 0, %1 44.37/13.81 %2 = call i32 @__VERIFIER_nondet_int() 44.37/13.81 %3 = call i32 @__VERIFIER_nondet_int() 44.37/13.81 %4 = call i32 @test_fun(i32 %2, i32 %3) 44.37/13.81 ret %4 44.37/13.81 44.37/13.81 44.37/13.81 Analyze Termination of all function calls matching the pattern: 44.37/13.81 main() 44.37/13.81 ---------------------------------------- 44.37/13.81 44.37/13.81 (3) LLVMToTerminationGraphProof (EQUIVALENT) 44.37/13.81 Constructed symbolic execution graph for LLVM program and proved memory safety. 44.37/13.81 ---------------------------------------- 44.37/13.81 44.37/13.81 (4) 44.37/13.81 Obligation: 44.37/13.81 SE Graph 44.37/13.81 ---------------------------------------- 44.37/13.81 44.37/13.81 (5) SymbolicExecutionGraphToSCCProof (SOUND) 44.37/13.81 Splitted symbolic execution graph to 3 SCCs. 44.37/13.81 ---------------------------------------- 44.37/13.81 44.37/13.81 (6) 44.37/13.81 Complex Obligation (AND) 44.37/13.81 44.37/13.81 ---------------------------------------- 44.37/13.81 44.37/13.81 (7) 44.37/13.81 Obligation: 44.37/13.81 SCC 44.37/13.81 ---------------------------------------- 44.37/13.81 44.37/13.81 (8) SCC2IRS (SOUND) 44.37/13.81 Transformed LLVM symbolic execution graph SCC into a rewrite problem. Log: 44.37/13.81 Generated rules. Obtained 32 rulesP rules: 44.37/13.81 f_998(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1463, v1464, v1465, v1466, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 4, 8) -> f_1000(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1463, v1464, v1465, v1466, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 4, 8) :|: 0 = 0 44.37/13.81 f_1000(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1463, v1464, v1465, v1466, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 4, 8) -> f_1002(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1465, v1466, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 4, 8) :|: 0 = 0 44.37/13.81 f_1002(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1465, v1466, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 4, 8) -> f_1004(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1465, v1466, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 4, 8, 2) :|: v1490 = 1 + v1464 && 2 <= v1490 44.37/13.81 f_1004(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1465, v1466, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 4, 8, 2) -> f_1006(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1465, v1466, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 4, 8, 2) :|: 0 = 0 44.37/13.81 f_1006(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1465, v1466, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 4, 8, 2) -> f_1008(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1465, v1466, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 4, 8, 2) :|: TRUE 44.37/13.81 f_1008(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1465, v1466, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 4, 8, 2) -> f_1010(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1465, v1466, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 4, 8, 2) :|: TRUE 44.37/13.81 f_1010(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1465, v1466, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 4, 8, 2) -> f_1012(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1465, v1466, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 4, 8, 2) :|: 0 = 0 44.37/13.81 f_1012(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1465, v1466, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 4, 8, 2) -> f_1014(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1465, v1466, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 4, 8, 2) :|: 0 = 0 44.37/13.81 f_1014(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1465, v1466, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 4, 8, 2) -> f_1015(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1465, v1466, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 4, 8, 2) :|: 0 = 0 44.37/13.81 f_1015(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1465, v1466, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 4, 8, 2) -> f_1016(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1465, v1466, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 4, 8, 2) :|: TRUE 44.37/13.81 f_1016(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1465, v1466, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 4, 8, 2) -> f_1017(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1465, v1466, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 4, 8, 2) :|: 0 = 0 44.37/13.81 f_1017(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1465, v1466, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 4, 8, 2) -> f_1018(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1466, v1465, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 4, 8, 2) :|: 0 = 0 44.37/13.81 f_1018(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1466, v1465, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 4, 8, 2) -> f_1019(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1466, v1465, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 2, 4, 8) :|: 0 < v1466 && 2 <= v1465 && 2 <= v1452 44.37/13.81 f_1019(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1466, v1465, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 2, 4, 8) -> f_1021(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1466, v1465, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 2, 4, 8) :|: 0 = 0 44.37/13.81 f_1021(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1466, v1465, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 2, 4, 8) -> f_1023(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1466, v1465, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 2, 4, 8) :|: 0 = 0 44.37/13.81 f_1023(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1466, v1465, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 2, 4, 8) -> f_1025(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1466, v1465, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 2, 4, 8) :|: TRUE 44.37/13.81 f_1025(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1466, v1465, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 2, 4, 8) -> f_1027(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1466, v1465, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 2, 4, 8) :|: 0 = 0 44.37/13.81 f_1027(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1466, v1465, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 2, 4, 8) -> f_1029(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1466, v1465, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 2, 4, 8) :|: 0 = 0 44.37/13.81 f_1029(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1466, v1465, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 2, 4, 8) -> f_1031(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1466, v1465, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 2, 4, 8) :|: 0 = 0 44.37/13.81 f_1031(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1466, v1465, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 2, 4, 8) -> f_1033(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1466, v1465, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 2, 4, 8) :|: TRUE 44.37/13.81 f_1033(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1466, v1465, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 2, 4, 8) -> f_1034(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1466, v1465, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 2, 4, 8) :|: 0 = 0 44.37/13.81 f_1034(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1466, v1465, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 2, 4, 8) -> f_1035(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1466, v1465, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 2, 4, 8) :|: 0 = 0 44.37/13.81 f_1035(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1466, v1465, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 2, 4, 8) -> f_1036(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1466, v1465, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 2, 4, 8) :|: 0 = 0 44.37/13.81 f_1036(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1466, v1465, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 2, 4, 8) -> f_1037(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1466, v1465, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 2, 4, 8) :|: TRUE 44.37/13.81 f_1037(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1466, v1465, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 2, 4, 8) -> f_1038(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1466, v1465, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 2, 4, 8) :|: 0 = 0 44.37/13.81 f_1038(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1466, v1465, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 2, 4, 8) -> f_1039(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1466, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 2, 4, 8) :|: 0 = 0 44.37/13.81 f_1039(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1466, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 2, 4, 8) -> f_1040(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1466, v1622, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 2, 4, 8) :|: 1 + v1622 = v1466 && 0 <= v1622 44.37/13.81 f_1040(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1466, v1622, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 2, 4, 8) -> f_1041(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1466, v1622, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 2, 4, 8) :|: 0 = 0 44.37/13.81 f_1041(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1466, v1622, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 2, 4, 8) -> f_1042(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1466, v1622, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 2, 4, 8) :|: TRUE 44.37/13.81 f_1042(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1466, v1622, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 2, 4, 8) -> f_1043(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1466, v1622, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 2, 4, 8) :|: TRUE 44.37/13.81 f_1043(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1466, v1622, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 2, 4, 8) -> f_996(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1464, v1490, v1466, v1622, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 4, 8) :|: TRUE 44.37/13.81 f_996(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1463, v1464, v1465, v1466, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 4, 8) -> f_998(v1451, v1452, v1453, v1454, v1455, v1456, v1457, v1458, v1459, v1460, 0, 1, v1463, v1464, v1465, v1466, v1467, v1468, v1469, v1470, v1471, v1472, v1473, v1474, v1475, v1476, 3, 7, 4, 8) :|: TRUE 44.37/13.81 Combined rules. Obtained 1 rulesP rules: 44.37/13.81 f_998(v1451:0, v1452:0, v1453:0, v1454:0, v1455:0, v1456:0, v1457:0, v1458:0, v1459:0, v1460:0, 0, 1, v1463:0, v1464:0, v1465:0, 1 + v1622:0, v1467:0, v1468:0, v1469:0, v1470:0, v1471:0, v1472:0, v1473:0, v1474:0, v1475:0, v1476:0, 3, 7, 4, 8) -> f_998(v1451:0, v1452:0, v1453:0, v1454:0, v1455:0, v1456:0, v1457:0, v1458:0, v1459:0, v1460:0, 0, 1, v1464:0, 1 + v1464:0, 1 + v1622:0, v1622:0, v1467:0, v1468:0, v1469:0, v1470:0, v1471:0, v1472:0, v1473:0, v1474:0, v1475:0, v1476:0, 3, 7, 4, 8) :|: v1464:0 > 0 && v1465:0 > 1 && v1622:0 > -1 && v1452:0 > 1 44.37/13.81 Filtered unneeded arguments: 44.37/13.81 f_998(x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, x16, x17, x18, x19, x20, x21, x22, x23, x24, x25, x26, x27, x28, x29, x30) -> f_998(x2, x14, x15, x16) 44.37/13.81 Removed division, modulo operations, cleaned up constraints. Obtained 1 rules.P rules: 44.37/13.81 f_998(v1452:0, v1464:0, v1465:0, sum~cons_1~v1622:0) -> f_998(v1452:0, 1 + v1464:0, 1 + v1622:0, v1622:0) :|: v1465:0 > 1 && v1464:0 > 0 && v1452:0 > 1 && v1622:0 > -1 && sum~cons_1~v1622:0 = 1 + v1622:0 44.37/13.81 44.37/13.81 ---------------------------------------- 44.37/13.81 44.37/13.81 (9) 44.37/13.81 Obligation: 44.37/13.81 Rules: 44.37/13.81 f_998(v1452:0, v1464:0, v1465:0, sum~cons_1~v1622:0) -> f_998(v1452:0, 1 + v1464:0, 1 + v1622:0, v1622:0) :|: v1465:0 > 1 && v1464:0 > 0 && v1452:0 > 1 && v1622:0 > -1 && sum~cons_1~v1622:0 = 1 + v1622:0 44.37/13.81 44.37/13.81 ---------------------------------------- 44.37/13.81 44.37/13.81 (10) IntTRSCompressionProof (EQUIVALENT) 44.37/13.81 Compressed rules. 44.37/13.81 ---------------------------------------- 44.37/13.81 44.37/13.81 (11) 44.37/13.81 Obligation: 44.37/13.81 Rules: 44.37/13.81 f_998(v1452:0:0, v1464:0:0, v1465:0:0, sum~cons_1~v1622:0:0) -> f_998(v1452:0:0, 1 + v1464:0:0, 1 + v1622:0:0, v1622:0:0) :|: v1452:0:0 > 1 && v1622:0:0 > -1 && v1464:0:0 > 0 && v1465:0:0 > 1 && sum~cons_1~v1622:0:0 = 1 + v1622:0:0 44.37/13.81 44.37/13.81 ---------------------------------------- 44.37/13.81 44.37/13.81 (12) RankingReductionPairProof (EQUIVALENT) 44.37/13.81 Interpretation: 44.37/13.81 [ f_998 ] = f_998_4 44.37/13.81 44.37/13.81 The following rules are decreasing: 44.37/13.81 f_998(v1452:0:0, v1464:0:0, v1465:0:0, sum~cons_1~v1622:0:0) -> f_998(v1452:0:0, 1 + v1464:0:0, 1 + v1622:0:0, v1622:0:0) :|: v1452:0:0 > 1 && v1622:0:0 > -1 && v1464:0:0 > 0 && v1465:0:0 > 1 && sum~cons_1~v1622:0:0 = 1 + v1622:0:0 44.37/13.81 44.37/13.81 The following rules are bounded: 44.37/13.81 f_998(v1452:0:0, v1464:0:0, v1465:0:0, sum~cons_1~v1622:0:0) -> f_998(v1452:0:0, 1 + v1464:0:0, 1 + v1622:0:0, v1622:0:0) :|: v1452:0:0 > 1 && v1622:0:0 > -1 && v1464:0:0 > 0 && v1465:0:0 > 1 && sum~cons_1~v1622:0:0 = 1 + v1622:0:0 44.37/13.81 44.37/13.81 44.37/13.81 ---------------------------------------- 44.37/13.81 44.37/13.81 (13) 44.37/13.81 YES 44.37/13.81 44.37/13.81 ---------------------------------------- 44.37/13.81 44.37/13.81 (14) 44.37/13.81 Obligation: 44.37/13.81 SCC 44.37/13.81 ---------------------------------------- 44.37/13.81 44.37/13.81 (15) SCC2IRS (SOUND) 44.37/13.81 Transformed LLVM symbolic execution graph SCC into a rewrite problem. Log: 44.37/13.81 Generated rules. Obtained 32 rulesP rules: 44.37/13.81 f_938(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1301, 1, v1303, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 4, 8) -> f_940(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1301, 1, v1303, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 4, 8) :|: 0 = 0 44.37/13.81 f_940(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1301, 1, v1303, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 4, 8) -> f_942(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1301, 1, v1303, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 4, 8) :|: 0 = 0 44.37/13.81 f_942(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1301, 1, v1303, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 4, 8) -> f_944(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1301, 1, v1303, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 4, 8) :|: TRUE 44.37/13.81 f_944(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1301, 1, v1303, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 4, 8) -> f_946(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1301, 1, v1303, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 4, 8) :|: 0 = 0 44.37/13.81 f_946(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1301, 1, v1303, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 4, 8) -> f_949(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1301, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 4, 8) :|: 0 = 0 44.37/13.81 f_949(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1301, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 4, 8) -> f_952(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1301, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) :|: 0 < v1303 && 2 <= v1301 && 2 <= v1291 44.37/13.81 f_952(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1301, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) -> f_956(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1301, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) :|: 0 = 0 44.37/13.81 f_956(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1301, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) -> f_960(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1301, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) :|: 0 = 0 44.37/13.81 f_960(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1301, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) -> f_964(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1301, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) :|: TRUE 44.37/13.81 f_964(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1301, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) -> f_968(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1301, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) :|: 0 = 0 44.37/13.81 f_968(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1301, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) -> f_972(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1301, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) :|: 0 = 0 44.37/13.81 f_972(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1301, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) -> f_975(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1301, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) :|: 0 = 0 44.37/13.81 f_975(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1301, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) -> f_978(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1301, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) :|: TRUE 44.37/13.81 f_978(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1301, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) -> f_980(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1301, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) :|: 0 = 0 44.37/13.81 f_980(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1301, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) -> f_982(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1301, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) :|: 0 = 0 44.37/13.81 f_982(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1301, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) -> f_984(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1301, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) :|: 0 = 0 44.37/13.81 f_984(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1301, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) -> f_986(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1301, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) :|: TRUE 44.37/13.81 f_986(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1301, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) -> f_988(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1301, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) :|: 0 = 0 44.37/13.81 f_988(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1301, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) -> f_990(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) :|: 0 = 0 44.37/13.81 f_990(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) -> f_992(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1449, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) :|: 1 + v1449 = v1303 && 0 <= v1449 44.37/13.81 f_992(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1449, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) -> f_994(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1449, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) :|: 0 = 0 44.37/13.81 f_994(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1449, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) -> f_997(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1449, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) :|: TRUE 44.37/13.81 f_997(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1449, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) -> f_999(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1449, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) :|: TRUE 44.37/13.81 f_999(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1449, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) -> f_1001(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1449, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) :|: TRUE 44.37/13.81 f_1001(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1449, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) -> f_1003(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1449, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) :|: 0 = 0 44.37/13.81 f_1003(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1449, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) -> f_1005(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1449, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) :|: 0 = 0 44.37/13.81 f_1005(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1449, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) -> f_1007(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1449, v1305, v1491, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) :|: v1491 = 1 + v1305 && 2 <= v1491 44.37/13.81 f_1007(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1449, v1305, v1491, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) -> f_1009(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1449, v1305, v1491, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) :|: 0 = 0 44.37/13.81 f_1009(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1449, v1305, v1491, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) -> f_1011(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1449, v1305, v1491, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) :|: TRUE 44.37/13.81 f_1011(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1449, v1305, v1491, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) -> f_1013(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1449, v1305, v1491, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) :|: TRUE 44.37/13.81 f_1013(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1449, v1305, v1491, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 2, 4, 8) -> f_936(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1303, 1, v1449, v1305, v1491, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 4, 8) :|: TRUE 44.37/13.81 f_936(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1301, 1, v1303, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 4, 8) -> f_938(v1290, v1291, v1292, v1293, v1294, v1295, v1296, v1297, v1298, v1299, 0, v1301, 1, v1303, v1304, v1305, v1306, v1307, v1308, v1309, v1310, v1311, v1312, v1313, v1314, v1315, 3, 7, 4, 8) :|: 0 = 0 44.37/13.81 Combined rules. Obtained 1 rulesP rules: 44.37/13.81 f_938(v1290:0, v1291:0, v1292:0, v1293:0, v1294:0, v1295:0, v1296:0, v1297:0, v1298:0, v1299:0, 0, v1301:0, 1, 1 + v1449:0, v1304:0, v1305:0, v1306:0, v1307:0, v1308:0, v1309:0, v1310:0, v1311:0, v1312:0, v1313:0, v1314:0, v1315:0, 3, 7, 4, 8) -> f_938(v1290:0, v1291:0, v1292:0, v1293:0, v1294:0, v1295:0, v1296:0, v1297:0, v1298:0, v1299:0, 0, 1 + v1449:0, 1, v1449:0, v1305:0, 1 + v1305:0, v1306:0, v1307:0, v1308:0, v1309:0, v1310:0, v1311:0, v1312:0, v1313:0, v1314:0, v1315:0, 3, 7, 4, 8) :|: v1301:0 > 1 && v1449:0 > -1 && v1291:0 > 1 && v1305:0 > 0 44.37/13.81 Filtered unneeded arguments: 44.37/13.81 f_938(x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, x16, x17, x18, x19, x20, x21, x22, x23, x24, x25, x26, x27, x28, x29, x30) -> f_938(x2, x12, x14, x16) 44.37/13.81 Removed division, modulo operations, cleaned up constraints. Obtained 1 rules.P rules: 44.37/13.81 f_938(v1291:0, v1301:0, sum~cons_1~v1449:0, v1305:0) -> f_938(v1291:0, 1 + v1449:0, v1449:0, 1 + v1305:0) :|: v1449:0 > -1 && v1301:0 > 1 && v1305:0 > 0 && v1291:0 > 1 && sum~cons_1~v1449:0 = 1 + v1449:0 44.37/13.81 44.37/13.81 ---------------------------------------- 44.37/13.81 44.37/13.81 (16) 44.37/13.81 Obligation: 44.37/13.81 Rules: 44.37/13.81 f_938(v1291:0, v1301:0, sum~cons_1~v1449:0, v1305:0) -> f_938(v1291:0, 1 + v1449:0, v1449:0, 1 + v1305:0) :|: v1449:0 > -1 && v1301:0 > 1 && v1305:0 > 0 && v1291:0 > 1 && sum~cons_1~v1449:0 = 1 + v1449:0 44.37/13.81 44.37/13.81 ---------------------------------------- 44.37/13.81 44.37/13.81 (17) IntTRSCompressionProof (EQUIVALENT) 44.37/13.81 Compressed rules. 44.37/13.81 ---------------------------------------- 44.37/13.81 44.37/13.81 (18) 44.37/13.81 Obligation: 44.37/13.81 Rules: 44.37/13.81 f_938(v1291:0:0, v1301:0:0, sum~cons_1~v1449:0:0, v1305:0:0) -> f_938(v1291:0:0, 1 + v1449:0:0, v1449:0:0, 1 + v1305:0:0) :|: v1305:0:0 > 0 && v1291:0:0 > 1 && v1301:0:0 > 1 && v1449:0:0 > -1 && sum~cons_1~v1449:0:0 = 1 + v1449:0:0 44.37/13.81 44.37/13.81 ---------------------------------------- 44.37/13.81 44.37/13.81 (19) RankingReductionPairProof (EQUIVALENT) 44.37/13.81 Interpretation: 44.37/13.81 [ f_938 ] = f_938_3 44.37/13.81 44.37/13.81 The following rules are decreasing: 44.37/13.81 f_938(v1291:0:0, v1301:0:0, sum~cons_1~v1449:0:0, v1305:0:0) -> f_938(v1291:0:0, 1 + v1449:0:0, v1449:0:0, 1 + v1305:0:0) :|: v1305:0:0 > 0 && v1291:0:0 > 1 && v1301:0:0 > 1 && v1449:0:0 > -1 && sum~cons_1~v1449:0:0 = 1 + v1449:0:0 44.37/13.81 44.37/13.81 The following rules are bounded: 44.37/13.81 f_938(v1291:0:0, v1301:0:0, sum~cons_1~v1449:0:0, v1305:0:0) -> f_938(v1291:0:0, 1 + v1449:0:0, v1449:0:0, 1 + v1305:0:0) :|: v1305:0:0 > 0 && v1291:0:0 > 1 && v1301:0:0 > 1 && v1449:0:0 > -1 && sum~cons_1~v1449:0:0 = 1 + v1449:0:0 44.37/13.81 44.37/13.81 44.37/13.81 ---------------------------------------- 44.37/13.81 44.37/13.81 (20) 44.37/13.81 YES 44.37/13.81 44.37/13.81 ---------------------------------------- 44.37/13.81 44.37/13.81 (21) 44.37/13.81 Obligation: 44.37/13.81 SCC 44.37/13.81 ---------------------------------------- 44.37/13.81 44.37/13.81 (22) SCC2IRS (SOUND) 44.37/13.81 Transformed LLVM symbolic execution graph SCC into a rewrite problem. Log: 44.37/13.81 Generated rules. Obtained 23 rulesP rules: 44.37/13.81 f_757(v714, v715, v716, v717, v718, v719, v720, v721, v722, v723, v724, 1, v726, v727, v728, v729, v730, v731, v732, v733, v734, v735, v736, v737, v738, 0, 3, 7, 4, 8) -> f_759(v714, v715, v716, v717, v718, v719, v720, v721, v722, v723, v726, 1, v724, v727, v728, v729, v730, v731, v732, v733, v734, v735, v736, v737, v738, 0, 3, 7, 4, 8) :|: 0 = 0 44.37/13.81 f_759(v714, v715, v716, v717, v718, v719, v720, v721, v722, v723, v726, 1, v724, v727, v728, v729, v730, v731, v732, v733, v734, v735, v736, v737, v738, 0, 3, 7, 4, 8) -> f_762(v714, v715, v716, v717, v718, v719, v720, v721, v722, v723, v726, 1, v724, v727, v728, v729, v730, v731, v732, v733, v734, v735, v736, v737, v738, 0, 3, 7, 2, 4, 8) :|: 0 < v726 && 2 <= v724 && 2 <= v714 44.37/13.81 f_762(v714, v715, v716, v717, v718, v719, v720, v721, v722, v723, v726, 1, v724, v727, v728, v729, v730, v731, v732, v733, v734, v735, v736, v737, v738, 0, 3, 7, 2, 4, 8) -> f_765(v714, v715, v716, v717, v718, v719, v720, v721, v722, v723, v726, 1, v724, v727, v728, v729, v730, v731, v732, v733, v734, v735, v736, v737, v738, 0, 3, 7, 2, 4, 8) :|: 0 = 0 44.37/13.81 f_765(v714, v715, v716, v717, v718, v719, v720, v721, v722, v723, v726, 1, v724, v727, v728, v729, v730, v731, v732, v733, v734, v735, v736, v737, v738, 0, 3, 7, 2, 4, 8) -> f_768(v714, v715, v716, v717, v718, v719, v720, v721, v722, v723, v726, 1, v724, v727, v728, v729, v730, v731, v732, v733, v734, v735, v736, v737, v738, 0, 3, 7, 2, 4, 8) :|: 0 = 0 44.37/13.81 f_768(v714, v715, v716, v717, v718, v719, v720, v721, v722, v723, v726, 1, v724, v727, v728, v729, v730, v731, v732, v733, v734, v735, v736, v737, v738, 0, 3, 7, 2, 4, 8) -> f_771(v714, v715, v716, v717, v718, v719, v720, v721, v722, v723, v726, 1, v724, v727, v728, v729, v730, v731, v732, v733, v734, v735, v736, v737, v738, 0, 3, 7, 2, 4, 8) :|: TRUE 44.37/13.81 f_771(v714, v715, v716, v717, v718, v719, v720, v721, v722, v723, v726, 1, v724, v727, v728, v729, v730, v731, v732, v733, v734, v735, v736, v737, v738, 0, 3, 7, 2, 4, 8) -> f_774(v714, v715, v716, v717, v718, v719, v720, v721, v722, v723, v726, 1, v724, v727, v728, v729, v730, v731, v732, v733, v734, v735, v736, v737, v738, 0, 3, 7, 2, 4, 8) :|: 0 = 0 44.37/13.81 f_774(v714, v715, v716, v717, v718, v719, v720, v721, v722, v723, v726, 1, v724, v727, v728, v729, v730, v731, v732, v733, v734, v735, v736, v737, v738, 0, 3, 7, 2, 4, 8) -> f_777(v714, v715, v716, v717, v718, v719, v720, v721, v722, v723, v726, 1, v724, v727, v728, v729, v730, v731, v732, v733, v734, v735, v736, v737, v738, 0, 3, 7, 2, 4, 8) :|: 0 = 0 44.37/13.81 f_777(v714, v715, v716, v717, v718, v719, v720, v721, v722, v723, v726, 1, v724, v727, v728, v729, v730, v731, v732, v733, v734, v735, v736, v737, v738, 0, 3, 7, 2, 4, 8) -> f_781(v714, v715, v716, v717, v718, v719, v720, v721, v722, v723, v726, 1, v724, v727, v728, v729, v730, v731, v732, v733, v734, v735, v736, v737, v738, 0, 3, 7, 2, 4, 8) :|: 0 = 0 44.37/13.81 f_781(v714, v715, v716, v717, v718, v719, v720, v721, v722, v723, v726, 1, v724, v727, v728, v729, v730, v731, v732, v733, v734, v735, v736, v737, v738, 0, 3, 7, 2, 4, 8) -> f_786(v714, v715, v716, v717, v718, v719, v720, v721, v722, v723, v726, 1, v724, v727, v728, v729, v730, v731, v732, v733, v734, v735, v736, v737, v738, 0, 3, 7, 2, 4, 8) :|: TRUE 44.37/13.81 f_786(v714, v715, v716, v717, v718, v719, v720, v721, v722, v723, v726, 1, v724, v727, v728, v729, v730, v731, v732, v733, v734, v735, v736, v737, v738, 0, 3, 7, 2, 4, 8) -> f_791(v714, v715, v716, v717, v718, v719, v720, v721, v722, v723, v726, 1, v724, v727, v728, v729, v730, v731, v732, v733, v734, v735, v736, v737, v738, 0, 3, 7, 2, 4, 8) :|: 0 = 0 44.37/13.81 f_791(v714, v715, v716, v717, v718, v719, v720, v721, v722, v723, v726, 1, v724, v727, v728, v729, v730, v731, v732, v733, v734, v735, v736, v737, v738, 0, 3, 7, 2, 4, 8) -> f_796(v714, v715, v716, v717, v718, v719, v720, v721, v722, v723, v726, 1, v727, v728, v729, v730, v731, v732, v733, v734, v735, v736, v737, v738, 0, 3, 7, 2, 4, 8) :|: 0 = 0 44.37/13.81 f_796(v714, v715, v716, v717, v718, v719, v720, v721, v722, v723, v726, 1, v727, v728, v729, v730, v731, v732, v733, v734, v735, v736, v737, v738, 0, 3, 7, 2, 4, 8) -> f_801(v714, v715, v716, v717, v718, v719, v720, v721, v722, v723, v726, 1, v817, v727, v728, v729, v730, v731, v732, v733, v734, v735, v736, v737, v738, 0, 3, 7, 2, 4, 8) :|: 1 + v817 = v726 && 0 <= v817 44.37/13.81 f_801(v714, v715, v716, v717, v718, v719, v720, v721, v722, v723, v726, 1, v817, v727, v728, v729, v730, v731, v732, v733, v734, v735, v736, v737, v738, 0, 3, 7, 2, 4, 8) -> f_806(v714, v715, v716, v717, v718, v719, v720, v721, v722, v723, v726, 1, v817, v727, v728, v729, v730, v731, v732, v733, v734, v735, v736, v737, v738, 0, 3, 7, 2, 4, 8) :|: 0 = 0 44.37/13.81 f_806(v714, v715, v716, v717, v718, v719, v720, v721, v722, v723, v726, 1, v817, v727, v728, v729, v730, v731, v732, v733, v734, v735, v736, v737, v738, 0, 3, 7, 2, 4, 8) -> f_811(v714, v715, v716, v717, v718, v719, v720, v721, v722, v723, v726, 1, v817, v727, v728, v729, v730, v731, v732, v733, v734, v735, v736, v737, v738, 0, 3, 7, 2, 4, 8) :|: TRUE 44.37/13.81 f_811(v714, v715, v716, v717, v718, v719, v720, v721, v722, v723, v726, 1, v817, v727, v728, v729, v730, v731, v732, v733, v734, v735, v736, v737, v738, 0, 3, 7, 2, 4, 8) -> f_815(v714, v715, v716, v717, v718, v719, v720, v721, v722, v723, v726, 1, v817, v727, v728, v729, v730, v731, v732, v733, v734, v735, v736, v737, v738, 0, 3, 7, 2, 4, 8) :|: TRUE 44.37/13.81 f_815(v714, v715, v716, v717, v718, v719, v720, v721, v722, v723, v726, 1, v817, v727, v728, v729, v730, v731, v732, v733, v734, v735, v736, v737, v738, 0, 3, 7, 2, 4, 8) -> f_818(v714, v715, v716, v717, v718, v719, v720, v721, v722, v723, v726, 1, v817, v727, v728, v729, v730, v731, v732, v733, v734, v735, v736, v737, v738, 0, 3, 7, 2, 4, 8) :|: 0 = 0 44.37/13.81 f_818(v714, v715, v716, v717, v718, v719, v720, v721, v722, v723, v726, 1, v817, v727, v728, v729, v730, v731, v732, v733, v734, v735, v736, v737, v738, 0, 3, 7, 2, 4, 8) -> f_821(v714, v715, v716, v717, v718, v719, v720, v721, v722, v723, v726, 1, v817, v728, v729, v730, v731, v732, v733, v734, v735, v736, v737, v738, 0, 3, 7, 2, 4, 8) :|: 0 = 0 44.37/13.81 f_821(v714, v715, v716, v717, v718, v719, v720, v721, v722, v723, v726, 1, v817, v728, v729, v730, v731, v732, v733, v734, v735, v736, v737, v738, 0, 3, 7, 2, 4, 8) -> f_824(v714, v715, v716, v717, v718, v719, v720, v721, v722, v723, v726, 1, v817, v728, v819, v729, v730, v731, v732, v733, v734, v735, v736, v737, v738, 0, 3, 7, 2, 4, 8) :|: v819 = 1 + v728 && 2 <= v819 44.37/13.81 f_824(v714, v715, v716, v717, v718, v719, v720, v721, v722, v723, v726, 1, v817, v728, v819, v729, v730, v731, v732, v733, v734, v735, v736, v737, v738, 0, 3, 7, 2, 4, 8) -> f_827(v714, v715, v716, v717, v718, v719, v720, v721, v722, v723, v726, 1, v817, v728, v819, v729, v730, v731, v732, v733, v734, v735, v736, v737, v738, 0, 3, 7, 2, 4, 8) :|: 0 = 0 44.37/13.81 f_827(v714, v715, v716, v717, v718, v719, v720, v721, v722, v723, v726, 1, v817, v728, v819, v729, v730, v731, v732, v733, v734, v735, v736, v737, v738, 0, 3, 7, 2, 4, 8) -> f_830(v714, v715, v716, v717, v718, v719, v720, v721, v722, v723, v726, 1, v817, v728, v819, v729, v730, v731, v732, v733, v734, v735, v736, v737, v738, 0, 3, 7, 2, 4, 8) :|: TRUE 44.37/13.81 f_830(v714, v715, v716, v717, v718, v719, v720, v721, v722, v723, v726, 1, v817, v728, v819, v729, v730, v731, v732, v733, v734, v735, v736, v737, v738, 0, 3, 7, 2, 4, 8) -> f_833(v714, v715, v716, v717, v718, v719, v720, v721, v722, v723, v726, 1, v817, v728, v819, v729, v730, v731, v732, v733, v734, v735, v736, v737, v738, 0, 3, 7, 2, 4, 8) :|: TRUE 44.37/13.81 f_833(v714, v715, v716, v717, v718, v719, v720, v721, v722, v723, v726, 1, v817, v728, v819, v729, v730, v731, v732, v733, v734, v735, v736, v737, v738, 0, 3, 7, 2, 4, 8) -> f_755(v714, v715, v716, v717, v718, v719, v720, v721, v722, v723, v726, 1, v817, v728, v819, v729, v730, v731, v732, v733, v734, v735, v736, v737, v738, 0, 3, 7, 4, 8) :|: TRUE 44.37/13.81 f_755(v714, v715, v716, v717, v718, v719, v720, v721, v722, v723, v724, 1, v726, v727, v728, v729, v730, v731, v732, v733, v734, v735, v736, v737, v738, 0, 3, 7, 4, 8) -> f_757(v714, v715, v716, v717, v718, v719, v720, v721, v722, v723, v724, 1, v726, v727, v728, v729, v730, v731, v732, v733, v734, v735, v736, v737, v738, 0, 3, 7, 4, 8) :|: 0 = 0 44.37/13.81 Combined rules. Obtained 1 rulesP rules: 44.37/13.81 f_757(v714:0, v715:0, v716:0, v717:0, v718:0, v719:0, v720:0, v721:0, v722:0, v723:0, v724:0, 1, 1 + v817:0, v727:0, v728:0, v729:0, v730:0, v731:0, v732:0, v733:0, v734:0, v735:0, v736:0, v737:0, v738:0, 0, 3, 7, 4, 8) -> f_757(v714:0, v715:0, v716:0, v717:0, v718:0, v719:0, v720:0, v721:0, v722:0, v723:0, 1 + v817:0, 1, v817:0, v728:0, 1 + v728:0, v729:0, v730:0, v731:0, v732:0, v733:0, v734:0, v735:0, v736:0, v737:0, v738:0, 0, 3, 7, 4, 8) :|: v724:0 > 1 && v817:0 > -1 && v714:0 > 1 && v728:0 > 0 44.37/13.81 Filtered unneeded arguments: 44.37/13.81 f_757(x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, x16, x17, x18, x19, x20, x21, x22, x23, x24, x25, x26, x27, x28, x29, x30) -> f_757(x1, x11, x13, x15) 44.37/13.81 Removed division, modulo operations, cleaned up constraints. Obtained 1 rules.P rules: 44.37/13.81 f_757(v714:0, v724:0, sum~cons_1~v817:0, v728:0) -> f_757(v714:0, 1 + v817:0, v817:0, 1 + v728:0) :|: v817:0 > -1 && v724:0 > 1 && v728:0 > 0 && v714:0 > 1 && sum~cons_1~v817:0 = 1 + v817:0 44.37/13.81 44.37/13.81 ---------------------------------------- 44.37/13.81 44.37/13.81 (23) 44.37/13.81 Obligation: 44.37/13.81 Rules: 44.37/13.81 f_757(v714:0, v724:0, sum~cons_1~v817:0, v728:0) -> f_757(v714:0, 1 + v817:0, v817:0, 1 + v728:0) :|: v817:0 > -1 && v724:0 > 1 && v728:0 > 0 && v714:0 > 1 && sum~cons_1~v817:0 = 1 + v817:0 44.37/13.81 44.37/13.81 ---------------------------------------- 44.37/13.81 44.37/13.81 (24) IntTRSCompressionProof (EQUIVALENT) 44.37/13.81 Compressed rules. 44.37/13.81 ---------------------------------------- 44.37/13.81 44.37/13.81 (25) 44.37/13.81 Obligation: 44.37/13.81 Rules: 44.37/13.81 f_757(v714:0:0, v724:0:0, sum~cons_1~v817:0:0, v728:0:0) -> f_757(v714:0:0, 1 + v817:0:0, v817:0:0, 1 + v728:0:0) :|: v728:0:0 > 0 && v714:0:0 > 1 && v724:0:0 > 1 && v817:0:0 > -1 && sum~cons_1~v817:0:0 = 1 + v817:0:0 44.37/13.81 44.37/13.81 ---------------------------------------- 44.37/13.81 44.37/13.81 (26) RankingReductionPairProof (EQUIVALENT) 44.37/13.81 Interpretation: 44.37/13.81 [ f_757 ] = f_757_3 44.37/13.81 44.37/13.81 The following rules are decreasing: 44.37/13.81 f_757(v714:0:0, v724:0:0, sum~cons_1~v817:0:0, v728:0:0) -> f_757(v714:0:0, 1 + v817:0:0, v817:0:0, 1 + v728:0:0) :|: v728:0:0 > 0 && v714:0:0 > 1 && v724:0:0 > 1 && v817:0:0 > -1 && sum~cons_1~v817:0:0 = 1 + v817:0:0 44.37/13.81 44.37/13.81 The following rules are bounded: 44.37/13.81 f_757(v714:0:0, v724:0:0, sum~cons_1~v817:0:0, v728:0:0) -> f_757(v714:0:0, 1 + v817:0:0, v817:0:0, 1 + v728:0:0) :|: v728:0:0 > 0 && v714:0:0 > 1 && v724:0:0 > 1 && v817:0:0 > -1 && sum~cons_1~v817:0:0 = 1 + v817:0:0 44.37/13.81 44.37/13.81 44.37/13.81 ---------------------------------------- 44.37/13.81 44.37/13.81 (27) 44.37/13.81 YES 44.64/13.87 EOF