21.00/6.59	YES
21.16/6.60	proof of /export/starexec/sandbox/benchmark/theBenchmark.c
21.16/6.60	# AProVE Commit ID: 48fb2092695e11cc9f56e44b17a92a5f88ffb256 marcel 20180622 unpublished dirty
21.16/6.60	
21.16/6.60	
21.16/6.60	Termination of the given C Problem could be proven:
21.16/6.60	
21.16/6.60	(0) C Problem
21.16/6.60	(1) CToLLVMProof [EQUIVALENT, 164 ms]
21.16/6.60	(2) LLVM problem
21.16/6.60	(3) LLVMToTerminationGraphProof [EQUIVALENT, 2074 ms]
21.16/6.60	(4) LLVM Symbolic Execution Graph
21.16/6.60	(5) SymbolicExecutionGraphToSCCProof [SOUND, 0 ms]
21.16/6.60	(6) AND
21.16/6.60	    (7) LLVM Symbolic Execution SCC
21.16/6.60	        (8) SCC2IRS [SOUND, 93 ms]
21.16/6.60	        (9) IntTRS
21.16/6.60	        (10) IntTRSCompressionProof [EQUIVALENT, 1 ms]
21.16/6.60	        (11) IntTRS
21.16/6.60	        (12) RankingReductionPairProof [EQUIVALENT, 6 ms]
21.16/6.60	        (13) YES
21.16/6.60	    (14) LLVM Symbolic Execution SCC
21.16/6.60	        (15) SCC2IRS [SOUND, 132 ms]
21.16/6.60	        (16) IntTRS
21.16/6.60	        (17) IntTRSCompressionProof [EQUIVALENT, 0 ms]
21.16/6.60	        (18) IntTRS
21.16/6.60	        (19) RankingReductionPairProof [EQUIVALENT, 25 ms]
21.16/6.60	        (20) YES
21.16/6.60	
21.16/6.60	
21.16/6.60	----------------------------------------
21.16/6.60	
21.16/6.60	(0)
21.16/6.60	Obligation:
21.16/6.60	c file /export/starexec/sandbox/benchmark/theBenchmark.c
21.16/6.60	----------------------------------------
21.16/6.60	
21.16/6.60	(1) CToLLVMProof (EQUIVALENT)
21.16/6.60	Compiled c-file /export/starexec/sandbox/benchmark/theBenchmark.c to LLVM.
21.16/6.60	----------------------------------------
21.16/6.60	
21.16/6.60	(2)
21.16/6.60	Obligation:
21.16/6.60	LLVM Problem
21.16/6.60	
21.16/6.60	Aliases:
21.16/6.60	
21.16/6.60	Data layout:
21.16/6.60	
21.16/6.60	"e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
21.16/6.60	
21.16/6.60	Machine:
21.16/6.60	
21.16/6.60	"x86_64-pc-linux-gnu"
21.16/6.60	
21.16/6.60	Type definitions:
21.16/6.60	
21.16/6.60	Global variables:
21.16/6.60	
21.16/6.60	Function declarations and definitions:
21.16/6.60	
21.16/6.60	*BasicFunctionTypename: "__VERIFIER_nondet_int" returnParam: i32 parameters: () variableLength: false visibilityType: DEFAULT callingConvention: ccc
21.16/6.60	*BasicFunctionTypename: "main" linkageType: EXTERNALLY_VISIBLE returnParam: i32 parameters: () variableLength: false visibilityType: DEFAULT callingConvention: ccc
21.16/6.60		0:
21.16/6.60			%1 = alloca i32, align 4
21.16/6.60			%x = alloca *i32, align 8
21.16/6.60			%y = alloca *i32, align 8
21.16/6.60			%z = alloca *i32, align 8
21.16/6.60			%m = alloca *i32, align 8
21.16/6.60			%n = alloca *i32, align 8
21.16/6.60			store 0, %1
21.16/6.60			%2 = alloca i8, numElementsLit: 4
21.16/6.60			%3 = bitcast *i8 %2 to *i32
21.16/6.60			store %3, %x
21.16/6.60			%4 = alloca i8, numElementsLit: 4
21.16/6.60			%5 = bitcast *i8 %4 to *i32
21.16/6.60			store %5, %y
21.16/6.60			%6 = alloca i8, numElementsLit: 4
21.16/6.60			%7 = bitcast *i8 %6 to *i32
21.16/6.60			store %7, %z
21.16/6.60			%8 = alloca i8, numElementsLit: 4
21.16/6.60			%9 = bitcast *i8 %8 to *i32
21.16/6.60			store %9, %m
21.16/6.60			%10 = alloca i8, numElementsLit: 4
21.16/6.60			%11 = bitcast *i8 %10 to *i32
21.16/6.60			store %11, %n
21.16/6.60			%12 = call i32 @__VERIFIER_nondet_int()
21.16/6.60			%13 = icmp ne %12 0
21.16/6.60			br %13, %14, %16
21.16/6.60		14:
21.16/6.60			%15 = load %x
21.16/6.60			store 1, %15
21.16/6.60			br %18
21.16/6.60		16:
21.16/6.60			%17 = load %x
21.16/6.60			store -1, %17
21.16/6.60			br %18
21.16/6.60		18:
21.16/6.60			br %19
21.16/6.60		19:
21.16/6.60			%20 = load %y
21.16/6.60			%21 = load %20
21.16/6.60			%22 = icmp slt %21 100
21.16/6.60			br %22, %23, %27
21.16/6.60		23:
21.16/6.60			%24 = load %z
21.16/6.60			%25 = load %24
21.16/6.60			%26 = icmp slt %25 100
21.16/6.60			br %27
21.16/6.60		27:
21.16/6.60			%28 = phi [0, %19], [%26, %23]
21.16/6.60			br %28, %29, %42
21.16/6.60		29:
21.16/6.60			%30 = load %y
21.16/6.60			%31 = load %30
21.16/6.60			%32 = load %x
21.16/6.60			%33 = load %32
21.16/6.60			%34 = add %31 %33
21.16/6.60			%35 = load %y
21.16/6.60			store %34, %35
21.16/6.60			%36 = load %z
21.16/6.60			%37 = load %36
21.16/6.60			%38 = load %x
21.16/6.60			%39 = load %38
21.16/6.60			%40 = sub %37 %39
21.16/6.60			%41 = load %z
21.16/6.60			store %40, %41
21.16/6.60			br %19
21.16/6.60		42:
21.16/6.60			ret 0
21.16/6.60	
21.16/6.60	
21.16/6.60	Analyze Termination of all function calls matching the pattern:
21.16/6.60	main()
21.16/6.60	----------------------------------------
21.16/6.60	
21.16/6.60	(3) LLVMToTerminationGraphProof (EQUIVALENT)
21.16/6.60	Constructed symbolic execution graph for LLVM program and proved memory safety.
21.16/6.60	----------------------------------------
21.16/6.60	
21.16/6.60	(4)
21.16/6.60	Obligation:
21.16/6.60	SE Graph
21.16/6.60	----------------------------------------
21.16/6.60	
21.16/6.60	(5) SymbolicExecutionGraphToSCCProof (SOUND)
21.16/6.60	Splitted symbolic execution graph to 2 SCCs.
21.16/6.60	----------------------------------------
21.16/6.60	
21.16/6.60	(6)
21.16/6.60	Complex Obligation (AND)
21.16/6.60	
21.16/6.60	----------------------------------------
21.16/6.60	
21.16/6.60	(7)
21.16/6.60	Obligation:
21.16/6.60	SCC
21.16/6.60	----------------------------------------
21.16/6.60	
21.16/6.60	(8) SCC2IRS (SOUND)
21.16/6.60	Transformed LLVM symbolic execution graph SCC into a rewrite problem. Log: 
21.16/6.60	Generated rules. Obtained 26 rulesP rules:
21.16/6.60	f_284(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v31, 1, v35, -1, v190, v194, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 99, 98, 100) -> f_286(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v35, v31, -1, v194, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 99, 98, 100) :|: 0 = 0
21.16/6.60	f_286(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v35, v31, -1, v194, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 99, 98, 100) -> f_289(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v35, v31, -1, v194, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 99, 98, 100) :|: 0 = 0
21.16/6.60	f_289(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v35, v31, -1, v194, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 99, 98, 100) -> f_292(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v35, v31, -1, v194, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 99, 98, 100) :|: TRUE
21.16/6.60	f_292(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v35, v31, -1, v194, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 99, 98, 100) -> f_295(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v35, v31, -1, v194, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 99, 98, 100) :|: 0 = 0
21.16/6.60	f_295(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v35, v31, -1, v194, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 99, 98, 100) -> f_298(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v194, v31, -1, v35, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 99, 98, 100) :|: 0 = 0
21.16/6.60	f_298(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v194, v31, -1, v35, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 99, 98, 100) -> f_300(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v194, v31, -1, v35, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 99, 98) :|: v194 < 100 && v35 <= 98
21.16/6.60	f_300(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v194, v31, -1, v35, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 99, 98) -> f_303(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v194, v31, -1, v35, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 99, 98) :|: 0 = 0
21.16/6.60	f_303(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v194, v31, -1, v35, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 99, 98) -> f_306(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v194, v31, -1, v35, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 99, 98) :|: 0 = 0
21.16/6.60	f_306(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v194, v31, -1, v35, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 99, 98) -> f_309(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v194, v31, -1, v35, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 99, 98) :|: TRUE
21.16/6.60	f_309(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v194, v31, -1, v35, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 99, 98) -> f_312(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v194, v31, -1, v35, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 99, 98) :|: 0 = 0
21.16/6.60	f_312(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v194, v31, -1, v35, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 99, 98) -> f_314(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v194, -1, v35, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 98, 99) :|: 0 = 0
21.16/6.60	f_314(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v194, -1, v35, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 98, 99) -> f_316(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v194, -1, v35, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 98, 99) :|: 0 = 0
21.16/6.60	f_316(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v194, -1, v35, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 98, 99) -> f_318(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v194, -1, v35, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 98, 99) :|: 0 = 0
21.16/6.60	f_318(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v194, -1, v35, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 98, 99) -> f_320(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v194, -1, v732, v35, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 98, 99, 97) :|: 1 + v732 = v190 && v732 <= 97
21.16/6.60	f_320(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v194, -1, v732, v35, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 98, 99, 97) -> f_322(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v194, -1, v732, v35, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 98, 99, 97) :|: 0 = 0
21.16/6.60	f_322(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v194, -1, v732, v35, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 98, 99, 97) -> f_324(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v194, -1, v732, v35, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 98, 99, 97) :|: TRUE
21.16/6.60	f_324(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v194, -1, v732, v35, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 98, 99, 97) -> f_326(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v194, -1, v732, v35, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 98, 99, 97) :|: 0 = 0
21.16/6.60	f_326(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v194, -1, v732, v35, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 98, 99, 97) -> f_328(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v194, -1, v732, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 98, 99, 97) :|: 0 = 0
21.16/6.60	f_328(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v194, -1, v732, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 98, 99, 97) -> f_330(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v194, -1, v732, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 98, 99, 97) :|: 0 = 0
21.16/6.60	f_330(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v194, -1, v732, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 98, 99, 97) -> f_332(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v194, -1, v732, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 98, 99, 97) :|: 0 = 0
21.16/6.60	f_332(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v194, -1, v732, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 98, 99, 97) -> f_334(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v194, -1, v732, v736, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 98, 99, 97, 100) :|: v736 = 1 + v194 && v736 <= 100
21.16/6.60	f_334(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v194, -1, v732, v736, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 98, 99, 97, 100) -> f_336(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v194, -1, v732, v736, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 98, 99, 97, 100) :|: 0 = 0
21.16/6.60	f_336(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v194, -1, v732, v736, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 98, 99, 97, 100) -> f_338(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v194, -1, v732, v736, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 98, 99, 97, 100) :|: TRUE
21.16/6.60	f_338(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v194, -1, v732, v736, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 98, 99, 97, 100) -> f_340(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v194, -1, v732, v736, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 98, 99, 97, 100) :|: TRUE
21.16/6.60	f_340(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v194, -1, v732, v736, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 98, 99, 97, 100) -> f_282(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v190, 1, v194, -1, v732, v736, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 99, 98, 100) :|: TRUE
21.16/6.60	f_282(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v31, 1, v35, -1, v190, v194, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 99, 98, 100) -> f_284(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, 0, v31, 1, v35, -1, v190, v194, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 3, 7, 4, 8, 99, 98, 100) :|: 0 = 0
21.16/6.60	Combined rules. Obtained 1 rulesP rules:
21.16/6.60	f_284(v1:0, v3:0, v5:0, v7:0, v9:0, v11:0, v13:0, v16:0, v19:0, v22:0, v25:0, 0, v31:0, 1, v35:0, -1, 1 + v732:0, v194:0, v2:0, v4:0, v6:0, v8:0, v10:0, v12:0, v14:0, v17:0, v20:0, v23:0, v26:0, 3, 7, 4, 8, 99, 98, 100) -> f_284(v1:0, v3:0, v5:0, v7:0, v9:0, v11:0, v13:0, v16:0, v19:0, v22:0, v25:0, 0, 1 + v732:0, 1, v194:0, -1, v732:0, 1 + v194:0, v2:0, v4:0, v6:0, v8:0, v10:0, v12:0, v14:0, v17:0, v20:0, v23:0, v26:0, 3, 7, 4, 8, 99, 98, 100) :|: v35:0 < 99 && v194:0 < 100 && v732:0 < 98
21.16/6.60	Filtered unneeded arguments:
21.16/6.60	   f_284(x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, x16, x17, x18, x19, x20, x21, x22, x23, x24, x25, x26, x27, x28, x29, x30, x31, x32, x33, x34, x35, x36) -> f_284(x15, x17, x18)
21.16/6.60	Removed division, modulo operations, cleaned up constraints. Obtained 1 rules.P rules:
21.16/6.60	f_284(v35:0, sum~cons_1~v732:0, v194:0) -> f_284(v194:0, v732:0, 1 + v194:0) :|: v194:0 < 100 && v732:0 < 98 && v35:0 < 99 && sum~cons_1~v732:0 = 1 + v732:0
21.16/6.60	
21.16/6.60	----------------------------------------
21.16/6.60	
21.16/6.60	(9)
21.16/6.60	Obligation:
21.16/6.60	Rules:
21.16/6.60	f_284(v35:0, sum~cons_1~v732:0, v194:0) -> f_284(v194:0, v732:0, 1 + v194:0) :|: v194:0 < 100 && v732:0 < 98 && v35:0 < 99 && sum~cons_1~v732:0 = 1 + v732:0
21.16/6.60	
21.16/6.60	----------------------------------------
21.16/6.60	
21.16/6.60	(10) IntTRSCompressionProof (EQUIVALENT)
21.16/6.60	Compressed rules.
21.16/6.60	----------------------------------------
21.16/6.60	
21.16/6.60	(11)
21.16/6.60	Obligation:
21.16/6.60	Rules:
21.16/6.60	f_284(v35:0:0, sum~cons_1~v732:0:0, v194:0:0) -> f_284(v194:0:0, v732:0:0, 1 + v194:0:0) :|: v194:0:0 < 100 && v732:0:0 < 98 && v35:0:0 < 99 && sum~cons_1~v732:0:0 = 1 + v732:0:0
21.16/6.60	
21.16/6.60	----------------------------------------
21.16/6.60	
21.16/6.60	(12) RankingReductionPairProof (EQUIVALENT)
21.16/6.60	Interpretation:
21.16/6.60	[ f_284 ] = -1*f_284_3
21.16/6.60	
21.16/6.60	The following rules are decreasing:
21.16/6.60	f_284(v35:0:0, sum~cons_1~v732:0:0, v194:0:0) -> f_284(v194:0:0, v732:0:0, 1 + v194:0:0) :|: v194:0:0 < 100 && v732:0:0 < 98 && v35:0:0 < 99 && sum~cons_1~v732:0:0 = 1 + v732:0:0
21.16/6.60	
21.16/6.60	The following rules are bounded:
21.16/6.60	f_284(v35:0:0, sum~cons_1~v732:0:0, v194:0:0) -> f_284(v194:0:0, v732:0:0, 1 + v194:0:0) :|: v194:0:0 < 100 && v732:0:0 < 98 && v35:0:0 < 99 && sum~cons_1~v732:0:0 = 1 + v732:0:0
21.16/6.60	
21.16/6.60	
21.16/6.60	----------------------------------------
21.16/6.60	
21.16/6.60	(13)
21.16/6.60	YES
21.16/6.60	
21.16/6.60	----------------------------------------
21.16/6.60	
21.16/6.60	(14)
21.16/6.60	Obligation:
21.16/6.60	SCC
21.16/6.60	----------------------------------------
21.16/6.60	
21.16/6.60	(15) SCC2IRS (SOUND)
21.16/6.60	Transformed LLVM symbolic execution graph SCC into a rewrite problem. Log: 
21.16/6.60	Generated rules. Obtained 26 rulesP rules:
21.16/6.60	f_283(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v29, v33, v189, v193, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 99, 100, 98) -> f_285(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v33, v29, v193, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 99, 100, 98) :|: 0 = 0
21.16/6.60	f_285(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v33, v29, v193, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 99, 100, 98) -> f_287(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v33, v29, v193, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 98, 99) :|: v189 < 100 && v29 <= 98
21.16/6.60	f_287(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v33, v29, v193, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 98, 99) -> f_290(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v33, v29, v193, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 98, 99) :|: 0 = 0
21.16/6.60	f_290(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v33, v29, v193, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 98, 99) -> f_293(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v33, v29, v193, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 98, 99) :|: TRUE
21.16/6.60	f_293(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v33, v29, v193, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 98, 99) -> f_296(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v33, v29, v193, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 98, 99) :|: 0 = 0
21.16/6.60	f_296(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v33, v29, v193, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 98, 99) -> f_299(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v193, v29, v33, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 98, 99) :|: 0 = 0
21.16/6.60	f_299(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v193, v29, v33, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 98, 99) -> f_302(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v193, v29, v33, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 98, 99) :|: 0 = 0
21.16/6.60	f_302(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v193, v29, v33, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 98, 99) -> f_305(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v193, v29, v33, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 98, 99) :|: 0 = 0
21.16/6.60	f_305(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v193, v29, v33, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 98, 99) -> f_308(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v193, v29, v33, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 98, 99) :|: TRUE
21.16/6.60	f_308(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v193, v29, v33, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 98, 99) -> f_311(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v193, v29, v33, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 98, 99) :|: 0 = 0
21.16/6.60	f_311(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v193, v29, v33, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 98, 99) -> f_313(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v193, v33, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 99, 98) :|: 0 = 0
21.16/6.60	f_313(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v193, v33, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 99, 98) -> f_315(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v193, v33, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 99, 98) :|: 0 = 0
21.16/6.60	f_315(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v193, v33, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 99, 98) -> f_317(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v193, v33, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 99, 98) :|: 0 = 0
21.16/6.60	f_317(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v193, v33, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 99, 98) -> f_319(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v193, v731, v33, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 99, 98, 100) :|: v731 = 1 + v189 && v731 <= 100
21.16/6.60	f_319(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v193, v731, v33, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 99, 98, 100) -> f_321(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v193, v731, v33, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 99, 98, 100) :|: 0 = 0
21.16/6.60	f_321(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v193, v731, v33, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 99, 98, 100) -> f_323(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v193, v731, v33, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 99, 98, 100) :|: TRUE
21.16/6.60	f_323(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v193, v731, v33, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 99, 98, 100) -> f_325(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v193, v731, v33, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 99, 98, 100) :|: 0 = 0
21.16/6.60	f_325(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v193, v731, v33, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 99, 98, 100) -> f_327(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v193, v731, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 99, 98, 100) :|: 0 = 0
21.16/6.60	f_327(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v193, v731, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 99, 98, 100) -> f_329(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v193, v731, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 99, 98, 100) :|: 0 = 0
21.16/6.60	f_329(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v193, v731, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 99, 98, 100) -> f_331(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v193, v731, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 99, 98, 100) :|: 0 = 0
21.16/6.60	f_331(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v193, v731, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 99, 98, 100) -> f_333(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v193, v731, v735, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 99, 98, 100, 97) :|: 1 + v735 = v193 && v735 <= 97
21.16/6.60	f_333(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v193, v731, v735, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 99, 98, 100, 97) -> f_335(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v193, v731, v735, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 99, 98, 100, 97) :|: 0 = 0
21.16/6.60	f_335(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v193, v731, v735, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 99, 98, 100, 97) -> f_337(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v193, v731, v735, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 99, 98, 100, 97) :|: TRUE
21.16/6.60	f_337(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v193, v731, v735, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 99, 98, 100, 97) -> f_339(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v193, v731, v735, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 99, 98, 100, 97) :|: TRUE
21.16/6.60	f_339(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v193, v731, v735, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 99, 98, 100, 97) -> f_281(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v189, v193, v731, v735, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 99, 100, 98) :|: TRUE
21.16/6.60	f_281(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v29, v33, v189, v193, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 99, 100, 98) -> f_283(v1, v3, v5, v7, v9, v11, v13, v16, v19, v22, v25, v28, 1, v29, v33, v189, v193, v2, v4, v6, v8, v10, v12, v14, v17, v20, v23, v26, 0, 3, 7, 4, 8, 99, 100, 98) :|: 0 = 0
21.16/6.60	Combined rules. Obtained 1 rulesP rules:
21.16/6.60	f_283(v1:0, v3:0, v5:0, v7:0, v9:0, v11:0, v13:0, v16:0, v19:0, v22:0, v25:0, v28:0, 1, v29:0, v33:0, v189:0, 1 + v735:0, v2:0, v4:0, v6:0, v8:0, v10:0, v12:0, v14:0, v17:0, v20:0, v23:0, v26:0, 0, 3, 7, 4, 8, 99, 100, 98) -> f_283(v1:0, v3:0, v5:0, v7:0, v9:0, v11:0, v13:0, v16:0, v19:0, v22:0, v25:0, v28:0, 1, v189:0, 1 + v735:0, 1 + v189:0, v735:0, v2:0, v4:0, v6:0, v8:0, v10:0, v12:0, v14:0, v17:0, v20:0, v23:0, v26:0, 0, 3, 7, 4, 8, 99, 100, 98) :|: v29:0 < 99 && v189:0 < 100 && v735:0 < 98
21.16/6.60	Filtered unneeded arguments:
21.16/6.60	   f_283(x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, x16, x17, x18, x19, x20, x21, x22, x23, x24, x25, x26, x27, x28, x29, x30, x31, x32, x33, x34, x35, x36) -> f_283(x14, x16, x17)
21.16/6.60	Removed division, modulo operations, cleaned up constraints. Obtained 1 rules.P rules:
21.16/6.60	f_283(v29:0, v189:0, sum~cons_1~v735:0) -> f_283(v189:0, 1 + v189:0, v735:0) :|: v189:0 < 100 && v735:0 < 98 && v29:0 < 99 && sum~cons_1~v735:0 = 1 + v735:0
21.16/6.60	
21.16/6.60	----------------------------------------
21.16/6.60	
21.16/6.60	(16)
21.16/6.60	Obligation:
21.16/6.60	Rules:
21.16/6.60	f_283(v29:0, v189:0, sum~cons_1~v735:0) -> f_283(v189:0, 1 + v189:0, v735:0) :|: v189:0 < 100 && v735:0 < 98 && v29:0 < 99 && sum~cons_1~v735:0 = 1 + v735:0
21.16/6.60	
21.16/6.60	----------------------------------------
21.16/6.60	
21.16/6.60	(17) IntTRSCompressionProof (EQUIVALENT)
21.16/6.60	Compressed rules.
21.16/6.60	----------------------------------------
21.16/6.60	
21.16/6.60	(18)
21.16/6.60	Obligation:
21.16/6.60	Rules:
21.16/6.60	f_283(v29:0:0, v189:0:0, sum~cons_1~v735:0:0) -> f_283(v189:0:0, 1 + v189:0:0, v735:0:0) :|: v189:0:0 < 100 && v735:0:0 < 98 && v29:0:0 < 99 && sum~cons_1~v735:0:0 = 1 + v735:0:0
21.16/6.60	
21.16/6.60	----------------------------------------
21.16/6.60	
21.16/6.60	(19) RankingReductionPairProof (EQUIVALENT)
21.16/6.60	Interpretation:
21.16/6.60	[ f_283 ] = -1*f_283_2
21.16/6.60	
21.16/6.60	The following rules are decreasing:
21.16/6.60	f_283(v29:0:0, v189:0:0, sum~cons_1~v735:0:0) -> f_283(v189:0:0, 1 + v189:0:0, v735:0:0) :|: v189:0:0 < 100 && v735:0:0 < 98 && v29:0:0 < 99 && sum~cons_1~v735:0:0 = 1 + v735:0:0
21.16/6.60	
21.16/6.60	The following rules are bounded:
21.16/6.60	f_283(v29:0:0, v189:0:0, sum~cons_1~v735:0:0) -> f_283(v189:0:0, 1 + v189:0:0, v735:0:0) :|: v189:0:0 < 100 && v735:0:0 < 98 && v29:0:0 < 99 && sum~cons_1~v735:0:0 = 1 + v735:0:0
21.16/6.60	
21.16/6.60	
21.16/6.60	----------------------------------------
21.16/6.60	
21.16/6.60	(20)
21.16/6.60	YES
21.21/6.69	EOF