41.99/14.21 YES 41.99/14.23 proof of /export/starexec/sandbox/benchmark/theBenchmark.c 41.99/14.23 # AProVE Commit ID: 48fb2092695e11cc9f56e44b17a92a5f88ffb256 marcel 20180622 unpublished dirty 41.99/14.23 41.99/14.23 41.99/14.23 Termination of the given C Problem could be proven: 41.99/14.23 41.99/14.23 (0) C Problem 41.99/14.23 (1) CToLLVMProof [EQUIVALENT, 172 ms] 41.99/14.23 (2) LLVM problem 41.99/14.23 (3) LLVMToTerminationGraphProof [EQUIVALENT, 9078 ms] 41.99/14.23 (4) LLVM Symbolic Execution Graph 41.99/14.23 (5) SymbolicExecutionGraphToSCCProof [SOUND, 5 ms] 41.99/14.23 (6) AND 41.99/14.23 (7) LLVM Symbolic Execution SCC 41.99/14.23 (8) SCC2IRS [SOUND, 159 ms] 41.99/14.23 (9) IntTRS 41.99/14.23 (10) IRS2T2 [EQUIVALENT, 0 ms] 41.99/14.23 (11) T2IntSys 41.99/14.23 (12) T2 [EQUIVALENT, 1303 ms] 41.99/14.23 (13) YES 41.99/14.23 (14) LLVM Symbolic Execution SCC 41.99/14.23 (15) SCC2IRS [SOUND, 81 ms] 41.99/14.23 (16) IntTRS 41.99/14.23 (17) IntTRSCompressionProof [EQUIVALENT, 0 ms] 41.99/14.23 (18) IntTRS 41.99/14.23 (19) RankingReductionPairProof [EQUIVALENT, 25 ms] 41.99/14.23 (20) YES 41.99/14.23 41.99/14.23 41.99/14.23 ---------------------------------------- 41.99/14.23 41.99/14.23 (0) 41.99/14.23 Obligation: 41.99/14.23 c file /export/starexec/sandbox/benchmark/theBenchmark.c 41.99/14.23 ---------------------------------------- 41.99/14.23 41.99/14.23 (1) CToLLVMProof (EQUIVALENT) 41.99/14.23 Compiled c-file /export/starexec/sandbox/benchmark/theBenchmark.c to LLVM. 41.99/14.23 ---------------------------------------- 41.99/14.23 41.99/14.23 (2) 41.99/14.23 Obligation: 41.99/14.23 LLVM Problem 41.99/14.23 41.99/14.23 Aliases: 41.99/14.23 41.99/14.23 Data layout: 41.99/14.23 41.99/14.23 "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" 41.99/14.23 41.99/14.23 Machine: 41.99/14.23 41.99/14.23 "x86_64-pc-linux-gnu" 41.99/14.23 41.99/14.23 Type definitions: 41.99/14.23 41.99/14.23 Global variables: 41.99/14.23 41.99/14.23 Function declarations and definitions: 41.99/14.23 41.99/14.23 *BasicFunctionTypename: "__VERIFIER_nondet_int" returnParam: i32 parameters: () variableLength: false visibilityType: DEFAULT callingConvention: ccc 41.99/14.23 *BasicFunctionTypename: "test_fun" linkageType: EXTERNALLY_VISIBLE returnParam: i32 parameters: (i i32, j i32) variableLength: false visibilityType: DEFAULT callingConvention: ccc 41.99/14.23 0: 41.99/14.23 %1 = alloca i32, align 4 41.99/14.23 %2 = alloca i32, align 4 41.99/14.23 %i_ref = alloca *i32, align 8 41.99/14.23 %j_ref = alloca *i32, align 8 41.99/14.23 %c = alloca *i32, align 8 41.99/14.23 store %i, %1 41.99/14.23 store %j, %2 41.99/14.23 %3 = alloca i8, numElementsLit: 4 41.99/14.23 %4 = bitcast *i8 %3 to *i32 41.99/14.23 store %4, %i_ref 41.99/14.23 %5 = alloca i8, numElementsLit: 4 41.99/14.23 %6 = bitcast *i8 %5 to *i32 41.99/14.23 store %6, %j_ref 41.99/14.23 %7 = alloca i8, numElementsLit: 4 41.99/14.23 %8 = bitcast *i8 %7 to *i32 41.99/14.23 store %8, %c 41.99/14.23 %9 = load %1 41.99/14.23 %10 = load %i_ref 41.99/14.23 store %9, %10 41.99/14.23 %11 = load %2 41.99/14.23 %12 = load %j_ref 41.99/14.23 store %11, %12 41.99/14.23 %13 = load %c 41.99/14.23 store 0, %13 41.99/14.23 br %14 41.99/14.23 14: 41.99/14.23 %15 = load %i_ref 41.99/14.23 %16 = load %15 41.99/14.23 %17 = icmp sge %16 0 41.99/14.23 br %17, %18, %41 41.99/14.23 18: 41.99/14.23 %19 = load %j_ref 41.99/14.23 store 0, %19 41.99/14.23 br %20 41.99/14.23 20: 41.99/14.23 %21 = load %j_ref 41.99/14.23 %22 = load %21 41.99/14.23 %23 = load %i_ref 41.99/14.23 %24 = load %23 41.99/14.23 %25 = sub %24 1 41.99/14.23 %26 = icmp sle %22 %25 41.99/14.23 br %26, %27, %36 41.99/14.23 27: 41.99/14.23 %28 = load %j_ref 41.99/14.23 %29 = load %28 41.99/14.23 %30 = add %29 1 41.99/14.23 %31 = load %j_ref 41.99/14.23 store %30, %31 41.99/14.23 %32 = load %c 41.99/14.23 %33 = load %32 41.99/14.23 %34 = add %33 1 41.99/14.23 %35 = load %c 41.99/14.23 store %34, %35 41.99/14.23 br %20 41.99/14.23 36: 41.99/14.23 %37 = load %i_ref 41.99/14.23 %38 = load %37 41.99/14.23 %39 = sub %38 1 41.99/14.23 %40 = load %i_ref 41.99/14.23 store %39, %40 41.99/14.23 br %14 41.99/14.23 41: 41.99/14.23 %42 = load %c 41.99/14.23 %43 = load %42 41.99/14.23 ret %43 41.99/14.23 41.99/14.23 *BasicFunctionTypename: "main" linkageType: EXTERNALLY_VISIBLE returnParam: i32 parameters: () variableLength: false visibilityType: DEFAULT callingConvention: ccc 41.99/14.23 0: 41.99/14.23 %1 = alloca i32, align 4 41.99/14.23 store 0, %1 41.99/14.23 %2 = call i32 @__VERIFIER_nondet_int() 41.99/14.23 %3 = call i32 @__VERIFIER_nondet_int() 41.99/14.23 %4 = call i32 @test_fun(i32 %2, i32 %3) 41.99/14.23 ret %4 41.99/14.23 41.99/14.23 41.99/14.23 Analyze Termination of all function calls matching the pattern: 41.99/14.23 main() 41.99/14.23 ---------------------------------------- 41.99/14.23 41.99/14.23 (3) LLVMToTerminationGraphProof (EQUIVALENT) 41.99/14.23 Constructed symbolic execution graph for LLVM program and proved memory safety. 41.99/14.23 ---------------------------------------- 41.99/14.23 41.99/14.23 (4) 41.99/14.23 Obligation: 41.99/14.23 SE Graph 41.99/14.23 ---------------------------------------- 41.99/14.23 41.99/14.23 (5) SymbolicExecutionGraphToSCCProof (SOUND) 41.99/14.23 Splitted symbolic execution graph to 2 SCCs. 41.99/14.23 ---------------------------------------- 41.99/14.23 41.99/14.23 (6) 41.99/14.23 Complex Obligation (AND) 41.99/14.23 41.99/14.23 ---------------------------------------- 41.99/14.23 41.99/14.23 (7) 41.99/14.23 Obligation: 41.99/14.23 SCC 41.99/14.23 ---------------------------------------- 41.99/14.23 41.99/14.23 (8) SCC2IRS (SOUND) 41.99/14.23 Transformed LLVM symbolic execution graph SCC into a rewrite problem. Log: 41.99/14.23 Generated rules. Obtained 46 rulesP rules: 41.99/14.23 f_713(v901, v902, v903, v904, v905, v906, v907, v908, v909, v910, v911, 1, v913, 0, v915, v916, v917, v918, v919, v920, v921, v922, v923, v924, v925, v926, v927, v928, 3, 7, 4, 8) -> f_714(v901, v902, v903, v904, v905, v906, v907, v908, v909, v910, v911, 1, 0, v913, v915, v916, v917, v918, v919, v920, v921, v922, v923, v924, v925, v926, v927, v928, 3, 7, 4, 8) :|: 0 = 0 41.99/14.23 f_714(v901, v902, v903, v904, v905, v906, v907, v908, v909, v910, v911, 1, 0, v913, v915, v916, v917, v918, v919, v920, v921, v922, v923, v924, v925, v926, v927, v928, 3, 7, 4, 8) -> f_715(v901, v902, v903, v904, v905, v906, v907, v908, v909, v910, v911, 1, 0, v913, v915, v916, v917, v918, v919, v920, v921, v922, v923, v924, v925, v926, v927, v928, 3, 7, 4, 8) :|: 0 = 0 41.99/14.23 f_715(v901, v902, v903, v904, v905, v906, v907, v908, v909, v910, v911, 1, 0, v913, v915, v916, v917, v918, v919, v920, v921, v922, v923, v924, v925, v926, v927, v928, 3, 7, 4, 8) -> f_716(v901, v902, v903, v904, v905, v906, v907, v908, v909, v910, v911, 1, 0, v915, v916, v917, v918, v913, v919, v920, v921, v922, v923, v924, v925, v926, v927, v928, 3, 7, 4, 8) :|: 0 = 0 41.99/14.23 f_716(v901, v902, v903, v904, v905, v906, v907, v908, v909, v910, v911, 1, 0, v915, v916, v917, v918, v913, v919, v920, v921, v922, v923, v924, v925, v926, v927, v928, 3, 7, 4, 8) -> f_717(v901, v902, v903, v904, v905, v906, v907, v908, v909, v910, v911, 1, 0, v944, v915, v916, v917, v918, v913, v919, v920, v921, v922, v923, v924, v925, v926, v927, v928, 3, 7, 4, 8) :|: 1 + v944 = v911 && 0 <= 1 + v944 41.99/14.23 f_717(v901, v902, v903, v904, v905, v906, v907, v908, v909, v910, v911, 1, 0, v944, v915, v916, v917, v918, v913, v919, v920, v921, v922, v923, v924, v925, v926, v927, v928, 3, 7, 4, 8) -> f_718(v901, v902, v903, v904, v905, v906, v907, v908, v909, v910, v911, 1, 0, v944, v915, v916, v917, v918, v913, v919, v920, v921, v922, v923, v924, v925, v926, v927, v928, 3, 7, 2, 4, 8) :|: 0 <= v944 && 1 <= v911 && 2 <= v913 && 2 <= v901 && 2 <= v916 && 1 <= v915 && 2 <= v918 && 1 <= v917 41.99/14.23 f_718(v901, v902, v903, v904, v905, v906, v907, v908, v909, v910, v911, 1, 0, v944, v915, v916, v917, v918, v913, v919, v920, v921, v922, v923, v924, v925, v926, v927, v928, 3, 7, 2, 4, 8) -> f_720(v901, v902, v903, v904, v905, v906, v907, v908, v909, v910, v911, 1, 0, v944, v915, v916, v917, v918, v913, v919, v920, v921, v922, v923, v924, v925, v926, v927, v928, 3, 7, 2, 4, 8) :|: 0 = 0 41.99/14.23 f_720(v901, v902, v903, v904, v905, v906, v907, v908, v909, v910, v911, 1, 0, v944, v915, v916, v917, v918, v913, v919, v920, v921, v922, v923, v924, v925, v926, v927, v928, 3, 7, 2, 4, 8) -> f_722(v901, v902, v903, v904, v905, v906, v907, v908, v909, v910, v911, 1, 0, v944, v915, v916, v917, v918, v913, v919, v920, v921, v922, v923, v924, v925, v926, v927, v928, 3, 7, 2, 4, 8) :|: TRUE 41.99/14.23 f_722(v901, v902, v903, v904, v905, v906, v907, v908, v909, v910, v911, 1, 0, v944, v915, v916, v917, v918, v913, v919, v920, v921, v922, v923, v924, v925, v926, v927, v928, 3, 7, 2, 4, 8) -> f_723(v901, v902, v903, v904, v905, v906, v907, v908, v909, v910, v911, 1, 0, v944, v915, v916, v917, v918, v913, v919, v920, v921, v922, v923, v924, v925, v926, v927, v928, 0, 3, 7, 2, 4, 8) :|: TRUE 41.99/14.23 f_723(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v973, 1, v975, v976, v977, v978, v979, v980, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 0, 3, 7, 2, 4, 8) -> f_725(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v973, 1, v975, v976, v977, v978, v979, v980, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 0, 3, 7, 2, 4, 8) :|: 0 = 0 41.99/14.23 f_725(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v973, 1, v975, v976, v977, v978, v979, v980, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 0, 3, 7, 2, 4, 8) -> f_727(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v973, 1, v975, v976, v978, v979, v980, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 0, 3, 7, 2, 4, 8) :|: 0 = 0 41.99/14.23 f_727(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v973, 1, v975, v976, v978, v979, v980, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 0, 3, 7, 2, 4, 8) -> f_729(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v973, 1, v975, v976, v1003, v979, v980, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 0, 3, 7, 2, 4, 8) :|: v1003 = 1 + v975 && 1 <= v1003 41.99/14.23 f_729(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v973, 1, v975, v976, v1003, v979, v980, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 0, 3, 7, 2, 4, 8) -> f_731(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v973, 1, v975, v976, v1003, v979, v980, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 0, 3, 7, 2, 4, 8) :|: 0 = 0 41.99/14.23 f_731(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v973, 1, v975, v976, v1003, v979, v980, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 0, 3, 7, 2, 4, 8) -> f_733(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v973, 1, v975, v976, v1003, v979, v980, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 0, 3, 7, 2, 4, 8) :|: TRUE 41.99/14.23 f_733(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v973, 1, v975, v976, v1003, v979, v980, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 0, 3, 7, 2, 4, 8) -> f_735(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v973, 1, v975, v976, v1003, v979, v980, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 0, 3, 7, 2, 4, 8) :|: 0 = 0 41.99/14.23 f_735(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v973, 1, v975, v976, v1003, v979, v980, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 0, 3, 7, 2, 4, 8) -> f_737(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v973, 1, v975, v976, v1003, v980, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 0, 3, 7, 2, 4, 8) :|: 0 = 0 41.99/14.23 f_737(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v973, 1, v975, v976, v1003, v980, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 0, 3, 7, 2, 4, 8) -> f_739(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v973, 1, v975, v976, v1003, v980, v1021, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 0, 3, 7, 2, 4, 8) :|: v1021 = 1 + v980 && 3 <= v1021 41.99/14.23 f_739(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v973, 1, v975, v976, v1003, v980, v1021, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 0, 3, 7, 2, 4, 8) -> f_741(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v973, 1, v975, v976, v1003, v980, v1021, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 0, 3, 7, 2, 4, 8) :|: 0 = 0 41.99/14.23 f_741(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v973, 1, v975, v976, v1003, v980, v1021, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 0, 3, 7, 2, 4, 8) -> f_743(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v973, 1, v975, v976, v1003, v980, v1021, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 0, 3, 7, 2, 4, 8) :|: TRUE 41.99/14.23 f_743(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v973, 1, v975, v976, v1003, v980, v1021, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 0, 3, 7, 2, 4, 8) -> f_745(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v973, 1, v975, v976, v1003, v980, v1021, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 0, 3, 7, 2, 4, 8) :|: TRUE 41.99/14.23 f_745(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v973, 1, v975, v976, v1003, v980, v1021, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 0, 3, 7, 2, 4, 8) -> f_747(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v973, 1, v975, v976, v1003, v980, v1021, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 0, 3, 7, 2, 4, 8) :|: 0 = 0 41.99/14.23 f_747(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v973, 1, v975, v976, v1003, v980, v1021, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 0, 3, 7, 2, 4, 8) -> f_749(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v973, 1, v1003, v976, v975, v980, v1021, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 0, 3, 7, 2, 4, 8) :|: 0 = 0 41.99/14.23 f_749(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v973, 1, v1003, v976, v975, v980, v1021, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 0, 3, 7, 2, 4, 8) -> f_751(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v973, 1, v1003, v976, v975, v980, v1021, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 0, 3, 7, 2, 4, 8) :|: 0 = 0 41.99/14.23 f_751(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v973, 1, v1003, v976, v975, v980, v1021, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 0, 3, 7, 2, 4, 8) -> f_752(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v973, 1, v1003, v976, v975, v980, v1021, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 0, 3, 7, 2, 4, 8) :|: 0 = 0 41.99/14.23 f_752(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v973, 1, v1003, v976, v975, v980, v1021, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 0, 3, 7, 2, 4, 8) -> f_753(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v973, 1, v1003, v976, v975, v980, v1021, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 0, 3, 7, 2, 4, 8) :|: 1 + v976 = v973 41.99/14.23 f_753(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v973, 1, v1003, v976, v975, v980, v1021, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 0, 3, 7, 2, 4, 8) -> f_754(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v973, 1, v1003, v976, v975, v980, v1021, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 0, 3, 7, 2, 4, 8) :|: v1003 <= v976 && 1 <= v976 && 2 <= v973 && 3 <= v981 && 3 <= v963 && 3 <= v980 && 4 <= v1021 41.99/14.23 f_753(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v973, 1, v1003, v976, v975, v980, v1021, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 0, 3, 7, 2, 4, 8) -> f_755(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v1003, 1, v975, v980, v1021, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 0, 3, 7, 2, 4, 8) :|: v976 < v1003 && v973 = v1003 && v976 = v975 41.99/14.23 f_754(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v973, 1, v1003, v976, v975, v980, v1021, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 0, 3, 7, 2, 4, 8) -> f_756(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v973, 1, v1003, v976, v975, v980, v1021, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 0, 3, 7, 2, 4, 8) :|: 0 = 0 41.99/14.23 f_756(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v973, 1, v1003, v976, v975, v980, v1021, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 0, 3, 7, 2, 4, 8) -> f_758(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v973, 1, v1003, v976, v975, v980, v1021, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 0, 3, 7, 2, 4, 8) :|: TRUE 41.99/14.23 f_758(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v973, 1, v1003, v976, v975, v980, v1021, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 0, 3, 7, 2, 4, 8) -> f_723(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v973, 1, v1003, v976, v975, v1003, v980, v1021, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 0, 3, 7, 2, 4, 8) :|: TRUE 41.99/14.23 f_755(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v1003, 1, v975, v980, v1021, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 0, 3, 7, 2, 4, 8) -> f_757(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v1003, 1, v975, 0, v980, v1021, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 3, 7, 2, 4, 8) :|: 0 = 0 41.99/14.23 f_757(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v1003, 1, v975, 0, v980, v1021, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 3, 7, 2, 4, 8) -> f_759(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v1003, 1, v975, 0, v980, v1021, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 3, 7, 2, 4, 8) :|: TRUE 41.99/14.23 f_759(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v1003, 1, v975, 0, v980, v1021, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 3, 7, 2, 4, 8) -> f_760(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v1003, 1, v975, 0, v980, v1021, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 3, 7, 2, 4, 8) :|: 0 = 0 41.99/14.23 f_760(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v1003, 1, v975, 0, v980, v1021, v981, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 3, 7, 2, 4, 8) -> f_761(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v1003, 1, v975, 0, v980, v1021, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 3, 7, 2, 4, 8) :|: 0 = 0 41.99/14.23 f_761(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v1003, 1, v975, 0, v980, v1021, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 3, 7, 2, 4, 8) -> f_762(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v1003, 1, v975, 0, v980, v1021, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 3, 7, 2, 4, 8) :|: 1 + v975 = v1003 41.99/14.23 f_762(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v1003, 1, v975, 0, v980, v1021, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 3, 7, 2, 4, 8) -> f_763(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v1003, 1, v975, 0, v980, v1021, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 3, 7, 2, 4, 8) :|: 0 = 0 41.99/14.23 f_763(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v1003, 1, v975, 0, v980, v1021, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 3, 7, 2, 4, 8) -> f_764(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v1003, 1, v975, 0, v980, v1021, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 3, 7, 2, 4, 8) :|: TRUE 41.99/14.23 f_764(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v1003, 1, v975, 0, v980, v1021, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 3, 7, 2, 4, 8) -> f_765(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v1003, 1, v975, 0, v980, v1021, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 3, 7, 2, 4, 8) :|: TRUE 41.99/14.23 f_765(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v1003, 1, v975, 0, v980, v1021, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 3, 7, 2, 4, 8) -> f_766(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v1003, 1, v975, 0, v980, v1021, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 3, 7, 2, 4, 8) :|: 0 = 0 41.99/14.23 f_766(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v1003, 1, v975, 0, v980, v1021, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 3, 7, 2, 4, 8) -> f_767(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v975, 1, v1003, 0, v980, v1021, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 3, 7, 2, 4, 8) :|: 0 = 0 41.99/14.23 f_767(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v975, 1, v1003, 0, v980, v1021, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 3, 7, 2, 4, 8) -> f_768(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v975, 1, v1003, 0, v980, v1021, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 3, 7, 2, 4, 8) :|: 0 = 0 41.99/14.23 f_768(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v975, 1, v1003, 0, v980, v1021, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 3, 7, 2, 4, 8) -> f_769(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v975, 1, v1003, 0, v980, v1021, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 3, 7, 2, 4, 8) :|: TRUE 41.99/14.23 f_769(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v975, 1, v1003, 0, v980, v1021, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 3, 7, 2, 4, 8) -> f_770(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v975, 1, v1003, 0, v980, v1021, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 3, 7, 2, 4, 8) :|: 0 = 0 41.99/14.23 f_770(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v975, 1, v1003, 0, v980, v1021, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 3, 7, 2, 4, 8) -> f_771(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v975, 1, v1003, 0, v980, v1021, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 3, 7, 2, 4, 8) :|: TRUE 41.99/14.23 f_771(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v975, 1, v1003, 0, v980, v1021, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 3, 7, 2, 4, 8) -> f_772(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v975, 1, v1003, 0, v980, v1021, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 3, 7, 2, 4, 8) :|: TRUE 41.99/14.23 f_772(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v975, 1, v1003, 0, v980, v1021, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 3, 7, 2, 4, 8) -> f_712(v963, v964, v965, v966, v967, v968, v969, v970, v971, v972, v975, 1, v1003, 0, v975, v1003, v980, v1021, v982, v983, v984, v985, v986, v987, v988, v989, v990, v991, 3, 7, 4, 8) :|: TRUE 41.99/14.23 f_712(v901, v902, v903, v904, v905, v906, v907, v908, v909, v910, v911, 1, v913, 0, v915, v916, v917, v918, v919, v920, v921, v922, v923, v924, v925, v926, v927, v928, 3, 7, 4, 8) -> f_713(v901, v902, v903, v904, v905, v906, v907, v908, v909, v910, v911, 1, v913, 0, v915, v916, v917, v918, v919, v920, v921, v922, v923, v924, v925, v926, v927, v928, 3, 7, 4, 8) :|: 0 = 0 41.99/14.23 Combined rules. Obtained 2 rulesP rules: 41.99/14.23 f_753(v963:0, v964:0, v965:0, v966:0, v967:0, v968:0, v969:0, v970:0, v971:0, v972:0, 1 + (1 + v944:0), 1, 1 + (1 + v944:0), 1 + v944:0, 1 + v944:0, v980:0, v1021:0, v981:0, v982:0, v983:0, v984:0, v985:0, v986:0, v987:0, v988:0, v989:0, v990:0, v991:0, 0, 3, 7, 2, 4, 8) -> f_753(v963:0, v964:0, v965:0, v966:0, v967:0, v968:0, v969:0, v970:0, v971:0, v972:0, 1 + v944:0, 1, 1, v944:0, 0, v1021:0, 1 + v1021:0, 1 + (1 + v944:0), v982:0, v983:0, v984:0, v985:0, v986:0, v987:0, v988:0, v989:0, v990:0, v991:0, 0, 3, 7, 2, 4, 8) :|: v944:0 > -1 && v963:0 > 1 && v1021:0 > 1 && v980:0 > 0 && 1 + v944:0 < 1 + (1 + v944:0) 41.99/14.23 f_753(v963:0, v964:0, v965:0, v966:0, v967:0, v968:0, v969:0, v970:0, v971:0, v972:0, 1 + v976:0, 1, v1003:0, v976:0, v975:0, v980:0, v1021:0, v981:0, v982:0, v983:0, v984:0, v985:0, v986:0, v987:0, v988:0, v989:0, v990:0, v991:0, 0, 3, 7, 2, 4, 8) -> f_753(v963:0, v964:0, v965:0, v966:0, v967:0, v968:0, v969:0, v970:0, v971:0, v972:0, 1 + v976:0, 1, 1 + v1003:0, v976:0, v1003:0, v1021:0, 1 + v1021:0, v981:0, v982:0, v983:0, v984:0, v985:0, v986:0, v987:0, v988:0, v989:0, v990:0, v991:0, 0, 3, 7, 2, 4, 8) :|: v1021:0 > 3 && v1003:0 > -1 && v976:0 > 0 && v976:0 >= v1003:0 && v981:0 > 2 && v980:0 > 2 && v963:0 > 2 41.99/14.23 Filtered unneeded arguments: 41.99/14.23 f_753(x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, x16, x17, x18, x19, x20, x21, x22, x23, x24, x25, x26, x27, x28, x29, x30, x31, x32, x33, x34) -> f_753(x1, x11, x13, x14, x15, x16, x17, x18) 41.99/14.23 Removed division, modulo operations, cleaned up constraints. Obtained 2 rules.P rules: 41.99/14.23 f_753(v963:0, sum~cons_1~sum~cons_1~v944:0, sum~cons_1~sum~cons_1~v944:01, sum~cons_1~v944:0, sum~cons_1~v944:01, v980:0, v1021:0, v981:0) -> f_753(v963:0, 1 + v944:0, 1, v944:0, 0, v1021:0, 1 + v1021:0, 1 + (1 + v944:0)) :|: v963:0 > 1 && v944:0 > -1 && v1021:0 > 1 && 1 + v944:0 < 1 + (1 + v944:0) && v980:0 > 0 && sum~cons_1~sum~cons_1~v944:0 = 1 + (1 + v944:0) && sum~cons_1~sum~cons_1~v944:01 = 1 + (1 + v944:0) && sum~cons_1~v944:0 = 1 + v944:0 && sum~cons_1~v944:01 = 1 + v944:0 41.99/14.23 f_753(v963:0, sum~cons_1~v976:0, v1003:0, v976:0, v975:0, v980:0, v1021:0, v981:0) -> f_753(v963:0, 1 + v976:0, 1 + v1003:0, v976:0, v1003:0, v1021:0, 1 + v1021:0, v981:0) :|: v1003:0 > -1 && v1021:0 > 3 && v976:0 > 0 && v976:0 >= v1003:0 && v981:0 > 2 && v963:0 > 2 && v980:0 > 2 && sum~cons_1~v976:0 = 1 + v976:0 41.99/14.23 41.99/14.23 ---------------------------------------- 41.99/14.23 41.99/14.23 (9) 41.99/14.23 Obligation: 41.99/14.23 Rules: 41.99/14.23 f_753(v963:0, sum~cons_1~sum~cons_1~v944:0, sum~cons_1~sum~cons_1~v944:01, sum~cons_1~v944:0, sum~cons_1~v944:01, v980:0, v1021:0, v981:0) -> f_753(v963:0, 1 + v944:0, 1, v944:0, 0, v1021:0, 1 + v1021:0, 1 + (1 + v944:0)) :|: v963:0 > 1 && v944:0 > -1 && v1021:0 > 1 && 1 + v944:0 < 1 + (1 + v944:0) && v980:0 > 0 && sum~cons_1~sum~cons_1~v944:0 = 1 + (1 + v944:0) && sum~cons_1~sum~cons_1~v944:01 = 1 + (1 + v944:0) && sum~cons_1~v944:0 = 1 + v944:0 && sum~cons_1~v944:01 = 1 + v944:0 41.99/14.23 f_753(x, x1, x2, x3, x4, x5, x6, x7) -> f_753(x, 1 + x3, 1 + x2, x3, x2, x6, 1 + x6, x7) :|: x2 > -1 && x6 > 3 && x3 > 0 && x3 >= x2 && x7 > 2 && x > 2 && x5 > 2 && x1 = 1 + x3 41.99/14.23 41.99/14.23 ---------------------------------------- 41.99/14.23 41.99/14.23 (10) IRS2T2 (EQUIVALENT) 41.99/14.23 Transformed input IRS into an integer transition system.Used the following mapping from defined symbols to location IDs: 41.99/14.23 41.99/14.23 (f_753_8,1) 41.99/14.23 41.99/14.23 ---------------------------------------- 41.99/14.23 41.99/14.23 (11) 41.99/14.23 Obligation: 41.99/14.23 START: 0; 41.99/14.23 41.99/14.23 FROM: 0; 41.99/14.23 TO: 1; 41.99/14.23 41.99/14.23 FROM: 1; 41.99/14.23 oldX0 := x0; 41.99/14.23 oldX1 := x1; 41.99/14.23 oldX2 := x2; 41.99/14.23 oldX3 := x3; 41.99/14.23 oldX4 := x4; 41.99/14.23 oldX5 := x5; 41.99/14.23 oldX6 := x6; 41.99/14.23 oldX7 := x7; 41.99/14.23 oldX8 := oldX1 - 2; 41.99/14.23 assume(oldX0 > 1 && oldX8 > -1 && oldX6 > 1 && 1 + oldX8 < 1 + (1 + oldX8) && oldX5 > 0 && oldX1 = 1 + (1 + oldX8) && oldX2 = 1 + (1 + oldX8) && oldX3 = 1 + oldX8 && oldX4 = 1 + oldX8); 42.23/14.23 x0 := oldX0; 42.23/14.23 x1 := 1 + oldX8; 42.23/14.23 x2 := 1; 42.23/14.23 x3 := oldX1 - 2; 42.23/14.23 x4 := 0; 42.23/14.23 x5 := oldX6; 42.23/14.23 x6 := 1 + oldX6; 42.23/14.23 x7 := 1 + (1 + oldX8); 42.23/14.23 TO: 1; 42.23/14.23 42.23/14.23 FROM: 1; 42.23/14.23 oldX0 := x0; 42.23/14.23 oldX1 := x1; 42.23/14.23 oldX2 := x2; 42.23/14.23 oldX3 := x3; 42.23/14.23 oldX4 := x4; 42.23/14.23 oldX5 := x5; 42.23/14.23 oldX6 := x6; 42.23/14.23 oldX7 := x7; 42.23/14.23 assume(oldX2 > -1 && oldX6 > 3 && oldX3 > 0 && oldX3 >= oldX2 && oldX7 > 2 && oldX0 > 2 && oldX5 > 2 && oldX1 = 1 + oldX3); 42.23/14.23 x0 := oldX0; 42.23/14.23 x1 := 1 + oldX3; 42.23/14.23 x2 := 1 + oldX2; 42.23/14.23 x3 := oldX3; 42.23/14.23 x4 := oldX2; 42.23/14.23 x5 := oldX6; 42.23/14.23 x6 := 1 + oldX6; 42.23/14.23 x7 := oldX7; 42.23/14.23 TO: 1; 42.23/14.23 42.23/14.23 42.23/14.23 ---------------------------------------- 42.23/14.23 42.23/14.23 (12) T2 (EQUIVALENT) 42.23/14.23 Initially, performed program simplifications using lexicographic rank functions: 42.23/14.23 * Removed transitions 1, 4, 5 using the following rank functions: 42.23/14.23 - Rank function 1: 42.23/14.23 RF for loc. 5: x1 42.23/14.23 RF for loc. 6: x1 42.23/14.23 Bound for (chained) transitions 4: 2 42.23/14.23 - Rank function 2: 42.23/14.23 RF for loc. 5: 1-2*x2+2*x3 42.23/14.23 RF for loc. 6: -2*x2+2*x3 42.23/14.23 Bound for (chained) transitions 5: 0 42.23/14.23 - Rank function 3: 42.23/14.23 RF for loc. 5: 0 42.23/14.23 RF for loc. 6: -1 42.23/14.23 Bound for (chained) transitions 1: 0 42.23/14.23 42.23/14.23 ---------------------------------------- 42.23/14.23 42.23/14.23 (13) 42.23/14.23 YES 42.23/14.23 42.23/14.23 ---------------------------------------- 42.23/14.23 42.23/14.23 (14) 42.23/14.23 Obligation: 42.23/14.23 SCC 42.23/14.23 ---------------------------------------- 42.23/14.23 42.23/14.23 (15) SCC2IRS (SOUND) 42.23/14.23 Transformed LLVM symbolic execution graph SCC into a rewrite problem. Log: 42.23/14.23 Generated rules. Obtained 20 rulesP rules: 42.23/14.23 f_477(v174, v175, v176, v177, v178, v179, v180, v181, v182, v183, 1, v185, v186, v187, v188, v189, v190, v191, v192, v193, v194, v195, v196, v197, 0, 3, 7, 4, 8) -> f_478(v174, v175, v176, v177, v178, v179, v180, v181, v182, v183, 1, v187, v186, v185, v188, v189, v190, v191, v192, v193, v194, v195, v196, v197, 0, 3, 7, 4, 8) :|: 0 = 0 42.23/14.23 f_478(v174, v175, v176, v177, v178, v179, v180, v181, v182, v183, 1, v187, v186, v185, v188, v189, v190, v191, v192, v193, v194, v195, v196, v197, 0, 3, 7, 4, 8) -> f_479(v174, v175, v176, v177, v178, v179, v180, v181, v182, v183, 1, v187, v186, v185, v188, v189, v190, v191, v192, v193, v194, v195, v196, v197, 0, 3, 7, 4, 8) :|: 0 = 0 42.23/14.23 f_479(v174, v175, v176, v177, v178, v179, v180, v181, v182, v183, 1, v187, v186, v185, v188, v189, v190, v191, v192, v193, v194, v195, v196, v197, 0, 3, 7, 4, 8) -> f_480(v174, v175, v176, v177, v178, v179, v180, v181, v182, v183, 1, v187, v186, v185, v188, v189, v190, v191, v192, v193, v194, v195, v196, v197, 0, 3, 7, 4, 8) :|: 0 = 0 42.23/14.23 f_480(v174, v175, v176, v177, v178, v179, v180, v181, v182, v183, 1, v187, v186, v185, v188, v189, v190, v191, v192, v193, v194, v195, v196, v197, 0, 3, 7, 4, 8) -> f_481(v174, v175, v176, v177, v178, v179, v180, v181, v182, v183, 1, v187, v186, v185, v188, v189, v190, v191, v192, v193, v194, v195, v196, v197, 0, 3, 7, 4, 8) :|: 1 + v186 = v174 42.23/14.23 f_481(v174, v175, v176, v177, v178, v179, v180, v181, v182, v183, 1, v187, v186, v185, v188, v189, v190, v191, v192, v193, v194, v195, v196, v197, 0, 3, 7, 4, 8) -> f_482(v174, v175, v176, v177, v178, v179, v180, v181, v182, v183, 1, v187, v186, v185, v188, v189, v190, v191, v192, v193, v194, v195, v196, v197, 0, 3, 7, 2, 4, 8) :|: v187 <= v186 && 1 <= v186 && 2 <= v174 42.23/14.23 f_482(v174, v175, v176, v177, v178, v179, v180, v181, v182, v183, 1, v187, v186, v185, v188, v189, v190, v191, v192, v193, v194, v195, v196, v197, 0, 3, 7, 2, 4, 8) -> f_484(v174, v175, v176, v177, v178, v179, v180, v181, v182, v183, 1, v187, v186, v185, v188, v189, v190, v191, v192, v193, v194, v195, v196, v197, 0, 3, 7, 2, 4, 8) :|: 0 = 0 42.23/14.23 f_484(v174, v175, v176, v177, v178, v179, v180, v181, v182, v183, 1, v187, v186, v185, v188, v189, v190, v191, v192, v193, v194, v195, v196, v197, 0, 3, 7, 2, 4, 8) -> f_486(v174, v175, v176, v177, v178, v179, v180, v181, v182, v183, 1, v187, v186, v185, v188, v189, v190, v191, v192, v193, v194, v195, v196, v197, 0, 3, 7, 2, 4, 8) :|: TRUE 42.23/14.23 f_486(v174, v175, v176, v177, v178, v179, v180, v181, v182, v183, 1, v187, v186, v185, v188, v189, v190, v191, v192, v193, v194, v195, v196, v197, 0, 3, 7, 2, 4, 8) -> f_488(v174, v175, v176, v177, v178, v179, v180, v181, v182, v183, 1, v187, v186, v185, v188, v189, v190, v191, v192, v193, v194, v195, v196, v197, 0, 3, 7, 2, 4, 8) :|: 0 = 0 42.23/14.23 f_488(v174, v175, v176, v177, v178, v179, v180, v181, v182, v183, 1, v187, v186, v185, v188, v189, v190, v191, v192, v193, v194, v195, v196, v197, 0, 3, 7, 2, 4, 8) -> f_490(v174, v175, v176, v177, v178, v179, v180, v181, v182, v183, 1, v187, v186, v185, v188, v189, v190, v191, v192, v193, v194, v195, v196, v197, 0, 3, 7, 2, 4, 8) :|: 0 = 0 42.23/14.23 f_490(v174, v175, v176, v177, v178, v179, v180, v181, v182, v183, 1, v187, v186, v185, v188, v189, v190, v191, v192, v193, v194, v195, v196, v197, 0, 3, 7, 2, 4, 8) -> f_492(v174, v175, v176, v177, v178, v179, v180, v181, v182, v183, 1, v187, v186, v199, v185, v188, v189, v190, v191, v192, v193, v194, v195, v196, v197, 0, 3, 7, 2, 4, 8) :|: v199 = 1 + v187 && 2 <= v199 42.23/14.23 f_492(v174, v175, v176, v177, v178, v179, v180, v181, v182, v183, 1, v187, v186, v199, v185, v188, v189, v190, v191, v192, v193, v194, v195, v196, v197, 0, 3, 7, 2, 4, 8) -> f_494(v174, v175, v176, v177, v178, v179, v180, v181, v182, v183, 1, v187, v186, v199, v185, v188, v189, v190, v191, v192, v193, v194, v195, v196, v197, 0, 3, 7, 2, 4, 8) :|: 0 = 0 42.23/14.23 f_494(v174, v175, v176, v177, v178, v179, v180, v181, v182, v183, 1, v187, v186, v199, v185, v188, v189, v190, v191, v192, v193, v194, v195, v196, v197, 0, 3, 7, 2, 4, 8) -> f_496(v174, v175, v176, v177, v178, v179, v180, v181, v182, v183, 1, v187, v186, v199, v185, v188, v189, v190, v191, v192, v193, v194, v195, v196, v197, 0, 3, 7, 2, 4, 8) :|: TRUE 42.23/14.23 f_496(v174, v175, v176, v177, v178, v179, v180, v181, v182, v183, 1, v187, v186, v199, v185, v188, v189, v190, v191, v192, v193, v194, v195, v196, v197, 0, 3, 7, 2, 4, 8) -> f_498(v174, v175, v176, v177, v178, v179, v180, v181, v182, v183, 1, v187, v186, v199, v185, v188, v189, v190, v191, v192, v193, v194, v195, v196, v197, 0, 3, 7, 2, 4, 8) :|: 0 = 0 42.23/14.23 f_498(v174, v175, v176, v177, v178, v179, v180, v181, v182, v183, 1, v187, v186, v199, v185, v188, v189, v190, v191, v192, v193, v194, v195, v196, v197, 0, 3, 7, 2, 4, 8) -> f_500(v174, v175, v176, v177, v178, v179, v180, v181, v182, v183, 1, v187, v186, v199, v188, v189, v190, v191, v192, v193, v194, v195, v196, v197, 0, 3, 7, 2, 4, 8) :|: 0 = 0 42.23/14.23 f_500(v174, v175, v176, v177, v178, v179, v180, v181, v182, v183, 1, v187, v186, v199, v188, v189, v190, v191, v192, v193, v194, v195, v196, v197, 0, 3, 7, 2, 4, 8) -> f_502(v174, v175, v176, v177, v178, v179, v180, v181, v182, v183, 1, v187, v186, v199, v188, v189, v190, v191, v192, v193, v194, v195, v196, v197, 0, 3, 7, 2, 4, 8) :|: v199 = 1 + v187 42.23/14.23 f_502(v174, v175, v176, v177, v178, v179, v180, v181, v182, v183, 1, v187, v186, v199, v188, v189, v190, v191, v192, v193, v194, v195, v196, v197, 0, 3, 7, 2, 4, 8) -> f_504(v174, v175, v176, v177, v178, v179, v180, v181, v182, v183, 1, v187, v186, v199, v188, v189, v190, v191, v192, v193, v194, v195, v196, v197, 0, 3, 7, 2, 4, 8) :|: 0 = 0 42.23/14.23 f_504(v174, v175, v176, v177, v178, v179, v180, v181, v182, v183, 1, v187, v186, v199, v188, v189, v190, v191, v192, v193, v194, v195, v196, v197, 0, 3, 7, 2, 4, 8) -> f_506(v174, v175, v176, v177, v178, v179, v180, v181, v182, v183, 1, v187, v186, v199, v188, v189, v190, v191, v192, v193, v194, v195, v196, v197, 0, 3, 7, 2, 4, 8) :|: TRUE 42.23/14.23 f_506(v174, v175, v176, v177, v178, v179, v180, v181, v182, v183, 1, v187, v186, v199, v188, v189, v190, v191, v192, v193, v194, v195, v196, v197, 0, 3, 7, 2, 4, 8) -> f_508(v174, v175, v176, v177, v178, v179, v180, v181, v182, v183, 1, v187, v186, v199, v188, v189, v190, v191, v192, v193, v194, v195, v196, v197, 0, 3, 7, 2, 4, 8) :|: TRUE 42.23/14.23 f_508(v174, v175, v176, v177, v178, v179, v180, v181, v182, v183, 1, v187, v186, v199, v188, v189, v190, v191, v192, v193, v194, v195, v196, v197, 0, 3, 7, 2, 4, 8) -> f_476(v174, v175, v176, v177, v178, v179, v180, v181, v182, v183, 1, v187, v186, v199, v188, v189, v190, v191, v192, v193, v194, v195, v196, v197, 0, 3, 7, 4, 8) :|: TRUE 42.23/14.23 f_476(v174, v175, v176, v177, v178, v179, v180, v181, v182, v183, 1, v185, v186, v187, v188, v189, v190, v191, v192, v193, v194, v195, v196, v197, 0, 3, 7, 4, 8) -> f_477(v174, v175, v176, v177, v178, v179, v180, v181, v182, v183, 1, v185, v186, v187, v188, v189, v190, v191, v192, v193, v194, v195, v196, v197, 0, 3, 7, 4, 8) :|: 0 = 0 42.23/14.23 Combined rules. Obtained 1 rulesP rules: 42.23/14.23 f_477(1 + v186:0, v175:0, v176:0, v177:0, v178:0, v179:0, v180:0, v181:0, v182:0, v183:0, 1, v185:0, v186:0, v187:0, v188:0, v189:0, v190:0, v191:0, v192:0, v193:0, v194:0, v195:0, v196:0, v197:0, 0, 3, 7, 4, 8) -> f_477(1 + v186:0, v175:0, v176:0, v177:0, v178:0, v179:0, v180:0, v181:0, v182:0, v183:0, 1, v187:0, v186:0, 1 + v187:0, v188:0, v189:0, v190:0, v191:0, v192:0, v193:0, v194:0, v195:0, v196:0, v197:0, 0, 3, 7, 4, 8) :|: v186:0 > 0 && v187:0 <= v186:0 && v187:0 > 0 42.23/14.23 Filtered unneeded arguments: 42.23/14.23 f_477(x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, x16, x17, x18, x19, x20, x21, x22, x23, x24, x25, x26, x27, x28, x29) -> f_477(x1, x13, x14) 42.23/14.23 Removed division, modulo operations, cleaned up constraints. Obtained 1 rules.P rules: 42.23/14.23 f_477(sum~cons_1~v186:0, v186:0, v187:0) -> f_477(1 + v186:0, v186:0, 1 + v187:0) :|: v187:0 <= v186:0 && v187:0 > 0 && v186:0 > 0 && sum~cons_1~v186:0 = 1 + v186:0 42.23/14.23 42.23/14.23 ---------------------------------------- 42.23/14.23 42.23/14.23 (16) 42.23/14.23 Obligation: 42.23/14.23 Rules: 42.23/14.23 f_477(sum~cons_1~v186:0, v186:0, v187:0) -> f_477(1 + v186:0, v186:0, 1 + v187:0) :|: v187:0 <= v186:0 && v187:0 > 0 && v186:0 > 0 && sum~cons_1~v186:0 = 1 + v186:0 42.23/14.23 42.23/14.23 ---------------------------------------- 42.23/14.23 42.23/14.23 (17) IntTRSCompressionProof (EQUIVALENT) 42.23/14.23 Compressed rules. 42.23/14.23 ---------------------------------------- 42.23/14.23 42.23/14.23 (18) 42.23/14.23 Obligation: 42.23/14.23 Rules: 42.23/14.23 f_477(sum~cons_1~v186:0:0, v186:0:0, v187:0:0) -> f_477(1 + v186:0:0, v186:0:0, 1 + v187:0:0) :|: v187:0:0 <= v186:0:0 && v187:0:0 > 0 && v186:0:0 > 0 && sum~cons_1~v186:0:0 = 1 + v186:0:0 42.23/14.23 42.23/14.23 ---------------------------------------- 42.23/14.23 42.23/14.23 (19) RankingReductionPairProof (EQUIVALENT) 42.23/14.23 Interpretation: 42.23/14.23 [ f_477 ] = -1*f_477_3 + f_477_2 42.23/14.23 42.23/14.23 The following rules are decreasing: 42.23/14.23 f_477(sum~cons_1~v186:0:0, v186:0:0, v187:0:0) -> f_477(1 + v186:0:0, v186:0:0, 1 + v187:0:0) :|: v187:0:0 <= v186:0:0 && v187:0:0 > 0 && v186:0:0 > 0 && sum~cons_1~v186:0:0 = 1 + v186:0:0 42.23/14.23 42.23/14.23 The following rules are bounded: 42.23/14.23 f_477(sum~cons_1~v186:0:0, v186:0:0, v187:0:0) -> f_477(1 + v186:0:0, v186:0:0, 1 + v187:0:0) :|: v187:0:0 <= v186:0:0 && v187:0:0 > 0 && v186:0:0 > 0 && sum~cons_1~v186:0:0 = 1 + v186:0:0 42.23/14.23 42.23/14.23 42.23/14.23 ---------------------------------------- 42.23/14.23 42.23/14.23 (20) 42.23/14.23 YES 42.24/14.29 EOF