45.60/14.38 YES 45.60/14.39 proof of /export/starexec/sandbox/benchmark/theBenchmark.c 45.60/14.39 # AProVE Commit ID: 48fb2092695e11cc9f56e44b17a92a5f88ffb256 marcel 20180622 unpublished dirty 45.60/14.39 45.60/14.39 45.60/14.39 Termination of the given C Problem could be proven: 45.60/14.39 45.60/14.39 (0) C Problem 45.60/14.39 (1) CToLLVMProof [EQUIVALENT, 174 ms] 45.60/14.39 (2) LLVM problem 45.60/14.39 (3) LLVMToTerminationGraphProof [EQUIVALENT, 8708 ms] 45.60/14.39 (4) LLVM Symbolic Execution Graph 45.60/14.39 (5) SymbolicExecutionGraphToSCCProof [SOUND, 0 ms] 45.60/14.39 (6) AND 45.60/14.39 (7) LLVM Symbolic Execution SCC 45.60/14.39 (8) SCC2IRS [SOUND, 106 ms] 45.60/14.39 (9) IntTRS 45.60/14.39 (10) IntTRSCompressionProof [EQUIVALENT, 0 ms] 45.60/14.39 (11) IntTRS 45.60/14.39 (12) RankingReductionPairProof [EQUIVALENT, 7 ms] 45.60/14.39 (13) YES 45.60/14.39 (14) LLVM Symbolic Execution SCC 45.60/14.39 (15) SCC2IRS [SOUND, 119 ms] 45.60/14.39 (16) IntTRS 45.60/14.39 (17) IntTRSCompressionProof [EQUIVALENT, 0 ms] 45.60/14.39 (18) IntTRS 45.60/14.39 (19) RankingReductionPairProof [EQUIVALENT, 26 ms] 45.60/14.39 (20) YES 45.60/14.39 (21) LLVM Symbolic Execution SCC 45.60/14.39 (22) SCC2IRS [SOUND, 70 ms] 45.60/14.39 (23) IntTRS 45.60/14.39 (24) IntTRSCompressionProof [EQUIVALENT, 1 ms] 45.60/14.39 (25) IntTRS 45.60/14.39 (26) RankingReductionPairProof [EQUIVALENT, 7 ms] 45.60/14.39 (27) YES 45.60/14.39 45.60/14.39 45.60/14.39 ---------------------------------------- 45.60/14.39 45.60/14.39 (0) 45.60/14.39 Obligation: 45.60/14.39 c file /export/starexec/sandbox/benchmark/theBenchmark.c 45.60/14.39 ---------------------------------------- 45.60/14.39 45.60/14.39 (1) CToLLVMProof (EQUIVALENT) 45.60/14.39 Compiled c-file /export/starexec/sandbox/benchmark/theBenchmark.c to LLVM. 45.60/14.39 ---------------------------------------- 45.60/14.39 45.60/14.39 (2) 45.60/14.39 Obligation: 45.60/14.39 LLVM Problem 45.60/14.39 45.60/14.39 Aliases: 45.60/14.39 45.60/14.39 Data layout: 45.60/14.39 45.60/14.39 "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" 45.60/14.39 45.60/14.39 Machine: 45.60/14.39 45.60/14.39 "x86_64-pc-linux-gnu" 45.60/14.39 45.60/14.39 Type definitions: 45.60/14.39 45.60/14.39 Global variables: 45.60/14.39 45.60/14.39 Function declarations and definitions: 45.60/14.39 45.60/14.39 *BasicFunctionTypename: "__VERIFIER_nondet_int" returnParam: i32 parameters: () variableLength: false visibilityType: DEFAULT callingConvention: ccc 45.60/14.39 *BasicFunctionTypename: "test_fun" linkageType: EXTERNALLY_VISIBLE returnParam: i32 parameters: (x i32, y i32) variableLength: false visibilityType: DEFAULT callingConvention: ccc 45.60/14.39 0: 45.60/14.39 %1 = alloca i32, align 4 45.60/14.39 %2 = alloca i32, align 4 45.60/14.39 %x_ref = alloca *i32, align 8 45.60/14.39 %y_ref = alloca *i32, align 8 45.60/14.39 %c = alloca *i32, align 8 45.60/14.39 store %x, %1 45.60/14.39 store %y, %2 45.60/14.39 %3 = alloca i8, numElementsLit: 4 45.60/14.39 %4 = bitcast *i8 %3 to *i32 45.60/14.39 store %4, %x_ref 45.60/14.39 %5 = alloca i8, numElementsLit: 4 45.60/14.39 %6 = bitcast *i8 %5 to *i32 45.60/14.39 store %6, %y_ref 45.60/14.39 %7 = alloca i8, numElementsLit: 4 45.60/14.39 %8 = bitcast *i8 %7 to *i32 45.60/14.39 store %8, %c 45.60/14.39 %9 = load %1 45.60/14.39 %10 = load %x_ref 45.60/14.39 store %9, %10 45.60/14.39 %11 = load %2 45.60/14.39 %12 = load %y_ref 45.60/14.39 store %11, %12 45.60/14.39 %13 = load %c 45.60/14.39 store 0, %13 45.60/14.39 br %14 45.60/14.39 14: 45.60/14.39 %15 = load %x_ref 45.60/14.39 %16 = load %15 45.60/14.39 %17 = icmp sgt %16 0 45.60/14.39 br %17, %18, %41 45.60/14.39 18: 45.60/14.39 br %19 45.60/14.39 19: 45.60/14.39 %20 = load %y_ref 45.60/14.39 %21 = load %20 45.60/14.39 %22 = icmp sgt %21 0 45.60/14.39 br %22, %23, %32 45.60/14.39 23: 45.60/14.39 %24 = load %y_ref 45.60/14.39 %25 = load %24 45.60/14.39 %26 = sub %25 1 45.60/14.39 %27 = load %y_ref 45.60/14.39 store %26, %27 45.60/14.39 %28 = load %c 45.60/14.39 %29 = load %28 45.60/14.39 %30 = add %29 1 45.60/14.39 %31 = load %c 45.60/14.39 store %30, %31 45.60/14.39 br %19 45.60/14.39 32: 45.60/14.39 %33 = load %x_ref 45.60/14.39 %34 = load %33 45.60/14.39 %35 = sub %34 1 45.60/14.39 %36 = load %x_ref 45.60/14.39 store %35, %36 45.60/14.39 %37 = load %c 45.60/14.39 %38 = load %37 45.60/14.39 %39 = add %38 1 45.60/14.39 %40 = load %c 45.60/14.39 store %39, %40 45.60/14.39 br %14 45.60/14.39 41: 45.60/14.39 %42 = load %c 45.60/14.39 %43 = load %42 45.60/14.39 ret %43 45.60/14.39 45.60/14.39 *BasicFunctionTypename: "main" linkageType: EXTERNALLY_VISIBLE returnParam: i32 parameters: () variableLength: false visibilityType: DEFAULT callingConvention: ccc 45.60/14.39 0: 45.60/14.39 %1 = alloca i32, align 4 45.60/14.39 store 0, %1 45.60/14.39 %2 = call i32 @__VERIFIER_nondet_int() 45.60/14.39 %3 = call i32 @__VERIFIER_nondet_int() 45.60/14.39 %4 = call i32 @test_fun(i32 %2, i32 %3) 45.60/14.39 ret %4 45.60/14.39 45.60/14.39 45.60/14.39 Analyze Termination of all function calls matching the pattern: 45.60/14.39 main() 45.60/14.39 ---------------------------------------- 45.60/14.39 45.60/14.39 (3) LLVMToTerminationGraphProof (EQUIVALENT) 45.60/14.39 Constructed symbolic execution graph for LLVM program and proved memory safety. 45.60/14.39 ---------------------------------------- 45.60/14.39 45.60/14.39 (4) 45.60/14.39 Obligation: 45.60/14.39 SE Graph 45.60/14.39 ---------------------------------------- 45.60/14.39 45.60/14.39 (5) SymbolicExecutionGraphToSCCProof (SOUND) 45.60/14.39 Splitted symbolic execution graph to 3 SCCs. 45.60/14.39 ---------------------------------------- 45.60/14.39 45.60/14.39 (6) 45.60/14.39 Complex Obligation (AND) 45.60/14.39 45.60/14.39 ---------------------------------------- 45.60/14.39 45.60/14.39 (7) 45.60/14.39 Obligation: 45.60/14.39 SCC 45.60/14.39 ---------------------------------------- 45.60/14.39 45.60/14.39 (8) SCC2IRS (SOUND) 45.60/14.39 Transformed LLVM symbolic execution graph SCC into a rewrite problem. Log: 45.60/14.39 Generated rules. Obtained 22 rulesP rules: 45.60/14.39 f_733(v717, v718, v719, v720, v721, v722, v723, v724, v725, v726, v727, 1, 0, v730, v731, v732, v733, v734, v735, v736, v737, v738, v739, v740, v741, v742, v743, v744, 3, 7, 2, 4, 8) -> f_734(v717, v718, v719, v720, v721, v722, v723, v724, v725, v726, v732, 1, 0, v730, v731, v727, v733, v734, v735, v736, v737, v738, v739, v740, v741, v742, v743, v744, 3, 7, 2, 4, 8) :|: 0 = 0 45.60/14.39 f_734(v717, v718, v719, v720, v721, v722, v723, v724, v725, v726, v732, 1, 0, v730, v731, v727, v733, v734, v735, v736, v737, v738, v739, v740, v741, v742, v743, v744, 3, 7, 2, 4, 8) -> f_735(v717, v718, v719, v720, v721, v722, v723, v724, v725, v726, v732, 1, 0, v730, v731, v727, v733, v734, v735, v736, v737, v738, v739, v740, v741, v742, v743, v744, 3, 7, 2, 4, 8) :|: 0 < v732 && 2 <= v727 && 2 <= v717 45.60/14.39 f_735(v717, v718, v719, v720, v721, v722, v723, v724, v725, v726, v732, 1, 0, v730, v731, v727, v733, v734, v735, v736, v737, v738, v739, v740, v741, v742, v743, v744, 3, 7, 2, 4, 8) -> f_737(v717, v718, v719, v720, v721, v722, v723, v724, v725, v726, v732, 1, 0, v730, v731, v727, v733, v734, v735, v736, v737, v738, v739, v740, v741, v742, v743, v744, 3, 7, 2, 4, 8) :|: 0 = 0 45.60/14.39 f_737(v717, v718, v719, v720, v721, v722, v723, v724, v725, v726, v732, 1, 0, v730, v731, v727, v733, v734, v735, v736, v737, v738, v739, v740, v741, v742, v743, v744, 3, 7, 2, 4, 8) -> f_739(v717, v718, v719, v720, v721, v722, v723, v724, v725, v726, v732, 1, 0, v730, v731, v727, v733, v734, v735, v736, v737, v738, v739, v740, v741, v742, v743, v744, 3, 7, 2, 4, 8) :|: TRUE 45.60/14.39 f_739(v717, v718, v719, v720, v721, v722, v723, v724, v725, v726, v732, 1, 0, v730, v731, v727, v733, v734, v735, v736, v737, v738, v739, v740, v741, v742, v743, v744, 3, 7, 2, 4, 8) -> f_741(v717, v718, v719, v720, v721, v722, v723, v724, v725, v726, v732, 1, 0, v730, v731, v727, v733, v734, v735, v736, v737, v738, v739, v740, v741, v742, v743, v744, 3, 7, 2, 4, 8) :|: TRUE 45.60/14.39 f_741(v717, v718, v719, v720, v721, v722, v723, v724, v725, v726, v732, 1, 0, v730, v731, v727, v733, v734, v735, v736, v737, v738, v739, v740, v741, v742, v743, v744, 3, 7, 2, 4, 8) -> f_743(v717, v718, v719, v720, v721, v722, v723, v724, v725, v726, v732, 1, 0, v730, v731, v727, v733, v734, v735, v736, v737, v738, v739, v740, v741, v742, v743, v744, 3, 7, 2, 4, 8) :|: 0 = 0 45.60/14.39 f_743(v717, v718, v719, v720, v721, v722, v723, v724, v725, v726, v732, 1, 0, v730, v731, v727, v733, v734, v735, v736, v737, v738, v739, v740, v741, v742, v743, v744, 3, 7, 2, 4, 8) -> f_745(v717, v718, v719, v720, v721, v722, v723, v724, v725, v726, v732, 1, 0, v730, v731, v727, v733, v734, v735, v736, v737, v738, v739, v740, v741, v742, v743, v744, 3, 7, 2, 4, 8) :|: 0 = 0 45.60/14.39 f_745(v717, v718, v719, v720, v721, v722, v723, v724, v725, v726, v732, 1, 0, v730, v731, v727, v733, v734, v735, v736, v737, v738, v739, v740, v741, v742, v743, v744, 3, 7, 2, 4, 8) -> f_747(v717, v718, v719, v720, v721, v722, v723, v724, v725, v726, v732, 1, 0, v730, v731, v727, v733, v734, v735, v736, v737, v738, v739, v740, v741, v742, v743, v744, 3, 7, 2, 4, 8) :|: 0 = 0 45.60/14.39 f_747(v717, v718, v719, v720, v721, v722, v723, v724, v725, v726, v732, 1, 0, v730, v731, v727, v733, v734, v735, v736, v737, v738, v739, v740, v741, v742, v743, v744, 3, 7, 2, 4, 8) -> f_748(v717, v718, v719, v720, v721, v722, v723, v724, v725, v726, v732, 1, 0, v730, v731, v727, v733, v734, v735, v736, v737, v738, v739, v740, v741, v742, v743, v744, 3, 7, 2, 4, 8) :|: TRUE 45.60/14.39 f_748(v717, v718, v719, v720, v721, v722, v723, v724, v725, v726, v732, 1, 0, v730, v731, v727, v733, v734, v735, v736, v737, v738, v739, v740, v741, v742, v743, v744, 3, 7, 2, 4, 8) -> f_749(v717, v718, v719, v720, v721, v722, v723, v724, v725, v726, v732, 1, 0, v730, v731, v727, v733, v734, v735, v736, v737, v738, v739, v740, v741, v742, v743, v744, 3, 7, 2, 4, 8) :|: 0 = 0 45.60/14.39 f_749(v717, v718, v719, v720, v721, v722, v723, v724, v725, v726, v732, 1, 0, v730, v731, v727, v733, v734, v735, v736, v737, v738, v739, v740, v741, v742, v743, v744, 3, 7, 2, 4, 8) -> f_750(v717, v718, v719, v720, v721, v722, v723, v724, v725, v726, v732, 1, 0, v730, v731, v733, v734, v735, v736, v737, v738, v739, v740, v741, v742, v743, v744, 3, 7, 2, 4, 8) :|: 0 = 0 45.60/14.39 f_750(v717, v718, v719, v720, v721, v722, v723, v724, v725, v726, v732, 1, 0, v730, v731, v733, v734, v735, v736, v737, v738, v739, v740, v741, v742, v743, v744, 3, 7, 2, 4, 8) -> f_751(v717, v718, v719, v720, v721, v722, v723, v724, v725, v726, v732, 1, 0, v730, v731, v771, v733, v734, v735, v736, v737, v738, v739, v740, v741, v742, v743, v744, 3, 7, 2, 4, 8) :|: 1 + v771 = v732 && 0 <= v771 45.60/14.39 f_751(v717, v718, v719, v720, v721, v722, v723, v724, v725, v726, v732, 1, 0, v730, v731, v771, v733, v734, v735, v736, v737, v738, v739, v740, v741, v742, v743, v744, 3, 7, 2, 4, 8) -> f_752(v717, v718, v719, v720, v721, v722, v723, v724, v725, v726, v732, 1, 0, v730, v731, v771, v733, v734, v735, v736, v737, v738, v739, v740, v741, v742, v743, v744, 3, 7, 2, 4, 8) :|: 0 = 0 45.60/14.39 f_752(v717, v718, v719, v720, v721, v722, v723, v724, v725, v726, v732, 1, 0, v730, v731, v771, v733, v734, v735, v736, v737, v738, v739, v740, v741, v742, v743, v744, 3, 7, 2, 4, 8) -> f_753(v717, v718, v719, v720, v721, v722, v723, v724, v725, v726, v732, 1, 0, v730, v731, v771, v733, v734, v735, v736, v737, v738, v739, v740, v741, v742, v743, v744, 3, 7, 2, 4, 8) :|: TRUE 45.60/14.39 f_753(v717, v718, v719, v720, v721, v722, v723, v724, v725, v726, v732, 1, 0, v730, v731, v771, v733, v734, v735, v736, v737, v738, v739, v740, v741, v742, v743, v744, 3, 7, 2, 4, 8) -> f_754(v717, v718, v719, v720, v721, v722, v723, v724, v725, v726, v732, 1, 0, v730, v731, v771, v733, v734, v735, v736, v737, v738, v739, v740, v741, v742, v743, v744, 3, 7, 2, 4, 8) :|: 0 = 0 45.60/14.39 f_754(v717, v718, v719, v720, v721, v722, v723, v724, v725, v726, v732, 1, 0, v730, v731, v771, v733, v734, v735, v736, v737, v738, v739, v740, v741, v742, v743, v744, 3, 7, 2, 4, 8) -> f_755(v717, v718, v719, v720, v721, v722, v723, v724, v725, v726, v732, 1, 0, v730, v731, v771, v734, v735, v736, v737, v738, v739, v740, v741, v742, v743, v744, 3, 7, 2, 4, 8) :|: 0 = 0 45.60/14.39 f_755(v717, v718, v719, v720, v721, v722, v723, v724, v725, v726, v732, 1, 0, v730, v731, v771, v734, v735, v736, v737, v738, v739, v740, v741, v742, v743, v744, 3, 7, 2, 4, 8) -> f_756(v717, v718, v719, v720, v721, v722, v723, v724, v725, v726, v732, 1, 0, v730, v731, v771, v734, v773, v735, v736, v737, v738, v739, v740, v741, v742, v743, v744, 3, 7, 2, 4, 8) :|: v773 = 1 + v734 && 3 <= v773 45.60/14.39 f_756(v717, v718, v719, v720, v721, v722, v723, v724, v725, v726, v732, 1, 0, v730, v731, v771, v734, v773, v735, v736, v737, v738, v739, v740, v741, v742, v743, v744, 3, 7, 2, 4, 8) -> f_757(v717, v718, v719, v720, v721, v722, v723, v724, v725, v726, v732, 1, 0, v730, v731, v771, v734, v773, v735, v736, v737, v738, v739, v740, v741, v742, v743, v744, 3, 7, 2, 4, 8) :|: 0 = 0 45.60/14.39 f_757(v717, v718, v719, v720, v721, v722, v723, v724, v725, v726, v732, 1, 0, v730, v731, v771, v734, v773, v735, v736, v737, v738, v739, v740, v741, v742, v743, v744, 3, 7, 2, 4, 8) -> f_758(v717, v718, v719, v720, v721, v722, v723, v724, v725, v726, v732, 1, 0, v730, v731, v771, v734, v773, v735, v736, v737, v738, v739, v740, v741, v742, v743, v744, 3, 7, 2, 4, 8) :|: TRUE 45.60/14.39 f_758(v717, v718, v719, v720, v721, v722, v723, v724, v725, v726, v732, 1, 0, v730, v731, v771, v734, v773, v735, v736, v737, v738, v739, v740, v741, v742, v743, v744, 3, 7, 2, 4, 8) -> f_759(v717, v718, v719, v720, v721, v722, v723, v724, v725, v726, v732, 1, 0, v730, v731, v771, v734, v773, v735, v736, v737, v738, v739, v740, v741, v742, v743, v744, 3, 7, 2, 4, 8) :|: TRUE 45.60/14.39 f_759(v717, v718, v719, v720, v721, v722, v723, v724, v725, v726, v732, 1, 0, v730, v731, v771, v734, v773, v735, v736, v737, v738, v739, v740, v741, v742, v743, v744, 3, 7, 2, 4, 8) -> f_732(v717, v718, v719, v720, v721, v722, v723, v724, v725, v726, v732, 1, 0, v730, v731, v771, v734, v773, v735, v736, v737, v738, v739, v740, v741, v742, v743, v744, 3, 7, 2, 4, 8) :|: TRUE 45.60/14.39 f_732(v717, v718, v719, v720, v721, v722, v723, v724, v725, v726, v727, 1, 0, v730, v731, v732, v733, v734, v735, v736, v737, v738, v739, v740, v741, v742, v743, v744, 3, 7, 2, 4, 8) -> f_733(v717, v718, v719, v720, v721, v722, v723, v724, v725, v726, v727, 1, 0, v730, v731, v732, v733, v734, v735, v736, v737, v738, v739, v740, v741, v742, v743, v744, 3, 7, 2, 4, 8) :|: 0 = 0 45.60/14.39 Combined rules. Obtained 1 rulesP rules: 45.60/14.39 f_733(v717:0, v718:0, v719:0, v720:0, v721:0, v722:0, v723:0, v724:0, v725:0, v726:0, v727:0, 1, 0, v730:0, v731:0, 1 + v771:0, v733:0, v734:0, v735:0, v736:0, v737:0, v738:0, v739:0, v740:0, v741:0, v742:0, v743:0, v744:0, 3, 7, 2, 4, 8) -> f_733(v717:0, v718:0, v719:0, v720:0, v721:0, v722:0, v723:0, v724:0, v725:0, v726:0, 1 + v771:0, 1, 0, v730:0, v731:0, v771:0, v734:0, 1 + v734:0, v735:0, v736:0, v737:0, v738:0, v739:0, v740:0, v741:0, v742:0, v743:0, v744:0, 3, 7, 2, 4, 8) :|: v727:0 > 1 && v771:0 > -1 && v717:0 > 1 && v734:0 > 1 45.60/14.39 Filtered unneeded arguments: 45.60/14.39 f_733(x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, x16, x17, x18, x19, x20, x21, x22, x23, x24, x25, x26, x27, x28, x29, x30, x31, x32, x33) -> f_733(x1, x11, x16, x18) 45.60/14.39 Removed division, modulo operations, cleaned up constraints. Obtained 1 rules.P rules: 45.60/14.39 f_733(v717:0, v727:0, sum~cons_1~v771:0, v734:0) -> f_733(v717:0, 1 + v771:0, v771:0, 1 + v734:0) :|: v771:0 > -1 && v727:0 > 1 && v734:0 > 1 && v717:0 > 1 && sum~cons_1~v771:0 = 1 + v771:0 45.60/14.39 45.60/14.39 ---------------------------------------- 45.60/14.39 45.60/14.39 (9) 45.60/14.39 Obligation: 45.60/14.39 Rules: 45.60/14.39 f_733(v717:0, v727:0, sum~cons_1~v771:0, v734:0) -> f_733(v717:0, 1 + v771:0, v771:0, 1 + v734:0) :|: v771:0 > -1 && v727:0 > 1 && v734:0 > 1 && v717:0 > 1 && sum~cons_1~v771:0 = 1 + v771:0 45.60/14.39 45.60/14.39 ---------------------------------------- 45.60/14.39 45.60/14.39 (10) IntTRSCompressionProof (EQUIVALENT) 45.60/14.39 Compressed rules. 45.60/14.39 ---------------------------------------- 45.60/14.39 45.60/14.39 (11) 45.60/14.39 Obligation: 45.60/14.39 Rules: 45.60/14.39 f_733(v717:0:0, v727:0:0, sum~cons_1~v771:0:0, v734:0:0) -> f_733(v717:0:0, 1 + v771:0:0, v771:0:0, 1 + v734:0:0) :|: v734:0:0 > 1 && v717:0:0 > 1 && v727:0:0 > 1 && v771:0:0 > -1 && sum~cons_1~v771:0:0 = 1 + v771:0:0 45.60/14.39 45.60/14.39 ---------------------------------------- 45.60/14.39 45.60/14.39 (12) RankingReductionPairProof (EQUIVALENT) 45.60/14.39 Interpretation: 45.60/14.39 [ f_733 ] = f_733_3 45.60/14.39 45.60/14.39 The following rules are decreasing: 45.60/14.39 f_733(v717:0:0, v727:0:0, sum~cons_1~v771:0:0, v734:0:0) -> f_733(v717:0:0, 1 + v771:0:0, v771:0:0, 1 + v734:0:0) :|: v734:0:0 > 1 && v717:0:0 > 1 && v727:0:0 > 1 && v771:0:0 > -1 && sum~cons_1~v771:0:0 = 1 + v771:0:0 45.60/14.39 45.60/14.39 The following rules are bounded: 45.60/14.39 f_733(v717:0:0, v727:0:0, sum~cons_1~v771:0:0, v734:0:0) -> f_733(v717:0:0, 1 + v771:0:0, v771:0:0, 1 + v734:0:0) :|: v734:0:0 > 1 && v717:0:0 > 1 && v727:0:0 > 1 && v771:0:0 > -1 && sum~cons_1~v771:0:0 = 1 + v771:0:0 45.60/14.39 45.60/14.39 45.60/14.39 ---------------------------------------- 45.60/14.39 45.60/14.39 (13) 45.60/14.39 YES 45.60/14.39 45.60/14.39 ---------------------------------------- 45.60/14.39 45.60/14.39 (14) 45.60/14.39 Obligation: 45.60/14.39 SCC 45.60/14.39 ---------------------------------------- 45.60/14.39 45.60/14.39 (15) SCC2IRS (SOUND) 45.60/14.39 Transformed LLVM symbolic execution graph SCC into a rewrite problem. Log: 45.60/14.39 Generated rules. Obtained 22 rulesP rules: 45.60/14.39 f_671(v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 1, 0, v560, v561, v562, v563, v564, v565, v566, v567, v568, v569, v570, v571, v572, 3, 7, 4, 8) -> f_673(v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v560, 1, 0, v557, v561, v562, v563, v564, v565, v566, v567, v568, v569, v570, v571, v572, 3, 7, 4, 8) :|: 0 = 0 45.60/14.39 f_673(v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v560, 1, 0, v557, v561, v562, v563, v564, v565, v566, v567, v568, v569, v570, v571, v572, 3, 7, 4, 8) -> f_675(v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v560, 1, 0, v557, v561, v562, v563, v564, v565, v566, v567, v568, v569, v570, v571, v572, 3, 7, 2, 4, 8) :|: 0 < v560 && 2 <= v557 && 2 <= v547 45.60/14.39 f_675(v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v560, 1, 0, v557, v561, v562, v563, v564, v565, v566, v567, v568, v569, v570, v571, v572, 3, 7, 2, 4, 8) -> f_678(v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v560, 1, 0, v557, v561, v562, v563, v564, v565, v566, v567, v568, v569, v570, v571, v572, 3, 7, 2, 4, 8) :|: 0 = 0 45.60/14.39 f_678(v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v560, 1, 0, v557, v561, v562, v563, v564, v565, v566, v567, v568, v569, v570, v571, v572, 3, 7, 2, 4, 8) -> f_681(v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v560, 1, 0, v557, v561, v562, v563, v564, v565, v566, v567, v568, v569, v570, v571, v572, 3, 7, 2, 4, 8) :|: TRUE 45.60/14.39 f_681(v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v560, 1, 0, v557, v561, v562, v563, v564, v565, v566, v567, v568, v569, v570, v571, v572, 3, 7, 2, 4, 8) -> f_684(v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v560, 1, 0, v557, v561, v562, v563, v564, v565, v566, v567, v568, v569, v570, v571, v572, 3, 7, 2, 4, 8) :|: TRUE 45.60/14.39 f_684(v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v560, 1, 0, v557, v561, v562, v563, v564, v565, v566, v567, v568, v569, v570, v571, v572, 3, 7, 2, 4, 8) -> f_688(v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v560, 1, 0, v557, v561, v562, v563, v564, v565, v566, v567, v568, v569, v570, v571, v572, 3, 7, 2, 4, 8) :|: 0 = 0 45.60/14.39 f_688(v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v560, 1, 0, v557, v561, v562, v563, v564, v565, v566, v567, v568, v569, v570, v571, v572, 3, 7, 2, 4, 8) -> f_691(v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v560, 1, 0, v557, v561, v562, v563, v564, v565, v566, v567, v568, v569, v570, v571, v572, 3, 7, 2, 4, 8) :|: 0 = 0 45.60/14.39 f_691(v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v560, 1, 0, v557, v561, v562, v563, v564, v565, v566, v567, v568, v569, v570, v571, v572, 3, 7, 2, 4, 8) -> f_694(v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v560, 1, 0, v557, v561, v562, v563, v564, v565, v566, v567, v568, v569, v570, v571, v572, 3, 7, 2, 4, 8) :|: 0 = 0 45.60/14.39 f_694(v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v560, 1, 0, v557, v561, v562, v563, v564, v565, v566, v567, v568, v569, v570, v571, v572, 3, 7, 2, 4, 8) -> f_697(v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v560, 1, 0, v557, v561, v562, v563, v564, v565, v566, v567, v568, v569, v570, v571, v572, 3, 7, 2, 4, 8) :|: TRUE 45.60/14.39 f_697(v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v560, 1, 0, v557, v561, v562, v563, v564, v565, v566, v567, v568, v569, v570, v571, v572, 3, 7, 2, 4, 8) -> f_700(v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v560, 1, 0, v557, v561, v562, v563, v564, v565, v566, v567, v568, v569, v570, v571, v572, 3, 7, 2, 4, 8) :|: 0 = 0 45.60/14.39 f_700(v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v560, 1, 0, v557, v561, v562, v563, v564, v565, v566, v567, v568, v569, v570, v571, v572, 3, 7, 2, 4, 8) -> f_703(v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v560, 1, 0, v561, v562, v563, v564, v565, v566, v567, v568, v569, v570, v571, v572, 3, 7, 2, 4, 8) :|: 0 = 0 45.60/14.39 f_703(v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v560, 1, 0, v561, v562, v563, v564, v565, v566, v567, v568, v569, v570, v571, v572, 3, 7, 2, 4, 8) -> f_706(v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v560, 1, 0, v653, v561, v562, v563, v564, v565, v566, v567, v568, v569, v570, v571, v572, 3, 7, 2, 4, 8) :|: 1 + v653 = v560 && 0 <= v653 45.60/14.39 f_706(v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v560, 1, 0, v653, v561, v562, v563, v564, v565, v566, v567, v568, v569, v570, v571, v572, 3, 7, 2, 4, 8) -> f_709(v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v560, 1, 0, v653, v561, v562, v563, v564, v565, v566, v567, v568, v569, v570, v571, v572, 3, 7, 2, 4, 8) :|: 0 = 0 45.60/14.39 f_709(v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v560, 1, 0, v653, v561, v562, v563, v564, v565, v566, v567, v568, v569, v570, v571, v572, 3, 7, 2, 4, 8) -> f_712(v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v560, 1, 0, v653, v561, v562, v563, v564, v565, v566, v567, v568, v569, v570, v571, v572, 3, 7, 2, 4, 8) :|: TRUE 45.60/14.39 f_712(v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v560, 1, 0, v653, v561, v562, v563, v564, v565, v566, v567, v568, v569, v570, v571, v572, 3, 7, 2, 4, 8) -> f_714(v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v560, 1, 0, v653, v561, v562, v563, v564, v565, v566, v567, v568, v569, v570, v571, v572, 3, 7, 2, 4, 8) :|: 0 = 0 45.60/14.39 f_714(v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v560, 1, 0, v653, v561, v562, v563, v564, v565, v566, v567, v568, v569, v570, v571, v572, 3, 7, 2, 4, 8) -> f_716(v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v560, 1, 0, v653, v562, v563, v564, v565, v566, v567, v568, v569, v570, v571, v572, 3, 7, 2, 4, 8) :|: 0 = 0 45.60/14.39 f_716(v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v560, 1, 0, v653, v562, v563, v564, v565, v566, v567, v568, v569, v570, v571, v572, 3, 7, 2, 4, 8) -> f_718(v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v560, 1, 0, v653, v562, v667, v563, v564, v565, v566, v567, v568, v569, v570, v571, v572, 3, 7, 2, 4, 8) :|: v667 = 1 + v562 && 2 <= v667 45.60/14.39 f_718(v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v560, 1, 0, v653, v562, v667, v563, v564, v565, v566, v567, v568, v569, v570, v571, v572, 3, 7, 2, 4, 8) -> f_720(v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v560, 1, 0, v653, v562, v667, v563, v564, v565, v566, v567, v568, v569, v570, v571, v572, 3, 7, 2, 4, 8) :|: 0 = 0 45.60/14.39 f_720(v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v560, 1, 0, v653, v562, v667, v563, v564, v565, v566, v567, v568, v569, v570, v571, v572, 3, 7, 2, 4, 8) -> f_722(v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v560, 1, 0, v653, v562, v667, v563, v564, v565, v566, v567, v568, v569, v570, v571, v572, 3, 7, 2, 4, 8) :|: TRUE 45.60/14.39 f_722(v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v560, 1, 0, v653, v562, v667, v563, v564, v565, v566, v567, v568, v569, v570, v571, v572, 3, 7, 2, 4, 8) -> f_724(v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v560, 1, 0, v653, v562, v667, v563, v564, v565, v566, v567, v568, v569, v570, v571, v572, 3, 7, 2, 4, 8) :|: TRUE 45.60/14.39 f_724(v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v560, 1, 0, v653, v562, v667, v563, v564, v565, v566, v567, v568, v569, v570, v571, v572, 3, 7, 2, 4, 8) -> f_669(v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v560, 1, 0, v653, v562, v667, v563, v564, v565, v566, v567, v568, v569, v570, v571, v572, 3, 7, 4, 8) :|: TRUE 45.60/14.39 f_669(v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 1, 0, v560, v561, v562, v563, v564, v565, v566, v567, v568, v569, v570, v571, v572, 3, 7, 4, 8) -> f_671(v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 1, 0, v560, v561, v562, v563, v564, v565, v566, v567, v568, v569, v570, v571, v572, 3, 7, 4, 8) :|: 0 = 0 45.60/14.39 Combined rules. Obtained 1 rulesP rules: 45.60/14.39 f_671(v547:0, v548:0, v549:0, v550:0, v551:0, v552:0, v553:0, v554:0, v555:0, v556:0, v557:0, 1, 0, 1 + v653:0, v561:0, v562:0, v563:0, v564:0, v565:0, v566:0, v567:0, v568:0, v569:0, v570:0, v571:0, v572:0, 3, 7, 4, 8) -> f_671(v547:0, v548:0, v549:0, v550:0, v551:0, v552:0, v553:0, v554:0, v555:0, v556:0, 1 + v653:0, 1, 0, v653:0, v562:0, 1 + v562:0, v563:0, v564:0, v565:0, v566:0, v567:0, v568:0, v569:0, v570:0, v571:0, v572:0, 3, 7, 4, 8) :|: v557:0 > 1 && v653:0 > -1 && v547:0 > 1 && v562:0 > 0 45.60/14.39 Filtered unneeded arguments: 45.60/14.39 f_671(x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, x16, x17, x18, x19, x20, x21, x22, x23, x24, x25, x26, x27, x28, x29, x30) -> f_671(x1, x11, x14, x16) 45.60/14.39 Removed division, modulo operations, cleaned up constraints. Obtained 1 rules.P rules: 45.60/14.39 f_671(v547:0, v557:0, sum~cons_1~v653:0, v562:0) -> f_671(v547:0, 1 + v653:0, v653:0, 1 + v562:0) :|: v653:0 > -1 && v557:0 > 1 && v562:0 > 0 && v547:0 > 1 && sum~cons_1~v653:0 = 1 + v653:0 45.60/14.39 45.60/14.39 ---------------------------------------- 45.60/14.39 45.60/14.39 (16) 45.60/14.39 Obligation: 45.60/14.39 Rules: 45.60/14.39 f_671(v547:0, v557:0, sum~cons_1~v653:0, v562:0) -> f_671(v547:0, 1 + v653:0, v653:0, 1 + v562:0) :|: v653:0 > -1 && v557:0 > 1 && v562:0 > 0 && v547:0 > 1 && sum~cons_1~v653:0 = 1 + v653:0 45.60/14.39 45.60/14.39 ---------------------------------------- 45.60/14.39 45.60/14.39 (17) IntTRSCompressionProof (EQUIVALENT) 45.60/14.39 Compressed rules. 45.60/14.39 ---------------------------------------- 45.60/14.39 45.60/14.39 (18) 45.60/14.39 Obligation: 45.60/14.39 Rules: 45.60/14.39 f_671(v547:0:0, v557:0:0, sum~cons_1~v653:0:0, v562:0:0) -> f_671(v547:0:0, 1 + v653:0:0, v653:0:0, 1 + v562:0:0) :|: v562:0:0 > 0 && v547:0:0 > 1 && v557:0:0 > 1 && v653:0:0 > -1 && sum~cons_1~v653:0:0 = 1 + v653:0:0 45.60/14.39 45.60/14.39 ---------------------------------------- 45.60/14.39 45.60/14.39 (19) RankingReductionPairProof (EQUIVALENT) 45.60/14.39 Interpretation: 45.60/14.39 [ f_671 ] = f_671_3 45.60/14.39 45.60/14.39 The following rules are decreasing: 45.60/14.39 f_671(v547:0:0, v557:0:0, sum~cons_1~v653:0:0, v562:0:0) -> f_671(v547:0:0, 1 + v653:0:0, v653:0:0, 1 + v562:0:0) :|: v562:0:0 > 0 && v547:0:0 > 1 && v557:0:0 > 1 && v653:0:0 > -1 && sum~cons_1~v653:0:0 = 1 + v653:0:0 45.60/14.39 45.60/14.39 The following rules are bounded: 45.60/14.39 f_671(v547:0:0, v557:0:0, sum~cons_1~v653:0:0, v562:0:0) -> f_671(v547:0:0, 1 + v653:0:0, v653:0:0, 1 + v562:0:0) :|: v562:0:0 > 0 && v547:0:0 > 1 && v557:0:0 > 1 && v653:0:0 > -1 && sum~cons_1~v653:0:0 = 1 + v653:0:0 45.60/14.39 45.60/14.39 45.60/14.39 ---------------------------------------- 45.60/14.39 45.60/14.39 (20) 45.60/14.39 YES 45.60/14.39 45.60/14.39 ---------------------------------------- 45.60/14.39 45.60/14.39 (21) 45.60/14.39 Obligation: 45.60/14.39 SCC 45.60/14.39 ---------------------------------------- 45.60/14.39 45.60/14.39 (22) SCC2IRS (SOUND) 45.60/14.39 Transformed LLVM symbolic execution graph SCC into a rewrite problem. Log: 45.60/14.39 Generated rules. Obtained 17 rulesP rules: 45.60/14.39 f_582(v372, v373, v374, v375, v376, v377, v378, v379, v380, v381, 1, v383, v384, v385, v386, v387, v388, v389, v390, v391, v392, v393, v394, v395, v396, 0, 3, 7, 4, 8) -> f_584(v372, v373, v374, v375, v376, v377, v378, v379, v380, v381, 1, v384, v383, v385, v386, v387, v388, v389, v390, v391, v392, v393, v394, v395, v396, 0, 3, 7, 4, 8) :|: 0 = 0 45.60/14.39 f_584(v372, v373, v374, v375, v376, v377, v378, v379, v380, v381, 1, v384, v383, v385, v386, v387, v388, v389, v390, v391, v392, v393, v394, v395, v396, 0, 3, 7, 4, 8) -> f_586(v372, v373, v374, v375, v376, v377, v378, v379, v380, v381, 1, v384, v383, v385, v386, v387, v388, v389, v390, v391, v392, v393, v394, v395, v396, 0, 3, 7, 2, 4, 8) :|: 0 < v384 && 2 <= v383 && 2 <= v373 45.60/14.39 f_586(v372, v373, v374, v375, v376, v377, v378, v379, v380, v381, 1, v384, v383, v385, v386, v387, v388, v389, v390, v391, v392, v393, v394, v395, v396, 0, 3, 7, 2, 4, 8) -> f_589(v372, v373, v374, v375, v376, v377, v378, v379, v380, v381, 1, v384, v383, v385, v386, v387, v388, v389, v390, v391, v392, v393, v394, v395, v396, 0, 3, 7, 2, 4, 8) :|: 0 = 0 45.60/14.39 f_589(v372, v373, v374, v375, v376, v377, v378, v379, v380, v381, 1, v384, v383, v385, v386, v387, v388, v389, v390, v391, v392, v393, v394, v395, v396, 0, 3, 7, 2, 4, 8) -> f_592(v372, v373, v374, v375, v376, v377, v378, v379, v380, v381, 1, v384, v383, v385, v386, v387, v388, v389, v390, v391, v392, v393, v394, v395, v396, 0, 3, 7, 2, 4, 8) :|: TRUE 45.60/14.39 f_592(v372, v373, v374, v375, v376, v377, v378, v379, v380, v381, 1, v384, v383, v385, v386, v387, v388, v389, v390, v391, v392, v393, v394, v395, v396, 0, 3, 7, 2, 4, 8) -> f_595(v372, v373, v374, v375, v376, v377, v378, v379, v380, v381, 1, v384, v383, v385, v386, v387, v388, v389, v390, v391, v392, v393, v394, v395, v396, 0, 3, 7, 2, 4, 8) :|: 0 = 0 45.60/14.39 f_595(v372, v373, v374, v375, v376, v377, v378, v379, v380, v381, 1, v384, v383, v385, v386, v387, v388, v389, v390, v391, v392, v393, v394, v395, v396, 0, 3, 7, 2, 4, 8) -> f_598(v372, v373, v374, v375, v376, v377, v378, v379, v380, v381, 1, v384, v385, v386, v387, v388, v389, v390, v391, v392, v393, v394, v395, v396, 0, 3, 7, 2, 4, 8) :|: 0 = 0 45.60/14.39 f_598(v372, v373, v374, v375, v376, v377, v378, v379, v380, v381, 1, v384, v385, v386, v387, v388, v389, v390, v391, v392, v393, v394, v395, v396, 0, 3, 7, 2, 4, 8) -> f_601(v372, v373, v374, v375, v376, v377, v378, v379, v380, v381, 1, v384, v414, v385, v386, v387, v388, v389, v390, v391, v392, v393, v394, v395, v396, 0, 3, 7, 2, 4, 8) :|: 1 + v414 = v384 && 0 <= v414 45.60/14.39 f_601(v372, v373, v374, v375, v376, v377, v378, v379, v380, v381, 1, v384, v414, v385, v386, v387, v388, v389, v390, v391, v392, v393, v394, v395, v396, 0, 3, 7, 2, 4, 8) -> f_604(v372, v373, v374, v375, v376, v377, v378, v379, v380, v381, 1, v384, v414, v385, v386, v387, v388, v389, v390, v391, v392, v393, v394, v395, v396, 0, 3, 7, 2, 4, 8) :|: 0 = 0 45.60/14.39 f_604(v372, v373, v374, v375, v376, v377, v378, v379, v380, v381, 1, v384, v414, v385, v386, v387, v388, v389, v390, v391, v392, v393, v394, v395, v396, 0, 3, 7, 2, 4, 8) -> f_608(v372, v373, v374, v375, v376, v377, v378, v379, v380, v381, 1, v384, v414, v385, v386, v387, v388, v389, v390, v391, v392, v393, v394, v395, v396, 0, 3, 7, 2, 4, 8) :|: TRUE 45.60/14.39 f_608(v372, v373, v374, v375, v376, v377, v378, v379, v380, v381, 1, v384, v414, v385, v386, v387, v388, v389, v390, v391, v392, v393, v394, v395, v396, 0, 3, 7, 2, 4, 8) -> f_611(v372, v373, v374, v375, v376, v377, v378, v379, v380, v381, 1, v384, v414, v385, v386, v387, v388, v389, v390, v391, v392, v393, v394, v395, v396, 0, 3, 7, 2, 4, 8) :|: 0 = 0 45.60/14.39 f_611(v372, v373, v374, v375, v376, v377, v378, v379, v380, v381, 1, v384, v414, v385, v386, v387, v388, v389, v390, v391, v392, v393, v394, v395, v396, 0, 3, 7, 2, 4, 8) -> f_614(v372, v373, v374, v375, v376, v377, v378, v379, v380, v381, 1, v384, v414, v386, v387, v388, v389, v390, v391, v392, v393, v394, v395, v396, 0, 3, 7, 2, 4, 8) :|: 0 = 0 45.60/14.39 f_614(v372, v373, v374, v375, v376, v377, v378, v379, v380, v381, 1, v384, v414, v386, v387, v388, v389, v390, v391, v392, v393, v394, v395, v396, 0, 3, 7, 2, 4, 8) -> f_618(v372, v373, v374, v375, v376, v377, v378, v379, v380, v381, 1, v384, v414, v386, v445, v387, v388, v389, v390, v391, v392, v393, v394, v395, v396, 0, 3, 7, 2, 4, 8) :|: v445 = 1 + v386 && 2 <= v445 45.60/14.39 f_618(v372, v373, v374, v375, v376, v377, v378, v379, v380, v381, 1, v384, v414, v386, v445, v387, v388, v389, v390, v391, v392, v393, v394, v395, v396, 0, 3, 7, 2, 4, 8) -> f_622(v372, v373, v374, v375, v376, v377, v378, v379, v380, v381, 1, v384, v414, v386, v445, v387, v388, v389, v390, v391, v392, v393, v394, v395, v396, 0, 3, 7, 2, 4, 8) :|: 0 = 0 45.60/14.39 f_622(v372, v373, v374, v375, v376, v377, v378, v379, v380, v381, 1, v384, v414, v386, v445, v387, v388, v389, v390, v391, v392, v393, v394, v395, v396, 0, 3, 7, 2, 4, 8) -> f_626(v372, v373, v374, v375, v376, v377, v378, v379, v380, v381, 1, v384, v414, v386, v445, v387, v388, v389, v390, v391, v392, v393, v394, v395, v396, 0, 3, 7, 2, 4, 8) :|: TRUE 45.60/14.39 f_626(v372, v373, v374, v375, v376, v377, v378, v379, v380, v381, 1, v384, v414, v386, v445, v387, v388, v389, v390, v391, v392, v393, v394, v395, v396, 0, 3, 7, 2, 4, 8) -> f_630(v372, v373, v374, v375, v376, v377, v378, v379, v380, v381, 1, v384, v414, v386, v445, v387, v388, v389, v390, v391, v392, v393, v394, v395, v396, 0, 3, 7, 2, 4, 8) :|: TRUE 45.60/14.39 f_630(v372, v373, v374, v375, v376, v377, v378, v379, v380, v381, 1, v384, v414, v386, v445, v387, v388, v389, v390, v391, v392, v393, v394, v395, v396, 0, 3, 7, 2, 4, 8) -> f_580(v372, v373, v374, v375, v376, v377, v378, v379, v380, v381, 1, v384, v414, v386, v445, v387, v388, v389, v390, v391, v392, v393, v394, v395, v396, 0, 3, 7, 4, 8) :|: TRUE 45.60/14.39 f_580(v372, v373, v374, v375, v376, v377, v378, v379, v380, v381, 1, v383, v384, v385, v386, v387, v388, v389, v390, v391, v392, v393, v394, v395, v396, 0, 3, 7, 4, 8) -> f_582(v372, v373, v374, v375, v376, v377, v378, v379, v380, v381, 1, v383, v384, v385, v386, v387, v388, v389, v390, v391, v392, v393, v394, v395, v396, 0, 3, 7, 4, 8) :|: 0 = 0 45.60/14.39 Combined rules. Obtained 1 rulesP rules: 45.60/14.39 f_582(v372:0, v373:0, v374:0, v375:0, v376:0, v377:0, v378:0, v379:0, v380:0, v381:0, 1, v383:0, 1 + v414:0, v385:0, v386:0, v387:0, v388:0, v389:0, v390:0, v391:0, v392:0, v393:0, v394:0, v395:0, v396:0, 0, 3, 7, 4, 8) -> f_582(v372:0, v373:0, v374:0, v375:0, v376:0, v377:0, v378:0, v379:0, v380:0, v381:0, 1, 1 + v414:0, v414:0, v386:0, 1 + v386:0, v387:0, v388:0, v389:0, v390:0, v391:0, v392:0, v393:0, v394:0, v395:0, v396:0, 0, 3, 7, 4, 8) :|: v383:0 > 1 && v414:0 > -1 && v373:0 > 1 && v386:0 > 0 45.60/14.39 Filtered unneeded arguments: 45.60/14.39 f_582(x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, x16, x17, x18, x19, x20, x21, x22, x23, x24, x25, x26, x27, x28, x29, x30) -> f_582(x2, x12, x13, x15) 45.60/14.39 Removed division, modulo operations, cleaned up constraints. Obtained 1 rules.P rules: 45.60/14.39 f_582(v373:0, v383:0, sum~cons_1~v414:0, v386:0) -> f_582(v373:0, 1 + v414:0, v414:0, 1 + v386:0) :|: v414:0 > -1 && v383:0 > 1 && v386:0 > 0 && v373:0 > 1 && sum~cons_1~v414:0 = 1 + v414:0 45.60/14.39 45.60/14.39 ---------------------------------------- 45.60/14.39 45.60/14.39 (23) 45.60/14.39 Obligation: 45.60/14.39 Rules: 45.60/14.39 f_582(v373:0, v383:0, sum~cons_1~v414:0, v386:0) -> f_582(v373:0, 1 + v414:0, v414:0, 1 + v386:0) :|: v414:0 > -1 && v383:0 > 1 && v386:0 > 0 && v373:0 > 1 && sum~cons_1~v414:0 = 1 + v414:0 45.60/14.39 45.60/14.39 ---------------------------------------- 45.60/14.39 45.60/14.39 (24) IntTRSCompressionProof (EQUIVALENT) 45.60/14.39 Compressed rules. 45.60/14.39 ---------------------------------------- 45.60/14.39 45.60/14.39 (25) 45.60/14.39 Obligation: 45.60/14.39 Rules: 45.60/14.39 f_582(v373:0:0, v383:0:0, sum~cons_1~v414:0:0, v386:0:0) -> f_582(v373:0:0, 1 + v414:0:0, v414:0:0, 1 + v386:0:0) :|: v386:0:0 > 0 && v373:0:0 > 1 && v383:0:0 > 1 && v414:0:0 > -1 && sum~cons_1~v414:0:0 = 1 + v414:0:0 45.60/14.39 45.60/14.39 ---------------------------------------- 45.60/14.39 45.60/14.39 (26) RankingReductionPairProof (EQUIVALENT) 45.60/14.39 Interpretation: 45.60/14.39 [ f_582 ] = f_582_3 45.60/14.39 45.60/14.39 The following rules are decreasing: 45.60/14.39 f_582(v373:0:0, v383:0:0, sum~cons_1~v414:0:0, v386:0:0) -> f_582(v373:0:0, 1 + v414:0:0, v414:0:0, 1 + v386:0:0) :|: v386:0:0 > 0 && v373:0:0 > 1 && v383:0:0 > 1 && v414:0:0 > -1 && sum~cons_1~v414:0:0 = 1 + v414:0:0 45.60/14.39 45.60/14.39 The following rules are bounded: 45.60/14.39 f_582(v373:0:0, v383:0:0, sum~cons_1~v414:0:0, v386:0:0) -> f_582(v373:0:0, 1 + v414:0:0, v414:0:0, 1 + v386:0:0) :|: v386:0:0 > 0 && v373:0:0 > 1 && v383:0:0 > 1 && v414:0:0 > -1 && sum~cons_1~v414:0:0 = 1 + v414:0:0 45.60/14.39 45.60/14.39 45.60/14.39 ---------------------------------------- 45.60/14.39 45.60/14.39 (27) 45.60/14.39 YES 45.75/14.44 EOF