28.46/9.24 YES 28.46/9.26 proof of /export/starexec/sandbox/benchmark/theBenchmark.c 28.46/9.26 # AProVE Commit ID: 48fb2092695e11cc9f56e44b17a92a5f88ffb256 marcel 20180622 unpublished dirty 28.46/9.26 28.46/9.26 28.46/9.26 Termination of the given C Problem could be proven: 28.46/9.26 28.46/9.26 (0) C Problem 28.46/9.26 (1) CToLLVMProof [EQUIVALENT, 174 ms] 28.46/9.26 (2) LLVM problem 28.46/9.26 (3) LLVMToTerminationGraphProof [EQUIVALENT, 5285 ms] 28.46/9.26 (4) LLVM Symbolic Execution Graph 28.46/9.26 (5) SymbolicExecutionGraphToSCCProof [SOUND, 0 ms] 28.46/9.26 (6) LLVM Symbolic Execution SCC 28.46/9.26 (7) SCC2IRS [SOUND, 86 ms] 28.46/9.26 (8) IntTRS 28.46/9.26 (9) IntTRSCompressionProof [EQUIVALENT, 0 ms] 28.46/9.26 (10) IntTRS 28.46/9.26 (11) PolynomialOrderProcessor [EQUIVALENT, 13 ms] 28.46/9.26 (12) YES 28.46/9.26 28.46/9.26 28.46/9.26 ---------------------------------------- 28.46/9.26 28.46/9.26 (0) 28.46/9.26 Obligation: 28.46/9.26 c file /export/starexec/sandbox/benchmark/theBenchmark.c 28.46/9.26 ---------------------------------------- 28.46/9.26 28.46/9.26 (1) CToLLVMProof (EQUIVALENT) 28.46/9.26 Compiled c-file /export/starexec/sandbox/benchmark/theBenchmark.c to LLVM. 28.46/9.26 ---------------------------------------- 28.46/9.26 28.46/9.26 (2) 28.46/9.26 Obligation: 28.46/9.26 LLVM Problem 28.46/9.26 28.46/9.26 Aliases: 28.46/9.26 28.46/9.26 Data layout: 28.46/9.26 28.46/9.26 "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" 28.46/9.26 28.46/9.26 Machine: 28.46/9.26 28.46/9.26 "x86_64-pc-linux-gnu" 28.46/9.26 28.46/9.26 Type definitions: 28.46/9.26 28.46/9.26 Global variables: 28.46/9.26 28.46/9.26 Function declarations and definitions: 28.46/9.26 28.46/9.26 *BasicFunctionTypename: "__VERIFIER_nondet_int" returnParam: i32 parameters: () variableLength: false visibilityType: DEFAULT callingConvention: ccc 28.46/9.26 *BasicFunctionTypename: "test_fun" linkageType: EXTERNALLY_VISIBLE returnParam: i32 parameters: (x i32, y i32) variableLength: false visibilityType: DEFAULT callingConvention: ccc 28.46/9.26 0: 28.46/9.26 %1 = alloca i32, align 4 28.46/9.26 %2 = alloca i32, align 4 28.46/9.26 %x_ref = alloca *i32, align 8 28.46/9.26 %y_ref = alloca *i32, align 8 28.46/9.26 %c = alloca *i32, align 8 28.46/9.26 store %x, %1 28.46/9.26 store %y, %2 28.46/9.26 %3 = alloca i8, numElementsLit: 4 28.46/9.26 %4 = bitcast *i8 %3 to *i32 28.46/9.26 store %4, %x_ref 28.46/9.26 %5 = alloca i8, numElementsLit: 4 28.46/9.26 %6 = bitcast *i8 %5 to *i32 28.46/9.26 store %6, %y_ref 28.46/9.26 %7 = alloca i8, numElementsLit: 4 28.46/9.26 %8 = bitcast *i8 %7 to *i32 28.46/9.26 store %8, %c 28.46/9.26 %9 = load %1 28.46/9.26 %10 = load %x_ref 28.46/9.26 store %9, %10 28.46/9.26 %11 = load %2 28.46/9.26 %12 = load %y_ref 28.46/9.26 store %11, %12 28.46/9.26 %13 = load %c 28.46/9.26 store 0, %13 28.46/9.26 br %14 28.46/9.26 14: 28.46/9.26 %15 = load %x_ref 28.46/9.26 %16 = load %15 28.46/9.26 %17 = icmp sgt %16 1 28.46/9.26 br %17, %18, %24 28.46/9.26 18: 28.46/9.26 %19 = load %x_ref 28.46/9.26 %20 = load %19 28.46/9.26 %21 = load %y_ref 28.46/9.26 %22 = load %21 28.46/9.26 %23 = icmp slt %20 %22 28.46/9.26 br %24 28.46/9.26 24: 28.46/9.26 %25 = phi [0, %14], [%23, %18] 28.46/9.26 br %25, %26, %37 28.46/9.26 26: 28.46/9.26 %27 = load %x_ref 28.46/9.26 %28 = load %27 28.46/9.26 %29 = load %x_ref 28.46/9.26 %30 = load %29 28.46/9.26 %31 = mul %28 %30 28.46/9.26 %32 = load %x_ref 28.46/9.26 store %31, %32 28.46/9.26 %33 = load %c 28.46/9.26 %34 = load %33 28.46/9.26 %35 = add %34 1 28.46/9.26 %36 = load %c 28.46/9.26 store %35, %36 28.46/9.26 br %14 28.46/9.26 37: 28.46/9.26 %38 = load %c 28.46/9.26 %39 = load %38 28.46/9.26 ret %39 28.46/9.26 28.46/9.26 *BasicFunctionTypename: "main" linkageType: EXTERNALLY_VISIBLE returnParam: i32 parameters: () variableLength: false visibilityType: DEFAULT callingConvention: ccc 28.46/9.26 0: 28.46/9.26 %1 = alloca i32, align 4 28.46/9.26 store 0, %1 28.46/9.26 %2 = call i32 @__VERIFIER_nondet_int() 28.46/9.26 %3 = call i32 @__VERIFIER_nondet_int() 28.46/9.26 %4 = call i32 @test_fun(i32 %2, i32 %3) 28.46/9.26 ret %4 28.46/9.26 28.46/9.26 28.46/9.26 Analyze Termination of all function calls matching the pattern: 28.46/9.26 main() 28.46/9.26 ---------------------------------------- 28.46/9.26 28.46/9.26 (3) LLVMToTerminationGraphProof (EQUIVALENT) 28.46/9.26 Constructed symbolic execution graph for LLVM program and proved memory safety. 28.46/9.26 ---------------------------------------- 28.46/9.26 28.46/9.26 (4) 28.46/9.26 Obligation: 28.46/9.26 SE Graph 28.46/9.26 ---------------------------------------- 28.46/9.26 28.46/9.26 (5) SymbolicExecutionGraphToSCCProof (SOUND) 28.46/9.26 Splitted symbolic execution graph to 1 SCC. 28.46/9.26 ---------------------------------------- 28.46/9.26 28.46/9.26 (6) 28.46/9.26 Obligation: 28.46/9.26 SCC 28.46/9.26 ---------------------------------------- 28.46/9.26 28.46/9.26 (7) SCC2IRS (SOUND) 28.46/9.26 Transformed LLVM symbolic execution graph SCC into a rewrite problem. Log: 28.46/9.26 Generated rules. Obtained 27 rulesP rules: 28.46/9.26 f_498(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v964, 1, v966, v967, v968, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) -> f_499(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v964, v967, v968, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) :|: 0 = 0 28.46/9.26 f_499(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v964, v967, v968, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) -> f_500(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v964, v967, v968, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) :|: 1 < v966 28.46/9.26 f_500(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v964, v967, v968, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) -> f_502(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v964, v967, v968, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) :|: 0 = 0 28.46/9.26 f_502(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v964, v967, v968, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) -> f_504(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v964, v967, v968, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) :|: TRUE 28.46/9.26 f_504(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v964, v967, v968, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) -> f_506(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v964, v967, v968, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) :|: 0 = 0 28.46/9.26 f_506(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v964, v967, v968, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) -> f_508(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v964, v967, v968, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) :|: 0 = 0 28.46/9.26 f_508(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v964, v967, v968, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) -> f_510(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v964, v967, v968, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) :|: 0 = 0 28.46/9.26 f_510(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v964, v967, v968, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) -> f_512(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v964, v967, v968, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) :|: 0 = 0 28.46/9.26 f_512(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v964, v967, v968, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) -> f_514(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v964, v967, v968, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) :|: v966 < v955 28.46/9.26 f_514(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v964, v967, v968, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) -> f_516(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v964, v967, v968, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) :|: 0 = 0 28.46/9.26 f_516(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v964, v967, v968, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) -> f_518(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v964, v967, v968, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) :|: 0 = 0 28.46/9.26 f_518(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v964, v967, v968, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) -> f_520(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v964, v967, v968, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) :|: TRUE 28.46/9.26 f_520(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v964, v967, v968, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) -> f_522(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v964, v967, v968, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) :|: 0 = 0 28.46/9.26 f_522(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v964, v967, v968, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) -> f_524(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v964, v967, v968, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) :|: 0 = 0 28.46/9.26 f_524(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v964, v967, v968, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) -> f_526(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v964, v967, v968, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) :|: 0 = 0 28.46/9.26 f_526(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v964, v967, v968, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) -> f_528(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v967, v968, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) :|: 0 = 0 28.46/9.26 f_528(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v967, v968, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) -> f_529(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v1107, v967, v968, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) :|: v1107 = v966 * v966 28.46/9.26 f_529(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v1107, v967, v968, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) -> f_530(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v1107, v967, v968, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) :|: 0 = 0 28.46/9.26 f_530(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v1107, v967, v968, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) -> f_531(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v1107, v967, v968, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) :|: TRUE 28.46/9.26 f_531(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v1107, v967, v968, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) -> f_532(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v1107, v967, v968, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) :|: 0 = 0 28.46/9.26 f_532(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v1107, v967, v968, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) -> f_533(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v1107, v968, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) :|: 0 = 0 28.46/9.26 f_533(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v1107, v968, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) -> f_534(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v1107, v968, v1109, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) :|: v1109 = 1 + v968 && 2 <= v1109 28.46/9.26 f_534(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v1107, v968, v1109, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) -> f_535(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v1107, v968, v1109, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) :|: 0 = 0 28.46/9.26 f_535(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v1107, v968, v1109, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) -> f_536(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v1107, v968, v1109, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) :|: TRUE 28.46/9.26 f_536(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v1107, v968, v1109, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) -> f_537(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v1107, v968, v1109, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) :|: TRUE 28.46/9.26 f_537(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v1107, v968, v1109, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) -> f_497(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v966, 1, v1107, v968, v1109, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) :|: TRUE 28.46/9.26 f_497(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v964, 1, v966, v967, v968, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) -> f_498(v954, v955, v956, v957, v958, v959, v960, v961, v962, v963, v964, 1, v966, v967, v968, v969, v970, v971, v972, v973, v974, v975, v976, v977, v978, 0, 3, 7, 2, 4, 8) :|: 0 = 0 28.46/9.26 Combined rules. Obtained 1 rulesP rules: 28.46/9.26 f_498(v954:0, v955:0, v956:0, v957:0, v958:0, v959:0, v960:0, v961:0, v962:0, v963:0, v964:0, 1, v966:0, v967:0, v968:0, v969:0, v970:0, v971:0, v972:0, v973:0, v974:0, v975:0, v976:0, v977:0, v978:0, 0, 3, 7, 2, 4, 8) -> f_498(v954:0, v955:0, v956:0, v957:0, v958:0, v959:0, v960:0, v961:0, v962:0, v963:0, v966:0, 1, v966:0 * v966:0, v968:0, 1 + v968:0, v969:0, v970:0, v971:0, v972:0, v973:0, v974:0, v975:0, v976:0, v977:0, v978:0, 0, 3, 7, 2, 4, 8) :|: v966:0 > 1 && v968:0 > 0 && v966:0 < v955:0 28.46/9.26 Filtered unneeded arguments: 28.46/9.26 f_498(x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, x16, x17, x18, x19, x20, x21, x22, x23, x24, x25, x26, x27, x28, x29, x30, x31) -> f_498(x2, x13, x15) 28.46/9.26 Removed division, modulo operations, cleaned up constraints. Obtained 1 rules.P rules: 28.46/9.26 f_498(v955:0, v966:0, v968:0) -> f_498(v955:0, v966:0 * v966:0, 1 + v968:0) :|: v968:0 > 0 && v966:0 < v955:0 && v966:0 > 1 28.46/9.26 28.46/9.26 ---------------------------------------- 28.46/9.26 28.46/9.26 (8) 28.46/9.26 Obligation: 28.46/9.26 Rules: 28.46/9.26 f_498(v955:0, v966:0, v968:0) -> f_498(v955:0, v966:0 * v966:0, 1 + v968:0) :|: v968:0 > 0 && v966:0 < v955:0 && v966:0 > 1 28.46/9.26 28.46/9.26 ---------------------------------------- 28.46/9.26 28.46/9.26 (9) IntTRSCompressionProof (EQUIVALENT) 28.46/9.26 Compressed rules. 28.46/9.26 ---------------------------------------- 28.46/9.26 28.46/9.26 (10) 28.46/9.26 Obligation: 28.46/9.26 Rules: 28.46/9.26 f_498(v955:0:0, v966:0:0, v968:0:0) -> f_498(v955:0:0, v966:0:0 * v966:0:0, 1 + v968:0:0) :|: v968:0:0 > 0 && v966:0:0 < v955:0:0 && v966:0:0 > 1 28.46/9.26 28.46/9.26 ---------------------------------------- 28.46/9.26 28.46/9.26 (11) PolynomialOrderProcessor (EQUIVALENT) 28.46/9.26 Found the following polynomial interpretation: 28.46/9.26 [f_498(x, x1, x2)] = -2 + x - x1 + x2 28.46/9.26 28.46/9.26 The following rules are decreasing: 28.46/9.26 f_498(v955:0:0, v966:0:0, v968:0:0) -> f_498(v955:0:0, v966:0:0 * v966:0:0, 1 + v968:0:0) :|: v968:0:0 > 0 && v966:0:0 < v955:0:0 && v966:0:0 > 1 28.46/9.26 The following rules are bounded: 28.46/9.26 f_498(v955:0:0, v966:0:0, v968:0:0) -> f_498(v955:0:0, v966:0:0 * v966:0:0, 1 + v968:0:0) :|: v968:0:0 > 0 && v966:0:0 < v955:0:0 && v966:0:0 > 1 28.46/9.26 28.46/9.26 ---------------------------------------- 28.46/9.26 28.46/9.26 (12) 28.46/9.26 YES 28.69/9.30 EOF