48.99/15.93	YES
49.42/15.94	proof of /export/starexec/sandbox/benchmark/theBenchmark.c
49.42/15.94	# AProVE Commit ID: 48fb2092695e11cc9f56e44b17a92a5f88ffb256 marcel 20180622 unpublished dirty
49.42/15.94	
49.42/15.94	
49.42/15.94	Termination of the given C Problem could be proven:
49.42/15.94	
49.42/15.94	(0) C Problem
49.42/15.94	(1) CToLLVMProof [EQUIVALENT, 168 ms]
49.42/15.94	(2) LLVM problem
49.42/15.94	(3) LLVMToTerminationGraphProof [EQUIVALENT, 10.5 s]
49.42/15.94	(4) LLVM Symbolic Execution Graph
49.42/15.94	(5) SymbolicExecutionGraphToSCCProof [SOUND, 0 ms]
49.42/15.94	(6) AND
49.42/15.94	    (7) LLVM Symbolic Execution SCC
49.42/15.94	        (8) SCC2IRS [SOUND, 81 ms]
49.42/15.94	        (9) IntTRS
49.42/15.94	        (10) IntTRSCompressionProof [EQUIVALENT, 0 ms]
49.42/15.94	        (11) IntTRS
49.42/15.94	        (12) RankingReductionPairProof [EQUIVALENT, 12 ms]
49.42/15.94	        (13) YES
49.42/15.94	    (14) LLVM Symbolic Execution SCC
49.42/15.94	        (15) SCC2IRS [SOUND, 96 ms]
49.42/15.94	        (16) IntTRS
49.42/15.94	        (17) IntTRSCompressionProof [EQUIVALENT, 0 ms]
49.42/15.94	        (18) IntTRS
49.42/15.94	        (19) RankingReductionPairProof [EQUIVALENT, 15 ms]
49.42/15.94	        (20) YES
49.42/15.94	    (21) LLVM Symbolic Execution SCC
49.42/15.94	        (22) SCC2IRS [SOUND, 118 ms]
49.42/15.94	        (23) IntTRS
49.42/15.94	        (24) IntTRSCompressionProof [EQUIVALENT, 0 ms]
49.42/15.94	        (25) IntTRS
49.42/15.94	        (26) PolynomialOrderProcessor [EQUIVALENT, 0 ms]
49.42/15.94	        (27) YES
49.42/15.94	
49.42/15.94	
49.42/15.94	----------------------------------------
49.42/15.94	
49.42/15.94	(0)
49.42/15.94	Obligation:
49.42/15.94	c file /export/starexec/sandbox/benchmark/theBenchmark.c
49.42/15.94	----------------------------------------
49.42/15.94	
49.42/15.94	(1) CToLLVMProof (EQUIVALENT)
49.42/15.94	Compiled c-file /export/starexec/sandbox/benchmark/theBenchmark.c to LLVM.
49.42/15.94	----------------------------------------
49.42/15.94	
49.42/15.94	(2)
49.42/15.94	Obligation:
49.42/15.94	LLVM Problem
49.42/15.94	
49.42/15.94	Aliases:
49.42/15.94	
49.42/15.94	Data layout:
49.42/15.94	
49.42/15.94	"e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
49.42/15.94	
49.42/15.94	Machine:
49.42/15.94	
49.42/15.94	"x86_64-pc-linux-gnu"
49.42/15.94	
49.42/15.94	Type definitions:
49.42/15.94	
49.42/15.94	Global variables:
49.42/15.94	
49.42/15.94	Function declarations and definitions:
49.42/15.94	
49.42/15.94	*BasicFunctionTypename: "__VERIFIER_nondet_int" returnParam: i32 parameters: () variableLength: false visibilityType: DEFAULT callingConvention: ccc
49.42/15.94	*BasicFunctionTypename: "test_fun" linkageType: EXTERNALLY_VISIBLE returnParam: i32 parameters: (x i32, y i32) variableLength: false visibilityType: DEFAULT callingConvention: ccc
49.42/15.94		0:
49.42/15.94			%1 = alloca i32, align 4
49.42/15.94			%2 = alloca i32, align 4
49.42/15.94			%x_ref = alloca *i32, align 8
49.42/15.94			%y_ref = alloca *i32, align 8
49.42/15.94			%c = alloca *i32, align 8
49.42/15.94			store %x, %1
49.42/15.94			store %y, %2
49.42/15.94			%3 = alloca i8, numElementsLit: 4
49.42/15.94			%4 = bitcast *i8 %3 to *i32
49.42/15.94			store %4, %x_ref
49.42/15.94			%5 = alloca i8, numElementsLit: 4
49.42/15.94			%6 = bitcast *i8 %5 to *i32
49.42/15.94			store %6, %y_ref
49.42/15.94			%7 = alloca i8, numElementsLit: 4
49.42/15.94			%8 = bitcast *i8 %7 to *i32
49.42/15.94			store %8, %c
49.42/15.94			%9 = load %1
49.42/15.94			%10 = load %x_ref
49.42/15.94			store %9, %10
49.42/15.94			%11 = load %2
49.42/15.94			%12 = load %y_ref
49.42/15.94			store %11, %12
49.42/15.94			%13 = load %c
49.42/15.94			store 0, %13
49.42/15.94			br %14
49.42/15.94		14:
49.42/15.94			%15 = load %x_ref
49.42/15.94			%16 = load %15
49.42/15.94			%17 = load %y_ref
49.42/15.94			%18 = load %17
49.42/15.94			%19 = add %16 %18
49.42/15.94			%20 = icmp sgt %19 0
49.42/15.94			br %20, %21, %46
49.42/15.94		21:
49.42/15.94			%22 = load %x_ref
49.42/15.94			%23 = load %22
49.42/15.94			%24 = icmp sgt %23 0
49.42/15.94			br %24, %25, %30
49.42/15.94		25:
49.42/15.94			%26 = load %x_ref
49.42/15.94			%27 = load %26
49.42/15.94			%28 = sub %27 1
49.42/15.94			%29 = load %x_ref
49.42/15.94			store %28, %29
49.42/15.94			br %41
49.42/15.94		30:
49.42/15.94			%31 = load %y_ref
49.42/15.94			%32 = load %31
49.42/15.94			%33 = icmp sgt %32 0
49.42/15.94			br %33, %34, %39
49.42/15.94		34:
49.42/15.94			%35 = load %y_ref
49.42/15.94			%36 = load %35
49.42/15.94			%37 = sub %36 1
49.42/15.94			%38 = load %y_ref
49.42/15.94			store %37, %38
49.42/15.94			br %40
49.42/15.94		39:
49.42/15.94			br %40
49.42/15.94		40:
49.42/15.94			br %41
49.42/15.94		41:
49.42/15.94			%42 = load %c
49.42/15.94			%43 = load %42
49.42/15.94			%44 = add %43 1
49.42/15.94			%45 = load %c
49.42/15.94			store %44, %45
49.42/15.94			br %14
49.42/15.94		46:
49.42/15.94			%47 = load %c
49.42/15.94			%48 = load %47
49.42/15.94			ret %48
49.42/15.94	
49.42/15.94	*BasicFunctionTypename: "main" linkageType: EXTERNALLY_VISIBLE returnParam: i32 parameters: () variableLength: false visibilityType: DEFAULT callingConvention: ccc
49.42/15.94		0:
49.42/15.94			%1 = alloca i32, align 4
49.42/15.94			store 0, %1
49.42/15.94			%2 = call i32 @__VERIFIER_nondet_int()
49.42/15.94			%3 = call i32 @__VERIFIER_nondet_int()
49.42/15.94			%4 = call i32 @test_fun(i32 %2, i32 %3)
49.42/15.94			ret %4
49.42/15.94	
49.42/15.94	
49.42/15.94	Analyze Termination of all function calls matching the pattern:
49.42/15.94	main()
49.42/15.94	----------------------------------------
49.42/15.94	
49.42/15.94	(3) LLVMToTerminationGraphProof (EQUIVALENT)
49.42/15.94	Constructed symbolic execution graph for LLVM program and proved memory safety.
49.42/15.94	----------------------------------------
49.42/15.94	
49.42/15.94	(4)
49.42/15.94	Obligation:
49.42/15.94	SE Graph
49.42/15.94	----------------------------------------
49.42/15.94	
49.42/15.94	(5) SymbolicExecutionGraphToSCCProof (SOUND)
49.42/15.94	Splitted symbolic execution graph to 3 SCCs.
49.42/15.94	----------------------------------------
49.42/15.94	
49.42/15.94	(6)
49.42/15.94	Complex Obligation (AND)
49.42/15.94	
49.42/15.94	----------------------------------------
49.42/15.94	
49.42/15.94	(7)
49.42/15.94	Obligation:
49.42/15.94	SCC
49.42/15.94	----------------------------------------
49.42/15.94	
49.42/15.94	(8) SCC2IRS (SOUND)
49.42/15.94	Transformed LLVM symbolic execution graph SCC into a rewrite problem. Log: 
49.42/15.94	Generated rules. Obtained 30 rulesP rules:
49.42/15.94	f_936(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1007, 1, v1009, v1010, v1011, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 4, 8) -> f_937(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1007, 1, v1009, v1010, v1011, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 4, 8) :|: 0 = 0
49.42/15.94	f_937(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1007, 1, v1009, v1010, v1011, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 4, 8) -> f_938(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1007, 1, v1010, v1011, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 4, 8) :|: 0 = 0
49.42/15.94	f_938(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1007, 1, v1010, v1011, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 4, 8) -> f_939(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1007, 1, v1010, v1022, v1011, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 4, 8, 2) :|: v1022 = 1 + v1010 && 2 <= v1022
49.42/15.94	f_939(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1007, 1, v1010, v1022, v1011, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 4, 8, 2) -> f_940(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1007, 1, v1010, v1022, v1011, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 4, 8, 2) :|: 0 = 0
49.42/15.94	f_940(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1007, 1, v1010, v1022, v1011, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 4, 8, 2) -> f_941(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1007, 1, v1010, v1022, v1011, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 4, 8, 2) :|: TRUE
49.42/15.94	f_941(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1007, 1, v1010, v1022, v1011, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 4, 8, 2) -> f_942(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1007, 1, v1010, v1022, v1011, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 4, 8, 2) :|: TRUE
49.42/15.94	f_942(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1007, 1, v1010, v1022, v1011, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 4, 8, 2) -> f_943(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1007, 1, v1010, v1022, v1011, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 4, 8, 2) :|: 0 = 0
49.42/15.94	f_943(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1007, 1, v1010, v1022, v1011, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 4, 8, 2) -> f_944(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1007, 1, v1010, v1022, v1011, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 4, 8, 2) :|: 0 = 0
49.42/15.94	f_944(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1007, 1, v1010, v1022, v1011, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 4, 8, 2) -> f_945(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1007, 1, v1010, v1022, v1011, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 4, 8, 2) :|: 0 = 0
49.42/15.94	f_945(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1007, 1, v1010, v1022, v1011, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 4, 8, 2) -> f_946(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1011, v1007, 1, v1010, v1022, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 4, 8, 2) :|: 0 = 0
49.42/15.94	f_946(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1011, v1007, 1, v1010, v1022, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 4, 8, 2) -> f_947(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1011, 1, v1010, v1022, v1007, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 4, 8, 2) :|: 0 = 0
49.42/15.94	f_947(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1011, 1, v1010, v1022, v1007, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 4, 8, 2) -> f_948(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1011, 1, v1010, v1022, v1007, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 2, 4, 8) :|: 0 < v1011 && 2 <= v1007 && 2 <= v997
49.42/15.94	f_948(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1011, 1, v1010, v1022, v1007, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 2, 4, 8) -> f_950(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1011, 1, v1010, v1022, v1007, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 2, 4, 8) :|: 0 = 0
49.42/15.94	f_950(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1011, 1, v1010, v1022, v1007, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 2, 4, 8) -> f_952(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1011, 1, v1010, v1022, v1007, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 2, 4, 8) :|: TRUE
49.42/15.94	f_952(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1011, 1, v1010, v1022, v1007, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 2, 4, 8) -> f_954(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1011, 1, v1010, v1022, v1007, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 2, 4, 8) :|: 0 = 0
49.42/15.94	f_954(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1011, 1, v1010, v1022, v1007, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 2, 4, 8) -> f_956(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1011, 1, v1010, v1022, v1007, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 2, 4, 8) :|: 0 = 0
49.42/15.94	f_956(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1011, 1, v1010, v1022, v1007, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 2, 4, 8) -> f_958(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1011, 1, v1010, v1022, v1007, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 2, 4, 8) :|: 0 = 0
49.42/15.94	f_958(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1011, 1, v1010, v1022, v1007, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 2, 4, 8) -> f_960(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1011, 1, v1010, v1022, v1007, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 2, 4, 8) :|: TRUE
49.42/15.94	f_960(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1011, 1, v1010, v1022, v1007, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 2, 4, 8) -> f_961(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1011, 1, v1010, v1022, v1007, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 2, 4, 8) :|: 0 = 0
49.42/15.94	f_961(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1011, 1, v1010, v1022, v1007, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 2, 4, 8) -> f_962(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1011, 1, v1010, v1022, v1007, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 2, 4, 8) :|: 0 = 0
49.42/15.94	f_962(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1011, 1, v1010, v1022, v1007, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 2, 4, 8) -> f_963(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1011, 1, v1010, v1022, v1007, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 2, 4, 8) :|: 0 = 0
49.42/15.94	f_963(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1011, 1, v1010, v1022, v1007, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 2, 4, 8) -> f_964(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1011, 1, v1010, v1022, v1007, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 2, 4, 8) :|: TRUE
49.42/15.94	f_964(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1011, 1, v1010, v1022, v1007, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 2, 4, 8) -> f_965(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1011, 1, v1010, v1022, v1007, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 2, 4, 8) :|: 0 = 0
49.42/15.94	f_965(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1011, 1, v1010, v1022, v1007, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 2, 4, 8) -> f_966(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1011, 1, v1010, v1022, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 2, 4, 8) :|: 0 = 0
49.42/15.94	f_966(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1011, 1, v1010, v1022, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 2, 4, 8) -> f_967(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1011, 1, v1010, v1022, v1071, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 2, 4, 8) :|: 1 + v1071 = v1011 && 0 <= v1071
49.42/15.94	f_967(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1011, 1, v1010, v1022, v1071, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 2, 4, 8) -> f_968(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1011, 1, v1010, v1022, v1071, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 2, 4, 8) :|: 0 = 0
49.42/15.94	f_968(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1011, 1, v1010, v1022, v1071, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 2, 4, 8) -> f_969(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1011, 1, v1010, v1022, v1071, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 2, 4, 8) :|: TRUE
49.42/15.94	f_969(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1011, 1, v1010, v1022, v1071, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 2, 4, 8) -> f_970(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1011, 1, v1010, v1022, v1071, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 2, 4, 8) :|: TRUE
49.42/15.94	f_970(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1011, 1, v1010, v1022, v1071, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 2, 4, 8) -> f_935(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1011, 1, v1010, v1022, v1071, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 4, 8) :|: TRUE
49.42/15.94	f_935(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1007, 1, v1009, v1010, v1011, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 4, 8) -> f_936(v996, v997, v998, v999, v1000, v1001, v1002, v1003, v1004, v1005, 0, v1007, 1, v1009, v1010, v1011, v1012, v1013, v1014, v1015, v1016, v1017, v1018, v1019, v1020, v1021, 3, 7, 4, 8) :|: TRUE
49.42/15.94	Combined rules. Obtained 1 rulesP rules:
49.42/15.94	f_936(v996:0, v997:0, v998:0, v999:0, v1000:0, v1001:0, v1002:0, v1003:0, v1004:0, v1005:0, 0, v1007:0, 1, v1009:0, v1010:0, 1 + v1071:0, v1012:0, v1013:0, v1014:0, v1015:0, v1016:0, v1017:0, v1018:0, v1019:0, v1020:0, v1021:0, 3, 7, 4, 8) -> f_936(v996:0, v997:0, v998:0, v999:0, v1000:0, v1001:0, v1002:0, v1003:0, v1004:0, v1005:0, 0, 1 + v1071:0, 1, v1010:0, 1 + v1010:0, v1071:0, v1012:0, v1013:0, v1014:0, v1015:0, v1016:0, v1017:0, v1018:0, v1019:0, v1020:0, v1021:0, 3, 7, 4, 8) :|: v1010:0 > 0 && v1007:0 > 1 && v1071:0 > -1 && v997:0 > 1
49.42/15.94	Filtered unneeded arguments:
49.42/15.94	   f_936(x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, x16, x17, x18, x19, x20, x21, x22, x23, x24, x25, x26, x27, x28, x29, x30) -> f_936(x2, x12, x15, x16)
49.42/15.94	Removed division, modulo operations, cleaned up constraints. Obtained 1 rules.P rules:
49.42/15.94	f_936(v997:0, v1007:0, v1010:0, sum~cons_1~v1071:0) -> f_936(v997:0, 1 + v1071:0, 1 + v1010:0, v1071:0) :|: v1007:0 > 1 && v1010:0 > 0 && v997:0 > 1 && v1071:0 > -1 && sum~cons_1~v1071:0 = 1 + v1071:0
49.42/15.94	
49.42/15.94	----------------------------------------
49.42/15.94	
49.42/15.94	(9)
49.42/15.94	Obligation:
49.42/15.94	Rules:
49.42/15.94	f_936(v997:0, v1007:0, v1010:0, sum~cons_1~v1071:0) -> f_936(v997:0, 1 + v1071:0, 1 + v1010:0, v1071:0) :|: v1007:0 > 1 && v1010:0 > 0 && v997:0 > 1 && v1071:0 > -1 && sum~cons_1~v1071:0 = 1 + v1071:0
49.42/15.94	
49.42/15.94	----------------------------------------
49.42/15.94	
49.42/15.94	(10) IntTRSCompressionProof (EQUIVALENT)
49.42/15.94	Compressed rules.
49.42/15.94	----------------------------------------
49.42/15.94	
49.42/15.94	(11)
49.42/15.94	Obligation:
49.42/15.94	Rules:
49.42/15.94	f_936(v997:0:0, v1007:0:0, v1010:0:0, sum~cons_1~v1071:0:0) -> f_936(v997:0:0, 1 + v1071:0:0, 1 + v1010:0:0, v1071:0:0) :|: v997:0:0 > 1 && v1071:0:0 > -1 && v1010:0:0 > 0 && v1007:0:0 > 1 && sum~cons_1~v1071:0:0 = 1 + v1071:0:0
49.42/15.94	
49.42/15.94	----------------------------------------
49.42/15.94	
49.42/15.94	(12) RankingReductionPairProof (EQUIVALENT)
49.42/15.94	Interpretation:
49.42/15.94	[ f_936 ] = f_936_4
49.42/15.94	
49.42/15.94	The following rules are decreasing:
49.42/15.94	f_936(v997:0:0, v1007:0:0, v1010:0:0, sum~cons_1~v1071:0:0) -> f_936(v997:0:0, 1 + v1071:0:0, 1 + v1010:0:0, v1071:0:0) :|: v997:0:0 > 1 && v1071:0:0 > -1 && v1010:0:0 > 0 && v1007:0:0 > 1 && sum~cons_1~v1071:0:0 = 1 + v1071:0:0
49.42/15.94	
49.42/15.94	The following rules are bounded:
49.42/15.94	f_936(v997:0:0, v1007:0:0, v1010:0:0, sum~cons_1~v1071:0:0) -> f_936(v997:0:0, 1 + v1071:0:0, 1 + v1010:0:0, v1071:0:0) :|: v997:0:0 > 1 && v1071:0:0 > -1 && v1010:0:0 > 0 && v1007:0:0 > 1 && sum~cons_1~v1071:0:0 = 1 + v1071:0:0
49.42/15.94	
49.42/15.94	
49.42/15.94	----------------------------------------
49.42/15.94	
49.42/15.94	(13)
49.42/15.94	YES
49.42/15.94	
49.42/15.94	----------------------------------------
49.42/15.94	
49.42/15.94	(14)
49.42/15.94	Obligation:
49.42/15.94	SCC
49.42/15.94	----------------------------------------
49.42/15.94	
49.42/15.94	(15) SCC2IRS (SOUND)
49.42/15.94	Transformed LLVM symbolic execution graph SCC into a rewrite problem. Log: 
49.42/15.94	Generated rules. Obtained 30 rulesP rules:
49.42/15.94	f_836(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v676, v677, 1, 0, v680, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 4, 8) -> f_838(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v676, v677, 1, 0, v680, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 4, 8) :|: 0 = 0
49.42/15.94	f_838(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v676, v677, 1, 0, v680, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 4, 8) -> f_840(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v676, v677, 1, 0, v680, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 4, 8) :|: 0 = 0
49.42/15.94	f_840(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v676, v677, 1, 0, v680, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 4, 8) -> f_842(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v677, 1, 0, v676, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 4, 8) :|: 0 = 0
49.42/15.94	f_842(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v677, 1, 0, v676, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 4, 8) -> f_844(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v676, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 4, 8) :|: v724 = v666 + v680
49.42/15.94	f_844(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v676, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 4, 8) -> f_846(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v676, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) :|: 0 < v724 && 1 <= v680 && 2 <= v676 && 2 <= v667
49.42/15.94	f_846(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v676, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) -> f_850(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v676, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) :|: 0 = 0
49.42/15.94	f_850(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v676, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) -> f_854(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v676, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) :|: TRUE
49.42/15.94	f_854(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v676, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) -> f_858(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v676, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) :|: 0 = 0
49.42/15.94	f_858(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v676, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) -> f_862(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v676, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) :|: 0 = 0
49.42/15.94	f_862(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v676, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) -> f_866(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v676, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) :|: 0 = 0
49.42/15.94	f_866(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v676, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) -> f_870(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v676, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) :|: TRUE
49.42/15.94	f_870(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v676, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) -> f_872(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v676, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) :|: 0 = 0
49.42/15.94	f_872(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v676, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) -> f_874(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v676, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) :|: 0 = 0
49.42/15.94	f_874(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v676, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) -> f_876(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v676, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) :|: 0 = 0
49.42/15.94	f_876(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v676, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) -> f_878(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v676, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) :|: TRUE
49.42/15.94	f_878(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v676, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) -> f_880(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v676, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) :|: 0 = 0
49.42/15.94	f_880(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v676, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) -> f_882(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) :|: 0 = 0
49.42/15.94	f_882(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) -> f_884(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v825, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) :|: 1 + v825 = v680 && 0 <= v825
49.42/15.94	f_884(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v825, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) -> f_886(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v825, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) :|: 0 = 0
49.42/15.94	f_886(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v825, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) -> f_888(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v825, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) :|: TRUE
49.42/15.94	f_888(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v825, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) -> f_890(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v825, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) :|: TRUE
49.42/15.94	f_890(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v825, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) -> f_893(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v825, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) :|: TRUE
49.42/15.94	f_893(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v825, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) -> f_895(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v825, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) :|: 0 = 0
49.42/15.94	f_895(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v825, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) -> f_897(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v825, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) :|: 0 = 0
49.42/15.94	f_897(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v825, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) -> f_899(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v825, v682, v884, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) :|: v884 = 1 + v682 && 2 <= v884
49.42/15.94	f_899(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v825, v682, v884, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) -> f_901(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v825, v682, v884, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) :|: 0 = 0
49.42/15.94	f_901(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v825, v682, v884, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) -> f_903(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v825, v682, v884, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) :|: TRUE
49.42/15.94	f_903(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v825, v682, v884, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) -> f_905(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v825, v682, v884, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) :|: TRUE
49.42/15.94	f_905(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v825, v682, v884, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 2, 4, 8) -> f_834(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v680, v724, 1, 0, v825, v682, v884, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 4, 8) :|: TRUE
49.42/15.94	f_834(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v676, v677, 1, 0, v680, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 4, 8) -> f_836(v666, v667, v668, v669, v670, v671, v672, v673, v674, v675, v676, v677, 1, 0, v680, v681, v682, v683, v684, v685, v686, v687, v688, v689, v690, v691, v692, 3, 7, 4, 8) :|: 0 = 0
49.42/15.94	Combined rules. Obtained 1 rulesP rules:
49.42/15.94	f_836(v666:0, v667:0, v668:0, v669:0, v670:0, v671:0, v672:0, v673:0, v674:0, v675:0, v676:0, v677:0, 1, 0, 1 + v825:0, v681:0, v682:0, v683:0, v684:0, v685:0, v686:0, v687:0, v688:0, v689:0, v690:0, v691:0, v692:0, 3, 7, 4, 8) -> f_836(v666:0, v667:0, v668:0, v669:0, v670:0, v671:0, v672:0, v673:0, v674:0, v675:0, 1 + v825:0, v666:0 + (1 + v825:0), 1, 0, v825:0, v682:0, 1 + v682:0, v683:0, v684:0, v685:0, v686:0, v687:0, v688:0, v689:0, v690:0, v691:0, v692:0, 3, 7, 4, 8) :|: v825:0 > -1 && v666:0 + (1 + v825:0) > 0 && v676:0 > 1 && v667:0 > 1 && v682:0 > 0
49.42/15.94	Filtered unneeded arguments:
49.42/15.94	   f_836(x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, x16, x17, x18, x19, x20, x21, x22, x23, x24, x25, x26, x27, x28, x29, x30, x31) -> f_836(x1, x2, x11, x15, x17)
49.42/15.94	Removed division, modulo operations, cleaned up constraints. Obtained 1 rules.P rules:
49.42/15.94	f_836(v666:0, v667:0, v676:0, sum~cons_1~v825:0, v682:0) -> f_836(v666:0, v667:0, 1 + v825:0, v825:0, 1 + v682:0) :|: v666:0 + (1 + v825:0) > 0 && v825:0 > -1 && v676:0 > 1 && v682:0 > 0 && v667:0 > 1 && sum~cons_1~v825:0 = 1 + v825:0
49.42/15.94	
49.42/15.94	----------------------------------------
49.42/15.94	
49.42/15.94	(16)
49.42/15.94	Obligation:
49.42/15.94	Rules:
49.42/15.94	f_836(v666:0, v667:0, v676:0, sum~cons_1~v825:0, v682:0) -> f_836(v666:0, v667:0, 1 + v825:0, v825:0, 1 + v682:0) :|: v666:0 + (1 + v825:0) > 0 && v825:0 > -1 && v676:0 > 1 && v682:0 > 0 && v667:0 > 1 && sum~cons_1~v825:0 = 1 + v825:0
49.42/15.94	
49.42/15.94	----------------------------------------
49.42/15.94	
49.42/15.94	(17) IntTRSCompressionProof (EQUIVALENT)
49.42/15.94	Compressed rules.
49.42/15.94	----------------------------------------
49.42/15.94	
49.42/15.94	(18)
49.42/15.94	Obligation:
49.42/15.94	Rules:
49.42/15.94	f_836(v666:0:0, v667:0:0, v676:0:0, sum~cons_1~v825:0:0, v682:0:0) -> f_836(v666:0:0, v667:0:0, 1 + v825:0:0, v825:0:0, 1 + v682:0:0) :|: v682:0:0 > 0 && v667:0:0 > 1 && v676:0:0 > 1 && v825:0:0 > -1 && v666:0:0 + (1 + v825:0:0) > 0 && sum~cons_1~v825:0:0 = 1 + v825:0:0
49.42/15.94	
49.42/15.94	----------------------------------------
49.42/15.94	
49.42/15.94	(19) RankingReductionPairProof (EQUIVALENT)
49.42/15.94	Interpretation:
49.42/15.94	[ f_836 ] = f_836_4
49.42/15.94	
49.42/15.94	The following rules are decreasing:
49.42/15.94	f_836(v666:0:0, v667:0:0, v676:0:0, sum~cons_1~v825:0:0, v682:0:0) -> f_836(v666:0:0, v667:0:0, 1 + v825:0:0, v825:0:0, 1 + v682:0:0) :|: v682:0:0 > 0 && v667:0:0 > 1 && v676:0:0 > 1 && v825:0:0 > -1 && v666:0:0 + (1 + v825:0:0) > 0 && sum~cons_1~v825:0:0 = 1 + v825:0:0
49.42/15.94	
49.42/15.94	The following rules are bounded:
49.42/15.94	f_836(v666:0:0, v667:0:0, v676:0:0, sum~cons_1~v825:0:0, v682:0:0) -> f_836(v666:0:0, v667:0:0, 1 + v825:0:0, v825:0:0, 1 + v682:0:0) :|: v682:0:0 > 0 && v667:0:0 > 1 && v676:0:0 > 1 && v825:0:0 > -1 && v666:0:0 + (1 + v825:0:0) > 0 && sum~cons_1~v825:0:0 = 1 + v825:0:0
49.42/15.94	
49.42/15.94	
49.42/15.94	----------------------------------------
49.42/15.94	
49.42/15.94	(20)
49.42/15.94	YES
49.42/15.94	
49.42/15.94	----------------------------------------
49.42/15.94	
49.42/15.94	(21)
49.42/15.94	Obligation:
49.42/15.94	SCC
49.42/15.94	----------------------------------------
49.42/15.94	
49.42/15.94	(22) SCC2IRS (SOUND)
49.42/15.94	Transformed LLVM symbolic execution graph SCC into a rewrite problem. Log: 
49.42/15.94	Generated rules. Obtained 26 rulesP rules:
49.42/15.94	f_749(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v542, v543, 1, v545, v546, v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 4, 8) -> f_751(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v543, 1, v542, v546, v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 4, 8) :|: 0 = 0
49.42/15.94	f_751(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v543, 1, v542, v546, v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 4, 8) -> f_753(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v543, 1, v542, v546, v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 4, 8) :|: 0 = 0
49.42/15.94	f_753(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v543, 1, v542, v546, v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 4, 8) -> f_755(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v543, 1, v542, v546, v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 4, 8) :|: 0 = 0
49.42/15.94	f_755(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v543, 1, v542, v546, v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 4, 8) -> f_757(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v600, 1, v542, v546, v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 4, 8) :|: v600 = v545 + v533
49.42/15.94	f_757(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v600, 1, v542, v546, v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 4, 8) -> f_759(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v600, 1, v542, v546, v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 4, 8) :|: 0 < v600
49.42/15.94	f_759(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v600, 1, v542, v546, v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 4, 8) -> f_763(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v600, 1, v542, v546, v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 4, 8) :|: 0 = 0
49.42/15.94	f_763(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v600, 1, v542, v546, v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 4, 8) -> f_767(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v600, 1, v542, v546, v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 4, 8) :|: TRUE
49.42/15.94	f_767(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v600, 1, v542, v546, v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 4, 8) -> f_771(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v600, 1, v542, v546, v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 4, 8) :|: 0 = 0
49.42/15.94	f_771(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v600, 1, v542, v546, v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 4, 8) -> f_775(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v600, 1, v542, v546, v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 4, 8) :|: 0 = 0
49.42/15.94	f_775(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v600, 1, v542, v546, v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 4, 8) -> f_779(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v600, 1, v542, v546, v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 2, 4, 8) :|: 0 < v545 && 2 <= v542 && 2 <= v532
49.42/15.94	f_779(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v600, 1, v542, v546, v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 2, 4, 8) -> f_784(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v600, 1, v542, v546, v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 2, 4, 8) :|: 0 = 0
49.42/15.94	f_784(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v600, 1, v542, v546, v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 2, 4, 8) -> f_787(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v600, 1, v542, v546, v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 2, 4, 8) :|: TRUE
49.42/15.94	f_787(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v600, 1, v542, v546, v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 2, 4, 8) -> f_790(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v600, 1, v542, v546, v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 2, 4, 8) :|: 0 = 0
49.42/15.94	f_790(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v600, 1, v542, v546, v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 2, 4, 8) -> f_793(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v600, 1, v546, v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 2, 4, 8) :|: 0 = 0
49.42/15.94	f_793(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v600, 1, v546, v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 2, 4, 8) -> f_796(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v600, 1, v602, v546, v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 2, 4, 8) :|: 1 + v602 = v545 && 0 <= v602
49.42/15.94	f_796(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v600, 1, v602, v546, v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 2, 4, 8) -> f_799(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v600, 1, v602, v546, v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 2, 4, 8) :|: 0 = 0
49.42/15.94	f_799(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v600, 1, v602, v546, v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 2, 4, 8) -> f_802(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v600, 1, v602, v546, v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 2, 4, 8) :|: TRUE
49.42/15.94	f_802(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v600, 1, v602, v546, v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 2, 4, 8) -> f_805(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v600, 1, v602, v546, v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 2, 4, 8) :|: TRUE
49.42/15.94	f_805(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v600, 1, v602, v546, v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 2, 4, 8) -> f_808(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v600, 1, v602, v546, v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 2, 4, 8) :|: 0 = 0
49.42/15.94	f_808(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v600, 1, v602, v546, v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 2, 4, 8) -> f_811(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v600, 1, v602, v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 2, 4, 8) :|: 0 = 0
49.42/15.94	f_811(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v600, 1, v602, v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 2, 4, 8) -> f_814(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v600, 1, v602, v547, v607, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 2, 4, 8) :|: v607 = 1 + v547 && 2 <= v607
49.42/15.94	f_814(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v600, 1, v602, v547, v607, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 2, 4, 8) -> f_817(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v600, 1, v602, v547, v607, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 2, 4, 8) :|: 0 = 0
49.42/15.94	f_817(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v600, 1, v602, v547, v607, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 2, 4, 8) -> f_820(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v600, 1, v602, v547, v607, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 2, 4, 8) :|: TRUE
49.42/15.94	f_820(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v600, 1, v602, v547, v607, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 2, 4, 8) -> f_823(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v600, 1, v602, v547, v607, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 2, 4, 8) :|: TRUE
49.42/15.94	f_823(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v600, 1, v602, v547, v607, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 2, 4, 8) -> f_746(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v545, v600, 1, v602, v547, v607, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 4, 8) :|: TRUE
49.42/15.94	f_746(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v542, v543, 1, v545, v546, v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 4, 8) -> f_749(v532, v533, v534, v535, v536, v537, v538, v539, v540, v541, v542, v543, 1, v545, v546, v547, v548, v549, v550, v551, v552, v553, v554, v555, v556, v557, 0, 3, 7, 4, 8) :|: 0 = 0
49.42/15.94	Combined rules. Obtained 1 rulesP rules:
49.42/15.94	f_749(v532:0, v533:0, v534:0, v535:0, v536:0, v537:0, v538:0, v539:0, v540:0, v541:0, v542:0, v543:0, 1, 1 + v602:0, v546:0, v547:0, v548:0, v549:0, v550:0, v551:0, v552:0, v553:0, v554:0, v555:0, v556:0, v557:0, 0, 3, 7, 4, 8) -> f_749(v532:0, v533:0, v534:0, v535:0, v536:0, v537:0, v538:0, v539:0, v540:0, v541:0, 1 + v602:0, 1 + v602:0 + v533:0, 1, v602:0, v547:0, 1 + v547:0, v548:0, v549:0, v550:0, v551:0, v552:0, v553:0, v554:0, v555:0, v556:0, v557:0, 0, 3, 7, 4, 8) :|: 1 + v602:0 + v533:0 > 0 && v542:0 > 1 && v602:0 > -1 && v532:0 > 1 && v547:0 > 0
49.42/15.94	Filtered unneeded arguments:
49.42/15.94	   f_749(x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, x16, x17, x18, x19, x20, x21, x22, x23, x24, x25, x26, x27, x28, x29, x30, x31) -> f_749(x1, x2, x11, x14, x16)
49.42/15.94	Removed division, modulo operations, cleaned up constraints. Obtained 1 rules.P rules:
49.42/15.94	f_749(v532:0, v533:0, v542:0, sum~cons_1~v602:0, v547:0) -> f_749(v532:0, v533:0, 1 + v602:0, v602:0, 1 + v547:0) :|: v542:0 > 1 && 1 + v602:0 + v533:0 > 0 && v602:0 > -1 && v547:0 > 0 && v532:0 > 1 && sum~cons_1~v602:0 = 1 + v602:0
49.42/15.94	
49.42/15.94	----------------------------------------
49.42/15.94	
49.42/15.94	(23)
49.42/15.94	Obligation:
49.42/15.94	Rules:
49.42/15.94	f_749(v532:0, v533:0, v542:0, sum~cons_1~v602:0, v547:0) -> f_749(v532:0, v533:0, 1 + v602:0, v602:0, 1 + v547:0) :|: v542:0 > 1 && 1 + v602:0 + v533:0 > 0 && v602:0 > -1 && v547:0 > 0 && v532:0 > 1 && sum~cons_1~v602:0 = 1 + v602:0
49.42/15.94	
49.42/15.94	----------------------------------------
49.42/15.94	
49.42/15.94	(24) IntTRSCompressionProof (EQUIVALENT)
49.42/15.94	Compressed rules.
49.42/15.94	----------------------------------------
49.42/15.94	
49.42/15.94	(25)
49.42/15.94	Obligation:
49.42/15.94	Rules:
49.42/15.94	f_749(v532:0:0, v533:0:0, v542:0:0, sum~cons_1~v602:0:0, v547:0:0) -> f_749(v532:0:0, v533:0:0, 1 + v602:0:0, v602:0:0, 1 + v547:0:0) :|: v547:0:0 > 0 && v532:0:0 > 1 && v602:0:0 > -1 && 1 + v602:0:0 + v533:0:0 > 0 && v542:0:0 > 1 && sum~cons_1~v602:0:0 = 1 + v602:0:0
49.42/15.94	
49.42/15.94	----------------------------------------
49.42/15.94	
49.42/15.94	(26) PolynomialOrderProcessor (EQUIVALENT)
49.42/15.94	Found the following polynomial interpretation:
49.42/15.94	[f_749(x, x1, x2, x3, x4)] = x3
49.42/15.94	
49.42/15.94	The following rules are decreasing:
49.42/15.94	f_749(v532:0:0, v533:0:0, v542:0:0, sum~cons_1~v602:0:0, v547:0:0) -> f_749(v532:0:0, v533:0:0, 1 + v602:0:0, v602:0:0, 1 + v547:0:0) :|: v547:0:0 > 0 && v532:0:0 > 1 && v602:0:0 > -1 && 1 + v602:0:0 + v533:0:0 > 0 && v542:0:0 > 1 && sum~cons_1~v602:0:0 = 1 + v602:0:0
49.42/15.94	The following rules are bounded:
49.42/15.94	f_749(v532:0:0, v533:0:0, v542:0:0, sum~cons_1~v602:0:0, v547:0:0) -> f_749(v532:0:0, v533:0:0, 1 + v602:0:0, v602:0:0, 1 + v547:0:0) :|: v547:0:0 > 0 && v532:0:0 > 1 && v602:0:0 > -1 && 1 + v602:0:0 + v533:0:0 > 0 && v542:0:0 > 1 && sum~cons_1~v602:0:0 = 1 + v602:0:0
49.42/15.94	
49.42/15.94	----------------------------------------
49.42/15.94	
49.42/15.94	(27)
49.42/15.94	YES
49.51/16.02	EOF