23.17/6.71	YES
23.17/6.72	proof of /export/starexec/sandbox2/benchmark/theBenchmark.c
23.17/6.72	# AProVE Commit ID: 48fb2092695e11cc9f56e44b17a92a5f88ffb256 marcel 20180622 unpublished dirty
23.17/6.72	
23.17/6.72	
23.17/6.72	Termination of the given C Problem could be proven:
23.17/6.72	
23.17/6.72	(0) C Problem
23.17/6.72	(1) CToLLVMProof [EQUIVALENT, 151 ms]
23.17/6.72	(2) LLVM problem
23.17/6.72	(3) LLVMToTerminationGraphProof [EQUIVALENT, 1404 ms]
23.17/6.72	(4) LLVM Symbolic Execution Graph
23.17/6.72	(5) SymbolicExecutionGraphToSCCProof [SOUND, 0 ms]
23.17/6.72	(6) AND
23.17/6.72	    (7) LLVM Symbolic Execution SCC
23.17/6.72	        (8) SCC2IRS [SOUND, 0 ms]
23.17/6.72	        (9) IntTRS
23.17/6.72	        (10) IntTRSCompressionProof [EQUIVALENT, 0 ms]
23.17/6.72	        (11) IntTRS
23.17/6.72	        (12) PolynomialOrderProcessor [EQUIVALENT, 0 ms]
23.17/6.72	        (13) YES
23.17/6.72	    (14) LLVM Symbolic Execution SCC
23.17/6.72	        (15) SCC2IRS [SOUND, 0 ms]
23.17/6.72	        (16) IntTRS
23.17/6.72	        (17) IntTRSCompressionProof [EQUIVALENT, 0 ms]
23.17/6.72	        (18) IntTRS
23.17/6.72	        (19) RankingReductionPairProof [EQUIVALENT, 8 ms]
23.17/6.72	        (20) YES
23.17/6.72	
23.17/6.72	
23.17/6.72	----------------------------------------
23.17/6.72	
23.17/6.72	(0)
23.17/6.72	Obligation:
23.17/6.72	c file /export/starexec/sandbox2/benchmark/theBenchmark.c
23.17/6.72	----------------------------------------
23.17/6.72	
23.17/6.72	(1) CToLLVMProof (EQUIVALENT)
23.17/6.72	Compiled c-file /export/starexec/sandbox2/benchmark/theBenchmark.c to LLVM.
23.17/6.72	----------------------------------------
23.17/6.72	
23.17/6.72	(2)
23.17/6.72	Obligation:
23.17/6.72	LLVM Problem
23.17/6.72	
23.17/6.72	Aliases:
23.17/6.72	
23.17/6.72	Data layout:
23.17/6.72	
23.17/6.72	"e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
23.17/6.72	
23.17/6.72	Machine:
23.17/6.72	
23.17/6.72	"x86_64-pc-linux-gnu"
23.17/6.72	
23.17/6.72	Type definitions:
23.17/6.72	
23.17/6.72	Global variables:
23.17/6.72	
23.17/6.72	Function declarations and definitions:
23.17/6.72	
23.17/6.72	*BasicFunctionTypename: "__VERIFIER_nondet_int" returnParam: i32 parameters: () variableLength: false visibilityType: DEFAULT callingConvention: ccc
23.17/6.72	*BasicFunctionTypename: "main" linkageType: EXTERNALLY_VISIBLE returnParam: i32 parameters: () variableLength: false visibilityType: DEFAULT callingConvention: ccc
23.17/6.72		0:
23.17/6.72			%1 = alloca i32, align 4
23.17/6.72			%x = alloca i32, align 4
23.17/6.72			%y = alloca i32, align 4
23.17/6.72			%z = alloca i32, align 4
23.17/6.72			store 0, %1
23.17/6.72			%2 = call i32 @__VERIFIER_nondet_int()
23.17/6.72			store %2, %y
23.17/6.72			%3 = call i32 @__VERIFIER_nondet_int()
23.17/6.72			store %3, %z
23.17/6.72			%4 = call i32 @__VERIFIER_nondet_int()
23.17/6.72			%5 = icmp ne %4 0
23.17/6.72			br %5, %6, %7
23.17/6.72		6:
23.17/6.72			store 1, %x
23.17/6.72			br %8
23.17/6.72		7:
23.17/6.72			store -1, %x
23.17/6.72			br %8
23.17/6.72		8:
23.17/6.72			br %9
23.17/6.72		9:
23.17/6.72			%10 = load %y
23.17/6.72			%11 = icmp slt %10 100
23.17/6.72			br %11, %12, %15
23.17/6.72		12:
23.17/6.72			%13 = load %z
23.17/6.72			%14 = icmp slt %13 100
23.17/6.72			br %15
23.17/6.72		15:
23.17/6.72			%16 = phi [0, %9], [%14, %12]
23.17/6.72			br %16, %17, %24
23.17/6.72		17:
23.17/6.72			%18 = load %y
23.17/6.72			%19 = load %x
23.17/6.72			%20 = add %18 %19
23.17/6.72			store %20, %y
23.17/6.72			%21 = load %z
23.17/6.72			%22 = load %x
23.17/6.72			%23 = sub %21 %22
23.17/6.72			store %23, %z
23.17/6.72			br %9
23.17/6.72		24:
23.17/6.72			ret 0
23.17/6.72	
23.17/6.72	
23.17/6.72	Analyze Termination of all function calls matching the pattern:
23.17/6.72	main()
23.17/6.72	----------------------------------------
23.17/6.72	
23.17/6.72	(3) LLVMToTerminationGraphProof (EQUIVALENT)
23.17/6.72	Constructed symbolic execution graph for LLVM program and proved memory safety.
23.17/6.72	----------------------------------------
23.17/6.72	
23.17/6.72	(4)
23.17/6.72	Obligation:
23.17/6.72	SE Graph
23.17/6.72	----------------------------------------
23.17/6.72	
23.17/6.72	(5) SymbolicExecutionGraphToSCCProof (SOUND)
23.17/6.72	Splitted symbolic execution graph to 2 SCCs.
23.17/6.72	----------------------------------------
23.17/6.72	
23.17/6.72	(6)
23.17/6.72	Complex Obligation (AND)
23.17/6.72	
23.17/6.72	----------------------------------------
23.17/6.72	
23.17/6.72	(7)
23.17/6.72	Obligation:
23.17/6.72	SCC
23.17/6.72	----------------------------------------
23.17/6.72	
23.17/6.72	(8) SCC2IRS (SOUND)
23.17/6.72	Transformed LLVM symbolic execution graph SCC into a rewrite problem. Log: 
23.17/6.72	Generated rules. Obtained 18 rulesP rules:
23.17/6.72	f_272(v715, v716, v717, v718, v719, v720, 0, v726, 1, v724, v722, -1, v727, v728, v729, v730, v731, 3, 99, 98, 100, 4) -> f_275(v715, v716, v717, v718, v719, v720, 0, v726, 1, v724, v722, -1, v727, v728, v729, v730, v731, 3, 99, 98, 100, 4) :|: 0 = 0
23.17/6.72	f_275(v715, v716, v717, v718, v719, v720, 0, v726, 1, v724, v722, -1, v727, v728, v729, v730, v731, 3, 99, 98, 100, 4) -> f_278(v715, v716, v717, v718, v719, v720, 0, v726, 1, v724, v722, -1, v727, v728, v729, v730, v731, 3, 99, 98, 100, 4) :|: TRUE
23.17/6.72	f_278(v715, v716, v717, v718, v719, v720, 0, v726, 1, v724, v722, -1, v727, v728, v729, v730, v731, 3, 99, 98, 100, 4) -> f_281(v715, v716, v717, v718, v719, v720, 0, v726, 1, v727, v722, -1, v724, v728, v729, v730, v731, 3, 99, 98, 100, 4) :|: 0 = 0
23.17/6.72	f_281(v715, v716, v717, v718, v719, v720, 0, v726, 1, v727, v722, -1, v724, v728, v729, v730, v731, 3, 99, 98, 100, 4) -> f_284(v715, v716, v717, v718, v719, v720, 0, v726, 1, v727, v722, -1, v724, v728, v729, v730, v731, 3, 99, 98, 4) :|: v727 < 100 && v724 <= 98 && v720 <= 98
23.17/6.72	f_284(v715, v716, v717, v718, v719, v720, 0, v726, 1, v727, v722, -1, v724, v728, v729, v730, v731, 3, 99, 98, 4) -> f_287(v715, v716, v717, v718, v719, v720, 0, v726, 1, v727, v722, -1, v724, v728, v729, v730, v731, 3, 99, 98, 4) :|: 0 = 0
23.17/6.72	f_287(v715, v716, v717, v718, v719, v720, 0, v726, 1, v727, v722, -1, v724, v728, v729, v730, v731, 3, 99, 98, 4) -> f_290(v715, v716, v717, v718, v719, v720, 0, v726, 1, v727, v722, -1, v724, v728, v729, v730, v731, 3, 99, 98, 4) :|: 0 = 0
23.17/6.72	f_290(v715, v716, v717, v718, v719, v720, 0, v726, 1, v727, v722, -1, v724, v728, v729, v730, v731, 3, 99, 98, 4) -> f_293(v715, v716, v717, v718, v719, v720, 0, v726, 1, v727, v722, -1, v724, v728, v729, v730, v731, 3, 99, 98, 4) :|: TRUE
23.17/6.72	f_293(v715, v716, v717, v718, v719, v720, 0, v726, 1, v727, v722, -1, v724, v728, v729, v730, v731, 3, 99, 98, 4) -> f_296(v715, v716, v717, v718, v719, v720, 0, v726, 1, v727, -1, v724, v728, v729, v730, v731, 3, 99, 98, 4) :|: 0 = 0
23.17/6.72	f_296(v715, v716, v717, v718, v719, v720, 0, v726, 1, v727, -1, v724, v728, v729, v730, v731, 3, 99, 98, 4) -> f_298(v715, v716, v717, v718, v719, v720, 0, v726, 1, v727, -1, v724, v728, v729, v730, v731, 3, 99, 98, 4) :|: 0 = 0
23.17/6.72	f_298(v715, v716, v717, v718, v719, v720, 0, v726, 1, v727, -1, v724, v728, v729, v730, v731, 3, 99, 98, 4) -> f_300(v715, v716, v717, v718, v719, v720, 0, v726, 1, v727, -1, v958, v724, v728, v729, v730, v731, 3, 99, 98, 4, 97) :|: 1 + v958 = v726 && v958 <= 97
23.17/6.72	f_300(v715, v716, v717, v718, v719, v720, 0, v726, 1, v727, -1, v958, v724, v728, v729, v730, v731, 3, 99, 98, 4, 97) -> f_302(v715, v716, v717, v718, v719, v720, 0, v726, 1, v727, -1, v958, v724, v728, v729, v730, v731, 3, 99, 98, 4, 97) :|: TRUE
23.17/6.72	f_302(v715, v716, v717, v718, v719, v720, 0, v726, 1, v727, -1, v958, v724, v728, v729, v730, v731, 3, 99, 98, 4, 97) -> f_304(v715, v716, v717, v718, v719, v720, 0, v726, 1, v727, -1, v958, v728, v729, v730, v731, 3, 99, 98, 4, 97) :|: 0 = 0
23.17/6.72	f_304(v715, v716, v717, v718, v719, v720, 0, v726, 1, v727, -1, v958, v728, v729, v730, v731, 3, 99, 98, 4, 97) -> f_306(v715, v716, v717, v718, v719, v720, 0, v726, 1, v727, -1, v958, v728, v729, v730, v731, 3, 99, 98, 4, 97) :|: 0 = 0
23.17/6.72	f_306(v715, v716, v717, v718, v719, v720, 0, v726, 1, v727, -1, v958, v728, v729, v730, v731, 3, 99, 98, 4, 97) -> f_308(v715, v716, v717, v718, v719, v720, 0, v726, 1, v727, -1, v958, v962, v728, v729, v730, v731, 3, 99, 98, 4, 97, 100) :|: v962 = 1 + v727 && v962 <= 100
23.17/6.72	f_308(v715, v716, v717, v718, v719, v720, 0, v726, 1, v727, -1, v958, v962, v728, v729, v730, v731, 3, 99, 98, 4, 97, 100) -> f_310(v715, v716, v717, v718, v719, v720, 0, v726, 1, v727, -1, v958, v962, v728, v729, v730, v731, 3, 99, 98, 4, 97, 100) :|: TRUE
23.17/6.72	f_310(v715, v716, v717, v718, v719, v720, 0, v726, 1, v727, -1, v958, v962, v728, v729, v730, v731, 3, 99, 98, 4, 97, 100) -> f_312(v715, v716, v717, v718, v719, v720, 0, v726, 1, v727, -1, v958, v962, v728, v729, v730, v731, 3, 99, 98, 4, 97, 100) :|: TRUE
23.17/6.72	f_312(v715, v716, v717, v718, v719, v720, 0, v726, 1, v727, -1, v958, v962, v728, v729, v730, v731, 3, 99, 98, 4, 97, 100) -> f_270(v715, v716, v717, v718, v719, v720, 0, v726, 1, v727, -1, v958, v962, v728, v729, v730, v731, 3, 99, 98, 100, 4) :|: TRUE
23.17/6.72	f_270(v715, v716, v717, v718, v719, v720, 0, v722, 1, v724, -1, v726, v727, v728, v729, v730, v731, 3, 99, 98, 100, 4) -> f_272(v715, v716, v717, v718, v719, v720, 0, v726, 1, v724, v722, -1, v727, v728, v729, v730, v731, 3, 99, 98, 100, 4) :|: 0 = 0
23.17/6.72	Combined rules. Obtained 1 rulesP rules:
23.17/6.72	f_272(v715:0, v716:0, v717:0, v718:0, v719:0, v720:0, 0, 1 + v958:0, 1, v724:0, v722:0, -1, v727:0, v728:0, v729:0, v730:0, v731:0, 3, 99, 98, 100, 4) -> f_272(v715:0, v716:0, v717:0, v718:0, v719:0, v720:0, 0, v958:0, 1, v727:0, 1 + v958:0, -1, 1 + v727:0, v728:0, v729:0, v730:0, v731:0, 3, 99, 98, 100, 4) :|: v724:0 < 99 && v727:0 < 100 && v720:0 < 99 && v958:0 < 98
23.17/6.72	Filtered unneeded arguments:
23.17/6.72	   f_272(x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, x16, x17, x18, x19, x20, x21, x22) -> f_272(x6, x8, x10, x13)
23.17/6.72	Removed division, modulo operations, cleaned up constraints. Obtained 1 rules.P rules:
23.17/6.72	f_272(v720:0, sum~cons_1~v958:0, v724:0, v727:0) -> f_272(v720:0, v958:0, v727:0, 1 + v727:0) :|: v727:0 < 100 && v724:0 < 99 && v958:0 < 98 && v720:0 < 99 && sum~cons_1~v958:0 = 1 + v958:0
23.17/6.72	
23.17/6.72	----------------------------------------
23.17/6.72	
23.17/6.72	(9)
23.17/6.72	Obligation:
23.17/6.72	Rules:
23.17/6.72	f_272(v720:0, sum~cons_1~v958:0, v724:0, v727:0) -> f_272(v720:0, v958:0, v727:0, 1 + v727:0) :|: v727:0 < 100 && v724:0 < 99 && v958:0 < 98 && v720:0 < 99 && sum~cons_1~v958:0 = 1 + v958:0
23.17/6.72	
23.17/6.72	----------------------------------------
23.17/6.72	
23.17/6.72	(10) IntTRSCompressionProof (EQUIVALENT)
23.17/6.72	Compressed rules.
23.17/6.72	----------------------------------------
23.17/6.72	
23.17/6.72	(11)
23.17/6.72	Obligation:
23.17/6.72	Rules:
23.17/6.72	f_272(v720:0:0, sum~cons_1~v958:0:0, v724:0:0, v727:0:0) -> f_272(v720:0:0, v958:0:0, v727:0:0, 1 + v727:0:0) :|: v958:0:0 < 98 && v720:0:0 < 99 && v724:0:0 < 99 && v727:0:0 < 100 && sum~cons_1~v958:0:0 = 1 + v958:0:0
23.17/6.72	
23.17/6.72	----------------------------------------
23.17/6.72	
23.17/6.72	(12) PolynomialOrderProcessor (EQUIVALENT)
23.17/6.72	Found the following polynomial interpretation:
23.17/6.72	[f_272(x, x1, x2, x3)] = 99 - x3
23.17/6.72	
23.17/6.72	The following rules are decreasing:
23.17/6.72	f_272(v720:0:0, sum~cons_1~v958:0:0, v724:0:0, v727:0:0) -> f_272(v720:0:0, v958:0:0, v727:0:0, 1 + v727:0:0) :|: v958:0:0 < 98 && v720:0:0 < 99 && v724:0:0 < 99 && v727:0:0 < 100 && sum~cons_1~v958:0:0 = 1 + v958:0:0
23.17/6.72	The following rules are bounded:
23.17/6.72	f_272(v720:0:0, sum~cons_1~v958:0:0, v724:0:0, v727:0:0) -> f_272(v720:0:0, v958:0:0, v727:0:0, 1 + v727:0:0) :|: v958:0:0 < 98 && v720:0:0 < 99 && v724:0:0 < 99 && v727:0:0 < 100 && sum~cons_1~v958:0:0 = 1 + v958:0:0
23.17/6.72	
23.17/6.72	----------------------------------------
23.17/6.72	
23.17/6.72	(13)
23.17/6.72	YES
23.17/6.72	
23.17/6.72	----------------------------------------
23.17/6.72	
23.17/6.72	(14)
23.17/6.72	Obligation:
23.17/6.72	SCC
23.17/6.72	----------------------------------------
23.17/6.72	
23.17/6.72	(15) SCC2IRS (SOUND)
23.17/6.72	Transformed LLVM symbolic execution graph SCC into a rewrite problem. Log: 
23.17/6.72	Generated rules. Obtained 18 rulesP rules:
23.17/6.72	f_271(v684, v685, v686, v687, v688, v689, v690, 1, v694, v693, v692, v695, v696, v697, v698, v699, 0, 3, 99, 100, 98, 4) -> f_273(v684, v685, v686, v687, v688, v689, v690, 1, v694, v693, v692, v695, v696, v697, v698, v699, 0, 3, 98, 99, 4) :|: v694 < 100 && v692 <= 98 && v688 <= 98
23.17/6.72	f_273(v684, v685, v686, v687, v688, v689, v690, 1, v694, v693, v692, v695, v696, v697, v698, v699, 0, 3, 98, 99, 4) -> f_276(v684, v685, v686, v687, v688, v689, v690, 1, v694, v693, v692, v695, v696, v697, v698, v699, 0, 3, 98, 99, 4) :|: 0 = 0
23.17/6.72	f_276(v684, v685, v686, v687, v688, v689, v690, 1, v694, v693, v692, v695, v696, v697, v698, v699, 0, 3, 98, 99, 4) -> f_279(v684, v685, v686, v687, v688, v689, v690, 1, v694, v693, v692, v695, v696, v697, v698, v699, 0, 3, 98, 99, 4) :|: TRUE
23.17/6.72	f_279(v684, v685, v686, v687, v688, v689, v690, 1, v694, v693, v692, v695, v696, v697, v698, v699, 0, 3, 98, 99, 4) -> f_282(v684, v685, v686, v687, v688, v689, v690, 1, v694, v695, v692, v693, v696, v697, v698, v699, 0, 3, 98, 99, 4) :|: 0 = 0
23.17/6.72	f_282(v684, v685, v686, v687, v688, v689, v690, 1, v694, v695, v692, v693, v696, v697, v698, v699, 0, 3, 98, 99, 4) -> f_286(v684, v685, v686, v687, v688, v689, v690, 1, v694, v695, v692, v693, v696, v697, v698, v699, 0, 3, 98, 99, 4) :|: 0 = 0
23.17/6.72	f_286(v684, v685, v686, v687, v688, v689, v690, 1, v694, v695, v692, v693, v696, v697, v698, v699, 0, 3, 98, 99, 4) -> f_289(v684, v685, v686, v687, v688, v689, v690, 1, v694, v695, v692, v693, v696, v697, v698, v699, 0, 3, 98, 99, 4) :|: 0 = 0
23.17/6.72	f_289(v684, v685, v686, v687, v688, v689, v690, 1, v694, v695, v692, v693, v696, v697, v698, v699, 0, 3, 98, 99, 4) -> f_292(v684, v685, v686, v687, v688, v689, v690, 1, v694, v695, v692, v693, v696, v697, v698, v699, 0, 3, 98, 99, 4) :|: TRUE
23.17/6.72	f_292(v684, v685, v686, v687, v688, v689, v690, 1, v694, v695, v692, v693, v696, v697, v698, v699, 0, 3, 98, 99, 4) -> f_295(v684, v685, v686, v687, v688, v689, v690, 1, v694, v695, v693, v696, v697, v698, v699, 0, 3, 98, 99, 4) :|: 0 = 0
23.17/6.72	f_295(v684, v685, v686, v687, v688, v689, v690, 1, v694, v695, v693, v696, v697, v698, v699, 0, 3, 98, 99, 4) -> f_297(v684, v685, v686, v687, v688, v689, v690, 1, v694, v695, v693, v696, v697, v698, v699, 0, 3, 98, 99, 4) :|: 0 = 0
23.17/6.72	f_297(v684, v685, v686, v687, v688, v689, v690, 1, v694, v695, v693, v696, v697, v698, v699, 0, 3, 98, 99, 4) -> f_299(v684, v685, v686, v687, v688, v689, v690, 1, v694, v695, v957, v693, v696, v697, v698, v699, 0, 3, 98, 99, 4, 100) :|: v957 = 1 + v694 && v957 <= 100
23.17/6.72	f_299(v684, v685, v686, v687, v688, v689, v690, 1, v694, v695, v957, v693, v696, v697, v698, v699, 0, 3, 98, 99, 4, 100) -> f_301(v684, v685, v686, v687, v688, v689, v690, 1, v694, v695, v957, v693, v696, v697, v698, v699, 0, 3, 98, 99, 4, 100) :|: TRUE
23.17/6.72	f_301(v684, v685, v686, v687, v688, v689, v690, 1, v694, v695, v957, v693, v696, v697, v698, v699, 0, 3, 98, 99, 4, 100) -> f_303(v684, v685, v686, v687, v688, v689, v690, 1, v694, v695, v957, v696, v697, v698, v699, 0, 3, 98, 99, 4, 100) :|: 0 = 0
23.17/6.72	f_303(v684, v685, v686, v687, v688, v689, v690, 1, v694, v695, v957, v696, v697, v698, v699, 0, 3, 98, 99, 4, 100) -> f_305(v684, v685, v686, v687, v688, v689, v690, 1, v694, v695, v957, v696, v697, v698, v699, 0, 3, 98, 99, 4, 100) :|: 0 = 0
23.17/6.72	f_305(v684, v685, v686, v687, v688, v689, v690, 1, v694, v695, v957, v696, v697, v698, v699, 0, 3, 98, 99, 4, 100) -> f_307(v684, v685, v686, v687, v688, v689, v690, 1, v694, v695, v957, v961, v696, v697, v698, v699, 0, 3, 98, 99, 4, 100, 97) :|: 1 + v961 = v695 && v961 <= 97
23.17/6.72	f_307(v684, v685, v686, v687, v688, v689, v690, 1, v694, v695, v957, v961, v696, v697, v698, v699, 0, 3, 98, 99, 4, 100, 97) -> f_309(v684, v685, v686, v687, v688, v689, v690, 1, v694, v695, v957, v961, v696, v697, v698, v699, 0, 3, 98, 99, 4, 100, 97) :|: TRUE
23.17/6.72	f_309(v684, v685, v686, v687, v688, v689, v690, 1, v694, v695, v957, v961, v696, v697, v698, v699, 0, 3, 98, 99, 4, 100, 97) -> f_311(v684, v685, v686, v687, v688, v689, v690, 1, v694, v695, v957, v961, v696, v697, v698, v699, 0, 3, 98, 99, 4, 100, 97) :|: TRUE
23.17/6.72	f_311(v684, v685, v686, v687, v688, v689, v690, 1, v694, v695, v957, v961, v696, v697, v698, v699, 0, 3, 98, 99, 4, 100, 97) -> f_268(v684, v685, v686, v687, v688, v689, v690, 1, v694, v695, v957, v961, v696, v697, v698, v699, 0, 3, 99, 100, 98, 4) :|: TRUE
23.17/6.72	f_268(v684, v685, v686, v687, v688, v689, v690, 1, v692, v693, v694, v695, v696, v697, v698, v699, 0, 3, 99, 100, 98, 4) -> f_271(v684, v685, v686, v687, v688, v689, v690, 1, v694, v693, v692, v695, v696, v697, v698, v699, 0, 3, 99, 100, 98, 4) :|: 0 = 0
23.17/6.72	Combined rules. Obtained 1 rulesP rules:
23.17/6.72	f_271(v684:0, v685:0, v686:0, v687:0, v688:0, v689:0, v690:0, 1, v694:0, v693:0, v692:0, 1 + v961:0, v696:0, v697:0, v698:0, v699:0, 0, 3, 99, 100, 98, 4) -> f_271(v684:0, v685:0, v686:0, v687:0, v688:0, v689:0, v690:0, 1, 1 + v694:0, 1 + v961:0, v694:0, v961:0, v696:0, v697:0, v698:0, v699:0, 0, 3, 99, 100, 98, 4) :|: v692:0 < 99 && v694:0 < 100 && v688:0 < 99 && v961:0 < 98
23.17/6.72	Filtered unneeded arguments:
23.17/6.72	   f_271(x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, x16, x17, x18, x19, x20, x21, x22) -> f_271(x5, x9, x11, x12)
23.17/6.72	Removed division, modulo operations, cleaned up constraints. Obtained 1 rules.P rules:
23.17/6.72	f_271(v688:0, v694:0, v692:0, sum~cons_1~v961:0) -> f_271(v688:0, 1 + v694:0, v694:0, v961:0) :|: v694:0 < 100 && v692:0 < 99 && v961:0 < 98 && v688:0 < 99 && sum~cons_1~v961:0 = 1 + v961:0
23.17/6.72	
23.17/6.72	----------------------------------------
23.17/6.72	
23.17/6.72	(16)
23.17/6.72	Obligation:
23.17/6.72	Rules:
23.17/6.72	f_271(v688:0, v694:0, v692:0, sum~cons_1~v961:0) -> f_271(v688:0, 1 + v694:0, v694:0, v961:0) :|: v694:0 < 100 && v692:0 < 99 && v961:0 < 98 && v688:0 < 99 && sum~cons_1~v961:0 = 1 + v961:0
23.17/6.72	
23.17/6.72	----------------------------------------
23.17/6.72	
23.17/6.72	(17) IntTRSCompressionProof (EQUIVALENT)
23.17/6.72	Compressed rules.
23.17/6.72	----------------------------------------
23.17/6.72	
23.17/6.72	(18)
23.17/6.72	Obligation:
23.17/6.72	Rules:
23.17/6.72	f_271(v688:0:0, v694:0:0, v692:0:0, sum~cons_1~v961:0:0) -> f_271(v688:0:0, 1 + v694:0:0, v694:0:0, v961:0:0) :|: v961:0:0 < 98 && v688:0:0 < 99 && v692:0:0 < 99 && v694:0:0 < 100 && sum~cons_1~v961:0:0 = 1 + v961:0:0
23.17/6.72	
23.17/6.72	----------------------------------------
23.17/6.72	
23.17/6.72	(19) RankingReductionPairProof (EQUIVALENT)
23.17/6.72	Interpretation:
23.17/6.72	[ f_271 ] = -1*f_271_2
23.17/6.72	
23.17/6.72	The following rules are decreasing:
23.17/6.72	f_271(v688:0:0, v694:0:0, v692:0:0, sum~cons_1~v961:0:0) -> f_271(v688:0:0, 1 + v694:0:0, v694:0:0, v961:0:0) :|: v961:0:0 < 98 && v688:0:0 < 99 && v692:0:0 < 99 && v694:0:0 < 100 && sum~cons_1~v961:0:0 = 1 + v961:0:0
23.17/6.72	
23.17/6.72	The following rules are bounded:
23.17/6.72	f_271(v688:0:0, v694:0:0, v692:0:0, sum~cons_1~v961:0:0) -> f_271(v688:0:0, 1 + v694:0:0, v694:0:0, v961:0:0) :|: v961:0:0 < 98 && v688:0:0 < 99 && v692:0:0 < 99 && v694:0:0 < 100 && sum~cons_1~v961:0:0 = 1 + v961:0:0
23.17/6.72	
23.17/6.72	
23.17/6.72	----------------------------------------
23.17/6.72	
23.17/6.72	(20)
23.17/6.72	YES
23.55/6.77	EOF