38.03/10.91	YES
39.24/10.94	proof of /export/starexec/sandbox/benchmark/theBenchmark.c
39.24/10.94	# AProVE Commit ID: 48fb2092695e11cc9f56e44b17a92a5f88ffb256 marcel 20180622 unpublished dirty
39.24/10.94	
39.24/10.94	
39.24/10.94	Termination of the given C Problem could be proven:
39.24/10.94	
39.24/10.94	(0) C Problem
39.24/10.94	(1) CToLLVMProof [EQUIVALENT, 154 ms]
39.24/10.94	(2) LLVM problem
39.24/10.94	(3) LLVMToTerminationGraphProof [EQUIVALENT, 4807 ms]
39.24/10.94	(4) LLVM Symbolic Execution Graph
39.24/10.94	(5) SymbolicExecutionGraphToSCCProof [SOUND, 0 ms]
39.24/10.94	(6) AND
39.24/10.94	    (7) LLVM Symbolic Execution SCC
39.24/10.94	        (8) SCC2IRS [SOUND, 69 ms]
39.24/10.94	        (9) IntTRS
39.24/10.94	        (10) IntTRSCompressionProof [EQUIVALENT, 0 ms]
39.24/10.94	        (11) IntTRS
39.24/10.94	        (12) PolynomialOrderProcessor [EQUIVALENT, 0 ms]
39.24/10.94	        (13) YES
39.24/10.94	    (14) LLVM Symbolic Execution SCC
39.24/10.94	        (15) SCC2IRS [SOUND, 47 ms]
39.24/10.94	        (16) IntTRS
39.24/10.94	        (17) IRS2T2 [EQUIVALENT, 0 ms]
39.24/10.94	        (18) T2IntSys
39.24/10.94	        (19) T2 [EQUIVALENT, 922 ms]
39.24/10.94	        (20) YES
39.24/10.94	
39.24/10.94	
39.24/10.94	----------------------------------------
39.24/10.94	
39.24/10.94	(0)
39.24/10.94	Obligation:
39.24/10.94	c file /export/starexec/sandbox/benchmark/theBenchmark.c
39.24/10.94	----------------------------------------
39.24/10.94	
39.24/10.94	(1) CToLLVMProof (EQUIVALENT)
39.24/10.94	Compiled c-file /export/starexec/sandbox/benchmark/theBenchmark.c to LLVM.
39.24/10.94	----------------------------------------
39.24/10.94	
39.24/10.94	(2)
39.24/10.94	Obligation:
39.24/10.94	LLVM Problem
39.24/10.94	
39.24/10.94	Aliases:
39.24/10.94	
39.24/10.94	Data layout:
39.24/10.94	
39.24/10.94	"e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
39.24/10.94	
39.24/10.94	Machine:
39.24/10.94	
39.24/10.94	"x86_64-pc-linux-gnu"
39.24/10.94	
39.24/10.94	Type definitions:
39.24/10.94	
39.24/10.94	Global variables:
39.24/10.94	
39.24/10.94	Function declarations and definitions:
39.24/10.94	
39.24/10.94	*BasicFunctionTypename: "__VERIFIER_nondet_int" returnParam: i32 parameters: () variableLength: false visibilityType: DEFAULT callingConvention: ccc
39.24/10.94	*BasicFunctionTypename: "main" linkageType: EXTERNALLY_VISIBLE returnParam: i32 parameters: () variableLength: false visibilityType: DEFAULT callingConvention: ccc
39.24/10.94		0:
39.24/10.94			%1 = alloca i32, align 4
39.24/10.94			%a = alloca i32, align 4
39.24/10.94			%b = alloca i32, align 4
39.24/10.94			%x = alloca i32, align 4
39.24/10.94			%y = alloca i32, align 4
39.24/10.94			store 0, %1
39.24/10.94			%2 = call i32 @__VERIFIER_nondet_int()
39.24/10.94			store %2, %a
39.24/10.94			%3 = call i32 @__VERIFIER_nondet_int()
39.24/10.94			store %3, %b
39.24/10.94			%4 = call i32 @__VERIFIER_nondet_int()
39.24/10.94			store %4, %x
39.24/10.94			%5 = call i32 @__VERIFIER_nondet_int()
39.24/10.94			store %5, %y
39.24/10.94			%6 = load %a
39.24/10.94			%7 = load %b
39.24/10.94			%8 = icmp eq %6 %7
39.24/10.94			br %8, %9, %32
39.24/10.94		9:
39.24/10.94			br %10
39.24/10.94		10:
39.24/10.94			%11 = load %x
39.24/10.94			%12 = icmp sge %11 0
39.24/10.94			br %12, %16, %13
39.24/10.94		13:
39.24/10.94			%14 = load %y
39.24/10.94			%15 = icmp sge %14 0
39.24/10.94			br %16
39.24/10.94		16:
39.24/10.94			%17 = phi [1, %10], [%15, %13]
39.24/10.94			br %17, %18, %31
39.24/10.94		18:
39.24/10.94			%19 = load %x
39.24/10.94			%20 = load %a
39.24/10.94			%21 = add %19 %20
39.24/10.94			%22 = load %b
39.24/10.94			%23 = sub %21 %22
39.24/10.94			%24 = sub %23 1
39.24/10.94			store %24, %x
39.24/10.94			%25 = load %y
39.24/10.94			%26 = load %b
39.24/10.94			%27 = add %25 %26
39.24/10.94			%28 = load %a
39.24/10.94			%29 = sub %27 %28
39.24/10.94			%30 = sub %29 1
39.24/10.94			store %30, %y
39.24/10.94			br %10
39.24/10.94		31:
39.24/10.94			br %32
39.24/10.94		32:
39.24/10.94			ret 0
39.24/10.94	
39.24/10.94	
39.24/10.94	Analyze Termination of all function calls matching the pattern:
39.24/10.94	main()
39.24/10.94	----------------------------------------
39.24/10.94	
39.24/10.94	(3) LLVMToTerminationGraphProof (EQUIVALENT)
39.24/10.94	Constructed symbolic execution graph for LLVM program and proved memory safety.
39.24/10.94	----------------------------------------
39.24/10.94	
39.24/10.94	(4)
39.24/10.94	Obligation:
39.24/10.94	SE Graph
39.24/10.94	----------------------------------------
39.24/10.94	
39.24/10.94	(5) SymbolicExecutionGraphToSCCProof (SOUND)
39.24/10.94	Splitted symbolic execution graph to 2 SCCs.
39.24/10.94	----------------------------------------
39.24/10.94	
39.24/10.94	(6)
39.24/10.94	Complex Obligation (AND)
39.24/10.94	
39.24/10.94	----------------------------------------
39.24/10.94	
39.24/10.94	(7)
39.24/10.94	Obligation:
39.24/10.94	SCC
39.24/10.94	----------------------------------------
39.24/10.94	
39.24/10.94	(8) SCC2IRS (SOUND)
39.24/10.94	Transformed LLVM symbolic execution graph SCC into a rewrite problem. Log: 
39.24/10.94	Generated rules. Obtained 25 rulesP rules:
39.24/10.94	f_414(v955, v956, v957, v958, v959, v960, v961, v962, 1, v968, 0, v966, v964, v967, v969, v970, v971, v972, v973, v974, v975, 3, 2, 4) -> f_415(v955, v956, v957, v958, v959, v960, v961, v962, 1, v968, 0, v966, v964, v967, v969, v970, v971, v972, v973, v974, v975, 3, 2, 4) :|: 0 = 0
39.24/10.94	f_415(v955, v956, v957, v958, v959, v960, v961, v962, 1, v968, 0, v966, v964, v967, v969, v970, v971, v972, v973, v974, v975, 3, 2, 4) -> f_416(v955, v956, v957, v958, v959, v960, v961, v962, 1, v968, 0, v966, v964, v967, v969, v970, v971, v972, v973, v974, v975, 3, 2, 4) :|: TRUE
39.24/10.94	f_416(v955, v956, v957, v958, v959, v960, v961, v962, 1, v968, 0, v966, v964, v967, v969, v970, v971, v972, v973, v974, v975, 3, 2, 4) -> f_417(v955, v956, v957, v958, v959, v960, v961, v962, 1, v968, 0, v970, v964, v967, v966, v969, v971, v972, v973, v974, v975, 3, 2, 4) :|: 0 = 0
39.24/10.94	f_417(v955, v956, v957, v958, v959, v960, v961, v962, 1, v968, 0, v970, v964, v967, v966, v969, v971, v972, v973, v974, v975, 3, 2, 4) -> f_418(v955, v956, v957, v958, v959, v960, v961, v962, 1, v968, 0, v970, v964, v967, v966, v969, v971, v972, v973, v974, v975, 3, 2, 4) :|: 0 <= v970 && 1 <= v966 && 1 <= v962
39.24/10.94	f_418(v955, v956, v957, v958, v959, v960, v961, v962, 1, v968, 0, v970, v964, v967, v966, v969, v971, v972, v973, v974, v975, 3, 2, 4) -> f_420(v955, v956, v957, v958, v959, v960, v961, v962, 1, v968, 0, v970, v964, v967, v966, v969, v971, v972, v973, v974, v975, 3, 2, 4) :|: 0 = 0
39.24/10.94	f_420(v955, v956, v957, v958, v959, v960, v961, v962, 1, v968, 0, v970, v964, v967, v966, v969, v971, v972, v973, v974, v975, 3, 2, 4) -> f_422(v955, v956, v957, v958, v959, v960, v961, v962, 1, v968, 0, v970, v964, v967, v966, v969, v971, v972, v973, v974, v975, 3, 2, 4) :|: 0 = 0
39.24/10.94	f_422(v955, v956, v957, v958, v959, v960, v961, v962, 1, v968, 0, v970, v964, v967, v966, v969, v971, v972, v973, v974, v975, 3, 2, 4) -> f_423(v955, v956, v957, v958, v959, v960, v961, v962, 1, v968, 0, v964, v967, v966, v969, v970, v971, v972, v973, v974, v975, 3, 4) :|: TRUE
39.24/10.94	f_423(v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 1, v1035, 0, v1037, v1038, v1039, v1040, v1041, v1042, v1043, v1044, v1045, v1046, 3, 4) -> f_425(v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 1, v1035, 0, v1037, v1038, v1039, v1040, v1041, v1042, v1043, v1044, v1045, v1046, 3, 4) :|: TRUE
39.24/10.94	f_425(v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 1, v1035, 0, v1037, v1038, v1039, v1040, v1041, v1042, v1043, v1044, v1045, v1046, 3, 4) -> f_427(v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 1, v1035, 0, v1038, v1037, v1039, v1040, v1041, v1042, v1043, v1044, v1045, v1046, 3, 4) :|: 0 = 0
39.24/10.94	f_427(v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 1, v1035, 0, v1038, v1037, v1039, v1040, v1041, v1042, v1043, v1044, v1045, v1046, 3, 4) -> f_429(v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 1, v1035, 0, v1038, v1037, v1039, v1040, v1041, v1042, v1043, v1044, v1045, v1046, 3, 4) :|: 0 = 0
39.24/10.94	f_429(v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 1, v1035, 0, v1038, v1037, v1039, v1040, v1041, v1042, v1043, v1044, v1045, v1046, 3, 4) -> f_430(v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 1, v1035, 0, v1119, v1037, v1039, v1040, v1041, v1042, v1043, v1044, v1045, v1046, 3, 4) :|: v1119 = v1035 + v1031
39.24/10.94	f_430(v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 1, v1035, 0, v1119, v1037, v1039, v1040, v1041, v1042, v1043, v1044, v1045, v1046, 3, 4) -> f_431(v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 1, v1035, 0, v1119, v1037, v1039, v1040, v1041, v1042, v1043, v1044, v1045, v1046, 3, 4) :|: 0 = 0
39.24/10.94	f_431(v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 1, v1035, 0, v1119, v1037, v1039, v1040, v1041, v1042, v1043, v1044, v1045, v1046, 3, 4) -> f_432(v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 1, v1035, 0, v1119, v1039, v1040, v1041, v1042, v1043, v1044, v1045, v1046, 3, 4) :|: v1035 + v1031 = v1119
39.24/10.94	f_432(v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 1, v1035, 0, v1119, v1039, v1040, v1041, v1042, v1043, v1044, v1045, v1046, 3, 4) -> f_433(v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 1, v1035, 0, v1119, v1120, v1039, v1040, v1041, v1042, v1043, v1044, v1045, v1046, 3, 4, 2) :|: 1 + v1120 = v1035 && 2 + v1120 <= 0
39.24/10.94	f_433(v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 1, v1035, 0, v1119, v1120, v1039, v1040, v1041, v1042, v1043, v1044, v1045, v1046, 3, 4, 2) -> f_434(v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 1, v1035, 0, v1119, v1120, v1039, v1040, v1041, v1042, v1043, v1044, v1045, v1046, 3, 4, 2) :|: TRUE
39.24/10.94	f_434(v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 1, v1035, 0, v1119, v1120, v1039, v1040, v1041, v1042, v1043, v1044, v1045, v1046, 3, 4, 2) -> f_435(v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 1, v1035, 0, v1119, v1120, v1041, v1040, v1039, v1042, v1043, v1044, v1045, v1046, 3, 4, 2) :|: 0 = 0
39.24/10.94	f_435(v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 1, v1035, 0, v1119, v1120, v1041, v1040, v1039, v1042, v1043, v1044, v1045, v1046, 3, 4, 2) -> f_436(v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 1, v1035, 0, v1119, v1120, v1041, v1040, v1039, v1042, v1043, v1044, v1045, v1046, 3, 4, 2) :|: 0 = 0
39.24/10.94	f_436(v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 1, v1035, 0, v1119, v1120, v1041, v1040, v1039, v1042, v1043, v1044, v1045, v1046, 3, 4, 2) -> f_437(v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 1, v1035, 0, v1119, v1120, v1041, v1122, v1039, v1042, v1043, v1044, v1045, v1046, 3, 4, 2) :|: v1122 = v1041 + v1031
39.24/10.94	f_437(v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 1, v1035, 0, v1119, v1120, v1041, v1122, v1039, v1042, v1043, v1044, v1045, v1046, 3, 4, 2) -> f_438(v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 1, v1035, 0, v1119, v1120, v1041, v1122, v1039, v1042, v1043, v1044, v1045, v1046, 3, 4, 2) :|: 0 = 0
39.24/10.94	f_438(v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 1, v1035, 0, v1119, v1120, v1041, v1122, v1039, v1042, v1043, v1044, v1045, v1046, 3, 4, 2) -> f_439(v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 1, v1035, 0, v1119, v1120, v1041, v1122, v1042, v1043, v1044, v1045, v1046, 3, 4, 2) :|: v1041 + v1031 = v1122
39.24/10.94	f_439(v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 1, v1035, 0, v1119, v1120, v1041, v1122, v1042, v1043, v1044, v1045, v1046, 3, 4, 2) -> f_440(v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 1, v1035, 0, v1119, v1120, v1041, v1122, v1123, v1042, v1043, v1044, v1045, v1046, 3, 4, 2) :|: 1 + v1123 = v1041 && 0 <= 1 + v1123
39.24/10.94	f_440(v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 1, v1035, 0, v1119, v1120, v1041, v1122, v1123, v1042, v1043, v1044, v1045, v1046, 3, 4, 2) -> f_441(v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 1, v1035, 0, v1119, v1120, v1041, v1122, v1123, v1042, v1043, v1044, v1045, v1046, 3, 4, 2) :|: TRUE
39.24/10.94	f_441(v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 1, v1035, 0, v1119, v1120, v1041, v1122, v1123, v1042, v1043, v1044, v1045, v1046, 3, 4, 2) -> f_442(v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 1, v1035, 0, v1119, v1120, v1041, v1122, v1123, v1042, v1043, v1044, v1045, v1046, 3, 4, 2) :|: TRUE
39.24/10.94	f_442(v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 1, v1035, 0, v1119, v1120, v1041, v1122, v1123, v1042, v1043, v1044, v1045, v1046, 3, 4, 2) -> f_413(v1026, v1027, v1028, v1029, v1030, v1031, v1032, v1033, 1, v1035, 0, v1041, v1119, v1120, v1122, v1123, v1042, v1043, v1044, v1045, v1046, 3, 2, 4) :|: TRUE
39.24/10.94	f_413(v955, v956, v957, v958, v959, v960, v961, v962, 1, v964, 0, v966, v967, v968, v969, v970, v971, v972, v973, v974, v975, 3, 2, 4) -> f_414(v955, v956, v957, v958, v959, v960, v961, v962, 1, v968, 0, v966, v964, v967, v969, v970, v971, v972, v973, v974, v975, 3, 2, 4) :|: 0 = 0
39.24/10.94	Combined rules. Obtained 1 rulesP rules:
39.24/10.94	f_414(v955:0, v956:0, v957:0, v958:0, v959:0, v960:0, v961:0, v962:0, 1, 1 + v1120:0, 0, v966:0, v964:0, v967:0, v969:0, 1 + v1123:0, v971:0, v972:0, v973:0, v974:0, v975:0, 3, 2, 4) -> f_414(v955:0, v956:0, v957:0, v958:0, v959:0, v960:0, v961:0, v962:0, 1, v1120:0, 0, 1 + v1123:0, 1 + v1120:0, 1 + v1120:0 + v960:0, 1 + v1123:0 + v960:0, v1123:0, v971:0, v972:0, v973:0, v974:0, v975:0, 3, 2, 4) :|: v966:0 > 0 && v1123:0 > -2 && v962:0 > 0 && v1120:0 < -1
39.24/10.94	Filtered unneeded arguments:
39.24/10.94	   f_414(x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, x16, x17, x18, x19, x20, x21, x22, x23, x24) -> f_414(x8, x10, x12, x16)
39.24/10.94	Removed division, modulo operations, cleaned up constraints. Obtained 1 rules.P rules:
39.24/10.94	f_414(v962:0, sum~cons_1~v1120:0, v966:0, sum~cons_1~v1123:0) -> f_414(v962:0, v1120:0, 1 + v1123:0, v1123:0) :|: v1123:0 > -2 && v966:0 > 0 && v1120:0 < -1 && v962:0 > 0 && sum~cons_1~v1120:0 = 1 + v1120:0 && sum~cons_1~v1123:0 = 1 + v1123:0
39.24/10.94	
39.24/10.94	----------------------------------------
39.24/10.94	
39.24/10.94	(9)
39.24/10.94	Obligation:
39.24/10.94	Rules:
39.24/10.94	f_414(v962:0, sum~cons_1~v1120:0, v966:0, sum~cons_1~v1123:0) -> f_414(v962:0, v1120:0, 1 + v1123:0, v1123:0) :|: v1123:0 > -2 && v966:0 > 0 && v1120:0 < -1 && v962:0 > 0 && sum~cons_1~v1120:0 = 1 + v1120:0 && sum~cons_1~v1123:0 = 1 + v1123:0
39.24/10.94	
39.24/10.94	----------------------------------------
39.24/10.94	
39.24/10.94	(10) IntTRSCompressionProof (EQUIVALENT)
39.24/10.94	Compressed rules.
39.24/10.94	----------------------------------------
39.24/10.94	
39.24/10.94	(11)
39.24/10.94	Obligation:
39.24/10.94	Rules:
39.24/10.94	f_414(v962:0:0, sum~cons_1~v1120:0:0, v966:0:0, sum~cons_1~v1123:0:0) -> f_414(v962:0:0, v1120:0:0, 1 + v1123:0:0, v1123:0:0) :|: v1120:0:0 < -1 && v962:0:0 > 0 && v966:0:0 > 0 && v1123:0:0 > -2 && sum~cons_1~v1120:0:0 = 1 + v1120:0:0 && sum~cons_1~v1123:0:0 = 1 + v1123:0:0
39.24/10.94	
39.24/10.94	----------------------------------------
39.24/10.94	
39.24/10.94	(12) PolynomialOrderProcessor (EQUIVALENT)
39.24/10.94	Found the following polynomial interpretation:
39.24/10.94	[f_414(x, x1, x2, x3)] = x3
39.24/10.94	
39.24/10.94	The following rules are decreasing:
39.24/10.94	f_414(v962:0:0, sum~cons_1~v1120:0:0, v966:0:0, sum~cons_1~v1123:0:0) -> f_414(v962:0:0, v1120:0:0, 1 + v1123:0:0, v1123:0:0) :|: v1120:0:0 < -1 && v962:0:0 > 0 && v966:0:0 > 0 && v1123:0:0 > -2 && sum~cons_1~v1120:0:0 = 1 + v1120:0:0 && sum~cons_1~v1123:0:0 = 1 + v1123:0:0
39.24/10.94	The following rules are bounded:
39.24/10.94	f_414(v962:0:0, sum~cons_1~v1120:0:0, v966:0:0, sum~cons_1~v1123:0:0) -> f_414(v962:0:0, v1120:0:0, 1 + v1123:0:0, v1123:0:0) :|: v1120:0:0 < -1 && v962:0:0 > 0 && v966:0:0 > 0 && v1123:0:0 > -2 && sum~cons_1~v1120:0:0 = 1 + v1120:0:0 && sum~cons_1~v1123:0:0 = 1 + v1123:0:0
39.24/10.94	
39.24/10.94	----------------------------------------
39.24/10.94	
39.24/10.94	(13)
39.24/10.94	YES
39.24/10.94	
39.24/10.94	----------------------------------------
39.24/10.94	
39.24/10.94	(14)
39.24/10.94	Obligation:
39.24/10.94	SCC
39.24/10.94	----------------------------------------
39.24/10.94	
39.24/10.94	(15) SCC2IRS (SOUND)
39.24/10.94	Transformed LLVM symbolic execution graph SCC into a rewrite problem. Log: 
39.24/10.94	Generated rules. Obtained 21 rulesP rules:
39.24/10.94	f_336(v585, v586, v587, v588, v589, v590, v591, v592, 1, v596, v594, v595, v597, v598, v599, v600, v601, v602, v603, v604, 0, 3, 4) -> f_338(v585, v586, v587, v588, v589, v590, v591, v592, 1, v596, v594, v595, v597, v598, v599, v600, v601, v602, v603, v604, 0, 3, 4) :|: 0 <= v596 && 1 <= v594 && 1 <= v591
39.24/10.94	f_338(v585, v586, v587, v588, v589, v590, v591, v592, 1, v596, v594, v595, v597, v598, v599, v600, v601, v602, v603, v604, 0, 3, 4) -> f_341(v585, v586, v587, v588, v589, v590, v591, v592, 1, v596, v594, v595, v597, v598, v599, v600, v601, v602, v603, v604, 0, 3, 4) :|: 0 = 0
39.24/10.94	f_341(v585, v586, v587, v588, v589, v590, v591, v592, 1, v596, v594, v595, v597, v598, v599, v600, v601, v602, v603, v604, 0, 3, 4) -> f_344(v585, v586, v587, v588, v589, v590, v591, v592, 1, v596, v594, v595, v597, v598, v599, v600, v601, v602, v603, v604, 0, 3, 4) :|: 0 = 0
39.24/10.94	f_344(v585, v586, v587, v588, v589, v590, v591, v592, 1, v596, v594, v595, v597, v598, v599, v600, v601, v602, v603, v604, 0, 3, 4) -> f_347(v585, v586, v587, v588, v589, v590, v591, v592, 1, v596, v594, v595, v597, v598, v599, v600, v601, v602, v603, v604, 0, 3, 4) :|: TRUE
39.24/10.94	f_347(v585, v586, v587, v588, v589, v590, v591, v592, 1, v596, v594, v595, v597, v598, v599, v600, v601, v602, v603, v604, 0, 3, 4) -> f_350(v585, v586, v587, v588, v589, v590, v591, v592, 1, v596, v595, v594, v597, v598, v599, v600, v601, v602, v603, v604, 0, 3, 4) :|: 0 = 0
39.24/10.94	f_350(v585, v586, v587, v588, v589, v590, v591, v592, 1, v596, v595, v594, v597, v598, v599, v600, v601, v602, v603, v604, 0, 3, 4) -> f_354(v585, v586, v587, v588, v589, v590, v591, v592, 1, v596, v595, v594, v597, v598, v599, v600, v601, v602, v603, v604, 0, 3, 4) :|: 0 = 0
39.24/10.94	f_354(v585, v586, v587, v588, v589, v590, v591, v592, 1, v596, v595, v594, v597, v598, v599, v600, v601, v602, v603, v604, 0, 3, 4) -> f_358(v585, v586, v587, v588, v589, v590, v591, v592, 1, v596, v661, v594, v597, v598, v599, v600, v601, v602, v603, v604, 0, 3, 4) :|: v661 = v596 + v590
39.24/10.94	f_358(v585, v586, v587, v588, v589, v590, v591, v592, 1, v596, v661, v594, v597, v598, v599, v600, v601, v602, v603, v604, 0, 3, 4) -> f_362(v585, v586, v587, v588, v589, v590, v591, v592, 1, v596, v661, v594, v597, v598, v599, v600, v601, v602, v603, v604, 0, 3, 4) :|: 0 = 0
39.24/10.94	f_362(v585, v586, v587, v588, v589, v590, v591, v592, 1, v596, v661, v594, v597, v598, v599, v600, v601, v602, v603, v604, 0, 3, 4) -> f_366(v585, v586, v587, v588, v589, v590, v591, v592, 1, v596, v661, v597, v598, v599, v600, v601, v602, v603, v604, 0, 3, 4) :|: v596 + v590 = v661
39.24/10.94	f_366(v585, v586, v587, v588, v589, v590, v591, v592, 1, v596, v661, v597, v598, v599, v600, v601, v602, v603, v604, 0, 3, 4) -> f_371(v585, v586, v587, v588, v589, v590, v591, v592, 1, v596, v661, v798, v597, v598, v599, v600, v601, v602, v603, v604, 0, 3, 4) :|: 1 + v798 = v596 && 0 <= 1 + v798
39.24/10.94	f_371(v585, v586, v587, v588, v589, v590, v591, v592, 1, v596, v661, v798, v597, v598, v599, v600, v601, v602, v603, v604, 0, 3, 4) -> f_374(v585, v586, v587, v588, v589, v590, v591, v592, 1, v596, v661, v798, v597, v598, v599, v600, v601, v602, v603, v604, 0, 3, 4) :|: TRUE
39.24/10.94	f_374(v585, v586, v587, v588, v589, v590, v591, v592, 1, v596, v661, v798, v597, v598, v599, v600, v601, v602, v603, v604, 0, 3, 4) -> f_377(v585, v586, v587, v588, v589, v590, v591, v592, 1, v596, v661, v798, v599, v598, v597, v600, v601, v602, v603, v604, 0, 3, 4) :|: 0 = 0
39.24/10.94	f_377(v585, v586, v587, v588, v589, v590, v591, v592, 1, v596, v661, v798, v599, v598, v597, v600, v601, v602, v603, v604, 0, 3, 4) -> f_380(v585, v586, v587, v588, v589, v590, v591, v592, 1, v596, v661, v798, v599, v598, v597, v600, v601, v602, v603, v604, 0, 3, 4) :|: 0 = 0
39.24/10.94	f_380(v585, v586, v587, v588, v589, v590, v591, v592, 1, v596, v661, v798, v599, v598, v597, v600, v601, v602, v603, v604, 0, 3, 4) -> f_383(v585, v586, v587, v588, v589, v590, v591, v592, 1, v596, v661, v798, v599, v808, v597, v600, v601, v602, v603, v604, 0, 3, 4) :|: v808 = v599 + v590
39.24/10.94	f_383(v585, v586, v587, v588, v589, v590, v591, v592, 1, v596, v661, v798, v599, v808, v597, v600, v601, v602, v603, v604, 0, 3, 4) -> f_387(v585, v586, v587, v588, v589, v590, v591, v592, 1, v596, v661, v798, v599, v808, v597, v600, v601, v602, v603, v604, 0, 3, 4) :|: 0 = 0
39.24/10.94	f_387(v585, v586, v587, v588, v589, v590, v591, v592, 1, v596, v661, v798, v599, v808, v597, v600, v601, v602, v603, v604, 0, 3, 4) -> f_391(v585, v586, v587, v588, v589, v590, v591, v592, 1, v596, v661, v798, v599, v808, v600, v601, v602, v603, v604, 0, 3, 4) :|: v599 + v590 = v808
39.24/10.94	f_391(v585, v586, v587, v588, v589, v590, v591, v592, 1, v596, v661, v798, v599, v808, v600, v601, v602, v603, v604, 0, 3, 4) -> f_395(v585, v586, v587, v588, v589, v590, v591, v592, 1, v596, v661, v798, v599, v808, v876, v600, v601, v602, v603, v604, 0, 3, 4) :|: 1 + v876 = v599
39.24/10.94	f_395(v585, v586, v587, v588, v589, v590, v591, v592, 1, v596, v661, v798, v599, v808, v876, v600, v601, v602, v603, v604, 0, 3, 4) -> f_399(v585, v586, v587, v588, v589, v590, v591, v592, 1, v596, v661, v798, v599, v808, v876, v600, v601, v602, v603, v604, 0, 3, 4) :|: TRUE
39.24/10.94	f_399(v585, v586, v587, v588, v589, v590, v591, v592, 1, v596, v661, v798, v599, v808, v876, v600, v601, v602, v603, v604, 0, 3, 4) -> f_403(v585, v586, v587, v588, v589, v590, v591, v592, 1, v596, v661, v798, v599, v808, v876, v600, v601, v602, v603, v604, 0, 3, 4) :|: TRUE
39.24/10.94	f_403(v585, v586, v587, v588, v589, v590, v591, v592, 1, v596, v661, v798, v599, v808, v876, v600, v601, v602, v603, v604, 0, 3, 4) -> f_334(v585, v586, v587, v588, v589, v590, v591, v592, 1, v596, v661, v798, v599, v808, v876, v600, v601, v602, v603, v604, 0, 3, 4) :|: TRUE
39.24/10.94	f_334(v585, v586, v587, v588, v589, v590, v591, v592, 1, v594, v595, v596, v597, v598, v599, v600, v601, v602, v603, v604, 0, 3, 4) -> f_336(v585, v586, v587, v588, v589, v590, v591, v592, 1, v596, v594, v595, v597, v598, v599, v600, v601, v602, v603, v604, 0, 3, 4) :|: 0 = 0
39.24/10.94	Combined rules. Obtained 1 rulesP rules:
39.24/10.94	f_336(v585:0, v586:0, v587:0, v588:0, v589:0, v590:0, v591:0, v592:0, 1, 1 + v798:0, v594:0, v595:0, v597:0, v598:0, 1 + v876:0, v600:0, v601:0, v602:0, v603:0, v604:0, 0, 3, 4) -> f_336(v585:0, v586:0, v587:0, v588:0, v589:0, v590:0, v591:0, v592:0, 1, v798:0, 1 + v798:0, 1 + v798:0 + v590:0, 1 + v876:0, 1 + v876:0 + v590:0, v876:0, v600:0, v601:0, v602:0, v603:0, v604:0, 0, 3, 4) :|: v594:0 > 0 && v798:0 > -2 && v591:0 > 0
39.24/10.94	Filtered unneeded arguments:
39.24/10.94	   f_336(x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, x16, x17, x18, x19, x20, x21, x22, x23) -> f_336(x7, x10, x11, x15)
39.24/10.94	Removed division, modulo operations, cleaned up constraints. Obtained 1 rules.P rules:
39.24/10.94	f_336(v591:0, sum~cons_1~v798:0, v594:0, sum~cons_1~v876:0) -> f_336(v591:0, v798:0, 1 + v798:0, v876:0) :|: v798:0 > -2 && v591:0 > 0 && v594:0 > 0 && sum~cons_1~v798:0 = 1 + v798:0 && sum~cons_1~v876:0 = 1 + v876:0
39.24/10.94	
39.24/10.94	----------------------------------------
39.24/10.94	
39.24/10.94	(16)
39.24/10.94	Obligation:
39.24/10.94	Rules:
39.24/10.94	f_336(v591:0, sum~cons_1~v798:0, v594:0, sum~cons_1~v876:0) -> f_336(v591:0, v798:0, 1 + v798:0, v876:0) :|: v798:0 > -2 && v591:0 > 0 && v594:0 > 0 && sum~cons_1~v798:0 = 1 + v798:0 && sum~cons_1~v876:0 = 1 + v876:0
39.24/10.94	
39.24/10.94	----------------------------------------
39.24/10.94	
39.24/10.94	(17) IRS2T2 (EQUIVALENT)
39.24/10.94	Transformed input IRS into an integer transition system.Used the following mapping from defined symbols to location IDs:
39.24/10.94	
39.24/10.94	   (f_336_4,1)
39.24/10.94	
39.24/10.94	----------------------------------------
39.24/10.94	
39.24/10.94	(18)
39.24/10.94	Obligation:
39.24/10.94	START: 0;
39.24/10.94	
39.24/10.94	FROM: 0;
39.24/10.94	TO: 1;
39.24/10.94	
39.24/10.94	FROM: 1;
39.24/10.94	oldX0 := x0;
39.24/10.94	oldX1 := x1;
39.24/10.94	oldX2 := x2;
39.24/10.94	oldX3 := x3;
39.24/10.94	oldX4 := oldX1 - 1;
39.24/10.94	oldX5 := oldX3 - 1;
39.24/10.94	assume(oldX4 > -2 && oldX0 > 0 && oldX2 > 0 && oldX1 = 1 + oldX4 && oldX3 = 1 + oldX5);
39.24/10.94	x0 := oldX0;
39.24/10.94	x1 := oldX1 - 1;
39.24/10.94	x2 := 1 + oldX4;
39.24/10.94	x3 := oldX3 - 1;
39.24/10.94	TO: 1;
39.24/10.94	
39.24/10.94	
39.24/10.94	----------------------------------------
39.24/10.94	
39.24/10.94	(19) T2 (EQUIVALENT)
39.24/10.94	Initially, performed program simplifications using lexicographic rank functions:
39.24/10.94	 * Removed transitions 1, 3, 4 using the following rank functions:
39.24/10.94	    - Rank function 1:
39.24/10.94	      RF for loc. 5: 1+2*x1
39.24/10.94	      RF for loc. 6: 2*x1
39.24/10.94	      Bound for (chained) transitions 3: 0
39.24/10.94	      Bound for (chained) transitions 4: 0
39.24/10.94	    - Rank function 2:
39.24/10.94	      RF for loc. 5: 0
39.24/10.94	      RF for loc. 6: -1
39.24/10.94	      Bound for (chained) transitions 1: 0
39.24/10.94	
39.24/10.94	----------------------------------------
39.24/10.94	
39.24/10.94	(20)
39.24/10.94	YES
39.32/11.03	EOF