MAYBE proof of prog.inttrs # AProVE Commit ID: 48fb2092695e11cc9f56e44b17a92a5f88ffb256 marcel 20180622 unpublished dirty Termination of the given IRSwT could not be shown: (0) IRSwT (1) IRSFormatTransformerProof [EQUIVALENT, 0 ms] (2) IRSwT (3) IRSwTTerminationDigraphProof [EQUIVALENT, 744 ms] (4) IRSwT (5) IntTRSCompressionProof [EQUIVALENT, 0 ms] (6) IRSwT (7) IntTRSUnneededArgumentFilterProof [EQUIVALENT, 0 ms] (8) IRSwT (9) TempFilterProof [SOUND, 62 ms] (10) IRSwT (11) IRSwTTerminationDigraphProof [EQUIVALENT, 0 ms] (12) IRSwT (13) IntTRSCompressionProof [EQUIVALENT, 0 ms] (14) IRSwT ---------------------------------------- (0) Obligation: Rules: l0(Result_4HAT0, __disjvr_0HAT0, __disjvr_1HAT0, tmp_6HAT0, x_5HAT0) -> l1(Result_4HATpost, __disjvr_0HATpost, __disjvr_1HATpost, tmp_6HATpost, x_5HATpost) :|: x_5HAT0 = x_5HATpost && tmp_6HAT0 = tmp_6HATpost && __disjvr_1HAT0 = __disjvr_1HATpost && __disjvr_0HAT0 = __disjvr_0HATpost && Result_4HAT0 = Result_4HATpost l1(x, x1, x2, x3, x4) -> l2(x5, x6, x7, x8, x9) :|: x4 = x9 && x2 = x7 && x1 = x6 && x5 = x5 && x4 <= 0 && 0 <= x8 && x8 <= 0 && x8 = x8 l1(x10, x11, x12, x13, x14) -> l3(x15, x16, x17, x18, x19) :|: x14 = x19 && x12 = x17 && x11 = x16 && x10 = x15 && 0 <= -1 + x14 && 0 <= x18 && x18 <= 0 && x18 = x18 l3(x20, x21, x22, x23, x24) -> l1(x25, x26, x27, x28, x29) :|: x24 = x29 && x23 = x28 && x22 = x27 && x21 = x26 && x20 = x25 l1(x30, x31, x32, x33, x34) -> l4(x35, x36, x37, x38, x39) :|: x34 = x39 && x32 = x37 && x31 = x36 && x30 = x35 && x38 = x38 l4(x40, x41, x42, x43, x44) -> l5(x45, x46, x47, x48, x49) :|: x44 = x49 && x43 = x48 && x42 = x47 && x41 = x46 && x40 = x45 && x46 = x41 l5(x50, x51, x52, x53, x54) -> l2(x55, x56, x57, x58, x59) :|: x53 = x58 && x52 = x57 && x51 = x56 && x55 = x55 && x59 <= 0 && x59 = -1 + x54 l1(x60, x61, x62, x63, x64) -> l7(x65, x66, x67, x68, x69) :|: x64 = x69 && x62 = x67 && x61 = x66 && x60 = x65 && x68 = x68 l7(x70, x71, x72, x73, x74) -> l8(x75, x76, x77, x78, x79) :|: x74 = x79 && x73 = x78 && x72 = x77 && x71 = x76 && x70 = x75 && x77 = x72 l8(x80, x81, x82, x83, x84) -> l6(x85, x86, x87, x88, x89) :|: x83 = x88 && x82 = x87 && x81 = x86 && x80 = x85 && 0 <= -1 + x89 && x89 = -1 + x84 l6(x90, x91, x92, x93, x94) -> l1(x95, x96, x97, x98, x99) :|: x94 = x99 && x93 = x98 && x92 = x97 && x91 = x96 && x90 = x95 l9(x100, x101, x102, x103, x104) -> l0(x105, x106, x107, x108, x109) :|: x104 = x109 && x103 = x108 && x102 = x107 && x101 = x106 && x100 = x105 Start term: l9(Result_4HAT0, __disjvr_0HAT0, __disjvr_1HAT0, tmp_6HAT0, x_5HAT0) ---------------------------------------- (1) IRSFormatTransformerProof (EQUIVALENT) Reformatted IRS to match normalized format (transformed away non-linear left-hand sides, !=, / and %). ---------------------------------------- (2) Obligation: Rules: l0(Result_4HAT0, __disjvr_0HAT0, __disjvr_1HAT0, tmp_6HAT0, x_5HAT0) -> l1(Result_4HATpost, __disjvr_0HATpost, __disjvr_1HATpost, tmp_6HATpost, x_5HATpost) :|: x_5HAT0 = x_5HATpost && tmp_6HAT0 = tmp_6HATpost && __disjvr_1HAT0 = __disjvr_1HATpost && __disjvr_0HAT0 = __disjvr_0HATpost && Result_4HAT0 = Result_4HATpost l1(x, x1, x2, x3, x4) -> l2(x5, x6, x7, x8, x9) :|: x4 = x9 && x2 = x7 && x1 = x6 && x5 = x5 && x4 <= 0 && 0 <= x8 && x8 <= 0 && x8 = x8 l1(x10, x11, x12, x13, x14) -> l3(x15, x16, x17, x18, x19) :|: x14 = x19 && x12 = x17 && x11 = x16 && x10 = x15 && 0 <= -1 + x14 && 0 <= x18 && x18 <= 0 && x18 = x18 l3(x20, x21, x22, x23, x24) -> l1(x25, x26, x27, x28, x29) :|: x24 = x29 && x23 = x28 && x22 = x27 && x21 = x26 && x20 = x25 l1(x30, x31, x32, x33, x34) -> l4(x35, x36, x37, x38, x39) :|: x34 = x39 && x32 = x37 && x31 = x36 && x30 = x35 && x38 = x38 l4(x40, x41, x42, x43, x44) -> l5(x45, x46, x47, x48, x49) :|: x44 = x49 && x43 = x48 && x42 = x47 && x41 = x46 && x40 = x45 && x46 = x41 l5(x50, x51, x52, x53, x54) -> l2(x55, x56, x57, x58, x59) :|: x53 = x58 && x52 = x57 && x51 = x56 && x55 = x55 && x59 <= 0 && x59 = -1 + x54 l1(x60, x61, x62, x63, x64) -> l7(x65, x66, x67, x68, x69) :|: x64 = x69 && x62 = x67 && x61 = x66 && x60 = x65 && x68 = x68 l7(x70, x71, x72, x73, x74) -> l8(x75, x76, x77, x78, x79) :|: x74 = x79 && x73 = x78 && x72 = x77 && x71 = x76 && x70 = x75 && x77 = x72 l8(x80, x81, x82, x83, x84) -> l6(x85, x86, x87, x88, x89) :|: x83 = x88 && x82 = x87 && x81 = x86 && x80 = x85 && 0 <= -1 + x89 && x89 = -1 + x84 l6(x90, x91, x92, x93, x94) -> l1(x95, x96, x97, x98, x99) :|: x94 = x99 && x93 = x98 && x92 = x97 && x91 = x96 && x90 = x95 l9(x100, x101, x102, x103, x104) -> l0(x105, x106, x107, x108, x109) :|: x104 = x109 && x103 = x108 && x102 = x107 && x101 = x106 && x100 = x105 Start term: l9(Result_4HAT0, __disjvr_0HAT0, __disjvr_1HAT0, tmp_6HAT0, x_5HAT0) ---------------------------------------- (3) IRSwTTerminationDigraphProof (EQUIVALENT) Constructed termination digraph! Nodes: (1) l0(Result_4HAT0, __disjvr_0HAT0, __disjvr_1HAT0, tmp_6HAT0, x_5HAT0) -> l1(Result_4HATpost, __disjvr_0HATpost, __disjvr_1HATpost, tmp_6HATpost, x_5HATpost) :|: x_5HAT0 = x_5HATpost && tmp_6HAT0 = tmp_6HATpost && __disjvr_1HAT0 = __disjvr_1HATpost && __disjvr_0HAT0 = __disjvr_0HATpost && Result_4HAT0 = Result_4HATpost (2) l1(x, x1, x2, x3, x4) -> l2(x5, x6, x7, x8, x9) :|: x4 = x9 && x2 = x7 && x1 = x6 && x5 = x5 && x4 <= 0 && 0 <= x8 && x8 <= 0 && x8 = x8 (3) l1(x10, x11, x12, x13, x14) -> l3(x15, x16, x17, x18, x19) :|: x14 = x19 && x12 = x17 && x11 = x16 && x10 = x15 && 0 <= -1 + x14 && 0 <= x18 && x18 <= 0 && x18 = x18 (4) l3(x20, x21, x22, x23, x24) -> l1(x25, x26, x27, x28, x29) :|: x24 = x29 && x23 = x28 && x22 = x27 && x21 = x26 && x20 = x25 (5) l1(x30, x31, x32, x33, x34) -> l4(x35, x36, x37, x38, x39) :|: x34 = x39 && x32 = x37 && x31 = x36 && x30 = x35 && x38 = x38 (6) l4(x40, x41, x42, x43, x44) -> l5(x45, x46, x47, x48, x49) :|: x44 = x49 && x43 = x48 && x42 = x47 && x41 = x46 && x40 = x45 && x46 = x41 (7) l5(x50, x51, x52, x53, x54) -> l2(x55, x56, x57, x58, x59) :|: x53 = x58 && x52 = x57 && x51 = x56 && x55 = x55 && x59 <= 0 && x59 = -1 + x54 (8) l1(x60, x61, x62, x63, x64) -> l7(x65, x66, x67, x68, x69) :|: x64 = x69 && x62 = x67 && x61 = x66 && x60 = x65 && x68 = x68 (9) l7(x70, x71, x72, x73, x74) -> l8(x75, x76, x77, x78, x79) :|: x74 = x79 && x73 = x78 && x72 = x77 && x71 = x76 && x70 = x75 && x77 = x72 (10) l8(x80, x81, x82, x83, x84) -> l6(x85, x86, x87, x88, x89) :|: x83 = x88 && x82 = x87 && x81 = x86 && x80 = x85 && 0 <= -1 + x89 && x89 = -1 + x84 (11) l6(x90, x91, x92, x93, x94) -> l1(x95, x96, x97, x98, x99) :|: x94 = x99 && x93 = x98 && x92 = x97 && x91 = x96 && x90 = x95 (12) l9(x100, x101, x102, x103, x104) -> l0(x105, x106, x107, x108, x109) :|: x104 = x109 && x103 = x108 && x102 = x107 && x101 = x106 && x100 = x105 Arcs: (1) -> (2), (3), (5), (8) (3) -> (4) (4) -> (2), (3), (5), (8) (5) -> (6) (6) -> (7) (8) -> (9) (9) -> (10) (10) -> (11) (11) -> (2), (3), (5), (8) (12) -> (1) This digraph is fully evaluated! ---------------------------------------- (4) Obligation: Termination digraph: Nodes: (1) l1(x10, x11, x12, x13, x14) -> l3(x15, x16, x17, x18, x19) :|: x14 = x19 && x12 = x17 && x11 = x16 && x10 = x15 && 0 <= -1 + x14 && 0 <= x18 && x18 <= 0 && x18 = x18 (2) l6(x90, x91, x92, x93, x94) -> l1(x95, x96, x97, x98, x99) :|: x94 = x99 && x93 = x98 && x92 = x97 && x91 = x96 && x90 = x95 (3) l8(x80, x81, x82, x83, x84) -> l6(x85, x86, x87, x88, x89) :|: x83 = x88 && x82 = x87 && x81 = x86 && x80 = x85 && 0 <= -1 + x89 && x89 = -1 + x84 (4) l7(x70, x71, x72, x73, x74) -> l8(x75, x76, x77, x78, x79) :|: x74 = x79 && x73 = x78 && x72 = x77 && x71 = x76 && x70 = x75 && x77 = x72 (5) l1(x60, x61, x62, x63, x64) -> l7(x65, x66, x67, x68, x69) :|: x64 = x69 && x62 = x67 && x61 = x66 && x60 = x65 && x68 = x68 (6) l3(x20, x21, x22, x23, x24) -> l1(x25, x26, x27, x28, x29) :|: x24 = x29 && x23 = x28 && x22 = x27 && x21 = x26 && x20 = x25 Arcs: (1) -> (6) (2) -> (1), (5) (3) -> (2) (4) -> (3) (5) -> (4) (6) -> (1), (5) This digraph is fully evaluated! ---------------------------------------- (5) IntTRSCompressionProof (EQUIVALENT) Compressed rules. ---------------------------------------- (6) Obligation: Rules: l1(x10:0, x11:0, x12:0, x13:0, x14:0) -> l1(x10:0, x11:0, x12:0, x18:0, x14:0) :|: x18:0 > -1 && x14:0 > 0 && x18:0 < 1 l1(x60:0, x61:0, x62:0, x63:0, x64:0) -> l1(x60:0, x61:0, x62:0, x68:0, -1 + x64:0) :|: x64:0 > 1 ---------------------------------------- (7) IntTRSUnneededArgumentFilterProof (EQUIVALENT) Some arguments are removed because they cannot influence termination. We removed arguments according to the following replacements: l1(x1, x2, x3, x4, x5) -> l1(x5) ---------------------------------------- (8) Obligation: Rules: l1(x14:0) -> l1(x14:0) :|: x18:0 > -1 && x14:0 > 0 && x18:0 < 1 l1(x64:0) -> l1(-1 + x64:0) :|: x64:0 > 1 ---------------------------------------- (9) TempFilterProof (SOUND) Used the following sort dictionary for filtering: l1(INTEGER) Replaced non-predefined constructor symbols by 0.The following proof was generated: # AProVE Commit ID: 48fb2092695e11cc9f56e44b17a92a5f88ffb256 marcel 20180622 unpublished dirty Termination of the given IntTRS could not be shown: - IntTRS - PolynomialOrderProcessor Rules: l1(x14:0) -> l1(x14:0) :|: x18:0 > -1 && x14:0 > 0 && x18:0 < 1 l1(x64:0) -> l1(c) :|: c = -1 + x64:0 && x64:0 > 1 Found the following polynomial interpretation: [l1(x)] = -2 + x The following rules are decreasing: l1(x64:0) -> l1(c) :|: c = -1 + x64:0 && x64:0 > 1 The following rules are bounded: l1(x64:0) -> l1(c) :|: c = -1 + x64:0 && x64:0 > 1 - IntTRS - PolynomialOrderProcessor - IntTRS Rules: l1(x14:0) -> l1(x14:0) :|: x18:0 > -1 && x14:0 > 0 && x18:0 < 1 ---------------------------------------- (10) Obligation: Rules: l1(x14:0) -> l1(x14:0) :|: x18:0 > -1 && x14:0 > 0 && x18:0 < 1 ---------------------------------------- (11) IRSwTTerminationDigraphProof (EQUIVALENT) Constructed termination digraph! Nodes: (1) l1(x14:0) -> l1(x14:0) :|: x18:0 > -1 && x14:0 > 0 && x18:0 < 1 Arcs: (1) -> (1) This digraph is fully evaluated! ---------------------------------------- (12) Obligation: Termination digraph: Nodes: (1) l1(x14:0) -> l1(x14:0) :|: x18:0 > -1 && x14:0 > 0 && x18:0 < 1 Arcs: (1) -> (1) This digraph is fully evaluated! ---------------------------------------- (13) IntTRSCompressionProof (EQUIVALENT) Compressed rules. ---------------------------------------- (14) Obligation: Rules: l1(x14:0:0) -> l1(x14:0:0) :|: x18:0:0 > -1 && x14:0:0 > 0 && x18:0:0 < 1