NO

### Pre-processing the ITS problem ###

Initial linear ITS problem
   Start location: l8
      0: l0 -> l1 : Dc_6^0'=Dc_6^post_1, InterfaceType_5^0'=InterfaceType_5^post_1, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_1, Result_4^0'=Result_4^post_1, __cil_tmp2_11^0'=__cil_tmp2_11^post_1, __const_256^0'=__const_256^post_1, __disjvr_0^0'=__disjvr_0^post_1, __retres1_10^0'=__retres1_10^post_1, cnt_27^0'=cnt_27^post_1, cnt_32^0'=cnt_32^post_1, ct_15^0'=ct_15^post_1, ct_49^0'=ct_49^post_1, fdoExtension_7^0'=fdoExtension_7^post_1, lt_12^0'=lt_12^post_1, lt_13^0'=lt_13^post_1, lt_14^0'=lt_14^post_1, lt_16^0'=lt_16^post_1, lt_17^0'=lt_17^post_1, lt_18^0'=lt_18^post_1, ntStatus_8^0'=ntStatus_8^post_1, [ MaximumInterfaceType_9^post_1==MaximumInterfaceType_9^post_1 && ntStatus_8^post_1==ntStatus_8^post_1 && fdoExtension_7^post_1==fdoExtension_7^post_1 && Dc_6^post_1==Dc_6^post_1 && InterfaceType_5^post_1==InterfaceType_5^post_1 && Result_4^0==Result_4^post_1 && __cil_tmp2_11^0==__cil_tmp2_11^post_1 && __const_256^0==__const_256^post_1 && __disjvr_0^0==__disjvr_0^post_1 && __retres1_10^0==__retres1_10^post_1 && cnt_27^0==cnt_27^post_1 && cnt_32^0==cnt_32^post_1 && ct_15^0==ct_15^post_1 && ct_49^0==ct_49^post_1 && lt_12^0==lt_12^post_1 && lt_13^0==lt_13^post_1 && lt_14^0==lt_14^post_1 && lt_16^0==lt_16^post_1 && lt_17^0==lt_17^post_1 && lt_18^0==lt_18^post_1 ], cost: 1
      1: l1 -> l3 : Dc_6^0'=Dc_6^post_2, InterfaceType_5^0'=InterfaceType_5^post_2, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_2, Result_4^0'=Result_4^post_2, __cil_tmp2_11^0'=__cil_tmp2_11^post_2, __const_256^0'=__const_256^post_2, __disjvr_0^0'=__disjvr_0^post_2, __retres1_10^0'=__retres1_10^post_2, cnt_27^0'=cnt_27^post_2, cnt_32^0'=cnt_32^post_2, ct_15^0'=ct_15^post_2, ct_49^0'=ct_49^post_2, fdoExtension_7^0'=fdoExtension_7^post_2, lt_12^0'=lt_12^post_2, lt_13^0'=lt_13^post_2, lt_14^0'=lt_14^post_2, lt_16^0'=lt_16^post_2, lt_17^0'=lt_17^post_2, lt_18^0'=lt_18^post_2, ntStatus_8^0'=ntStatus_8^post_2, [ lt_17^1_1==cnt_27^0 && lt_18^1_1==cnt_32^0 && 0<=-1-lt_17^1_1+lt_18^1_1 && lt_17^post_2==lt_17^post_2 && lt_18^post_2==lt_18^post_2 && lt_16^1_1==cnt_27^0 && lt_16^post_2==lt_16^post_2 && ct_15^1_1==ct_15^1_1 && ct_15^post_2==ct_15^post_2 && lt_14^1_1==ct_49^0 && 0<=-1+lt_14^1_1 && lt_14^post_2==lt_14^post_2 && lt_13^post_2==ct_49^0 && Dc_6^0==Dc_6^post_2 && InterfaceType_5^0==InterfaceType_5^post_2 && MaximumInterfaceType_9^0==MaximumInterfaceType_9^post_2 && Result_4^0==Result_4^post_2 && __cil_tmp2_11^0==__cil_tmp2_11^post_2 && __const_256^0==__const_256^post_2 && __disjvr_0^0==__disjvr_0^post_2 && __retres1_10^0==__retres1_10^post_2 && cnt_27^0==cnt_27^post_2 && cnt_32^0==cnt_32^post_2 && ct_49^0==ct_49^post_2 && fdoExtension_7^0==fdoExtension_7^post_2 && lt_12^0==lt_12^post_2 && ntStatus_8^0==ntStatus_8^post_2 ], cost: 1
      4: l1 -> l5 : Dc_6^0'=Dc_6^post_5, InterfaceType_5^0'=InterfaceType_5^post_5, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_5, Result_4^0'=Result_4^post_5, __cil_tmp2_11^0'=__cil_tmp2_11^post_5, __const_256^0'=__const_256^post_5, __disjvr_0^0'=__disjvr_0^post_5, __retres1_10^0'=__retres1_10^post_5, cnt_27^0'=cnt_27^post_5, cnt_32^0'=cnt_32^post_5, ct_15^0'=ct_15^post_5, ct_49^0'=ct_49^post_5, fdoExtension_7^0'=fdoExtension_7^post_5, lt_12^0'=lt_12^post_5, lt_13^0'=lt_13^post_5, lt_14^0'=lt_14^post_5, lt_16^0'=lt_16^post_5, lt_17^0'=lt_17^post_5, lt_18^0'=lt_18^post_5, ntStatus_8^0'=ntStatus_8^post_5, [ lt_17^1_2_1==cnt_27^0 && lt_18^1_2_1==cnt_32^0 && 0<=-1-lt_17^1_2_1+lt_18^1_2_1 && lt_17^post_5==lt_17^post_5 && lt_18^post_5==lt_18^post_5 && lt_16^1_2_1==cnt_27^0 && lt_16^post_5==lt_16^post_5 && ct_15^1_2==ct_15^1_2 && ct_15^post_5==ct_15^post_5 && lt_14^1_2_1==ct_49^0 && lt_14^1_2_1<=0 && lt_14^post_5==lt_14^post_5 && Dc_6^0==Dc_6^post_5 && InterfaceType_5^0==InterfaceType_5^post_5 && MaximumInterfaceType_9^0==MaximumInterfaceType_9^post_5 && Result_4^0==Result_4^post_5 && __cil_tmp2_11^0==__cil_tmp2_11^post_5 && __const_256^0==__const_256^post_5 && __disjvr_0^0==__disjvr_0^post_5 && __retres1_10^0==__retres1_10^post_5 && cnt_27^0==cnt_27^post_5 && cnt_32^0==cnt_32^post_5 && ct_49^0==ct_49^post_5 && fdoExtension_7^0==fdoExtension_7^post_5 && lt_12^0==lt_12^post_5 && lt_13^0==lt_13^post_5 && ntStatus_8^0==ntStatus_8^post_5 ], cost: 1
      6: l1 -> l6 : Dc_6^0'=Dc_6^post_7, InterfaceType_5^0'=InterfaceType_5^post_7, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_7, Result_4^0'=Result_4^post_7, __cil_tmp2_11^0'=__cil_tmp2_11^post_7, __const_256^0'=__const_256^post_7, __disjvr_0^0'=__disjvr_0^post_7, __retres1_10^0'=__retres1_10^post_7, cnt_27^0'=cnt_27^post_7, cnt_32^0'=cnt_32^post_7, ct_15^0'=ct_15^post_7, ct_49^0'=ct_49^post_7, fdoExtension_7^0'=fdoExtension_7^post_7, lt_12^0'=lt_12^post_7, lt_13^0'=lt_13^post_7, lt_14^0'=lt_14^post_7, lt_16^0'=lt_16^post_7, lt_17^0'=lt_17^post_7, lt_18^0'=lt_18^post_7, ntStatus_8^0'=ntStatus_8^post_7, [ lt_17^1_3_1==cnt_27^0 && lt_18^1_3_1==cnt_32^0 && 0<=-1-lt_17^1_3_1+lt_18^1_3_1 && lt_17^post_7==lt_17^post_7 && lt_18^post_7==lt_18^post_7 && lt_16^1_3_1==cnt_27^0 && lt_16^post_7==lt_16^post_7 && ct_15^1_3==ct_15^1_3 && ct_15^post_7==ct_15^post_7 && lt_14^1_3_1==ct_49^0 && 0<=-1+lt_14^1_3_1 && lt_14^post_7==lt_14^post_7 && lt_13^1_1==ct_49^0 && lt_13^1_1<=__const_256^0 && __const_256^0<=lt_13^1_1 && lt_13^post_7==lt_13^post_7 && Dc_6^0==Dc_6^post_7 && InterfaceType_5^0==InterfaceType_5^post_7 && MaximumInterfaceType_9^0==MaximumInterfaceType_9^post_7 && Result_4^0==Result_4^post_7 && __cil_tmp2_11^0==__cil_tmp2_11^post_7 && __const_256^0==__const_256^post_7 && __disjvr_0^0==__disjvr_0^post_7 && __retres1_10^0==__retres1_10^post_7 && cnt_27^0==cnt_27^post_7 && cnt_32^0==cnt_32^post_7 && ct_49^0==ct_49^post_7 && fdoExtension_7^0==fdoExtension_7^post_7 && lt_12^0==lt_12^post_7 && ntStatus_8^0==ntStatus_8^post_7 ], cost: 1
      8: l1 -> l7 : Dc_6^0'=Dc_6^post_9, InterfaceType_5^0'=InterfaceType_5^post_9, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_9, Result_4^0'=Result_4^post_9, __cil_tmp2_11^0'=__cil_tmp2_11^post_9, __const_256^0'=__const_256^post_9, __disjvr_0^0'=__disjvr_0^post_9, __retres1_10^0'=__retres1_10^post_9, cnt_27^0'=cnt_27^post_9, cnt_32^0'=cnt_32^post_9, ct_15^0'=ct_15^post_9, ct_49^0'=ct_49^post_9, fdoExtension_7^0'=fdoExtension_7^post_9, lt_12^0'=lt_12^post_9, lt_13^0'=lt_13^post_9, lt_14^0'=lt_14^post_9, lt_16^0'=lt_16^post_9, lt_17^0'=lt_17^post_9, lt_18^0'=lt_18^post_9, ntStatus_8^0'=ntStatus_8^post_9, [ lt_17^1_3_2==cnt_27^0 && lt_18^1_4_1==cnt_32^0 && -lt_17^1_3_2+lt_18^1_4_1<=0 && lt_17^post_9==lt_17^post_9 && lt_18^post_9==lt_18^post_9 && __retres1_10^post_9==0 && __cil_tmp2_11^post_9==__retres1_10^post_9 && Result_4^post_9==__cil_tmp2_11^post_9 && Dc_6^0==Dc_6^post_9 && InterfaceType_5^0==InterfaceType_5^post_9 && MaximumInterfaceType_9^0==MaximumInterfaceType_9^post_9 && __const_256^0==__const_256^post_9 && __disjvr_0^0==__disjvr_0^post_9 && cnt_27^0==cnt_27^post_9 && cnt_32^0==cnt_32^post_9 && ct_15^0==ct_15^post_9 && ct_49^0==ct_49^post_9 && fdoExtension_7^0==fdoExtension_7^post_9 && lt_12^0==lt_12^post_9 && lt_13^0==lt_13^post_9 && lt_14^0==lt_14^post_9 && lt_16^0==lt_16^post_9 && ntStatus_8^0==ntStatus_8^post_9 ], cost: 1
      2: l3 -> l4 : Dc_6^0'=Dc_6^post_3, InterfaceType_5^0'=InterfaceType_5^post_3, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_3, Result_4^0'=Result_4^post_3, __cil_tmp2_11^0'=__cil_tmp2_11^post_3, __const_256^0'=__const_256^post_3, __disjvr_0^0'=__disjvr_0^post_3, __retres1_10^0'=__retres1_10^post_3, cnt_27^0'=cnt_27^post_3, cnt_32^0'=cnt_32^post_3, ct_15^0'=ct_15^post_3, ct_49^0'=ct_49^post_3, fdoExtension_7^0'=fdoExtension_7^post_3, lt_12^0'=lt_12^post_3, lt_13^0'=lt_13^post_3, lt_14^0'=lt_14^post_3, lt_16^0'=lt_16^post_3, lt_17^0'=lt_17^post_3, lt_18^0'=lt_18^post_3, ntStatus_8^0'=ntStatus_8^post_3, [ __disjvr_0^post_3==__disjvr_0^0 && Dc_6^0==Dc_6^post_3 && InterfaceType_5^0==InterfaceType_5^post_3 && MaximumInterfaceType_9^0==MaximumInterfaceType_9^post_3 && Result_4^0==Result_4^post_3 && __cil_tmp2_11^0==__cil_tmp2_11^post_3 && __const_256^0==__const_256^post_3 && __disjvr_0^0==__disjvr_0^post_3 && __retres1_10^0==__retres1_10^post_3 && cnt_27^0==cnt_27^post_3 && cnt_32^0==cnt_32^post_3 && ct_15^0==ct_15^post_3 && ct_49^0==ct_49^post_3 && fdoExtension_7^0==fdoExtension_7^post_3 && lt_12^0==lt_12^post_3 && lt_13^0==lt_13^post_3 && lt_14^0==lt_14^post_3 && lt_16^0==lt_16^post_3 && lt_17^0==lt_17^post_3 && lt_18^0==lt_18^post_3 && ntStatus_8^0==ntStatus_8^post_3 ], cost: 1
      3: l4 -> l2 : Dc_6^0'=Dc_6^post_4, InterfaceType_5^0'=InterfaceType_5^post_4, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_4, Result_4^0'=Result_4^post_4, __cil_tmp2_11^0'=__cil_tmp2_11^post_4, __const_256^0'=__const_256^post_4, __disjvr_0^0'=__disjvr_0^post_4, __retres1_10^0'=__retres1_10^post_4, cnt_27^0'=cnt_27^post_4, cnt_32^0'=cnt_32^post_4, ct_15^0'=ct_15^post_4, ct_49^0'=ct_49^post_4, fdoExtension_7^0'=fdoExtension_7^post_4, lt_12^0'=lt_12^post_4, lt_13^0'=lt_13^post_4, lt_14^0'=lt_14^post_4, lt_16^0'=lt_16^post_4, lt_17^0'=lt_17^post_4, lt_18^0'=lt_18^post_4, ntStatus_8^0'=ntStatus_8^post_4, [ lt_13^post_4==lt_13^post_4 && lt_12^1_1==ct_49^0 && __retres1_10^post_4==lt_12^1_1 && lt_12^post_4==lt_12^post_4 && __cil_tmp2_11^post_4==__retres1_10^post_4 && Result_4^post_4==__cil_tmp2_11^post_4 && Dc_6^0==Dc_6^post_4 && InterfaceType_5^0==InterfaceType_5^post_4 && MaximumInterfaceType_9^0==MaximumInterfaceType_9^post_4 && __const_256^0==__const_256^post_4 && __disjvr_0^0==__disjvr_0^post_4 && cnt_27^0==cnt_27^post_4 && cnt_32^0==cnt_32^post_4 && ct_15^0==ct_15^post_4 && ct_49^0==ct_49^post_4 && fdoExtension_7^0==fdoExtension_7^post_4 && lt_14^0==lt_14^post_4 && lt_16^0==lt_16^post_4 && lt_17^0==lt_17^post_4 && lt_18^0==lt_18^post_4 && ntStatus_8^0==ntStatus_8^post_4 ], cost: 1
      5: l5 -> l1 : Dc_6^0'=Dc_6^post_6, InterfaceType_5^0'=InterfaceType_5^post_6, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_6, Result_4^0'=Result_4^post_6, __cil_tmp2_11^0'=__cil_tmp2_11^post_6, __const_256^0'=__const_256^post_6, __disjvr_0^0'=__disjvr_0^post_6, __retres1_10^0'=__retres1_10^post_6, cnt_27^0'=cnt_27^post_6, cnt_32^0'=cnt_32^post_6, ct_15^0'=ct_15^post_6, ct_49^0'=ct_49^post_6, fdoExtension_7^0'=fdoExtension_7^post_6, lt_12^0'=lt_12^post_6, lt_13^0'=lt_13^post_6, lt_14^0'=lt_14^post_6, lt_16^0'=lt_16^post_6, lt_17^0'=lt_17^post_6, lt_18^0'=lt_18^post_6, ntStatus_8^0'=ntStatus_8^post_6, [ Dc_6^0==Dc_6^post_6 && InterfaceType_5^0==InterfaceType_5^post_6 && MaximumInterfaceType_9^0==MaximumInterfaceType_9^post_6 && Result_4^0==Result_4^post_6 && __cil_tmp2_11^0==__cil_tmp2_11^post_6 && __const_256^0==__const_256^post_6 && __disjvr_0^0==__disjvr_0^post_6 && __retres1_10^0==__retres1_10^post_6 && cnt_27^0==cnt_27^post_6 && cnt_32^0==cnt_32^post_6 && ct_15^0==ct_15^post_6 && ct_49^0==ct_49^post_6 && fdoExtension_7^0==fdoExtension_7^post_6 && lt_12^0==lt_12^post_6 && lt_13^0==lt_13^post_6 && lt_14^0==lt_14^post_6 && lt_16^0==lt_16^post_6 && lt_17^0==lt_17^post_6 && lt_18^0==lt_18^post_6 && ntStatus_8^0==ntStatus_8^post_6 ], cost: 1
      7: l6 -> l1 : Dc_6^0'=Dc_6^post_8, InterfaceType_5^0'=InterfaceType_5^post_8, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_8, Result_4^0'=Result_4^post_8, __cil_tmp2_11^0'=__cil_tmp2_11^post_8, __const_256^0'=__const_256^post_8, __disjvr_0^0'=__disjvr_0^post_8, __retres1_10^0'=__retres1_10^post_8, cnt_27^0'=cnt_27^post_8, cnt_32^0'=cnt_32^post_8, ct_15^0'=ct_15^post_8, ct_49^0'=ct_49^post_8, fdoExtension_7^0'=fdoExtension_7^post_8, lt_12^0'=lt_12^post_8, lt_13^0'=lt_13^post_8, lt_14^0'=lt_14^post_8, lt_16^0'=lt_16^post_8, lt_17^0'=lt_17^post_8, lt_18^0'=lt_18^post_8, ntStatus_8^0'=ntStatus_8^post_8, [ Dc_6^0==Dc_6^post_8 && InterfaceType_5^0==InterfaceType_5^post_8 && MaximumInterfaceType_9^0==MaximumInterfaceType_9^post_8 && Result_4^0==Result_4^post_8 && __cil_tmp2_11^0==__cil_tmp2_11^post_8 && __const_256^0==__const_256^post_8 && __disjvr_0^0==__disjvr_0^post_8 && __retres1_10^0==__retres1_10^post_8 && cnt_27^0==cnt_27^post_8 && cnt_32^0==cnt_32^post_8 && ct_15^0==ct_15^post_8 && ct_49^0==ct_49^post_8 && fdoExtension_7^0==fdoExtension_7^post_8 && lt_12^0==lt_12^post_8 && lt_13^0==lt_13^post_8 && lt_14^0==lt_14^post_8 && lt_16^0==lt_16^post_8 && lt_17^0==lt_17^post_8 && lt_18^0==lt_18^post_8 && ntStatus_8^0==ntStatus_8^post_8 ], cost: 1
      9: l8 -> l0 : Dc_6^0'=Dc_6^post_10, InterfaceType_5^0'=InterfaceType_5^post_10, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_10, Result_4^0'=Result_4^post_10, __cil_tmp2_11^0'=__cil_tmp2_11^post_10, __const_256^0'=__const_256^post_10, __disjvr_0^0'=__disjvr_0^post_10, __retres1_10^0'=__retres1_10^post_10, cnt_27^0'=cnt_27^post_10, cnt_32^0'=cnt_32^post_10, ct_15^0'=ct_15^post_10, ct_49^0'=ct_49^post_10, fdoExtension_7^0'=fdoExtension_7^post_10, lt_12^0'=lt_12^post_10, lt_13^0'=lt_13^post_10, lt_14^0'=lt_14^post_10, lt_16^0'=lt_16^post_10, lt_17^0'=lt_17^post_10, lt_18^0'=lt_18^post_10, ntStatus_8^0'=ntStatus_8^post_10, [ Dc_6^0==Dc_6^post_10 && InterfaceType_5^0==InterfaceType_5^post_10 && MaximumInterfaceType_9^0==MaximumInterfaceType_9^post_10 && Result_4^0==Result_4^post_10 && __cil_tmp2_11^0==__cil_tmp2_11^post_10 && __const_256^0==__const_256^post_10 && __disjvr_0^0==__disjvr_0^post_10 && __retres1_10^0==__retres1_10^post_10 && cnt_27^0==cnt_27^post_10 && cnt_32^0==cnt_32^post_10 && ct_15^0==ct_15^post_10 && ct_49^0==ct_49^post_10 && fdoExtension_7^0==fdoExtension_7^post_10 && lt_12^0==lt_12^post_10 && lt_13^0==lt_13^post_10 && lt_14^0==lt_14^post_10 && lt_16^0==lt_16^post_10 && lt_17^0==lt_17^post_10 && lt_18^0==lt_18^post_10 && ntStatus_8^0==ntStatus_8^post_10 ], cost: 1

Checking for constant complexity:
   The following rule is satisfiable with cost >= 1, yielding constant complexity:
      9: l8 -> l0 : Dc_6^0'=Dc_6^post_10, InterfaceType_5^0'=InterfaceType_5^post_10, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_10, Result_4^0'=Result_4^post_10, __cil_tmp2_11^0'=__cil_tmp2_11^post_10, __const_256^0'=__const_256^post_10, __disjvr_0^0'=__disjvr_0^post_10, __retres1_10^0'=__retres1_10^post_10, cnt_27^0'=cnt_27^post_10, cnt_32^0'=cnt_32^post_10, ct_15^0'=ct_15^post_10, ct_49^0'=ct_49^post_10, fdoExtension_7^0'=fdoExtension_7^post_10, lt_12^0'=lt_12^post_10, lt_13^0'=lt_13^post_10, lt_14^0'=lt_14^post_10, lt_16^0'=lt_16^post_10, lt_17^0'=lt_17^post_10, lt_18^0'=lt_18^post_10, ntStatus_8^0'=ntStatus_8^post_10, [ Dc_6^0==Dc_6^post_10 && InterfaceType_5^0==InterfaceType_5^post_10 && MaximumInterfaceType_9^0==MaximumInterfaceType_9^post_10 && Result_4^0==Result_4^post_10 && __cil_tmp2_11^0==__cil_tmp2_11^post_10 && __const_256^0==__const_256^post_10 && __disjvr_0^0==__disjvr_0^post_10 && __retres1_10^0==__retres1_10^post_10 && cnt_27^0==cnt_27^post_10 && cnt_32^0==cnt_32^post_10 && ct_15^0==ct_15^post_10 && ct_49^0==ct_49^post_10 && fdoExtension_7^0==fdoExtension_7^post_10 && lt_12^0==lt_12^post_10 && lt_13^0==lt_13^post_10 && lt_14^0==lt_14^post_10 && lt_16^0==lt_16^post_10 && lt_17^0==lt_17^post_10 && lt_18^0==lt_18^post_10 && ntStatus_8^0==ntStatus_8^post_10 ], cost: 1

Removed unreachable and leaf rules:
   Start location: l8
      0: l0 -> l1 : Dc_6^0'=Dc_6^post_1, InterfaceType_5^0'=InterfaceType_5^post_1, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_1, Result_4^0'=Result_4^post_1, __cil_tmp2_11^0'=__cil_tmp2_11^post_1, __const_256^0'=__const_256^post_1, __disjvr_0^0'=__disjvr_0^post_1, __retres1_10^0'=__retres1_10^post_1, cnt_27^0'=cnt_27^post_1, cnt_32^0'=cnt_32^post_1, ct_15^0'=ct_15^post_1, ct_49^0'=ct_49^post_1, fdoExtension_7^0'=fdoExtension_7^post_1, lt_12^0'=lt_12^post_1, lt_13^0'=lt_13^post_1, lt_14^0'=lt_14^post_1, lt_16^0'=lt_16^post_1, lt_17^0'=lt_17^post_1, lt_18^0'=lt_18^post_1, ntStatus_8^0'=ntStatus_8^post_1, [ MaximumInterfaceType_9^post_1==MaximumInterfaceType_9^post_1 && ntStatus_8^post_1==ntStatus_8^post_1 && fdoExtension_7^post_1==fdoExtension_7^post_1 && Dc_6^post_1==Dc_6^post_1 && InterfaceType_5^post_1==InterfaceType_5^post_1 && Result_4^0==Result_4^post_1 && __cil_tmp2_11^0==__cil_tmp2_11^post_1 && __const_256^0==__const_256^post_1 && __disjvr_0^0==__disjvr_0^post_1 && __retres1_10^0==__retres1_10^post_1 && cnt_27^0==cnt_27^post_1 && cnt_32^0==cnt_32^post_1 && ct_15^0==ct_15^post_1 && ct_49^0==ct_49^post_1 && lt_12^0==lt_12^post_1 && lt_13^0==lt_13^post_1 && lt_14^0==lt_14^post_1 && lt_16^0==lt_16^post_1 && lt_17^0==lt_17^post_1 && lt_18^0==lt_18^post_1 ], cost: 1
      4: l1 -> l5 : Dc_6^0'=Dc_6^post_5, InterfaceType_5^0'=InterfaceType_5^post_5, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_5, Result_4^0'=Result_4^post_5, __cil_tmp2_11^0'=__cil_tmp2_11^post_5, __const_256^0'=__const_256^post_5, __disjvr_0^0'=__disjvr_0^post_5, __retres1_10^0'=__retres1_10^post_5, cnt_27^0'=cnt_27^post_5, cnt_32^0'=cnt_32^post_5, ct_15^0'=ct_15^post_5, ct_49^0'=ct_49^post_5, fdoExtension_7^0'=fdoExtension_7^post_5, lt_12^0'=lt_12^post_5, lt_13^0'=lt_13^post_5, lt_14^0'=lt_14^post_5, lt_16^0'=lt_16^post_5, lt_17^0'=lt_17^post_5, lt_18^0'=lt_18^post_5, ntStatus_8^0'=ntStatus_8^post_5, [ lt_17^1_2_1==cnt_27^0 && lt_18^1_2_1==cnt_32^0 && 0<=-1-lt_17^1_2_1+lt_18^1_2_1 && lt_17^post_5==lt_17^post_5 && lt_18^post_5==lt_18^post_5 && lt_16^1_2_1==cnt_27^0 && lt_16^post_5==lt_16^post_5 && ct_15^1_2==ct_15^1_2 && ct_15^post_5==ct_15^post_5 && lt_14^1_2_1==ct_49^0 && lt_14^1_2_1<=0 && lt_14^post_5==lt_14^post_5 && Dc_6^0==Dc_6^post_5 && InterfaceType_5^0==InterfaceType_5^post_5 && MaximumInterfaceType_9^0==MaximumInterfaceType_9^post_5 && Result_4^0==Result_4^post_5 && __cil_tmp2_11^0==__cil_tmp2_11^post_5 && __const_256^0==__const_256^post_5 && __disjvr_0^0==__disjvr_0^post_5 && __retres1_10^0==__retres1_10^post_5 && cnt_27^0==cnt_27^post_5 && cnt_32^0==cnt_32^post_5 && ct_49^0==ct_49^post_5 && fdoExtension_7^0==fdoExtension_7^post_5 && lt_12^0==lt_12^post_5 && lt_13^0==lt_13^post_5 && ntStatus_8^0==ntStatus_8^post_5 ], cost: 1
      6: l1 -> l6 : Dc_6^0'=Dc_6^post_7, InterfaceType_5^0'=InterfaceType_5^post_7, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_7, Result_4^0'=Result_4^post_7, __cil_tmp2_11^0'=__cil_tmp2_11^post_7, __const_256^0'=__const_256^post_7, __disjvr_0^0'=__disjvr_0^post_7, __retres1_10^0'=__retres1_10^post_7, cnt_27^0'=cnt_27^post_7, cnt_32^0'=cnt_32^post_7, ct_15^0'=ct_15^post_7, ct_49^0'=ct_49^post_7, fdoExtension_7^0'=fdoExtension_7^post_7, lt_12^0'=lt_12^post_7, lt_13^0'=lt_13^post_7, lt_14^0'=lt_14^post_7, lt_16^0'=lt_16^post_7, lt_17^0'=lt_17^post_7, lt_18^0'=lt_18^post_7, ntStatus_8^0'=ntStatus_8^post_7, [ lt_17^1_3_1==cnt_27^0 && lt_18^1_3_1==cnt_32^0 && 0<=-1-lt_17^1_3_1+lt_18^1_3_1 && lt_17^post_7==lt_17^post_7 && lt_18^post_7==lt_18^post_7 && lt_16^1_3_1==cnt_27^0 && lt_16^post_7==lt_16^post_7 && ct_15^1_3==ct_15^1_3 && ct_15^post_7==ct_15^post_7 && lt_14^1_3_1==ct_49^0 && 0<=-1+lt_14^1_3_1 && lt_14^post_7==lt_14^post_7 && lt_13^1_1==ct_49^0 && lt_13^1_1<=__const_256^0 && __const_256^0<=lt_13^1_1 && lt_13^post_7==lt_13^post_7 && Dc_6^0==Dc_6^post_7 && InterfaceType_5^0==InterfaceType_5^post_7 && MaximumInterfaceType_9^0==MaximumInterfaceType_9^post_7 && Result_4^0==Result_4^post_7 && __cil_tmp2_11^0==__cil_tmp2_11^post_7 && __const_256^0==__const_256^post_7 && __disjvr_0^0==__disjvr_0^post_7 && __retres1_10^0==__retres1_10^post_7 && cnt_27^0==cnt_27^post_7 && cnt_32^0==cnt_32^post_7 && ct_49^0==ct_49^post_7 && fdoExtension_7^0==fdoExtension_7^post_7 && lt_12^0==lt_12^post_7 && ntStatus_8^0==ntStatus_8^post_7 ], cost: 1
      5: l5 -> l1 : Dc_6^0'=Dc_6^post_6, InterfaceType_5^0'=InterfaceType_5^post_6, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_6, Result_4^0'=Result_4^post_6, __cil_tmp2_11^0'=__cil_tmp2_11^post_6, __const_256^0'=__const_256^post_6, __disjvr_0^0'=__disjvr_0^post_6, __retres1_10^0'=__retres1_10^post_6, cnt_27^0'=cnt_27^post_6, cnt_32^0'=cnt_32^post_6, ct_15^0'=ct_15^post_6, ct_49^0'=ct_49^post_6, fdoExtension_7^0'=fdoExtension_7^post_6, lt_12^0'=lt_12^post_6, lt_13^0'=lt_13^post_6, lt_14^0'=lt_14^post_6, lt_16^0'=lt_16^post_6, lt_17^0'=lt_17^post_6, lt_18^0'=lt_18^post_6, ntStatus_8^0'=ntStatus_8^post_6, [ Dc_6^0==Dc_6^post_6 && InterfaceType_5^0==InterfaceType_5^post_6 && MaximumInterfaceType_9^0==MaximumInterfaceType_9^post_6 && Result_4^0==Result_4^post_6 && __cil_tmp2_11^0==__cil_tmp2_11^post_6 && __const_256^0==__const_256^post_6 && __disjvr_0^0==__disjvr_0^post_6 && __retres1_10^0==__retres1_10^post_6 && cnt_27^0==cnt_27^post_6 && cnt_32^0==cnt_32^post_6 && ct_15^0==ct_15^post_6 && ct_49^0==ct_49^post_6 && fdoExtension_7^0==fdoExtension_7^post_6 && lt_12^0==lt_12^post_6 && lt_13^0==lt_13^post_6 && lt_14^0==lt_14^post_6 && lt_16^0==lt_16^post_6 && lt_17^0==lt_17^post_6 && lt_18^0==lt_18^post_6 && ntStatus_8^0==ntStatus_8^post_6 ], cost: 1
      7: l6 -> l1 : Dc_6^0'=Dc_6^post_8, InterfaceType_5^0'=InterfaceType_5^post_8, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_8, Result_4^0'=Result_4^post_8, __cil_tmp2_11^0'=__cil_tmp2_11^post_8, __const_256^0'=__const_256^post_8, __disjvr_0^0'=__disjvr_0^post_8, __retres1_10^0'=__retres1_10^post_8, cnt_27^0'=cnt_27^post_8, cnt_32^0'=cnt_32^post_8, ct_15^0'=ct_15^post_8, ct_49^0'=ct_49^post_8, fdoExtension_7^0'=fdoExtension_7^post_8, lt_12^0'=lt_12^post_8, lt_13^0'=lt_13^post_8, lt_14^0'=lt_14^post_8, lt_16^0'=lt_16^post_8, lt_17^0'=lt_17^post_8, lt_18^0'=lt_18^post_8, ntStatus_8^0'=ntStatus_8^post_8, [ Dc_6^0==Dc_6^post_8 && InterfaceType_5^0==InterfaceType_5^post_8 && MaximumInterfaceType_9^0==MaximumInterfaceType_9^post_8 && Result_4^0==Result_4^post_8 && __cil_tmp2_11^0==__cil_tmp2_11^post_8 && __const_256^0==__const_256^post_8 && __disjvr_0^0==__disjvr_0^post_8 && __retres1_10^0==__retres1_10^post_8 && cnt_27^0==cnt_27^post_8 && cnt_32^0==cnt_32^post_8 && ct_15^0==ct_15^post_8 && ct_49^0==ct_49^post_8 && fdoExtension_7^0==fdoExtension_7^post_8 && lt_12^0==lt_12^post_8 && lt_13^0==lt_13^post_8 && lt_14^0==lt_14^post_8 && lt_16^0==lt_16^post_8 && lt_17^0==lt_17^post_8 && lt_18^0==lt_18^post_8 && ntStatus_8^0==ntStatus_8^post_8 ], cost: 1
      9: l8 -> l0 : Dc_6^0'=Dc_6^post_10, InterfaceType_5^0'=InterfaceType_5^post_10, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_10, Result_4^0'=Result_4^post_10, __cil_tmp2_11^0'=__cil_tmp2_11^post_10, __const_256^0'=__const_256^post_10, __disjvr_0^0'=__disjvr_0^post_10, __retres1_10^0'=__retres1_10^post_10, cnt_27^0'=cnt_27^post_10, cnt_32^0'=cnt_32^post_10, ct_15^0'=ct_15^post_10, ct_49^0'=ct_49^post_10, fdoExtension_7^0'=fdoExtension_7^post_10, lt_12^0'=lt_12^post_10, lt_13^0'=lt_13^post_10, lt_14^0'=lt_14^post_10, lt_16^0'=lt_16^post_10, lt_17^0'=lt_17^post_10, lt_18^0'=lt_18^post_10, ntStatus_8^0'=ntStatus_8^post_10, [ Dc_6^0==Dc_6^post_10 && InterfaceType_5^0==InterfaceType_5^post_10 && MaximumInterfaceType_9^0==MaximumInterfaceType_9^post_10 && Result_4^0==Result_4^post_10 && __cil_tmp2_11^0==__cil_tmp2_11^post_10 && __const_256^0==__const_256^post_10 && __disjvr_0^0==__disjvr_0^post_10 && __retres1_10^0==__retres1_10^post_10 && cnt_27^0==cnt_27^post_10 && cnt_32^0==cnt_32^post_10 && ct_15^0==ct_15^post_10 && ct_49^0==ct_49^post_10 && fdoExtension_7^0==fdoExtension_7^post_10 && lt_12^0==lt_12^post_10 && lt_13^0==lt_13^post_10 && lt_14^0==lt_14^post_10 && lt_16^0==lt_16^post_10 && lt_17^0==lt_17^post_10 && lt_18^0==lt_18^post_10 && ntStatus_8^0==ntStatus_8^post_10 ], cost: 1

Simplified all rules, resulting in:
   Start location: l8
      0: l0 -> l1 : Dc_6^0'=Dc_6^post_1, InterfaceType_5^0'=InterfaceType_5^post_1, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_1, fdoExtension_7^0'=fdoExtension_7^post_1, ntStatus_8^0'=ntStatus_8^post_1, [], cost: 1
      4: l1 -> l5 : ct_15^0'=ct_15^post_5, lt_14^0'=lt_14^post_5, lt_16^0'=lt_16^post_5, lt_17^0'=lt_17^post_5, lt_18^0'=lt_18^post_5, [ 0<=-1-cnt_27^0+cnt_32^0 && ct_49^0<=0 ], cost: 1
      6: l1 -> l6 : ct_15^0'=ct_15^post_7, lt_13^0'=lt_13^post_7, lt_14^0'=lt_14^post_7, lt_16^0'=lt_16^post_7, lt_17^0'=lt_17^post_7, lt_18^0'=lt_18^post_7, [ 0<=-1-cnt_27^0+cnt_32^0 && 0<=-1+ct_49^0 && ct_49^0-__const_256^0==0 ], cost: 1
      5: l5 -> l1 : [], cost: 1
      7: l6 -> l1 : [], cost: 1
      9: l8 -> l0 : [], cost: 1

### Simplification by acceleration and chaining ###

Eliminated locations (on linear paths):
   Start location: l8
     11: l1 -> l1 : ct_15^0'=ct_15^post_5, lt_14^0'=lt_14^post_5, lt_16^0'=lt_16^post_5, lt_17^0'=lt_17^post_5, lt_18^0'=lt_18^post_5, [ 0<=-1-cnt_27^0+cnt_32^0 && ct_49^0<=0 ], cost: 2
     12: l1 -> l1 : ct_15^0'=ct_15^post_7, lt_13^0'=lt_13^post_7, lt_14^0'=lt_14^post_7, lt_16^0'=lt_16^post_7, lt_17^0'=lt_17^post_7, lt_18^0'=lt_18^post_7, [ 0<=-1-cnt_27^0+cnt_32^0 && 0<=-1+ct_49^0 && ct_49^0-__const_256^0==0 ], cost: 2
     10: l8 -> l1 : Dc_6^0'=Dc_6^post_1, InterfaceType_5^0'=InterfaceType_5^post_1, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_1, fdoExtension_7^0'=fdoExtension_7^post_1, ntStatus_8^0'=ntStatus_8^post_1, [], cost: 2

Accelerating simple loops of location 1.
   Accelerating the following rules:
     11: l1 -> l1 : ct_15^0'=ct_15^post_5, lt_14^0'=lt_14^post_5, lt_16^0'=lt_16^post_5, lt_17^0'=lt_17^post_5, lt_18^0'=lt_18^post_5, [ 0<=-1-cnt_27^0+cnt_32^0 && ct_49^0<=0 ], cost: 2
     12: l1 -> l1 : ct_15^0'=ct_15^post_7, lt_13^0'=lt_13^post_7, lt_14^0'=lt_14^post_7, lt_16^0'=lt_16^post_7, lt_17^0'=lt_17^post_7, lt_18^0'=lt_18^post_7, [ 0<=-1-cnt_27^0+cnt_32^0 && 0<=-1+ct_49^0 && ct_49^0-__const_256^0==0 ], cost: 2

   Accelerated rule 11 with non-termination, yielding the new rule 13.
   Accelerated rule 12 with non-termination, yielding the new rule 14.
[accelerate] Nesting with 0 inner and 0 outer candidates
   Removing the simple loops: 11 12.

Accelerated all simple loops using metering functions (where possible):
   Start location: l8
     13: l1 -> [9] : [ 0<=-1-cnt_27^0+cnt_32^0 && ct_49^0<=0 ], cost: NONTERM
     14: l1 -> [9] : [ 0<=-1-cnt_27^0+cnt_32^0 && 0<=-1+ct_49^0 && ct_49^0-__const_256^0==0 ], cost: NONTERM
     10: l8 -> l1 : Dc_6^0'=Dc_6^post_1, InterfaceType_5^0'=InterfaceType_5^post_1, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_1, fdoExtension_7^0'=fdoExtension_7^post_1, ntStatus_8^0'=ntStatus_8^post_1, [], cost: 2

Chained accelerated rules (with incoming rules):
   Start location: l8
     10: l8 -> l1 : Dc_6^0'=Dc_6^post_1, InterfaceType_5^0'=InterfaceType_5^post_1, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_1, fdoExtension_7^0'=fdoExtension_7^post_1, ntStatus_8^0'=ntStatus_8^post_1, [], cost: 2
     15: l8 -> [9] : [ 0<=-1-cnt_27^0+cnt_32^0 && ct_49^0<=0 ], cost: NONTERM
     16: l8 -> [9] : [ 0<=-1-cnt_27^0+cnt_32^0 && 0<=-1+ct_49^0 && ct_49^0-__const_256^0==0 ], cost: NONTERM

Removed unreachable locations (and leaf rules with constant cost):
   Start location: l8
     15: l8 -> [9] : [ 0<=-1-cnt_27^0+cnt_32^0 && ct_49^0<=0 ], cost: NONTERM
     16: l8 -> [9] : [ 0<=-1-cnt_27^0+cnt_32^0 && 0<=-1+ct_49^0 && ct_49^0-__const_256^0==0 ], cost: NONTERM

### Computing asymptotic complexity ###

Fully simplified ITS problem
   Start location: l8
     15: l8 -> [9] : [ 0<=-1-cnt_27^0+cnt_32^0 && ct_49^0<=0 ], cost: NONTERM
     16: l8 -> [9] : [ 0<=-1-cnt_27^0+cnt_32^0 && 0<=-1+ct_49^0 && ct_49^0-__const_256^0==0 ], cost: NONTERM

Computing asymptotic complexity for rule 15
   Guard is satisfiable, yielding nontermination
   Resulting cost NONTERM has complexity: Nonterm

Found new complexity Nonterm.

Obtained the following overall complexity (w.r.t. the length of the input n):
   Complexity:  Nonterm
   Cpx degree:  Nonterm
   Solved cost: NONTERM
   Rule cost:   NONTERM
   Rule guard:  [ 0<=-1-cnt_27^0+cnt_32^0 && ct_49^0<=0 ]

NO