NO

### Pre-processing the ITS problem ###

Initial linear ITS problem
   Start location: l34
      0: l0 -> l1 : AsyncAddressData^0'=AsyncAddressData^post_1, BusResetIrp^0'=BusResetIrp^post_1, CromData^0'=CromData^post_1, DeviceObject^0'=DeviceObject^post_1, Irp^0'=Irp^post_1, Irql^0'=Irql^post_1, IsochDetachData^0'=IsochDetachData^post_1, IsochResourceData^0'=IsochResourceData^post_1, ResourceIrp^0'=ResourceIrp^post_1, StackSize^0'=StackSize^post_1, __rho_10_^0'=__rho_10_^post_1, __rho_11_^0'=__rho_11_^post_1, __rho_12_^0'=__rho_12_^post_1, __rho_1_^0'=__rho_1_^post_1, __rho_2_^0'=__rho_2_^post_1, __rho_3_^0'=__rho_3_^post_1, __rho_4_^0'=__rho_4_^post_1, __rho_5_^0'=__rho_5_^post_1, __rho_666_^0'=__rho_666_^post_1, __rho_7_^0'=__rho_7_^post_1, __rho_8_^0'=__rho_8_^post_1, __rho_9_^0'=__rho_9_^post_1, a11^0'=a11^post_1, a1818^0'=a1818^post_1, a2525^0'=a2525^post_1, a2828^0'=a2828^post_1, a3131^0'=a3131^post_1, a3232^0'=a3232^post_1, a3434^0'=a3434^post_1, a3737^0'=a3737^post_1, a3838^0'=a3838^post_1, a4343^0'=a4343^post_1, a4545^0'=a4545^post_1, a77^0'=a77^post_1, b22^0'=b22^post_1, b2626^0'=b2626^post_1, b2929^0'=b2929^post_1, b3333^0'=b3333^post_1, b3535^0'=b3535^post_1, i^0'=i^post_1, i___01313^0'=i___01313^post_1, i___01717^0'=i___01717^post_1, i___02020^0'=i___02020^post_1, i___02424^0'=i___02424^post_1, i___04040^0'=i___04040^post_1, i___04747^0'=i___04747^post_1, i___099^0'=i___099^post_1, ioA^0'=ioA^post_1, ioR^0'=ioR^post_1, k1^0'=k1^post_1, k2^0'=k2^post_1, k3^0'=k3^post_1, k4^0'=k4^post_1, k5^0'=k5^post_1, keA^0'=keA^post_1, keR^0'=keR^post_1, ntStatus^0'=ntStatus^post_1, pIrb^0'=pIrb^post_1, phi_io_compl^0'=phi_io_compl^post_1, phi_nSUC_ret^0'=phi_nSUC_ret^post_1, prevCancel^0'=prevCancel^post_1, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_1, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_1, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_1, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_1, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_1, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_1, [ k3^0<=0 && i___02020^post_1==Irql^0 && keR^1_1==1 && keR^post_1==0 && __rho_11_^post_1==__rho_11_^post_1 && k4^post_1==__rho_11_^post_1 && AsyncAddressData^0==AsyncAddressData^post_1 && BusResetIrp^0==BusResetIrp^post_1 && CromData^0==CromData^post_1 && DeviceObject^0==DeviceObject^post_1 && Irp^0==Irp^post_1 && Irql^0==Irql^post_1 && IsochDetachData^0==IsochDetachData^post_1 && IsochResourceData^0==IsochResourceData^post_1 && ResourceIrp^0==ResourceIrp^post_1 && StackSize^0==StackSize^post_1 && __rho_10_^0==__rho_10_^post_1 && __rho_12_^0==__rho_12_^post_1 && __rho_1_^0==__rho_1_^post_1 && __rho_2_^0==__rho_2_^post_1 && __rho_3_^0==__rho_3_^post_1 && __rho_4_^0==__rho_4_^post_1 && __rho_5_^0==__rho_5_^post_1 && __rho_666_^0==__rho_666_^post_1 && __rho_7_^0==__rho_7_^post_1 && __rho_8_^0==__rho_8_^post_1 && __rho_9_^0==__rho_9_^post_1 && a11^0==a11^post_1 && a1818^0==a1818^post_1 && a2525^0==a2525^post_1 && a2828^0==a2828^post_1 && a3131^0==a3131^post_1 && a3232^0==a3232^post_1 && a3434^0==a3434^post_1 && a3737^0==a3737^post_1 && a3838^0==a3838^post_1 && a4343^0==a4343^post_1 && a4545^0==a4545^post_1 && a77^0==a77^post_1 && b22^0==b22^post_1 && b2626^0==b2626^post_1 && b2929^0==b2929^post_1 && b3333^0==b3333^post_1 && b3535^0==b3535^post_1 && i^0==i^post_1 && i___01313^0==i___01313^post_1 && i___01717^0==i___01717^post_1 && i___02424^0==i___02424^post_1 && i___04040^0==i___04040^post_1 && i___04747^0==i___04747^post_1 && i___099^0==i___099^post_1 && ioA^0==ioA^post_1 && ioR^0==ioR^post_1 && k1^0==k1^post_1 && k2^0==k2^post_1 && k3^0==k3^post_1 && k5^0==k5^post_1 && keA^0==keA^post_1 && ntStatus^0==ntStatus^post_1 && pIrb^0==pIrb^post_1 && phi_io_compl^0==phi_io_compl^post_1 && phi_nSUC_ret^0==phi_nSUC_ret^post_1 && prevCancel^0==prevCancel^post_1 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_1 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_1 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_1 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_1 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_1 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_1 ], cost: 1
      1: l0 -> l2 : AsyncAddressData^0'=AsyncAddressData^post_2, BusResetIrp^0'=BusResetIrp^post_2, CromData^0'=CromData^post_2, DeviceObject^0'=DeviceObject^post_2, Irp^0'=Irp^post_2, Irql^0'=Irql^post_2, IsochDetachData^0'=IsochDetachData^post_2, IsochResourceData^0'=IsochResourceData^post_2, ResourceIrp^0'=ResourceIrp^post_2, StackSize^0'=StackSize^post_2, __rho_10_^0'=__rho_10_^post_2, __rho_11_^0'=__rho_11_^post_2, __rho_12_^0'=__rho_12_^post_2, __rho_1_^0'=__rho_1_^post_2, __rho_2_^0'=__rho_2_^post_2, __rho_3_^0'=__rho_3_^post_2, __rho_4_^0'=__rho_4_^post_2, __rho_5_^0'=__rho_5_^post_2, __rho_666_^0'=__rho_666_^post_2, __rho_7_^0'=__rho_7_^post_2, __rho_8_^0'=__rho_8_^post_2, __rho_9_^0'=__rho_9_^post_2, a11^0'=a11^post_2, a1818^0'=a1818^post_2, a2525^0'=a2525^post_2, a2828^0'=a2828^post_2, a3131^0'=a3131^post_2, a3232^0'=a3232^post_2, a3434^0'=a3434^post_2, a3737^0'=a3737^post_2, a3838^0'=a3838^post_2, a4343^0'=a4343^post_2, a4545^0'=a4545^post_2, a77^0'=a77^post_2, b22^0'=b22^post_2, b2626^0'=b2626^post_2, b2929^0'=b2929^post_2, b3333^0'=b3333^post_2, b3535^0'=b3535^post_2, i^0'=i^post_2, i___01313^0'=i___01313^post_2, i___01717^0'=i___01717^post_2, i___02020^0'=i___02020^post_2, i___02424^0'=i___02424^post_2, i___04040^0'=i___04040^post_2, i___04747^0'=i___04747^post_2, i___099^0'=i___099^post_2, ioA^0'=ioA^post_2, ioR^0'=ioR^post_2, k1^0'=k1^post_2, k2^0'=k2^post_2, k3^0'=k3^post_2, k4^0'=k4^post_2, k5^0'=k5^post_2, keA^0'=keA^post_2, keR^0'=keR^post_2, ntStatus^0'=ntStatus^post_2, pIrb^0'=pIrb^post_2, phi_io_compl^0'=phi_io_compl^post_2, phi_nSUC_ret^0'=phi_nSUC_ret^post_2, prevCancel^0'=prevCancel^post_2, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_2, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_2, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_2, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_2, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_2, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_2, [ 1<=k3^0 && IsochDetachData^1_1==IsochDetachData^1_1 && i^post_2==i^post_2 && IsochDetachData^post_2==IsochDetachData^post_2 && k3^post_2==-1+k3^0 && i___01717^post_2==Irql^0 && keR^1_2_1==1 && keR^post_2==0 && a1818^post_2==IsochDetachData^post_2 && AsyncAddressData^0==AsyncAddressData^post_2 && BusResetIrp^0==BusResetIrp^post_2 && CromData^0==CromData^post_2 && DeviceObject^0==DeviceObject^post_2 && Irp^0==Irp^post_2 && Irql^0==Irql^post_2 && IsochResourceData^0==IsochResourceData^post_2 && ResourceIrp^0==ResourceIrp^post_2 && StackSize^0==StackSize^post_2 && __rho_10_^0==__rho_10_^post_2 && __rho_11_^0==__rho_11_^post_2 && __rho_12_^0==__rho_12_^post_2 && __rho_1_^0==__rho_1_^post_2 && __rho_2_^0==__rho_2_^post_2 && __rho_3_^0==__rho_3_^post_2 && __rho_4_^0==__rho_4_^post_2 && __rho_5_^0==__rho_5_^post_2 && __rho_666_^0==__rho_666_^post_2 && __rho_7_^0==__rho_7_^post_2 && __rho_8_^0==__rho_8_^post_2 && __rho_9_^0==__rho_9_^post_2 && a11^0==a11^post_2 && a2525^0==a2525^post_2 && a2828^0==a2828^post_2 && a3131^0==a3131^post_2 && a3232^0==a3232^post_2 && a3434^0==a3434^post_2 && a3737^0==a3737^post_2 && a3838^0==a3838^post_2 && a4343^0==a4343^post_2 && a4545^0==a4545^post_2 && a77^0==a77^post_2 && b22^0==b22^post_2 && b2626^0==b2626^post_2 && b2929^0==b2929^post_2 && b3333^0==b3333^post_2 && b3535^0==b3535^post_2 && i___01313^0==i___01313^post_2 && i___02020^0==i___02020^post_2 && i___02424^0==i___02424^post_2 && i___04040^0==i___04040^post_2 && i___04747^0==i___04747^post_2 && i___099^0==i___099^post_2 && ioA^0==ioA^post_2 && ioR^0==ioR^post_2 && k1^0==k1^post_2 && k2^0==k2^post_2 && k4^0==k4^post_2 && k5^0==k5^post_2 && keA^0==keA^post_2 && ntStatus^0==ntStatus^post_2 && pIrb^0==pIrb^post_2 && phi_io_compl^0==phi_io_compl^post_2 && phi_nSUC_ret^0==phi_nSUC_ret^post_2 && prevCancel^0==prevCancel^post_2 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_2 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_2 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_2 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_2 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_2 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_2 ], cost: 1
     23: l1 -> l17 : AsyncAddressData^0'=AsyncAddressData^post_24, BusResetIrp^0'=BusResetIrp^post_24, CromData^0'=CromData^post_24, DeviceObject^0'=DeviceObject^post_24, Irp^0'=Irp^post_24, Irql^0'=Irql^post_24, IsochDetachData^0'=IsochDetachData^post_24, IsochResourceData^0'=IsochResourceData^post_24, ResourceIrp^0'=ResourceIrp^post_24, StackSize^0'=StackSize^post_24, __rho_10_^0'=__rho_10_^post_24, __rho_11_^0'=__rho_11_^post_24, __rho_12_^0'=__rho_12_^post_24, __rho_1_^0'=__rho_1_^post_24, __rho_2_^0'=__rho_2_^post_24, __rho_3_^0'=__rho_3_^post_24, __rho_4_^0'=__rho_4_^post_24, __rho_5_^0'=__rho_5_^post_24, __rho_666_^0'=__rho_666_^post_24, __rho_7_^0'=__rho_7_^post_24, __rho_8_^0'=__rho_8_^post_24, __rho_9_^0'=__rho_9_^post_24, a11^0'=a11^post_24, a1818^0'=a1818^post_24, a2525^0'=a2525^post_24, a2828^0'=a2828^post_24, a3131^0'=a3131^post_24, a3232^0'=a3232^post_24, a3434^0'=a3434^post_24, a3737^0'=a3737^post_24, a3838^0'=a3838^post_24, a4343^0'=a4343^post_24, a4545^0'=a4545^post_24, a77^0'=a77^post_24, b22^0'=b22^post_24, b2626^0'=b2626^post_24, b2929^0'=b2929^post_24, b3333^0'=b3333^post_24, b3535^0'=b3535^post_24, i^0'=i^post_24, i___01313^0'=i___01313^post_24, i___01717^0'=i___01717^post_24, i___02020^0'=i___02020^post_24, i___02424^0'=i___02424^post_24, i___04040^0'=i___04040^post_24, i___04747^0'=i___04747^post_24, i___099^0'=i___099^post_24, ioA^0'=ioA^post_24, ioR^0'=ioR^post_24, k1^0'=k1^post_24, k2^0'=k2^post_24, k3^0'=k3^post_24, k4^0'=k4^post_24, k5^0'=k5^post_24, keA^0'=keA^post_24, keR^0'=keR^post_24, ntStatus^0'=ntStatus^post_24, pIrb^0'=pIrb^post_24, phi_io_compl^0'=phi_io_compl^post_24, phi_nSUC_ret^0'=phi_nSUC_ret^post_24, prevCancel^0'=prevCancel^post_24, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_24, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_24, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_24, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_24, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_24, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_24, [ keA^1_2==1 && keA^post_24==0 && AsyncAddressData^0==AsyncAddressData^post_24 && BusResetIrp^0==BusResetIrp^post_24 && CromData^0==CromData^post_24 && DeviceObject^0==DeviceObject^post_24 && Irp^0==Irp^post_24 && Irql^0==Irql^post_24 && IsochDetachData^0==IsochDetachData^post_24 && IsochResourceData^0==IsochResourceData^post_24 && ResourceIrp^0==ResourceIrp^post_24 && StackSize^0==StackSize^post_24 && __rho_10_^0==__rho_10_^post_24 && __rho_11_^0==__rho_11_^post_24 && __rho_12_^0==__rho_12_^post_24 && __rho_1_^0==__rho_1_^post_24 && __rho_2_^0==__rho_2_^post_24 && __rho_3_^0==__rho_3_^post_24 && __rho_4_^0==__rho_4_^post_24 && __rho_5_^0==__rho_5_^post_24 && __rho_666_^0==__rho_666_^post_24 && __rho_7_^0==__rho_7_^post_24 && __rho_8_^0==__rho_8_^post_24 && __rho_9_^0==__rho_9_^post_24 && a11^0==a11^post_24 && a1818^0==a1818^post_24 && a2525^0==a2525^post_24 && a2828^0==a2828^post_24 && a3131^0==a3131^post_24 && a3232^0==a3232^post_24 && a3434^0==a3434^post_24 && a3737^0==a3737^post_24 && a3838^0==a3838^post_24 && a4343^0==a4343^post_24 && a4545^0==a4545^post_24 && a77^0==a77^post_24 && b22^0==b22^post_24 && b2626^0==b2626^post_24 && b2929^0==b2929^post_24 && b3333^0==b3333^post_24 && b3535^0==b3535^post_24 && i^0==i^post_24 && i___01313^0==i___01313^post_24 && i___01717^0==i___01717^post_24 && i___02020^0==i___02020^post_24 && i___02424^0==i___02424^post_24 && i___04040^0==i___04040^post_24 && i___04747^0==i___04747^post_24 && i___099^0==i___099^post_24 && ioA^0==ioA^post_24 && ioR^0==ioR^post_24 && k1^0==k1^post_24 && k2^0==k2^post_24 && k3^0==k3^post_24 && k4^0==k4^post_24 && k5^0==k5^post_24 && keR^0==keR^post_24 && ntStatus^0==ntStatus^post_24 && pIrb^0==pIrb^post_24 && phi_io_compl^0==phi_io_compl^post_24 && phi_nSUC_ret^0==phi_nSUC_ret^post_24 && prevCancel^0==prevCancel^post_24 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_24 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_24 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_24 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_24 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_24 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_24 ], cost: 1
     16: l2 -> l0 : AsyncAddressData^0'=AsyncAddressData^post_17, BusResetIrp^0'=BusResetIrp^post_17, CromData^0'=CromData^post_17, DeviceObject^0'=DeviceObject^post_17, Irp^0'=Irp^post_17, Irql^0'=Irql^post_17, IsochDetachData^0'=IsochDetachData^post_17, IsochResourceData^0'=IsochResourceData^post_17, ResourceIrp^0'=ResourceIrp^post_17, StackSize^0'=StackSize^post_17, __rho_10_^0'=__rho_10_^post_17, __rho_11_^0'=__rho_11_^post_17, __rho_12_^0'=__rho_12_^post_17, __rho_1_^0'=__rho_1_^post_17, __rho_2_^0'=__rho_2_^post_17, __rho_3_^0'=__rho_3_^post_17, __rho_4_^0'=__rho_4_^post_17, __rho_5_^0'=__rho_5_^post_17, __rho_666_^0'=__rho_666_^post_17, __rho_7_^0'=__rho_7_^post_17, __rho_8_^0'=__rho_8_^post_17, __rho_9_^0'=__rho_9_^post_17, a11^0'=a11^post_17, a1818^0'=a1818^post_17, a2525^0'=a2525^post_17, a2828^0'=a2828^post_17, a3131^0'=a3131^post_17, a3232^0'=a3232^post_17, a3434^0'=a3434^post_17, a3737^0'=a3737^post_17, a3838^0'=a3838^post_17, a4343^0'=a4343^post_17, a4545^0'=a4545^post_17, a77^0'=a77^post_17, b22^0'=b22^post_17, b2626^0'=b2626^post_17, b2929^0'=b2929^post_17, b3333^0'=b3333^post_17, b3535^0'=b3535^post_17, i^0'=i^post_17, i___01313^0'=i___01313^post_17, i___01717^0'=i___01717^post_17, i___02020^0'=i___02020^post_17, i___02424^0'=i___02424^post_17, i___04040^0'=i___04040^post_17, i___04747^0'=i___04747^post_17, i___099^0'=i___099^post_17, ioA^0'=ioA^post_17, ioR^0'=ioR^post_17, k1^0'=k1^post_17, k2^0'=k2^post_17, k3^0'=k3^post_17, k4^0'=k4^post_17, k5^0'=k5^post_17, keA^0'=keA^post_17, keR^0'=keR^post_17, ntStatus^0'=ntStatus^post_17, pIrb^0'=pIrb^post_17, phi_io_compl^0'=phi_io_compl^post_17, phi_nSUC_ret^0'=phi_nSUC_ret^post_17, prevCancel^0'=prevCancel^post_17, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_17, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_17, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_17, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_17, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_17, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_17, [ keA^1_1==1 && keA^post_17==0 && AsyncAddressData^0==AsyncAddressData^post_17 && BusResetIrp^0==BusResetIrp^post_17 && CromData^0==CromData^post_17 && DeviceObject^0==DeviceObject^post_17 && Irp^0==Irp^post_17 && Irql^0==Irql^post_17 && IsochDetachData^0==IsochDetachData^post_17 && IsochResourceData^0==IsochResourceData^post_17 && ResourceIrp^0==ResourceIrp^post_17 && StackSize^0==StackSize^post_17 && __rho_10_^0==__rho_10_^post_17 && __rho_11_^0==__rho_11_^post_17 && __rho_12_^0==__rho_12_^post_17 && __rho_1_^0==__rho_1_^post_17 && __rho_2_^0==__rho_2_^post_17 && __rho_3_^0==__rho_3_^post_17 && __rho_4_^0==__rho_4_^post_17 && __rho_5_^0==__rho_5_^post_17 && __rho_666_^0==__rho_666_^post_17 && __rho_7_^0==__rho_7_^post_17 && __rho_8_^0==__rho_8_^post_17 && __rho_9_^0==__rho_9_^post_17 && a11^0==a11^post_17 && a1818^0==a1818^post_17 && a2525^0==a2525^post_17 && a2828^0==a2828^post_17 && a3131^0==a3131^post_17 && a3232^0==a3232^post_17 && a3434^0==a3434^post_17 && a3737^0==a3737^post_17 && a3838^0==a3838^post_17 && a4343^0==a4343^post_17 && a4545^0==a4545^post_17 && a77^0==a77^post_17 && b22^0==b22^post_17 && b2626^0==b2626^post_17 && b2929^0==b2929^post_17 && b3333^0==b3333^post_17 && b3535^0==b3535^post_17 && i^0==i^post_17 && i___01313^0==i___01313^post_17 && i___01717^0==i___01717^post_17 && i___02020^0==i___02020^post_17 && i___02424^0==i___02424^post_17 && i___04040^0==i___04040^post_17 && i___04747^0==i___04747^post_17 && i___099^0==i___099^post_17 && ioA^0==ioA^post_17 && ioR^0==ioR^post_17 && k1^0==k1^post_17 && k2^0==k2^post_17 && k3^0==k3^post_17 && k4^0==k4^post_17 && k5^0==k5^post_17 && keR^0==keR^post_17 && ntStatus^0==ntStatus^post_17 && pIrb^0==pIrb^post_17 && phi_io_compl^0==phi_io_compl^post_17 && phi_nSUC_ret^0==phi_nSUC_ret^post_17 && prevCancel^0==prevCancel^post_17 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_17 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_17 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_17 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_17 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_17 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_17 ], cost: 1
      2: l3 -> l4 : AsyncAddressData^0'=AsyncAddressData^post_3, BusResetIrp^0'=BusResetIrp^post_3, CromData^0'=CromData^post_3, DeviceObject^0'=DeviceObject^post_3, Irp^0'=Irp^post_3, Irql^0'=Irql^post_3, IsochDetachData^0'=IsochDetachData^post_3, IsochResourceData^0'=IsochResourceData^post_3, ResourceIrp^0'=ResourceIrp^post_3, StackSize^0'=StackSize^post_3, __rho_10_^0'=__rho_10_^post_3, __rho_11_^0'=__rho_11_^post_3, __rho_12_^0'=__rho_12_^post_3, __rho_1_^0'=__rho_1_^post_3, __rho_2_^0'=__rho_2_^post_3, __rho_3_^0'=__rho_3_^post_3, __rho_4_^0'=__rho_4_^post_3, __rho_5_^0'=__rho_5_^post_3, __rho_666_^0'=__rho_666_^post_3, __rho_7_^0'=__rho_7_^post_3, __rho_8_^0'=__rho_8_^post_3, __rho_9_^0'=__rho_9_^post_3, a11^0'=a11^post_3, a1818^0'=a1818^post_3, a2525^0'=a2525^post_3, a2828^0'=a2828^post_3, a3131^0'=a3131^post_3, a3232^0'=a3232^post_3, a3434^0'=a3434^post_3, a3737^0'=a3737^post_3, a3838^0'=a3838^post_3, a4343^0'=a4343^post_3, a4545^0'=a4545^post_3, a77^0'=a77^post_3, b22^0'=b22^post_3, b2626^0'=b2626^post_3, b2929^0'=b2929^post_3, b3333^0'=b3333^post_3, b3535^0'=b3535^post_3, i^0'=i^post_3, i___01313^0'=i___01313^post_3, i___01717^0'=i___01717^post_3, i___02020^0'=i___02020^post_3, i___02424^0'=i___02424^post_3, i___04040^0'=i___04040^post_3, i___04747^0'=i___04747^post_3, i___099^0'=i___099^post_3, ioA^0'=ioA^post_3, ioR^0'=ioR^post_3, k1^0'=k1^post_3, k2^0'=k2^post_3, k3^0'=k3^post_3, k4^0'=k4^post_3, k5^0'=k5^post_3, keA^0'=keA^post_3, keR^0'=keR^post_3, ntStatus^0'=ntStatus^post_3, pIrb^0'=pIrb^post_3, phi_io_compl^0'=phi_io_compl^post_3, phi_nSUC_ret^0'=phi_nSUC_ret^post_3, prevCancel^0'=prevCancel^post_3, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_3, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_3, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_3, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_3, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_3, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_3, [ AsyncAddressData^0<=0 && AsyncAddressData^0==AsyncAddressData^post_3 && BusResetIrp^0==BusResetIrp^post_3 && CromData^0==CromData^post_3 && DeviceObject^0==DeviceObject^post_3 && Irp^0==Irp^post_3 && Irql^0==Irql^post_3 && IsochDetachData^0==IsochDetachData^post_3 && IsochResourceData^0==IsochResourceData^post_3 && ResourceIrp^0==ResourceIrp^post_3 && StackSize^0==StackSize^post_3 && __rho_10_^0==__rho_10_^post_3 && __rho_11_^0==__rho_11_^post_3 && __rho_12_^0==__rho_12_^post_3 && __rho_1_^0==__rho_1_^post_3 && __rho_2_^0==__rho_2_^post_3 && __rho_3_^0==__rho_3_^post_3 && __rho_4_^0==__rho_4_^post_3 && __rho_5_^0==__rho_5_^post_3 && __rho_666_^0==__rho_666_^post_3 && __rho_7_^0==__rho_7_^post_3 && __rho_8_^0==__rho_8_^post_3 && __rho_9_^0==__rho_9_^post_3 && a11^0==a11^post_3 && a1818^0==a1818^post_3 && a2525^0==a2525^post_3 && a2828^0==a2828^post_3 && a3131^0==a3131^post_3 && a3232^0==a3232^post_3 && a3434^0==a3434^post_3 && a3737^0==a3737^post_3 && a3838^0==a3838^post_3 && a4343^0==a4343^post_3 && a4545^0==a4545^post_3 && a77^0==a77^post_3 && b22^0==b22^post_3 && b2626^0==b2626^post_3 && b2929^0==b2929^post_3 && b3333^0==b3333^post_3 && b3535^0==b3535^post_3 && i^0==i^post_3 && i___01313^0==i___01313^post_3 && i___01717^0==i___01717^post_3 && i___02020^0==i___02020^post_3 && i___02424^0==i___02424^post_3 && i___04040^0==i___04040^post_3 && i___04747^0==i___04747^post_3 && i___099^0==i___099^post_3 && ioA^0==ioA^post_3 && ioR^0==ioR^post_3 && k1^0==k1^post_3 && k2^0==k2^post_3 && k3^0==k3^post_3 && k4^0==k4^post_3 && k5^0==k5^post_3 && keA^0==keA^post_3 && keR^0==keR^post_3 && ntStatus^0==ntStatus^post_3 && pIrb^0==pIrb^post_3 && phi_io_compl^0==phi_io_compl^post_3 && phi_nSUC_ret^0==phi_nSUC_ret^post_3 && prevCancel^0==prevCancel^post_3 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_3 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_3 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_3 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_3 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_3 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_3 ], cost: 1
      3: l3 -> l4 : AsyncAddressData^0'=AsyncAddressData^post_4, BusResetIrp^0'=BusResetIrp^post_4, CromData^0'=CromData^post_4, DeviceObject^0'=DeviceObject^post_4, Irp^0'=Irp^post_4, Irql^0'=Irql^post_4, IsochDetachData^0'=IsochDetachData^post_4, IsochResourceData^0'=IsochResourceData^post_4, ResourceIrp^0'=ResourceIrp^post_4, StackSize^0'=StackSize^post_4, __rho_10_^0'=__rho_10_^post_4, __rho_11_^0'=__rho_11_^post_4, __rho_12_^0'=__rho_12_^post_4, __rho_1_^0'=__rho_1_^post_4, __rho_2_^0'=__rho_2_^post_4, __rho_3_^0'=__rho_3_^post_4, __rho_4_^0'=__rho_4_^post_4, __rho_5_^0'=__rho_5_^post_4, __rho_666_^0'=__rho_666_^post_4, __rho_7_^0'=__rho_7_^post_4, __rho_8_^0'=__rho_8_^post_4, __rho_9_^0'=__rho_9_^post_4, a11^0'=a11^post_4, a1818^0'=a1818^post_4, a2525^0'=a2525^post_4, a2828^0'=a2828^post_4, a3131^0'=a3131^post_4, a3232^0'=a3232^post_4, a3434^0'=a3434^post_4, a3737^0'=a3737^post_4, a3838^0'=a3838^post_4, a4343^0'=a4343^post_4, a4545^0'=a4545^post_4, a77^0'=a77^post_4, b22^0'=b22^post_4, b2626^0'=b2626^post_4, b2929^0'=b2929^post_4, b3333^0'=b3333^post_4, b3535^0'=b3535^post_4, i^0'=i^post_4, i___01313^0'=i___01313^post_4, i___01717^0'=i___01717^post_4, i___02020^0'=i___02020^post_4, i___02424^0'=i___02424^post_4, i___04040^0'=i___04040^post_4, i___04747^0'=i___04747^post_4, i___099^0'=i___099^post_4, ioA^0'=ioA^post_4, ioR^0'=ioR^post_4, k1^0'=k1^post_4, k2^0'=k2^post_4, k3^0'=k3^post_4, k4^0'=k4^post_4, k5^0'=k5^post_4, keA^0'=keA^post_4, keR^0'=keR^post_4, ntStatus^0'=ntStatus^post_4, pIrb^0'=pIrb^post_4, phi_io_compl^0'=phi_io_compl^post_4, phi_nSUC_ret^0'=phi_nSUC_ret^post_4, prevCancel^0'=prevCancel^post_4, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_4, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_4, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_4, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_4, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_4, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_4, [ 1<=AsyncAddressData^0 && AsyncAddressData^0==AsyncAddressData^post_4 && BusResetIrp^0==BusResetIrp^post_4 && CromData^0==CromData^post_4 && DeviceObject^0==DeviceObject^post_4 && Irp^0==Irp^post_4 && Irql^0==Irql^post_4 && IsochDetachData^0==IsochDetachData^post_4 && IsochResourceData^0==IsochResourceData^post_4 && ResourceIrp^0==ResourceIrp^post_4 && StackSize^0==StackSize^post_4 && __rho_10_^0==__rho_10_^post_4 && __rho_11_^0==__rho_11_^post_4 && __rho_12_^0==__rho_12_^post_4 && __rho_1_^0==__rho_1_^post_4 && __rho_2_^0==__rho_2_^post_4 && __rho_3_^0==__rho_3_^post_4 && __rho_4_^0==__rho_4_^post_4 && __rho_5_^0==__rho_5_^post_4 && __rho_666_^0==__rho_666_^post_4 && __rho_7_^0==__rho_7_^post_4 && __rho_8_^0==__rho_8_^post_4 && __rho_9_^0==__rho_9_^post_4 && a11^0==a11^post_4 && a1818^0==a1818^post_4 && a2525^0==a2525^post_4 && a2828^0==a2828^post_4 && a3131^0==a3131^post_4 && a3232^0==a3232^post_4 && a3434^0==a3434^post_4 && a3737^0==a3737^post_4 && a3838^0==a3838^post_4 && a4343^0==a4343^post_4 && a4545^0==a4545^post_4 && a77^0==a77^post_4 && b22^0==b22^post_4 && b2626^0==b2626^post_4 && b2929^0==b2929^post_4 && b3333^0==b3333^post_4 && b3535^0==b3535^post_4 && i^0==i^post_4 && i___01313^0==i___01313^post_4 && i___01717^0==i___01717^post_4 && i___02020^0==i___02020^post_4 && i___02424^0==i___02424^post_4 && i___04040^0==i___04040^post_4 && i___04747^0==i___04747^post_4 && i___099^0==i___099^post_4 && ioA^0==ioA^post_4 && ioR^0==ioR^post_4 && k1^0==k1^post_4 && k2^0==k2^post_4 && k3^0==k3^post_4 && k4^0==k4^post_4 && k5^0==k5^post_4 && keA^0==keA^post_4 && keR^0==keR^post_4 && ntStatus^0==ntStatus^post_4 && pIrb^0==pIrb^post_4 && phi_io_compl^0==phi_io_compl^post_4 && phi_nSUC_ret^0==phi_nSUC_ret^post_4 && prevCancel^0==prevCancel^post_4 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_4 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_4 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_4 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_4 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_4 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_4 ], cost: 1
     15: l4 -> l12 : AsyncAddressData^0'=AsyncAddressData^post_16, BusResetIrp^0'=BusResetIrp^post_16, CromData^0'=CromData^post_16, DeviceObject^0'=DeviceObject^post_16, Irp^0'=Irp^post_16, Irql^0'=Irql^post_16, IsochDetachData^0'=IsochDetachData^post_16, IsochResourceData^0'=IsochResourceData^post_16, ResourceIrp^0'=ResourceIrp^post_16, StackSize^0'=StackSize^post_16, __rho_10_^0'=__rho_10_^post_16, __rho_11_^0'=__rho_11_^post_16, __rho_12_^0'=__rho_12_^post_16, __rho_1_^0'=__rho_1_^post_16, __rho_2_^0'=__rho_2_^post_16, __rho_3_^0'=__rho_3_^post_16, __rho_4_^0'=__rho_4_^post_16, __rho_5_^0'=__rho_5_^post_16, __rho_666_^0'=__rho_666_^post_16, __rho_7_^0'=__rho_7_^post_16, __rho_8_^0'=__rho_8_^post_16, __rho_9_^0'=__rho_9_^post_16, a11^0'=a11^post_16, a1818^0'=a1818^post_16, a2525^0'=a2525^post_16, a2828^0'=a2828^post_16, a3131^0'=a3131^post_16, a3232^0'=a3232^post_16, a3434^0'=a3434^post_16, a3737^0'=a3737^post_16, a3838^0'=a3838^post_16, a4343^0'=a4343^post_16, a4545^0'=a4545^post_16, a77^0'=a77^post_16, b22^0'=b22^post_16, b2626^0'=b2626^post_16, b2929^0'=b2929^post_16, b3333^0'=b3333^post_16, b3535^0'=b3535^post_16, i^0'=i^post_16, i___01313^0'=i___01313^post_16, i___01717^0'=i___01717^post_16, i___02020^0'=i___02020^post_16, i___02424^0'=i___02424^post_16, i___04040^0'=i___04040^post_16, i___04747^0'=i___04747^post_16, i___099^0'=i___099^post_16, ioA^0'=ioA^post_16, ioR^0'=ioR^post_16, k1^0'=k1^post_16, k2^0'=k2^post_16, k3^0'=k3^post_16, k4^0'=k4^post_16, k5^0'=k5^post_16, keA^0'=keA^post_16, keR^0'=keR^post_16, ntStatus^0'=ntStatus^post_16, pIrb^0'=pIrb^post_16, phi_io_compl^0'=phi_io_compl^post_16, phi_nSUC_ret^0'=phi_nSUC_ret^post_16, prevCancel^0'=prevCancel^post_16, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_16, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_16, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_16, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_16, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_16, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_16, [ AsyncAddressData^0==AsyncAddressData^post_16 && BusResetIrp^0==BusResetIrp^post_16 && CromData^0==CromData^post_16 && DeviceObject^0==DeviceObject^post_16 && Irp^0==Irp^post_16 && Irql^0==Irql^post_16 && IsochDetachData^0==IsochDetachData^post_16 && IsochResourceData^0==IsochResourceData^post_16 && ResourceIrp^0==ResourceIrp^post_16 && StackSize^0==StackSize^post_16 && __rho_10_^0==__rho_10_^post_16 && __rho_11_^0==__rho_11_^post_16 && __rho_12_^0==__rho_12_^post_16 && __rho_1_^0==__rho_1_^post_16 && __rho_2_^0==__rho_2_^post_16 && __rho_3_^0==__rho_3_^post_16 && __rho_4_^0==__rho_4_^post_16 && __rho_5_^0==__rho_5_^post_16 && __rho_666_^0==__rho_666_^post_16 && __rho_7_^0==__rho_7_^post_16 && __rho_8_^0==__rho_8_^post_16 && __rho_9_^0==__rho_9_^post_16 && a11^0==a11^post_16 && a1818^0==a1818^post_16 && a2525^0==a2525^post_16 && a2828^0==a2828^post_16 && a3131^0==a3131^post_16 && a3232^0==a3232^post_16 && a3434^0==a3434^post_16 && a3737^0==a3737^post_16 && a3838^0==a3838^post_16 && a4343^0==a4343^post_16 && a4545^0==a4545^post_16 && a77^0==a77^post_16 && b22^0==b22^post_16 && b2626^0==b2626^post_16 && b2929^0==b2929^post_16 && b3333^0==b3333^post_16 && b3535^0==b3535^post_16 && i^0==i^post_16 && i___01313^0==i___01313^post_16 && i___01717^0==i___01717^post_16 && i___02020^0==i___02020^post_16 && i___02424^0==i___02424^post_16 && i___04040^0==i___04040^post_16 && i___04747^0==i___04747^post_16 && i___099^0==i___099^post_16 && ioA^0==ioA^post_16 && ioR^0==ioR^post_16 && k1^0==k1^post_16 && k2^0==k2^post_16 && k3^0==k3^post_16 && k4^0==k4^post_16 && k5^0==k5^post_16 && keA^0==keA^post_16 && keR^0==keR^post_16 && ntStatus^0==ntStatus^post_16 && pIrb^0==pIrb^post_16 && phi_io_compl^0==phi_io_compl^post_16 && phi_nSUC_ret^0==phi_nSUC_ret^post_16 && prevCancel^0==prevCancel^post_16 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_16 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_16 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_16 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_16 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_16 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_16 ], cost: 1
      4: l5 -> l3 : AsyncAddressData^0'=AsyncAddressData^post_5, BusResetIrp^0'=BusResetIrp^post_5, CromData^0'=CromData^post_5, DeviceObject^0'=DeviceObject^post_5, Irp^0'=Irp^post_5, Irql^0'=Irql^post_5, IsochDetachData^0'=IsochDetachData^post_5, IsochResourceData^0'=IsochResourceData^post_5, ResourceIrp^0'=ResourceIrp^post_5, StackSize^0'=StackSize^post_5, __rho_10_^0'=__rho_10_^post_5, __rho_11_^0'=__rho_11_^post_5, __rho_12_^0'=__rho_12_^post_5, __rho_1_^0'=__rho_1_^post_5, __rho_2_^0'=__rho_2_^post_5, __rho_3_^0'=__rho_3_^post_5, __rho_4_^0'=__rho_4_^post_5, __rho_5_^0'=__rho_5_^post_5, __rho_666_^0'=__rho_666_^post_5, __rho_7_^0'=__rho_7_^post_5, __rho_8_^0'=__rho_8_^post_5, __rho_9_^0'=__rho_9_^post_5, a11^0'=a11^post_5, a1818^0'=a1818^post_5, a2525^0'=a2525^post_5, a2828^0'=a2828^post_5, a3131^0'=a3131^post_5, a3232^0'=a3232^post_5, a3434^0'=a3434^post_5, a3737^0'=a3737^post_5, a3838^0'=a3838^post_5, a4343^0'=a4343^post_5, a4545^0'=a4545^post_5, a77^0'=a77^post_5, b22^0'=b22^post_5, b2626^0'=b2626^post_5, b2929^0'=b2929^post_5, b3333^0'=b3333^post_5, b3535^0'=b3535^post_5, i^0'=i^post_5, i___01313^0'=i___01313^post_5, i___01717^0'=i___01717^post_5, i___02020^0'=i___02020^post_5, i___02424^0'=i___02424^post_5, i___04040^0'=i___04040^post_5, i___04747^0'=i___04747^post_5, i___099^0'=i___099^post_5, ioA^0'=ioA^post_5, ioR^0'=ioR^post_5, k1^0'=k1^post_5, k2^0'=k2^post_5, k3^0'=k3^post_5, k4^0'=k4^post_5, k5^0'=k5^post_5, keA^0'=keA^post_5, keR^0'=keR^post_5, ntStatus^0'=ntStatus^post_5, pIrb^0'=pIrb^post_5, phi_io_compl^0'=phi_io_compl^post_5, phi_nSUC_ret^0'=phi_nSUC_ret^post_5, prevCancel^0'=prevCancel^post_5, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_5, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_5, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_5, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_5, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_5, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_5, [ __rho_9_^0<=0 && AsyncAddressData^0==AsyncAddressData^post_5 && BusResetIrp^0==BusResetIrp^post_5 && CromData^0==CromData^post_5 && DeviceObject^0==DeviceObject^post_5 && Irp^0==Irp^post_5 && Irql^0==Irql^post_5 && IsochDetachData^0==IsochDetachData^post_5 && IsochResourceData^0==IsochResourceData^post_5 && ResourceIrp^0==ResourceIrp^post_5 && StackSize^0==StackSize^post_5 && __rho_10_^0==__rho_10_^post_5 && __rho_11_^0==__rho_11_^post_5 && __rho_12_^0==__rho_12_^post_5 && __rho_1_^0==__rho_1_^post_5 && __rho_2_^0==__rho_2_^post_5 && __rho_3_^0==__rho_3_^post_5 && __rho_4_^0==__rho_4_^post_5 && __rho_5_^0==__rho_5_^post_5 && __rho_666_^0==__rho_666_^post_5 && __rho_7_^0==__rho_7_^post_5 && __rho_8_^0==__rho_8_^post_5 && __rho_9_^0==__rho_9_^post_5 && a11^0==a11^post_5 && a1818^0==a1818^post_5 && a2525^0==a2525^post_5 && a2828^0==a2828^post_5 && a3131^0==a3131^post_5 && a3232^0==a3232^post_5 && a3434^0==a3434^post_5 && a3737^0==a3737^post_5 && a3838^0==a3838^post_5 && a4343^0==a4343^post_5 && a4545^0==a4545^post_5 && a77^0==a77^post_5 && b22^0==b22^post_5 && b2626^0==b2626^post_5 && b2929^0==b2929^post_5 && b3333^0==b3333^post_5 && b3535^0==b3535^post_5 && i^0==i^post_5 && i___01313^0==i___01313^post_5 && i___01717^0==i___01717^post_5 && i___02020^0==i___02020^post_5 && i___02424^0==i___02424^post_5 && i___04040^0==i___04040^post_5 && i___04747^0==i___04747^post_5 && i___099^0==i___099^post_5 && ioA^0==ioA^post_5 && ioR^0==ioR^post_5 && k1^0==k1^post_5 && k2^0==k2^post_5 && k3^0==k3^post_5 && k4^0==k4^post_5 && k5^0==k5^post_5 && keA^0==keA^post_5 && keR^0==keR^post_5 && ntStatus^0==ntStatus^post_5 && pIrb^0==pIrb^post_5 && phi_io_compl^0==phi_io_compl^post_5 && phi_nSUC_ret^0==phi_nSUC_ret^post_5 && prevCancel^0==prevCancel^post_5 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_5 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_5 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_5 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_5 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_5 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_5 ], cost: 1
      5: l5 -> l3 : AsyncAddressData^0'=AsyncAddressData^post_6, BusResetIrp^0'=BusResetIrp^post_6, CromData^0'=CromData^post_6, DeviceObject^0'=DeviceObject^post_6, Irp^0'=Irp^post_6, Irql^0'=Irql^post_6, IsochDetachData^0'=IsochDetachData^post_6, IsochResourceData^0'=IsochResourceData^post_6, ResourceIrp^0'=ResourceIrp^post_6, StackSize^0'=StackSize^post_6, __rho_10_^0'=__rho_10_^post_6, __rho_11_^0'=__rho_11_^post_6, __rho_12_^0'=__rho_12_^post_6, __rho_1_^0'=__rho_1_^post_6, __rho_2_^0'=__rho_2_^post_6, __rho_3_^0'=__rho_3_^post_6, __rho_4_^0'=__rho_4_^post_6, __rho_5_^0'=__rho_5_^post_6, __rho_666_^0'=__rho_666_^post_6, __rho_7_^0'=__rho_7_^post_6, __rho_8_^0'=__rho_8_^post_6, __rho_9_^0'=__rho_9_^post_6, a11^0'=a11^post_6, a1818^0'=a1818^post_6, a2525^0'=a2525^post_6, a2828^0'=a2828^post_6, a3131^0'=a3131^post_6, a3232^0'=a3232^post_6, a3434^0'=a3434^post_6, a3737^0'=a3737^post_6, a3838^0'=a3838^post_6, a4343^0'=a4343^post_6, a4545^0'=a4545^post_6, a77^0'=a77^post_6, b22^0'=b22^post_6, b2626^0'=b2626^post_6, b2929^0'=b2929^post_6, b3333^0'=b3333^post_6, b3535^0'=b3535^post_6, i^0'=i^post_6, i___01313^0'=i___01313^post_6, i___01717^0'=i___01717^post_6, i___02020^0'=i___02020^post_6, i___02424^0'=i___02424^post_6, i___04040^0'=i___04040^post_6, i___04747^0'=i___04747^post_6, i___099^0'=i___099^post_6, ioA^0'=ioA^post_6, ioR^0'=ioR^post_6, k1^0'=k1^post_6, k2^0'=k2^post_6, k3^0'=k3^post_6, k4^0'=k4^post_6, k5^0'=k5^post_6, keA^0'=keA^post_6, keR^0'=keR^post_6, ntStatus^0'=ntStatus^post_6, pIrb^0'=pIrb^post_6, phi_io_compl^0'=phi_io_compl^post_6, phi_nSUC_ret^0'=phi_nSUC_ret^post_6, prevCancel^0'=prevCancel^post_6, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_6, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_6, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_6, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_6, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_6, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_6, [ 1<=__rho_9_^0 && AsyncAddressData^0==AsyncAddressData^post_6 && BusResetIrp^0==BusResetIrp^post_6 && CromData^0==CromData^post_6 && DeviceObject^0==DeviceObject^post_6 && Irp^0==Irp^post_6 && Irql^0==Irql^post_6 && IsochDetachData^0==IsochDetachData^post_6 && IsochResourceData^0==IsochResourceData^post_6 && ResourceIrp^0==ResourceIrp^post_6 && StackSize^0==StackSize^post_6 && __rho_10_^0==__rho_10_^post_6 && __rho_11_^0==__rho_11_^post_6 && __rho_12_^0==__rho_12_^post_6 && __rho_1_^0==__rho_1_^post_6 && __rho_2_^0==__rho_2_^post_6 && __rho_3_^0==__rho_3_^post_6 && __rho_4_^0==__rho_4_^post_6 && __rho_5_^0==__rho_5_^post_6 && __rho_666_^0==__rho_666_^post_6 && __rho_7_^0==__rho_7_^post_6 && __rho_8_^0==__rho_8_^post_6 && __rho_9_^0==__rho_9_^post_6 && a11^0==a11^post_6 && a1818^0==a1818^post_6 && a2525^0==a2525^post_6 && a2828^0==a2828^post_6 && a3131^0==a3131^post_6 && a3232^0==a3232^post_6 && a3434^0==a3434^post_6 && a3737^0==a3737^post_6 && a3838^0==a3838^post_6 && a4343^0==a4343^post_6 && a4545^0==a4545^post_6 && a77^0==a77^post_6 && b22^0==b22^post_6 && b2626^0==b2626^post_6 && b2929^0==b2929^post_6 && b3333^0==b3333^post_6 && b3535^0==b3535^post_6 && i^0==i^post_6 && i___01313^0==i___01313^post_6 && i___01717^0==i___01717^post_6 && i___02020^0==i___02020^post_6 && i___02424^0==i___02424^post_6 && i___04040^0==i___04040^post_6 && i___04747^0==i___04747^post_6 && i___099^0==i___099^post_6 && ioA^0==ioA^post_6 && ioR^0==ioR^post_6 && k1^0==k1^post_6 && k2^0==k2^post_6 && k3^0==k3^post_6 && k4^0==k4^post_6 && k5^0==k5^post_6 && keA^0==keA^post_6 && keR^0==keR^post_6 && ntStatus^0==ntStatus^post_6 && pIrb^0==pIrb^post_6 && phi_io_compl^0==phi_io_compl^post_6 && phi_nSUC_ret^0==phi_nSUC_ret^post_6 && prevCancel^0==prevCancel^post_6 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_6 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_6 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_6 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_6 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_6 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_6 ], cost: 1
      6: l6 -> l5 : AsyncAddressData^0'=AsyncAddressData^post_7, BusResetIrp^0'=BusResetIrp^post_7, CromData^0'=CromData^post_7, DeviceObject^0'=DeviceObject^post_7, Irp^0'=Irp^post_7, Irql^0'=Irql^post_7, IsochDetachData^0'=IsochDetachData^post_7, IsochResourceData^0'=IsochResourceData^post_7, ResourceIrp^0'=ResourceIrp^post_7, StackSize^0'=StackSize^post_7, __rho_10_^0'=__rho_10_^post_7, __rho_11_^0'=__rho_11_^post_7, __rho_12_^0'=__rho_12_^post_7, __rho_1_^0'=__rho_1_^post_7, __rho_2_^0'=__rho_2_^post_7, __rho_3_^0'=__rho_3_^post_7, __rho_4_^0'=__rho_4_^post_7, __rho_5_^0'=__rho_5_^post_7, __rho_666_^0'=__rho_666_^post_7, __rho_7_^0'=__rho_7_^post_7, __rho_8_^0'=__rho_8_^post_7, __rho_9_^0'=__rho_9_^post_7, a11^0'=a11^post_7, a1818^0'=a1818^post_7, a2525^0'=a2525^post_7, a2828^0'=a2828^post_7, a3131^0'=a3131^post_7, a3232^0'=a3232^post_7, a3434^0'=a3434^post_7, a3737^0'=a3737^post_7, a3838^0'=a3838^post_7, a4343^0'=a4343^post_7, a4545^0'=a4545^post_7, a77^0'=a77^post_7, b22^0'=b22^post_7, b2626^0'=b2626^post_7, b2929^0'=b2929^post_7, b3333^0'=b3333^post_7, b3535^0'=b3535^post_7, i^0'=i^post_7, i___01313^0'=i___01313^post_7, i___01717^0'=i___01717^post_7, i___02020^0'=i___02020^post_7, i___02424^0'=i___02424^post_7, i___04040^0'=i___04040^post_7, i___04747^0'=i___04747^post_7, i___099^0'=i___099^post_7, ioA^0'=ioA^post_7, ioR^0'=ioR^post_7, k1^0'=k1^post_7, k2^0'=k2^post_7, k3^0'=k3^post_7, k4^0'=k4^post_7, k5^0'=k5^post_7, keA^0'=keA^post_7, keR^0'=keR^post_7, ntStatus^0'=ntStatus^post_7, pIrb^0'=pIrb^post_7, phi_io_compl^0'=phi_io_compl^post_7, phi_nSUC_ret^0'=phi_nSUC_ret^post_7, prevCancel^0'=prevCancel^post_7, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_7, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_7, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_7, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_7, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_7, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_7, [ __rho_9_^post_7==__rho_9_^post_7 && AsyncAddressData^0==AsyncAddressData^post_7 && BusResetIrp^0==BusResetIrp^post_7 && CromData^0==CromData^post_7 && DeviceObject^0==DeviceObject^post_7 && Irp^0==Irp^post_7 && Irql^0==Irql^post_7 && IsochDetachData^0==IsochDetachData^post_7 && IsochResourceData^0==IsochResourceData^post_7 && ResourceIrp^0==ResourceIrp^post_7 && StackSize^0==StackSize^post_7 && __rho_10_^0==__rho_10_^post_7 && __rho_11_^0==__rho_11_^post_7 && __rho_12_^0==__rho_12_^post_7 && __rho_1_^0==__rho_1_^post_7 && __rho_2_^0==__rho_2_^post_7 && __rho_3_^0==__rho_3_^post_7 && __rho_4_^0==__rho_4_^post_7 && __rho_5_^0==__rho_5_^post_7 && __rho_666_^0==__rho_666_^post_7 && __rho_7_^0==__rho_7_^post_7 && __rho_8_^0==__rho_8_^post_7 && a11^0==a11^post_7 && a1818^0==a1818^post_7 && a2525^0==a2525^post_7 && a2828^0==a2828^post_7 && a3131^0==a3131^post_7 && a3232^0==a3232^post_7 && a3434^0==a3434^post_7 && a3737^0==a3737^post_7 && a3838^0==a3838^post_7 && a4343^0==a4343^post_7 && a4545^0==a4545^post_7 && a77^0==a77^post_7 && b22^0==b22^post_7 && b2626^0==b2626^post_7 && b2929^0==b2929^post_7 && b3333^0==b3333^post_7 && b3535^0==b3535^post_7 && i^0==i^post_7 && i___01313^0==i___01313^post_7 && i___01717^0==i___01717^post_7 && i___02020^0==i___02020^post_7 && i___02424^0==i___02424^post_7 && i___04040^0==i___04040^post_7 && i___04747^0==i___04747^post_7 && i___099^0==i___099^post_7 && ioA^0==ioA^post_7 && ioR^0==ioR^post_7 && k1^0==k1^post_7 && k2^0==k2^post_7 && k3^0==k3^post_7 && k4^0==k4^post_7 && k5^0==k5^post_7 && keA^0==keA^post_7 && keR^0==keR^post_7 && ntStatus^0==ntStatus^post_7 && pIrb^0==pIrb^post_7 && phi_io_compl^0==phi_io_compl^post_7 && phi_nSUC_ret^0==phi_nSUC_ret^post_7 && prevCancel^0==prevCancel^post_7 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_7 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_7 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_7 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_7 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_7 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_7 ], cost: 1
      7: l7 -> l6 : AsyncAddressData^0'=AsyncAddressData^post_8, BusResetIrp^0'=BusResetIrp^post_8, CromData^0'=CromData^post_8, DeviceObject^0'=DeviceObject^post_8, Irp^0'=Irp^post_8, Irql^0'=Irql^post_8, IsochDetachData^0'=IsochDetachData^post_8, IsochResourceData^0'=IsochResourceData^post_8, ResourceIrp^0'=ResourceIrp^post_8, StackSize^0'=StackSize^post_8, __rho_10_^0'=__rho_10_^post_8, __rho_11_^0'=__rho_11_^post_8, __rho_12_^0'=__rho_12_^post_8, __rho_1_^0'=__rho_1_^post_8, __rho_2_^0'=__rho_2_^post_8, __rho_3_^0'=__rho_3_^post_8, __rho_4_^0'=__rho_4_^post_8, __rho_5_^0'=__rho_5_^post_8, __rho_666_^0'=__rho_666_^post_8, __rho_7_^0'=__rho_7_^post_8, __rho_8_^0'=__rho_8_^post_8, __rho_9_^0'=__rho_9_^post_8, a11^0'=a11^post_8, a1818^0'=a1818^post_8, a2525^0'=a2525^post_8, a2828^0'=a2828^post_8, a3131^0'=a3131^post_8, a3232^0'=a3232^post_8, a3434^0'=a3434^post_8, a3737^0'=a3737^post_8, a3838^0'=a3838^post_8, a4343^0'=a4343^post_8, a4545^0'=a4545^post_8, a77^0'=a77^post_8, b22^0'=b22^post_8, b2626^0'=b2626^post_8, b2929^0'=b2929^post_8, b3333^0'=b3333^post_8, b3535^0'=b3535^post_8, i^0'=i^post_8, i___01313^0'=i___01313^post_8, i___01717^0'=i___01717^post_8, i___02020^0'=i___02020^post_8, i___02424^0'=i___02424^post_8, i___04040^0'=i___04040^post_8, i___04747^0'=i___04747^post_8, i___099^0'=i___099^post_8, ioA^0'=ioA^post_8, ioR^0'=ioR^post_8, k1^0'=k1^post_8, k2^0'=k2^post_8, k3^0'=k3^post_8, k4^0'=k4^post_8, k5^0'=k5^post_8, keA^0'=keA^post_8, keR^0'=keR^post_8, ntStatus^0'=ntStatus^post_8, pIrb^0'=pIrb^post_8, phi_io_compl^0'=phi_io_compl^post_8, phi_nSUC_ret^0'=phi_nSUC_ret^post_8, prevCancel^0'=prevCancel^post_8, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_8, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_8, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_8, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_8, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_8, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_8, [ __rho_8_^0<=0 && AsyncAddressData^0==AsyncAddressData^post_8 && BusResetIrp^0==BusResetIrp^post_8 && CromData^0==CromData^post_8 && DeviceObject^0==DeviceObject^post_8 && Irp^0==Irp^post_8 && Irql^0==Irql^post_8 && IsochDetachData^0==IsochDetachData^post_8 && IsochResourceData^0==IsochResourceData^post_8 && ResourceIrp^0==ResourceIrp^post_8 && StackSize^0==StackSize^post_8 && __rho_10_^0==__rho_10_^post_8 && __rho_11_^0==__rho_11_^post_8 && __rho_12_^0==__rho_12_^post_8 && __rho_1_^0==__rho_1_^post_8 && __rho_2_^0==__rho_2_^post_8 && __rho_3_^0==__rho_3_^post_8 && __rho_4_^0==__rho_4_^post_8 && __rho_5_^0==__rho_5_^post_8 && __rho_666_^0==__rho_666_^post_8 && __rho_7_^0==__rho_7_^post_8 && __rho_8_^0==__rho_8_^post_8 && __rho_9_^0==__rho_9_^post_8 && a11^0==a11^post_8 && a1818^0==a1818^post_8 && a2525^0==a2525^post_8 && a2828^0==a2828^post_8 && a3131^0==a3131^post_8 && a3232^0==a3232^post_8 && a3434^0==a3434^post_8 && a3737^0==a3737^post_8 && a3838^0==a3838^post_8 && a4343^0==a4343^post_8 && a4545^0==a4545^post_8 && a77^0==a77^post_8 && b22^0==b22^post_8 && b2626^0==b2626^post_8 && b2929^0==b2929^post_8 && b3333^0==b3333^post_8 && b3535^0==b3535^post_8 && i^0==i^post_8 && i___01313^0==i___01313^post_8 && i___01717^0==i___01717^post_8 && i___02020^0==i___02020^post_8 && i___02424^0==i___02424^post_8 && i___04040^0==i___04040^post_8 && i___04747^0==i___04747^post_8 && i___099^0==i___099^post_8 && ioA^0==ioA^post_8 && ioR^0==ioR^post_8 && k1^0==k1^post_8 && k2^0==k2^post_8 && k3^0==k3^post_8 && k4^0==k4^post_8 && k5^0==k5^post_8 && keA^0==keA^post_8 && keR^0==keR^post_8 && ntStatus^0==ntStatus^post_8 && pIrb^0==pIrb^post_8 && phi_io_compl^0==phi_io_compl^post_8 && phi_nSUC_ret^0==phi_nSUC_ret^post_8 && prevCancel^0==prevCancel^post_8 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_8 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_8 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_8 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_8 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_8 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_8 ], cost: 1
      8: l7 -> l6 : AsyncAddressData^0'=AsyncAddressData^post_9, BusResetIrp^0'=BusResetIrp^post_9, CromData^0'=CromData^post_9, DeviceObject^0'=DeviceObject^post_9, Irp^0'=Irp^post_9, Irql^0'=Irql^post_9, IsochDetachData^0'=IsochDetachData^post_9, IsochResourceData^0'=IsochResourceData^post_9, ResourceIrp^0'=ResourceIrp^post_9, StackSize^0'=StackSize^post_9, __rho_10_^0'=__rho_10_^post_9, __rho_11_^0'=__rho_11_^post_9, __rho_12_^0'=__rho_12_^post_9, __rho_1_^0'=__rho_1_^post_9, __rho_2_^0'=__rho_2_^post_9, __rho_3_^0'=__rho_3_^post_9, __rho_4_^0'=__rho_4_^post_9, __rho_5_^0'=__rho_5_^post_9, __rho_666_^0'=__rho_666_^post_9, __rho_7_^0'=__rho_7_^post_9, __rho_8_^0'=__rho_8_^post_9, __rho_9_^0'=__rho_9_^post_9, a11^0'=a11^post_9, a1818^0'=a1818^post_9, a2525^0'=a2525^post_9, a2828^0'=a2828^post_9, a3131^0'=a3131^post_9, a3232^0'=a3232^post_9, a3434^0'=a3434^post_9, a3737^0'=a3737^post_9, a3838^0'=a3838^post_9, a4343^0'=a4343^post_9, a4545^0'=a4545^post_9, a77^0'=a77^post_9, b22^0'=b22^post_9, b2626^0'=b2626^post_9, b2929^0'=b2929^post_9, b3333^0'=b3333^post_9, b3535^0'=b3535^post_9, i^0'=i^post_9, i___01313^0'=i___01313^post_9, i___01717^0'=i___01717^post_9, i___02020^0'=i___02020^post_9, i___02424^0'=i___02424^post_9, i___04040^0'=i___04040^post_9, i___04747^0'=i___04747^post_9, i___099^0'=i___099^post_9, ioA^0'=ioA^post_9, ioR^0'=ioR^post_9, k1^0'=k1^post_9, k2^0'=k2^post_9, k3^0'=k3^post_9, k4^0'=k4^post_9, k5^0'=k5^post_9, keA^0'=keA^post_9, keR^0'=keR^post_9, ntStatus^0'=ntStatus^post_9, pIrb^0'=pIrb^post_9, phi_io_compl^0'=phi_io_compl^post_9, phi_nSUC_ret^0'=phi_nSUC_ret^post_9, prevCancel^0'=prevCancel^post_9, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_9, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_9, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_9, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_9, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_9, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_9, [ 1<=__rho_8_^0 && AsyncAddressData^0==AsyncAddressData^post_9 && BusResetIrp^0==BusResetIrp^post_9 && CromData^0==CromData^post_9 && DeviceObject^0==DeviceObject^post_9 && Irp^0==Irp^post_9 && Irql^0==Irql^post_9 && IsochDetachData^0==IsochDetachData^post_9 && IsochResourceData^0==IsochResourceData^post_9 && ResourceIrp^0==ResourceIrp^post_9 && StackSize^0==StackSize^post_9 && __rho_10_^0==__rho_10_^post_9 && __rho_11_^0==__rho_11_^post_9 && __rho_12_^0==__rho_12_^post_9 && __rho_1_^0==__rho_1_^post_9 && __rho_2_^0==__rho_2_^post_9 && __rho_3_^0==__rho_3_^post_9 && __rho_4_^0==__rho_4_^post_9 && __rho_5_^0==__rho_5_^post_9 && __rho_666_^0==__rho_666_^post_9 && __rho_7_^0==__rho_7_^post_9 && __rho_8_^0==__rho_8_^post_9 && __rho_9_^0==__rho_9_^post_9 && a11^0==a11^post_9 && a1818^0==a1818^post_9 && a2525^0==a2525^post_9 && a2828^0==a2828^post_9 && a3131^0==a3131^post_9 && a3232^0==a3232^post_9 && a3434^0==a3434^post_9 && a3737^0==a3737^post_9 && a3838^0==a3838^post_9 && a4343^0==a4343^post_9 && a4545^0==a4545^post_9 && a77^0==a77^post_9 && b22^0==b22^post_9 && b2626^0==b2626^post_9 && b2929^0==b2929^post_9 && b3333^0==b3333^post_9 && b3535^0==b3535^post_9 && i^0==i^post_9 && i___01313^0==i___01313^post_9 && i___01717^0==i___01717^post_9 && i___02020^0==i___02020^post_9 && i___02424^0==i___02424^post_9 && i___04040^0==i___04040^post_9 && i___04747^0==i___04747^post_9 && i___099^0==i___099^post_9 && ioA^0==ioA^post_9 && ioR^0==ioR^post_9 && k1^0==k1^post_9 && k2^0==k2^post_9 && k3^0==k3^post_9 && k4^0==k4^post_9 && k5^0==k5^post_9 && keA^0==keA^post_9 && keR^0==keR^post_9 && ntStatus^0==ntStatus^post_9 && pIrb^0==pIrb^post_9 && phi_io_compl^0==phi_io_compl^post_9 && phi_nSUC_ret^0==phi_nSUC_ret^post_9 && prevCancel^0==prevCancel^post_9 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_9 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_9 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_9 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_9 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_9 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_9 ], cost: 1
      9: l8 -> l7 : AsyncAddressData^0'=AsyncAddressData^post_10, BusResetIrp^0'=BusResetIrp^post_10, CromData^0'=CromData^post_10, DeviceObject^0'=DeviceObject^post_10, Irp^0'=Irp^post_10, Irql^0'=Irql^post_10, IsochDetachData^0'=IsochDetachData^post_10, IsochResourceData^0'=IsochResourceData^post_10, ResourceIrp^0'=ResourceIrp^post_10, StackSize^0'=StackSize^post_10, __rho_10_^0'=__rho_10_^post_10, __rho_11_^0'=__rho_11_^post_10, __rho_12_^0'=__rho_12_^post_10, __rho_1_^0'=__rho_1_^post_10, __rho_2_^0'=__rho_2_^post_10, __rho_3_^0'=__rho_3_^post_10, __rho_4_^0'=__rho_4_^post_10, __rho_5_^0'=__rho_5_^post_10, __rho_666_^0'=__rho_666_^post_10, __rho_7_^0'=__rho_7_^post_10, __rho_8_^0'=__rho_8_^post_10, __rho_9_^0'=__rho_9_^post_10, a11^0'=a11^post_10, a1818^0'=a1818^post_10, a2525^0'=a2525^post_10, a2828^0'=a2828^post_10, a3131^0'=a3131^post_10, a3232^0'=a3232^post_10, a3434^0'=a3434^post_10, a3737^0'=a3737^post_10, a3838^0'=a3838^post_10, a4343^0'=a4343^post_10, a4545^0'=a4545^post_10, a77^0'=a77^post_10, b22^0'=b22^post_10, b2626^0'=b2626^post_10, b2929^0'=b2929^post_10, b3333^0'=b3333^post_10, b3535^0'=b3535^post_10, i^0'=i^post_10, i___01313^0'=i___01313^post_10, i___01717^0'=i___01717^post_10, i___02020^0'=i___02020^post_10, i___02424^0'=i___02424^post_10, i___04040^0'=i___04040^post_10, i___04747^0'=i___04747^post_10, i___099^0'=i___099^post_10, ioA^0'=ioA^post_10, ioR^0'=ioR^post_10, k1^0'=k1^post_10, k2^0'=k2^post_10, k3^0'=k3^post_10, k4^0'=k4^post_10, k5^0'=k5^post_10, keA^0'=keA^post_10, keR^0'=keR^post_10, ntStatus^0'=ntStatus^post_10, pIrb^0'=pIrb^post_10, phi_io_compl^0'=phi_io_compl^post_10, phi_nSUC_ret^0'=phi_nSUC_ret^post_10, prevCancel^0'=prevCancel^post_10, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_10, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_10, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_10, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_10, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_10, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_10, [ __rho_8_^post_10==__rho_8_^post_10 && AsyncAddressData^0==AsyncAddressData^post_10 && BusResetIrp^0==BusResetIrp^post_10 && CromData^0==CromData^post_10 && DeviceObject^0==DeviceObject^post_10 && Irp^0==Irp^post_10 && Irql^0==Irql^post_10 && IsochDetachData^0==IsochDetachData^post_10 && IsochResourceData^0==IsochResourceData^post_10 && ResourceIrp^0==ResourceIrp^post_10 && StackSize^0==StackSize^post_10 && __rho_10_^0==__rho_10_^post_10 && __rho_11_^0==__rho_11_^post_10 && __rho_12_^0==__rho_12_^post_10 && __rho_1_^0==__rho_1_^post_10 && __rho_2_^0==__rho_2_^post_10 && __rho_3_^0==__rho_3_^post_10 && __rho_4_^0==__rho_4_^post_10 && __rho_5_^0==__rho_5_^post_10 && __rho_666_^0==__rho_666_^post_10 && __rho_7_^0==__rho_7_^post_10 && __rho_9_^0==__rho_9_^post_10 && a11^0==a11^post_10 && a1818^0==a1818^post_10 && a2525^0==a2525^post_10 && a2828^0==a2828^post_10 && a3131^0==a3131^post_10 && a3232^0==a3232^post_10 && a3434^0==a3434^post_10 && a3737^0==a3737^post_10 && a3838^0==a3838^post_10 && a4343^0==a4343^post_10 && a4545^0==a4545^post_10 && a77^0==a77^post_10 && b22^0==b22^post_10 && b2626^0==b2626^post_10 && b2929^0==b2929^post_10 && b3333^0==b3333^post_10 && b3535^0==b3535^post_10 && i^0==i^post_10 && i___01313^0==i___01313^post_10 && i___01717^0==i___01717^post_10 && i___02020^0==i___02020^post_10 && i___02424^0==i___02424^post_10 && i___04040^0==i___04040^post_10 && i___04747^0==i___04747^post_10 && i___099^0==i___099^post_10 && ioA^0==ioA^post_10 && ioR^0==ioR^post_10 && k1^0==k1^post_10 && k2^0==k2^post_10 && k3^0==k3^post_10 && k4^0==k4^post_10 && k5^0==k5^post_10 && keA^0==keA^post_10 && keR^0==keR^post_10 && ntStatus^0==ntStatus^post_10 && pIrb^0==pIrb^post_10 && phi_io_compl^0==phi_io_compl^post_10 && phi_nSUC_ret^0==phi_nSUC_ret^post_10 && prevCancel^0==prevCancel^post_10 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_10 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_10 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_10 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_10 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_10 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_10 ], cost: 1
     10: l9 -> l8 : AsyncAddressData^0'=AsyncAddressData^post_11, BusResetIrp^0'=BusResetIrp^post_11, CromData^0'=CromData^post_11, DeviceObject^0'=DeviceObject^post_11, Irp^0'=Irp^post_11, Irql^0'=Irql^post_11, IsochDetachData^0'=IsochDetachData^post_11, IsochResourceData^0'=IsochResourceData^post_11, ResourceIrp^0'=ResourceIrp^post_11, StackSize^0'=StackSize^post_11, __rho_10_^0'=__rho_10_^post_11, __rho_11_^0'=__rho_11_^post_11, __rho_12_^0'=__rho_12_^post_11, __rho_1_^0'=__rho_1_^post_11, __rho_2_^0'=__rho_2_^post_11, __rho_3_^0'=__rho_3_^post_11, __rho_4_^0'=__rho_4_^post_11, __rho_5_^0'=__rho_5_^post_11, __rho_666_^0'=__rho_666_^post_11, __rho_7_^0'=__rho_7_^post_11, __rho_8_^0'=__rho_8_^post_11, __rho_9_^0'=__rho_9_^post_11, a11^0'=a11^post_11, a1818^0'=a1818^post_11, a2525^0'=a2525^post_11, a2828^0'=a2828^post_11, a3131^0'=a3131^post_11, a3232^0'=a3232^post_11, a3434^0'=a3434^post_11, a3737^0'=a3737^post_11, a3838^0'=a3838^post_11, a4343^0'=a4343^post_11, a4545^0'=a4545^post_11, a77^0'=a77^post_11, b22^0'=b22^post_11, b2626^0'=b2626^post_11, b2929^0'=b2929^post_11, b3333^0'=b3333^post_11, b3535^0'=b3535^post_11, i^0'=i^post_11, i___01313^0'=i___01313^post_11, i___01717^0'=i___01717^post_11, i___02020^0'=i___02020^post_11, i___02424^0'=i___02424^post_11, i___04040^0'=i___04040^post_11, i___04747^0'=i___04747^post_11, i___099^0'=i___099^post_11, ioA^0'=ioA^post_11, ioR^0'=ioR^post_11, k1^0'=k1^post_11, k2^0'=k2^post_11, k3^0'=k3^post_11, k4^0'=k4^post_11, k5^0'=k5^post_11, keA^0'=keA^post_11, keR^0'=keR^post_11, ntStatus^0'=ntStatus^post_11, pIrb^0'=pIrb^post_11, phi_io_compl^0'=phi_io_compl^post_11, phi_nSUC_ret^0'=phi_nSUC_ret^post_11, prevCancel^0'=prevCancel^post_11, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_11, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_11, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_11, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_11, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_11, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_11, [ __rho_7_^0<=0 && AsyncAddressData^0==AsyncAddressData^post_11 && BusResetIrp^0==BusResetIrp^post_11 && CromData^0==CromData^post_11 && DeviceObject^0==DeviceObject^post_11 && Irp^0==Irp^post_11 && Irql^0==Irql^post_11 && IsochDetachData^0==IsochDetachData^post_11 && IsochResourceData^0==IsochResourceData^post_11 && ResourceIrp^0==ResourceIrp^post_11 && StackSize^0==StackSize^post_11 && __rho_10_^0==__rho_10_^post_11 && __rho_11_^0==__rho_11_^post_11 && __rho_12_^0==__rho_12_^post_11 && __rho_1_^0==__rho_1_^post_11 && __rho_2_^0==__rho_2_^post_11 && __rho_3_^0==__rho_3_^post_11 && __rho_4_^0==__rho_4_^post_11 && __rho_5_^0==__rho_5_^post_11 && __rho_666_^0==__rho_666_^post_11 && __rho_7_^0==__rho_7_^post_11 && __rho_8_^0==__rho_8_^post_11 && __rho_9_^0==__rho_9_^post_11 && a11^0==a11^post_11 && a1818^0==a1818^post_11 && a2525^0==a2525^post_11 && a2828^0==a2828^post_11 && a3131^0==a3131^post_11 && a3232^0==a3232^post_11 && a3434^0==a3434^post_11 && a3737^0==a3737^post_11 && a3838^0==a3838^post_11 && a4343^0==a4343^post_11 && a4545^0==a4545^post_11 && a77^0==a77^post_11 && b22^0==b22^post_11 && b2626^0==b2626^post_11 && b2929^0==b2929^post_11 && b3333^0==b3333^post_11 && b3535^0==b3535^post_11 && i^0==i^post_11 && i___01313^0==i___01313^post_11 && i___01717^0==i___01717^post_11 && i___02020^0==i___02020^post_11 && i___02424^0==i___02424^post_11 && i___04040^0==i___04040^post_11 && i___04747^0==i___04747^post_11 && i___099^0==i___099^post_11 && ioA^0==ioA^post_11 && ioR^0==ioR^post_11 && k1^0==k1^post_11 && k2^0==k2^post_11 && k3^0==k3^post_11 && k4^0==k4^post_11 && k5^0==k5^post_11 && keA^0==keA^post_11 && keR^0==keR^post_11 && ntStatus^0==ntStatus^post_11 && pIrb^0==pIrb^post_11 && phi_io_compl^0==phi_io_compl^post_11 && phi_nSUC_ret^0==phi_nSUC_ret^post_11 && prevCancel^0==prevCancel^post_11 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_11 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_11 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_11 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_11 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_11 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_11 ], cost: 1
     11: l9 -> l8 : AsyncAddressData^0'=AsyncAddressData^post_12, BusResetIrp^0'=BusResetIrp^post_12, CromData^0'=CromData^post_12, DeviceObject^0'=DeviceObject^post_12, Irp^0'=Irp^post_12, Irql^0'=Irql^post_12, IsochDetachData^0'=IsochDetachData^post_12, IsochResourceData^0'=IsochResourceData^post_12, ResourceIrp^0'=ResourceIrp^post_12, StackSize^0'=StackSize^post_12, __rho_10_^0'=__rho_10_^post_12, __rho_11_^0'=__rho_11_^post_12, __rho_12_^0'=__rho_12_^post_12, __rho_1_^0'=__rho_1_^post_12, __rho_2_^0'=__rho_2_^post_12, __rho_3_^0'=__rho_3_^post_12, __rho_4_^0'=__rho_4_^post_12, __rho_5_^0'=__rho_5_^post_12, __rho_666_^0'=__rho_666_^post_12, __rho_7_^0'=__rho_7_^post_12, __rho_8_^0'=__rho_8_^post_12, __rho_9_^0'=__rho_9_^post_12, a11^0'=a11^post_12, a1818^0'=a1818^post_12, a2525^0'=a2525^post_12, a2828^0'=a2828^post_12, a3131^0'=a3131^post_12, a3232^0'=a3232^post_12, a3434^0'=a3434^post_12, a3737^0'=a3737^post_12, a3838^0'=a3838^post_12, a4343^0'=a4343^post_12, a4545^0'=a4545^post_12, a77^0'=a77^post_12, b22^0'=b22^post_12, b2626^0'=b2626^post_12, b2929^0'=b2929^post_12, b3333^0'=b3333^post_12, b3535^0'=b3535^post_12, i^0'=i^post_12, i___01313^0'=i___01313^post_12, i___01717^0'=i___01717^post_12, i___02020^0'=i___02020^post_12, i___02424^0'=i___02424^post_12, i___04040^0'=i___04040^post_12, i___04747^0'=i___04747^post_12, i___099^0'=i___099^post_12, ioA^0'=ioA^post_12, ioR^0'=ioR^post_12, k1^0'=k1^post_12, k2^0'=k2^post_12, k3^0'=k3^post_12, k4^0'=k4^post_12, k5^0'=k5^post_12, keA^0'=keA^post_12, keR^0'=keR^post_12, ntStatus^0'=ntStatus^post_12, pIrb^0'=pIrb^post_12, phi_io_compl^0'=phi_io_compl^post_12, phi_nSUC_ret^0'=phi_nSUC_ret^post_12, prevCancel^0'=prevCancel^post_12, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_12, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_12, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_12, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_12, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_12, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_12, [ 1<=__rho_7_^0 && AsyncAddressData^0==AsyncAddressData^post_12 && BusResetIrp^0==BusResetIrp^post_12 && CromData^0==CromData^post_12 && DeviceObject^0==DeviceObject^post_12 && Irp^0==Irp^post_12 && Irql^0==Irql^post_12 && IsochDetachData^0==IsochDetachData^post_12 && IsochResourceData^0==IsochResourceData^post_12 && ResourceIrp^0==ResourceIrp^post_12 && StackSize^0==StackSize^post_12 && __rho_10_^0==__rho_10_^post_12 && __rho_11_^0==__rho_11_^post_12 && __rho_12_^0==__rho_12_^post_12 && __rho_1_^0==__rho_1_^post_12 && __rho_2_^0==__rho_2_^post_12 && __rho_3_^0==__rho_3_^post_12 && __rho_4_^0==__rho_4_^post_12 && __rho_5_^0==__rho_5_^post_12 && __rho_666_^0==__rho_666_^post_12 && __rho_7_^0==__rho_7_^post_12 && __rho_8_^0==__rho_8_^post_12 && __rho_9_^0==__rho_9_^post_12 && a11^0==a11^post_12 && a1818^0==a1818^post_12 && a2525^0==a2525^post_12 && a2828^0==a2828^post_12 && a3131^0==a3131^post_12 && a3232^0==a3232^post_12 && a3434^0==a3434^post_12 && a3737^0==a3737^post_12 && a3838^0==a3838^post_12 && a4343^0==a4343^post_12 && a4545^0==a4545^post_12 && a77^0==a77^post_12 && b22^0==b22^post_12 && b2626^0==b2626^post_12 && b2929^0==b2929^post_12 && b3333^0==b3333^post_12 && b3535^0==b3535^post_12 && i^0==i^post_12 && i___01313^0==i___01313^post_12 && i___01717^0==i___01717^post_12 && i___02020^0==i___02020^post_12 && i___02424^0==i___02424^post_12 && i___04040^0==i___04040^post_12 && i___04747^0==i___04747^post_12 && i___099^0==i___099^post_12 && ioA^0==ioA^post_12 && ioR^0==ioR^post_12 && k1^0==k1^post_12 && k2^0==k2^post_12 && k3^0==k3^post_12 && k4^0==k4^post_12 && k5^0==k5^post_12 && keA^0==keA^post_12 && keR^0==keR^post_12 && ntStatus^0==ntStatus^post_12 && pIrb^0==pIrb^post_12 && phi_io_compl^0==phi_io_compl^post_12 && phi_nSUC_ret^0==phi_nSUC_ret^post_12 && prevCancel^0==prevCancel^post_12 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_12 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_12 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_12 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_12 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_12 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_12 ], cost: 1
     12: l10 -> l11 : AsyncAddressData^0'=AsyncAddressData^post_13, BusResetIrp^0'=BusResetIrp^post_13, CromData^0'=CromData^post_13, DeviceObject^0'=DeviceObject^post_13, Irp^0'=Irp^post_13, Irql^0'=Irql^post_13, IsochDetachData^0'=IsochDetachData^post_13, IsochResourceData^0'=IsochResourceData^post_13, ResourceIrp^0'=ResourceIrp^post_13, StackSize^0'=StackSize^post_13, __rho_10_^0'=__rho_10_^post_13, __rho_11_^0'=__rho_11_^post_13, __rho_12_^0'=__rho_12_^post_13, __rho_1_^0'=__rho_1_^post_13, __rho_2_^0'=__rho_2_^post_13, __rho_3_^0'=__rho_3_^post_13, __rho_4_^0'=__rho_4_^post_13, __rho_5_^0'=__rho_5_^post_13, __rho_666_^0'=__rho_666_^post_13, __rho_7_^0'=__rho_7_^post_13, __rho_8_^0'=__rho_8_^post_13, __rho_9_^0'=__rho_9_^post_13, a11^0'=a11^post_13, a1818^0'=a1818^post_13, a2525^0'=a2525^post_13, a2828^0'=a2828^post_13, a3131^0'=a3131^post_13, a3232^0'=a3232^post_13, a3434^0'=a3434^post_13, a3737^0'=a3737^post_13, a3838^0'=a3838^post_13, a4343^0'=a4343^post_13, a4545^0'=a4545^post_13, a77^0'=a77^post_13, b22^0'=b22^post_13, b2626^0'=b2626^post_13, b2929^0'=b2929^post_13, b3333^0'=b3333^post_13, b3535^0'=b3535^post_13, i^0'=i^post_13, i___01313^0'=i___01313^post_13, i___01717^0'=i___01717^post_13, i___02020^0'=i___02020^post_13, i___02424^0'=i___02424^post_13, i___04040^0'=i___04040^post_13, i___04747^0'=i___04747^post_13, i___099^0'=i___099^post_13, ioA^0'=ioA^post_13, ioR^0'=ioR^post_13, k1^0'=k1^post_13, k2^0'=k2^post_13, k3^0'=k3^post_13, k4^0'=k4^post_13, k5^0'=k5^post_13, keA^0'=keA^post_13, keR^0'=keR^post_13, ntStatus^0'=ntStatus^post_13, pIrb^0'=pIrb^post_13, phi_io_compl^0'=phi_io_compl^post_13, phi_nSUC_ret^0'=phi_nSUC_ret^post_13, prevCancel^0'=prevCancel^post_13, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_13, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_13, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_13, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_13, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_13, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_13, [ AsyncAddressData^0==AsyncAddressData^post_13 && BusResetIrp^0==BusResetIrp^post_13 && CromData^0==CromData^post_13 && DeviceObject^0==DeviceObject^post_13 && Irp^0==Irp^post_13 && Irql^0==Irql^post_13 && IsochDetachData^0==IsochDetachData^post_13 && IsochResourceData^0==IsochResourceData^post_13 && ResourceIrp^0==ResourceIrp^post_13 && StackSize^0==StackSize^post_13 && __rho_10_^0==__rho_10_^post_13 && __rho_11_^0==__rho_11_^post_13 && __rho_12_^0==__rho_12_^post_13 && __rho_1_^0==__rho_1_^post_13 && __rho_2_^0==__rho_2_^post_13 && __rho_3_^0==__rho_3_^post_13 && __rho_4_^0==__rho_4_^post_13 && __rho_5_^0==__rho_5_^post_13 && __rho_666_^0==__rho_666_^post_13 && __rho_7_^0==__rho_7_^post_13 && __rho_8_^0==__rho_8_^post_13 && __rho_9_^0==__rho_9_^post_13 && a11^0==a11^post_13 && a1818^0==a1818^post_13 && a2525^0==a2525^post_13 && a2828^0==a2828^post_13 && a3131^0==a3131^post_13 && a3232^0==a3232^post_13 && a3434^0==a3434^post_13 && a3737^0==a3737^post_13 && a3838^0==a3838^post_13 && a4343^0==a4343^post_13 && a4545^0==a4545^post_13 && a77^0==a77^post_13 && b22^0==b22^post_13 && b2626^0==b2626^post_13 && b2929^0==b2929^post_13 && b3333^0==b3333^post_13 && b3535^0==b3535^post_13 && i^0==i^post_13 && i___01313^0==i___01313^post_13 && i___01717^0==i___01717^post_13 && i___02020^0==i___02020^post_13 && i___02424^0==i___02424^post_13 && i___04040^0==i___04040^post_13 && i___04747^0==i___04747^post_13 && i___099^0==i___099^post_13 && ioA^0==ioA^post_13 && ioR^0==ioR^post_13 && k1^0==k1^post_13 && k2^0==k2^post_13 && k3^0==k3^post_13 && k4^0==k4^post_13 && k5^0==k5^post_13 && keA^0==keA^post_13 && keR^0==keR^post_13 && ntStatus^0==ntStatus^post_13 && pIrb^0==pIrb^post_13 && phi_io_compl^0==phi_io_compl^post_13 && phi_nSUC_ret^0==phi_nSUC_ret^post_13 && prevCancel^0==prevCancel^post_13 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_13 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_13 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_13 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_13 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_13 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_13 ], cost: 1
     26: l11 -> l18 : AsyncAddressData^0'=AsyncAddressData^post_27, BusResetIrp^0'=BusResetIrp^post_27, CromData^0'=CromData^post_27, DeviceObject^0'=DeviceObject^post_27, Irp^0'=Irp^post_27, Irql^0'=Irql^post_27, IsochDetachData^0'=IsochDetachData^post_27, IsochResourceData^0'=IsochResourceData^post_27, ResourceIrp^0'=ResourceIrp^post_27, StackSize^0'=StackSize^post_27, __rho_10_^0'=__rho_10_^post_27, __rho_11_^0'=__rho_11_^post_27, __rho_12_^0'=__rho_12_^post_27, __rho_1_^0'=__rho_1_^post_27, __rho_2_^0'=__rho_2_^post_27, __rho_3_^0'=__rho_3_^post_27, __rho_4_^0'=__rho_4_^post_27, __rho_5_^0'=__rho_5_^post_27, __rho_666_^0'=__rho_666_^post_27, __rho_7_^0'=__rho_7_^post_27, __rho_8_^0'=__rho_8_^post_27, __rho_9_^0'=__rho_9_^post_27, a11^0'=a11^post_27, a1818^0'=a1818^post_27, a2525^0'=a2525^post_27, a2828^0'=a2828^post_27, a3131^0'=a3131^post_27, a3232^0'=a3232^post_27, a3434^0'=a3434^post_27, a3737^0'=a3737^post_27, a3838^0'=a3838^post_27, a4343^0'=a4343^post_27, a4545^0'=a4545^post_27, a77^0'=a77^post_27, b22^0'=b22^post_27, b2626^0'=b2626^post_27, b2929^0'=b2929^post_27, b3333^0'=b3333^post_27, b3535^0'=b3535^post_27, i^0'=i^post_27, i___01313^0'=i___01313^post_27, i___01717^0'=i___01717^post_27, i___02020^0'=i___02020^post_27, i___02424^0'=i___02424^post_27, i___04040^0'=i___04040^post_27, i___04747^0'=i___04747^post_27, i___099^0'=i___099^post_27, ioA^0'=ioA^post_27, ioR^0'=ioR^post_27, k1^0'=k1^post_27, k2^0'=k2^post_27, k3^0'=k3^post_27, k4^0'=k4^post_27, k5^0'=k5^post_27, keA^0'=keA^post_27, keR^0'=keR^post_27, ntStatus^0'=ntStatus^post_27, pIrb^0'=pIrb^post_27, phi_io_compl^0'=phi_io_compl^post_27, phi_nSUC_ret^0'=phi_nSUC_ret^post_27, prevCancel^0'=prevCancel^post_27, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_27, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_27, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_27, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_27, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_27, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_27, [ 1<=k1^0 && CromData^post_27==CromData^post_27 && k1^post_27==-1+k1^0 && AsyncAddressData^0==AsyncAddressData^post_27 && BusResetIrp^0==BusResetIrp^post_27 && DeviceObject^0==DeviceObject^post_27 && Irp^0==Irp^post_27 && Irql^0==Irql^post_27 && IsochDetachData^0==IsochDetachData^post_27 && IsochResourceData^0==IsochResourceData^post_27 && ResourceIrp^0==ResourceIrp^post_27 && StackSize^0==StackSize^post_27 && __rho_10_^0==__rho_10_^post_27 && __rho_11_^0==__rho_11_^post_27 && __rho_12_^0==__rho_12_^post_27 && __rho_1_^0==__rho_1_^post_27 && __rho_2_^0==__rho_2_^post_27 && __rho_3_^0==__rho_3_^post_27 && __rho_4_^0==__rho_4_^post_27 && __rho_5_^0==__rho_5_^post_27 && __rho_666_^0==__rho_666_^post_27 && __rho_7_^0==__rho_7_^post_27 && __rho_8_^0==__rho_8_^post_27 && __rho_9_^0==__rho_9_^post_27 && a11^0==a11^post_27 && a1818^0==a1818^post_27 && a2525^0==a2525^post_27 && a2828^0==a2828^post_27 && a3131^0==a3131^post_27 && a3232^0==a3232^post_27 && a3434^0==a3434^post_27 && a3737^0==a3737^post_27 && a3838^0==a3838^post_27 && a4343^0==a4343^post_27 && a4545^0==a4545^post_27 && a77^0==a77^post_27 && b22^0==b22^post_27 && b2626^0==b2626^post_27 && b2929^0==b2929^post_27 && b3333^0==b3333^post_27 && b3535^0==b3535^post_27 && i^0==i^post_27 && i___01313^0==i___01313^post_27 && i___01717^0==i___01717^post_27 && i___02020^0==i___02020^post_27 && i___02424^0==i___02424^post_27 && i___04040^0==i___04040^post_27 && i___04747^0==i___04747^post_27 && i___099^0==i___099^post_27 && ioA^0==ioA^post_27 && ioR^0==ioR^post_27 && k2^0==k2^post_27 && k3^0==k3^post_27 && k4^0==k4^post_27 && k5^0==k5^post_27 && keA^0==keA^post_27 && keR^0==keR^post_27 && ntStatus^0==ntStatus^post_27 && pIrb^0==pIrb^post_27 && phi_io_compl^0==phi_io_compl^post_27 && phi_nSUC_ret^0==phi_nSUC_ret^post_27 && prevCancel^0==prevCancel^post_27 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_27 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_27 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_27 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_27 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_27 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_27 ], cost: 1
     27: l11 -> l4 : AsyncAddressData^0'=AsyncAddressData^post_28, BusResetIrp^0'=BusResetIrp^post_28, CromData^0'=CromData^post_28, DeviceObject^0'=DeviceObject^post_28, Irp^0'=Irp^post_28, Irql^0'=Irql^post_28, IsochDetachData^0'=IsochDetachData^post_28, IsochResourceData^0'=IsochResourceData^post_28, ResourceIrp^0'=ResourceIrp^post_28, StackSize^0'=StackSize^post_28, __rho_10_^0'=__rho_10_^post_28, __rho_11_^0'=__rho_11_^post_28, __rho_12_^0'=__rho_12_^post_28, __rho_1_^0'=__rho_1_^post_28, __rho_2_^0'=__rho_2_^post_28, __rho_3_^0'=__rho_3_^post_28, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_28, __rho_666_^0'=__rho_666_^post_28, __rho_7_^0'=__rho_7_^post_28, __rho_8_^0'=__rho_8_^post_28, __rho_9_^0'=__rho_9_^post_28, a11^0'=a11^post_28, a1818^0'=a1818^post_28, a2525^0'=a2525^post_28, a2828^0'=a2828^post_28, a3131^0'=a3131^post_28, a3232^0'=a3232^post_28, a3434^0'=a3434^post_28, a3737^0'=a3737^post_28, a3838^0'=a3838^post_28, a4343^0'=a4343^post_28, a4545^0'=a4545^post_28, a77^0'=a77^post_28, b22^0'=b22^post_28, b2626^0'=b2626^post_28, b2929^0'=b2929^post_28, b3333^0'=b3333^post_28, b3535^0'=b3535^post_28, i^0'=i^post_28, i___01313^0'=i___01313^post_28, i___01717^0'=i___01717^post_28, i___02020^0'=i___02020^post_28, i___02424^0'=i___02424^post_28, i___04040^0'=i___04040^post_28, i___04747^0'=i___04747^post_28, i___099^0'=i___099^post_28, ioA^0'=ioA^post_28, ioR^0'=ioR^post_28, k1^0'=k1^post_28, k2^0'=k2^post_28, k3^0'=k3^post_28, k4^0'=k4^post_28, k5^0'=k5^post_28, keA^0'=keA^post_28, keR^0'=keR^post_28, ntStatus^0'=ntStatus^post_28, pIrb^0'=pIrb^post_28, phi_io_compl^0'=phi_io_compl^post_28, phi_nSUC_ret^0'=phi_nSUC_ret^post_28, prevCancel^0'=prevCancel^post_28, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_28, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_28, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_28, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_28, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_28, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_28, [ k1^0<=0 && i___099^post_28==Irql^0 && keR^1_3_1==1 && keR^post_28==0 && keA^1_3==1 && keA^post_28==0 && __rho_4_^post_28==__rho_4_^post_28 && k2^post_28==__rho_4_^post_28 && AsyncAddressData^0==AsyncAddressData^post_28 && BusResetIrp^0==BusResetIrp^post_28 && CromData^0==CromData^post_28 && DeviceObject^0==DeviceObject^post_28 && Irp^0==Irp^post_28 && Irql^0==Irql^post_28 && IsochDetachData^0==IsochDetachData^post_28 && IsochResourceData^0==IsochResourceData^post_28 && ResourceIrp^0==ResourceIrp^post_28 && StackSize^0==StackSize^post_28 && __rho_10_^0==__rho_10_^post_28 && __rho_11_^0==__rho_11_^post_28 && __rho_12_^0==__rho_12_^post_28 && __rho_1_^0==__rho_1_^post_28 && __rho_2_^0==__rho_2_^post_28 && __rho_3_^0==__rho_3_^post_28 && __rho_5_^0==__rho_5_^post_28 && __rho_666_^0==__rho_666_^post_28 && __rho_7_^0==__rho_7_^post_28 && __rho_8_^0==__rho_8_^post_28 && __rho_9_^0==__rho_9_^post_28 && a11^0==a11^post_28 && a1818^0==a1818^post_28 && a2525^0==a2525^post_28 && a2828^0==a2828^post_28 && a3131^0==a3131^post_28 && a3232^0==a3232^post_28 && a3434^0==a3434^post_28 && a3737^0==a3737^post_28 && a3838^0==a3838^post_28 && a4343^0==a4343^post_28 && a4545^0==a4545^post_28 && a77^0==a77^post_28 && b22^0==b22^post_28 && b2626^0==b2626^post_28 && b2929^0==b2929^post_28 && b3333^0==b3333^post_28 && b3535^0==b3535^post_28 && i^0==i^post_28 && i___01313^0==i___01313^post_28 && i___01717^0==i___01717^post_28 && i___02020^0==i___02020^post_28 && i___02424^0==i___02424^post_28 && i___04040^0==i___04040^post_28 && i___04747^0==i___04747^post_28 && ioA^0==ioA^post_28 && ioR^0==ioR^post_28 && k1^0==k1^post_28 && k3^0==k3^post_28 && k4^0==k4^post_28 && k5^0==k5^post_28 && ntStatus^0==ntStatus^post_28 && pIrb^0==pIrb^post_28 && phi_io_compl^0==phi_io_compl^post_28 && phi_nSUC_ret^0==phi_nSUC_ret^post_28 && prevCancel^0==prevCancel^post_28 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_28 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_28 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_28 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_28 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_28 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_28 ], cost: 1
     13: l12 -> l9 : AsyncAddressData^0'=AsyncAddressData^post_14, BusResetIrp^0'=BusResetIrp^post_14, CromData^0'=CromData^post_14, DeviceObject^0'=DeviceObject^post_14, Irp^0'=Irp^post_14, Irql^0'=Irql^post_14, IsochDetachData^0'=IsochDetachData^post_14, IsochResourceData^0'=IsochResourceData^post_14, ResourceIrp^0'=ResourceIrp^post_14, StackSize^0'=StackSize^post_14, __rho_10_^0'=__rho_10_^post_14, __rho_11_^0'=__rho_11_^post_14, __rho_12_^0'=__rho_12_^post_14, __rho_1_^0'=__rho_1_^post_14, __rho_2_^0'=__rho_2_^post_14, __rho_3_^0'=__rho_3_^post_14, __rho_4_^0'=__rho_4_^post_14, __rho_5_^0'=__rho_5_^post_14, __rho_666_^0'=__rho_666_^post_14, __rho_7_^0'=__rho_7_^post_14, __rho_8_^0'=__rho_8_^post_14, __rho_9_^0'=__rho_9_^post_14, a11^0'=a11^post_14, a1818^0'=a1818^post_14, a2525^0'=a2525^post_14, a2828^0'=a2828^post_14, a3131^0'=a3131^post_14, a3232^0'=a3232^post_14, a3434^0'=a3434^post_14, a3737^0'=a3737^post_14, a3838^0'=a3838^post_14, a4343^0'=a4343^post_14, a4545^0'=a4545^post_14, a77^0'=a77^post_14, b22^0'=b22^post_14, b2626^0'=b2626^post_14, b2929^0'=b2929^post_14, b3333^0'=b3333^post_14, b3535^0'=b3535^post_14, i^0'=i^post_14, i___01313^0'=i___01313^post_14, i___01717^0'=i___01717^post_14, i___02020^0'=i___02020^post_14, i___02424^0'=i___02424^post_14, i___04040^0'=i___04040^post_14, i___04747^0'=i___04747^post_14, i___099^0'=i___099^post_14, ioA^0'=ioA^post_14, ioR^0'=ioR^post_14, k1^0'=k1^post_14, k2^0'=k2^post_14, k3^0'=k3^post_14, k4^0'=k4^post_14, k5^0'=k5^post_14, keA^0'=keA^post_14, keR^0'=keR^post_14, ntStatus^0'=ntStatus^post_14, pIrb^0'=pIrb^post_14, phi_io_compl^0'=phi_io_compl^post_14, phi_nSUC_ret^0'=phi_nSUC_ret^post_14, prevCancel^0'=prevCancel^post_14, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_14, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_14, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_14, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_14, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_14, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_14, [ 1<=k2^0 && AsyncAddressData^1_1==AsyncAddressData^1_1 && AsyncAddressData^post_14==AsyncAddressData^post_14 && k2^post_14==-1+k2^0 && __rho_7_^post_14==__rho_7_^post_14 && BusResetIrp^0==BusResetIrp^post_14 && CromData^0==CromData^post_14 && DeviceObject^0==DeviceObject^post_14 && Irp^0==Irp^post_14 && Irql^0==Irql^post_14 && IsochDetachData^0==IsochDetachData^post_14 && IsochResourceData^0==IsochResourceData^post_14 && ResourceIrp^0==ResourceIrp^post_14 && StackSize^0==StackSize^post_14 && __rho_10_^0==__rho_10_^post_14 && __rho_11_^0==__rho_11_^post_14 && __rho_12_^0==__rho_12_^post_14 && __rho_1_^0==__rho_1_^post_14 && __rho_2_^0==__rho_2_^post_14 && __rho_3_^0==__rho_3_^post_14 && __rho_4_^0==__rho_4_^post_14 && __rho_5_^0==__rho_5_^post_14 && __rho_666_^0==__rho_666_^post_14 && __rho_8_^0==__rho_8_^post_14 && __rho_9_^0==__rho_9_^post_14 && a11^0==a11^post_14 && a1818^0==a1818^post_14 && a2525^0==a2525^post_14 && a2828^0==a2828^post_14 && a3131^0==a3131^post_14 && a3232^0==a3232^post_14 && a3434^0==a3434^post_14 && a3737^0==a3737^post_14 && a3838^0==a3838^post_14 && a4343^0==a4343^post_14 && a4545^0==a4545^post_14 && a77^0==a77^post_14 && b22^0==b22^post_14 && b2626^0==b2626^post_14 && b2929^0==b2929^post_14 && b3333^0==b3333^post_14 && b3535^0==b3535^post_14 && i^0==i^post_14 && i___01313^0==i___01313^post_14 && i___01717^0==i___01717^post_14 && i___02020^0==i___02020^post_14 && i___02424^0==i___02424^post_14 && i___04040^0==i___04040^post_14 && i___04747^0==i___04747^post_14 && i___099^0==i___099^post_14 && ioA^0==ioA^post_14 && ioR^0==ioR^post_14 && k1^0==k1^post_14 && k3^0==k3^post_14 && k4^0==k4^post_14 && k5^0==k5^post_14 && keA^0==keA^post_14 && keR^0==keR^post_14 && ntStatus^0==ntStatus^post_14 && pIrb^0==pIrb^post_14 && phi_io_compl^0==phi_io_compl^post_14 && phi_nSUC_ret^0==phi_nSUC_ret^post_14 && prevCancel^0==prevCancel^post_14 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_14 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_14 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_14 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_14 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_14 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_14 ], cost: 1
     14: l12 -> l2 : AsyncAddressData^0'=AsyncAddressData^post_15, BusResetIrp^0'=BusResetIrp^post_15, CromData^0'=CromData^post_15, DeviceObject^0'=DeviceObject^post_15, Irp^0'=Irp^post_15, Irql^0'=Irql^post_15, IsochDetachData^0'=IsochDetachData^post_15, IsochResourceData^0'=IsochResourceData^post_15, ResourceIrp^0'=ResourceIrp^post_15, StackSize^0'=StackSize^post_15, __rho_10_^0'=__rho_10_^post_15, __rho_11_^0'=__rho_11_^post_15, __rho_12_^0'=__rho_12_^post_15, __rho_1_^0'=__rho_1_^post_15, __rho_2_^0'=__rho_2_^post_15, __rho_3_^0'=__rho_3_^post_15, __rho_4_^0'=__rho_4_^post_15, __rho_5_^0'=__rho_5_^post_15, __rho_666_^0'=__rho_666_^post_15, __rho_7_^0'=__rho_7_^post_15, __rho_8_^0'=__rho_8_^post_15, __rho_9_^0'=__rho_9_^post_15, a11^0'=a11^post_15, a1818^0'=a1818^post_15, a2525^0'=a2525^post_15, a2828^0'=a2828^post_15, a3131^0'=a3131^post_15, a3232^0'=a3232^post_15, a3434^0'=a3434^post_15, a3737^0'=a3737^post_15, a3838^0'=a3838^post_15, a4343^0'=a4343^post_15, a4545^0'=a4545^post_15, a77^0'=a77^post_15, b22^0'=b22^post_15, b2626^0'=b2626^post_15, b2929^0'=b2929^post_15, b3333^0'=b3333^post_15, b3535^0'=b3535^post_15, i^0'=i^post_15, i___01313^0'=i___01313^post_15, i___01717^0'=i___01717^post_15, i___02020^0'=i___02020^post_15, i___02424^0'=i___02424^post_15, i___04040^0'=i___04040^post_15, i___04747^0'=i___04747^post_15, i___099^0'=i___099^post_15, ioA^0'=ioA^post_15, ioR^0'=ioR^post_15, k1^0'=k1^post_15, k2^0'=k2^post_15, k3^0'=k3^post_15, k4^0'=k4^post_15, k5^0'=k5^post_15, keA^0'=keA^post_15, keR^0'=keR^post_15, ntStatus^0'=ntStatus^post_15, pIrb^0'=pIrb^post_15, phi_io_compl^0'=phi_io_compl^post_15, phi_nSUC_ret^0'=phi_nSUC_ret^post_15, prevCancel^0'=prevCancel^post_15, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_15, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_15, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_15, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_15, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_15, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_15, [ k2^0<=0 && i___01313^post_15==Irql^0 && keR^1_2_2==1 && keR^post_15==0 && __rho_10_^post_15==__rho_10_^post_15 && k3^post_15==__rho_10_^post_15 && AsyncAddressData^0==AsyncAddressData^post_15 && BusResetIrp^0==BusResetIrp^post_15 && CromData^0==CromData^post_15 && DeviceObject^0==DeviceObject^post_15 && Irp^0==Irp^post_15 && Irql^0==Irql^post_15 && IsochDetachData^0==IsochDetachData^post_15 && IsochResourceData^0==IsochResourceData^post_15 && ResourceIrp^0==ResourceIrp^post_15 && StackSize^0==StackSize^post_15 && __rho_11_^0==__rho_11_^post_15 && __rho_12_^0==__rho_12_^post_15 && __rho_1_^0==__rho_1_^post_15 && __rho_2_^0==__rho_2_^post_15 && __rho_3_^0==__rho_3_^post_15 && __rho_4_^0==__rho_4_^post_15 && __rho_5_^0==__rho_5_^post_15 && __rho_666_^0==__rho_666_^post_15 && __rho_7_^0==__rho_7_^post_15 && __rho_8_^0==__rho_8_^post_15 && __rho_9_^0==__rho_9_^post_15 && a11^0==a11^post_15 && a1818^0==a1818^post_15 && a2525^0==a2525^post_15 && a2828^0==a2828^post_15 && a3131^0==a3131^post_15 && a3232^0==a3232^post_15 && a3434^0==a3434^post_15 && a3737^0==a3737^post_15 && a3838^0==a3838^post_15 && a4343^0==a4343^post_15 && a4545^0==a4545^post_15 && a77^0==a77^post_15 && b22^0==b22^post_15 && b2626^0==b2626^post_15 && b2929^0==b2929^post_15 && b3333^0==b3333^post_15 && b3535^0==b3535^post_15 && i^0==i^post_15 && i___01717^0==i___01717^post_15 && i___02020^0==i___02020^post_15 && i___02424^0==i___02424^post_15 && i___04040^0==i___04040^post_15 && i___04747^0==i___04747^post_15 && i___099^0==i___099^post_15 && ioA^0==ioA^post_15 && ioR^0==ioR^post_15 && k1^0==k1^post_15 && k2^0==k2^post_15 && k4^0==k4^post_15 && k5^0==k5^post_15 && keA^0==keA^post_15 && ntStatus^0==ntStatus^post_15 && pIrb^0==pIrb^post_15 && phi_io_compl^0==phi_io_compl^post_15 && phi_nSUC_ret^0==phi_nSUC_ret^post_15 && prevCancel^0==prevCancel^post_15 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_15 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_15 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_15 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_15 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_15 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_15 ], cost: 1
     17: l13 -> l10 : AsyncAddressData^0'=AsyncAddressData^post_18, BusResetIrp^0'=BusResetIrp^post_18, CromData^0'=CromData^post_18, DeviceObject^0'=DeviceObject^post_18, Irp^0'=Irp^post_18, Irql^0'=Irql^post_18, IsochDetachData^0'=IsochDetachData^post_18, IsochResourceData^0'=IsochResourceData^post_18, ResourceIrp^0'=ResourceIrp^post_18, StackSize^0'=StackSize^post_18, __rho_10_^0'=__rho_10_^post_18, __rho_11_^0'=__rho_11_^post_18, __rho_12_^0'=__rho_12_^post_18, __rho_1_^0'=__rho_1_^post_18, __rho_2_^0'=__rho_2_^post_18, __rho_3_^0'=__rho_3_^post_18, __rho_4_^0'=__rho_4_^post_18, __rho_5_^0'=__rho_5_^post_18, __rho_666_^0'=__rho_666_^post_18, __rho_7_^0'=__rho_7_^post_18, __rho_8_^0'=__rho_8_^post_18, __rho_9_^0'=__rho_9_^post_18, a11^0'=a11^post_18, a1818^0'=a1818^post_18, a2525^0'=a2525^post_18, a2828^0'=a2828^post_18, a3131^0'=a3131^post_18, a3232^0'=a3232^post_18, a3434^0'=a3434^post_18, a3737^0'=a3737^post_18, a3838^0'=a3838^post_18, a4343^0'=a4343^post_18, a4545^0'=a4545^post_18, a77^0'=a77^post_18, b22^0'=b22^post_18, b2626^0'=b2626^post_18, b2929^0'=b2929^post_18, b3333^0'=b3333^post_18, b3535^0'=b3535^post_18, i^0'=i^post_18, i___01313^0'=i___01313^post_18, i___01717^0'=i___01717^post_18, i___02020^0'=i___02020^post_18, i___02424^0'=i___02424^post_18, i___04040^0'=i___04040^post_18, i___04747^0'=i___04747^post_18, i___099^0'=i___099^post_18, ioA^0'=ioA^post_18, ioR^0'=ioR^post_18, k1^0'=k1^post_18, k2^0'=k2^post_18, k3^0'=k3^post_18, k4^0'=k4^post_18, k5^0'=k5^post_18, keA^0'=keA^post_18, keR^0'=keR^post_18, ntStatus^0'=ntStatus^post_18, pIrb^0'=pIrb^post_18, phi_io_compl^0'=phi_io_compl^post_18, phi_nSUC_ret^0'=phi_nSUC_ret^post_18, prevCancel^0'=prevCancel^post_18, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_18, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_18, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_18, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_18, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_18, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_18, [ a77^post_18==CromData^0 && AsyncAddressData^0==AsyncAddressData^post_18 && BusResetIrp^0==BusResetIrp^post_18 && CromData^0==CromData^post_18 && DeviceObject^0==DeviceObject^post_18 && Irp^0==Irp^post_18 && Irql^0==Irql^post_18 && IsochDetachData^0==IsochDetachData^post_18 && IsochResourceData^0==IsochResourceData^post_18 && ResourceIrp^0==ResourceIrp^post_18 && StackSize^0==StackSize^post_18 && __rho_10_^0==__rho_10_^post_18 && __rho_11_^0==__rho_11_^post_18 && __rho_12_^0==__rho_12_^post_18 && __rho_1_^0==__rho_1_^post_18 && __rho_2_^0==__rho_2_^post_18 && __rho_3_^0==__rho_3_^post_18 && __rho_4_^0==__rho_4_^post_18 && __rho_5_^0==__rho_5_^post_18 && __rho_666_^0==__rho_666_^post_18 && __rho_7_^0==__rho_7_^post_18 && __rho_8_^0==__rho_8_^post_18 && __rho_9_^0==__rho_9_^post_18 && a11^0==a11^post_18 && a1818^0==a1818^post_18 && a2525^0==a2525^post_18 && a2828^0==a2828^post_18 && a3131^0==a3131^post_18 && a3232^0==a3232^post_18 && a3434^0==a3434^post_18 && a3737^0==a3737^post_18 && a3838^0==a3838^post_18 && a4343^0==a4343^post_18 && a4545^0==a4545^post_18 && b22^0==b22^post_18 && b2626^0==b2626^post_18 && b2929^0==b2929^post_18 && b3333^0==b3333^post_18 && b3535^0==b3535^post_18 && i^0==i^post_18 && i___01313^0==i___01313^post_18 && i___01717^0==i___01717^post_18 && i___02020^0==i___02020^post_18 && i___02424^0==i___02424^post_18 && i___04040^0==i___04040^post_18 && i___04747^0==i___04747^post_18 && i___099^0==i___099^post_18 && ioA^0==ioA^post_18 && ioR^0==ioR^post_18 && k1^0==k1^post_18 && k2^0==k2^post_18 && k3^0==k3^post_18 && k4^0==k4^post_18 && k5^0==k5^post_18 && keA^0==keA^post_18 && keR^0==keR^post_18 && ntStatus^0==ntStatus^post_18 && pIrb^0==pIrb^post_18 && phi_io_compl^0==phi_io_compl^post_18 && phi_nSUC_ret^0==phi_nSUC_ret^post_18 && prevCancel^0==prevCancel^post_18 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_18 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_18 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_18 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_18 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_18 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_18 ], cost: 1
     18: l14 -> l13 : AsyncAddressData^0'=AsyncAddressData^post_19, BusResetIrp^0'=BusResetIrp^post_19, CromData^0'=CromData^post_19, DeviceObject^0'=DeviceObject^post_19, Irp^0'=Irp^post_19, Irql^0'=Irql^post_19, IsochDetachData^0'=IsochDetachData^post_19, IsochResourceData^0'=IsochResourceData^post_19, ResourceIrp^0'=ResourceIrp^post_19, StackSize^0'=StackSize^post_19, __rho_10_^0'=__rho_10_^post_19, __rho_11_^0'=__rho_11_^post_19, __rho_12_^0'=__rho_12_^post_19, __rho_1_^0'=__rho_1_^post_19, __rho_2_^0'=__rho_2_^post_19, __rho_3_^0'=__rho_3_^post_19, __rho_4_^0'=__rho_4_^post_19, __rho_5_^0'=__rho_5_^post_19, __rho_666_^0'=__rho_666_^post_19, __rho_7_^0'=__rho_7_^post_19, __rho_8_^0'=__rho_8_^post_19, __rho_9_^0'=__rho_9_^post_19, a11^0'=a11^post_19, a1818^0'=a1818^post_19, a2525^0'=a2525^post_19, a2828^0'=a2828^post_19, a3131^0'=a3131^post_19, a3232^0'=a3232^post_19, a3434^0'=a3434^post_19, a3737^0'=a3737^post_19, a3838^0'=a3838^post_19, a4343^0'=a4343^post_19, a4545^0'=a4545^post_19, a77^0'=a77^post_19, b22^0'=b22^post_19, b2626^0'=b2626^post_19, b2929^0'=b2929^post_19, b3333^0'=b3333^post_19, b3535^0'=b3535^post_19, i^0'=i^post_19, i___01313^0'=i___01313^post_19, i___01717^0'=i___01717^post_19, i___02020^0'=i___02020^post_19, i___02424^0'=i___02424^post_19, i___04040^0'=i___04040^post_19, i___04747^0'=i___04747^post_19, i___099^0'=i___099^post_19, ioA^0'=ioA^post_19, ioR^0'=ioR^post_19, k1^0'=k1^post_19, k2^0'=k2^post_19, k3^0'=k3^post_19, k4^0'=k4^post_19, k5^0'=k5^post_19, keA^0'=keA^post_19, keR^0'=keR^post_19, ntStatus^0'=ntStatus^post_19, pIrb^0'=pIrb^post_19, phi_io_compl^0'=phi_io_compl^post_19, phi_nSUC_ret^0'=phi_nSUC_ret^post_19, prevCancel^0'=prevCancel^post_19, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_19, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_19, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_19, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_19, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_19, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_19, [ __rho_3_^0<=0 && AsyncAddressData^0==AsyncAddressData^post_19 && BusResetIrp^0==BusResetIrp^post_19 && CromData^0==CromData^post_19 && DeviceObject^0==DeviceObject^post_19 && Irp^0==Irp^post_19 && Irql^0==Irql^post_19 && IsochDetachData^0==IsochDetachData^post_19 && IsochResourceData^0==IsochResourceData^post_19 && ResourceIrp^0==ResourceIrp^post_19 && StackSize^0==StackSize^post_19 && __rho_10_^0==__rho_10_^post_19 && __rho_11_^0==__rho_11_^post_19 && __rho_12_^0==__rho_12_^post_19 && __rho_1_^0==__rho_1_^post_19 && __rho_2_^0==__rho_2_^post_19 && __rho_3_^0==__rho_3_^post_19 && __rho_4_^0==__rho_4_^post_19 && __rho_5_^0==__rho_5_^post_19 && __rho_666_^0==__rho_666_^post_19 && __rho_7_^0==__rho_7_^post_19 && __rho_8_^0==__rho_8_^post_19 && __rho_9_^0==__rho_9_^post_19 && a11^0==a11^post_19 && a1818^0==a1818^post_19 && a2525^0==a2525^post_19 && a2828^0==a2828^post_19 && a3131^0==a3131^post_19 && a3232^0==a3232^post_19 && a3434^0==a3434^post_19 && a3737^0==a3737^post_19 && a3838^0==a3838^post_19 && a4343^0==a4343^post_19 && a4545^0==a4545^post_19 && a77^0==a77^post_19 && b22^0==b22^post_19 && b2626^0==b2626^post_19 && b2929^0==b2929^post_19 && b3333^0==b3333^post_19 && b3535^0==b3535^post_19 && i^0==i^post_19 && i___01313^0==i___01313^post_19 && i___01717^0==i___01717^post_19 && i___02020^0==i___02020^post_19 && i___02424^0==i___02424^post_19 && i___04040^0==i___04040^post_19 && i___04747^0==i___04747^post_19 && i___099^0==i___099^post_19 && ioA^0==ioA^post_19 && ioR^0==ioR^post_19 && k1^0==k1^post_19 && k2^0==k2^post_19 && k3^0==k3^post_19 && k4^0==k4^post_19 && k5^0==k5^post_19 && keA^0==keA^post_19 && keR^0==keR^post_19 && ntStatus^0==ntStatus^post_19 && pIrb^0==pIrb^post_19 && phi_io_compl^0==phi_io_compl^post_19 && phi_nSUC_ret^0==phi_nSUC_ret^post_19 && prevCancel^0==prevCancel^post_19 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_19 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_19 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_19 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_19 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_19 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_19 ], cost: 1
     19: l14 -> l13 : AsyncAddressData^0'=AsyncAddressData^post_20, BusResetIrp^0'=BusResetIrp^post_20, CromData^0'=CromData^post_20, DeviceObject^0'=DeviceObject^post_20, Irp^0'=Irp^post_20, Irql^0'=Irql^post_20, IsochDetachData^0'=IsochDetachData^post_20, IsochResourceData^0'=IsochResourceData^post_20, ResourceIrp^0'=ResourceIrp^post_20, StackSize^0'=StackSize^post_20, __rho_10_^0'=__rho_10_^post_20, __rho_11_^0'=__rho_11_^post_20, __rho_12_^0'=__rho_12_^post_20, __rho_1_^0'=__rho_1_^post_20, __rho_2_^0'=__rho_2_^post_20, __rho_3_^0'=__rho_3_^post_20, __rho_4_^0'=__rho_4_^post_20, __rho_5_^0'=__rho_5_^post_20, __rho_666_^0'=__rho_666_^post_20, __rho_7_^0'=__rho_7_^post_20, __rho_8_^0'=__rho_8_^post_20, __rho_9_^0'=__rho_9_^post_20, a11^0'=a11^post_20, a1818^0'=a1818^post_20, a2525^0'=a2525^post_20, a2828^0'=a2828^post_20, a3131^0'=a3131^post_20, a3232^0'=a3232^post_20, a3434^0'=a3434^post_20, a3737^0'=a3737^post_20, a3838^0'=a3838^post_20, a4343^0'=a4343^post_20, a4545^0'=a4545^post_20, a77^0'=a77^post_20, b22^0'=b22^post_20, b2626^0'=b2626^post_20, b2929^0'=b2929^post_20, b3333^0'=b3333^post_20, b3535^0'=b3535^post_20, i^0'=i^post_20, i___01313^0'=i___01313^post_20, i___01717^0'=i___01717^post_20, i___02020^0'=i___02020^post_20, i___02424^0'=i___02424^post_20, i___04040^0'=i___04040^post_20, i___04747^0'=i___04747^post_20, i___099^0'=i___099^post_20, ioA^0'=ioA^post_20, ioR^0'=ioR^post_20, k1^0'=k1^post_20, k2^0'=k2^post_20, k3^0'=k3^post_20, k4^0'=k4^post_20, k5^0'=k5^post_20, keA^0'=keA^post_20, keR^0'=keR^post_20, ntStatus^0'=ntStatus^post_20, pIrb^0'=pIrb^post_20, phi_io_compl^0'=phi_io_compl^post_20, phi_nSUC_ret^0'=phi_nSUC_ret^post_20, prevCancel^0'=prevCancel^post_20, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_20, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_20, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_20, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_20, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_20, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_20, [ 1<=__rho_3_^0 && AsyncAddressData^0==AsyncAddressData^post_20 && BusResetIrp^0==BusResetIrp^post_20 && CromData^0==CromData^post_20 && DeviceObject^0==DeviceObject^post_20 && Irp^0==Irp^post_20 && Irql^0==Irql^post_20 && IsochDetachData^0==IsochDetachData^post_20 && IsochResourceData^0==IsochResourceData^post_20 && ResourceIrp^0==ResourceIrp^post_20 && StackSize^0==StackSize^post_20 && __rho_10_^0==__rho_10_^post_20 && __rho_11_^0==__rho_11_^post_20 && __rho_12_^0==__rho_12_^post_20 && __rho_1_^0==__rho_1_^post_20 && __rho_2_^0==__rho_2_^post_20 && __rho_3_^0==__rho_3_^post_20 && __rho_4_^0==__rho_4_^post_20 && __rho_5_^0==__rho_5_^post_20 && __rho_666_^0==__rho_666_^post_20 && __rho_7_^0==__rho_7_^post_20 && __rho_8_^0==__rho_8_^post_20 && __rho_9_^0==__rho_9_^post_20 && a11^0==a11^post_20 && a1818^0==a1818^post_20 && a2525^0==a2525^post_20 && a2828^0==a2828^post_20 && a3131^0==a3131^post_20 && a3232^0==a3232^post_20 && a3434^0==a3434^post_20 && a3737^0==a3737^post_20 && a3838^0==a3838^post_20 && a4343^0==a4343^post_20 && a4545^0==a4545^post_20 && a77^0==a77^post_20 && b22^0==b22^post_20 && b2626^0==b2626^post_20 && b2929^0==b2929^post_20 && b3333^0==b3333^post_20 && b3535^0==b3535^post_20 && i^0==i^post_20 && i___01313^0==i___01313^post_20 && i___01717^0==i___01717^post_20 && i___02020^0==i___02020^post_20 && i___02424^0==i___02424^post_20 && i___04040^0==i___04040^post_20 && i___04747^0==i___04747^post_20 && i___099^0==i___099^post_20 && ioA^0==ioA^post_20 && ioR^0==ioR^post_20 && k1^0==k1^post_20 && k2^0==k2^post_20 && k3^0==k3^post_20 && k4^0==k4^post_20 && k5^0==k5^post_20 && keA^0==keA^post_20 && keR^0==keR^post_20 && ntStatus^0==ntStatus^post_20 && pIrb^0==pIrb^post_20 && phi_io_compl^0==phi_io_compl^post_20 && phi_nSUC_ret^0==phi_nSUC_ret^post_20 && prevCancel^0==prevCancel^post_20 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_20 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_20 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_20 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_20 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_20 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_20 ], cost: 1
     20: l15 -> l14 : AsyncAddressData^0'=AsyncAddressData^post_21, BusResetIrp^0'=BusResetIrp^post_21, CromData^0'=CromData^post_21, DeviceObject^0'=DeviceObject^post_21, Irp^0'=Irp^post_21, Irql^0'=Irql^post_21, IsochDetachData^0'=IsochDetachData^post_21, IsochResourceData^0'=IsochResourceData^post_21, ResourceIrp^0'=ResourceIrp^post_21, StackSize^0'=StackSize^post_21, __rho_10_^0'=__rho_10_^post_21, __rho_11_^0'=__rho_11_^post_21, __rho_12_^0'=__rho_12_^post_21, __rho_1_^0'=__rho_1_^post_21, __rho_2_^0'=__rho_2_^post_21, __rho_3_^0'=__rho_3_^post_21, __rho_4_^0'=__rho_4_^post_21, __rho_5_^0'=__rho_5_^post_21, __rho_666_^0'=__rho_666_^post_21, __rho_7_^0'=__rho_7_^post_21, __rho_8_^0'=__rho_8_^post_21, __rho_9_^0'=__rho_9_^post_21, a11^0'=a11^post_21, a1818^0'=a1818^post_21, a2525^0'=a2525^post_21, a2828^0'=a2828^post_21, a3131^0'=a3131^post_21, a3232^0'=a3232^post_21, a3434^0'=a3434^post_21, a3737^0'=a3737^post_21, a3838^0'=a3838^post_21, a4343^0'=a4343^post_21, a4545^0'=a4545^post_21, a77^0'=a77^post_21, b22^0'=b22^post_21, b2626^0'=b2626^post_21, b2929^0'=b2929^post_21, b3333^0'=b3333^post_21, b3535^0'=b3535^post_21, i^0'=i^post_21, i___01313^0'=i___01313^post_21, i___01717^0'=i___01717^post_21, i___02020^0'=i___02020^post_21, i___02424^0'=i___02424^post_21, i___04040^0'=i___04040^post_21, i___04747^0'=i___04747^post_21, i___099^0'=i___099^post_21, ioA^0'=ioA^post_21, ioR^0'=ioR^post_21, k1^0'=k1^post_21, k2^0'=k2^post_21, k3^0'=k3^post_21, k4^0'=k4^post_21, k5^0'=k5^post_21, keA^0'=keA^post_21, keR^0'=keR^post_21, ntStatus^0'=ntStatus^post_21, pIrb^0'=pIrb^post_21, phi_io_compl^0'=phi_io_compl^post_21, phi_nSUC_ret^0'=phi_nSUC_ret^post_21, prevCancel^0'=prevCancel^post_21, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_21, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_21, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_21, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_21, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_21, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_21, [ __rho_3_^post_21==__rho_3_^post_21 && AsyncAddressData^0==AsyncAddressData^post_21 && BusResetIrp^0==BusResetIrp^post_21 && CromData^0==CromData^post_21 && DeviceObject^0==DeviceObject^post_21 && Irp^0==Irp^post_21 && Irql^0==Irql^post_21 && IsochDetachData^0==IsochDetachData^post_21 && IsochResourceData^0==IsochResourceData^post_21 && ResourceIrp^0==ResourceIrp^post_21 && StackSize^0==StackSize^post_21 && __rho_10_^0==__rho_10_^post_21 && __rho_11_^0==__rho_11_^post_21 && __rho_12_^0==__rho_12_^post_21 && __rho_1_^0==__rho_1_^post_21 && __rho_2_^0==__rho_2_^post_21 && __rho_4_^0==__rho_4_^post_21 && __rho_5_^0==__rho_5_^post_21 && __rho_666_^0==__rho_666_^post_21 && __rho_7_^0==__rho_7_^post_21 && __rho_8_^0==__rho_8_^post_21 && __rho_9_^0==__rho_9_^post_21 && a11^0==a11^post_21 && a1818^0==a1818^post_21 && a2525^0==a2525^post_21 && a2828^0==a2828^post_21 && a3131^0==a3131^post_21 && a3232^0==a3232^post_21 && a3434^0==a3434^post_21 && a3737^0==a3737^post_21 && a3838^0==a3838^post_21 && a4343^0==a4343^post_21 && a4545^0==a4545^post_21 && a77^0==a77^post_21 && b22^0==b22^post_21 && b2626^0==b2626^post_21 && b2929^0==b2929^post_21 && b3333^0==b3333^post_21 && b3535^0==b3535^post_21 && i^0==i^post_21 && i___01313^0==i___01313^post_21 && i___01717^0==i___01717^post_21 && i___02020^0==i___02020^post_21 && i___02424^0==i___02424^post_21 && i___04040^0==i___04040^post_21 && i___04747^0==i___04747^post_21 && i___099^0==i___099^post_21 && ioA^0==ioA^post_21 && ioR^0==ioR^post_21 && k1^0==k1^post_21 && k2^0==k2^post_21 && k3^0==k3^post_21 && k4^0==k4^post_21 && k5^0==k5^post_21 && keA^0==keA^post_21 && keR^0==keR^post_21 && ntStatus^0==ntStatus^post_21 && pIrb^0==pIrb^post_21 && phi_io_compl^0==phi_io_compl^post_21 && phi_nSUC_ret^0==phi_nSUC_ret^post_21 && prevCancel^0==prevCancel^post_21 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_21 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_21 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_21 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_21 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_21 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_21 ], cost: 1
     21: l16 -> l15 : AsyncAddressData^0'=AsyncAddressData^post_22, BusResetIrp^0'=BusResetIrp^post_22, CromData^0'=CromData^post_22, DeviceObject^0'=DeviceObject^post_22, Irp^0'=Irp^post_22, Irql^0'=Irql^post_22, IsochDetachData^0'=IsochDetachData^post_22, IsochResourceData^0'=IsochResourceData^post_22, ResourceIrp^0'=ResourceIrp^post_22, StackSize^0'=StackSize^post_22, __rho_10_^0'=__rho_10_^post_22, __rho_11_^0'=__rho_11_^post_22, __rho_12_^0'=__rho_12_^post_22, __rho_1_^0'=__rho_1_^post_22, __rho_2_^0'=__rho_2_^post_22, __rho_3_^0'=__rho_3_^post_22, __rho_4_^0'=__rho_4_^post_22, __rho_5_^0'=__rho_5_^post_22, __rho_666_^0'=__rho_666_^post_22, __rho_7_^0'=__rho_7_^post_22, __rho_8_^0'=__rho_8_^post_22, __rho_9_^0'=__rho_9_^post_22, a11^0'=a11^post_22, a1818^0'=a1818^post_22, a2525^0'=a2525^post_22, a2828^0'=a2828^post_22, a3131^0'=a3131^post_22, a3232^0'=a3232^post_22, a3434^0'=a3434^post_22, a3737^0'=a3737^post_22, a3838^0'=a3838^post_22, a4343^0'=a4343^post_22, a4545^0'=a4545^post_22, a77^0'=a77^post_22, b22^0'=b22^post_22, b2626^0'=b2626^post_22, b2929^0'=b2929^post_22, b3333^0'=b3333^post_22, b3535^0'=b3535^post_22, i^0'=i^post_22, i___01313^0'=i___01313^post_22, i___01717^0'=i___01717^post_22, i___02020^0'=i___02020^post_22, i___02424^0'=i___02424^post_22, i___04040^0'=i___04040^post_22, i___04747^0'=i___04747^post_22, i___099^0'=i___099^post_22, ioA^0'=ioA^post_22, ioR^0'=ioR^post_22, k1^0'=k1^post_22, k2^0'=k2^post_22, k3^0'=k3^post_22, k4^0'=k4^post_22, k5^0'=k5^post_22, keA^0'=keA^post_22, keR^0'=keR^post_22, ntStatus^0'=ntStatus^post_22, pIrb^0'=pIrb^post_22, phi_io_compl^0'=phi_io_compl^post_22, phi_nSUC_ret^0'=phi_nSUC_ret^post_22, prevCancel^0'=prevCancel^post_22, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_22, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_22, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_22, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_22, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_22, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_22, [ __rho_2_^0<=0 && AsyncAddressData^0==AsyncAddressData^post_22 && BusResetIrp^0==BusResetIrp^post_22 && CromData^0==CromData^post_22 && DeviceObject^0==DeviceObject^post_22 && Irp^0==Irp^post_22 && Irql^0==Irql^post_22 && IsochDetachData^0==IsochDetachData^post_22 && IsochResourceData^0==IsochResourceData^post_22 && ResourceIrp^0==ResourceIrp^post_22 && StackSize^0==StackSize^post_22 && __rho_10_^0==__rho_10_^post_22 && __rho_11_^0==__rho_11_^post_22 && __rho_12_^0==__rho_12_^post_22 && __rho_1_^0==__rho_1_^post_22 && __rho_2_^0==__rho_2_^post_22 && __rho_3_^0==__rho_3_^post_22 && __rho_4_^0==__rho_4_^post_22 && __rho_5_^0==__rho_5_^post_22 && __rho_666_^0==__rho_666_^post_22 && __rho_7_^0==__rho_7_^post_22 && __rho_8_^0==__rho_8_^post_22 && __rho_9_^0==__rho_9_^post_22 && a11^0==a11^post_22 && a1818^0==a1818^post_22 && a2525^0==a2525^post_22 && a2828^0==a2828^post_22 && a3131^0==a3131^post_22 && a3232^0==a3232^post_22 && a3434^0==a3434^post_22 && a3737^0==a3737^post_22 && a3838^0==a3838^post_22 && a4343^0==a4343^post_22 && a4545^0==a4545^post_22 && a77^0==a77^post_22 && b22^0==b22^post_22 && b2626^0==b2626^post_22 && b2929^0==b2929^post_22 && b3333^0==b3333^post_22 && b3535^0==b3535^post_22 && i^0==i^post_22 && i___01313^0==i___01313^post_22 && i___01717^0==i___01717^post_22 && i___02020^0==i___02020^post_22 && i___02424^0==i___02424^post_22 && i___04040^0==i___04040^post_22 && i___04747^0==i___04747^post_22 && i___099^0==i___099^post_22 && ioA^0==ioA^post_22 && ioR^0==ioR^post_22 && k1^0==k1^post_22 && k2^0==k2^post_22 && k3^0==k3^post_22 && k4^0==k4^post_22 && k5^0==k5^post_22 && keA^0==keA^post_22 && keR^0==keR^post_22 && ntStatus^0==ntStatus^post_22 && pIrb^0==pIrb^post_22 && phi_io_compl^0==phi_io_compl^post_22 && phi_nSUC_ret^0==phi_nSUC_ret^post_22 && prevCancel^0==prevCancel^post_22 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_22 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_22 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_22 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_22 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_22 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_22 ], cost: 1
     22: l16 -> l15 : AsyncAddressData^0'=AsyncAddressData^post_23, BusResetIrp^0'=BusResetIrp^post_23, CromData^0'=CromData^post_23, DeviceObject^0'=DeviceObject^post_23, Irp^0'=Irp^post_23, Irql^0'=Irql^post_23, IsochDetachData^0'=IsochDetachData^post_23, IsochResourceData^0'=IsochResourceData^post_23, ResourceIrp^0'=ResourceIrp^post_23, StackSize^0'=StackSize^post_23, __rho_10_^0'=__rho_10_^post_23, __rho_11_^0'=__rho_11_^post_23, __rho_12_^0'=__rho_12_^post_23, __rho_1_^0'=__rho_1_^post_23, __rho_2_^0'=__rho_2_^post_23, __rho_3_^0'=__rho_3_^post_23, __rho_4_^0'=__rho_4_^post_23, __rho_5_^0'=__rho_5_^post_23, __rho_666_^0'=__rho_666_^post_23, __rho_7_^0'=__rho_7_^post_23, __rho_8_^0'=__rho_8_^post_23, __rho_9_^0'=__rho_9_^post_23, a11^0'=a11^post_23, a1818^0'=a1818^post_23, a2525^0'=a2525^post_23, a2828^0'=a2828^post_23, a3131^0'=a3131^post_23, a3232^0'=a3232^post_23, a3434^0'=a3434^post_23, a3737^0'=a3737^post_23, a3838^0'=a3838^post_23, a4343^0'=a4343^post_23, a4545^0'=a4545^post_23, a77^0'=a77^post_23, b22^0'=b22^post_23, b2626^0'=b2626^post_23, b2929^0'=b2929^post_23, b3333^0'=b3333^post_23, b3535^0'=b3535^post_23, i^0'=i^post_23, i___01313^0'=i___01313^post_23, i___01717^0'=i___01717^post_23, i___02020^0'=i___02020^post_23, i___02424^0'=i___02424^post_23, i___04040^0'=i___04040^post_23, i___04747^0'=i___04747^post_23, i___099^0'=i___099^post_23, ioA^0'=ioA^post_23, ioR^0'=ioR^post_23, k1^0'=k1^post_23, k2^0'=k2^post_23, k3^0'=k3^post_23, k4^0'=k4^post_23, k5^0'=k5^post_23, keA^0'=keA^post_23, keR^0'=keR^post_23, ntStatus^0'=ntStatus^post_23, pIrb^0'=pIrb^post_23, phi_io_compl^0'=phi_io_compl^post_23, phi_nSUC_ret^0'=phi_nSUC_ret^post_23, prevCancel^0'=prevCancel^post_23, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_23, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_23, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_23, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_23, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_23, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_23, [ 1<=__rho_2_^0 && AsyncAddressData^0==AsyncAddressData^post_23 && BusResetIrp^0==BusResetIrp^post_23 && CromData^0==CromData^post_23 && DeviceObject^0==DeviceObject^post_23 && Irp^0==Irp^post_23 && Irql^0==Irql^post_23 && IsochDetachData^0==IsochDetachData^post_23 && IsochResourceData^0==IsochResourceData^post_23 && ResourceIrp^0==ResourceIrp^post_23 && StackSize^0==StackSize^post_23 && __rho_10_^0==__rho_10_^post_23 && __rho_11_^0==__rho_11_^post_23 && __rho_12_^0==__rho_12_^post_23 && __rho_1_^0==__rho_1_^post_23 && __rho_2_^0==__rho_2_^post_23 && __rho_3_^0==__rho_3_^post_23 && __rho_4_^0==__rho_4_^post_23 && __rho_5_^0==__rho_5_^post_23 && __rho_666_^0==__rho_666_^post_23 && __rho_7_^0==__rho_7_^post_23 && __rho_8_^0==__rho_8_^post_23 && __rho_9_^0==__rho_9_^post_23 && a11^0==a11^post_23 && a1818^0==a1818^post_23 && a2525^0==a2525^post_23 && a2828^0==a2828^post_23 && a3131^0==a3131^post_23 && a3232^0==a3232^post_23 && a3434^0==a3434^post_23 && a3737^0==a3737^post_23 && a3838^0==a3838^post_23 && a4343^0==a4343^post_23 && a4545^0==a4545^post_23 && a77^0==a77^post_23 && b22^0==b22^post_23 && b2626^0==b2626^post_23 && b2929^0==b2929^post_23 && b3333^0==b3333^post_23 && b3535^0==b3535^post_23 && i^0==i^post_23 && i___01313^0==i___01313^post_23 && i___01717^0==i___01717^post_23 && i___02020^0==i___02020^post_23 && i___02424^0==i___02424^post_23 && i___04040^0==i___04040^post_23 && i___04747^0==i___04747^post_23 && i___099^0==i___099^post_23 && ioA^0==ioA^post_23 && ioR^0==ioR^post_23 && k1^0==k1^post_23 && k2^0==k2^post_23 && k3^0==k3^post_23 && k4^0==k4^post_23 && k5^0==k5^post_23 && keA^0==keA^post_23 && keR^0==keR^post_23 && ntStatus^0==ntStatus^post_23 && pIrb^0==pIrb^post_23 && phi_io_compl^0==phi_io_compl^post_23 && phi_nSUC_ret^0==phi_nSUC_ret^post_23 && prevCancel^0==prevCancel^post_23 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_23 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_23 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_23 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_23 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_23 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_23 ], cost: 1
     49: l17 -> l19 : AsyncAddressData^0'=AsyncAddressData^post_50, BusResetIrp^0'=BusResetIrp^post_50, CromData^0'=CromData^post_50, DeviceObject^0'=DeviceObject^post_50, Irp^0'=Irp^post_50, Irql^0'=Irql^post_50, IsochDetachData^0'=IsochDetachData^post_50, IsochResourceData^0'=IsochResourceData^post_50, ResourceIrp^0'=ResourceIrp^post_50, StackSize^0'=StackSize^post_50, __rho_10_^0'=__rho_10_^post_50, __rho_11_^0'=__rho_11_^post_50, __rho_12_^0'=__rho_12_^post_50, __rho_1_^0'=__rho_1_^post_50, __rho_2_^0'=__rho_2_^post_50, __rho_3_^0'=__rho_3_^post_50, __rho_4_^0'=__rho_4_^post_50, __rho_5_^0'=__rho_5_^post_50, __rho_666_^0'=__rho_666_^post_50, __rho_7_^0'=__rho_7_^post_50, __rho_8_^0'=__rho_8_^post_50, __rho_9_^0'=__rho_9_^post_50, a11^0'=a11^post_50, a1818^0'=a1818^post_50, a2525^0'=a2525^post_50, a2828^0'=a2828^post_50, a3131^0'=a3131^post_50, a3232^0'=a3232^post_50, a3434^0'=a3434^post_50, a3737^0'=a3737^post_50, a3838^0'=a3838^post_50, a4343^0'=a4343^post_50, a4545^0'=a4545^post_50, a77^0'=a77^post_50, b22^0'=b22^post_50, b2626^0'=b2626^post_50, b2929^0'=b2929^post_50, b3333^0'=b3333^post_50, b3535^0'=b3535^post_50, i^0'=i^post_50, i___01313^0'=i___01313^post_50, i___01717^0'=i___01717^post_50, i___02020^0'=i___02020^post_50, i___02424^0'=i___02424^post_50, i___04040^0'=i___04040^post_50, i___04747^0'=i___04747^post_50, i___099^0'=i___099^post_50, ioA^0'=ioA^post_50, ioR^0'=ioR^post_50, k1^0'=k1^post_50, k2^0'=k2^post_50, k3^0'=k3^post_50, k4^0'=k4^post_50, k5^0'=k5^post_50, keA^0'=keA^post_50, keR^0'=keR^post_50, ntStatus^0'=ntStatus^post_50, pIrb^0'=pIrb^post_50, phi_io_compl^0'=phi_io_compl^post_50, phi_nSUC_ret^0'=phi_nSUC_ret^post_50, prevCancel^0'=prevCancel^post_50, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_50, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_50, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_50, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_50, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_50, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_50, [ k4^0<=0 && i___04040^post_50==Irql^0 && keR^1_4_1==1 && keR^post_50==0 && keA^1_5==1 && keA^post_50==0 && __rho_12_^post_50==__rho_12_^post_50 && k5^post_50==__rho_12_^post_50 && AsyncAddressData^0==AsyncAddressData^post_50 && BusResetIrp^0==BusResetIrp^post_50 && CromData^0==CromData^post_50 && DeviceObject^0==DeviceObject^post_50 && Irp^0==Irp^post_50 && Irql^0==Irql^post_50 && IsochDetachData^0==IsochDetachData^post_50 && IsochResourceData^0==IsochResourceData^post_50 && ResourceIrp^0==ResourceIrp^post_50 && StackSize^0==StackSize^post_50 && __rho_10_^0==__rho_10_^post_50 && __rho_11_^0==__rho_11_^post_50 && __rho_1_^0==__rho_1_^post_50 && __rho_2_^0==__rho_2_^post_50 && __rho_3_^0==__rho_3_^post_50 && __rho_4_^0==__rho_4_^post_50 && __rho_5_^0==__rho_5_^post_50 && __rho_666_^0==__rho_666_^post_50 && __rho_7_^0==__rho_7_^post_50 && __rho_8_^0==__rho_8_^post_50 && __rho_9_^0==__rho_9_^post_50 && a11^0==a11^post_50 && a1818^0==a1818^post_50 && a2525^0==a2525^post_50 && a2828^0==a2828^post_50 && a3131^0==a3131^post_50 && a3232^0==a3232^post_50 && a3434^0==a3434^post_50 && a3737^0==a3737^post_50 && a3838^0==a3838^post_50 && a4343^0==a4343^post_50 && a4545^0==a4545^post_50 && a77^0==a77^post_50 && b22^0==b22^post_50 && b2626^0==b2626^post_50 && b2929^0==b2929^post_50 && b3333^0==b3333^post_50 && b3535^0==b3535^post_50 && i^0==i^post_50 && i___01313^0==i___01313^post_50 && i___01717^0==i___01717^post_50 && i___02020^0==i___02020^post_50 && i___02424^0==i___02424^post_50 && i___04747^0==i___04747^post_50 && i___099^0==i___099^post_50 && ioA^0==ioA^post_50 && ioR^0==ioR^post_50 && k1^0==k1^post_50 && k2^0==k2^post_50 && k3^0==k3^post_50 && k4^0==k4^post_50 && ntStatus^0==ntStatus^post_50 && pIrb^0==pIrb^post_50 && phi_io_compl^0==phi_io_compl^post_50 && phi_nSUC_ret^0==phi_nSUC_ret^post_50 && prevCancel^0==prevCancel^post_50 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_50 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_50 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_50 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_50 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_50 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_50 ], cost: 1
     50: l17 -> l32 : AsyncAddressData^0'=AsyncAddressData^post_51, BusResetIrp^0'=BusResetIrp^post_51, CromData^0'=CromData^post_51, DeviceObject^0'=DeviceObject^post_51, Irp^0'=Irp^post_51, Irql^0'=Irql^post_51, IsochDetachData^0'=IsochDetachData^post_51, IsochResourceData^0'=IsochResourceData^post_51, ResourceIrp^0'=ResourceIrp^post_51, StackSize^0'=StackSize^post_51, __rho_10_^0'=__rho_10_^post_51, __rho_11_^0'=__rho_11_^post_51, __rho_12_^0'=__rho_12_^post_51, __rho_1_^0'=__rho_1_^post_51, __rho_2_^0'=__rho_2_^post_51, __rho_3_^0'=__rho_3_^post_51, __rho_4_^0'=__rho_4_^post_51, __rho_5_^0'=__rho_5_^post_51, __rho_666_^0'=__rho_666_^post_51, __rho_7_^0'=__rho_7_^post_51, __rho_8_^0'=__rho_8_^post_51, __rho_9_^0'=__rho_9_^post_51, a11^0'=a11^post_51, a1818^0'=a1818^post_51, a2525^0'=a2525^post_51, a2828^0'=a2828^post_51, a3131^0'=a3131^post_51, a3232^0'=a3232^post_51, a3434^0'=a3434^post_51, a3737^0'=a3737^post_51, a3838^0'=a3838^post_51, a4343^0'=a4343^post_51, a4545^0'=a4545^post_51, a77^0'=a77^post_51, b22^0'=b22^post_51, b2626^0'=b2626^post_51, b2929^0'=b2929^post_51, b3333^0'=b3333^post_51, b3535^0'=b3535^post_51, i^0'=i^post_51, i___01313^0'=i___01313^post_51, i___01717^0'=i___01717^post_51, i___02020^0'=i___02020^post_51, i___02424^0'=i___02424^post_51, i___04040^0'=i___04040^post_51, i___04747^0'=i___04747^post_51, i___099^0'=i___099^post_51, ioA^0'=ioA^post_51, ioR^0'=ioR^post_51, k1^0'=k1^post_51, k2^0'=k2^post_51, k3^0'=k3^post_51, k4^0'=k4^post_51, k5^0'=k5^post_51, keA^0'=keA^post_51, keR^0'=keR^post_51, ntStatus^0'=ntStatus^post_51, pIrb^0'=pIrb^post_51, phi_io_compl^0'=phi_io_compl^post_51, phi_nSUC_ret^0'=phi_nSUC_ret^post_51, prevCancel^0'=prevCancel^post_51, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_51, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_51, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_51, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_51, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_51, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_51, [ 1<=k4^0 && IsochResourceData^post_51==IsochResourceData^post_51 && k4^post_51==-1+k4^0 && i___02424^post_51==Irql^0 && keR^1_4_2==1 && keR^post_51==0 && AsyncAddressData^0==AsyncAddressData^post_51 && BusResetIrp^0==BusResetIrp^post_51 && CromData^0==CromData^post_51 && DeviceObject^0==DeviceObject^post_51 && Irp^0==Irp^post_51 && Irql^0==Irql^post_51 && IsochDetachData^0==IsochDetachData^post_51 && ResourceIrp^0==ResourceIrp^post_51 && StackSize^0==StackSize^post_51 && __rho_10_^0==__rho_10_^post_51 && __rho_11_^0==__rho_11_^post_51 && __rho_12_^0==__rho_12_^post_51 && __rho_1_^0==__rho_1_^post_51 && __rho_2_^0==__rho_2_^post_51 && __rho_3_^0==__rho_3_^post_51 && __rho_4_^0==__rho_4_^post_51 && __rho_5_^0==__rho_5_^post_51 && __rho_666_^0==__rho_666_^post_51 && __rho_7_^0==__rho_7_^post_51 && __rho_8_^0==__rho_8_^post_51 && __rho_9_^0==__rho_9_^post_51 && a11^0==a11^post_51 && a1818^0==a1818^post_51 && a2525^0==a2525^post_51 && a2828^0==a2828^post_51 && a3131^0==a3131^post_51 && a3232^0==a3232^post_51 && a3434^0==a3434^post_51 && a3737^0==a3737^post_51 && a3838^0==a3838^post_51 && a4343^0==a4343^post_51 && a4545^0==a4545^post_51 && a77^0==a77^post_51 && b22^0==b22^post_51 && b2626^0==b2626^post_51 && b2929^0==b2929^post_51 && b3333^0==b3333^post_51 && b3535^0==b3535^post_51 && i^0==i^post_51 && i___01313^0==i___01313^post_51 && i___01717^0==i___01717^post_51 && i___02020^0==i___02020^post_51 && i___04040^0==i___04040^post_51 && i___04747^0==i___04747^post_51 && i___099^0==i___099^post_51 && ioA^0==ioA^post_51 && ioR^0==ioR^post_51 && k1^0==k1^post_51 && k2^0==k2^post_51 && k3^0==k3^post_51 && k5^0==k5^post_51 && keA^0==keA^post_51 && ntStatus^0==ntStatus^post_51 && pIrb^0==pIrb^post_51 && phi_io_compl^0==phi_io_compl^post_51 && phi_nSUC_ret^0==phi_nSUC_ret^post_51 && prevCancel^0==prevCancel^post_51 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_51 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_51 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_51 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_51 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_51 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_51 ], cost: 1
     24: l18 -> l10 : AsyncAddressData^0'=AsyncAddressData^post_25, BusResetIrp^0'=BusResetIrp^post_25, CromData^0'=CromData^post_25, DeviceObject^0'=DeviceObject^post_25, Irp^0'=Irp^post_25, Irql^0'=Irql^post_25, IsochDetachData^0'=IsochDetachData^post_25, IsochResourceData^0'=IsochResourceData^post_25, ResourceIrp^0'=ResourceIrp^post_25, StackSize^0'=StackSize^post_25, __rho_10_^0'=__rho_10_^post_25, __rho_11_^0'=__rho_11_^post_25, __rho_12_^0'=__rho_12_^post_25, __rho_1_^0'=__rho_1_^post_25, __rho_2_^0'=__rho_2_^post_25, __rho_3_^0'=__rho_3_^post_25, __rho_4_^0'=__rho_4_^post_25, __rho_5_^0'=__rho_5_^post_25, __rho_666_^0'=__rho_666_^post_25, __rho_7_^0'=__rho_7_^post_25, __rho_8_^0'=__rho_8_^post_25, __rho_9_^0'=__rho_9_^post_25, a11^0'=a11^post_25, a1818^0'=a1818^post_25, a2525^0'=a2525^post_25, a2828^0'=a2828^post_25, a3131^0'=a3131^post_25, a3232^0'=a3232^post_25, a3434^0'=a3434^post_25, a3737^0'=a3737^post_25, a3838^0'=a3838^post_25, a4343^0'=a4343^post_25, a4545^0'=a4545^post_25, a77^0'=a77^post_25, b22^0'=b22^post_25, b2626^0'=b2626^post_25, b2929^0'=b2929^post_25, b3333^0'=b3333^post_25, b3535^0'=b3535^post_25, i^0'=i^post_25, i___01313^0'=i___01313^post_25, i___01717^0'=i___01717^post_25, i___02020^0'=i___02020^post_25, i___02424^0'=i___02424^post_25, i___04040^0'=i___04040^post_25, i___04747^0'=i___04747^post_25, i___099^0'=i___099^post_25, ioA^0'=ioA^post_25, ioR^0'=ioR^post_25, k1^0'=k1^post_25, k2^0'=k2^post_25, k3^0'=k3^post_25, k4^0'=k4^post_25, k5^0'=k5^post_25, keA^0'=keA^post_25, keR^0'=keR^post_25, ntStatus^0'=ntStatus^post_25, pIrb^0'=pIrb^post_25, phi_io_compl^0'=phi_io_compl^post_25, phi_nSUC_ret^0'=phi_nSUC_ret^post_25, prevCancel^0'=prevCancel^post_25, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_25, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_25, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_25, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_25, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_25, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_25, [ CromData^0<=0 && AsyncAddressData^0==AsyncAddressData^post_25 && BusResetIrp^0==BusResetIrp^post_25 && CromData^0==CromData^post_25 && DeviceObject^0==DeviceObject^post_25 && Irp^0==Irp^post_25 && Irql^0==Irql^post_25 && IsochDetachData^0==IsochDetachData^post_25 && IsochResourceData^0==IsochResourceData^post_25 && ResourceIrp^0==ResourceIrp^post_25 && StackSize^0==StackSize^post_25 && __rho_10_^0==__rho_10_^post_25 && __rho_11_^0==__rho_11_^post_25 && __rho_12_^0==__rho_12_^post_25 && __rho_1_^0==__rho_1_^post_25 && __rho_2_^0==__rho_2_^post_25 && __rho_3_^0==__rho_3_^post_25 && __rho_4_^0==__rho_4_^post_25 && __rho_5_^0==__rho_5_^post_25 && __rho_666_^0==__rho_666_^post_25 && __rho_7_^0==__rho_7_^post_25 && __rho_8_^0==__rho_8_^post_25 && __rho_9_^0==__rho_9_^post_25 && a11^0==a11^post_25 && a1818^0==a1818^post_25 && a2525^0==a2525^post_25 && a2828^0==a2828^post_25 && a3131^0==a3131^post_25 && a3232^0==a3232^post_25 && a3434^0==a3434^post_25 && a3737^0==a3737^post_25 && a3838^0==a3838^post_25 && a4343^0==a4343^post_25 && a4545^0==a4545^post_25 && a77^0==a77^post_25 && b22^0==b22^post_25 && b2626^0==b2626^post_25 && b2929^0==b2929^post_25 && b3333^0==b3333^post_25 && b3535^0==b3535^post_25 && i^0==i^post_25 && i___01313^0==i___01313^post_25 && i___01717^0==i___01717^post_25 && i___02020^0==i___02020^post_25 && i___02424^0==i___02424^post_25 && i___04040^0==i___04040^post_25 && i___04747^0==i___04747^post_25 && i___099^0==i___099^post_25 && ioA^0==ioA^post_25 && ioR^0==ioR^post_25 && k1^0==k1^post_25 && k2^0==k2^post_25 && k3^0==k3^post_25 && k4^0==k4^post_25 && k5^0==k5^post_25 && keA^0==keA^post_25 && keR^0==keR^post_25 && ntStatus^0==ntStatus^post_25 && pIrb^0==pIrb^post_25 && phi_io_compl^0==phi_io_compl^post_25 && phi_nSUC_ret^0==phi_nSUC_ret^post_25 && prevCancel^0==prevCancel^post_25 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_25 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_25 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_25 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_25 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_25 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_25 ], cost: 1
     25: l18 -> l16 : AsyncAddressData^0'=AsyncAddressData^post_26, BusResetIrp^0'=BusResetIrp^post_26, CromData^0'=CromData^post_26, DeviceObject^0'=DeviceObject^post_26, Irp^0'=Irp^post_26, Irql^0'=Irql^post_26, IsochDetachData^0'=IsochDetachData^post_26, IsochResourceData^0'=IsochResourceData^post_26, ResourceIrp^0'=ResourceIrp^post_26, StackSize^0'=StackSize^post_26, __rho_10_^0'=__rho_10_^post_26, __rho_11_^0'=__rho_11_^post_26, __rho_12_^0'=__rho_12_^post_26, __rho_1_^0'=__rho_1_^post_26, __rho_2_^0'=__rho_2_^post_26, __rho_3_^0'=__rho_3_^post_26, __rho_4_^0'=__rho_4_^post_26, __rho_5_^0'=__rho_5_^post_26, __rho_666_^0'=__rho_666_^post_26, __rho_7_^0'=__rho_7_^post_26, __rho_8_^0'=__rho_8_^post_26, __rho_9_^0'=__rho_9_^post_26, a11^0'=a11^post_26, a1818^0'=a1818^post_26, a2525^0'=a2525^post_26, a2828^0'=a2828^post_26, a3131^0'=a3131^post_26, a3232^0'=a3232^post_26, a3434^0'=a3434^post_26, a3737^0'=a3737^post_26, a3838^0'=a3838^post_26, a4343^0'=a4343^post_26, a4545^0'=a4545^post_26, a77^0'=a77^post_26, b22^0'=b22^post_26, b2626^0'=b2626^post_26, b2929^0'=b2929^post_26, b3333^0'=b3333^post_26, b3535^0'=b3535^post_26, i^0'=i^post_26, i___01313^0'=i___01313^post_26, i___01717^0'=i___01717^post_26, i___02020^0'=i___02020^post_26, i___02424^0'=i___02424^post_26, i___04040^0'=i___04040^post_26, i___04747^0'=i___04747^post_26, i___099^0'=i___099^post_26, ioA^0'=ioA^post_26, ioR^0'=ioR^post_26, k1^0'=k1^post_26, k2^0'=k2^post_26, k3^0'=k3^post_26, k4^0'=k4^post_26, k5^0'=k5^post_26, keA^0'=keA^post_26, keR^0'=keR^post_26, ntStatus^0'=ntStatus^post_26, pIrb^0'=pIrb^post_26, phi_io_compl^0'=phi_io_compl^post_26, phi_nSUC_ret^0'=phi_nSUC_ret^post_26, prevCancel^0'=prevCancel^post_26, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_26, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_26, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_26, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_26, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_26, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_26, [ 1<=CromData^0 && __rho_2_^post_26==__rho_2_^post_26 && AsyncAddressData^0==AsyncAddressData^post_26 && BusResetIrp^0==BusResetIrp^post_26 && CromData^0==CromData^post_26 && DeviceObject^0==DeviceObject^post_26 && Irp^0==Irp^post_26 && Irql^0==Irql^post_26 && IsochDetachData^0==IsochDetachData^post_26 && IsochResourceData^0==IsochResourceData^post_26 && ResourceIrp^0==ResourceIrp^post_26 && StackSize^0==StackSize^post_26 && __rho_10_^0==__rho_10_^post_26 && __rho_11_^0==__rho_11_^post_26 && __rho_12_^0==__rho_12_^post_26 && __rho_1_^0==__rho_1_^post_26 && __rho_3_^0==__rho_3_^post_26 && __rho_4_^0==__rho_4_^post_26 && __rho_5_^0==__rho_5_^post_26 && __rho_666_^0==__rho_666_^post_26 && __rho_7_^0==__rho_7_^post_26 && __rho_8_^0==__rho_8_^post_26 && __rho_9_^0==__rho_9_^post_26 && a11^0==a11^post_26 && a1818^0==a1818^post_26 && a2525^0==a2525^post_26 && a2828^0==a2828^post_26 && a3131^0==a3131^post_26 && a3232^0==a3232^post_26 && a3434^0==a3434^post_26 && a3737^0==a3737^post_26 && a3838^0==a3838^post_26 && a4343^0==a4343^post_26 && a4545^0==a4545^post_26 && a77^0==a77^post_26 && b22^0==b22^post_26 && b2626^0==b2626^post_26 && b2929^0==b2929^post_26 && b3333^0==b3333^post_26 && b3535^0==b3535^post_26 && i^0==i^post_26 && i___01313^0==i___01313^post_26 && i___01717^0==i___01717^post_26 && i___02020^0==i___02020^post_26 && i___02424^0==i___02424^post_26 && i___04040^0==i___04040^post_26 && i___04747^0==i___04747^post_26 && i___099^0==i___099^post_26 && ioA^0==ioA^post_26 && ioR^0==ioR^post_26 && k1^0==k1^post_26 && k2^0==k2^post_26 && k3^0==k3^post_26 && k4^0==k4^post_26 && k5^0==k5^post_26 && keA^0==keA^post_26 && keR^0==keR^post_26 && ntStatus^0==ntStatus^post_26 && pIrb^0==pIrb^post_26 && phi_io_compl^0==phi_io_compl^post_26 && phi_nSUC_ret^0==phi_nSUC_ret^post_26 && prevCancel^0==prevCancel^post_26 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_26 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_26 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_26 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_26 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_26 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_26 ], cost: 1
     28: l19 -> l20 : AsyncAddressData^0'=AsyncAddressData^post_29, BusResetIrp^0'=BusResetIrp^post_29, CromData^0'=CromData^post_29, DeviceObject^0'=DeviceObject^post_29, Irp^0'=Irp^post_29, Irql^0'=Irql^post_29, IsochDetachData^0'=IsochDetachData^post_29, IsochResourceData^0'=IsochResourceData^post_29, ResourceIrp^0'=ResourceIrp^post_29, StackSize^0'=StackSize^post_29, __rho_10_^0'=__rho_10_^post_29, __rho_11_^0'=__rho_11_^post_29, __rho_12_^0'=__rho_12_^post_29, __rho_1_^0'=__rho_1_^post_29, __rho_2_^0'=__rho_2_^post_29, __rho_3_^0'=__rho_3_^post_29, __rho_4_^0'=__rho_4_^post_29, __rho_5_^0'=__rho_5_^post_29, __rho_666_^0'=__rho_666_^post_29, __rho_7_^0'=__rho_7_^post_29, __rho_8_^0'=__rho_8_^post_29, __rho_9_^0'=__rho_9_^post_29, a11^0'=a11^post_29, a1818^0'=a1818^post_29, a2525^0'=a2525^post_29, a2828^0'=a2828^post_29, a3131^0'=a3131^post_29, a3232^0'=a3232^post_29, a3434^0'=a3434^post_29, a3737^0'=a3737^post_29, a3838^0'=a3838^post_29, a4343^0'=a4343^post_29, a4545^0'=a4545^post_29, a77^0'=a77^post_29, b22^0'=b22^post_29, b2626^0'=b2626^post_29, b2929^0'=b2929^post_29, b3333^0'=b3333^post_29, b3535^0'=b3535^post_29, i^0'=i^post_29, i___01313^0'=i___01313^post_29, i___01717^0'=i___01717^post_29, i___02020^0'=i___02020^post_29, i___02424^0'=i___02424^post_29, i___04040^0'=i___04040^post_29, i___04747^0'=i___04747^post_29, i___099^0'=i___099^post_29, ioA^0'=ioA^post_29, ioR^0'=ioR^post_29, k1^0'=k1^post_29, k2^0'=k2^post_29, k3^0'=k3^post_29, k4^0'=k4^post_29, k5^0'=k5^post_29, keA^0'=keA^post_29, keR^0'=keR^post_29, ntStatus^0'=ntStatus^post_29, pIrb^0'=pIrb^post_29, phi_io_compl^0'=phi_io_compl^post_29, phi_nSUC_ret^0'=phi_nSUC_ret^post_29, prevCancel^0'=prevCancel^post_29, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_29, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_29, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_29, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_29, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_29, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_29, [ AsyncAddressData^0==AsyncAddressData^post_29 && BusResetIrp^0==BusResetIrp^post_29 && CromData^0==CromData^post_29 && DeviceObject^0==DeviceObject^post_29 && Irp^0==Irp^post_29 && Irql^0==Irql^post_29 && IsochDetachData^0==IsochDetachData^post_29 && IsochResourceData^0==IsochResourceData^post_29 && ResourceIrp^0==ResourceIrp^post_29 && StackSize^0==StackSize^post_29 && __rho_10_^0==__rho_10_^post_29 && __rho_11_^0==__rho_11_^post_29 && __rho_12_^0==__rho_12_^post_29 && __rho_1_^0==__rho_1_^post_29 && __rho_2_^0==__rho_2_^post_29 && __rho_3_^0==__rho_3_^post_29 && __rho_4_^0==__rho_4_^post_29 && __rho_5_^0==__rho_5_^post_29 && __rho_666_^0==__rho_666_^post_29 && __rho_7_^0==__rho_7_^post_29 && __rho_8_^0==__rho_8_^post_29 && __rho_9_^0==__rho_9_^post_29 && a11^0==a11^post_29 && a1818^0==a1818^post_29 && a2525^0==a2525^post_29 && a2828^0==a2828^post_29 && a3131^0==a3131^post_29 && a3232^0==a3232^post_29 && a3434^0==a3434^post_29 && a3737^0==a3737^post_29 && a3838^0==a3838^post_29 && a4343^0==a4343^post_29 && a4545^0==a4545^post_29 && a77^0==a77^post_29 && b22^0==b22^post_29 && b2626^0==b2626^post_29 && b2929^0==b2929^post_29 && b3333^0==b3333^post_29 && b3535^0==b3535^post_29 && i^0==i^post_29 && i___01313^0==i___01313^post_29 && i___01717^0==i___01717^post_29 && i___02020^0==i___02020^post_29 && i___02424^0==i___02424^post_29 && i___04040^0==i___04040^post_29 && i___04747^0==i___04747^post_29 && i___099^0==i___099^post_29 && ioA^0==ioA^post_29 && ioR^0==ioR^post_29 && k1^0==k1^post_29 && k2^0==k2^post_29 && k3^0==k3^post_29 && k4^0==k4^post_29 && k5^0==k5^post_29 && keA^0==keA^post_29 && keR^0==keR^post_29 && ntStatus^0==ntStatus^post_29 && pIrb^0==pIrb^post_29 && phi_io_compl^0==phi_io_compl^post_29 && phi_nSUC_ret^0==phi_nSUC_ret^post_29 && prevCancel^0==prevCancel^post_29 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_29 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_29 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_29 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_29 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_29 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_29 ], cost: 1
     37: l20 -> l19 : AsyncAddressData^0'=AsyncAddressData^post_38, BusResetIrp^0'=BusResetIrp^post_38, CromData^0'=CromData^post_38, DeviceObject^0'=DeviceObject^post_38, Irp^0'=Irp^post_38, Irql^0'=Irql^post_38, IsochDetachData^0'=IsochDetachData^post_38, IsochResourceData^0'=IsochResourceData^post_38, ResourceIrp^0'=ResourceIrp^post_38, StackSize^0'=StackSize^post_38, __rho_10_^0'=__rho_10_^post_38, __rho_11_^0'=__rho_11_^post_38, __rho_12_^0'=__rho_12_^post_38, __rho_1_^0'=__rho_1_^post_38, __rho_2_^0'=__rho_2_^post_38, __rho_3_^0'=__rho_3_^post_38, __rho_4_^0'=__rho_4_^post_38, __rho_5_^0'=__rho_5_^post_38, __rho_666_^0'=__rho_666_^post_38, __rho_7_^0'=__rho_7_^post_38, __rho_8_^0'=__rho_8_^post_38, __rho_9_^0'=__rho_9_^post_38, a11^0'=a11^post_38, a1818^0'=a1818^post_38, a2525^0'=a2525^post_38, a2828^0'=a2828^post_38, a3131^0'=a3131^post_38, a3232^0'=a3232^post_38, a3434^0'=a3434^post_38, a3737^0'=a3737^post_38, a3838^0'=a3838^post_38, a4343^0'=a4343^post_38, a4545^0'=a4545^post_38, a77^0'=a77^post_38, b22^0'=b22^post_38, b2626^0'=b2626^post_38, b2929^0'=b2929^post_38, b3333^0'=b3333^post_38, b3535^0'=b3535^post_38, i^0'=i^post_38, i___01313^0'=i___01313^post_38, i___01717^0'=i___01717^post_38, i___02020^0'=i___02020^post_38, i___02424^0'=i___02424^post_38, i___04040^0'=i___04040^post_38, i___04747^0'=i___04747^post_38, i___099^0'=i___099^post_38, ioA^0'=ioA^post_38, ioR^0'=ioR^post_38, k1^0'=k1^post_38, k2^0'=k2^post_38, k3^0'=k3^post_38, k4^0'=k4^post_38, k5^0'=k5^post_38, keA^0'=keA^post_38, keR^0'=keR^post_38, ntStatus^0'=ntStatus^post_38, pIrb^0'=pIrb^post_38, phi_io_compl^0'=phi_io_compl^post_38, phi_nSUC_ret^0'=phi_nSUC_ret^post_38, prevCancel^0'=prevCancel^post_38, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_38, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_38, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_38, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_38, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_38, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_38, [ 1<=k5^0 && prevCancel^1_1==0 && BusResetIrp^post_38==BusResetIrp^post_38 && k5^post_38==-1+k5^0 && a4343^post_38==0 && ret_IoSetCancelRoutine4444^post_38==0 && prevCancel^post_38==ret_IoSetCancelRoutine4444^post_38 && phi_io_compl^post_38==1 && a4545^post_38==BusResetIrp^post_38 && AsyncAddressData^0==AsyncAddressData^post_38 && CromData^0==CromData^post_38 && DeviceObject^0==DeviceObject^post_38 && Irp^0==Irp^post_38 && Irql^0==Irql^post_38 && IsochDetachData^0==IsochDetachData^post_38 && IsochResourceData^0==IsochResourceData^post_38 && ResourceIrp^0==ResourceIrp^post_38 && StackSize^0==StackSize^post_38 && __rho_10_^0==__rho_10_^post_38 && __rho_11_^0==__rho_11_^post_38 && __rho_12_^0==__rho_12_^post_38 && __rho_1_^0==__rho_1_^post_38 && __rho_2_^0==__rho_2_^post_38 && __rho_3_^0==__rho_3_^post_38 && __rho_4_^0==__rho_4_^post_38 && __rho_5_^0==__rho_5_^post_38 && __rho_666_^0==__rho_666_^post_38 && __rho_7_^0==__rho_7_^post_38 && __rho_8_^0==__rho_8_^post_38 && __rho_9_^0==__rho_9_^post_38 && a11^0==a11^post_38 && a1818^0==a1818^post_38 && a2525^0==a2525^post_38 && a2828^0==a2828^post_38 && a3131^0==a3131^post_38 && a3232^0==a3232^post_38 && a3434^0==a3434^post_38 && a3737^0==a3737^post_38 && a3838^0==a3838^post_38 && a77^0==a77^post_38 && b22^0==b22^post_38 && b2626^0==b2626^post_38 && b2929^0==b2929^post_38 && b3333^0==b3333^post_38 && b3535^0==b3535^post_38 && i^0==i^post_38 && i___01313^0==i___01313^post_38 && i___01717^0==i___01717^post_38 && i___02020^0==i___02020^post_38 && i___02424^0==i___02424^post_38 && i___04040^0==i___04040^post_38 && i___04747^0==i___04747^post_38 && i___099^0==i___099^post_38 && ioA^0==ioA^post_38 && ioR^0==ioR^post_38 && k1^0==k1^post_38 && k2^0==k2^post_38 && k3^0==k3^post_38 && k4^0==k4^post_38 && keA^0==keA^post_38 && keR^0==keR^post_38 && ntStatus^0==ntStatus^post_38 && pIrb^0==pIrb^post_38 && phi_nSUC_ret^0==phi_nSUC_ret^post_38 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_38 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_38 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_38 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_38 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_38 ], cost: 1
     38: l20 -> l26 : AsyncAddressData^0'=AsyncAddressData^post_39, BusResetIrp^0'=BusResetIrp^post_39, CromData^0'=CromData^post_39, DeviceObject^0'=DeviceObject^post_39, Irp^0'=Irp^post_39, Irql^0'=Irql^post_39, IsochDetachData^0'=IsochDetachData^post_39, IsochResourceData^0'=IsochResourceData^post_39, ResourceIrp^0'=ResourceIrp^post_39, StackSize^0'=StackSize^post_39, __rho_10_^0'=__rho_10_^post_39, __rho_11_^0'=__rho_11_^post_39, __rho_12_^0'=__rho_12_^post_39, __rho_1_^0'=__rho_1_^post_39, __rho_2_^0'=__rho_2_^post_39, __rho_3_^0'=__rho_3_^post_39, __rho_4_^0'=__rho_4_^post_39, __rho_5_^0'=__rho_5_^post_39, __rho_666_^0'=__rho_666_^post_39, __rho_7_^0'=__rho_7_^post_39, __rho_8_^0'=__rho_8_^post_39, __rho_9_^0'=__rho_9_^post_39, a11^0'=a11^post_39, a1818^0'=a1818^post_39, a2525^0'=a2525^post_39, a2828^0'=a2828^post_39, a3131^0'=a3131^post_39, a3232^0'=a3232^post_39, a3434^0'=a3434^post_39, a3737^0'=a3737^post_39, a3838^0'=a3838^post_39, a4343^0'=a4343^post_39, a4545^0'=a4545^post_39, a77^0'=a77^post_39, b22^0'=b22^post_39, b2626^0'=b2626^post_39, b2929^0'=b2929^post_39, b3333^0'=b3333^post_39, b3535^0'=b3535^post_39, i^0'=i^post_39, i___01313^0'=i___01313^post_39, i___01717^0'=i___01717^post_39, i___02020^0'=i___02020^post_39, i___02424^0'=i___02424^post_39, i___04040^0'=i___04040^post_39, i___04747^0'=i___04747^post_39, i___099^0'=i___099^post_39, ioA^0'=ioA^post_39, ioR^0'=ioR^post_39, k1^0'=k1^post_39, k2^0'=k2^post_39, k3^0'=k3^post_39, k4^0'=k4^post_39, k5^0'=k5^post_39, keA^0'=keA^post_39, keR^0'=keR^post_39, ntStatus^0'=ntStatus^post_39, pIrb^0'=pIrb^post_39, phi_io_compl^0'=phi_io_compl^post_39, phi_nSUC_ret^0'=phi_nSUC_ret^post_39, prevCancel^0'=prevCancel^post_39, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_39, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_39, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_39, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_39, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_39, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_39, [ k5^0<=0 && i___04747^post_39==Irql^0 && keR^1_3_2==1 && keR^post_39==0 && AsyncAddressData^0==AsyncAddressData^post_39 && BusResetIrp^0==BusResetIrp^post_39 && CromData^0==CromData^post_39 && DeviceObject^0==DeviceObject^post_39 && Irp^0==Irp^post_39 && Irql^0==Irql^post_39 && IsochDetachData^0==IsochDetachData^post_39 && IsochResourceData^0==IsochResourceData^post_39 && ResourceIrp^0==ResourceIrp^post_39 && StackSize^0==StackSize^post_39 && __rho_10_^0==__rho_10_^post_39 && __rho_11_^0==__rho_11_^post_39 && __rho_12_^0==__rho_12_^post_39 && __rho_1_^0==__rho_1_^post_39 && __rho_2_^0==__rho_2_^post_39 && __rho_3_^0==__rho_3_^post_39 && __rho_4_^0==__rho_4_^post_39 && __rho_5_^0==__rho_5_^post_39 && __rho_666_^0==__rho_666_^post_39 && __rho_7_^0==__rho_7_^post_39 && __rho_8_^0==__rho_8_^post_39 && __rho_9_^0==__rho_9_^post_39 && a11^0==a11^post_39 && a1818^0==a1818^post_39 && a2525^0==a2525^post_39 && a2828^0==a2828^post_39 && a3131^0==a3131^post_39 && a3232^0==a3232^post_39 && a3434^0==a3434^post_39 && a3737^0==a3737^post_39 && a3838^0==a3838^post_39 && a4343^0==a4343^post_39 && a4545^0==a4545^post_39 && a77^0==a77^post_39 && b22^0==b22^post_39 && b2626^0==b2626^post_39 && b2929^0==b2929^post_39 && b3333^0==b3333^post_39 && b3535^0==b3535^post_39 && i^0==i^post_39 && i___01313^0==i___01313^post_39 && i___01717^0==i___01717^post_39 && i___02020^0==i___02020^post_39 && i___02424^0==i___02424^post_39 && i___04040^0==i___04040^post_39 && i___099^0==i___099^post_39 && ioA^0==ioA^post_39 && ioR^0==ioR^post_39 && k1^0==k1^post_39 && k2^0==k2^post_39 && k3^0==k3^post_39 && k4^0==k4^post_39 && k5^0==k5^post_39 && keA^0==keA^post_39 && ntStatus^0==ntStatus^post_39 && pIrb^0==pIrb^post_39 && phi_io_compl^0==phi_io_compl^post_39 && phi_nSUC_ret^0==phi_nSUC_ret^post_39 && prevCancel^0==prevCancel^post_39 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_39 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_39 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_39 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_39 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_39 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_39 ], cost: 1
     29: l21 -> l10 : AsyncAddressData^0'=AsyncAddressData^post_30, BusResetIrp^0'=BusResetIrp^post_30, CromData^0'=CromData^post_30, DeviceObject^0'=DeviceObject^post_30, Irp^0'=Irp^post_30, Irql^0'=Irql^post_30, IsochDetachData^0'=IsochDetachData^post_30, IsochResourceData^0'=IsochResourceData^post_30, ResourceIrp^0'=ResourceIrp^post_30, StackSize^0'=StackSize^post_30, __rho_10_^0'=__rho_10_^post_30, __rho_11_^0'=__rho_11_^post_30, __rho_12_^0'=__rho_12_^post_30, __rho_1_^0'=__rho_1_^post_30, __rho_2_^0'=__rho_2_^post_30, __rho_3_^0'=__rho_3_^post_30, __rho_4_^0'=__rho_4_^post_30, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_30, __rho_7_^0'=__rho_7_^post_30, __rho_8_^0'=__rho_8_^post_30, __rho_9_^0'=__rho_9_^post_30, a11^0'=a11^post_30, a1818^0'=a1818^post_30, a2525^0'=a2525^post_30, a2828^0'=a2828^post_30, a3131^0'=a3131^post_30, a3232^0'=a3232^post_30, a3434^0'=a3434^post_30, a3737^0'=a3737^post_30, a3838^0'=a3838^post_30, a4343^0'=a4343^post_30, a4545^0'=a4545^post_30, a77^0'=a77^post_30, b22^0'=b22^post_30, b2626^0'=b2626^post_30, b2929^0'=b2929^post_30, b3333^0'=b3333^post_30, b3535^0'=b3535^post_30, i^0'=i^post_30, i___01313^0'=i___01313^post_30, i___01717^0'=i___01717^post_30, i___02020^0'=i___02020^post_30, i___02424^0'=i___02424^post_30, i___04040^0'=i___04040^post_30, i___04747^0'=i___04747^post_30, i___099^0'=i___099^post_30, ioA^0'=ioA^post_30, ioR^0'=ioR^post_30, k1^0'=k1^post_30, k2^0'=k2^post_30, k3^0'=k3^post_30, k4^0'=k4^post_30, k5^0'=k5^post_30, keA^0'=keA^post_30, keR^0'=keR^post_30, ntStatus^0'=ntStatus^post_30, pIrb^0'=pIrb^post_30, phi_io_compl^0'=phi_io_compl^post_30, phi_nSUC_ret^0'=phi_nSUC_ret^post_30, prevCancel^0'=prevCancel^post_30, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_30, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_30, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_30, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_30, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_30, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_30, [ ret_IoSetDeviceInterfaceState44^post_30==0 && ntStatus^post_30==ret_IoSetDeviceInterfaceState44^post_30 && keA^1_4==1 && keA^post_30==0 && __rho_5_^post_30==__rho_5_^post_30 && k1^post_30==__rho_5_^post_30 && AsyncAddressData^0==AsyncAddressData^post_30 && BusResetIrp^0==BusResetIrp^post_30 && CromData^0==CromData^post_30 && DeviceObject^0==DeviceObject^post_30 && Irp^0==Irp^post_30 && Irql^0==Irql^post_30 && IsochDetachData^0==IsochDetachData^post_30 && IsochResourceData^0==IsochResourceData^post_30 && ResourceIrp^0==ResourceIrp^post_30 && StackSize^0==StackSize^post_30 && __rho_10_^0==__rho_10_^post_30 && __rho_11_^0==__rho_11_^post_30 && __rho_12_^0==__rho_12_^post_30 && __rho_1_^0==__rho_1_^post_30 && __rho_2_^0==__rho_2_^post_30 && __rho_3_^0==__rho_3_^post_30 && __rho_4_^0==__rho_4_^post_30 && __rho_666_^0==__rho_666_^post_30 && __rho_7_^0==__rho_7_^post_30 && __rho_8_^0==__rho_8_^post_30 && __rho_9_^0==__rho_9_^post_30 && a11^0==a11^post_30 && a1818^0==a1818^post_30 && a2525^0==a2525^post_30 && a2828^0==a2828^post_30 && a3131^0==a3131^post_30 && a3232^0==a3232^post_30 && a3434^0==a3434^post_30 && a3737^0==a3737^post_30 && a3838^0==a3838^post_30 && a4343^0==a4343^post_30 && a4545^0==a4545^post_30 && a77^0==a77^post_30 && b22^0==b22^post_30 && b2626^0==b2626^post_30 && b2929^0==b2929^post_30 && b3333^0==b3333^post_30 && b3535^0==b3535^post_30 && i^0==i^post_30 && i___01313^0==i___01313^post_30 && i___01717^0==i___01717^post_30 && i___02020^0==i___02020^post_30 && i___02424^0==i___02424^post_30 && i___04040^0==i___04040^post_30 && i___04747^0==i___04747^post_30 && i___099^0==i___099^post_30 && ioA^0==ioA^post_30 && ioR^0==ioR^post_30 && k2^0==k2^post_30 && k3^0==k3^post_30 && k4^0==k4^post_30 && k5^0==k5^post_30 && keR^0==keR^post_30 && pIrb^0==pIrb^post_30 && phi_io_compl^0==phi_io_compl^post_30 && phi_nSUC_ret^0==phi_nSUC_ret^post_30 && prevCancel^0==prevCancel^post_30 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_30 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_30 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_30 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_30 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_30 ], cost: 1
     30: l22 -> l23 : AsyncAddressData^0'=AsyncAddressData^post_31, BusResetIrp^0'=BusResetIrp^post_31, CromData^0'=CromData^post_31, DeviceObject^0'=DeviceObject^post_31, Irp^0'=Irp^post_31, Irql^0'=Irql^post_31, IsochDetachData^0'=IsochDetachData^post_31, IsochResourceData^0'=IsochResourceData^post_31, ResourceIrp^0'=ResourceIrp^post_31, StackSize^0'=StackSize^post_31, __rho_10_^0'=__rho_10_^post_31, __rho_11_^0'=__rho_11_^post_31, __rho_12_^0'=__rho_12_^post_31, __rho_1_^0'=__rho_1_^post_31, __rho_2_^0'=__rho_2_^post_31, __rho_3_^0'=__rho_3_^post_31, __rho_4_^0'=__rho_4_^post_31, __rho_5_^0'=__rho_5_^post_31, __rho_666_^0'=__rho_666_^post_31, __rho_7_^0'=__rho_7_^post_31, __rho_8_^0'=__rho_8_^post_31, __rho_9_^0'=__rho_9_^post_31, a11^0'=a11^post_31, a1818^0'=a1818^post_31, a2525^0'=a2525^post_31, a2828^0'=a2828^post_31, a3131^0'=a3131^post_31, a3232^0'=a3232^post_31, a3434^0'=a3434^post_31, a3737^0'=a3737^post_31, a3838^0'=a3838^post_31, a4343^0'=a4343^post_31, a4545^0'=a4545^post_31, a77^0'=a77^post_31, b22^0'=b22^post_31, b2626^0'=b2626^post_31, b2929^0'=b2929^post_31, b3333^0'=b3333^post_31, b3535^0'=b3535^post_31, i^0'=i^post_31, i___01313^0'=i___01313^post_31, i___01717^0'=i___01717^post_31, i___02020^0'=i___02020^post_31, i___02424^0'=i___02424^post_31, i___04040^0'=i___04040^post_31, i___04747^0'=i___04747^post_31, i___099^0'=i___099^post_31, ioA^0'=ioA^post_31, ioR^0'=ioR^post_31, k1^0'=k1^post_31, k2^0'=k2^post_31, k3^0'=k3^post_31, k4^0'=k4^post_31, k5^0'=k5^post_31, keA^0'=keA^post_31, keR^0'=keR^post_31, ntStatus^0'=ntStatus^post_31, pIrb^0'=pIrb^post_31, phi_io_compl^0'=phi_io_compl^post_31, phi_nSUC_ret^0'=phi_nSUC_ret^post_31, prevCancel^0'=prevCancel^post_31, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_31, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_31, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_31, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_31, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_31, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_31, [ AsyncAddressData^0==AsyncAddressData^post_31 && BusResetIrp^0==BusResetIrp^post_31 && CromData^0==CromData^post_31 && DeviceObject^0==DeviceObject^post_31 && Irp^0==Irp^post_31 && Irql^0==Irql^post_31 && IsochDetachData^0==IsochDetachData^post_31 && IsochResourceData^0==IsochResourceData^post_31 && ResourceIrp^0==ResourceIrp^post_31 && StackSize^0==StackSize^post_31 && __rho_10_^0==__rho_10_^post_31 && __rho_11_^0==__rho_11_^post_31 && __rho_12_^0==__rho_12_^post_31 && __rho_1_^0==__rho_1_^post_31 && __rho_2_^0==__rho_2_^post_31 && __rho_3_^0==__rho_3_^post_31 && __rho_4_^0==__rho_4_^post_31 && __rho_5_^0==__rho_5_^post_31 && __rho_666_^0==__rho_666_^post_31 && __rho_7_^0==__rho_7_^post_31 && __rho_8_^0==__rho_8_^post_31 && __rho_9_^0==__rho_9_^post_31 && a11^0==a11^post_31 && a1818^0==a1818^post_31 && a2525^0==a2525^post_31 && a2828^0==a2828^post_31 && a3131^0==a3131^post_31 && a3232^0==a3232^post_31 && a3434^0==a3434^post_31 && a3737^0==a3737^post_31 && a3838^0==a3838^post_31 && a4343^0==a4343^post_31 && a4545^0==a4545^post_31 && a77^0==a77^post_31 && b22^0==b22^post_31 && b2626^0==b2626^post_31 && b2929^0==b2929^post_31 && b3333^0==b3333^post_31 && b3535^0==b3535^post_31 && i^0==i^post_31 && i___01313^0==i___01313^post_31 && i___01717^0==i___01717^post_31 && i___02020^0==i___02020^post_31 && i___02424^0==i___02424^post_31 && i___04040^0==i___04040^post_31 && i___04747^0==i___04747^post_31 && i___099^0==i___099^post_31 && ioA^0==ioA^post_31 && ioR^0==ioR^post_31 && k1^0==k1^post_31 && k2^0==k2^post_31 && k3^0==k3^post_31 && k4^0==k4^post_31 && k5^0==k5^post_31 && keA^0==keA^post_31 && keR^0==keR^post_31 && ntStatus^0==ntStatus^post_31 && pIrb^0==pIrb^post_31 && phi_io_compl^0==phi_io_compl^post_31 && phi_nSUC_ret^0==phi_nSUC_ret^post_31 && prevCancel^0==prevCancel^post_31 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_31 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_31 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_31 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_31 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_31 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_31 ], cost: 1
     31: l24 -> l25 : AsyncAddressData^0'=AsyncAddressData^post_32, BusResetIrp^0'=BusResetIrp^post_32, CromData^0'=CromData^post_32, DeviceObject^0'=DeviceObject^post_32, Irp^0'=Irp^post_32, Irql^0'=Irql^post_32, IsochDetachData^0'=IsochDetachData^post_32, IsochResourceData^0'=IsochResourceData^post_32, ResourceIrp^0'=ResourceIrp^post_32, StackSize^0'=StackSize^post_32, __rho_10_^0'=__rho_10_^post_32, __rho_11_^0'=__rho_11_^post_32, __rho_12_^0'=__rho_12_^post_32, __rho_1_^0'=__rho_1_^post_32, __rho_2_^0'=__rho_2_^post_32, __rho_3_^0'=__rho_3_^post_32, __rho_4_^0'=__rho_4_^post_32, __rho_5_^0'=__rho_5_^post_32, __rho_666_^0'=__rho_666_^post_32, __rho_7_^0'=__rho_7_^post_32, __rho_8_^0'=__rho_8_^post_32, __rho_9_^0'=__rho_9_^post_32, a11^0'=a11^post_32, a1818^0'=a1818^post_32, a2525^0'=a2525^post_32, a2828^0'=a2828^post_32, a3131^0'=a3131^post_32, a3232^0'=a3232^post_32, a3434^0'=a3434^post_32, a3737^0'=a3737^post_32, a3838^0'=a3838^post_32, a4343^0'=a4343^post_32, a4545^0'=a4545^post_32, a77^0'=a77^post_32, b22^0'=b22^post_32, b2626^0'=b2626^post_32, b2929^0'=b2929^post_32, b3333^0'=b3333^post_32, b3535^0'=b3535^post_32, i^0'=i^post_32, i___01313^0'=i___01313^post_32, i___01717^0'=i___01717^post_32, i___02020^0'=i___02020^post_32, i___02424^0'=i___02424^post_32, i___04040^0'=i___04040^post_32, i___04747^0'=i___04747^post_32, i___099^0'=i___099^post_32, ioA^0'=ioA^post_32, ioR^0'=ioR^post_32, k1^0'=k1^post_32, k2^0'=k2^post_32, k3^0'=k3^post_32, k4^0'=k4^post_32, k5^0'=k5^post_32, keA^0'=keA^post_32, keR^0'=keR^post_32, ntStatus^0'=ntStatus^post_32, pIrb^0'=pIrb^post_32, phi_io_compl^0'=phi_io_compl^post_32, phi_nSUC_ret^0'=phi_nSUC_ret^post_32, prevCancel^0'=prevCancel^post_32, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_32, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_32, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_32, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_32, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_32, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_32, [ phi_nSUC_ret^post_32==1 && AsyncAddressData^0==AsyncAddressData^post_32 && BusResetIrp^0==BusResetIrp^post_32 && CromData^0==CromData^post_32 && DeviceObject^0==DeviceObject^post_32 && Irp^0==Irp^post_32 && Irql^0==Irql^post_32 && IsochDetachData^0==IsochDetachData^post_32 && IsochResourceData^0==IsochResourceData^post_32 && ResourceIrp^0==ResourceIrp^post_32 && StackSize^0==StackSize^post_32 && __rho_10_^0==__rho_10_^post_32 && __rho_11_^0==__rho_11_^post_32 && __rho_12_^0==__rho_12_^post_32 && __rho_1_^0==__rho_1_^post_32 && __rho_2_^0==__rho_2_^post_32 && __rho_3_^0==__rho_3_^post_32 && __rho_4_^0==__rho_4_^post_32 && __rho_5_^0==__rho_5_^post_32 && __rho_666_^0==__rho_666_^post_32 && __rho_7_^0==__rho_7_^post_32 && __rho_8_^0==__rho_8_^post_32 && __rho_9_^0==__rho_9_^post_32 && a11^0==a11^post_32 && a1818^0==a1818^post_32 && a2525^0==a2525^post_32 && a2828^0==a2828^post_32 && a3131^0==a3131^post_32 && a3232^0==a3232^post_32 && a3434^0==a3434^post_32 && a3737^0==a3737^post_32 && a3838^0==a3838^post_32 && a4343^0==a4343^post_32 && a4545^0==a4545^post_32 && a77^0==a77^post_32 && b22^0==b22^post_32 && b2626^0==b2626^post_32 && b2929^0==b2929^post_32 && b3333^0==b3333^post_32 && b3535^0==b3535^post_32 && i^0==i^post_32 && i___01313^0==i___01313^post_32 && i___01717^0==i___01717^post_32 && i___02020^0==i___02020^post_32 && i___02424^0==i___02424^post_32 && i___04040^0==i___04040^post_32 && i___04747^0==i___04747^post_32 && i___099^0==i___099^post_32 && ioA^0==ioA^post_32 && ioR^0==ioR^post_32 && k1^0==k1^post_32 && k2^0==k2^post_32 && k3^0==k3^post_32 && k4^0==k4^post_32 && k5^0==k5^post_32 && keA^0==keA^post_32 && keR^0==keR^post_32 && ntStatus^0==ntStatus^post_32 && pIrb^0==pIrb^post_32 && phi_io_compl^0==phi_io_compl^post_32 && prevCancel^0==prevCancel^post_32 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_32 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_32 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_32 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_32 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_32 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_32 ], cost: 1
     35: l25 -> l27 : AsyncAddressData^0'=AsyncAddressData^post_36, BusResetIrp^0'=BusResetIrp^post_36, CromData^0'=CromData^post_36, DeviceObject^0'=DeviceObject^post_36, Irp^0'=Irp^post_36, Irql^0'=Irql^post_36, IsochDetachData^0'=IsochDetachData^post_36, IsochResourceData^0'=IsochResourceData^post_36, ResourceIrp^0'=ResourceIrp^post_36, StackSize^0'=StackSize^post_36, __rho_10_^0'=__rho_10_^post_36, __rho_11_^0'=__rho_11_^post_36, __rho_12_^0'=__rho_12_^post_36, __rho_1_^0'=__rho_1_^post_36, __rho_2_^0'=__rho_2_^post_36, __rho_3_^0'=__rho_3_^post_36, __rho_4_^0'=__rho_4_^post_36, __rho_5_^0'=__rho_5_^post_36, __rho_666_^0'=__rho_666_^post_36, __rho_7_^0'=__rho_7_^post_36, __rho_8_^0'=__rho_8_^post_36, __rho_9_^0'=__rho_9_^post_36, a11^0'=a11^post_36, a1818^0'=a1818^post_36, a2525^0'=a2525^post_36, a2828^0'=a2828^post_36, a3131^0'=a3131^post_36, a3232^0'=a3232^post_36, a3434^0'=a3434^post_36, a3737^0'=a3737^post_36, a3838^0'=a3838^post_36, a4343^0'=a4343^post_36, a4545^0'=a4545^post_36, a77^0'=a77^post_36, b22^0'=b22^post_36, b2626^0'=b2626^post_36, b2929^0'=b2929^post_36, b3333^0'=b3333^post_36, b3535^0'=b3535^post_36, i^0'=i^post_36, i___01313^0'=i___01313^post_36, i___01717^0'=i___01717^post_36, i___02020^0'=i___02020^post_36, i___02424^0'=i___02424^post_36, i___04040^0'=i___04040^post_36, i___04747^0'=i___04747^post_36, i___099^0'=i___099^post_36, ioA^0'=ioA^post_36, ioR^0'=ioR^post_36, k1^0'=k1^post_36, k2^0'=k2^post_36, k3^0'=k3^post_36, k4^0'=k4^post_36, k5^0'=k5^post_36, keA^0'=keA^post_36, keR^0'=keR^post_36, ntStatus^0'=ntStatus^post_36, pIrb^0'=pIrb^post_36, phi_io_compl^0'=phi_io_compl^post_36, phi_nSUC_ret^0'=phi_nSUC_ret^post_36, prevCancel^0'=prevCancel^post_36, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_36, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_36, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_36, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_36, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_36, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_36, [ AsyncAddressData^0==AsyncAddressData^post_36 && BusResetIrp^0==BusResetIrp^post_36 && CromData^0==CromData^post_36 && DeviceObject^0==DeviceObject^post_36 && Irp^0==Irp^post_36 && Irql^0==Irql^post_36 && IsochDetachData^0==IsochDetachData^post_36 && IsochResourceData^0==IsochResourceData^post_36 && ResourceIrp^0==ResourceIrp^post_36 && StackSize^0==StackSize^post_36 && __rho_10_^0==__rho_10_^post_36 && __rho_11_^0==__rho_11_^post_36 && __rho_12_^0==__rho_12_^post_36 && __rho_1_^0==__rho_1_^post_36 && __rho_2_^0==__rho_2_^post_36 && __rho_3_^0==__rho_3_^post_36 && __rho_4_^0==__rho_4_^post_36 && __rho_5_^0==__rho_5_^post_36 && __rho_666_^0==__rho_666_^post_36 && __rho_7_^0==__rho_7_^post_36 && __rho_8_^0==__rho_8_^post_36 && __rho_9_^0==__rho_9_^post_36 && a11^0==a11^post_36 && a1818^0==a1818^post_36 && a2525^0==a2525^post_36 && a2828^0==a2828^post_36 && a3131^0==a3131^post_36 && a3232^0==a3232^post_36 && a3434^0==a3434^post_36 && a3737^0==a3737^post_36 && a3838^0==a3838^post_36 && a4343^0==a4343^post_36 && a4545^0==a4545^post_36 && a77^0==a77^post_36 && b22^0==b22^post_36 && b2626^0==b2626^post_36 && b2929^0==b2929^post_36 && b3333^0==b3333^post_36 && b3535^0==b3535^post_36 && i^0==i^post_36 && i___01313^0==i___01313^post_36 && i___01717^0==i___01717^post_36 && i___02020^0==i___02020^post_36 && i___02424^0==i___02424^post_36 && i___04040^0==i___04040^post_36 && i___04747^0==i___04747^post_36 && i___099^0==i___099^post_36 && ioA^0==ioA^post_36 && ioR^0==ioR^post_36 && k1^0==k1^post_36 && k2^0==k2^post_36 && k3^0==k3^post_36 && k4^0==k4^post_36 && k5^0==k5^post_36 && keA^0==keA^post_36 && keR^0==keR^post_36 && ntStatus^0==ntStatus^post_36 && pIrb^0==pIrb^post_36 && phi_io_compl^0==phi_io_compl^post_36 && phi_nSUC_ret^0==phi_nSUC_ret^post_36 && prevCancel^0==prevCancel^post_36 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_36 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_36 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_36 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_36 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_36 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_36 ], cost: 1
     32: l26 -> l25 : AsyncAddressData^0'=AsyncAddressData^post_33, BusResetIrp^0'=BusResetIrp^post_33, CromData^0'=CromData^post_33, DeviceObject^0'=DeviceObject^post_33, Irp^0'=Irp^post_33, Irql^0'=Irql^post_33, IsochDetachData^0'=IsochDetachData^post_33, IsochResourceData^0'=IsochResourceData^post_33, ResourceIrp^0'=ResourceIrp^post_33, StackSize^0'=StackSize^post_33, __rho_10_^0'=__rho_10_^post_33, __rho_11_^0'=__rho_11_^post_33, __rho_12_^0'=__rho_12_^post_33, __rho_1_^0'=__rho_1_^post_33, __rho_2_^0'=__rho_2_^post_33, __rho_3_^0'=__rho_3_^post_33, __rho_4_^0'=__rho_4_^post_33, __rho_5_^0'=__rho_5_^post_33, __rho_666_^0'=__rho_666_^post_33, __rho_7_^0'=__rho_7_^post_33, __rho_8_^0'=__rho_8_^post_33, __rho_9_^0'=__rho_9_^post_33, a11^0'=a11^post_33, a1818^0'=a1818^post_33, a2525^0'=a2525^post_33, a2828^0'=a2828^post_33, a3131^0'=a3131^post_33, a3232^0'=a3232^post_33, a3434^0'=a3434^post_33, a3737^0'=a3737^post_33, a3838^0'=a3838^post_33, a4343^0'=a4343^post_33, a4545^0'=a4545^post_33, a77^0'=a77^post_33, b22^0'=b22^post_33, b2626^0'=b2626^post_33, b2929^0'=b2929^post_33, b3333^0'=b3333^post_33, b3535^0'=b3535^post_33, i^0'=i^post_33, i___01313^0'=i___01313^post_33, i___01717^0'=i___01717^post_33, i___02020^0'=i___02020^post_33, i___02424^0'=i___02424^post_33, i___04040^0'=i___04040^post_33, i___04747^0'=i___04747^post_33, i___099^0'=i___099^post_33, ioA^0'=ioA^post_33, ioR^0'=ioR^post_33, k1^0'=k1^post_33, k2^0'=k2^post_33, k3^0'=k3^post_33, k4^0'=k4^post_33, k5^0'=k5^post_33, keA^0'=keA^post_33, keR^0'=keR^post_33, ntStatus^0'=ntStatus^post_33, pIrb^0'=pIrb^post_33, phi_io_compl^0'=phi_io_compl^post_33, phi_nSUC_ret^0'=phi_nSUC_ret^post_33, prevCancel^0'=prevCancel^post_33, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_33, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_33, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_33, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_33, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_33, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_33, [ ntStatus^0<=2 && 2<=ntStatus^0 && AsyncAddressData^0==AsyncAddressData^post_33 && BusResetIrp^0==BusResetIrp^post_33 && CromData^0==CromData^post_33 && DeviceObject^0==DeviceObject^post_33 && Irp^0==Irp^post_33 && Irql^0==Irql^post_33 && IsochDetachData^0==IsochDetachData^post_33 && IsochResourceData^0==IsochResourceData^post_33 && ResourceIrp^0==ResourceIrp^post_33 && StackSize^0==StackSize^post_33 && __rho_10_^0==__rho_10_^post_33 && __rho_11_^0==__rho_11_^post_33 && __rho_12_^0==__rho_12_^post_33 && __rho_1_^0==__rho_1_^post_33 && __rho_2_^0==__rho_2_^post_33 && __rho_3_^0==__rho_3_^post_33 && __rho_4_^0==__rho_4_^post_33 && __rho_5_^0==__rho_5_^post_33 && __rho_666_^0==__rho_666_^post_33 && __rho_7_^0==__rho_7_^post_33 && __rho_8_^0==__rho_8_^post_33 && __rho_9_^0==__rho_9_^post_33 && a11^0==a11^post_33 && a1818^0==a1818^post_33 && a2525^0==a2525^post_33 && a2828^0==a2828^post_33 && a3131^0==a3131^post_33 && a3232^0==a3232^post_33 && a3434^0==a3434^post_33 && a3737^0==a3737^post_33 && a3838^0==a3838^post_33 && a4343^0==a4343^post_33 && a4545^0==a4545^post_33 && a77^0==a77^post_33 && b22^0==b22^post_33 && b2626^0==b2626^post_33 && b2929^0==b2929^post_33 && b3333^0==b3333^post_33 && b3535^0==b3535^post_33 && i^0==i^post_33 && i___01313^0==i___01313^post_33 && i___01717^0==i___01717^post_33 && i___02020^0==i___02020^post_33 && i___02424^0==i___02424^post_33 && i___04040^0==i___04040^post_33 && i___04747^0==i___04747^post_33 && i___099^0==i___099^post_33 && ioA^0==ioA^post_33 && ioR^0==ioR^post_33 && k1^0==k1^post_33 && k2^0==k2^post_33 && k3^0==k3^post_33 && k4^0==k4^post_33 && k5^0==k5^post_33 && keA^0==keA^post_33 && keR^0==keR^post_33 && ntStatus^0==ntStatus^post_33 && pIrb^0==pIrb^post_33 && phi_io_compl^0==phi_io_compl^post_33 && phi_nSUC_ret^0==phi_nSUC_ret^post_33 && prevCancel^0==prevCancel^post_33 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_33 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_33 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_33 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_33 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_33 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_33 ], cost: 1
     33: l26 -> l24 : AsyncAddressData^0'=AsyncAddressData^post_34, BusResetIrp^0'=BusResetIrp^post_34, CromData^0'=CromData^post_34, DeviceObject^0'=DeviceObject^post_34, Irp^0'=Irp^post_34, Irql^0'=Irql^post_34, IsochDetachData^0'=IsochDetachData^post_34, IsochResourceData^0'=IsochResourceData^post_34, ResourceIrp^0'=ResourceIrp^post_34, StackSize^0'=StackSize^post_34, __rho_10_^0'=__rho_10_^post_34, __rho_11_^0'=__rho_11_^post_34, __rho_12_^0'=__rho_12_^post_34, __rho_1_^0'=__rho_1_^post_34, __rho_2_^0'=__rho_2_^post_34, __rho_3_^0'=__rho_3_^post_34, __rho_4_^0'=__rho_4_^post_34, __rho_5_^0'=__rho_5_^post_34, __rho_666_^0'=__rho_666_^post_34, __rho_7_^0'=__rho_7_^post_34, __rho_8_^0'=__rho_8_^post_34, __rho_9_^0'=__rho_9_^post_34, a11^0'=a11^post_34, a1818^0'=a1818^post_34, a2525^0'=a2525^post_34, a2828^0'=a2828^post_34, a3131^0'=a3131^post_34, a3232^0'=a3232^post_34, a3434^0'=a3434^post_34, a3737^0'=a3737^post_34, a3838^0'=a3838^post_34, a4343^0'=a4343^post_34, a4545^0'=a4545^post_34, a77^0'=a77^post_34, b22^0'=b22^post_34, b2626^0'=b2626^post_34, b2929^0'=b2929^post_34, b3333^0'=b3333^post_34, b3535^0'=b3535^post_34, i^0'=i^post_34, i___01313^0'=i___01313^post_34, i___01717^0'=i___01717^post_34, i___02020^0'=i___02020^post_34, i___02424^0'=i___02424^post_34, i___04040^0'=i___04040^post_34, i___04747^0'=i___04747^post_34, i___099^0'=i___099^post_34, ioA^0'=ioA^post_34, ioR^0'=ioR^post_34, k1^0'=k1^post_34, k2^0'=k2^post_34, k3^0'=k3^post_34, k4^0'=k4^post_34, k5^0'=k5^post_34, keA^0'=keA^post_34, keR^0'=keR^post_34, ntStatus^0'=ntStatus^post_34, pIrb^0'=pIrb^post_34, phi_io_compl^0'=phi_io_compl^post_34, phi_nSUC_ret^0'=phi_nSUC_ret^post_34, prevCancel^0'=prevCancel^post_34, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_34, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_34, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_34, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_34, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_34, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_34, [ 3<=ntStatus^0 && AsyncAddressData^0==AsyncAddressData^post_34 && BusResetIrp^0==BusResetIrp^post_34 && CromData^0==CromData^post_34 && DeviceObject^0==DeviceObject^post_34 && Irp^0==Irp^post_34 && Irql^0==Irql^post_34 && IsochDetachData^0==IsochDetachData^post_34 && IsochResourceData^0==IsochResourceData^post_34 && ResourceIrp^0==ResourceIrp^post_34 && StackSize^0==StackSize^post_34 && __rho_10_^0==__rho_10_^post_34 && __rho_11_^0==__rho_11_^post_34 && __rho_12_^0==__rho_12_^post_34 && __rho_1_^0==__rho_1_^post_34 && __rho_2_^0==__rho_2_^post_34 && __rho_3_^0==__rho_3_^post_34 && __rho_4_^0==__rho_4_^post_34 && __rho_5_^0==__rho_5_^post_34 && __rho_666_^0==__rho_666_^post_34 && __rho_7_^0==__rho_7_^post_34 && __rho_8_^0==__rho_8_^post_34 && __rho_9_^0==__rho_9_^post_34 && a11^0==a11^post_34 && a1818^0==a1818^post_34 && a2525^0==a2525^post_34 && a2828^0==a2828^post_34 && a3131^0==a3131^post_34 && a3232^0==a3232^post_34 && a3434^0==a3434^post_34 && a3737^0==a3737^post_34 && a3838^0==a3838^post_34 && a4343^0==a4343^post_34 && a4545^0==a4545^post_34 && a77^0==a77^post_34 && b22^0==b22^post_34 && b2626^0==b2626^post_34 && b2929^0==b2929^post_34 && b3333^0==b3333^post_34 && b3535^0==b3535^post_34 && i^0==i^post_34 && i___01313^0==i___01313^post_34 && i___01717^0==i___01717^post_34 && i___02020^0==i___02020^post_34 && i___02424^0==i___02424^post_34 && i___04040^0==i___04040^post_34 && i___04747^0==i___04747^post_34 && i___099^0==i___099^post_34 && ioA^0==ioA^post_34 && ioR^0==ioR^post_34 && k1^0==k1^post_34 && k2^0==k2^post_34 && k3^0==k3^post_34 && k4^0==k4^post_34 && k5^0==k5^post_34 && keA^0==keA^post_34 && keR^0==keR^post_34 && ntStatus^0==ntStatus^post_34 && pIrb^0==pIrb^post_34 && phi_io_compl^0==phi_io_compl^post_34 && phi_nSUC_ret^0==phi_nSUC_ret^post_34 && prevCancel^0==prevCancel^post_34 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_34 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_34 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_34 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_34 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_34 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_34 ], cost: 1
     34: l26 -> l24 : AsyncAddressData^0'=AsyncAddressData^post_35, BusResetIrp^0'=BusResetIrp^post_35, CromData^0'=CromData^post_35, DeviceObject^0'=DeviceObject^post_35, Irp^0'=Irp^post_35, Irql^0'=Irql^post_35, IsochDetachData^0'=IsochDetachData^post_35, IsochResourceData^0'=IsochResourceData^post_35, ResourceIrp^0'=ResourceIrp^post_35, StackSize^0'=StackSize^post_35, __rho_10_^0'=__rho_10_^post_35, __rho_11_^0'=__rho_11_^post_35, __rho_12_^0'=__rho_12_^post_35, __rho_1_^0'=__rho_1_^post_35, __rho_2_^0'=__rho_2_^post_35, __rho_3_^0'=__rho_3_^post_35, __rho_4_^0'=__rho_4_^post_35, __rho_5_^0'=__rho_5_^post_35, __rho_666_^0'=__rho_666_^post_35, __rho_7_^0'=__rho_7_^post_35, __rho_8_^0'=__rho_8_^post_35, __rho_9_^0'=__rho_9_^post_35, a11^0'=a11^post_35, a1818^0'=a1818^post_35, a2525^0'=a2525^post_35, a2828^0'=a2828^post_35, a3131^0'=a3131^post_35, a3232^0'=a3232^post_35, a3434^0'=a3434^post_35, a3737^0'=a3737^post_35, a3838^0'=a3838^post_35, a4343^0'=a4343^post_35, a4545^0'=a4545^post_35, a77^0'=a77^post_35, b22^0'=b22^post_35, b2626^0'=b2626^post_35, b2929^0'=b2929^post_35, b3333^0'=b3333^post_35, b3535^0'=b3535^post_35, i^0'=i^post_35, i___01313^0'=i___01313^post_35, i___01717^0'=i___01717^post_35, i___02020^0'=i___02020^post_35, i___02424^0'=i___02424^post_35, i___04040^0'=i___04040^post_35, i___04747^0'=i___04747^post_35, i___099^0'=i___099^post_35, ioA^0'=ioA^post_35, ioR^0'=ioR^post_35, k1^0'=k1^post_35, k2^0'=k2^post_35, k3^0'=k3^post_35, k4^0'=k4^post_35, k5^0'=k5^post_35, keA^0'=keA^post_35, keR^0'=keR^post_35, ntStatus^0'=ntStatus^post_35, pIrb^0'=pIrb^post_35, phi_io_compl^0'=phi_io_compl^post_35, phi_nSUC_ret^0'=phi_nSUC_ret^post_35, prevCancel^0'=prevCancel^post_35, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_35, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_35, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_35, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_35, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_35, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_35, [ 1+ntStatus^0<=2 && AsyncAddressData^0==AsyncAddressData^post_35 && BusResetIrp^0==BusResetIrp^post_35 && CromData^0==CromData^post_35 && DeviceObject^0==DeviceObject^post_35 && Irp^0==Irp^post_35 && Irql^0==Irql^post_35 && IsochDetachData^0==IsochDetachData^post_35 && IsochResourceData^0==IsochResourceData^post_35 && ResourceIrp^0==ResourceIrp^post_35 && StackSize^0==StackSize^post_35 && __rho_10_^0==__rho_10_^post_35 && __rho_11_^0==__rho_11_^post_35 && __rho_12_^0==__rho_12_^post_35 && __rho_1_^0==__rho_1_^post_35 && __rho_2_^0==__rho_2_^post_35 && __rho_3_^0==__rho_3_^post_35 && __rho_4_^0==__rho_4_^post_35 && __rho_5_^0==__rho_5_^post_35 && __rho_666_^0==__rho_666_^post_35 && __rho_7_^0==__rho_7_^post_35 && __rho_8_^0==__rho_8_^post_35 && __rho_9_^0==__rho_9_^post_35 && a11^0==a11^post_35 && a1818^0==a1818^post_35 && a2525^0==a2525^post_35 && a2828^0==a2828^post_35 && a3131^0==a3131^post_35 && a3232^0==a3232^post_35 && a3434^0==a3434^post_35 && a3737^0==a3737^post_35 && a3838^0==a3838^post_35 && a4343^0==a4343^post_35 && a4545^0==a4545^post_35 && a77^0==a77^post_35 && b22^0==b22^post_35 && b2626^0==b2626^post_35 && b2929^0==b2929^post_35 && b3333^0==b3333^post_35 && b3535^0==b3535^post_35 && i^0==i^post_35 && i___01313^0==i___01313^post_35 && i___01717^0==i___01717^post_35 && i___02020^0==i___02020^post_35 && i___02424^0==i___02424^post_35 && i___04040^0==i___04040^post_35 && i___04747^0==i___04747^post_35 && i___099^0==i___099^post_35 && ioA^0==ioA^post_35 && ioR^0==ioR^post_35 && k1^0==k1^post_35 && k2^0==k2^post_35 && k3^0==k3^post_35 && k4^0==k4^post_35 && k5^0==k5^post_35 && keA^0==keA^post_35 && keR^0==keR^post_35 && ntStatus^0==ntStatus^post_35 && pIrb^0==pIrb^post_35 && phi_io_compl^0==phi_io_compl^post_35 && phi_nSUC_ret^0==phi_nSUC_ret^post_35 && prevCancel^0==prevCancel^post_35 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_35 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_35 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_35 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_35 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_35 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_35 ], cost: 1
     36: l27 -> l25 : AsyncAddressData^0'=AsyncAddressData^post_37, BusResetIrp^0'=BusResetIrp^post_37, CromData^0'=CromData^post_37, DeviceObject^0'=DeviceObject^post_37, Irp^0'=Irp^post_37, Irql^0'=Irql^post_37, IsochDetachData^0'=IsochDetachData^post_37, IsochResourceData^0'=IsochResourceData^post_37, ResourceIrp^0'=ResourceIrp^post_37, StackSize^0'=StackSize^post_37, __rho_10_^0'=__rho_10_^post_37, __rho_11_^0'=__rho_11_^post_37, __rho_12_^0'=__rho_12_^post_37, __rho_1_^0'=__rho_1_^post_37, __rho_2_^0'=__rho_2_^post_37, __rho_3_^0'=__rho_3_^post_37, __rho_4_^0'=__rho_4_^post_37, __rho_5_^0'=__rho_5_^post_37, __rho_666_^0'=__rho_666_^post_37, __rho_7_^0'=__rho_7_^post_37, __rho_8_^0'=__rho_8_^post_37, __rho_9_^0'=__rho_9_^post_37, a11^0'=a11^post_37, a1818^0'=a1818^post_37, a2525^0'=a2525^post_37, a2828^0'=a2828^post_37, a3131^0'=a3131^post_37, a3232^0'=a3232^post_37, a3434^0'=a3434^post_37, a3737^0'=a3737^post_37, a3838^0'=a3838^post_37, a4343^0'=a4343^post_37, a4545^0'=a4545^post_37, a77^0'=a77^post_37, b22^0'=b22^post_37, b2626^0'=b2626^post_37, b2929^0'=b2929^post_37, b3333^0'=b3333^post_37, b3535^0'=b3535^post_37, i^0'=i^post_37, i___01313^0'=i___01313^post_37, i___01717^0'=i___01717^post_37, i___02020^0'=i___02020^post_37, i___02424^0'=i___02424^post_37, i___04040^0'=i___04040^post_37, i___04747^0'=i___04747^post_37, i___099^0'=i___099^post_37, ioA^0'=ioA^post_37, ioR^0'=ioR^post_37, k1^0'=k1^post_37, k2^0'=k2^post_37, k3^0'=k3^post_37, k4^0'=k4^post_37, k5^0'=k5^post_37, keA^0'=keA^post_37, keR^0'=keR^post_37, ntStatus^0'=ntStatus^post_37, pIrb^0'=pIrb^post_37, phi_io_compl^0'=phi_io_compl^post_37, phi_nSUC_ret^0'=phi_nSUC_ret^post_37, prevCancel^0'=prevCancel^post_37, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_37, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_37, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_37, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_37, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_37, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_37, [ AsyncAddressData^0==AsyncAddressData^post_37 && BusResetIrp^0==BusResetIrp^post_37 && CromData^0==CromData^post_37 && DeviceObject^0==DeviceObject^post_37 && Irp^0==Irp^post_37 && Irql^0==Irql^post_37 && IsochDetachData^0==IsochDetachData^post_37 && IsochResourceData^0==IsochResourceData^post_37 && ResourceIrp^0==ResourceIrp^post_37 && StackSize^0==StackSize^post_37 && __rho_10_^0==__rho_10_^post_37 && __rho_11_^0==__rho_11_^post_37 && __rho_12_^0==__rho_12_^post_37 && __rho_1_^0==__rho_1_^post_37 && __rho_2_^0==__rho_2_^post_37 && __rho_3_^0==__rho_3_^post_37 && __rho_4_^0==__rho_4_^post_37 && __rho_5_^0==__rho_5_^post_37 && __rho_666_^0==__rho_666_^post_37 && __rho_7_^0==__rho_7_^post_37 && __rho_8_^0==__rho_8_^post_37 && __rho_9_^0==__rho_9_^post_37 && a11^0==a11^post_37 && a1818^0==a1818^post_37 && a2525^0==a2525^post_37 && a2828^0==a2828^post_37 && a3131^0==a3131^post_37 && a3232^0==a3232^post_37 && a3434^0==a3434^post_37 && a3737^0==a3737^post_37 && a3838^0==a3838^post_37 && a4343^0==a4343^post_37 && a4545^0==a4545^post_37 && a77^0==a77^post_37 && b22^0==b22^post_37 && b2626^0==b2626^post_37 && b2929^0==b2929^post_37 && b3333^0==b3333^post_37 && b3535^0==b3535^post_37 && i^0==i^post_37 && i___01313^0==i___01313^post_37 && i___01717^0==i___01717^post_37 && i___02020^0==i___02020^post_37 && i___02424^0==i___02424^post_37 && i___04040^0==i___04040^post_37 && i___04747^0==i___04747^post_37 && i___099^0==i___099^post_37 && ioA^0==ioA^post_37 && ioR^0==ioR^post_37 && k1^0==k1^post_37 && k2^0==k2^post_37 && k3^0==k3^post_37 && k4^0==k4^post_37 && k5^0==k5^post_37 && keA^0==keA^post_37 && keR^0==keR^post_37 && ntStatus^0==ntStatus^post_37 && pIrb^0==pIrb^post_37 && phi_io_compl^0==phi_io_compl^post_37 && phi_nSUC_ret^0==phi_nSUC_ret^post_37 && prevCancel^0==prevCancel^post_37 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_37 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_37 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_37 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_37 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_37 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_37 ], cost: 1
     39: l28 -> l21 : AsyncAddressData^0'=AsyncAddressData^post_40, BusResetIrp^0'=BusResetIrp^post_40, CromData^0'=CromData^post_40, DeviceObject^0'=DeviceObject^post_40, Irp^0'=Irp^post_40, Irql^0'=Irql^post_40, IsochDetachData^0'=IsochDetachData^post_40, IsochResourceData^0'=IsochResourceData^post_40, ResourceIrp^0'=ResourceIrp^post_40, StackSize^0'=StackSize^post_40, __rho_10_^0'=__rho_10_^post_40, __rho_11_^0'=__rho_11_^post_40, __rho_12_^0'=__rho_12_^post_40, __rho_1_^0'=__rho_1_^post_40, __rho_2_^0'=__rho_2_^post_40, __rho_3_^0'=__rho_3_^post_40, __rho_4_^0'=__rho_4_^post_40, __rho_5_^0'=__rho_5_^post_40, __rho_666_^0'=__rho_666_^post_40, __rho_7_^0'=__rho_7_^post_40, __rho_8_^0'=__rho_8_^post_40, __rho_9_^0'=__rho_9_^post_40, a11^0'=a11^post_40, a1818^0'=a1818^post_40, a2525^0'=a2525^post_40, a2828^0'=a2828^post_40, a3131^0'=a3131^post_40, a3232^0'=a3232^post_40, a3434^0'=a3434^post_40, a3737^0'=a3737^post_40, a3838^0'=a3838^post_40, a4343^0'=a4343^post_40, a4545^0'=a4545^post_40, a77^0'=a77^post_40, b22^0'=b22^post_40, b2626^0'=b2626^post_40, b2929^0'=b2929^post_40, b3333^0'=b3333^post_40, b3535^0'=b3535^post_40, i^0'=i^post_40, i___01313^0'=i___01313^post_40, i___01717^0'=i___01717^post_40, i___02020^0'=i___02020^post_40, i___02424^0'=i___02424^post_40, i___04040^0'=i___04040^post_40, i___04747^0'=i___04747^post_40, i___099^0'=i___099^post_40, ioA^0'=ioA^post_40, ioR^0'=ioR^post_40, k1^0'=k1^post_40, k2^0'=k2^post_40, k3^0'=k3^post_40, k4^0'=k4^post_40, k5^0'=k5^post_40, keA^0'=keA^post_40, keR^0'=keR^post_40, ntStatus^0'=ntStatus^post_40, pIrb^0'=pIrb^post_40, phi_io_compl^0'=phi_io_compl^post_40, phi_nSUC_ret^0'=phi_nSUC_ret^post_40, prevCancel^0'=prevCancel^post_40, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_40, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_40, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_40, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_40, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_40, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_40, [ __rho_1_^0<=0 && AsyncAddressData^0==AsyncAddressData^post_40 && BusResetIrp^0==BusResetIrp^post_40 && CromData^0==CromData^post_40 && DeviceObject^0==DeviceObject^post_40 && Irp^0==Irp^post_40 && Irql^0==Irql^post_40 && IsochDetachData^0==IsochDetachData^post_40 && IsochResourceData^0==IsochResourceData^post_40 && ResourceIrp^0==ResourceIrp^post_40 && StackSize^0==StackSize^post_40 && __rho_10_^0==__rho_10_^post_40 && __rho_11_^0==__rho_11_^post_40 && __rho_12_^0==__rho_12_^post_40 && __rho_1_^0==__rho_1_^post_40 && __rho_2_^0==__rho_2_^post_40 && __rho_3_^0==__rho_3_^post_40 && __rho_4_^0==__rho_4_^post_40 && __rho_5_^0==__rho_5_^post_40 && __rho_666_^0==__rho_666_^post_40 && __rho_7_^0==__rho_7_^post_40 && __rho_8_^0==__rho_8_^post_40 && __rho_9_^0==__rho_9_^post_40 && a11^0==a11^post_40 && a1818^0==a1818^post_40 && a2525^0==a2525^post_40 && a2828^0==a2828^post_40 && a3131^0==a3131^post_40 && a3232^0==a3232^post_40 && a3434^0==a3434^post_40 && a3737^0==a3737^post_40 && a3838^0==a3838^post_40 && a4343^0==a4343^post_40 && a4545^0==a4545^post_40 && a77^0==a77^post_40 && b22^0==b22^post_40 && b2626^0==b2626^post_40 && b2929^0==b2929^post_40 && b3333^0==b3333^post_40 && b3535^0==b3535^post_40 && i^0==i^post_40 && i___01313^0==i___01313^post_40 && i___01717^0==i___01717^post_40 && i___02020^0==i___02020^post_40 && i___02424^0==i___02424^post_40 && i___04040^0==i___04040^post_40 && i___04747^0==i___04747^post_40 && i___099^0==i___099^post_40 && ioA^0==ioA^post_40 && ioR^0==ioR^post_40 && k1^0==k1^post_40 && k2^0==k2^post_40 && k3^0==k3^post_40 && k4^0==k4^post_40 && k5^0==k5^post_40 && keA^0==keA^post_40 && keR^0==keR^post_40 && ntStatus^0==ntStatus^post_40 && pIrb^0==pIrb^post_40 && phi_io_compl^0==phi_io_compl^post_40 && phi_nSUC_ret^0==phi_nSUC_ret^post_40 && prevCancel^0==prevCancel^post_40 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_40 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_40 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_40 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_40 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_40 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_40 ], cost: 1
     40: l28 -> l21 : AsyncAddressData^0'=AsyncAddressData^post_41, BusResetIrp^0'=BusResetIrp^post_41, CromData^0'=CromData^post_41, DeviceObject^0'=DeviceObject^post_41, Irp^0'=Irp^post_41, Irql^0'=Irql^post_41, IsochDetachData^0'=IsochDetachData^post_41, IsochResourceData^0'=IsochResourceData^post_41, ResourceIrp^0'=ResourceIrp^post_41, StackSize^0'=StackSize^post_41, __rho_10_^0'=__rho_10_^post_41, __rho_11_^0'=__rho_11_^post_41, __rho_12_^0'=__rho_12_^post_41, __rho_1_^0'=__rho_1_^post_41, __rho_2_^0'=__rho_2_^post_41, __rho_3_^0'=__rho_3_^post_41, __rho_4_^0'=__rho_4_^post_41, __rho_5_^0'=__rho_5_^post_41, __rho_666_^0'=__rho_666_^post_41, __rho_7_^0'=__rho_7_^post_41, __rho_8_^0'=__rho_8_^post_41, __rho_9_^0'=__rho_9_^post_41, a11^0'=a11^post_41, a1818^0'=a1818^post_41, a2525^0'=a2525^post_41, a2828^0'=a2828^post_41, a3131^0'=a3131^post_41, a3232^0'=a3232^post_41, a3434^0'=a3434^post_41, a3737^0'=a3737^post_41, a3838^0'=a3838^post_41, a4343^0'=a4343^post_41, a4545^0'=a4545^post_41, a77^0'=a77^post_41, b22^0'=b22^post_41, b2626^0'=b2626^post_41, b2929^0'=b2929^post_41, b3333^0'=b3333^post_41, b3535^0'=b3535^post_41, i^0'=i^post_41, i___01313^0'=i___01313^post_41, i___01717^0'=i___01717^post_41, i___02020^0'=i___02020^post_41, i___02424^0'=i___02424^post_41, i___04040^0'=i___04040^post_41, i___04747^0'=i___04747^post_41, i___099^0'=i___099^post_41, ioA^0'=ioA^post_41, ioR^0'=ioR^post_41, k1^0'=k1^post_41, k2^0'=k2^post_41, k3^0'=k3^post_41, k4^0'=k4^post_41, k5^0'=k5^post_41, keA^0'=keA^post_41, keR^0'=keR^post_41, ntStatus^0'=ntStatus^post_41, pIrb^0'=pIrb^post_41, phi_io_compl^0'=phi_io_compl^post_41, phi_nSUC_ret^0'=phi_nSUC_ret^post_41, prevCancel^0'=prevCancel^post_41, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_41, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_41, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_41, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_41, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_41, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_41, [ 1<=__rho_1_^0 && a11^post_41==DeviceObject^0 && b22^post_41==Irp^0 && ret_t1394Diag_PnpStopDevice33^post_41==0 && ntStatus^post_41==ret_t1394Diag_PnpStopDevice33^post_41 && AsyncAddressData^0==AsyncAddressData^post_41 && BusResetIrp^0==BusResetIrp^post_41 && CromData^0==CromData^post_41 && DeviceObject^0==DeviceObject^post_41 && Irp^0==Irp^post_41 && Irql^0==Irql^post_41 && IsochDetachData^0==IsochDetachData^post_41 && IsochResourceData^0==IsochResourceData^post_41 && ResourceIrp^0==ResourceIrp^post_41 && StackSize^0==StackSize^post_41 && __rho_10_^0==__rho_10_^post_41 && __rho_11_^0==__rho_11_^post_41 && __rho_12_^0==__rho_12_^post_41 && __rho_1_^0==__rho_1_^post_41 && __rho_2_^0==__rho_2_^post_41 && __rho_3_^0==__rho_3_^post_41 && __rho_4_^0==__rho_4_^post_41 && __rho_5_^0==__rho_5_^post_41 && __rho_666_^0==__rho_666_^post_41 && __rho_7_^0==__rho_7_^post_41 && __rho_8_^0==__rho_8_^post_41 && __rho_9_^0==__rho_9_^post_41 && a1818^0==a1818^post_41 && a2525^0==a2525^post_41 && a2828^0==a2828^post_41 && a3131^0==a3131^post_41 && a3232^0==a3232^post_41 && a3434^0==a3434^post_41 && a3737^0==a3737^post_41 && a3838^0==a3838^post_41 && a4343^0==a4343^post_41 && a4545^0==a4545^post_41 && a77^0==a77^post_41 && b2626^0==b2626^post_41 && b2929^0==b2929^post_41 && b3333^0==b3333^post_41 && b3535^0==b3535^post_41 && i^0==i^post_41 && i___01313^0==i___01313^post_41 && i___01717^0==i___01717^post_41 && i___02020^0==i___02020^post_41 && i___02424^0==i___02424^post_41 && i___04040^0==i___04040^post_41 && i___04747^0==i___04747^post_41 && i___099^0==i___099^post_41 && ioA^0==ioA^post_41 && ioR^0==ioR^post_41 && k1^0==k1^post_41 && k2^0==k2^post_41 && k3^0==k3^post_41 && k4^0==k4^post_41 && k5^0==k5^post_41 && keA^0==keA^post_41 && keR^0==keR^post_41 && pIrb^0==pIrb^post_41 && phi_io_compl^0==phi_io_compl^post_41 && phi_nSUC_ret^0==phi_nSUC_ret^post_41 && prevCancel^0==prevCancel^post_41 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_41 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_41 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_41 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_41 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_41 ], cost: 1
     41: l29 -> l1 : AsyncAddressData^0'=AsyncAddressData^post_42, BusResetIrp^0'=BusResetIrp^post_42, CromData^0'=CromData^post_42, DeviceObject^0'=DeviceObject^post_42, Irp^0'=Irp^post_42, Irql^0'=Irql^post_42, IsochDetachData^0'=IsochDetachData^post_42, IsochResourceData^0'=IsochResourceData^post_42, ResourceIrp^0'=ResourceIrp^post_42, StackSize^0'=StackSize^post_42, __rho_10_^0'=__rho_10_^post_42, __rho_11_^0'=__rho_11_^post_42, __rho_12_^0'=__rho_12_^post_42, __rho_1_^0'=__rho_1_^post_42, __rho_2_^0'=__rho_2_^post_42, __rho_3_^0'=__rho_3_^post_42, __rho_4_^0'=__rho_4_^post_42, __rho_5_^0'=__rho_5_^post_42, __rho_666_^0'=__rho_666_^post_42, __rho_7_^0'=__rho_7_^post_42, __rho_8_^0'=__rho_8_^post_42, __rho_9_^0'=__rho_9_^post_42, a11^0'=a11^post_42, a1818^0'=a1818^post_42, a2525^0'=a2525^post_42, a2828^0'=a2828^post_42, a3131^0'=a3131^post_42, a3232^0'=a3232^post_42, a3434^0'=a3434^post_42, a3737^0'=a3737^post_42, a3838^0'=a3838^post_42, a4343^0'=a4343^post_42, a4545^0'=a4545^post_42, a77^0'=a77^post_42, b22^0'=b22^post_42, b2626^0'=b2626^post_42, b2929^0'=b2929^post_42, b3333^0'=b3333^post_42, b3535^0'=b3535^post_42, i^0'=i^post_42, i___01313^0'=i___01313^post_42, i___01717^0'=i___01717^post_42, i___02020^0'=i___02020^post_42, i___02424^0'=i___02424^post_42, i___04040^0'=i___04040^post_42, i___04747^0'=i___04747^post_42, i___099^0'=i___099^post_42, ioA^0'=ioA^post_42, ioR^0'=ioR^post_42, k1^0'=k1^post_42, k2^0'=k2^post_42, k3^0'=k3^post_42, k4^0'=k4^post_42, k5^0'=k5^post_42, keA^0'=keA^post_42, keR^0'=keR^post_42, ntStatus^0'=ntStatus^post_42, pIrb^0'=pIrb^post_42, phi_io_compl^0'=phi_io_compl^post_42, phi_nSUC_ret^0'=phi_nSUC_ret^post_42, prevCancel^0'=prevCancel^post_42, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_42, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_42, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_42, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_42, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_42, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_42, [ 1<=pIrb^0 && a3232^post_42==pIrb^0 && b3333^post_42==0 && a3434^post_42==ResourceIrp^0 && b3535^post_42==pIrb^0 && ret_t1394_SubmitIrpSynch3636^post_42==0 && ntStatus^post_42==ret_t1394_SubmitIrpSynch3636^post_42 && a3737^post_42==pIrb^0 && a3838^post_42==ResourceIrp^0 && AsyncAddressData^0==AsyncAddressData^post_42 && BusResetIrp^0==BusResetIrp^post_42 && CromData^0==CromData^post_42 && DeviceObject^0==DeviceObject^post_42 && Irp^0==Irp^post_42 && Irql^0==Irql^post_42 && IsochDetachData^0==IsochDetachData^post_42 && IsochResourceData^0==IsochResourceData^post_42 && ResourceIrp^0==ResourceIrp^post_42 && StackSize^0==StackSize^post_42 && __rho_10_^0==__rho_10_^post_42 && __rho_11_^0==__rho_11_^post_42 && __rho_12_^0==__rho_12_^post_42 && __rho_1_^0==__rho_1_^post_42 && __rho_2_^0==__rho_2_^post_42 && __rho_3_^0==__rho_3_^post_42 && __rho_4_^0==__rho_4_^post_42 && __rho_5_^0==__rho_5_^post_42 && __rho_666_^0==__rho_666_^post_42 && __rho_7_^0==__rho_7_^post_42 && __rho_8_^0==__rho_8_^post_42 && __rho_9_^0==__rho_9_^post_42 && a11^0==a11^post_42 && a1818^0==a1818^post_42 && a2525^0==a2525^post_42 && a2828^0==a2828^post_42 && a3131^0==a3131^post_42 && a4343^0==a4343^post_42 && a4545^0==a4545^post_42 && a77^0==a77^post_42 && b22^0==b22^post_42 && b2626^0==b2626^post_42 && b2929^0==b2929^post_42 && i^0==i^post_42 && i___01313^0==i___01313^post_42 && i___01717^0==i___01717^post_42 && i___02020^0==i___02020^post_42 && i___02424^0==i___02424^post_42 && i___04040^0==i___04040^post_42 && i___04747^0==i___04747^post_42 && i___099^0==i___099^post_42 && ioA^0==ioA^post_42 && ioR^0==ioR^post_42 && k1^0==k1^post_42 && k2^0==k2^post_42 && k3^0==k3^post_42 && k4^0==k4^post_42 && k5^0==k5^post_42 && keA^0==keA^post_42 && keR^0==keR^post_42 && pIrb^0==pIrb^post_42 && phi_io_compl^0==phi_io_compl^post_42 && phi_nSUC_ret^0==phi_nSUC_ret^post_42 && prevCancel^0==prevCancel^post_42 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_42 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_42 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_42 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_42 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_42 ], cost: 1
     42: l29 -> l1 : AsyncAddressData^0'=AsyncAddressData^post_43, BusResetIrp^0'=BusResetIrp^post_43, CromData^0'=CromData^post_43, DeviceObject^0'=DeviceObject^post_43, Irp^0'=Irp^post_43, Irql^0'=Irql^post_43, IsochDetachData^0'=IsochDetachData^post_43, IsochResourceData^0'=IsochResourceData^post_43, ResourceIrp^0'=ResourceIrp^post_43, StackSize^0'=StackSize^post_43, __rho_10_^0'=__rho_10_^post_43, __rho_11_^0'=__rho_11_^post_43, __rho_12_^0'=__rho_12_^post_43, __rho_1_^0'=__rho_1_^post_43, __rho_2_^0'=__rho_2_^post_43, __rho_3_^0'=__rho_3_^post_43, __rho_4_^0'=__rho_4_^post_43, __rho_5_^0'=__rho_5_^post_43, __rho_666_^0'=__rho_666_^post_43, __rho_7_^0'=__rho_7_^post_43, __rho_8_^0'=__rho_8_^post_43, __rho_9_^0'=__rho_9_^post_43, a11^0'=a11^post_43, a1818^0'=a1818^post_43, a2525^0'=a2525^post_43, a2828^0'=a2828^post_43, a3131^0'=a3131^post_43, a3232^0'=a3232^post_43, a3434^0'=a3434^post_43, a3737^0'=a3737^post_43, a3838^0'=a3838^post_43, a4343^0'=a4343^post_43, a4545^0'=a4545^post_43, a77^0'=a77^post_43, b22^0'=b22^post_43, b2626^0'=b2626^post_43, b2929^0'=b2929^post_43, b3333^0'=b3333^post_43, b3535^0'=b3535^post_43, i^0'=i^post_43, i___01313^0'=i___01313^post_43, i___01717^0'=i___01717^post_43, i___02020^0'=i___02020^post_43, i___02424^0'=i___02424^post_43, i___04040^0'=i___04040^post_43, i___04747^0'=i___04747^post_43, i___099^0'=i___099^post_43, ioA^0'=ioA^post_43, ioR^0'=ioR^post_43, k1^0'=k1^post_43, k2^0'=k2^post_43, k3^0'=k3^post_43, k4^0'=k4^post_43, k5^0'=k5^post_43, keA^0'=keA^post_43, keR^0'=keR^post_43, ntStatus^0'=ntStatus^post_43, pIrb^0'=pIrb^post_43, phi_io_compl^0'=phi_io_compl^post_43, phi_nSUC_ret^0'=phi_nSUC_ret^post_43, prevCancel^0'=prevCancel^post_43, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_43, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_43, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_43, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_43, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_43, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_43, [ pIrb^0<=0 && a3131^post_43==ResourceIrp^0 && AsyncAddressData^0==AsyncAddressData^post_43 && BusResetIrp^0==BusResetIrp^post_43 && CromData^0==CromData^post_43 && DeviceObject^0==DeviceObject^post_43 && Irp^0==Irp^post_43 && Irql^0==Irql^post_43 && IsochDetachData^0==IsochDetachData^post_43 && IsochResourceData^0==IsochResourceData^post_43 && ResourceIrp^0==ResourceIrp^post_43 && StackSize^0==StackSize^post_43 && __rho_10_^0==__rho_10_^post_43 && __rho_11_^0==__rho_11_^post_43 && __rho_12_^0==__rho_12_^post_43 && __rho_1_^0==__rho_1_^post_43 && __rho_2_^0==__rho_2_^post_43 && __rho_3_^0==__rho_3_^post_43 && __rho_4_^0==__rho_4_^post_43 && __rho_5_^0==__rho_5_^post_43 && __rho_666_^0==__rho_666_^post_43 && __rho_7_^0==__rho_7_^post_43 && __rho_8_^0==__rho_8_^post_43 && __rho_9_^0==__rho_9_^post_43 && a11^0==a11^post_43 && a1818^0==a1818^post_43 && a2525^0==a2525^post_43 && a2828^0==a2828^post_43 && a3232^0==a3232^post_43 && a3434^0==a3434^post_43 && a3737^0==a3737^post_43 && a3838^0==a3838^post_43 && a4343^0==a4343^post_43 && a4545^0==a4545^post_43 && a77^0==a77^post_43 && b22^0==b22^post_43 && b2626^0==b2626^post_43 && b2929^0==b2929^post_43 && b3333^0==b3333^post_43 && b3535^0==b3535^post_43 && i^0==i^post_43 && i___01313^0==i___01313^post_43 && i___01717^0==i___01717^post_43 && i___02020^0==i___02020^post_43 && i___02424^0==i___02424^post_43 && i___04040^0==i___04040^post_43 && i___04747^0==i___04747^post_43 && i___099^0==i___099^post_43 && ioA^0==ioA^post_43 && ioR^0==ioR^post_43 && k1^0==k1^post_43 && k2^0==k2^post_43 && k3^0==k3^post_43 && k4^0==k4^post_43 && k5^0==k5^post_43 && keA^0==keA^post_43 && keR^0==keR^post_43 && ntStatus^0==ntStatus^post_43 && pIrb^0==pIrb^post_43 && phi_io_compl^0==phi_io_compl^post_43 && phi_nSUC_ret^0==phi_nSUC_ret^post_43 && prevCancel^0==prevCancel^post_43 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_43 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_43 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_43 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_43 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_43 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_43 ], cost: 1
     43: l30 -> l29 : AsyncAddressData^0'=AsyncAddressData^post_44, BusResetIrp^0'=BusResetIrp^post_44, CromData^0'=CromData^post_44, DeviceObject^0'=DeviceObject^post_44, Irp^0'=Irp^post_44, Irql^0'=Irql^post_44, IsochDetachData^0'=IsochDetachData^post_44, IsochResourceData^0'=IsochResourceData^post_44, ResourceIrp^0'=ResourceIrp^post_44, StackSize^0'=StackSize^post_44, __rho_10_^0'=__rho_10_^post_44, __rho_11_^0'=__rho_11_^post_44, __rho_12_^0'=__rho_12_^post_44, __rho_1_^0'=__rho_1_^post_44, __rho_2_^0'=__rho_2_^post_44, __rho_3_^0'=__rho_3_^post_44, __rho_4_^0'=__rho_4_^post_44, __rho_5_^0'=__rho_5_^post_44, __rho_666_^0'=__rho_666_^post_44, __rho_7_^0'=__rho_7_^post_44, __rho_8_^0'=__rho_8_^post_44, __rho_9_^0'=__rho_9_^post_44, a11^0'=a11^post_44, a1818^0'=a1818^post_44, a2525^0'=a2525^post_44, a2828^0'=a2828^post_44, a3131^0'=a3131^post_44, a3232^0'=a3232^post_44, a3434^0'=a3434^post_44, a3737^0'=a3737^post_44, a3838^0'=a3838^post_44, a4343^0'=a4343^post_44, a4545^0'=a4545^post_44, a77^0'=a77^post_44, b22^0'=b22^post_44, b2626^0'=b2626^post_44, b2929^0'=b2929^post_44, b3333^0'=b3333^post_44, b3535^0'=b3535^post_44, i^0'=i^post_44, i___01313^0'=i___01313^post_44, i___01717^0'=i___01717^post_44, i___02020^0'=i___02020^post_44, i___02424^0'=i___02424^post_44, i___04040^0'=i___04040^post_44, i___04747^0'=i___04747^post_44, i___099^0'=i___099^post_44, ioA^0'=ioA^post_44, ioR^0'=ioR^post_44, k1^0'=k1^post_44, k2^0'=k2^post_44, k3^0'=k3^post_44, k4^0'=k4^post_44, k5^0'=k5^post_44, keA^0'=keA^post_44, keR^0'=keR^post_44, ntStatus^0'=ntStatus^post_44, pIrb^0'=pIrb^post_44, phi_io_compl^0'=phi_io_compl^post_44, phi_nSUC_ret^0'=phi_nSUC_ret^post_44, prevCancel^0'=prevCancel^post_44, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_44, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_44, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_44, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_44, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_44, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_44, [ a2828^post_44==1 && b2929^post_44==0 && ret_ExAllocatePool3030^post_44==0 && pIrb^post_44==ret_ExAllocatePool3030^post_44 && AsyncAddressData^0==AsyncAddressData^post_44 && BusResetIrp^0==BusResetIrp^post_44 && CromData^0==CromData^post_44 && DeviceObject^0==DeviceObject^post_44 && Irp^0==Irp^post_44 && Irql^0==Irql^post_44 && IsochDetachData^0==IsochDetachData^post_44 && IsochResourceData^0==IsochResourceData^post_44 && ResourceIrp^0==ResourceIrp^post_44 && StackSize^0==StackSize^post_44 && __rho_10_^0==__rho_10_^post_44 && __rho_11_^0==__rho_11_^post_44 && __rho_12_^0==__rho_12_^post_44 && __rho_1_^0==__rho_1_^post_44 && __rho_2_^0==__rho_2_^post_44 && __rho_3_^0==__rho_3_^post_44 && __rho_4_^0==__rho_4_^post_44 && __rho_5_^0==__rho_5_^post_44 && __rho_666_^0==__rho_666_^post_44 && __rho_7_^0==__rho_7_^post_44 && __rho_8_^0==__rho_8_^post_44 && __rho_9_^0==__rho_9_^post_44 && a11^0==a11^post_44 && a1818^0==a1818^post_44 && a2525^0==a2525^post_44 && a3131^0==a3131^post_44 && a3232^0==a3232^post_44 && a3434^0==a3434^post_44 && a3737^0==a3737^post_44 && a3838^0==a3838^post_44 && a4343^0==a4343^post_44 && a4545^0==a4545^post_44 && a77^0==a77^post_44 && b22^0==b22^post_44 && b2626^0==b2626^post_44 && b3333^0==b3333^post_44 && b3535^0==b3535^post_44 && i^0==i^post_44 && i___01313^0==i___01313^post_44 && i___01717^0==i___01717^post_44 && i___02020^0==i___02020^post_44 && i___02424^0==i___02424^post_44 && i___04040^0==i___04040^post_44 && i___04747^0==i___04747^post_44 && i___099^0==i___099^post_44 && ioA^0==ioA^post_44 && ioR^0==ioR^post_44 && k1^0==k1^post_44 && k2^0==k2^post_44 && k3^0==k3^post_44 && k4^0==k4^post_44 && k5^0==k5^post_44 && keA^0==keA^post_44 && keR^0==keR^post_44 && ntStatus^0==ntStatus^post_44 && phi_io_compl^0==phi_io_compl^post_44 && phi_nSUC_ret^0==phi_nSUC_ret^post_44 && prevCancel^0==prevCancel^post_44 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_44 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_44 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_44 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_44 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_44 ], cost: 1
     44: l31 -> l30 : AsyncAddressData^0'=AsyncAddressData^post_45, BusResetIrp^0'=BusResetIrp^post_45, CromData^0'=CromData^post_45, DeviceObject^0'=DeviceObject^post_45, Irp^0'=Irp^post_45, Irql^0'=Irql^post_45, IsochDetachData^0'=IsochDetachData^post_45, IsochResourceData^0'=IsochResourceData^post_45, ResourceIrp^0'=ResourceIrp^post_45, StackSize^0'=StackSize^post_45, __rho_10_^0'=__rho_10_^post_45, __rho_11_^0'=__rho_11_^post_45, __rho_12_^0'=__rho_12_^post_45, __rho_1_^0'=__rho_1_^post_45, __rho_2_^0'=__rho_2_^post_45, __rho_3_^0'=__rho_3_^post_45, __rho_4_^0'=__rho_4_^post_45, __rho_5_^0'=__rho_5_^post_45, __rho_666_^0'=__rho_666_^post_45, __rho_7_^0'=__rho_7_^post_45, __rho_8_^0'=__rho_8_^post_45, __rho_9_^0'=__rho_9_^post_45, a11^0'=a11^post_45, a1818^0'=a1818^post_45, a2525^0'=a2525^post_45, a2828^0'=a2828^post_45, a3131^0'=a3131^post_45, a3232^0'=a3232^post_45, a3434^0'=a3434^post_45, a3737^0'=a3737^post_45, a3838^0'=a3838^post_45, a4343^0'=a4343^post_45, a4545^0'=a4545^post_45, a77^0'=a77^post_45, b22^0'=b22^post_45, b2626^0'=b2626^post_45, b2929^0'=b2929^post_45, b3333^0'=b3333^post_45, b3535^0'=b3535^post_45, i^0'=i^post_45, i___01313^0'=i___01313^post_45, i___01717^0'=i___01717^post_45, i___02020^0'=i___02020^post_45, i___02424^0'=i___02424^post_45, i___04040^0'=i___04040^post_45, i___04747^0'=i___04747^post_45, i___099^0'=i___099^post_45, ioA^0'=ioA^post_45, ioR^0'=ioR^post_45, k1^0'=k1^post_45, k2^0'=k2^post_45, k3^0'=k3^post_45, k4^0'=k4^post_45, k5^0'=k5^post_45, keA^0'=keA^post_45, keR^0'=keR^post_45, ntStatus^0'=ntStatus^post_45, pIrb^0'=pIrb^post_45, phi_io_compl^0'=phi_io_compl^post_45, phi_nSUC_ret^0'=phi_nSUC_ret^post_45, prevCancel^0'=prevCancel^post_45, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_45, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_45, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_45, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_45, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_45, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_45, [ 1<=ResourceIrp^0 && AsyncAddressData^0==AsyncAddressData^post_45 && BusResetIrp^0==BusResetIrp^post_45 && CromData^0==CromData^post_45 && DeviceObject^0==DeviceObject^post_45 && Irp^0==Irp^post_45 && Irql^0==Irql^post_45 && IsochDetachData^0==IsochDetachData^post_45 && IsochResourceData^0==IsochResourceData^post_45 && ResourceIrp^0==ResourceIrp^post_45 && StackSize^0==StackSize^post_45 && __rho_10_^0==__rho_10_^post_45 && __rho_11_^0==__rho_11_^post_45 && __rho_12_^0==__rho_12_^post_45 && __rho_1_^0==__rho_1_^post_45 && __rho_2_^0==__rho_2_^post_45 && __rho_3_^0==__rho_3_^post_45 && __rho_4_^0==__rho_4_^post_45 && __rho_5_^0==__rho_5_^post_45 && __rho_666_^0==__rho_666_^post_45 && __rho_7_^0==__rho_7_^post_45 && __rho_8_^0==__rho_8_^post_45 && __rho_9_^0==__rho_9_^post_45 && a11^0==a11^post_45 && a1818^0==a1818^post_45 && a2525^0==a2525^post_45 && a2828^0==a2828^post_45 && a3131^0==a3131^post_45 && a3232^0==a3232^post_45 && a3434^0==a3434^post_45 && a3737^0==a3737^post_45 && a3838^0==a3838^post_45 && a4343^0==a4343^post_45 && a4545^0==a4545^post_45 && a77^0==a77^post_45 && b22^0==b22^post_45 && b2626^0==b2626^post_45 && b2929^0==b2929^post_45 && b3333^0==b3333^post_45 && b3535^0==b3535^post_45 && i^0==i^post_45 && i___01313^0==i___01313^post_45 && i___01717^0==i___01717^post_45 && i___02020^0==i___02020^post_45 && i___02424^0==i___02424^post_45 && i___04040^0==i___04040^post_45 && i___04747^0==i___04747^post_45 && i___099^0==i___099^post_45 && ioA^0==ioA^post_45 && ioR^0==ioR^post_45 && k1^0==k1^post_45 && k2^0==k2^post_45 && k3^0==k3^post_45 && k4^0==k4^post_45 && k5^0==k5^post_45 && keA^0==keA^post_45 && keR^0==keR^post_45 && ntStatus^0==ntStatus^post_45 && pIrb^0==pIrb^post_45 && phi_io_compl^0==phi_io_compl^post_45 && phi_nSUC_ret^0==phi_nSUC_ret^post_45 && prevCancel^0==prevCancel^post_45 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_45 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_45 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_45 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_45 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_45 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_45 ], cost: 1
     45: l31 -> l30 : AsyncAddressData^0'=AsyncAddressData^post_46, BusResetIrp^0'=BusResetIrp^post_46, CromData^0'=CromData^post_46, DeviceObject^0'=DeviceObject^post_46, Irp^0'=Irp^post_46, Irql^0'=Irql^post_46, IsochDetachData^0'=IsochDetachData^post_46, IsochResourceData^0'=IsochResourceData^post_46, ResourceIrp^0'=ResourceIrp^post_46, StackSize^0'=StackSize^post_46, __rho_10_^0'=__rho_10_^post_46, __rho_11_^0'=__rho_11_^post_46, __rho_12_^0'=__rho_12_^post_46, __rho_1_^0'=__rho_1_^post_46, __rho_2_^0'=__rho_2_^post_46, __rho_3_^0'=__rho_3_^post_46, __rho_4_^0'=__rho_4_^post_46, __rho_5_^0'=__rho_5_^post_46, __rho_666_^0'=__rho_666_^post_46, __rho_7_^0'=__rho_7_^post_46, __rho_8_^0'=__rho_8_^post_46, __rho_9_^0'=__rho_9_^post_46, a11^0'=a11^post_46, a1818^0'=a1818^post_46, a2525^0'=a2525^post_46, a2828^0'=a2828^post_46, a3131^0'=a3131^post_46, a3232^0'=a3232^post_46, a3434^0'=a3434^post_46, a3737^0'=a3737^post_46, a3838^0'=a3838^post_46, a4343^0'=a4343^post_46, a4545^0'=a4545^post_46, a77^0'=a77^post_46, b22^0'=b22^post_46, b2626^0'=b2626^post_46, b2929^0'=b2929^post_46, b3333^0'=b3333^post_46, b3535^0'=b3535^post_46, i^0'=i^post_46, i___01313^0'=i___01313^post_46, i___01717^0'=i___01717^post_46, i___02020^0'=i___02020^post_46, i___02424^0'=i___02424^post_46, i___04040^0'=i___04040^post_46, i___04747^0'=i___04747^post_46, i___099^0'=i___099^post_46, ioA^0'=ioA^post_46, ioR^0'=ioR^post_46, k1^0'=k1^post_46, k2^0'=k2^post_46, k3^0'=k3^post_46, k4^0'=k4^post_46, k5^0'=k5^post_46, keA^0'=keA^post_46, keR^0'=keR^post_46, ntStatus^0'=ntStatus^post_46, pIrb^0'=pIrb^post_46, phi_io_compl^0'=phi_io_compl^post_46, phi_nSUC_ret^0'=phi_nSUC_ret^post_46, prevCancel^0'=prevCancel^post_46, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_46, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_46, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_46, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_46, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_46, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_46, [ 1+ResourceIrp^0<=0 && AsyncAddressData^0==AsyncAddressData^post_46 && BusResetIrp^0==BusResetIrp^post_46 && CromData^0==CromData^post_46 && DeviceObject^0==DeviceObject^post_46 && Irp^0==Irp^post_46 && Irql^0==Irql^post_46 && IsochDetachData^0==IsochDetachData^post_46 && IsochResourceData^0==IsochResourceData^post_46 && ResourceIrp^0==ResourceIrp^post_46 && StackSize^0==StackSize^post_46 && __rho_10_^0==__rho_10_^post_46 && __rho_11_^0==__rho_11_^post_46 && __rho_12_^0==__rho_12_^post_46 && __rho_1_^0==__rho_1_^post_46 && __rho_2_^0==__rho_2_^post_46 && __rho_3_^0==__rho_3_^post_46 && __rho_4_^0==__rho_4_^post_46 && __rho_5_^0==__rho_5_^post_46 && __rho_666_^0==__rho_666_^post_46 && __rho_7_^0==__rho_7_^post_46 && __rho_8_^0==__rho_8_^post_46 && __rho_9_^0==__rho_9_^post_46 && a11^0==a11^post_46 && a1818^0==a1818^post_46 && a2525^0==a2525^post_46 && a2828^0==a2828^post_46 && a3131^0==a3131^post_46 && a3232^0==a3232^post_46 && a3434^0==a3434^post_46 && a3737^0==a3737^post_46 && a3838^0==a3838^post_46 && a4343^0==a4343^post_46 && a4545^0==a4545^post_46 && a77^0==a77^post_46 && b22^0==b22^post_46 && b2626^0==b2626^post_46 && b2929^0==b2929^post_46 && b3333^0==b3333^post_46 && b3535^0==b3535^post_46 && i^0==i^post_46 && i___01313^0==i___01313^post_46 && i___01717^0==i___01717^post_46 && i___02020^0==i___02020^post_46 && i___02424^0==i___02424^post_46 && i___04040^0==i___04040^post_46 && i___04747^0==i___04747^post_46 && i___099^0==i___099^post_46 && ioA^0==ioA^post_46 && ioR^0==ioR^post_46 && k1^0==k1^post_46 && k2^0==k2^post_46 && k3^0==k3^post_46 && k4^0==k4^post_46 && k5^0==k5^post_46 && keA^0==keA^post_46 && keR^0==keR^post_46 && ntStatus^0==ntStatus^post_46 && pIrb^0==pIrb^post_46 && phi_io_compl^0==phi_io_compl^post_46 && phi_nSUC_ret^0==phi_nSUC_ret^post_46 && prevCancel^0==prevCancel^post_46 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_46 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_46 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_46 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_46 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_46 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_46 ], cost: 1
     46: l31 -> l1 : AsyncAddressData^0'=AsyncAddressData^post_47, BusResetIrp^0'=BusResetIrp^post_47, CromData^0'=CromData^post_47, DeviceObject^0'=DeviceObject^post_47, Irp^0'=Irp^post_47, Irql^0'=Irql^post_47, IsochDetachData^0'=IsochDetachData^post_47, IsochResourceData^0'=IsochResourceData^post_47, ResourceIrp^0'=ResourceIrp^post_47, StackSize^0'=StackSize^post_47, __rho_10_^0'=__rho_10_^post_47, __rho_11_^0'=__rho_11_^post_47, __rho_12_^0'=__rho_12_^post_47, __rho_1_^0'=__rho_1_^post_47, __rho_2_^0'=__rho_2_^post_47, __rho_3_^0'=__rho_3_^post_47, __rho_4_^0'=__rho_4_^post_47, __rho_5_^0'=__rho_5_^post_47, __rho_666_^0'=__rho_666_^post_47, __rho_7_^0'=__rho_7_^post_47, __rho_8_^0'=__rho_8_^post_47, __rho_9_^0'=__rho_9_^post_47, a11^0'=a11^post_47, a1818^0'=a1818^post_47, a2525^0'=a2525^post_47, a2828^0'=a2828^post_47, a3131^0'=a3131^post_47, a3232^0'=a3232^post_47, a3434^0'=a3434^post_47, a3737^0'=a3737^post_47, a3838^0'=a3838^post_47, a4343^0'=a4343^post_47, a4545^0'=a4545^post_47, a77^0'=a77^post_47, b22^0'=b22^post_47, b2626^0'=b2626^post_47, b2929^0'=b2929^post_47, b3333^0'=b3333^post_47, b3535^0'=b3535^post_47, i^0'=i^post_47, i___01313^0'=i___01313^post_47, i___01717^0'=i___01717^post_47, i___02020^0'=i___02020^post_47, i___02424^0'=i___02424^post_47, i___04040^0'=i___04040^post_47, i___04747^0'=i___04747^post_47, i___099^0'=i___099^post_47, ioA^0'=ioA^post_47, ioR^0'=ioR^post_47, k1^0'=k1^post_47, k2^0'=k2^post_47, k3^0'=k3^post_47, k4^0'=k4^post_47, k5^0'=k5^post_47, keA^0'=keA^post_47, keR^0'=keR^post_47, ntStatus^0'=ntStatus^post_47, pIrb^0'=pIrb^post_47, phi_io_compl^0'=phi_io_compl^post_47, phi_nSUC_ret^0'=phi_nSUC_ret^post_47, prevCancel^0'=prevCancel^post_47, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_47, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_47, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_47, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_47, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_47, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_47, [ ResourceIrp^0<=0 && 0<=ResourceIrp^0 && AsyncAddressData^0==AsyncAddressData^post_47 && BusResetIrp^0==BusResetIrp^post_47 && CromData^0==CromData^post_47 && DeviceObject^0==DeviceObject^post_47 && Irp^0==Irp^post_47 && Irql^0==Irql^post_47 && IsochDetachData^0==IsochDetachData^post_47 && IsochResourceData^0==IsochResourceData^post_47 && ResourceIrp^0==ResourceIrp^post_47 && StackSize^0==StackSize^post_47 && __rho_10_^0==__rho_10_^post_47 && __rho_11_^0==__rho_11_^post_47 && __rho_12_^0==__rho_12_^post_47 && __rho_1_^0==__rho_1_^post_47 && __rho_2_^0==__rho_2_^post_47 && __rho_3_^0==__rho_3_^post_47 && __rho_4_^0==__rho_4_^post_47 && __rho_5_^0==__rho_5_^post_47 && __rho_666_^0==__rho_666_^post_47 && __rho_7_^0==__rho_7_^post_47 && __rho_8_^0==__rho_8_^post_47 && __rho_9_^0==__rho_9_^post_47 && a11^0==a11^post_47 && a1818^0==a1818^post_47 && a2525^0==a2525^post_47 && a2828^0==a2828^post_47 && a3131^0==a3131^post_47 && a3232^0==a3232^post_47 && a3434^0==a3434^post_47 && a3737^0==a3737^post_47 && a3838^0==a3838^post_47 && a4343^0==a4343^post_47 && a4545^0==a4545^post_47 && a77^0==a77^post_47 && b22^0==b22^post_47 && b2626^0==b2626^post_47 && b2929^0==b2929^post_47 && b3333^0==b3333^post_47 && b3535^0==b3535^post_47 && i^0==i^post_47 && i___01313^0==i___01313^post_47 && i___01717^0==i___01717^post_47 && i___02020^0==i___02020^post_47 && i___02424^0==i___02424^post_47 && i___04040^0==i___04040^post_47 && i___04747^0==i___04747^post_47 && i___099^0==i___099^post_47 && ioA^0==ioA^post_47 && ioR^0==ioR^post_47 && k1^0==k1^post_47 && k2^0==k2^post_47 && k3^0==k3^post_47 && k4^0==k4^post_47 && k5^0==k5^post_47 && keA^0==keA^post_47 && keR^0==keR^post_47 && ntStatus^0==ntStatus^post_47 && pIrb^0==pIrb^post_47 && phi_io_compl^0==phi_io_compl^post_47 && phi_nSUC_ret^0==phi_nSUC_ret^post_47 && prevCancel^0==prevCancel^post_47 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_47 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_47 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_47 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_47 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_47 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_47 ], cost: 1
     47: l32 -> l1 : AsyncAddressData^0'=AsyncAddressData^post_48, BusResetIrp^0'=BusResetIrp^post_48, CromData^0'=CromData^post_48, DeviceObject^0'=DeviceObject^post_48, Irp^0'=Irp^post_48, Irql^0'=Irql^post_48, IsochDetachData^0'=IsochDetachData^post_48, IsochResourceData^0'=IsochResourceData^post_48, ResourceIrp^0'=ResourceIrp^post_48, StackSize^0'=StackSize^post_48, __rho_10_^0'=__rho_10_^post_48, __rho_11_^0'=__rho_11_^post_48, __rho_12_^0'=__rho_12_^post_48, __rho_1_^0'=__rho_1_^post_48, __rho_2_^0'=__rho_2_^post_48, __rho_3_^0'=__rho_3_^post_48, __rho_4_^0'=__rho_4_^post_48, __rho_5_^0'=__rho_5_^post_48, __rho_666_^0'=__rho_666_^post_48, __rho_7_^0'=__rho_7_^post_48, __rho_8_^0'=__rho_8_^post_48, __rho_9_^0'=__rho_9_^post_48, a11^0'=a11^post_48, a1818^0'=a1818^post_48, a2525^0'=a2525^post_48, a2828^0'=a2828^post_48, a3131^0'=a3131^post_48, a3232^0'=a3232^post_48, a3434^0'=a3434^post_48, a3737^0'=a3737^post_48, a3838^0'=a3838^post_48, a4343^0'=a4343^post_48, a4545^0'=a4545^post_48, a77^0'=a77^post_48, b22^0'=b22^post_48, b2626^0'=b2626^post_48, b2929^0'=b2929^post_48, b3333^0'=b3333^post_48, b3535^0'=b3535^post_48, i^0'=i^post_48, i___01313^0'=i___01313^post_48, i___01717^0'=i___01717^post_48, i___02020^0'=i___02020^post_48, i___02424^0'=i___02424^post_48, i___04040^0'=i___04040^post_48, i___04747^0'=i___04747^post_48, i___099^0'=i___099^post_48, ioA^0'=ioA^post_48, ioR^0'=ioR^post_48, k1^0'=k1^post_48, k2^0'=k2^post_48, k3^0'=k3^post_48, k4^0'=k4^post_48, k5^0'=k5^post_48, keA^0'=keA^post_48, keR^0'=keR^post_48, ntStatus^0'=ntStatus^post_48, pIrb^0'=pIrb^post_48, phi_io_compl^0'=phi_io_compl^post_48, phi_nSUC_ret^0'=phi_nSUC_ret^post_48, prevCancel^0'=prevCancel^post_48, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_48, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_48, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_48, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_48, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_48, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_48, [ IsochResourceData^0<=0 && AsyncAddressData^0==AsyncAddressData^post_48 && BusResetIrp^0==BusResetIrp^post_48 && CromData^0==CromData^post_48 && DeviceObject^0==DeviceObject^post_48 && Irp^0==Irp^post_48 && Irql^0==Irql^post_48 && IsochDetachData^0==IsochDetachData^post_48 && IsochResourceData^0==IsochResourceData^post_48 && ResourceIrp^0==ResourceIrp^post_48 && StackSize^0==StackSize^post_48 && __rho_10_^0==__rho_10_^post_48 && __rho_11_^0==__rho_11_^post_48 && __rho_12_^0==__rho_12_^post_48 && __rho_1_^0==__rho_1_^post_48 && __rho_2_^0==__rho_2_^post_48 && __rho_3_^0==__rho_3_^post_48 && __rho_4_^0==__rho_4_^post_48 && __rho_5_^0==__rho_5_^post_48 && __rho_666_^0==__rho_666_^post_48 && __rho_7_^0==__rho_7_^post_48 && __rho_8_^0==__rho_8_^post_48 && __rho_9_^0==__rho_9_^post_48 && a11^0==a11^post_48 && a1818^0==a1818^post_48 && a2525^0==a2525^post_48 && a2828^0==a2828^post_48 && a3131^0==a3131^post_48 && a3232^0==a3232^post_48 && a3434^0==a3434^post_48 && a3737^0==a3737^post_48 && a3838^0==a3838^post_48 && a4343^0==a4343^post_48 && a4545^0==a4545^post_48 && a77^0==a77^post_48 && b22^0==b22^post_48 && b2626^0==b2626^post_48 && b2929^0==b2929^post_48 && b3333^0==b3333^post_48 && b3535^0==b3535^post_48 && i^0==i^post_48 && i___01313^0==i___01313^post_48 && i___01717^0==i___01717^post_48 && i___02020^0==i___02020^post_48 && i___02424^0==i___02424^post_48 && i___04040^0==i___04040^post_48 && i___04747^0==i___04747^post_48 && i___099^0==i___099^post_48 && ioA^0==ioA^post_48 && ioR^0==ioR^post_48 && k1^0==k1^post_48 && k2^0==k2^post_48 && k3^0==k3^post_48 && k4^0==k4^post_48 && k5^0==k5^post_48 && keA^0==keA^post_48 && keR^0==keR^post_48 && ntStatus^0==ntStatus^post_48 && pIrb^0==pIrb^post_48 && phi_io_compl^0==phi_io_compl^post_48 && phi_nSUC_ret^0==phi_nSUC_ret^post_48 && prevCancel^0==prevCancel^post_48 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_48 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_48 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_48 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_48 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_48 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_48 ], cost: 1
     48: l32 -> l31 : AsyncAddressData^0'=AsyncAddressData^post_49, BusResetIrp^0'=BusResetIrp^post_49, CromData^0'=CromData^post_49, DeviceObject^0'=DeviceObject^post_49, Irp^0'=Irp^post_49, Irql^0'=Irql^post_49, IsochDetachData^0'=IsochDetachData^post_49, IsochResourceData^0'=IsochResourceData^post_49, ResourceIrp^0'=ResourceIrp^post_49, StackSize^0'=StackSize^post_49, __rho_10_^0'=__rho_10_^post_49, __rho_11_^0'=__rho_11_^post_49, __rho_12_^0'=__rho_12_^post_49, __rho_1_^0'=__rho_1_^post_49, __rho_2_^0'=__rho_2_^post_49, __rho_3_^0'=__rho_3_^post_49, __rho_4_^0'=__rho_4_^post_49, __rho_5_^0'=__rho_5_^post_49, __rho_666_^0'=__rho_666_^post_49, __rho_7_^0'=__rho_7_^post_49, __rho_8_^0'=__rho_8_^post_49, __rho_9_^0'=__rho_9_^post_49, a11^0'=a11^post_49, a1818^0'=a1818^post_49, a2525^0'=a2525^post_49, a2828^0'=a2828^post_49, a3131^0'=a3131^post_49, a3232^0'=a3232^post_49, a3434^0'=a3434^post_49, a3737^0'=a3737^post_49, a3838^0'=a3838^post_49, a4343^0'=a4343^post_49, a4545^0'=a4545^post_49, a77^0'=a77^post_49, b22^0'=b22^post_49, b2626^0'=b2626^post_49, b2929^0'=b2929^post_49, b3333^0'=b3333^post_49, b3535^0'=b3535^post_49, i^0'=i^post_49, i___01313^0'=i___01313^post_49, i___01717^0'=i___01717^post_49, i___02020^0'=i___02020^post_49, i___02424^0'=i___02424^post_49, i___04040^0'=i___04040^post_49, i___04747^0'=i___04747^post_49, i___099^0'=i___099^post_49, ioA^0'=ioA^post_49, ioR^0'=ioR^post_49, k1^0'=k1^post_49, k2^0'=k2^post_49, k3^0'=k3^post_49, k4^0'=k4^post_49, k5^0'=k5^post_49, keA^0'=keA^post_49, keR^0'=keR^post_49, ntStatus^0'=ntStatus^post_49, pIrb^0'=pIrb^post_49, phi_io_compl^0'=phi_io_compl^post_49, phi_nSUC_ret^0'=phi_nSUC_ret^post_49, prevCancel^0'=prevCancel^post_49, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_49, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_49, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_49, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_49, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_49, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_49, [ 1<=IsochResourceData^0 && pIrb^post_49==pIrb^post_49 && ResourceIrp^1_1==ResourceIrp^1_1 && StackSize^post_49==StackSize^post_49 && a2525^post_49==StackSize^post_49 && b2626^post_49==0 && ret_IoAllocateIrp2727^post_49==0 && ResourceIrp^post_49==ret_IoAllocateIrp2727^post_49 && AsyncAddressData^0==AsyncAddressData^post_49 && BusResetIrp^0==BusResetIrp^post_49 && CromData^0==CromData^post_49 && DeviceObject^0==DeviceObject^post_49 && Irp^0==Irp^post_49 && Irql^0==Irql^post_49 && IsochDetachData^0==IsochDetachData^post_49 && IsochResourceData^0==IsochResourceData^post_49 && __rho_10_^0==__rho_10_^post_49 && __rho_11_^0==__rho_11_^post_49 && __rho_12_^0==__rho_12_^post_49 && __rho_1_^0==__rho_1_^post_49 && __rho_2_^0==__rho_2_^post_49 && __rho_3_^0==__rho_3_^post_49 && __rho_4_^0==__rho_4_^post_49 && __rho_5_^0==__rho_5_^post_49 && __rho_666_^0==__rho_666_^post_49 && __rho_7_^0==__rho_7_^post_49 && __rho_8_^0==__rho_8_^post_49 && __rho_9_^0==__rho_9_^post_49 && a11^0==a11^post_49 && a1818^0==a1818^post_49 && a2828^0==a2828^post_49 && a3131^0==a3131^post_49 && a3232^0==a3232^post_49 && a3434^0==a3434^post_49 && a3737^0==a3737^post_49 && a3838^0==a3838^post_49 && a4343^0==a4343^post_49 && a4545^0==a4545^post_49 && a77^0==a77^post_49 && b22^0==b22^post_49 && b2929^0==b2929^post_49 && b3333^0==b3333^post_49 && b3535^0==b3535^post_49 && i^0==i^post_49 && i___01313^0==i___01313^post_49 && i___01717^0==i___01717^post_49 && i___02020^0==i___02020^post_49 && i___02424^0==i___02424^post_49 && i___04040^0==i___04040^post_49 && i___04747^0==i___04747^post_49 && i___099^0==i___099^post_49 && ioA^0==ioA^post_49 && ioR^0==ioR^post_49 && k1^0==k1^post_49 && k2^0==k2^post_49 && k3^0==k3^post_49 && k4^0==k4^post_49 && k5^0==k5^post_49 && keA^0==keA^post_49 && keR^0==keR^post_49 && ntStatus^0==ntStatus^post_49 && phi_io_compl^0==phi_io_compl^post_49 && phi_nSUC_ret^0==phi_nSUC_ret^post_49 && prevCancel^0==prevCancel^post_49 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_49 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_49 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_49 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_49 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_49 ], cost: 1
     51: l33 -> l28 : AsyncAddressData^0'=AsyncAddressData^post_52, BusResetIrp^0'=BusResetIrp^post_52, CromData^0'=CromData^post_52, DeviceObject^0'=DeviceObject^post_52, Irp^0'=Irp^post_52, Irql^0'=Irql^post_52, IsochDetachData^0'=IsochDetachData^post_52, IsochResourceData^0'=IsochResourceData^post_52, ResourceIrp^0'=ResourceIrp^post_52, StackSize^0'=StackSize^post_52, __rho_10_^0'=__rho_10_^post_52, __rho_11_^0'=__rho_11_^post_52, __rho_12_^0'=__rho_12_^post_52, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_52, __rho_3_^0'=__rho_3_^post_52, __rho_4_^0'=__rho_4_^post_52, __rho_5_^0'=__rho_5_^post_52, __rho_666_^0'=__rho_666_^post_52, __rho_7_^0'=__rho_7_^post_52, __rho_8_^0'=__rho_8_^post_52, __rho_9_^0'=__rho_9_^post_52, a11^0'=a11^post_52, a1818^0'=a1818^post_52, a2525^0'=a2525^post_52, a2828^0'=a2828^post_52, a3131^0'=a3131^post_52, a3232^0'=a3232^post_52, a3434^0'=a3434^post_52, a3737^0'=a3737^post_52, a3838^0'=a3838^post_52, a4343^0'=a4343^post_52, a4545^0'=a4545^post_52, a77^0'=a77^post_52, b22^0'=b22^post_52, b2626^0'=b2626^post_52, b2929^0'=b2929^post_52, b3333^0'=b3333^post_52, b3535^0'=b3535^post_52, i^0'=i^post_52, i___01313^0'=i___01313^post_52, i___01717^0'=i___01717^post_52, i___02020^0'=i___02020^post_52, i___02424^0'=i___02424^post_52, i___04040^0'=i___04040^post_52, i___04747^0'=i___04747^post_52, i___099^0'=i___099^post_52, ioA^0'=ioA^post_52, ioR^0'=ioR^post_52, k1^0'=k1^post_52, k2^0'=k2^post_52, k3^0'=k3^post_52, k4^0'=k4^post_52, k5^0'=k5^post_52, keA^0'=keA^post_52, keR^0'=keR^post_52, ntStatus^0'=ntStatus^post_52, pIrb^0'=pIrb^post_52, phi_io_compl^0'=phi_io_compl^post_52, phi_nSUC_ret^0'=phi_nSUC_ret^post_52, prevCancel^0'=prevCancel^post_52, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_52, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_52, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_52, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_52, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_52, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_52, [ ioR^post_52==0 && ioA^post_52==ioR^post_52 && keR^post_52==ioA^post_52 && keA^post_52==keR^post_52 && phi_nSUC_ret^post_52==0 && phi_io_compl^post_52==0 && __rho_666_^post_52==__rho_666_^post_52 && __rho_1_^post_52==__rho_1_^post_52 && AsyncAddressData^0==AsyncAddressData^post_52 && BusResetIrp^0==BusResetIrp^post_52 && CromData^0==CromData^post_52 && DeviceObject^0==DeviceObject^post_52 && Irp^0==Irp^post_52 && Irql^0==Irql^post_52 && IsochDetachData^0==IsochDetachData^post_52 && IsochResourceData^0==IsochResourceData^post_52 && ResourceIrp^0==ResourceIrp^post_52 && StackSize^0==StackSize^post_52 && __rho_10_^0==__rho_10_^post_52 && __rho_11_^0==__rho_11_^post_52 && __rho_12_^0==__rho_12_^post_52 && __rho_2_^0==__rho_2_^post_52 && __rho_3_^0==__rho_3_^post_52 && __rho_4_^0==__rho_4_^post_52 && __rho_5_^0==__rho_5_^post_52 && __rho_7_^0==__rho_7_^post_52 && __rho_8_^0==__rho_8_^post_52 && __rho_9_^0==__rho_9_^post_52 && a11^0==a11^post_52 && a1818^0==a1818^post_52 && a2525^0==a2525^post_52 && a2828^0==a2828^post_52 && a3131^0==a3131^post_52 && a3232^0==a3232^post_52 && a3434^0==a3434^post_52 && a3737^0==a3737^post_52 && a3838^0==a3838^post_52 && a4343^0==a4343^post_52 && a4545^0==a4545^post_52 && a77^0==a77^post_52 && b22^0==b22^post_52 && b2626^0==b2626^post_52 && b2929^0==b2929^post_52 && b3333^0==b3333^post_52 && b3535^0==b3535^post_52 && i^0==i^post_52 && i___01313^0==i___01313^post_52 && i___01717^0==i___01717^post_52 && i___02020^0==i___02020^post_52 && i___02424^0==i___02424^post_52 && i___04040^0==i___04040^post_52 && i___04747^0==i___04747^post_52 && i___099^0==i___099^post_52 && k1^0==k1^post_52 && k2^0==k2^post_52 && k3^0==k3^post_52 && k4^0==k4^post_52 && k5^0==k5^post_52 && ntStatus^0==ntStatus^post_52 && pIrb^0==pIrb^post_52 && prevCancel^0==prevCancel^post_52 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_52 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_52 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_52 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_52 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_52 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_52 ], cost: 1
     52: l34 -> l33 : AsyncAddressData^0'=AsyncAddressData^post_53, BusResetIrp^0'=BusResetIrp^post_53, CromData^0'=CromData^post_53, DeviceObject^0'=DeviceObject^post_53, Irp^0'=Irp^post_53, Irql^0'=Irql^post_53, IsochDetachData^0'=IsochDetachData^post_53, IsochResourceData^0'=IsochResourceData^post_53, ResourceIrp^0'=ResourceIrp^post_53, StackSize^0'=StackSize^post_53, __rho_10_^0'=__rho_10_^post_53, __rho_11_^0'=__rho_11_^post_53, __rho_12_^0'=__rho_12_^post_53, __rho_1_^0'=__rho_1_^post_53, __rho_2_^0'=__rho_2_^post_53, __rho_3_^0'=__rho_3_^post_53, __rho_4_^0'=__rho_4_^post_53, __rho_5_^0'=__rho_5_^post_53, __rho_666_^0'=__rho_666_^post_53, __rho_7_^0'=__rho_7_^post_53, __rho_8_^0'=__rho_8_^post_53, __rho_9_^0'=__rho_9_^post_53, a11^0'=a11^post_53, a1818^0'=a1818^post_53, a2525^0'=a2525^post_53, a2828^0'=a2828^post_53, a3131^0'=a3131^post_53, a3232^0'=a3232^post_53, a3434^0'=a3434^post_53, a3737^0'=a3737^post_53, a3838^0'=a3838^post_53, a4343^0'=a4343^post_53, a4545^0'=a4545^post_53, a77^0'=a77^post_53, b22^0'=b22^post_53, b2626^0'=b2626^post_53, b2929^0'=b2929^post_53, b3333^0'=b3333^post_53, b3535^0'=b3535^post_53, i^0'=i^post_53, i___01313^0'=i___01313^post_53, i___01717^0'=i___01717^post_53, i___02020^0'=i___02020^post_53, i___02424^0'=i___02424^post_53, i___04040^0'=i___04040^post_53, i___04747^0'=i___04747^post_53, i___099^0'=i___099^post_53, ioA^0'=ioA^post_53, ioR^0'=ioR^post_53, k1^0'=k1^post_53, k2^0'=k2^post_53, k3^0'=k3^post_53, k4^0'=k4^post_53, k5^0'=k5^post_53, keA^0'=keA^post_53, keR^0'=keR^post_53, ntStatus^0'=ntStatus^post_53, pIrb^0'=pIrb^post_53, phi_io_compl^0'=phi_io_compl^post_53, phi_nSUC_ret^0'=phi_nSUC_ret^post_53, prevCancel^0'=prevCancel^post_53, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_53, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_53, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_53, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_53, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_53, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_53, [ AsyncAddressData^0==AsyncAddressData^post_53 && BusResetIrp^0==BusResetIrp^post_53 && CromData^0==CromData^post_53 && DeviceObject^0==DeviceObject^post_53 && Irp^0==Irp^post_53 && Irql^0==Irql^post_53 && IsochDetachData^0==IsochDetachData^post_53 && IsochResourceData^0==IsochResourceData^post_53 && ResourceIrp^0==ResourceIrp^post_53 && StackSize^0==StackSize^post_53 && __rho_10_^0==__rho_10_^post_53 && __rho_11_^0==__rho_11_^post_53 && __rho_12_^0==__rho_12_^post_53 && __rho_1_^0==__rho_1_^post_53 && __rho_2_^0==__rho_2_^post_53 && __rho_3_^0==__rho_3_^post_53 && __rho_4_^0==__rho_4_^post_53 && __rho_5_^0==__rho_5_^post_53 && __rho_666_^0==__rho_666_^post_53 && __rho_7_^0==__rho_7_^post_53 && __rho_8_^0==__rho_8_^post_53 && __rho_9_^0==__rho_9_^post_53 && a11^0==a11^post_53 && a1818^0==a1818^post_53 && a2525^0==a2525^post_53 && a2828^0==a2828^post_53 && a3131^0==a3131^post_53 && a3232^0==a3232^post_53 && a3434^0==a3434^post_53 && a3737^0==a3737^post_53 && a3838^0==a3838^post_53 && a4343^0==a4343^post_53 && a4545^0==a4545^post_53 && a77^0==a77^post_53 && b22^0==b22^post_53 && b2626^0==b2626^post_53 && b2929^0==b2929^post_53 && b3333^0==b3333^post_53 && b3535^0==b3535^post_53 && i^0==i^post_53 && i___01313^0==i___01313^post_53 && i___01717^0==i___01717^post_53 && i___02020^0==i___02020^post_53 && i___02424^0==i___02424^post_53 && i___04040^0==i___04040^post_53 && i___04747^0==i___04747^post_53 && i___099^0==i___099^post_53 && ioA^0==ioA^post_53 && ioR^0==ioR^post_53 && k1^0==k1^post_53 && k2^0==k2^post_53 && k3^0==k3^post_53 && k4^0==k4^post_53 && k5^0==k5^post_53 && keA^0==keA^post_53 && keR^0==keR^post_53 && ntStatus^0==ntStatus^post_53 && pIrb^0==pIrb^post_53 && phi_io_compl^0==phi_io_compl^post_53 && phi_nSUC_ret^0==phi_nSUC_ret^post_53 && prevCancel^0==prevCancel^post_53 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_53 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_53 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_53 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_53 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_53 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_53 ], cost: 1

Checking for constant complexity:
   The following rule is satisfiable with cost >= 1, yielding constant complexity:
     52: l34 -> l33 : AsyncAddressData^0'=AsyncAddressData^post_53, BusResetIrp^0'=BusResetIrp^post_53, CromData^0'=CromData^post_53, DeviceObject^0'=DeviceObject^post_53, Irp^0'=Irp^post_53, Irql^0'=Irql^post_53, IsochDetachData^0'=IsochDetachData^post_53, IsochResourceData^0'=IsochResourceData^post_53, ResourceIrp^0'=ResourceIrp^post_53, StackSize^0'=StackSize^post_53, __rho_10_^0'=__rho_10_^post_53, __rho_11_^0'=__rho_11_^post_53, __rho_12_^0'=__rho_12_^post_53, __rho_1_^0'=__rho_1_^post_53, __rho_2_^0'=__rho_2_^post_53, __rho_3_^0'=__rho_3_^post_53, __rho_4_^0'=__rho_4_^post_53, __rho_5_^0'=__rho_5_^post_53, __rho_666_^0'=__rho_666_^post_53, __rho_7_^0'=__rho_7_^post_53, __rho_8_^0'=__rho_8_^post_53, __rho_9_^0'=__rho_9_^post_53, a11^0'=a11^post_53, a1818^0'=a1818^post_53, a2525^0'=a2525^post_53, a2828^0'=a2828^post_53, a3131^0'=a3131^post_53, a3232^0'=a3232^post_53, a3434^0'=a3434^post_53, a3737^0'=a3737^post_53, a3838^0'=a3838^post_53, a4343^0'=a4343^post_53, a4545^0'=a4545^post_53, a77^0'=a77^post_53, b22^0'=b22^post_53, b2626^0'=b2626^post_53, b2929^0'=b2929^post_53, b3333^0'=b3333^post_53, b3535^0'=b3535^post_53, i^0'=i^post_53, i___01313^0'=i___01313^post_53, i___01717^0'=i___01717^post_53, i___02020^0'=i___02020^post_53, i___02424^0'=i___02424^post_53, i___04040^0'=i___04040^post_53, i___04747^0'=i___04747^post_53, i___099^0'=i___099^post_53, ioA^0'=ioA^post_53, ioR^0'=ioR^post_53, k1^0'=k1^post_53, k2^0'=k2^post_53, k3^0'=k3^post_53, k4^0'=k4^post_53, k5^0'=k5^post_53, keA^0'=keA^post_53, keR^0'=keR^post_53, ntStatus^0'=ntStatus^post_53, pIrb^0'=pIrb^post_53, phi_io_compl^0'=phi_io_compl^post_53, phi_nSUC_ret^0'=phi_nSUC_ret^post_53, prevCancel^0'=prevCancel^post_53, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_53, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_53, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_53, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_53, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_53, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_53, [ AsyncAddressData^0==AsyncAddressData^post_53 && BusResetIrp^0==BusResetIrp^post_53 && CromData^0==CromData^post_53 && DeviceObject^0==DeviceObject^post_53 && Irp^0==Irp^post_53 && Irql^0==Irql^post_53 && IsochDetachData^0==IsochDetachData^post_53 && IsochResourceData^0==IsochResourceData^post_53 && ResourceIrp^0==ResourceIrp^post_53 && StackSize^0==StackSize^post_53 && __rho_10_^0==__rho_10_^post_53 && __rho_11_^0==__rho_11_^post_53 && __rho_12_^0==__rho_12_^post_53 && __rho_1_^0==__rho_1_^post_53 && __rho_2_^0==__rho_2_^post_53 && __rho_3_^0==__rho_3_^post_53 && __rho_4_^0==__rho_4_^post_53 && __rho_5_^0==__rho_5_^post_53 && __rho_666_^0==__rho_666_^post_53 && __rho_7_^0==__rho_7_^post_53 && __rho_8_^0==__rho_8_^post_53 && __rho_9_^0==__rho_9_^post_53 && a11^0==a11^post_53 && a1818^0==a1818^post_53 && a2525^0==a2525^post_53 && a2828^0==a2828^post_53 && a3131^0==a3131^post_53 && a3232^0==a3232^post_53 && a3434^0==a3434^post_53 && a3737^0==a3737^post_53 && a3838^0==a3838^post_53 && a4343^0==a4343^post_53 && a4545^0==a4545^post_53 && a77^0==a77^post_53 && b22^0==b22^post_53 && b2626^0==b2626^post_53 && b2929^0==b2929^post_53 && b3333^0==b3333^post_53 && b3535^0==b3535^post_53 && i^0==i^post_53 && i___01313^0==i___01313^post_53 && i___01717^0==i___01717^post_53 && i___02020^0==i___02020^post_53 && i___02424^0==i___02424^post_53 && i___04040^0==i___04040^post_53 && i___04747^0==i___04747^post_53 && i___099^0==i___099^post_53 && ioA^0==ioA^post_53 && ioR^0==ioR^post_53 && k1^0==k1^post_53 && k2^0==k2^post_53 && k3^0==k3^post_53 && k4^0==k4^post_53 && k5^0==k5^post_53 && keA^0==keA^post_53 && keR^0==keR^post_53 && ntStatus^0==ntStatus^post_53 && pIrb^0==pIrb^post_53 && phi_io_compl^0==phi_io_compl^post_53 && phi_nSUC_ret^0==phi_nSUC_ret^post_53 && prevCancel^0==prevCancel^post_53 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_53 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_53 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_53 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_53 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_53 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_53 ], cost: 1

Removed unreachable and leaf rules:
   Start location: l34
      0: l0 -> l1 : AsyncAddressData^0'=AsyncAddressData^post_1, BusResetIrp^0'=BusResetIrp^post_1, CromData^0'=CromData^post_1, DeviceObject^0'=DeviceObject^post_1, Irp^0'=Irp^post_1, Irql^0'=Irql^post_1, IsochDetachData^0'=IsochDetachData^post_1, IsochResourceData^0'=IsochResourceData^post_1, ResourceIrp^0'=ResourceIrp^post_1, StackSize^0'=StackSize^post_1, __rho_10_^0'=__rho_10_^post_1, __rho_11_^0'=__rho_11_^post_1, __rho_12_^0'=__rho_12_^post_1, __rho_1_^0'=__rho_1_^post_1, __rho_2_^0'=__rho_2_^post_1, __rho_3_^0'=__rho_3_^post_1, __rho_4_^0'=__rho_4_^post_1, __rho_5_^0'=__rho_5_^post_1, __rho_666_^0'=__rho_666_^post_1, __rho_7_^0'=__rho_7_^post_1, __rho_8_^0'=__rho_8_^post_1, __rho_9_^0'=__rho_9_^post_1, a11^0'=a11^post_1, a1818^0'=a1818^post_1, a2525^0'=a2525^post_1, a2828^0'=a2828^post_1, a3131^0'=a3131^post_1, a3232^0'=a3232^post_1, a3434^0'=a3434^post_1, a3737^0'=a3737^post_1, a3838^0'=a3838^post_1, a4343^0'=a4343^post_1, a4545^0'=a4545^post_1, a77^0'=a77^post_1, b22^0'=b22^post_1, b2626^0'=b2626^post_1, b2929^0'=b2929^post_1, b3333^0'=b3333^post_1, b3535^0'=b3535^post_1, i^0'=i^post_1, i___01313^0'=i___01313^post_1, i___01717^0'=i___01717^post_1, i___02020^0'=i___02020^post_1, i___02424^0'=i___02424^post_1, i___04040^0'=i___04040^post_1, i___04747^0'=i___04747^post_1, i___099^0'=i___099^post_1, ioA^0'=ioA^post_1, ioR^0'=ioR^post_1, k1^0'=k1^post_1, k2^0'=k2^post_1, k3^0'=k3^post_1, k4^0'=k4^post_1, k5^0'=k5^post_1, keA^0'=keA^post_1, keR^0'=keR^post_1, ntStatus^0'=ntStatus^post_1, pIrb^0'=pIrb^post_1, phi_io_compl^0'=phi_io_compl^post_1, phi_nSUC_ret^0'=phi_nSUC_ret^post_1, prevCancel^0'=prevCancel^post_1, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_1, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_1, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_1, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_1, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_1, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_1, [ k3^0<=0 && i___02020^post_1==Irql^0 && keR^1_1==1 && keR^post_1==0 && __rho_11_^post_1==__rho_11_^post_1 && k4^post_1==__rho_11_^post_1 && AsyncAddressData^0==AsyncAddressData^post_1 && BusResetIrp^0==BusResetIrp^post_1 && CromData^0==CromData^post_1 && DeviceObject^0==DeviceObject^post_1 && Irp^0==Irp^post_1 && Irql^0==Irql^post_1 && IsochDetachData^0==IsochDetachData^post_1 && IsochResourceData^0==IsochResourceData^post_1 && ResourceIrp^0==ResourceIrp^post_1 && StackSize^0==StackSize^post_1 && __rho_10_^0==__rho_10_^post_1 && __rho_12_^0==__rho_12_^post_1 && __rho_1_^0==__rho_1_^post_1 && __rho_2_^0==__rho_2_^post_1 && __rho_3_^0==__rho_3_^post_1 && __rho_4_^0==__rho_4_^post_1 && __rho_5_^0==__rho_5_^post_1 && __rho_666_^0==__rho_666_^post_1 && __rho_7_^0==__rho_7_^post_1 && __rho_8_^0==__rho_8_^post_1 && __rho_9_^0==__rho_9_^post_1 && a11^0==a11^post_1 && a1818^0==a1818^post_1 && a2525^0==a2525^post_1 && a2828^0==a2828^post_1 && a3131^0==a3131^post_1 && a3232^0==a3232^post_1 && a3434^0==a3434^post_1 && a3737^0==a3737^post_1 && a3838^0==a3838^post_1 && a4343^0==a4343^post_1 && a4545^0==a4545^post_1 && a77^0==a77^post_1 && b22^0==b22^post_1 && b2626^0==b2626^post_1 && b2929^0==b2929^post_1 && b3333^0==b3333^post_1 && b3535^0==b3535^post_1 && i^0==i^post_1 && i___01313^0==i___01313^post_1 && i___01717^0==i___01717^post_1 && i___02424^0==i___02424^post_1 && i___04040^0==i___04040^post_1 && i___04747^0==i___04747^post_1 && i___099^0==i___099^post_1 && ioA^0==ioA^post_1 && ioR^0==ioR^post_1 && k1^0==k1^post_1 && k2^0==k2^post_1 && k3^0==k3^post_1 && k5^0==k5^post_1 && keA^0==keA^post_1 && ntStatus^0==ntStatus^post_1 && pIrb^0==pIrb^post_1 && phi_io_compl^0==phi_io_compl^post_1 && phi_nSUC_ret^0==phi_nSUC_ret^post_1 && prevCancel^0==prevCancel^post_1 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_1 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_1 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_1 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_1 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_1 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_1 ], cost: 1
      1: l0 -> l2 : AsyncAddressData^0'=AsyncAddressData^post_2, BusResetIrp^0'=BusResetIrp^post_2, CromData^0'=CromData^post_2, DeviceObject^0'=DeviceObject^post_2, Irp^0'=Irp^post_2, Irql^0'=Irql^post_2, IsochDetachData^0'=IsochDetachData^post_2, IsochResourceData^0'=IsochResourceData^post_2, ResourceIrp^0'=ResourceIrp^post_2, StackSize^0'=StackSize^post_2, __rho_10_^0'=__rho_10_^post_2, __rho_11_^0'=__rho_11_^post_2, __rho_12_^0'=__rho_12_^post_2, __rho_1_^0'=__rho_1_^post_2, __rho_2_^0'=__rho_2_^post_2, __rho_3_^0'=__rho_3_^post_2, __rho_4_^0'=__rho_4_^post_2, __rho_5_^0'=__rho_5_^post_2, __rho_666_^0'=__rho_666_^post_2, __rho_7_^0'=__rho_7_^post_2, __rho_8_^0'=__rho_8_^post_2, __rho_9_^0'=__rho_9_^post_2, a11^0'=a11^post_2, a1818^0'=a1818^post_2, a2525^0'=a2525^post_2, a2828^0'=a2828^post_2, a3131^0'=a3131^post_2, a3232^0'=a3232^post_2, a3434^0'=a3434^post_2, a3737^0'=a3737^post_2, a3838^0'=a3838^post_2, a4343^0'=a4343^post_2, a4545^0'=a4545^post_2, a77^0'=a77^post_2, b22^0'=b22^post_2, b2626^0'=b2626^post_2, b2929^0'=b2929^post_2, b3333^0'=b3333^post_2, b3535^0'=b3535^post_2, i^0'=i^post_2, i___01313^0'=i___01313^post_2, i___01717^0'=i___01717^post_2, i___02020^0'=i___02020^post_2, i___02424^0'=i___02424^post_2, i___04040^0'=i___04040^post_2, i___04747^0'=i___04747^post_2, i___099^0'=i___099^post_2, ioA^0'=ioA^post_2, ioR^0'=ioR^post_2, k1^0'=k1^post_2, k2^0'=k2^post_2, k3^0'=k3^post_2, k4^0'=k4^post_2, k5^0'=k5^post_2, keA^0'=keA^post_2, keR^0'=keR^post_2, ntStatus^0'=ntStatus^post_2, pIrb^0'=pIrb^post_2, phi_io_compl^0'=phi_io_compl^post_2, phi_nSUC_ret^0'=phi_nSUC_ret^post_2, prevCancel^0'=prevCancel^post_2, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_2, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_2, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_2, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_2, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_2, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_2, [ 1<=k3^0 && IsochDetachData^1_1==IsochDetachData^1_1 && i^post_2==i^post_2 && IsochDetachData^post_2==IsochDetachData^post_2 && k3^post_2==-1+k3^0 && i___01717^post_2==Irql^0 && keR^1_2_1==1 && keR^post_2==0 && a1818^post_2==IsochDetachData^post_2 && AsyncAddressData^0==AsyncAddressData^post_2 && BusResetIrp^0==BusResetIrp^post_2 && CromData^0==CromData^post_2 && DeviceObject^0==DeviceObject^post_2 && Irp^0==Irp^post_2 && Irql^0==Irql^post_2 && IsochResourceData^0==IsochResourceData^post_2 && ResourceIrp^0==ResourceIrp^post_2 && StackSize^0==StackSize^post_2 && __rho_10_^0==__rho_10_^post_2 && __rho_11_^0==__rho_11_^post_2 && __rho_12_^0==__rho_12_^post_2 && __rho_1_^0==__rho_1_^post_2 && __rho_2_^0==__rho_2_^post_2 && __rho_3_^0==__rho_3_^post_2 && __rho_4_^0==__rho_4_^post_2 && __rho_5_^0==__rho_5_^post_2 && __rho_666_^0==__rho_666_^post_2 && __rho_7_^0==__rho_7_^post_2 && __rho_8_^0==__rho_8_^post_2 && __rho_9_^0==__rho_9_^post_2 && a11^0==a11^post_2 && a2525^0==a2525^post_2 && a2828^0==a2828^post_2 && a3131^0==a3131^post_2 && a3232^0==a3232^post_2 && a3434^0==a3434^post_2 && a3737^0==a3737^post_2 && a3838^0==a3838^post_2 && a4343^0==a4343^post_2 && a4545^0==a4545^post_2 && a77^0==a77^post_2 && b22^0==b22^post_2 && b2626^0==b2626^post_2 && b2929^0==b2929^post_2 && b3333^0==b3333^post_2 && b3535^0==b3535^post_2 && i___01313^0==i___01313^post_2 && i___02020^0==i___02020^post_2 && i___02424^0==i___02424^post_2 && i___04040^0==i___04040^post_2 && i___04747^0==i___04747^post_2 && i___099^0==i___099^post_2 && ioA^0==ioA^post_2 && ioR^0==ioR^post_2 && k1^0==k1^post_2 && k2^0==k2^post_2 && k4^0==k4^post_2 && k5^0==k5^post_2 && keA^0==keA^post_2 && ntStatus^0==ntStatus^post_2 && pIrb^0==pIrb^post_2 && phi_io_compl^0==phi_io_compl^post_2 && phi_nSUC_ret^0==phi_nSUC_ret^post_2 && prevCancel^0==prevCancel^post_2 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_2 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_2 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_2 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_2 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_2 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_2 ], cost: 1
     23: l1 -> l17 : AsyncAddressData^0'=AsyncAddressData^post_24, BusResetIrp^0'=BusResetIrp^post_24, CromData^0'=CromData^post_24, DeviceObject^0'=DeviceObject^post_24, Irp^0'=Irp^post_24, Irql^0'=Irql^post_24, IsochDetachData^0'=IsochDetachData^post_24, IsochResourceData^0'=IsochResourceData^post_24, ResourceIrp^0'=ResourceIrp^post_24, StackSize^0'=StackSize^post_24, __rho_10_^0'=__rho_10_^post_24, __rho_11_^0'=__rho_11_^post_24, __rho_12_^0'=__rho_12_^post_24, __rho_1_^0'=__rho_1_^post_24, __rho_2_^0'=__rho_2_^post_24, __rho_3_^0'=__rho_3_^post_24, __rho_4_^0'=__rho_4_^post_24, __rho_5_^0'=__rho_5_^post_24, __rho_666_^0'=__rho_666_^post_24, __rho_7_^0'=__rho_7_^post_24, __rho_8_^0'=__rho_8_^post_24, __rho_9_^0'=__rho_9_^post_24, a11^0'=a11^post_24, a1818^0'=a1818^post_24, a2525^0'=a2525^post_24, a2828^0'=a2828^post_24, a3131^0'=a3131^post_24, a3232^0'=a3232^post_24, a3434^0'=a3434^post_24, a3737^0'=a3737^post_24, a3838^0'=a3838^post_24, a4343^0'=a4343^post_24, a4545^0'=a4545^post_24, a77^0'=a77^post_24, b22^0'=b22^post_24, b2626^0'=b2626^post_24, b2929^0'=b2929^post_24, b3333^0'=b3333^post_24, b3535^0'=b3535^post_24, i^0'=i^post_24, i___01313^0'=i___01313^post_24, i___01717^0'=i___01717^post_24, i___02020^0'=i___02020^post_24, i___02424^0'=i___02424^post_24, i___04040^0'=i___04040^post_24, i___04747^0'=i___04747^post_24, i___099^0'=i___099^post_24, ioA^0'=ioA^post_24, ioR^0'=ioR^post_24, k1^0'=k1^post_24, k2^0'=k2^post_24, k3^0'=k3^post_24, k4^0'=k4^post_24, k5^0'=k5^post_24, keA^0'=keA^post_24, keR^0'=keR^post_24, ntStatus^0'=ntStatus^post_24, pIrb^0'=pIrb^post_24, phi_io_compl^0'=phi_io_compl^post_24, phi_nSUC_ret^0'=phi_nSUC_ret^post_24, prevCancel^0'=prevCancel^post_24, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_24, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_24, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_24, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_24, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_24, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_24, [ keA^1_2==1 && keA^post_24==0 && AsyncAddressData^0==AsyncAddressData^post_24 && BusResetIrp^0==BusResetIrp^post_24 && CromData^0==CromData^post_24 && DeviceObject^0==DeviceObject^post_24 && Irp^0==Irp^post_24 && Irql^0==Irql^post_24 && IsochDetachData^0==IsochDetachData^post_24 && IsochResourceData^0==IsochResourceData^post_24 && ResourceIrp^0==ResourceIrp^post_24 && StackSize^0==StackSize^post_24 && __rho_10_^0==__rho_10_^post_24 && __rho_11_^0==__rho_11_^post_24 && __rho_12_^0==__rho_12_^post_24 && __rho_1_^0==__rho_1_^post_24 && __rho_2_^0==__rho_2_^post_24 && __rho_3_^0==__rho_3_^post_24 && __rho_4_^0==__rho_4_^post_24 && __rho_5_^0==__rho_5_^post_24 && __rho_666_^0==__rho_666_^post_24 && __rho_7_^0==__rho_7_^post_24 && __rho_8_^0==__rho_8_^post_24 && __rho_9_^0==__rho_9_^post_24 && a11^0==a11^post_24 && a1818^0==a1818^post_24 && a2525^0==a2525^post_24 && a2828^0==a2828^post_24 && a3131^0==a3131^post_24 && a3232^0==a3232^post_24 && a3434^0==a3434^post_24 && a3737^0==a3737^post_24 && a3838^0==a3838^post_24 && a4343^0==a4343^post_24 && a4545^0==a4545^post_24 && a77^0==a77^post_24 && b22^0==b22^post_24 && b2626^0==b2626^post_24 && b2929^0==b2929^post_24 && b3333^0==b3333^post_24 && b3535^0==b3535^post_24 && i^0==i^post_24 && i___01313^0==i___01313^post_24 && i___01717^0==i___01717^post_24 && i___02020^0==i___02020^post_24 && i___02424^0==i___02424^post_24 && i___04040^0==i___04040^post_24 && i___04747^0==i___04747^post_24 && i___099^0==i___099^post_24 && ioA^0==ioA^post_24 && ioR^0==ioR^post_24 && k1^0==k1^post_24 && k2^0==k2^post_24 && k3^0==k3^post_24 && k4^0==k4^post_24 && k5^0==k5^post_24 && keR^0==keR^post_24 && ntStatus^0==ntStatus^post_24 && pIrb^0==pIrb^post_24 && phi_io_compl^0==phi_io_compl^post_24 && phi_nSUC_ret^0==phi_nSUC_ret^post_24 && prevCancel^0==prevCancel^post_24 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_24 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_24 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_24 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_24 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_24 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_24 ], cost: 1
     16: l2 -> l0 : AsyncAddressData^0'=AsyncAddressData^post_17, BusResetIrp^0'=BusResetIrp^post_17, CromData^0'=CromData^post_17, DeviceObject^0'=DeviceObject^post_17, Irp^0'=Irp^post_17, Irql^0'=Irql^post_17, IsochDetachData^0'=IsochDetachData^post_17, IsochResourceData^0'=IsochResourceData^post_17, ResourceIrp^0'=ResourceIrp^post_17, StackSize^0'=StackSize^post_17, __rho_10_^0'=__rho_10_^post_17, __rho_11_^0'=__rho_11_^post_17, __rho_12_^0'=__rho_12_^post_17, __rho_1_^0'=__rho_1_^post_17, __rho_2_^0'=__rho_2_^post_17, __rho_3_^0'=__rho_3_^post_17, __rho_4_^0'=__rho_4_^post_17, __rho_5_^0'=__rho_5_^post_17, __rho_666_^0'=__rho_666_^post_17, __rho_7_^0'=__rho_7_^post_17, __rho_8_^0'=__rho_8_^post_17, __rho_9_^0'=__rho_9_^post_17, a11^0'=a11^post_17, a1818^0'=a1818^post_17, a2525^0'=a2525^post_17, a2828^0'=a2828^post_17, a3131^0'=a3131^post_17, a3232^0'=a3232^post_17, a3434^0'=a3434^post_17, a3737^0'=a3737^post_17, a3838^0'=a3838^post_17, a4343^0'=a4343^post_17, a4545^0'=a4545^post_17, a77^0'=a77^post_17, b22^0'=b22^post_17, b2626^0'=b2626^post_17, b2929^0'=b2929^post_17, b3333^0'=b3333^post_17, b3535^0'=b3535^post_17, i^0'=i^post_17, i___01313^0'=i___01313^post_17, i___01717^0'=i___01717^post_17, i___02020^0'=i___02020^post_17, i___02424^0'=i___02424^post_17, i___04040^0'=i___04040^post_17, i___04747^0'=i___04747^post_17, i___099^0'=i___099^post_17, ioA^0'=ioA^post_17, ioR^0'=ioR^post_17, k1^0'=k1^post_17, k2^0'=k2^post_17, k3^0'=k3^post_17, k4^0'=k4^post_17, k5^0'=k5^post_17, keA^0'=keA^post_17, keR^0'=keR^post_17, ntStatus^0'=ntStatus^post_17, pIrb^0'=pIrb^post_17, phi_io_compl^0'=phi_io_compl^post_17, phi_nSUC_ret^0'=phi_nSUC_ret^post_17, prevCancel^0'=prevCancel^post_17, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_17, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_17, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_17, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_17, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_17, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_17, [ keA^1_1==1 && keA^post_17==0 && AsyncAddressData^0==AsyncAddressData^post_17 && BusResetIrp^0==BusResetIrp^post_17 && CromData^0==CromData^post_17 && DeviceObject^0==DeviceObject^post_17 && Irp^0==Irp^post_17 && Irql^0==Irql^post_17 && IsochDetachData^0==IsochDetachData^post_17 && IsochResourceData^0==IsochResourceData^post_17 && ResourceIrp^0==ResourceIrp^post_17 && StackSize^0==StackSize^post_17 && __rho_10_^0==__rho_10_^post_17 && __rho_11_^0==__rho_11_^post_17 && __rho_12_^0==__rho_12_^post_17 && __rho_1_^0==__rho_1_^post_17 && __rho_2_^0==__rho_2_^post_17 && __rho_3_^0==__rho_3_^post_17 && __rho_4_^0==__rho_4_^post_17 && __rho_5_^0==__rho_5_^post_17 && __rho_666_^0==__rho_666_^post_17 && __rho_7_^0==__rho_7_^post_17 && __rho_8_^0==__rho_8_^post_17 && __rho_9_^0==__rho_9_^post_17 && a11^0==a11^post_17 && a1818^0==a1818^post_17 && a2525^0==a2525^post_17 && a2828^0==a2828^post_17 && a3131^0==a3131^post_17 && a3232^0==a3232^post_17 && a3434^0==a3434^post_17 && a3737^0==a3737^post_17 && a3838^0==a3838^post_17 && a4343^0==a4343^post_17 && a4545^0==a4545^post_17 && a77^0==a77^post_17 && b22^0==b22^post_17 && b2626^0==b2626^post_17 && b2929^0==b2929^post_17 && b3333^0==b3333^post_17 && b3535^0==b3535^post_17 && i^0==i^post_17 && i___01313^0==i___01313^post_17 && i___01717^0==i___01717^post_17 && i___02020^0==i___02020^post_17 && i___02424^0==i___02424^post_17 && i___04040^0==i___04040^post_17 && i___04747^0==i___04747^post_17 && i___099^0==i___099^post_17 && ioA^0==ioA^post_17 && ioR^0==ioR^post_17 && k1^0==k1^post_17 && k2^0==k2^post_17 && k3^0==k3^post_17 && k4^0==k4^post_17 && k5^0==k5^post_17 && keR^0==keR^post_17 && ntStatus^0==ntStatus^post_17 && pIrb^0==pIrb^post_17 && phi_io_compl^0==phi_io_compl^post_17 && phi_nSUC_ret^0==phi_nSUC_ret^post_17 && prevCancel^0==prevCancel^post_17 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_17 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_17 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_17 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_17 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_17 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_17 ], cost: 1
      2: l3 -> l4 : AsyncAddressData^0'=AsyncAddressData^post_3, BusResetIrp^0'=BusResetIrp^post_3, CromData^0'=CromData^post_3, DeviceObject^0'=DeviceObject^post_3, Irp^0'=Irp^post_3, Irql^0'=Irql^post_3, IsochDetachData^0'=IsochDetachData^post_3, IsochResourceData^0'=IsochResourceData^post_3, ResourceIrp^0'=ResourceIrp^post_3, StackSize^0'=StackSize^post_3, __rho_10_^0'=__rho_10_^post_3, __rho_11_^0'=__rho_11_^post_3, __rho_12_^0'=__rho_12_^post_3, __rho_1_^0'=__rho_1_^post_3, __rho_2_^0'=__rho_2_^post_3, __rho_3_^0'=__rho_3_^post_3, __rho_4_^0'=__rho_4_^post_3, __rho_5_^0'=__rho_5_^post_3, __rho_666_^0'=__rho_666_^post_3, __rho_7_^0'=__rho_7_^post_3, __rho_8_^0'=__rho_8_^post_3, __rho_9_^0'=__rho_9_^post_3, a11^0'=a11^post_3, a1818^0'=a1818^post_3, a2525^0'=a2525^post_3, a2828^0'=a2828^post_3, a3131^0'=a3131^post_3, a3232^0'=a3232^post_3, a3434^0'=a3434^post_3, a3737^0'=a3737^post_3, a3838^0'=a3838^post_3, a4343^0'=a4343^post_3, a4545^0'=a4545^post_3, a77^0'=a77^post_3, b22^0'=b22^post_3, b2626^0'=b2626^post_3, b2929^0'=b2929^post_3, b3333^0'=b3333^post_3, b3535^0'=b3535^post_3, i^0'=i^post_3, i___01313^0'=i___01313^post_3, i___01717^0'=i___01717^post_3, i___02020^0'=i___02020^post_3, i___02424^0'=i___02424^post_3, i___04040^0'=i___04040^post_3, i___04747^0'=i___04747^post_3, i___099^0'=i___099^post_3, ioA^0'=ioA^post_3, ioR^0'=ioR^post_3, k1^0'=k1^post_3, k2^0'=k2^post_3, k3^0'=k3^post_3, k4^0'=k4^post_3, k5^0'=k5^post_3, keA^0'=keA^post_3, keR^0'=keR^post_3, ntStatus^0'=ntStatus^post_3, pIrb^0'=pIrb^post_3, phi_io_compl^0'=phi_io_compl^post_3, phi_nSUC_ret^0'=phi_nSUC_ret^post_3, prevCancel^0'=prevCancel^post_3, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_3, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_3, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_3, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_3, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_3, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_3, [ AsyncAddressData^0<=0 && AsyncAddressData^0==AsyncAddressData^post_3 && BusResetIrp^0==BusResetIrp^post_3 && CromData^0==CromData^post_3 && DeviceObject^0==DeviceObject^post_3 && Irp^0==Irp^post_3 && Irql^0==Irql^post_3 && IsochDetachData^0==IsochDetachData^post_3 && IsochResourceData^0==IsochResourceData^post_3 && ResourceIrp^0==ResourceIrp^post_3 && StackSize^0==StackSize^post_3 && __rho_10_^0==__rho_10_^post_3 && __rho_11_^0==__rho_11_^post_3 && __rho_12_^0==__rho_12_^post_3 && __rho_1_^0==__rho_1_^post_3 && __rho_2_^0==__rho_2_^post_3 && __rho_3_^0==__rho_3_^post_3 && __rho_4_^0==__rho_4_^post_3 && __rho_5_^0==__rho_5_^post_3 && __rho_666_^0==__rho_666_^post_3 && __rho_7_^0==__rho_7_^post_3 && __rho_8_^0==__rho_8_^post_3 && __rho_9_^0==__rho_9_^post_3 && a11^0==a11^post_3 && a1818^0==a1818^post_3 && a2525^0==a2525^post_3 && a2828^0==a2828^post_3 && a3131^0==a3131^post_3 && a3232^0==a3232^post_3 && a3434^0==a3434^post_3 && a3737^0==a3737^post_3 && a3838^0==a3838^post_3 && a4343^0==a4343^post_3 && a4545^0==a4545^post_3 && a77^0==a77^post_3 && b22^0==b22^post_3 && b2626^0==b2626^post_3 && b2929^0==b2929^post_3 && b3333^0==b3333^post_3 && b3535^0==b3535^post_3 && i^0==i^post_3 && i___01313^0==i___01313^post_3 && i___01717^0==i___01717^post_3 && i___02020^0==i___02020^post_3 && i___02424^0==i___02424^post_3 && i___04040^0==i___04040^post_3 && i___04747^0==i___04747^post_3 && i___099^0==i___099^post_3 && ioA^0==ioA^post_3 && ioR^0==ioR^post_3 && k1^0==k1^post_3 && k2^0==k2^post_3 && k3^0==k3^post_3 && k4^0==k4^post_3 && k5^0==k5^post_3 && keA^0==keA^post_3 && keR^0==keR^post_3 && ntStatus^0==ntStatus^post_3 && pIrb^0==pIrb^post_3 && phi_io_compl^0==phi_io_compl^post_3 && phi_nSUC_ret^0==phi_nSUC_ret^post_3 && prevCancel^0==prevCancel^post_3 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_3 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_3 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_3 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_3 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_3 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_3 ], cost: 1
      3: l3 -> l4 : AsyncAddressData^0'=AsyncAddressData^post_4, BusResetIrp^0'=BusResetIrp^post_4, CromData^0'=CromData^post_4, DeviceObject^0'=DeviceObject^post_4, Irp^0'=Irp^post_4, Irql^0'=Irql^post_4, IsochDetachData^0'=IsochDetachData^post_4, IsochResourceData^0'=IsochResourceData^post_4, ResourceIrp^0'=ResourceIrp^post_4, StackSize^0'=StackSize^post_4, __rho_10_^0'=__rho_10_^post_4, __rho_11_^0'=__rho_11_^post_4, __rho_12_^0'=__rho_12_^post_4, __rho_1_^0'=__rho_1_^post_4, __rho_2_^0'=__rho_2_^post_4, __rho_3_^0'=__rho_3_^post_4, __rho_4_^0'=__rho_4_^post_4, __rho_5_^0'=__rho_5_^post_4, __rho_666_^0'=__rho_666_^post_4, __rho_7_^0'=__rho_7_^post_4, __rho_8_^0'=__rho_8_^post_4, __rho_9_^0'=__rho_9_^post_4, a11^0'=a11^post_4, a1818^0'=a1818^post_4, a2525^0'=a2525^post_4, a2828^0'=a2828^post_4, a3131^0'=a3131^post_4, a3232^0'=a3232^post_4, a3434^0'=a3434^post_4, a3737^0'=a3737^post_4, a3838^0'=a3838^post_4, a4343^0'=a4343^post_4, a4545^0'=a4545^post_4, a77^0'=a77^post_4, b22^0'=b22^post_4, b2626^0'=b2626^post_4, b2929^0'=b2929^post_4, b3333^0'=b3333^post_4, b3535^0'=b3535^post_4, i^0'=i^post_4, i___01313^0'=i___01313^post_4, i___01717^0'=i___01717^post_4, i___02020^0'=i___02020^post_4, i___02424^0'=i___02424^post_4, i___04040^0'=i___04040^post_4, i___04747^0'=i___04747^post_4, i___099^0'=i___099^post_4, ioA^0'=ioA^post_4, ioR^0'=ioR^post_4, k1^0'=k1^post_4, k2^0'=k2^post_4, k3^0'=k3^post_4, k4^0'=k4^post_4, k5^0'=k5^post_4, keA^0'=keA^post_4, keR^0'=keR^post_4, ntStatus^0'=ntStatus^post_4, pIrb^0'=pIrb^post_4, phi_io_compl^0'=phi_io_compl^post_4, phi_nSUC_ret^0'=phi_nSUC_ret^post_4, prevCancel^0'=prevCancel^post_4, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_4, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_4, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_4, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_4, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_4, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_4, [ 1<=AsyncAddressData^0 && AsyncAddressData^0==AsyncAddressData^post_4 && BusResetIrp^0==BusResetIrp^post_4 && CromData^0==CromData^post_4 && DeviceObject^0==DeviceObject^post_4 && Irp^0==Irp^post_4 && Irql^0==Irql^post_4 && IsochDetachData^0==IsochDetachData^post_4 && IsochResourceData^0==IsochResourceData^post_4 && ResourceIrp^0==ResourceIrp^post_4 && StackSize^0==StackSize^post_4 && __rho_10_^0==__rho_10_^post_4 && __rho_11_^0==__rho_11_^post_4 && __rho_12_^0==__rho_12_^post_4 && __rho_1_^0==__rho_1_^post_4 && __rho_2_^0==__rho_2_^post_4 && __rho_3_^0==__rho_3_^post_4 && __rho_4_^0==__rho_4_^post_4 && __rho_5_^0==__rho_5_^post_4 && __rho_666_^0==__rho_666_^post_4 && __rho_7_^0==__rho_7_^post_4 && __rho_8_^0==__rho_8_^post_4 && __rho_9_^0==__rho_9_^post_4 && a11^0==a11^post_4 && a1818^0==a1818^post_4 && a2525^0==a2525^post_4 && a2828^0==a2828^post_4 && a3131^0==a3131^post_4 && a3232^0==a3232^post_4 && a3434^0==a3434^post_4 && a3737^0==a3737^post_4 && a3838^0==a3838^post_4 && a4343^0==a4343^post_4 && a4545^0==a4545^post_4 && a77^0==a77^post_4 && b22^0==b22^post_4 && b2626^0==b2626^post_4 && b2929^0==b2929^post_4 && b3333^0==b3333^post_4 && b3535^0==b3535^post_4 && i^0==i^post_4 && i___01313^0==i___01313^post_4 && i___01717^0==i___01717^post_4 && i___02020^0==i___02020^post_4 && i___02424^0==i___02424^post_4 && i___04040^0==i___04040^post_4 && i___04747^0==i___04747^post_4 && i___099^0==i___099^post_4 && ioA^0==ioA^post_4 && ioR^0==ioR^post_4 && k1^0==k1^post_4 && k2^0==k2^post_4 && k3^0==k3^post_4 && k4^0==k4^post_4 && k5^0==k5^post_4 && keA^0==keA^post_4 && keR^0==keR^post_4 && ntStatus^0==ntStatus^post_4 && pIrb^0==pIrb^post_4 && phi_io_compl^0==phi_io_compl^post_4 && phi_nSUC_ret^0==phi_nSUC_ret^post_4 && prevCancel^0==prevCancel^post_4 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_4 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_4 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_4 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_4 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_4 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_4 ], cost: 1
     15: l4 -> l12 : AsyncAddressData^0'=AsyncAddressData^post_16, BusResetIrp^0'=BusResetIrp^post_16, CromData^0'=CromData^post_16, DeviceObject^0'=DeviceObject^post_16, Irp^0'=Irp^post_16, Irql^0'=Irql^post_16, IsochDetachData^0'=IsochDetachData^post_16, IsochResourceData^0'=IsochResourceData^post_16, ResourceIrp^0'=ResourceIrp^post_16, StackSize^0'=StackSize^post_16, __rho_10_^0'=__rho_10_^post_16, __rho_11_^0'=__rho_11_^post_16, __rho_12_^0'=__rho_12_^post_16, __rho_1_^0'=__rho_1_^post_16, __rho_2_^0'=__rho_2_^post_16, __rho_3_^0'=__rho_3_^post_16, __rho_4_^0'=__rho_4_^post_16, __rho_5_^0'=__rho_5_^post_16, __rho_666_^0'=__rho_666_^post_16, __rho_7_^0'=__rho_7_^post_16, __rho_8_^0'=__rho_8_^post_16, __rho_9_^0'=__rho_9_^post_16, a11^0'=a11^post_16, a1818^0'=a1818^post_16, a2525^0'=a2525^post_16, a2828^0'=a2828^post_16, a3131^0'=a3131^post_16, a3232^0'=a3232^post_16, a3434^0'=a3434^post_16, a3737^0'=a3737^post_16, a3838^0'=a3838^post_16, a4343^0'=a4343^post_16, a4545^0'=a4545^post_16, a77^0'=a77^post_16, b22^0'=b22^post_16, b2626^0'=b2626^post_16, b2929^0'=b2929^post_16, b3333^0'=b3333^post_16, b3535^0'=b3535^post_16, i^0'=i^post_16, i___01313^0'=i___01313^post_16, i___01717^0'=i___01717^post_16, i___02020^0'=i___02020^post_16, i___02424^0'=i___02424^post_16, i___04040^0'=i___04040^post_16, i___04747^0'=i___04747^post_16, i___099^0'=i___099^post_16, ioA^0'=ioA^post_16, ioR^0'=ioR^post_16, k1^0'=k1^post_16, k2^0'=k2^post_16, k3^0'=k3^post_16, k4^0'=k4^post_16, k5^0'=k5^post_16, keA^0'=keA^post_16, keR^0'=keR^post_16, ntStatus^0'=ntStatus^post_16, pIrb^0'=pIrb^post_16, phi_io_compl^0'=phi_io_compl^post_16, phi_nSUC_ret^0'=phi_nSUC_ret^post_16, prevCancel^0'=prevCancel^post_16, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_16, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_16, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_16, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_16, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_16, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_16, [ AsyncAddressData^0==AsyncAddressData^post_16 && BusResetIrp^0==BusResetIrp^post_16 && CromData^0==CromData^post_16 && DeviceObject^0==DeviceObject^post_16 && Irp^0==Irp^post_16 && Irql^0==Irql^post_16 && IsochDetachData^0==IsochDetachData^post_16 && IsochResourceData^0==IsochResourceData^post_16 && ResourceIrp^0==ResourceIrp^post_16 && StackSize^0==StackSize^post_16 && __rho_10_^0==__rho_10_^post_16 && __rho_11_^0==__rho_11_^post_16 && __rho_12_^0==__rho_12_^post_16 && __rho_1_^0==__rho_1_^post_16 && __rho_2_^0==__rho_2_^post_16 && __rho_3_^0==__rho_3_^post_16 && __rho_4_^0==__rho_4_^post_16 && __rho_5_^0==__rho_5_^post_16 && __rho_666_^0==__rho_666_^post_16 && __rho_7_^0==__rho_7_^post_16 && __rho_8_^0==__rho_8_^post_16 && __rho_9_^0==__rho_9_^post_16 && a11^0==a11^post_16 && a1818^0==a1818^post_16 && a2525^0==a2525^post_16 && a2828^0==a2828^post_16 && a3131^0==a3131^post_16 && a3232^0==a3232^post_16 && a3434^0==a3434^post_16 && a3737^0==a3737^post_16 && a3838^0==a3838^post_16 && a4343^0==a4343^post_16 && a4545^0==a4545^post_16 && a77^0==a77^post_16 && b22^0==b22^post_16 && b2626^0==b2626^post_16 && b2929^0==b2929^post_16 && b3333^0==b3333^post_16 && b3535^0==b3535^post_16 && i^0==i^post_16 && i___01313^0==i___01313^post_16 && i___01717^0==i___01717^post_16 && i___02020^0==i___02020^post_16 && i___02424^0==i___02424^post_16 && i___04040^0==i___04040^post_16 && i___04747^0==i___04747^post_16 && i___099^0==i___099^post_16 && ioA^0==ioA^post_16 && ioR^0==ioR^post_16 && k1^0==k1^post_16 && k2^0==k2^post_16 && k3^0==k3^post_16 && k4^0==k4^post_16 && k5^0==k5^post_16 && keA^0==keA^post_16 && keR^0==keR^post_16 && ntStatus^0==ntStatus^post_16 && pIrb^0==pIrb^post_16 && phi_io_compl^0==phi_io_compl^post_16 && phi_nSUC_ret^0==phi_nSUC_ret^post_16 && prevCancel^0==prevCancel^post_16 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_16 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_16 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_16 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_16 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_16 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_16 ], cost: 1
      4: l5 -> l3 : AsyncAddressData^0'=AsyncAddressData^post_5, BusResetIrp^0'=BusResetIrp^post_5, CromData^0'=CromData^post_5, DeviceObject^0'=DeviceObject^post_5, Irp^0'=Irp^post_5, Irql^0'=Irql^post_5, IsochDetachData^0'=IsochDetachData^post_5, IsochResourceData^0'=IsochResourceData^post_5, ResourceIrp^0'=ResourceIrp^post_5, StackSize^0'=StackSize^post_5, __rho_10_^0'=__rho_10_^post_5, __rho_11_^0'=__rho_11_^post_5, __rho_12_^0'=__rho_12_^post_5, __rho_1_^0'=__rho_1_^post_5, __rho_2_^0'=__rho_2_^post_5, __rho_3_^0'=__rho_3_^post_5, __rho_4_^0'=__rho_4_^post_5, __rho_5_^0'=__rho_5_^post_5, __rho_666_^0'=__rho_666_^post_5, __rho_7_^0'=__rho_7_^post_5, __rho_8_^0'=__rho_8_^post_5, __rho_9_^0'=__rho_9_^post_5, a11^0'=a11^post_5, a1818^0'=a1818^post_5, a2525^0'=a2525^post_5, a2828^0'=a2828^post_5, a3131^0'=a3131^post_5, a3232^0'=a3232^post_5, a3434^0'=a3434^post_5, a3737^0'=a3737^post_5, a3838^0'=a3838^post_5, a4343^0'=a4343^post_5, a4545^0'=a4545^post_5, a77^0'=a77^post_5, b22^0'=b22^post_5, b2626^0'=b2626^post_5, b2929^0'=b2929^post_5, b3333^0'=b3333^post_5, b3535^0'=b3535^post_5, i^0'=i^post_5, i___01313^0'=i___01313^post_5, i___01717^0'=i___01717^post_5, i___02020^0'=i___02020^post_5, i___02424^0'=i___02424^post_5, i___04040^0'=i___04040^post_5, i___04747^0'=i___04747^post_5, i___099^0'=i___099^post_5, ioA^0'=ioA^post_5, ioR^0'=ioR^post_5, k1^0'=k1^post_5, k2^0'=k2^post_5, k3^0'=k3^post_5, k4^0'=k4^post_5, k5^0'=k5^post_5, keA^0'=keA^post_5, keR^0'=keR^post_5, ntStatus^0'=ntStatus^post_5, pIrb^0'=pIrb^post_5, phi_io_compl^0'=phi_io_compl^post_5, phi_nSUC_ret^0'=phi_nSUC_ret^post_5, prevCancel^0'=prevCancel^post_5, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_5, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_5, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_5, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_5, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_5, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_5, [ __rho_9_^0<=0 && AsyncAddressData^0==AsyncAddressData^post_5 && BusResetIrp^0==BusResetIrp^post_5 && CromData^0==CromData^post_5 && DeviceObject^0==DeviceObject^post_5 && Irp^0==Irp^post_5 && Irql^0==Irql^post_5 && IsochDetachData^0==IsochDetachData^post_5 && IsochResourceData^0==IsochResourceData^post_5 && ResourceIrp^0==ResourceIrp^post_5 && StackSize^0==StackSize^post_5 && __rho_10_^0==__rho_10_^post_5 && __rho_11_^0==__rho_11_^post_5 && __rho_12_^0==__rho_12_^post_5 && __rho_1_^0==__rho_1_^post_5 && __rho_2_^0==__rho_2_^post_5 && __rho_3_^0==__rho_3_^post_5 && __rho_4_^0==__rho_4_^post_5 && __rho_5_^0==__rho_5_^post_5 && __rho_666_^0==__rho_666_^post_5 && __rho_7_^0==__rho_7_^post_5 && __rho_8_^0==__rho_8_^post_5 && __rho_9_^0==__rho_9_^post_5 && a11^0==a11^post_5 && a1818^0==a1818^post_5 && a2525^0==a2525^post_5 && a2828^0==a2828^post_5 && a3131^0==a3131^post_5 && a3232^0==a3232^post_5 && a3434^0==a3434^post_5 && a3737^0==a3737^post_5 && a3838^0==a3838^post_5 && a4343^0==a4343^post_5 && a4545^0==a4545^post_5 && a77^0==a77^post_5 && b22^0==b22^post_5 && b2626^0==b2626^post_5 && b2929^0==b2929^post_5 && b3333^0==b3333^post_5 && b3535^0==b3535^post_5 && i^0==i^post_5 && i___01313^0==i___01313^post_5 && i___01717^0==i___01717^post_5 && i___02020^0==i___02020^post_5 && i___02424^0==i___02424^post_5 && i___04040^0==i___04040^post_5 && i___04747^0==i___04747^post_5 && i___099^0==i___099^post_5 && ioA^0==ioA^post_5 && ioR^0==ioR^post_5 && k1^0==k1^post_5 && k2^0==k2^post_5 && k3^0==k3^post_5 && k4^0==k4^post_5 && k5^0==k5^post_5 && keA^0==keA^post_5 && keR^0==keR^post_5 && ntStatus^0==ntStatus^post_5 && pIrb^0==pIrb^post_5 && phi_io_compl^0==phi_io_compl^post_5 && phi_nSUC_ret^0==phi_nSUC_ret^post_5 && prevCancel^0==prevCancel^post_5 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_5 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_5 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_5 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_5 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_5 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_5 ], cost: 1
      5: l5 -> l3 : AsyncAddressData^0'=AsyncAddressData^post_6, BusResetIrp^0'=BusResetIrp^post_6, CromData^0'=CromData^post_6, DeviceObject^0'=DeviceObject^post_6, Irp^0'=Irp^post_6, Irql^0'=Irql^post_6, IsochDetachData^0'=IsochDetachData^post_6, IsochResourceData^0'=IsochResourceData^post_6, ResourceIrp^0'=ResourceIrp^post_6, StackSize^0'=StackSize^post_6, __rho_10_^0'=__rho_10_^post_6, __rho_11_^0'=__rho_11_^post_6, __rho_12_^0'=__rho_12_^post_6, __rho_1_^0'=__rho_1_^post_6, __rho_2_^0'=__rho_2_^post_6, __rho_3_^0'=__rho_3_^post_6, __rho_4_^0'=__rho_4_^post_6, __rho_5_^0'=__rho_5_^post_6, __rho_666_^0'=__rho_666_^post_6, __rho_7_^0'=__rho_7_^post_6, __rho_8_^0'=__rho_8_^post_6, __rho_9_^0'=__rho_9_^post_6, a11^0'=a11^post_6, a1818^0'=a1818^post_6, a2525^0'=a2525^post_6, a2828^0'=a2828^post_6, a3131^0'=a3131^post_6, a3232^0'=a3232^post_6, a3434^0'=a3434^post_6, a3737^0'=a3737^post_6, a3838^0'=a3838^post_6, a4343^0'=a4343^post_6, a4545^0'=a4545^post_6, a77^0'=a77^post_6, b22^0'=b22^post_6, b2626^0'=b2626^post_6, b2929^0'=b2929^post_6, b3333^0'=b3333^post_6, b3535^0'=b3535^post_6, i^0'=i^post_6, i___01313^0'=i___01313^post_6, i___01717^0'=i___01717^post_6, i___02020^0'=i___02020^post_6, i___02424^0'=i___02424^post_6, i___04040^0'=i___04040^post_6, i___04747^0'=i___04747^post_6, i___099^0'=i___099^post_6, ioA^0'=ioA^post_6, ioR^0'=ioR^post_6, k1^0'=k1^post_6, k2^0'=k2^post_6, k3^0'=k3^post_6, k4^0'=k4^post_6, k5^0'=k5^post_6, keA^0'=keA^post_6, keR^0'=keR^post_6, ntStatus^0'=ntStatus^post_6, pIrb^0'=pIrb^post_6, phi_io_compl^0'=phi_io_compl^post_6, phi_nSUC_ret^0'=phi_nSUC_ret^post_6, prevCancel^0'=prevCancel^post_6, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_6, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_6, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_6, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_6, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_6, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_6, [ 1<=__rho_9_^0 && AsyncAddressData^0==AsyncAddressData^post_6 && BusResetIrp^0==BusResetIrp^post_6 && CromData^0==CromData^post_6 && DeviceObject^0==DeviceObject^post_6 && Irp^0==Irp^post_6 && Irql^0==Irql^post_6 && IsochDetachData^0==IsochDetachData^post_6 && IsochResourceData^0==IsochResourceData^post_6 && ResourceIrp^0==ResourceIrp^post_6 && StackSize^0==StackSize^post_6 && __rho_10_^0==__rho_10_^post_6 && __rho_11_^0==__rho_11_^post_6 && __rho_12_^0==__rho_12_^post_6 && __rho_1_^0==__rho_1_^post_6 && __rho_2_^0==__rho_2_^post_6 && __rho_3_^0==__rho_3_^post_6 && __rho_4_^0==__rho_4_^post_6 && __rho_5_^0==__rho_5_^post_6 && __rho_666_^0==__rho_666_^post_6 && __rho_7_^0==__rho_7_^post_6 && __rho_8_^0==__rho_8_^post_6 && __rho_9_^0==__rho_9_^post_6 && a11^0==a11^post_6 && a1818^0==a1818^post_6 && a2525^0==a2525^post_6 && a2828^0==a2828^post_6 && a3131^0==a3131^post_6 && a3232^0==a3232^post_6 && a3434^0==a3434^post_6 && a3737^0==a3737^post_6 && a3838^0==a3838^post_6 && a4343^0==a4343^post_6 && a4545^0==a4545^post_6 && a77^0==a77^post_6 && b22^0==b22^post_6 && b2626^0==b2626^post_6 && b2929^0==b2929^post_6 && b3333^0==b3333^post_6 && b3535^0==b3535^post_6 && i^0==i^post_6 && i___01313^0==i___01313^post_6 && i___01717^0==i___01717^post_6 && i___02020^0==i___02020^post_6 && i___02424^0==i___02424^post_6 && i___04040^0==i___04040^post_6 && i___04747^0==i___04747^post_6 && i___099^0==i___099^post_6 && ioA^0==ioA^post_6 && ioR^0==ioR^post_6 && k1^0==k1^post_6 && k2^0==k2^post_6 && k3^0==k3^post_6 && k4^0==k4^post_6 && k5^0==k5^post_6 && keA^0==keA^post_6 && keR^0==keR^post_6 && ntStatus^0==ntStatus^post_6 && pIrb^0==pIrb^post_6 && phi_io_compl^0==phi_io_compl^post_6 && phi_nSUC_ret^0==phi_nSUC_ret^post_6 && prevCancel^0==prevCancel^post_6 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_6 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_6 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_6 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_6 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_6 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_6 ], cost: 1
      6: l6 -> l5 : AsyncAddressData^0'=AsyncAddressData^post_7, BusResetIrp^0'=BusResetIrp^post_7, CromData^0'=CromData^post_7, DeviceObject^0'=DeviceObject^post_7, Irp^0'=Irp^post_7, Irql^0'=Irql^post_7, IsochDetachData^0'=IsochDetachData^post_7, IsochResourceData^0'=IsochResourceData^post_7, ResourceIrp^0'=ResourceIrp^post_7, StackSize^0'=StackSize^post_7, __rho_10_^0'=__rho_10_^post_7, __rho_11_^0'=__rho_11_^post_7, __rho_12_^0'=__rho_12_^post_7, __rho_1_^0'=__rho_1_^post_7, __rho_2_^0'=__rho_2_^post_7, __rho_3_^0'=__rho_3_^post_7, __rho_4_^0'=__rho_4_^post_7, __rho_5_^0'=__rho_5_^post_7, __rho_666_^0'=__rho_666_^post_7, __rho_7_^0'=__rho_7_^post_7, __rho_8_^0'=__rho_8_^post_7, __rho_9_^0'=__rho_9_^post_7, a11^0'=a11^post_7, a1818^0'=a1818^post_7, a2525^0'=a2525^post_7, a2828^0'=a2828^post_7, a3131^0'=a3131^post_7, a3232^0'=a3232^post_7, a3434^0'=a3434^post_7, a3737^0'=a3737^post_7, a3838^0'=a3838^post_7, a4343^0'=a4343^post_7, a4545^0'=a4545^post_7, a77^0'=a77^post_7, b22^0'=b22^post_7, b2626^0'=b2626^post_7, b2929^0'=b2929^post_7, b3333^0'=b3333^post_7, b3535^0'=b3535^post_7, i^0'=i^post_7, i___01313^0'=i___01313^post_7, i___01717^0'=i___01717^post_7, i___02020^0'=i___02020^post_7, i___02424^0'=i___02424^post_7, i___04040^0'=i___04040^post_7, i___04747^0'=i___04747^post_7, i___099^0'=i___099^post_7, ioA^0'=ioA^post_7, ioR^0'=ioR^post_7, k1^0'=k1^post_7, k2^0'=k2^post_7, k3^0'=k3^post_7, k4^0'=k4^post_7, k5^0'=k5^post_7, keA^0'=keA^post_7, keR^0'=keR^post_7, ntStatus^0'=ntStatus^post_7, pIrb^0'=pIrb^post_7, phi_io_compl^0'=phi_io_compl^post_7, phi_nSUC_ret^0'=phi_nSUC_ret^post_7, prevCancel^0'=prevCancel^post_7, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_7, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_7, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_7, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_7, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_7, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_7, [ __rho_9_^post_7==__rho_9_^post_7 && AsyncAddressData^0==AsyncAddressData^post_7 && BusResetIrp^0==BusResetIrp^post_7 && CromData^0==CromData^post_7 && DeviceObject^0==DeviceObject^post_7 && Irp^0==Irp^post_7 && Irql^0==Irql^post_7 && IsochDetachData^0==IsochDetachData^post_7 && IsochResourceData^0==IsochResourceData^post_7 && ResourceIrp^0==ResourceIrp^post_7 && StackSize^0==StackSize^post_7 && __rho_10_^0==__rho_10_^post_7 && __rho_11_^0==__rho_11_^post_7 && __rho_12_^0==__rho_12_^post_7 && __rho_1_^0==__rho_1_^post_7 && __rho_2_^0==__rho_2_^post_7 && __rho_3_^0==__rho_3_^post_7 && __rho_4_^0==__rho_4_^post_7 && __rho_5_^0==__rho_5_^post_7 && __rho_666_^0==__rho_666_^post_7 && __rho_7_^0==__rho_7_^post_7 && __rho_8_^0==__rho_8_^post_7 && a11^0==a11^post_7 && a1818^0==a1818^post_7 && a2525^0==a2525^post_7 && a2828^0==a2828^post_7 && a3131^0==a3131^post_7 && a3232^0==a3232^post_7 && a3434^0==a3434^post_7 && a3737^0==a3737^post_7 && a3838^0==a3838^post_7 && a4343^0==a4343^post_7 && a4545^0==a4545^post_7 && a77^0==a77^post_7 && b22^0==b22^post_7 && b2626^0==b2626^post_7 && b2929^0==b2929^post_7 && b3333^0==b3333^post_7 && b3535^0==b3535^post_7 && i^0==i^post_7 && i___01313^0==i___01313^post_7 && i___01717^0==i___01717^post_7 && i___02020^0==i___02020^post_7 && i___02424^0==i___02424^post_7 && i___04040^0==i___04040^post_7 && i___04747^0==i___04747^post_7 && i___099^0==i___099^post_7 && ioA^0==ioA^post_7 && ioR^0==ioR^post_7 && k1^0==k1^post_7 && k2^0==k2^post_7 && k3^0==k3^post_7 && k4^0==k4^post_7 && k5^0==k5^post_7 && keA^0==keA^post_7 && keR^0==keR^post_7 && ntStatus^0==ntStatus^post_7 && pIrb^0==pIrb^post_7 && phi_io_compl^0==phi_io_compl^post_7 && phi_nSUC_ret^0==phi_nSUC_ret^post_7 && prevCancel^0==prevCancel^post_7 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_7 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_7 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_7 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_7 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_7 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_7 ], cost: 1
      7: l7 -> l6 : AsyncAddressData^0'=AsyncAddressData^post_8, BusResetIrp^0'=BusResetIrp^post_8, CromData^0'=CromData^post_8, DeviceObject^0'=DeviceObject^post_8, Irp^0'=Irp^post_8, Irql^0'=Irql^post_8, IsochDetachData^0'=IsochDetachData^post_8, IsochResourceData^0'=IsochResourceData^post_8, ResourceIrp^0'=ResourceIrp^post_8, StackSize^0'=StackSize^post_8, __rho_10_^0'=__rho_10_^post_8, __rho_11_^0'=__rho_11_^post_8, __rho_12_^0'=__rho_12_^post_8, __rho_1_^0'=__rho_1_^post_8, __rho_2_^0'=__rho_2_^post_8, __rho_3_^0'=__rho_3_^post_8, __rho_4_^0'=__rho_4_^post_8, __rho_5_^0'=__rho_5_^post_8, __rho_666_^0'=__rho_666_^post_8, __rho_7_^0'=__rho_7_^post_8, __rho_8_^0'=__rho_8_^post_8, __rho_9_^0'=__rho_9_^post_8, a11^0'=a11^post_8, a1818^0'=a1818^post_8, a2525^0'=a2525^post_8, a2828^0'=a2828^post_8, a3131^0'=a3131^post_8, a3232^0'=a3232^post_8, a3434^0'=a3434^post_8, a3737^0'=a3737^post_8, a3838^0'=a3838^post_8, a4343^0'=a4343^post_8, a4545^0'=a4545^post_8, a77^0'=a77^post_8, b22^0'=b22^post_8, b2626^0'=b2626^post_8, b2929^0'=b2929^post_8, b3333^0'=b3333^post_8, b3535^0'=b3535^post_8, i^0'=i^post_8, i___01313^0'=i___01313^post_8, i___01717^0'=i___01717^post_8, i___02020^0'=i___02020^post_8, i___02424^0'=i___02424^post_8, i___04040^0'=i___04040^post_8, i___04747^0'=i___04747^post_8, i___099^0'=i___099^post_8, ioA^0'=ioA^post_8, ioR^0'=ioR^post_8, k1^0'=k1^post_8, k2^0'=k2^post_8, k3^0'=k3^post_8, k4^0'=k4^post_8, k5^0'=k5^post_8, keA^0'=keA^post_8, keR^0'=keR^post_8, ntStatus^0'=ntStatus^post_8, pIrb^0'=pIrb^post_8, phi_io_compl^0'=phi_io_compl^post_8, phi_nSUC_ret^0'=phi_nSUC_ret^post_8, prevCancel^0'=prevCancel^post_8, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_8, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_8, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_8, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_8, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_8, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_8, [ __rho_8_^0<=0 && AsyncAddressData^0==AsyncAddressData^post_8 && BusResetIrp^0==BusResetIrp^post_8 && CromData^0==CromData^post_8 && DeviceObject^0==DeviceObject^post_8 && Irp^0==Irp^post_8 && Irql^0==Irql^post_8 && IsochDetachData^0==IsochDetachData^post_8 && IsochResourceData^0==IsochResourceData^post_8 && ResourceIrp^0==ResourceIrp^post_8 && StackSize^0==StackSize^post_8 && __rho_10_^0==__rho_10_^post_8 && __rho_11_^0==__rho_11_^post_8 && __rho_12_^0==__rho_12_^post_8 && __rho_1_^0==__rho_1_^post_8 && __rho_2_^0==__rho_2_^post_8 && __rho_3_^0==__rho_3_^post_8 && __rho_4_^0==__rho_4_^post_8 && __rho_5_^0==__rho_5_^post_8 && __rho_666_^0==__rho_666_^post_8 && __rho_7_^0==__rho_7_^post_8 && __rho_8_^0==__rho_8_^post_8 && __rho_9_^0==__rho_9_^post_8 && a11^0==a11^post_8 && a1818^0==a1818^post_8 && a2525^0==a2525^post_8 && a2828^0==a2828^post_8 && a3131^0==a3131^post_8 && a3232^0==a3232^post_8 && a3434^0==a3434^post_8 && a3737^0==a3737^post_8 && a3838^0==a3838^post_8 && a4343^0==a4343^post_8 && a4545^0==a4545^post_8 && a77^0==a77^post_8 && b22^0==b22^post_8 && b2626^0==b2626^post_8 && b2929^0==b2929^post_8 && b3333^0==b3333^post_8 && b3535^0==b3535^post_8 && i^0==i^post_8 && i___01313^0==i___01313^post_8 && i___01717^0==i___01717^post_8 && i___02020^0==i___02020^post_8 && i___02424^0==i___02424^post_8 && i___04040^0==i___04040^post_8 && i___04747^0==i___04747^post_8 && i___099^0==i___099^post_8 && ioA^0==ioA^post_8 && ioR^0==ioR^post_8 && k1^0==k1^post_8 && k2^0==k2^post_8 && k3^0==k3^post_8 && k4^0==k4^post_8 && k5^0==k5^post_8 && keA^0==keA^post_8 && keR^0==keR^post_8 && ntStatus^0==ntStatus^post_8 && pIrb^0==pIrb^post_8 && phi_io_compl^0==phi_io_compl^post_8 && phi_nSUC_ret^0==phi_nSUC_ret^post_8 && prevCancel^0==prevCancel^post_8 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_8 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_8 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_8 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_8 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_8 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_8 ], cost: 1
      8: l7 -> l6 : AsyncAddressData^0'=AsyncAddressData^post_9, BusResetIrp^0'=BusResetIrp^post_9, CromData^0'=CromData^post_9, DeviceObject^0'=DeviceObject^post_9, Irp^0'=Irp^post_9, Irql^0'=Irql^post_9, IsochDetachData^0'=IsochDetachData^post_9, IsochResourceData^0'=IsochResourceData^post_9, ResourceIrp^0'=ResourceIrp^post_9, StackSize^0'=StackSize^post_9, __rho_10_^0'=__rho_10_^post_9, __rho_11_^0'=__rho_11_^post_9, __rho_12_^0'=__rho_12_^post_9, __rho_1_^0'=__rho_1_^post_9, __rho_2_^0'=__rho_2_^post_9, __rho_3_^0'=__rho_3_^post_9, __rho_4_^0'=__rho_4_^post_9, __rho_5_^0'=__rho_5_^post_9, __rho_666_^0'=__rho_666_^post_9, __rho_7_^0'=__rho_7_^post_9, __rho_8_^0'=__rho_8_^post_9, __rho_9_^0'=__rho_9_^post_9, a11^0'=a11^post_9, a1818^0'=a1818^post_9, a2525^0'=a2525^post_9, a2828^0'=a2828^post_9, a3131^0'=a3131^post_9, a3232^0'=a3232^post_9, a3434^0'=a3434^post_9, a3737^0'=a3737^post_9, a3838^0'=a3838^post_9, a4343^0'=a4343^post_9, a4545^0'=a4545^post_9, a77^0'=a77^post_9, b22^0'=b22^post_9, b2626^0'=b2626^post_9, b2929^0'=b2929^post_9, b3333^0'=b3333^post_9, b3535^0'=b3535^post_9, i^0'=i^post_9, i___01313^0'=i___01313^post_9, i___01717^0'=i___01717^post_9, i___02020^0'=i___02020^post_9, i___02424^0'=i___02424^post_9, i___04040^0'=i___04040^post_9, i___04747^0'=i___04747^post_9, i___099^0'=i___099^post_9, ioA^0'=ioA^post_9, ioR^0'=ioR^post_9, k1^0'=k1^post_9, k2^0'=k2^post_9, k3^0'=k3^post_9, k4^0'=k4^post_9, k5^0'=k5^post_9, keA^0'=keA^post_9, keR^0'=keR^post_9, ntStatus^0'=ntStatus^post_9, pIrb^0'=pIrb^post_9, phi_io_compl^0'=phi_io_compl^post_9, phi_nSUC_ret^0'=phi_nSUC_ret^post_9, prevCancel^0'=prevCancel^post_9, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_9, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_9, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_9, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_9, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_9, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_9, [ 1<=__rho_8_^0 && AsyncAddressData^0==AsyncAddressData^post_9 && BusResetIrp^0==BusResetIrp^post_9 && CromData^0==CromData^post_9 && DeviceObject^0==DeviceObject^post_9 && Irp^0==Irp^post_9 && Irql^0==Irql^post_9 && IsochDetachData^0==IsochDetachData^post_9 && IsochResourceData^0==IsochResourceData^post_9 && ResourceIrp^0==ResourceIrp^post_9 && StackSize^0==StackSize^post_9 && __rho_10_^0==__rho_10_^post_9 && __rho_11_^0==__rho_11_^post_9 && __rho_12_^0==__rho_12_^post_9 && __rho_1_^0==__rho_1_^post_9 && __rho_2_^0==__rho_2_^post_9 && __rho_3_^0==__rho_3_^post_9 && __rho_4_^0==__rho_4_^post_9 && __rho_5_^0==__rho_5_^post_9 && __rho_666_^0==__rho_666_^post_9 && __rho_7_^0==__rho_7_^post_9 && __rho_8_^0==__rho_8_^post_9 && __rho_9_^0==__rho_9_^post_9 && a11^0==a11^post_9 && a1818^0==a1818^post_9 && a2525^0==a2525^post_9 && a2828^0==a2828^post_9 && a3131^0==a3131^post_9 && a3232^0==a3232^post_9 && a3434^0==a3434^post_9 && a3737^0==a3737^post_9 && a3838^0==a3838^post_9 && a4343^0==a4343^post_9 && a4545^0==a4545^post_9 && a77^0==a77^post_9 && b22^0==b22^post_9 && b2626^0==b2626^post_9 && b2929^0==b2929^post_9 && b3333^0==b3333^post_9 && b3535^0==b3535^post_9 && i^0==i^post_9 && i___01313^0==i___01313^post_9 && i___01717^0==i___01717^post_9 && i___02020^0==i___02020^post_9 && i___02424^0==i___02424^post_9 && i___04040^0==i___04040^post_9 && i___04747^0==i___04747^post_9 && i___099^0==i___099^post_9 && ioA^0==ioA^post_9 && ioR^0==ioR^post_9 && k1^0==k1^post_9 && k2^0==k2^post_9 && k3^0==k3^post_9 && k4^0==k4^post_9 && k5^0==k5^post_9 && keA^0==keA^post_9 && keR^0==keR^post_9 && ntStatus^0==ntStatus^post_9 && pIrb^0==pIrb^post_9 && phi_io_compl^0==phi_io_compl^post_9 && phi_nSUC_ret^0==phi_nSUC_ret^post_9 && prevCancel^0==prevCancel^post_9 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_9 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_9 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_9 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_9 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_9 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_9 ], cost: 1
      9: l8 -> l7 : AsyncAddressData^0'=AsyncAddressData^post_10, BusResetIrp^0'=BusResetIrp^post_10, CromData^0'=CromData^post_10, DeviceObject^0'=DeviceObject^post_10, Irp^0'=Irp^post_10, Irql^0'=Irql^post_10, IsochDetachData^0'=IsochDetachData^post_10, IsochResourceData^0'=IsochResourceData^post_10, ResourceIrp^0'=ResourceIrp^post_10, StackSize^0'=StackSize^post_10, __rho_10_^0'=__rho_10_^post_10, __rho_11_^0'=__rho_11_^post_10, __rho_12_^0'=__rho_12_^post_10, __rho_1_^0'=__rho_1_^post_10, __rho_2_^0'=__rho_2_^post_10, __rho_3_^0'=__rho_3_^post_10, __rho_4_^0'=__rho_4_^post_10, __rho_5_^0'=__rho_5_^post_10, __rho_666_^0'=__rho_666_^post_10, __rho_7_^0'=__rho_7_^post_10, __rho_8_^0'=__rho_8_^post_10, __rho_9_^0'=__rho_9_^post_10, a11^0'=a11^post_10, a1818^0'=a1818^post_10, a2525^0'=a2525^post_10, a2828^0'=a2828^post_10, a3131^0'=a3131^post_10, a3232^0'=a3232^post_10, a3434^0'=a3434^post_10, a3737^0'=a3737^post_10, a3838^0'=a3838^post_10, a4343^0'=a4343^post_10, a4545^0'=a4545^post_10, a77^0'=a77^post_10, b22^0'=b22^post_10, b2626^0'=b2626^post_10, b2929^0'=b2929^post_10, b3333^0'=b3333^post_10, b3535^0'=b3535^post_10, i^0'=i^post_10, i___01313^0'=i___01313^post_10, i___01717^0'=i___01717^post_10, i___02020^0'=i___02020^post_10, i___02424^0'=i___02424^post_10, i___04040^0'=i___04040^post_10, i___04747^0'=i___04747^post_10, i___099^0'=i___099^post_10, ioA^0'=ioA^post_10, ioR^0'=ioR^post_10, k1^0'=k1^post_10, k2^0'=k2^post_10, k3^0'=k3^post_10, k4^0'=k4^post_10, k5^0'=k5^post_10, keA^0'=keA^post_10, keR^0'=keR^post_10, ntStatus^0'=ntStatus^post_10, pIrb^0'=pIrb^post_10, phi_io_compl^0'=phi_io_compl^post_10, phi_nSUC_ret^0'=phi_nSUC_ret^post_10, prevCancel^0'=prevCancel^post_10, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_10, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_10, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_10, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_10, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_10, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_10, [ __rho_8_^post_10==__rho_8_^post_10 && AsyncAddressData^0==AsyncAddressData^post_10 && BusResetIrp^0==BusResetIrp^post_10 && CromData^0==CromData^post_10 && DeviceObject^0==DeviceObject^post_10 && Irp^0==Irp^post_10 && Irql^0==Irql^post_10 && IsochDetachData^0==IsochDetachData^post_10 && IsochResourceData^0==IsochResourceData^post_10 && ResourceIrp^0==ResourceIrp^post_10 && StackSize^0==StackSize^post_10 && __rho_10_^0==__rho_10_^post_10 && __rho_11_^0==__rho_11_^post_10 && __rho_12_^0==__rho_12_^post_10 && __rho_1_^0==__rho_1_^post_10 && __rho_2_^0==__rho_2_^post_10 && __rho_3_^0==__rho_3_^post_10 && __rho_4_^0==__rho_4_^post_10 && __rho_5_^0==__rho_5_^post_10 && __rho_666_^0==__rho_666_^post_10 && __rho_7_^0==__rho_7_^post_10 && __rho_9_^0==__rho_9_^post_10 && a11^0==a11^post_10 && a1818^0==a1818^post_10 && a2525^0==a2525^post_10 && a2828^0==a2828^post_10 && a3131^0==a3131^post_10 && a3232^0==a3232^post_10 && a3434^0==a3434^post_10 && a3737^0==a3737^post_10 && a3838^0==a3838^post_10 && a4343^0==a4343^post_10 && a4545^0==a4545^post_10 && a77^0==a77^post_10 && b22^0==b22^post_10 && b2626^0==b2626^post_10 && b2929^0==b2929^post_10 && b3333^0==b3333^post_10 && b3535^0==b3535^post_10 && i^0==i^post_10 && i___01313^0==i___01313^post_10 && i___01717^0==i___01717^post_10 && i___02020^0==i___02020^post_10 && i___02424^0==i___02424^post_10 && i___04040^0==i___04040^post_10 && i___04747^0==i___04747^post_10 && i___099^0==i___099^post_10 && ioA^0==ioA^post_10 && ioR^0==ioR^post_10 && k1^0==k1^post_10 && k2^0==k2^post_10 && k3^0==k3^post_10 && k4^0==k4^post_10 && k5^0==k5^post_10 && keA^0==keA^post_10 && keR^0==keR^post_10 && ntStatus^0==ntStatus^post_10 && pIrb^0==pIrb^post_10 && phi_io_compl^0==phi_io_compl^post_10 && phi_nSUC_ret^0==phi_nSUC_ret^post_10 && prevCancel^0==prevCancel^post_10 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_10 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_10 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_10 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_10 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_10 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_10 ], cost: 1
     10: l9 -> l8 : AsyncAddressData^0'=AsyncAddressData^post_11, BusResetIrp^0'=BusResetIrp^post_11, CromData^0'=CromData^post_11, DeviceObject^0'=DeviceObject^post_11, Irp^0'=Irp^post_11, Irql^0'=Irql^post_11, IsochDetachData^0'=IsochDetachData^post_11, IsochResourceData^0'=IsochResourceData^post_11, ResourceIrp^0'=ResourceIrp^post_11, StackSize^0'=StackSize^post_11, __rho_10_^0'=__rho_10_^post_11, __rho_11_^0'=__rho_11_^post_11, __rho_12_^0'=__rho_12_^post_11, __rho_1_^0'=__rho_1_^post_11, __rho_2_^0'=__rho_2_^post_11, __rho_3_^0'=__rho_3_^post_11, __rho_4_^0'=__rho_4_^post_11, __rho_5_^0'=__rho_5_^post_11, __rho_666_^0'=__rho_666_^post_11, __rho_7_^0'=__rho_7_^post_11, __rho_8_^0'=__rho_8_^post_11, __rho_9_^0'=__rho_9_^post_11, a11^0'=a11^post_11, a1818^0'=a1818^post_11, a2525^0'=a2525^post_11, a2828^0'=a2828^post_11, a3131^0'=a3131^post_11, a3232^0'=a3232^post_11, a3434^0'=a3434^post_11, a3737^0'=a3737^post_11, a3838^0'=a3838^post_11, a4343^0'=a4343^post_11, a4545^0'=a4545^post_11, a77^0'=a77^post_11, b22^0'=b22^post_11, b2626^0'=b2626^post_11, b2929^0'=b2929^post_11, b3333^0'=b3333^post_11, b3535^0'=b3535^post_11, i^0'=i^post_11, i___01313^0'=i___01313^post_11, i___01717^0'=i___01717^post_11, i___02020^0'=i___02020^post_11, i___02424^0'=i___02424^post_11, i___04040^0'=i___04040^post_11, i___04747^0'=i___04747^post_11, i___099^0'=i___099^post_11, ioA^0'=ioA^post_11, ioR^0'=ioR^post_11, k1^0'=k1^post_11, k2^0'=k2^post_11, k3^0'=k3^post_11, k4^0'=k4^post_11, k5^0'=k5^post_11, keA^0'=keA^post_11, keR^0'=keR^post_11, ntStatus^0'=ntStatus^post_11, pIrb^0'=pIrb^post_11, phi_io_compl^0'=phi_io_compl^post_11, phi_nSUC_ret^0'=phi_nSUC_ret^post_11, prevCancel^0'=prevCancel^post_11, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_11, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_11, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_11, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_11, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_11, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_11, [ __rho_7_^0<=0 && AsyncAddressData^0==AsyncAddressData^post_11 && BusResetIrp^0==BusResetIrp^post_11 && CromData^0==CromData^post_11 && DeviceObject^0==DeviceObject^post_11 && Irp^0==Irp^post_11 && Irql^0==Irql^post_11 && IsochDetachData^0==IsochDetachData^post_11 && IsochResourceData^0==IsochResourceData^post_11 && ResourceIrp^0==ResourceIrp^post_11 && StackSize^0==StackSize^post_11 && __rho_10_^0==__rho_10_^post_11 && __rho_11_^0==__rho_11_^post_11 && __rho_12_^0==__rho_12_^post_11 && __rho_1_^0==__rho_1_^post_11 && __rho_2_^0==__rho_2_^post_11 && __rho_3_^0==__rho_3_^post_11 && __rho_4_^0==__rho_4_^post_11 && __rho_5_^0==__rho_5_^post_11 && __rho_666_^0==__rho_666_^post_11 && __rho_7_^0==__rho_7_^post_11 && __rho_8_^0==__rho_8_^post_11 && __rho_9_^0==__rho_9_^post_11 && a11^0==a11^post_11 && a1818^0==a1818^post_11 && a2525^0==a2525^post_11 && a2828^0==a2828^post_11 && a3131^0==a3131^post_11 && a3232^0==a3232^post_11 && a3434^0==a3434^post_11 && a3737^0==a3737^post_11 && a3838^0==a3838^post_11 && a4343^0==a4343^post_11 && a4545^0==a4545^post_11 && a77^0==a77^post_11 && b22^0==b22^post_11 && b2626^0==b2626^post_11 && b2929^0==b2929^post_11 && b3333^0==b3333^post_11 && b3535^0==b3535^post_11 && i^0==i^post_11 && i___01313^0==i___01313^post_11 && i___01717^0==i___01717^post_11 && i___02020^0==i___02020^post_11 && i___02424^0==i___02424^post_11 && i___04040^0==i___04040^post_11 && i___04747^0==i___04747^post_11 && i___099^0==i___099^post_11 && ioA^0==ioA^post_11 && ioR^0==ioR^post_11 && k1^0==k1^post_11 && k2^0==k2^post_11 && k3^0==k3^post_11 && k4^0==k4^post_11 && k5^0==k5^post_11 && keA^0==keA^post_11 && keR^0==keR^post_11 && ntStatus^0==ntStatus^post_11 && pIrb^0==pIrb^post_11 && phi_io_compl^0==phi_io_compl^post_11 && phi_nSUC_ret^0==phi_nSUC_ret^post_11 && prevCancel^0==prevCancel^post_11 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_11 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_11 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_11 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_11 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_11 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_11 ], cost: 1
     11: l9 -> l8 : AsyncAddressData^0'=AsyncAddressData^post_12, BusResetIrp^0'=BusResetIrp^post_12, CromData^0'=CromData^post_12, DeviceObject^0'=DeviceObject^post_12, Irp^0'=Irp^post_12, Irql^0'=Irql^post_12, IsochDetachData^0'=IsochDetachData^post_12, IsochResourceData^0'=IsochResourceData^post_12, ResourceIrp^0'=ResourceIrp^post_12, StackSize^0'=StackSize^post_12, __rho_10_^0'=__rho_10_^post_12, __rho_11_^0'=__rho_11_^post_12, __rho_12_^0'=__rho_12_^post_12, __rho_1_^0'=__rho_1_^post_12, __rho_2_^0'=__rho_2_^post_12, __rho_3_^0'=__rho_3_^post_12, __rho_4_^0'=__rho_4_^post_12, __rho_5_^0'=__rho_5_^post_12, __rho_666_^0'=__rho_666_^post_12, __rho_7_^0'=__rho_7_^post_12, __rho_8_^0'=__rho_8_^post_12, __rho_9_^0'=__rho_9_^post_12, a11^0'=a11^post_12, a1818^0'=a1818^post_12, a2525^0'=a2525^post_12, a2828^0'=a2828^post_12, a3131^0'=a3131^post_12, a3232^0'=a3232^post_12, a3434^0'=a3434^post_12, a3737^0'=a3737^post_12, a3838^0'=a3838^post_12, a4343^0'=a4343^post_12, a4545^0'=a4545^post_12, a77^0'=a77^post_12, b22^0'=b22^post_12, b2626^0'=b2626^post_12, b2929^0'=b2929^post_12, b3333^0'=b3333^post_12, b3535^0'=b3535^post_12, i^0'=i^post_12, i___01313^0'=i___01313^post_12, i___01717^0'=i___01717^post_12, i___02020^0'=i___02020^post_12, i___02424^0'=i___02424^post_12, i___04040^0'=i___04040^post_12, i___04747^0'=i___04747^post_12, i___099^0'=i___099^post_12, ioA^0'=ioA^post_12, ioR^0'=ioR^post_12, k1^0'=k1^post_12, k2^0'=k2^post_12, k3^0'=k3^post_12, k4^0'=k4^post_12, k5^0'=k5^post_12, keA^0'=keA^post_12, keR^0'=keR^post_12, ntStatus^0'=ntStatus^post_12, pIrb^0'=pIrb^post_12, phi_io_compl^0'=phi_io_compl^post_12, phi_nSUC_ret^0'=phi_nSUC_ret^post_12, prevCancel^0'=prevCancel^post_12, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_12, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_12, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_12, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_12, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_12, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_12, [ 1<=__rho_7_^0 && AsyncAddressData^0==AsyncAddressData^post_12 && BusResetIrp^0==BusResetIrp^post_12 && CromData^0==CromData^post_12 && DeviceObject^0==DeviceObject^post_12 && Irp^0==Irp^post_12 && Irql^0==Irql^post_12 && IsochDetachData^0==IsochDetachData^post_12 && IsochResourceData^0==IsochResourceData^post_12 && ResourceIrp^0==ResourceIrp^post_12 && StackSize^0==StackSize^post_12 && __rho_10_^0==__rho_10_^post_12 && __rho_11_^0==__rho_11_^post_12 && __rho_12_^0==__rho_12_^post_12 && __rho_1_^0==__rho_1_^post_12 && __rho_2_^0==__rho_2_^post_12 && __rho_3_^0==__rho_3_^post_12 && __rho_4_^0==__rho_4_^post_12 && __rho_5_^0==__rho_5_^post_12 && __rho_666_^0==__rho_666_^post_12 && __rho_7_^0==__rho_7_^post_12 && __rho_8_^0==__rho_8_^post_12 && __rho_9_^0==__rho_9_^post_12 && a11^0==a11^post_12 && a1818^0==a1818^post_12 && a2525^0==a2525^post_12 && a2828^0==a2828^post_12 && a3131^0==a3131^post_12 && a3232^0==a3232^post_12 && a3434^0==a3434^post_12 && a3737^0==a3737^post_12 && a3838^0==a3838^post_12 && a4343^0==a4343^post_12 && a4545^0==a4545^post_12 && a77^0==a77^post_12 && b22^0==b22^post_12 && b2626^0==b2626^post_12 && b2929^0==b2929^post_12 && b3333^0==b3333^post_12 && b3535^0==b3535^post_12 && i^0==i^post_12 && i___01313^0==i___01313^post_12 && i___01717^0==i___01717^post_12 && i___02020^0==i___02020^post_12 && i___02424^0==i___02424^post_12 && i___04040^0==i___04040^post_12 && i___04747^0==i___04747^post_12 && i___099^0==i___099^post_12 && ioA^0==ioA^post_12 && ioR^0==ioR^post_12 && k1^0==k1^post_12 && k2^0==k2^post_12 && k3^0==k3^post_12 && k4^0==k4^post_12 && k5^0==k5^post_12 && keA^0==keA^post_12 && keR^0==keR^post_12 && ntStatus^0==ntStatus^post_12 && pIrb^0==pIrb^post_12 && phi_io_compl^0==phi_io_compl^post_12 && phi_nSUC_ret^0==phi_nSUC_ret^post_12 && prevCancel^0==prevCancel^post_12 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_12 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_12 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_12 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_12 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_12 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_12 ], cost: 1
     12: l10 -> l11 : AsyncAddressData^0'=AsyncAddressData^post_13, BusResetIrp^0'=BusResetIrp^post_13, CromData^0'=CromData^post_13, DeviceObject^0'=DeviceObject^post_13, Irp^0'=Irp^post_13, Irql^0'=Irql^post_13, IsochDetachData^0'=IsochDetachData^post_13, IsochResourceData^0'=IsochResourceData^post_13, ResourceIrp^0'=ResourceIrp^post_13, StackSize^0'=StackSize^post_13, __rho_10_^0'=__rho_10_^post_13, __rho_11_^0'=__rho_11_^post_13, __rho_12_^0'=__rho_12_^post_13, __rho_1_^0'=__rho_1_^post_13, __rho_2_^0'=__rho_2_^post_13, __rho_3_^0'=__rho_3_^post_13, __rho_4_^0'=__rho_4_^post_13, __rho_5_^0'=__rho_5_^post_13, __rho_666_^0'=__rho_666_^post_13, __rho_7_^0'=__rho_7_^post_13, __rho_8_^0'=__rho_8_^post_13, __rho_9_^0'=__rho_9_^post_13, a11^0'=a11^post_13, a1818^0'=a1818^post_13, a2525^0'=a2525^post_13, a2828^0'=a2828^post_13, a3131^0'=a3131^post_13, a3232^0'=a3232^post_13, a3434^0'=a3434^post_13, a3737^0'=a3737^post_13, a3838^0'=a3838^post_13, a4343^0'=a4343^post_13, a4545^0'=a4545^post_13, a77^0'=a77^post_13, b22^0'=b22^post_13, b2626^0'=b2626^post_13, b2929^0'=b2929^post_13, b3333^0'=b3333^post_13, b3535^0'=b3535^post_13, i^0'=i^post_13, i___01313^0'=i___01313^post_13, i___01717^0'=i___01717^post_13, i___02020^0'=i___02020^post_13, i___02424^0'=i___02424^post_13, i___04040^0'=i___04040^post_13, i___04747^0'=i___04747^post_13, i___099^0'=i___099^post_13, ioA^0'=ioA^post_13, ioR^0'=ioR^post_13, k1^0'=k1^post_13, k2^0'=k2^post_13, k3^0'=k3^post_13, k4^0'=k4^post_13, k5^0'=k5^post_13, keA^0'=keA^post_13, keR^0'=keR^post_13, ntStatus^0'=ntStatus^post_13, pIrb^0'=pIrb^post_13, phi_io_compl^0'=phi_io_compl^post_13, phi_nSUC_ret^0'=phi_nSUC_ret^post_13, prevCancel^0'=prevCancel^post_13, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_13, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_13, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_13, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_13, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_13, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_13, [ AsyncAddressData^0==AsyncAddressData^post_13 && BusResetIrp^0==BusResetIrp^post_13 && CromData^0==CromData^post_13 && DeviceObject^0==DeviceObject^post_13 && Irp^0==Irp^post_13 && Irql^0==Irql^post_13 && IsochDetachData^0==IsochDetachData^post_13 && IsochResourceData^0==IsochResourceData^post_13 && ResourceIrp^0==ResourceIrp^post_13 && StackSize^0==StackSize^post_13 && __rho_10_^0==__rho_10_^post_13 && __rho_11_^0==__rho_11_^post_13 && __rho_12_^0==__rho_12_^post_13 && __rho_1_^0==__rho_1_^post_13 && __rho_2_^0==__rho_2_^post_13 && __rho_3_^0==__rho_3_^post_13 && __rho_4_^0==__rho_4_^post_13 && __rho_5_^0==__rho_5_^post_13 && __rho_666_^0==__rho_666_^post_13 && __rho_7_^0==__rho_7_^post_13 && __rho_8_^0==__rho_8_^post_13 && __rho_9_^0==__rho_9_^post_13 && a11^0==a11^post_13 && a1818^0==a1818^post_13 && a2525^0==a2525^post_13 && a2828^0==a2828^post_13 && a3131^0==a3131^post_13 && a3232^0==a3232^post_13 && a3434^0==a3434^post_13 && a3737^0==a3737^post_13 && a3838^0==a3838^post_13 && a4343^0==a4343^post_13 && a4545^0==a4545^post_13 && a77^0==a77^post_13 && b22^0==b22^post_13 && b2626^0==b2626^post_13 && b2929^0==b2929^post_13 && b3333^0==b3333^post_13 && b3535^0==b3535^post_13 && i^0==i^post_13 && i___01313^0==i___01313^post_13 && i___01717^0==i___01717^post_13 && i___02020^0==i___02020^post_13 && i___02424^0==i___02424^post_13 && i___04040^0==i___04040^post_13 && i___04747^0==i___04747^post_13 && i___099^0==i___099^post_13 && ioA^0==ioA^post_13 && ioR^0==ioR^post_13 && k1^0==k1^post_13 && k2^0==k2^post_13 && k3^0==k3^post_13 && k4^0==k4^post_13 && k5^0==k5^post_13 && keA^0==keA^post_13 && keR^0==keR^post_13 && ntStatus^0==ntStatus^post_13 && pIrb^0==pIrb^post_13 && phi_io_compl^0==phi_io_compl^post_13 && phi_nSUC_ret^0==phi_nSUC_ret^post_13 && prevCancel^0==prevCancel^post_13 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_13 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_13 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_13 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_13 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_13 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_13 ], cost: 1
     26: l11 -> l18 : AsyncAddressData^0'=AsyncAddressData^post_27, BusResetIrp^0'=BusResetIrp^post_27, CromData^0'=CromData^post_27, DeviceObject^0'=DeviceObject^post_27, Irp^0'=Irp^post_27, Irql^0'=Irql^post_27, IsochDetachData^0'=IsochDetachData^post_27, IsochResourceData^0'=IsochResourceData^post_27, ResourceIrp^0'=ResourceIrp^post_27, StackSize^0'=StackSize^post_27, __rho_10_^0'=__rho_10_^post_27, __rho_11_^0'=__rho_11_^post_27, __rho_12_^0'=__rho_12_^post_27, __rho_1_^0'=__rho_1_^post_27, __rho_2_^0'=__rho_2_^post_27, __rho_3_^0'=__rho_3_^post_27, __rho_4_^0'=__rho_4_^post_27, __rho_5_^0'=__rho_5_^post_27, __rho_666_^0'=__rho_666_^post_27, __rho_7_^0'=__rho_7_^post_27, __rho_8_^0'=__rho_8_^post_27, __rho_9_^0'=__rho_9_^post_27, a11^0'=a11^post_27, a1818^0'=a1818^post_27, a2525^0'=a2525^post_27, a2828^0'=a2828^post_27, a3131^0'=a3131^post_27, a3232^0'=a3232^post_27, a3434^0'=a3434^post_27, a3737^0'=a3737^post_27, a3838^0'=a3838^post_27, a4343^0'=a4343^post_27, a4545^0'=a4545^post_27, a77^0'=a77^post_27, b22^0'=b22^post_27, b2626^0'=b2626^post_27, b2929^0'=b2929^post_27, b3333^0'=b3333^post_27, b3535^0'=b3535^post_27, i^0'=i^post_27, i___01313^0'=i___01313^post_27, i___01717^0'=i___01717^post_27, i___02020^0'=i___02020^post_27, i___02424^0'=i___02424^post_27, i___04040^0'=i___04040^post_27, i___04747^0'=i___04747^post_27, i___099^0'=i___099^post_27, ioA^0'=ioA^post_27, ioR^0'=ioR^post_27, k1^0'=k1^post_27, k2^0'=k2^post_27, k3^0'=k3^post_27, k4^0'=k4^post_27, k5^0'=k5^post_27, keA^0'=keA^post_27, keR^0'=keR^post_27, ntStatus^0'=ntStatus^post_27, pIrb^0'=pIrb^post_27, phi_io_compl^0'=phi_io_compl^post_27, phi_nSUC_ret^0'=phi_nSUC_ret^post_27, prevCancel^0'=prevCancel^post_27, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_27, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_27, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_27, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_27, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_27, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_27, [ 1<=k1^0 && CromData^post_27==CromData^post_27 && k1^post_27==-1+k1^0 && AsyncAddressData^0==AsyncAddressData^post_27 && BusResetIrp^0==BusResetIrp^post_27 && DeviceObject^0==DeviceObject^post_27 && Irp^0==Irp^post_27 && Irql^0==Irql^post_27 && IsochDetachData^0==IsochDetachData^post_27 && IsochResourceData^0==IsochResourceData^post_27 && ResourceIrp^0==ResourceIrp^post_27 && StackSize^0==StackSize^post_27 && __rho_10_^0==__rho_10_^post_27 && __rho_11_^0==__rho_11_^post_27 && __rho_12_^0==__rho_12_^post_27 && __rho_1_^0==__rho_1_^post_27 && __rho_2_^0==__rho_2_^post_27 && __rho_3_^0==__rho_3_^post_27 && __rho_4_^0==__rho_4_^post_27 && __rho_5_^0==__rho_5_^post_27 && __rho_666_^0==__rho_666_^post_27 && __rho_7_^0==__rho_7_^post_27 && __rho_8_^0==__rho_8_^post_27 && __rho_9_^0==__rho_9_^post_27 && a11^0==a11^post_27 && a1818^0==a1818^post_27 && a2525^0==a2525^post_27 && a2828^0==a2828^post_27 && a3131^0==a3131^post_27 && a3232^0==a3232^post_27 && a3434^0==a3434^post_27 && a3737^0==a3737^post_27 && a3838^0==a3838^post_27 && a4343^0==a4343^post_27 && a4545^0==a4545^post_27 && a77^0==a77^post_27 && b22^0==b22^post_27 && b2626^0==b2626^post_27 && b2929^0==b2929^post_27 && b3333^0==b3333^post_27 && b3535^0==b3535^post_27 && i^0==i^post_27 && i___01313^0==i___01313^post_27 && i___01717^0==i___01717^post_27 && i___02020^0==i___02020^post_27 && i___02424^0==i___02424^post_27 && i___04040^0==i___04040^post_27 && i___04747^0==i___04747^post_27 && i___099^0==i___099^post_27 && ioA^0==ioA^post_27 && ioR^0==ioR^post_27 && k2^0==k2^post_27 && k3^0==k3^post_27 && k4^0==k4^post_27 && k5^0==k5^post_27 && keA^0==keA^post_27 && keR^0==keR^post_27 && ntStatus^0==ntStatus^post_27 && pIrb^0==pIrb^post_27 && phi_io_compl^0==phi_io_compl^post_27 && phi_nSUC_ret^0==phi_nSUC_ret^post_27 && prevCancel^0==prevCancel^post_27 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_27 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_27 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_27 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_27 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_27 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_27 ], cost: 1
     27: l11 -> l4 : AsyncAddressData^0'=AsyncAddressData^post_28, BusResetIrp^0'=BusResetIrp^post_28, CromData^0'=CromData^post_28, DeviceObject^0'=DeviceObject^post_28, Irp^0'=Irp^post_28, Irql^0'=Irql^post_28, IsochDetachData^0'=IsochDetachData^post_28, IsochResourceData^0'=IsochResourceData^post_28, ResourceIrp^0'=ResourceIrp^post_28, StackSize^0'=StackSize^post_28, __rho_10_^0'=__rho_10_^post_28, __rho_11_^0'=__rho_11_^post_28, __rho_12_^0'=__rho_12_^post_28, __rho_1_^0'=__rho_1_^post_28, __rho_2_^0'=__rho_2_^post_28, __rho_3_^0'=__rho_3_^post_28, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_28, __rho_666_^0'=__rho_666_^post_28, __rho_7_^0'=__rho_7_^post_28, __rho_8_^0'=__rho_8_^post_28, __rho_9_^0'=__rho_9_^post_28, a11^0'=a11^post_28, a1818^0'=a1818^post_28, a2525^0'=a2525^post_28, a2828^0'=a2828^post_28, a3131^0'=a3131^post_28, a3232^0'=a3232^post_28, a3434^0'=a3434^post_28, a3737^0'=a3737^post_28, a3838^0'=a3838^post_28, a4343^0'=a4343^post_28, a4545^0'=a4545^post_28, a77^0'=a77^post_28, b22^0'=b22^post_28, b2626^0'=b2626^post_28, b2929^0'=b2929^post_28, b3333^0'=b3333^post_28, b3535^0'=b3535^post_28, i^0'=i^post_28, i___01313^0'=i___01313^post_28, i___01717^0'=i___01717^post_28, i___02020^0'=i___02020^post_28, i___02424^0'=i___02424^post_28, i___04040^0'=i___04040^post_28, i___04747^0'=i___04747^post_28, i___099^0'=i___099^post_28, ioA^0'=ioA^post_28, ioR^0'=ioR^post_28, k1^0'=k1^post_28, k2^0'=k2^post_28, k3^0'=k3^post_28, k4^0'=k4^post_28, k5^0'=k5^post_28, keA^0'=keA^post_28, keR^0'=keR^post_28, ntStatus^0'=ntStatus^post_28, pIrb^0'=pIrb^post_28, phi_io_compl^0'=phi_io_compl^post_28, phi_nSUC_ret^0'=phi_nSUC_ret^post_28, prevCancel^0'=prevCancel^post_28, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_28, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_28, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_28, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_28, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_28, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_28, [ k1^0<=0 && i___099^post_28==Irql^0 && keR^1_3_1==1 && keR^post_28==0 && keA^1_3==1 && keA^post_28==0 && __rho_4_^post_28==__rho_4_^post_28 && k2^post_28==__rho_4_^post_28 && AsyncAddressData^0==AsyncAddressData^post_28 && BusResetIrp^0==BusResetIrp^post_28 && CromData^0==CromData^post_28 && DeviceObject^0==DeviceObject^post_28 && Irp^0==Irp^post_28 && Irql^0==Irql^post_28 && IsochDetachData^0==IsochDetachData^post_28 && IsochResourceData^0==IsochResourceData^post_28 && ResourceIrp^0==ResourceIrp^post_28 && StackSize^0==StackSize^post_28 && __rho_10_^0==__rho_10_^post_28 && __rho_11_^0==__rho_11_^post_28 && __rho_12_^0==__rho_12_^post_28 && __rho_1_^0==__rho_1_^post_28 && __rho_2_^0==__rho_2_^post_28 && __rho_3_^0==__rho_3_^post_28 && __rho_5_^0==__rho_5_^post_28 && __rho_666_^0==__rho_666_^post_28 && __rho_7_^0==__rho_7_^post_28 && __rho_8_^0==__rho_8_^post_28 && __rho_9_^0==__rho_9_^post_28 && a11^0==a11^post_28 && a1818^0==a1818^post_28 && a2525^0==a2525^post_28 && a2828^0==a2828^post_28 && a3131^0==a3131^post_28 && a3232^0==a3232^post_28 && a3434^0==a3434^post_28 && a3737^0==a3737^post_28 && a3838^0==a3838^post_28 && a4343^0==a4343^post_28 && a4545^0==a4545^post_28 && a77^0==a77^post_28 && b22^0==b22^post_28 && b2626^0==b2626^post_28 && b2929^0==b2929^post_28 && b3333^0==b3333^post_28 && b3535^0==b3535^post_28 && i^0==i^post_28 && i___01313^0==i___01313^post_28 && i___01717^0==i___01717^post_28 && i___02020^0==i___02020^post_28 && i___02424^0==i___02424^post_28 && i___04040^0==i___04040^post_28 && i___04747^0==i___04747^post_28 && ioA^0==ioA^post_28 && ioR^0==ioR^post_28 && k1^0==k1^post_28 && k3^0==k3^post_28 && k4^0==k4^post_28 && k5^0==k5^post_28 && ntStatus^0==ntStatus^post_28 && pIrb^0==pIrb^post_28 && phi_io_compl^0==phi_io_compl^post_28 && phi_nSUC_ret^0==phi_nSUC_ret^post_28 && prevCancel^0==prevCancel^post_28 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_28 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_28 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_28 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_28 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_28 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_28 ], cost: 1
     13: l12 -> l9 : AsyncAddressData^0'=AsyncAddressData^post_14, BusResetIrp^0'=BusResetIrp^post_14, CromData^0'=CromData^post_14, DeviceObject^0'=DeviceObject^post_14, Irp^0'=Irp^post_14, Irql^0'=Irql^post_14, IsochDetachData^0'=IsochDetachData^post_14, IsochResourceData^0'=IsochResourceData^post_14, ResourceIrp^0'=ResourceIrp^post_14, StackSize^0'=StackSize^post_14, __rho_10_^0'=__rho_10_^post_14, __rho_11_^0'=__rho_11_^post_14, __rho_12_^0'=__rho_12_^post_14, __rho_1_^0'=__rho_1_^post_14, __rho_2_^0'=__rho_2_^post_14, __rho_3_^0'=__rho_3_^post_14, __rho_4_^0'=__rho_4_^post_14, __rho_5_^0'=__rho_5_^post_14, __rho_666_^0'=__rho_666_^post_14, __rho_7_^0'=__rho_7_^post_14, __rho_8_^0'=__rho_8_^post_14, __rho_9_^0'=__rho_9_^post_14, a11^0'=a11^post_14, a1818^0'=a1818^post_14, a2525^0'=a2525^post_14, a2828^0'=a2828^post_14, a3131^0'=a3131^post_14, a3232^0'=a3232^post_14, a3434^0'=a3434^post_14, a3737^0'=a3737^post_14, a3838^0'=a3838^post_14, a4343^0'=a4343^post_14, a4545^0'=a4545^post_14, a77^0'=a77^post_14, b22^0'=b22^post_14, b2626^0'=b2626^post_14, b2929^0'=b2929^post_14, b3333^0'=b3333^post_14, b3535^0'=b3535^post_14, i^0'=i^post_14, i___01313^0'=i___01313^post_14, i___01717^0'=i___01717^post_14, i___02020^0'=i___02020^post_14, i___02424^0'=i___02424^post_14, i___04040^0'=i___04040^post_14, i___04747^0'=i___04747^post_14, i___099^0'=i___099^post_14, ioA^0'=ioA^post_14, ioR^0'=ioR^post_14, k1^0'=k1^post_14, k2^0'=k2^post_14, k3^0'=k3^post_14, k4^0'=k4^post_14, k5^0'=k5^post_14, keA^0'=keA^post_14, keR^0'=keR^post_14, ntStatus^0'=ntStatus^post_14, pIrb^0'=pIrb^post_14, phi_io_compl^0'=phi_io_compl^post_14, phi_nSUC_ret^0'=phi_nSUC_ret^post_14, prevCancel^0'=prevCancel^post_14, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_14, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_14, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_14, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_14, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_14, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_14, [ 1<=k2^0 && AsyncAddressData^1_1==AsyncAddressData^1_1 && AsyncAddressData^post_14==AsyncAddressData^post_14 && k2^post_14==-1+k2^0 && __rho_7_^post_14==__rho_7_^post_14 && BusResetIrp^0==BusResetIrp^post_14 && CromData^0==CromData^post_14 && DeviceObject^0==DeviceObject^post_14 && Irp^0==Irp^post_14 && Irql^0==Irql^post_14 && IsochDetachData^0==IsochDetachData^post_14 && IsochResourceData^0==IsochResourceData^post_14 && ResourceIrp^0==ResourceIrp^post_14 && StackSize^0==StackSize^post_14 && __rho_10_^0==__rho_10_^post_14 && __rho_11_^0==__rho_11_^post_14 && __rho_12_^0==__rho_12_^post_14 && __rho_1_^0==__rho_1_^post_14 && __rho_2_^0==__rho_2_^post_14 && __rho_3_^0==__rho_3_^post_14 && __rho_4_^0==__rho_4_^post_14 && __rho_5_^0==__rho_5_^post_14 && __rho_666_^0==__rho_666_^post_14 && __rho_8_^0==__rho_8_^post_14 && __rho_9_^0==__rho_9_^post_14 && a11^0==a11^post_14 && a1818^0==a1818^post_14 && a2525^0==a2525^post_14 && a2828^0==a2828^post_14 && a3131^0==a3131^post_14 && a3232^0==a3232^post_14 && a3434^0==a3434^post_14 && a3737^0==a3737^post_14 && a3838^0==a3838^post_14 && a4343^0==a4343^post_14 && a4545^0==a4545^post_14 && a77^0==a77^post_14 && b22^0==b22^post_14 && b2626^0==b2626^post_14 && b2929^0==b2929^post_14 && b3333^0==b3333^post_14 && b3535^0==b3535^post_14 && i^0==i^post_14 && i___01313^0==i___01313^post_14 && i___01717^0==i___01717^post_14 && i___02020^0==i___02020^post_14 && i___02424^0==i___02424^post_14 && i___04040^0==i___04040^post_14 && i___04747^0==i___04747^post_14 && i___099^0==i___099^post_14 && ioA^0==ioA^post_14 && ioR^0==ioR^post_14 && k1^0==k1^post_14 && k3^0==k3^post_14 && k4^0==k4^post_14 && k5^0==k5^post_14 && keA^0==keA^post_14 && keR^0==keR^post_14 && ntStatus^0==ntStatus^post_14 && pIrb^0==pIrb^post_14 && phi_io_compl^0==phi_io_compl^post_14 && phi_nSUC_ret^0==phi_nSUC_ret^post_14 && prevCancel^0==prevCancel^post_14 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_14 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_14 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_14 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_14 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_14 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_14 ], cost: 1
     14: l12 -> l2 : AsyncAddressData^0'=AsyncAddressData^post_15, BusResetIrp^0'=BusResetIrp^post_15, CromData^0'=CromData^post_15, DeviceObject^0'=DeviceObject^post_15, Irp^0'=Irp^post_15, Irql^0'=Irql^post_15, IsochDetachData^0'=IsochDetachData^post_15, IsochResourceData^0'=IsochResourceData^post_15, ResourceIrp^0'=ResourceIrp^post_15, StackSize^0'=StackSize^post_15, __rho_10_^0'=__rho_10_^post_15, __rho_11_^0'=__rho_11_^post_15, __rho_12_^0'=__rho_12_^post_15, __rho_1_^0'=__rho_1_^post_15, __rho_2_^0'=__rho_2_^post_15, __rho_3_^0'=__rho_3_^post_15, __rho_4_^0'=__rho_4_^post_15, __rho_5_^0'=__rho_5_^post_15, __rho_666_^0'=__rho_666_^post_15, __rho_7_^0'=__rho_7_^post_15, __rho_8_^0'=__rho_8_^post_15, __rho_9_^0'=__rho_9_^post_15, a11^0'=a11^post_15, a1818^0'=a1818^post_15, a2525^0'=a2525^post_15, a2828^0'=a2828^post_15, a3131^0'=a3131^post_15, a3232^0'=a3232^post_15, a3434^0'=a3434^post_15, a3737^0'=a3737^post_15, a3838^0'=a3838^post_15, a4343^0'=a4343^post_15, a4545^0'=a4545^post_15, a77^0'=a77^post_15, b22^0'=b22^post_15, b2626^0'=b2626^post_15, b2929^0'=b2929^post_15, b3333^0'=b3333^post_15, b3535^0'=b3535^post_15, i^0'=i^post_15, i___01313^0'=i___01313^post_15, i___01717^0'=i___01717^post_15, i___02020^0'=i___02020^post_15, i___02424^0'=i___02424^post_15, i___04040^0'=i___04040^post_15, i___04747^0'=i___04747^post_15, i___099^0'=i___099^post_15, ioA^0'=ioA^post_15, ioR^0'=ioR^post_15, k1^0'=k1^post_15, k2^0'=k2^post_15, k3^0'=k3^post_15, k4^0'=k4^post_15, k5^0'=k5^post_15, keA^0'=keA^post_15, keR^0'=keR^post_15, ntStatus^0'=ntStatus^post_15, pIrb^0'=pIrb^post_15, phi_io_compl^0'=phi_io_compl^post_15, phi_nSUC_ret^0'=phi_nSUC_ret^post_15, prevCancel^0'=prevCancel^post_15, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_15, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_15, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_15, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_15, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_15, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_15, [ k2^0<=0 && i___01313^post_15==Irql^0 && keR^1_2_2==1 && keR^post_15==0 && __rho_10_^post_15==__rho_10_^post_15 && k3^post_15==__rho_10_^post_15 && AsyncAddressData^0==AsyncAddressData^post_15 && BusResetIrp^0==BusResetIrp^post_15 && CromData^0==CromData^post_15 && DeviceObject^0==DeviceObject^post_15 && Irp^0==Irp^post_15 && Irql^0==Irql^post_15 && IsochDetachData^0==IsochDetachData^post_15 && IsochResourceData^0==IsochResourceData^post_15 && ResourceIrp^0==ResourceIrp^post_15 && StackSize^0==StackSize^post_15 && __rho_11_^0==__rho_11_^post_15 && __rho_12_^0==__rho_12_^post_15 && __rho_1_^0==__rho_1_^post_15 && __rho_2_^0==__rho_2_^post_15 && __rho_3_^0==__rho_3_^post_15 && __rho_4_^0==__rho_4_^post_15 && __rho_5_^0==__rho_5_^post_15 && __rho_666_^0==__rho_666_^post_15 && __rho_7_^0==__rho_7_^post_15 && __rho_8_^0==__rho_8_^post_15 && __rho_9_^0==__rho_9_^post_15 && a11^0==a11^post_15 && a1818^0==a1818^post_15 && a2525^0==a2525^post_15 && a2828^0==a2828^post_15 && a3131^0==a3131^post_15 && a3232^0==a3232^post_15 && a3434^0==a3434^post_15 && a3737^0==a3737^post_15 && a3838^0==a3838^post_15 && a4343^0==a4343^post_15 && a4545^0==a4545^post_15 && a77^0==a77^post_15 && b22^0==b22^post_15 && b2626^0==b2626^post_15 && b2929^0==b2929^post_15 && b3333^0==b3333^post_15 && b3535^0==b3535^post_15 && i^0==i^post_15 && i___01717^0==i___01717^post_15 && i___02020^0==i___02020^post_15 && i___02424^0==i___02424^post_15 && i___04040^0==i___04040^post_15 && i___04747^0==i___04747^post_15 && i___099^0==i___099^post_15 && ioA^0==ioA^post_15 && ioR^0==ioR^post_15 && k1^0==k1^post_15 && k2^0==k2^post_15 && k4^0==k4^post_15 && k5^0==k5^post_15 && keA^0==keA^post_15 && ntStatus^0==ntStatus^post_15 && pIrb^0==pIrb^post_15 && phi_io_compl^0==phi_io_compl^post_15 && phi_nSUC_ret^0==phi_nSUC_ret^post_15 && prevCancel^0==prevCancel^post_15 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_15 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_15 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_15 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_15 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_15 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_15 ], cost: 1
     17: l13 -> l10 : AsyncAddressData^0'=AsyncAddressData^post_18, BusResetIrp^0'=BusResetIrp^post_18, CromData^0'=CromData^post_18, DeviceObject^0'=DeviceObject^post_18, Irp^0'=Irp^post_18, Irql^0'=Irql^post_18, IsochDetachData^0'=IsochDetachData^post_18, IsochResourceData^0'=IsochResourceData^post_18, ResourceIrp^0'=ResourceIrp^post_18, StackSize^0'=StackSize^post_18, __rho_10_^0'=__rho_10_^post_18, __rho_11_^0'=__rho_11_^post_18, __rho_12_^0'=__rho_12_^post_18, __rho_1_^0'=__rho_1_^post_18, __rho_2_^0'=__rho_2_^post_18, __rho_3_^0'=__rho_3_^post_18, __rho_4_^0'=__rho_4_^post_18, __rho_5_^0'=__rho_5_^post_18, __rho_666_^0'=__rho_666_^post_18, __rho_7_^0'=__rho_7_^post_18, __rho_8_^0'=__rho_8_^post_18, __rho_9_^0'=__rho_9_^post_18, a11^0'=a11^post_18, a1818^0'=a1818^post_18, a2525^0'=a2525^post_18, a2828^0'=a2828^post_18, a3131^0'=a3131^post_18, a3232^0'=a3232^post_18, a3434^0'=a3434^post_18, a3737^0'=a3737^post_18, a3838^0'=a3838^post_18, a4343^0'=a4343^post_18, a4545^0'=a4545^post_18, a77^0'=a77^post_18, b22^0'=b22^post_18, b2626^0'=b2626^post_18, b2929^0'=b2929^post_18, b3333^0'=b3333^post_18, b3535^0'=b3535^post_18, i^0'=i^post_18, i___01313^0'=i___01313^post_18, i___01717^0'=i___01717^post_18, i___02020^0'=i___02020^post_18, i___02424^0'=i___02424^post_18, i___04040^0'=i___04040^post_18, i___04747^0'=i___04747^post_18, i___099^0'=i___099^post_18, ioA^0'=ioA^post_18, ioR^0'=ioR^post_18, k1^0'=k1^post_18, k2^0'=k2^post_18, k3^0'=k3^post_18, k4^0'=k4^post_18, k5^0'=k5^post_18, keA^0'=keA^post_18, keR^0'=keR^post_18, ntStatus^0'=ntStatus^post_18, pIrb^0'=pIrb^post_18, phi_io_compl^0'=phi_io_compl^post_18, phi_nSUC_ret^0'=phi_nSUC_ret^post_18, prevCancel^0'=prevCancel^post_18, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_18, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_18, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_18, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_18, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_18, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_18, [ a77^post_18==CromData^0 && AsyncAddressData^0==AsyncAddressData^post_18 && BusResetIrp^0==BusResetIrp^post_18 && CromData^0==CromData^post_18 && DeviceObject^0==DeviceObject^post_18 && Irp^0==Irp^post_18 && Irql^0==Irql^post_18 && IsochDetachData^0==IsochDetachData^post_18 && IsochResourceData^0==IsochResourceData^post_18 && ResourceIrp^0==ResourceIrp^post_18 && StackSize^0==StackSize^post_18 && __rho_10_^0==__rho_10_^post_18 && __rho_11_^0==__rho_11_^post_18 && __rho_12_^0==__rho_12_^post_18 && __rho_1_^0==__rho_1_^post_18 && __rho_2_^0==__rho_2_^post_18 && __rho_3_^0==__rho_3_^post_18 && __rho_4_^0==__rho_4_^post_18 && __rho_5_^0==__rho_5_^post_18 && __rho_666_^0==__rho_666_^post_18 && __rho_7_^0==__rho_7_^post_18 && __rho_8_^0==__rho_8_^post_18 && __rho_9_^0==__rho_9_^post_18 && a11^0==a11^post_18 && a1818^0==a1818^post_18 && a2525^0==a2525^post_18 && a2828^0==a2828^post_18 && a3131^0==a3131^post_18 && a3232^0==a3232^post_18 && a3434^0==a3434^post_18 && a3737^0==a3737^post_18 && a3838^0==a3838^post_18 && a4343^0==a4343^post_18 && a4545^0==a4545^post_18 && b22^0==b22^post_18 && b2626^0==b2626^post_18 && b2929^0==b2929^post_18 && b3333^0==b3333^post_18 && b3535^0==b3535^post_18 && i^0==i^post_18 && i___01313^0==i___01313^post_18 && i___01717^0==i___01717^post_18 && i___02020^0==i___02020^post_18 && i___02424^0==i___02424^post_18 && i___04040^0==i___04040^post_18 && i___04747^0==i___04747^post_18 && i___099^0==i___099^post_18 && ioA^0==ioA^post_18 && ioR^0==ioR^post_18 && k1^0==k1^post_18 && k2^0==k2^post_18 && k3^0==k3^post_18 && k4^0==k4^post_18 && k5^0==k5^post_18 && keA^0==keA^post_18 && keR^0==keR^post_18 && ntStatus^0==ntStatus^post_18 && pIrb^0==pIrb^post_18 && phi_io_compl^0==phi_io_compl^post_18 && phi_nSUC_ret^0==phi_nSUC_ret^post_18 && prevCancel^0==prevCancel^post_18 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_18 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_18 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_18 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_18 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_18 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_18 ], cost: 1
     18: l14 -> l13 : AsyncAddressData^0'=AsyncAddressData^post_19, BusResetIrp^0'=BusResetIrp^post_19, CromData^0'=CromData^post_19, DeviceObject^0'=DeviceObject^post_19, Irp^0'=Irp^post_19, Irql^0'=Irql^post_19, IsochDetachData^0'=IsochDetachData^post_19, IsochResourceData^0'=IsochResourceData^post_19, ResourceIrp^0'=ResourceIrp^post_19, StackSize^0'=StackSize^post_19, __rho_10_^0'=__rho_10_^post_19, __rho_11_^0'=__rho_11_^post_19, __rho_12_^0'=__rho_12_^post_19, __rho_1_^0'=__rho_1_^post_19, __rho_2_^0'=__rho_2_^post_19, __rho_3_^0'=__rho_3_^post_19, __rho_4_^0'=__rho_4_^post_19, __rho_5_^0'=__rho_5_^post_19, __rho_666_^0'=__rho_666_^post_19, __rho_7_^0'=__rho_7_^post_19, __rho_8_^0'=__rho_8_^post_19, __rho_9_^0'=__rho_9_^post_19, a11^0'=a11^post_19, a1818^0'=a1818^post_19, a2525^0'=a2525^post_19, a2828^0'=a2828^post_19, a3131^0'=a3131^post_19, a3232^0'=a3232^post_19, a3434^0'=a3434^post_19, a3737^0'=a3737^post_19, a3838^0'=a3838^post_19, a4343^0'=a4343^post_19, a4545^0'=a4545^post_19, a77^0'=a77^post_19, b22^0'=b22^post_19, b2626^0'=b2626^post_19, b2929^0'=b2929^post_19, b3333^0'=b3333^post_19, b3535^0'=b3535^post_19, i^0'=i^post_19, i___01313^0'=i___01313^post_19, i___01717^0'=i___01717^post_19, i___02020^0'=i___02020^post_19, i___02424^0'=i___02424^post_19, i___04040^0'=i___04040^post_19, i___04747^0'=i___04747^post_19, i___099^0'=i___099^post_19, ioA^0'=ioA^post_19, ioR^0'=ioR^post_19, k1^0'=k1^post_19, k2^0'=k2^post_19, k3^0'=k3^post_19, k4^0'=k4^post_19, k5^0'=k5^post_19, keA^0'=keA^post_19, keR^0'=keR^post_19, ntStatus^0'=ntStatus^post_19, pIrb^0'=pIrb^post_19, phi_io_compl^0'=phi_io_compl^post_19, phi_nSUC_ret^0'=phi_nSUC_ret^post_19, prevCancel^0'=prevCancel^post_19, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_19, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_19, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_19, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_19, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_19, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_19, [ __rho_3_^0<=0 && AsyncAddressData^0==AsyncAddressData^post_19 && BusResetIrp^0==BusResetIrp^post_19 && CromData^0==CromData^post_19 && DeviceObject^0==DeviceObject^post_19 && Irp^0==Irp^post_19 && Irql^0==Irql^post_19 && IsochDetachData^0==IsochDetachData^post_19 && IsochResourceData^0==IsochResourceData^post_19 && ResourceIrp^0==ResourceIrp^post_19 && StackSize^0==StackSize^post_19 && __rho_10_^0==__rho_10_^post_19 && __rho_11_^0==__rho_11_^post_19 && __rho_12_^0==__rho_12_^post_19 && __rho_1_^0==__rho_1_^post_19 && __rho_2_^0==__rho_2_^post_19 && __rho_3_^0==__rho_3_^post_19 && __rho_4_^0==__rho_4_^post_19 && __rho_5_^0==__rho_5_^post_19 && __rho_666_^0==__rho_666_^post_19 && __rho_7_^0==__rho_7_^post_19 && __rho_8_^0==__rho_8_^post_19 && __rho_9_^0==__rho_9_^post_19 && a11^0==a11^post_19 && a1818^0==a1818^post_19 && a2525^0==a2525^post_19 && a2828^0==a2828^post_19 && a3131^0==a3131^post_19 && a3232^0==a3232^post_19 && a3434^0==a3434^post_19 && a3737^0==a3737^post_19 && a3838^0==a3838^post_19 && a4343^0==a4343^post_19 && a4545^0==a4545^post_19 && a77^0==a77^post_19 && b22^0==b22^post_19 && b2626^0==b2626^post_19 && b2929^0==b2929^post_19 && b3333^0==b3333^post_19 && b3535^0==b3535^post_19 && i^0==i^post_19 && i___01313^0==i___01313^post_19 && i___01717^0==i___01717^post_19 && i___02020^0==i___02020^post_19 && i___02424^0==i___02424^post_19 && i___04040^0==i___04040^post_19 && i___04747^0==i___04747^post_19 && i___099^0==i___099^post_19 && ioA^0==ioA^post_19 && ioR^0==ioR^post_19 && k1^0==k1^post_19 && k2^0==k2^post_19 && k3^0==k3^post_19 && k4^0==k4^post_19 && k5^0==k5^post_19 && keA^0==keA^post_19 && keR^0==keR^post_19 && ntStatus^0==ntStatus^post_19 && pIrb^0==pIrb^post_19 && phi_io_compl^0==phi_io_compl^post_19 && phi_nSUC_ret^0==phi_nSUC_ret^post_19 && prevCancel^0==prevCancel^post_19 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_19 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_19 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_19 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_19 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_19 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_19 ], cost: 1
     19: l14 -> l13 : AsyncAddressData^0'=AsyncAddressData^post_20, BusResetIrp^0'=BusResetIrp^post_20, CromData^0'=CromData^post_20, DeviceObject^0'=DeviceObject^post_20, Irp^0'=Irp^post_20, Irql^0'=Irql^post_20, IsochDetachData^0'=IsochDetachData^post_20, IsochResourceData^0'=IsochResourceData^post_20, ResourceIrp^0'=ResourceIrp^post_20, StackSize^0'=StackSize^post_20, __rho_10_^0'=__rho_10_^post_20, __rho_11_^0'=__rho_11_^post_20, __rho_12_^0'=__rho_12_^post_20, __rho_1_^0'=__rho_1_^post_20, __rho_2_^0'=__rho_2_^post_20, __rho_3_^0'=__rho_3_^post_20, __rho_4_^0'=__rho_4_^post_20, __rho_5_^0'=__rho_5_^post_20, __rho_666_^0'=__rho_666_^post_20, __rho_7_^0'=__rho_7_^post_20, __rho_8_^0'=__rho_8_^post_20, __rho_9_^0'=__rho_9_^post_20, a11^0'=a11^post_20, a1818^0'=a1818^post_20, a2525^0'=a2525^post_20, a2828^0'=a2828^post_20, a3131^0'=a3131^post_20, a3232^0'=a3232^post_20, a3434^0'=a3434^post_20, a3737^0'=a3737^post_20, a3838^0'=a3838^post_20, a4343^0'=a4343^post_20, a4545^0'=a4545^post_20, a77^0'=a77^post_20, b22^0'=b22^post_20, b2626^0'=b2626^post_20, b2929^0'=b2929^post_20, b3333^0'=b3333^post_20, b3535^0'=b3535^post_20, i^0'=i^post_20, i___01313^0'=i___01313^post_20, i___01717^0'=i___01717^post_20, i___02020^0'=i___02020^post_20, i___02424^0'=i___02424^post_20, i___04040^0'=i___04040^post_20, i___04747^0'=i___04747^post_20, i___099^0'=i___099^post_20, ioA^0'=ioA^post_20, ioR^0'=ioR^post_20, k1^0'=k1^post_20, k2^0'=k2^post_20, k3^0'=k3^post_20, k4^0'=k4^post_20, k5^0'=k5^post_20, keA^0'=keA^post_20, keR^0'=keR^post_20, ntStatus^0'=ntStatus^post_20, pIrb^0'=pIrb^post_20, phi_io_compl^0'=phi_io_compl^post_20, phi_nSUC_ret^0'=phi_nSUC_ret^post_20, prevCancel^0'=prevCancel^post_20, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_20, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_20, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_20, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_20, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_20, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_20, [ 1<=__rho_3_^0 && AsyncAddressData^0==AsyncAddressData^post_20 && BusResetIrp^0==BusResetIrp^post_20 && CromData^0==CromData^post_20 && DeviceObject^0==DeviceObject^post_20 && Irp^0==Irp^post_20 && Irql^0==Irql^post_20 && IsochDetachData^0==IsochDetachData^post_20 && IsochResourceData^0==IsochResourceData^post_20 && ResourceIrp^0==ResourceIrp^post_20 && StackSize^0==StackSize^post_20 && __rho_10_^0==__rho_10_^post_20 && __rho_11_^0==__rho_11_^post_20 && __rho_12_^0==__rho_12_^post_20 && __rho_1_^0==__rho_1_^post_20 && __rho_2_^0==__rho_2_^post_20 && __rho_3_^0==__rho_3_^post_20 && __rho_4_^0==__rho_4_^post_20 && __rho_5_^0==__rho_5_^post_20 && __rho_666_^0==__rho_666_^post_20 && __rho_7_^0==__rho_7_^post_20 && __rho_8_^0==__rho_8_^post_20 && __rho_9_^0==__rho_9_^post_20 && a11^0==a11^post_20 && a1818^0==a1818^post_20 && a2525^0==a2525^post_20 && a2828^0==a2828^post_20 && a3131^0==a3131^post_20 && a3232^0==a3232^post_20 && a3434^0==a3434^post_20 && a3737^0==a3737^post_20 && a3838^0==a3838^post_20 && a4343^0==a4343^post_20 && a4545^0==a4545^post_20 && a77^0==a77^post_20 && b22^0==b22^post_20 && b2626^0==b2626^post_20 && b2929^0==b2929^post_20 && b3333^0==b3333^post_20 && b3535^0==b3535^post_20 && i^0==i^post_20 && i___01313^0==i___01313^post_20 && i___01717^0==i___01717^post_20 && i___02020^0==i___02020^post_20 && i___02424^0==i___02424^post_20 && i___04040^0==i___04040^post_20 && i___04747^0==i___04747^post_20 && i___099^0==i___099^post_20 && ioA^0==ioA^post_20 && ioR^0==ioR^post_20 && k1^0==k1^post_20 && k2^0==k2^post_20 && k3^0==k3^post_20 && k4^0==k4^post_20 && k5^0==k5^post_20 && keA^0==keA^post_20 && keR^0==keR^post_20 && ntStatus^0==ntStatus^post_20 && pIrb^0==pIrb^post_20 && phi_io_compl^0==phi_io_compl^post_20 && phi_nSUC_ret^0==phi_nSUC_ret^post_20 && prevCancel^0==prevCancel^post_20 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_20 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_20 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_20 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_20 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_20 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_20 ], cost: 1
     20: l15 -> l14 : AsyncAddressData^0'=AsyncAddressData^post_21, BusResetIrp^0'=BusResetIrp^post_21, CromData^0'=CromData^post_21, DeviceObject^0'=DeviceObject^post_21, Irp^0'=Irp^post_21, Irql^0'=Irql^post_21, IsochDetachData^0'=IsochDetachData^post_21, IsochResourceData^0'=IsochResourceData^post_21, ResourceIrp^0'=ResourceIrp^post_21, StackSize^0'=StackSize^post_21, __rho_10_^0'=__rho_10_^post_21, __rho_11_^0'=__rho_11_^post_21, __rho_12_^0'=__rho_12_^post_21, __rho_1_^0'=__rho_1_^post_21, __rho_2_^0'=__rho_2_^post_21, __rho_3_^0'=__rho_3_^post_21, __rho_4_^0'=__rho_4_^post_21, __rho_5_^0'=__rho_5_^post_21, __rho_666_^0'=__rho_666_^post_21, __rho_7_^0'=__rho_7_^post_21, __rho_8_^0'=__rho_8_^post_21, __rho_9_^0'=__rho_9_^post_21, a11^0'=a11^post_21, a1818^0'=a1818^post_21, a2525^0'=a2525^post_21, a2828^0'=a2828^post_21, a3131^0'=a3131^post_21, a3232^0'=a3232^post_21, a3434^0'=a3434^post_21, a3737^0'=a3737^post_21, a3838^0'=a3838^post_21, a4343^0'=a4343^post_21, a4545^0'=a4545^post_21, a77^0'=a77^post_21, b22^0'=b22^post_21, b2626^0'=b2626^post_21, b2929^0'=b2929^post_21, b3333^0'=b3333^post_21, b3535^0'=b3535^post_21, i^0'=i^post_21, i___01313^0'=i___01313^post_21, i___01717^0'=i___01717^post_21, i___02020^0'=i___02020^post_21, i___02424^0'=i___02424^post_21, i___04040^0'=i___04040^post_21, i___04747^0'=i___04747^post_21, i___099^0'=i___099^post_21, ioA^0'=ioA^post_21, ioR^0'=ioR^post_21, k1^0'=k1^post_21, k2^0'=k2^post_21, k3^0'=k3^post_21, k4^0'=k4^post_21, k5^0'=k5^post_21, keA^0'=keA^post_21, keR^0'=keR^post_21, ntStatus^0'=ntStatus^post_21, pIrb^0'=pIrb^post_21, phi_io_compl^0'=phi_io_compl^post_21, phi_nSUC_ret^0'=phi_nSUC_ret^post_21, prevCancel^0'=prevCancel^post_21, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_21, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_21, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_21, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_21, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_21, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_21, [ __rho_3_^post_21==__rho_3_^post_21 && AsyncAddressData^0==AsyncAddressData^post_21 && BusResetIrp^0==BusResetIrp^post_21 && CromData^0==CromData^post_21 && DeviceObject^0==DeviceObject^post_21 && Irp^0==Irp^post_21 && Irql^0==Irql^post_21 && IsochDetachData^0==IsochDetachData^post_21 && IsochResourceData^0==IsochResourceData^post_21 && ResourceIrp^0==ResourceIrp^post_21 && StackSize^0==StackSize^post_21 && __rho_10_^0==__rho_10_^post_21 && __rho_11_^0==__rho_11_^post_21 && __rho_12_^0==__rho_12_^post_21 && __rho_1_^0==__rho_1_^post_21 && __rho_2_^0==__rho_2_^post_21 && __rho_4_^0==__rho_4_^post_21 && __rho_5_^0==__rho_5_^post_21 && __rho_666_^0==__rho_666_^post_21 && __rho_7_^0==__rho_7_^post_21 && __rho_8_^0==__rho_8_^post_21 && __rho_9_^0==__rho_9_^post_21 && a11^0==a11^post_21 && a1818^0==a1818^post_21 && a2525^0==a2525^post_21 && a2828^0==a2828^post_21 && a3131^0==a3131^post_21 && a3232^0==a3232^post_21 && a3434^0==a3434^post_21 && a3737^0==a3737^post_21 && a3838^0==a3838^post_21 && a4343^0==a4343^post_21 && a4545^0==a4545^post_21 && a77^0==a77^post_21 && b22^0==b22^post_21 && b2626^0==b2626^post_21 && b2929^0==b2929^post_21 && b3333^0==b3333^post_21 && b3535^0==b3535^post_21 && i^0==i^post_21 && i___01313^0==i___01313^post_21 && i___01717^0==i___01717^post_21 && i___02020^0==i___02020^post_21 && i___02424^0==i___02424^post_21 && i___04040^0==i___04040^post_21 && i___04747^0==i___04747^post_21 && i___099^0==i___099^post_21 && ioA^0==ioA^post_21 && ioR^0==ioR^post_21 && k1^0==k1^post_21 && k2^0==k2^post_21 && k3^0==k3^post_21 && k4^0==k4^post_21 && k5^0==k5^post_21 && keA^0==keA^post_21 && keR^0==keR^post_21 && ntStatus^0==ntStatus^post_21 && pIrb^0==pIrb^post_21 && phi_io_compl^0==phi_io_compl^post_21 && phi_nSUC_ret^0==phi_nSUC_ret^post_21 && prevCancel^0==prevCancel^post_21 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_21 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_21 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_21 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_21 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_21 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_21 ], cost: 1
     21: l16 -> l15 : AsyncAddressData^0'=AsyncAddressData^post_22, BusResetIrp^0'=BusResetIrp^post_22, CromData^0'=CromData^post_22, DeviceObject^0'=DeviceObject^post_22, Irp^0'=Irp^post_22, Irql^0'=Irql^post_22, IsochDetachData^0'=IsochDetachData^post_22, IsochResourceData^0'=IsochResourceData^post_22, ResourceIrp^0'=ResourceIrp^post_22, StackSize^0'=StackSize^post_22, __rho_10_^0'=__rho_10_^post_22, __rho_11_^0'=__rho_11_^post_22, __rho_12_^0'=__rho_12_^post_22, __rho_1_^0'=__rho_1_^post_22, __rho_2_^0'=__rho_2_^post_22, __rho_3_^0'=__rho_3_^post_22, __rho_4_^0'=__rho_4_^post_22, __rho_5_^0'=__rho_5_^post_22, __rho_666_^0'=__rho_666_^post_22, __rho_7_^0'=__rho_7_^post_22, __rho_8_^0'=__rho_8_^post_22, __rho_9_^0'=__rho_9_^post_22, a11^0'=a11^post_22, a1818^0'=a1818^post_22, a2525^0'=a2525^post_22, a2828^0'=a2828^post_22, a3131^0'=a3131^post_22, a3232^0'=a3232^post_22, a3434^0'=a3434^post_22, a3737^0'=a3737^post_22, a3838^0'=a3838^post_22, a4343^0'=a4343^post_22, a4545^0'=a4545^post_22, a77^0'=a77^post_22, b22^0'=b22^post_22, b2626^0'=b2626^post_22, b2929^0'=b2929^post_22, b3333^0'=b3333^post_22, b3535^0'=b3535^post_22, i^0'=i^post_22, i___01313^0'=i___01313^post_22, i___01717^0'=i___01717^post_22, i___02020^0'=i___02020^post_22, i___02424^0'=i___02424^post_22, i___04040^0'=i___04040^post_22, i___04747^0'=i___04747^post_22, i___099^0'=i___099^post_22, ioA^0'=ioA^post_22, ioR^0'=ioR^post_22, k1^0'=k1^post_22, k2^0'=k2^post_22, k3^0'=k3^post_22, k4^0'=k4^post_22, k5^0'=k5^post_22, keA^0'=keA^post_22, keR^0'=keR^post_22, ntStatus^0'=ntStatus^post_22, pIrb^0'=pIrb^post_22, phi_io_compl^0'=phi_io_compl^post_22, phi_nSUC_ret^0'=phi_nSUC_ret^post_22, prevCancel^0'=prevCancel^post_22, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_22, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_22, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_22, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_22, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_22, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_22, [ __rho_2_^0<=0 && AsyncAddressData^0==AsyncAddressData^post_22 && BusResetIrp^0==BusResetIrp^post_22 && CromData^0==CromData^post_22 && DeviceObject^0==DeviceObject^post_22 && Irp^0==Irp^post_22 && Irql^0==Irql^post_22 && IsochDetachData^0==IsochDetachData^post_22 && IsochResourceData^0==IsochResourceData^post_22 && ResourceIrp^0==ResourceIrp^post_22 && StackSize^0==StackSize^post_22 && __rho_10_^0==__rho_10_^post_22 && __rho_11_^0==__rho_11_^post_22 && __rho_12_^0==__rho_12_^post_22 && __rho_1_^0==__rho_1_^post_22 && __rho_2_^0==__rho_2_^post_22 && __rho_3_^0==__rho_3_^post_22 && __rho_4_^0==__rho_4_^post_22 && __rho_5_^0==__rho_5_^post_22 && __rho_666_^0==__rho_666_^post_22 && __rho_7_^0==__rho_7_^post_22 && __rho_8_^0==__rho_8_^post_22 && __rho_9_^0==__rho_9_^post_22 && a11^0==a11^post_22 && a1818^0==a1818^post_22 && a2525^0==a2525^post_22 && a2828^0==a2828^post_22 && a3131^0==a3131^post_22 && a3232^0==a3232^post_22 && a3434^0==a3434^post_22 && a3737^0==a3737^post_22 && a3838^0==a3838^post_22 && a4343^0==a4343^post_22 && a4545^0==a4545^post_22 && a77^0==a77^post_22 && b22^0==b22^post_22 && b2626^0==b2626^post_22 && b2929^0==b2929^post_22 && b3333^0==b3333^post_22 && b3535^0==b3535^post_22 && i^0==i^post_22 && i___01313^0==i___01313^post_22 && i___01717^0==i___01717^post_22 && i___02020^0==i___02020^post_22 && i___02424^0==i___02424^post_22 && i___04040^0==i___04040^post_22 && i___04747^0==i___04747^post_22 && i___099^0==i___099^post_22 && ioA^0==ioA^post_22 && ioR^0==ioR^post_22 && k1^0==k1^post_22 && k2^0==k2^post_22 && k3^0==k3^post_22 && k4^0==k4^post_22 && k5^0==k5^post_22 && keA^0==keA^post_22 && keR^0==keR^post_22 && ntStatus^0==ntStatus^post_22 && pIrb^0==pIrb^post_22 && phi_io_compl^0==phi_io_compl^post_22 && phi_nSUC_ret^0==phi_nSUC_ret^post_22 && prevCancel^0==prevCancel^post_22 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_22 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_22 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_22 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_22 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_22 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_22 ], cost: 1
     22: l16 -> l15 : AsyncAddressData^0'=AsyncAddressData^post_23, BusResetIrp^0'=BusResetIrp^post_23, CromData^0'=CromData^post_23, DeviceObject^0'=DeviceObject^post_23, Irp^0'=Irp^post_23, Irql^0'=Irql^post_23, IsochDetachData^0'=IsochDetachData^post_23, IsochResourceData^0'=IsochResourceData^post_23, ResourceIrp^0'=ResourceIrp^post_23, StackSize^0'=StackSize^post_23, __rho_10_^0'=__rho_10_^post_23, __rho_11_^0'=__rho_11_^post_23, __rho_12_^0'=__rho_12_^post_23, __rho_1_^0'=__rho_1_^post_23, __rho_2_^0'=__rho_2_^post_23, __rho_3_^0'=__rho_3_^post_23, __rho_4_^0'=__rho_4_^post_23, __rho_5_^0'=__rho_5_^post_23, __rho_666_^0'=__rho_666_^post_23, __rho_7_^0'=__rho_7_^post_23, __rho_8_^0'=__rho_8_^post_23, __rho_9_^0'=__rho_9_^post_23, a11^0'=a11^post_23, a1818^0'=a1818^post_23, a2525^0'=a2525^post_23, a2828^0'=a2828^post_23, a3131^0'=a3131^post_23, a3232^0'=a3232^post_23, a3434^0'=a3434^post_23, a3737^0'=a3737^post_23, a3838^0'=a3838^post_23, a4343^0'=a4343^post_23, a4545^0'=a4545^post_23, a77^0'=a77^post_23, b22^0'=b22^post_23, b2626^0'=b2626^post_23, b2929^0'=b2929^post_23, b3333^0'=b3333^post_23, b3535^0'=b3535^post_23, i^0'=i^post_23, i___01313^0'=i___01313^post_23, i___01717^0'=i___01717^post_23, i___02020^0'=i___02020^post_23, i___02424^0'=i___02424^post_23, i___04040^0'=i___04040^post_23, i___04747^0'=i___04747^post_23, i___099^0'=i___099^post_23, ioA^0'=ioA^post_23, ioR^0'=ioR^post_23, k1^0'=k1^post_23, k2^0'=k2^post_23, k3^0'=k3^post_23, k4^0'=k4^post_23, k5^0'=k5^post_23, keA^0'=keA^post_23, keR^0'=keR^post_23, ntStatus^0'=ntStatus^post_23, pIrb^0'=pIrb^post_23, phi_io_compl^0'=phi_io_compl^post_23, phi_nSUC_ret^0'=phi_nSUC_ret^post_23, prevCancel^0'=prevCancel^post_23, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_23, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_23, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_23, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_23, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_23, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_23, [ 1<=__rho_2_^0 && AsyncAddressData^0==AsyncAddressData^post_23 && BusResetIrp^0==BusResetIrp^post_23 && CromData^0==CromData^post_23 && DeviceObject^0==DeviceObject^post_23 && Irp^0==Irp^post_23 && Irql^0==Irql^post_23 && IsochDetachData^0==IsochDetachData^post_23 && IsochResourceData^0==IsochResourceData^post_23 && ResourceIrp^0==ResourceIrp^post_23 && StackSize^0==StackSize^post_23 && __rho_10_^0==__rho_10_^post_23 && __rho_11_^0==__rho_11_^post_23 && __rho_12_^0==__rho_12_^post_23 && __rho_1_^0==__rho_1_^post_23 && __rho_2_^0==__rho_2_^post_23 && __rho_3_^0==__rho_3_^post_23 && __rho_4_^0==__rho_4_^post_23 && __rho_5_^0==__rho_5_^post_23 && __rho_666_^0==__rho_666_^post_23 && __rho_7_^0==__rho_7_^post_23 && __rho_8_^0==__rho_8_^post_23 && __rho_9_^0==__rho_9_^post_23 && a11^0==a11^post_23 && a1818^0==a1818^post_23 && a2525^0==a2525^post_23 && a2828^0==a2828^post_23 && a3131^0==a3131^post_23 && a3232^0==a3232^post_23 && a3434^0==a3434^post_23 && a3737^0==a3737^post_23 && a3838^0==a3838^post_23 && a4343^0==a4343^post_23 && a4545^0==a4545^post_23 && a77^0==a77^post_23 && b22^0==b22^post_23 && b2626^0==b2626^post_23 && b2929^0==b2929^post_23 && b3333^0==b3333^post_23 && b3535^0==b3535^post_23 && i^0==i^post_23 && i___01313^0==i___01313^post_23 && i___01717^0==i___01717^post_23 && i___02020^0==i___02020^post_23 && i___02424^0==i___02424^post_23 && i___04040^0==i___04040^post_23 && i___04747^0==i___04747^post_23 && i___099^0==i___099^post_23 && ioA^0==ioA^post_23 && ioR^0==ioR^post_23 && k1^0==k1^post_23 && k2^0==k2^post_23 && k3^0==k3^post_23 && k4^0==k4^post_23 && k5^0==k5^post_23 && keA^0==keA^post_23 && keR^0==keR^post_23 && ntStatus^0==ntStatus^post_23 && pIrb^0==pIrb^post_23 && phi_io_compl^0==phi_io_compl^post_23 && phi_nSUC_ret^0==phi_nSUC_ret^post_23 && prevCancel^0==prevCancel^post_23 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_23 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_23 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_23 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_23 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_23 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_23 ], cost: 1
     49: l17 -> l19 : AsyncAddressData^0'=AsyncAddressData^post_50, BusResetIrp^0'=BusResetIrp^post_50, CromData^0'=CromData^post_50, DeviceObject^0'=DeviceObject^post_50, Irp^0'=Irp^post_50, Irql^0'=Irql^post_50, IsochDetachData^0'=IsochDetachData^post_50, IsochResourceData^0'=IsochResourceData^post_50, ResourceIrp^0'=ResourceIrp^post_50, StackSize^0'=StackSize^post_50, __rho_10_^0'=__rho_10_^post_50, __rho_11_^0'=__rho_11_^post_50, __rho_12_^0'=__rho_12_^post_50, __rho_1_^0'=__rho_1_^post_50, __rho_2_^0'=__rho_2_^post_50, __rho_3_^0'=__rho_3_^post_50, __rho_4_^0'=__rho_4_^post_50, __rho_5_^0'=__rho_5_^post_50, __rho_666_^0'=__rho_666_^post_50, __rho_7_^0'=__rho_7_^post_50, __rho_8_^0'=__rho_8_^post_50, __rho_9_^0'=__rho_9_^post_50, a11^0'=a11^post_50, a1818^0'=a1818^post_50, a2525^0'=a2525^post_50, a2828^0'=a2828^post_50, a3131^0'=a3131^post_50, a3232^0'=a3232^post_50, a3434^0'=a3434^post_50, a3737^0'=a3737^post_50, a3838^0'=a3838^post_50, a4343^0'=a4343^post_50, a4545^0'=a4545^post_50, a77^0'=a77^post_50, b22^0'=b22^post_50, b2626^0'=b2626^post_50, b2929^0'=b2929^post_50, b3333^0'=b3333^post_50, b3535^0'=b3535^post_50, i^0'=i^post_50, i___01313^0'=i___01313^post_50, i___01717^0'=i___01717^post_50, i___02020^0'=i___02020^post_50, i___02424^0'=i___02424^post_50, i___04040^0'=i___04040^post_50, i___04747^0'=i___04747^post_50, i___099^0'=i___099^post_50, ioA^0'=ioA^post_50, ioR^0'=ioR^post_50, k1^0'=k1^post_50, k2^0'=k2^post_50, k3^0'=k3^post_50, k4^0'=k4^post_50, k5^0'=k5^post_50, keA^0'=keA^post_50, keR^0'=keR^post_50, ntStatus^0'=ntStatus^post_50, pIrb^0'=pIrb^post_50, phi_io_compl^0'=phi_io_compl^post_50, phi_nSUC_ret^0'=phi_nSUC_ret^post_50, prevCancel^0'=prevCancel^post_50, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_50, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_50, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_50, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_50, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_50, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_50, [ k4^0<=0 && i___04040^post_50==Irql^0 && keR^1_4_1==1 && keR^post_50==0 && keA^1_5==1 && keA^post_50==0 && __rho_12_^post_50==__rho_12_^post_50 && k5^post_50==__rho_12_^post_50 && AsyncAddressData^0==AsyncAddressData^post_50 && BusResetIrp^0==BusResetIrp^post_50 && CromData^0==CromData^post_50 && DeviceObject^0==DeviceObject^post_50 && Irp^0==Irp^post_50 && Irql^0==Irql^post_50 && IsochDetachData^0==IsochDetachData^post_50 && IsochResourceData^0==IsochResourceData^post_50 && ResourceIrp^0==ResourceIrp^post_50 && StackSize^0==StackSize^post_50 && __rho_10_^0==__rho_10_^post_50 && __rho_11_^0==__rho_11_^post_50 && __rho_1_^0==__rho_1_^post_50 && __rho_2_^0==__rho_2_^post_50 && __rho_3_^0==__rho_3_^post_50 && __rho_4_^0==__rho_4_^post_50 && __rho_5_^0==__rho_5_^post_50 && __rho_666_^0==__rho_666_^post_50 && __rho_7_^0==__rho_7_^post_50 && __rho_8_^0==__rho_8_^post_50 && __rho_9_^0==__rho_9_^post_50 && a11^0==a11^post_50 && a1818^0==a1818^post_50 && a2525^0==a2525^post_50 && a2828^0==a2828^post_50 && a3131^0==a3131^post_50 && a3232^0==a3232^post_50 && a3434^0==a3434^post_50 && a3737^0==a3737^post_50 && a3838^0==a3838^post_50 && a4343^0==a4343^post_50 && a4545^0==a4545^post_50 && a77^0==a77^post_50 && b22^0==b22^post_50 && b2626^0==b2626^post_50 && b2929^0==b2929^post_50 && b3333^0==b3333^post_50 && b3535^0==b3535^post_50 && i^0==i^post_50 && i___01313^0==i___01313^post_50 && i___01717^0==i___01717^post_50 && i___02020^0==i___02020^post_50 && i___02424^0==i___02424^post_50 && i___04747^0==i___04747^post_50 && i___099^0==i___099^post_50 && ioA^0==ioA^post_50 && ioR^0==ioR^post_50 && k1^0==k1^post_50 && k2^0==k2^post_50 && k3^0==k3^post_50 && k4^0==k4^post_50 && ntStatus^0==ntStatus^post_50 && pIrb^0==pIrb^post_50 && phi_io_compl^0==phi_io_compl^post_50 && phi_nSUC_ret^0==phi_nSUC_ret^post_50 && prevCancel^0==prevCancel^post_50 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_50 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_50 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_50 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_50 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_50 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_50 ], cost: 1
     50: l17 -> l32 : AsyncAddressData^0'=AsyncAddressData^post_51, BusResetIrp^0'=BusResetIrp^post_51, CromData^0'=CromData^post_51, DeviceObject^0'=DeviceObject^post_51, Irp^0'=Irp^post_51, Irql^0'=Irql^post_51, IsochDetachData^0'=IsochDetachData^post_51, IsochResourceData^0'=IsochResourceData^post_51, ResourceIrp^0'=ResourceIrp^post_51, StackSize^0'=StackSize^post_51, __rho_10_^0'=__rho_10_^post_51, __rho_11_^0'=__rho_11_^post_51, __rho_12_^0'=__rho_12_^post_51, __rho_1_^0'=__rho_1_^post_51, __rho_2_^0'=__rho_2_^post_51, __rho_3_^0'=__rho_3_^post_51, __rho_4_^0'=__rho_4_^post_51, __rho_5_^0'=__rho_5_^post_51, __rho_666_^0'=__rho_666_^post_51, __rho_7_^0'=__rho_7_^post_51, __rho_8_^0'=__rho_8_^post_51, __rho_9_^0'=__rho_9_^post_51, a11^0'=a11^post_51, a1818^0'=a1818^post_51, a2525^0'=a2525^post_51, a2828^0'=a2828^post_51, a3131^0'=a3131^post_51, a3232^0'=a3232^post_51, a3434^0'=a3434^post_51, a3737^0'=a3737^post_51, a3838^0'=a3838^post_51, a4343^0'=a4343^post_51, a4545^0'=a4545^post_51, a77^0'=a77^post_51, b22^0'=b22^post_51, b2626^0'=b2626^post_51, b2929^0'=b2929^post_51, b3333^0'=b3333^post_51, b3535^0'=b3535^post_51, i^0'=i^post_51, i___01313^0'=i___01313^post_51, i___01717^0'=i___01717^post_51, i___02020^0'=i___02020^post_51, i___02424^0'=i___02424^post_51, i___04040^0'=i___04040^post_51, i___04747^0'=i___04747^post_51, i___099^0'=i___099^post_51, ioA^0'=ioA^post_51, ioR^0'=ioR^post_51, k1^0'=k1^post_51, k2^0'=k2^post_51, k3^0'=k3^post_51, k4^0'=k4^post_51, k5^0'=k5^post_51, keA^0'=keA^post_51, keR^0'=keR^post_51, ntStatus^0'=ntStatus^post_51, pIrb^0'=pIrb^post_51, phi_io_compl^0'=phi_io_compl^post_51, phi_nSUC_ret^0'=phi_nSUC_ret^post_51, prevCancel^0'=prevCancel^post_51, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_51, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_51, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_51, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_51, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_51, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_51, [ 1<=k4^0 && IsochResourceData^post_51==IsochResourceData^post_51 && k4^post_51==-1+k4^0 && i___02424^post_51==Irql^0 && keR^1_4_2==1 && keR^post_51==0 && AsyncAddressData^0==AsyncAddressData^post_51 && BusResetIrp^0==BusResetIrp^post_51 && CromData^0==CromData^post_51 && DeviceObject^0==DeviceObject^post_51 && Irp^0==Irp^post_51 && Irql^0==Irql^post_51 && IsochDetachData^0==IsochDetachData^post_51 && ResourceIrp^0==ResourceIrp^post_51 && StackSize^0==StackSize^post_51 && __rho_10_^0==__rho_10_^post_51 && __rho_11_^0==__rho_11_^post_51 && __rho_12_^0==__rho_12_^post_51 && __rho_1_^0==__rho_1_^post_51 && __rho_2_^0==__rho_2_^post_51 && __rho_3_^0==__rho_3_^post_51 && __rho_4_^0==__rho_4_^post_51 && __rho_5_^0==__rho_5_^post_51 && __rho_666_^0==__rho_666_^post_51 && __rho_7_^0==__rho_7_^post_51 && __rho_8_^0==__rho_8_^post_51 && __rho_9_^0==__rho_9_^post_51 && a11^0==a11^post_51 && a1818^0==a1818^post_51 && a2525^0==a2525^post_51 && a2828^0==a2828^post_51 && a3131^0==a3131^post_51 && a3232^0==a3232^post_51 && a3434^0==a3434^post_51 && a3737^0==a3737^post_51 && a3838^0==a3838^post_51 && a4343^0==a4343^post_51 && a4545^0==a4545^post_51 && a77^0==a77^post_51 && b22^0==b22^post_51 && b2626^0==b2626^post_51 && b2929^0==b2929^post_51 && b3333^0==b3333^post_51 && b3535^0==b3535^post_51 && i^0==i^post_51 && i___01313^0==i___01313^post_51 && i___01717^0==i___01717^post_51 && i___02020^0==i___02020^post_51 && i___04040^0==i___04040^post_51 && i___04747^0==i___04747^post_51 && i___099^0==i___099^post_51 && ioA^0==ioA^post_51 && ioR^0==ioR^post_51 && k1^0==k1^post_51 && k2^0==k2^post_51 && k3^0==k3^post_51 && k5^0==k5^post_51 && keA^0==keA^post_51 && ntStatus^0==ntStatus^post_51 && pIrb^0==pIrb^post_51 && phi_io_compl^0==phi_io_compl^post_51 && phi_nSUC_ret^0==phi_nSUC_ret^post_51 && prevCancel^0==prevCancel^post_51 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_51 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_51 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_51 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_51 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_51 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_51 ], cost: 1
     24: l18 -> l10 : AsyncAddressData^0'=AsyncAddressData^post_25, BusResetIrp^0'=BusResetIrp^post_25, CromData^0'=CromData^post_25, DeviceObject^0'=DeviceObject^post_25, Irp^0'=Irp^post_25, Irql^0'=Irql^post_25, IsochDetachData^0'=IsochDetachData^post_25, IsochResourceData^0'=IsochResourceData^post_25, ResourceIrp^0'=ResourceIrp^post_25, StackSize^0'=StackSize^post_25, __rho_10_^0'=__rho_10_^post_25, __rho_11_^0'=__rho_11_^post_25, __rho_12_^0'=__rho_12_^post_25, __rho_1_^0'=__rho_1_^post_25, __rho_2_^0'=__rho_2_^post_25, __rho_3_^0'=__rho_3_^post_25, __rho_4_^0'=__rho_4_^post_25, __rho_5_^0'=__rho_5_^post_25, __rho_666_^0'=__rho_666_^post_25, __rho_7_^0'=__rho_7_^post_25, __rho_8_^0'=__rho_8_^post_25, __rho_9_^0'=__rho_9_^post_25, a11^0'=a11^post_25, a1818^0'=a1818^post_25, a2525^0'=a2525^post_25, a2828^0'=a2828^post_25, a3131^0'=a3131^post_25, a3232^0'=a3232^post_25, a3434^0'=a3434^post_25, a3737^0'=a3737^post_25, a3838^0'=a3838^post_25, a4343^0'=a4343^post_25, a4545^0'=a4545^post_25, a77^0'=a77^post_25, b22^0'=b22^post_25, b2626^0'=b2626^post_25, b2929^0'=b2929^post_25, b3333^0'=b3333^post_25, b3535^0'=b3535^post_25, i^0'=i^post_25, i___01313^0'=i___01313^post_25, i___01717^0'=i___01717^post_25, i___02020^0'=i___02020^post_25, i___02424^0'=i___02424^post_25, i___04040^0'=i___04040^post_25, i___04747^0'=i___04747^post_25, i___099^0'=i___099^post_25, ioA^0'=ioA^post_25, ioR^0'=ioR^post_25, k1^0'=k1^post_25, k2^0'=k2^post_25, k3^0'=k3^post_25, k4^0'=k4^post_25, k5^0'=k5^post_25, keA^0'=keA^post_25, keR^0'=keR^post_25, ntStatus^0'=ntStatus^post_25, pIrb^0'=pIrb^post_25, phi_io_compl^0'=phi_io_compl^post_25, phi_nSUC_ret^0'=phi_nSUC_ret^post_25, prevCancel^0'=prevCancel^post_25, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_25, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_25, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_25, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_25, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_25, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_25, [ CromData^0<=0 && AsyncAddressData^0==AsyncAddressData^post_25 && BusResetIrp^0==BusResetIrp^post_25 && CromData^0==CromData^post_25 && DeviceObject^0==DeviceObject^post_25 && Irp^0==Irp^post_25 && Irql^0==Irql^post_25 && IsochDetachData^0==IsochDetachData^post_25 && IsochResourceData^0==IsochResourceData^post_25 && ResourceIrp^0==ResourceIrp^post_25 && StackSize^0==StackSize^post_25 && __rho_10_^0==__rho_10_^post_25 && __rho_11_^0==__rho_11_^post_25 && __rho_12_^0==__rho_12_^post_25 && __rho_1_^0==__rho_1_^post_25 && __rho_2_^0==__rho_2_^post_25 && __rho_3_^0==__rho_3_^post_25 && __rho_4_^0==__rho_4_^post_25 && __rho_5_^0==__rho_5_^post_25 && __rho_666_^0==__rho_666_^post_25 && __rho_7_^0==__rho_7_^post_25 && __rho_8_^0==__rho_8_^post_25 && __rho_9_^0==__rho_9_^post_25 && a11^0==a11^post_25 && a1818^0==a1818^post_25 && a2525^0==a2525^post_25 && a2828^0==a2828^post_25 && a3131^0==a3131^post_25 && a3232^0==a3232^post_25 && a3434^0==a3434^post_25 && a3737^0==a3737^post_25 && a3838^0==a3838^post_25 && a4343^0==a4343^post_25 && a4545^0==a4545^post_25 && a77^0==a77^post_25 && b22^0==b22^post_25 && b2626^0==b2626^post_25 && b2929^0==b2929^post_25 && b3333^0==b3333^post_25 && b3535^0==b3535^post_25 && i^0==i^post_25 && i___01313^0==i___01313^post_25 && i___01717^0==i___01717^post_25 && i___02020^0==i___02020^post_25 && i___02424^0==i___02424^post_25 && i___04040^0==i___04040^post_25 && i___04747^0==i___04747^post_25 && i___099^0==i___099^post_25 && ioA^0==ioA^post_25 && ioR^0==ioR^post_25 && k1^0==k1^post_25 && k2^0==k2^post_25 && k3^0==k3^post_25 && k4^0==k4^post_25 && k5^0==k5^post_25 && keA^0==keA^post_25 && keR^0==keR^post_25 && ntStatus^0==ntStatus^post_25 && pIrb^0==pIrb^post_25 && phi_io_compl^0==phi_io_compl^post_25 && phi_nSUC_ret^0==phi_nSUC_ret^post_25 && prevCancel^0==prevCancel^post_25 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_25 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_25 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_25 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_25 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_25 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_25 ], cost: 1
     25: l18 -> l16 : AsyncAddressData^0'=AsyncAddressData^post_26, BusResetIrp^0'=BusResetIrp^post_26, CromData^0'=CromData^post_26, DeviceObject^0'=DeviceObject^post_26, Irp^0'=Irp^post_26, Irql^0'=Irql^post_26, IsochDetachData^0'=IsochDetachData^post_26, IsochResourceData^0'=IsochResourceData^post_26, ResourceIrp^0'=ResourceIrp^post_26, StackSize^0'=StackSize^post_26, __rho_10_^0'=__rho_10_^post_26, __rho_11_^0'=__rho_11_^post_26, __rho_12_^0'=__rho_12_^post_26, __rho_1_^0'=__rho_1_^post_26, __rho_2_^0'=__rho_2_^post_26, __rho_3_^0'=__rho_3_^post_26, __rho_4_^0'=__rho_4_^post_26, __rho_5_^0'=__rho_5_^post_26, __rho_666_^0'=__rho_666_^post_26, __rho_7_^0'=__rho_7_^post_26, __rho_8_^0'=__rho_8_^post_26, __rho_9_^0'=__rho_9_^post_26, a11^0'=a11^post_26, a1818^0'=a1818^post_26, a2525^0'=a2525^post_26, a2828^0'=a2828^post_26, a3131^0'=a3131^post_26, a3232^0'=a3232^post_26, a3434^0'=a3434^post_26, a3737^0'=a3737^post_26, a3838^0'=a3838^post_26, a4343^0'=a4343^post_26, a4545^0'=a4545^post_26, a77^0'=a77^post_26, b22^0'=b22^post_26, b2626^0'=b2626^post_26, b2929^0'=b2929^post_26, b3333^0'=b3333^post_26, b3535^0'=b3535^post_26, i^0'=i^post_26, i___01313^0'=i___01313^post_26, i___01717^0'=i___01717^post_26, i___02020^0'=i___02020^post_26, i___02424^0'=i___02424^post_26, i___04040^0'=i___04040^post_26, i___04747^0'=i___04747^post_26, i___099^0'=i___099^post_26, ioA^0'=ioA^post_26, ioR^0'=ioR^post_26, k1^0'=k1^post_26, k2^0'=k2^post_26, k3^0'=k3^post_26, k4^0'=k4^post_26, k5^0'=k5^post_26, keA^0'=keA^post_26, keR^0'=keR^post_26, ntStatus^0'=ntStatus^post_26, pIrb^0'=pIrb^post_26, phi_io_compl^0'=phi_io_compl^post_26, phi_nSUC_ret^0'=phi_nSUC_ret^post_26, prevCancel^0'=prevCancel^post_26, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_26, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_26, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_26, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_26, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_26, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_26, [ 1<=CromData^0 && __rho_2_^post_26==__rho_2_^post_26 && AsyncAddressData^0==AsyncAddressData^post_26 && BusResetIrp^0==BusResetIrp^post_26 && CromData^0==CromData^post_26 && DeviceObject^0==DeviceObject^post_26 && Irp^0==Irp^post_26 && Irql^0==Irql^post_26 && IsochDetachData^0==IsochDetachData^post_26 && IsochResourceData^0==IsochResourceData^post_26 && ResourceIrp^0==ResourceIrp^post_26 && StackSize^0==StackSize^post_26 && __rho_10_^0==__rho_10_^post_26 && __rho_11_^0==__rho_11_^post_26 && __rho_12_^0==__rho_12_^post_26 && __rho_1_^0==__rho_1_^post_26 && __rho_3_^0==__rho_3_^post_26 && __rho_4_^0==__rho_4_^post_26 && __rho_5_^0==__rho_5_^post_26 && __rho_666_^0==__rho_666_^post_26 && __rho_7_^0==__rho_7_^post_26 && __rho_8_^0==__rho_8_^post_26 && __rho_9_^0==__rho_9_^post_26 && a11^0==a11^post_26 && a1818^0==a1818^post_26 && a2525^0==a2525^post_26 && a2828^0==a2828^post_26 && a3131^0==a3131^post_26 && a3232^0==a3232^post_26 && a3434^0==a3434^post_26 && a3737^0==a3737^post_26 && a3838^0==a3838^post_26 && a4343^0==a4343^post_26 && a4545^0==a4545^post_26 && a77^0==a77^post_26 && b22^0==b22^post_26 && b2626^0==b2626^post_26 && b2929^0==b2929^post_26 && b3333^0==b3333^post_26 && b3535^0==b3535^post_26 && i^0==i^post_26 && i___01313^0==i___01313^post_26 && i___01717^0==i___01717^post_26 && i___02020^0==i___02020^post_26 && i___02424^0==i___02424^post_26 && i___04040^0==i___04040^post_26 && i___04747^0==i___04747^post_26 && i___099^0==i___099^post_26 && ioA^0==ioA^post_26 && ioR^0==ioR^post_26 && k1^0==k1^post_26 && k2^0==k2^post_26 && k3^0==k3^post_26 && k4^0==k4^post_26 && k5^0==k5^post_26 && keA^0==keA^post_26 && keR^0==keR^post_26 && ntStatus^0==ntStatus^post_26 && pIrb^0==pIrb^post_26 && phi_io_compl^0==phi_io_compl^post_26 && phi_nSUC_ret^0==phi_nSUC_ret^post_26 && prevCancel^0==prevCancel^post_26 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_26 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_26 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_26 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_26 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_26 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_26 ], cost: 1
     28: l19 -> l20 : AsyncAddressData^0'=AsyncAddressData^post_29, BusResetIrp^0'=BusResetIrp^post_29, CromData^0'=CromData^post_29, DeviceObject^0'=DeviceObject^post_29, Irp^0'=Irp^post_29, Irql^0'=Irql^post_29, IsochDetachData^0'=IsochDetachData^post_29, IsochResourceData^0'=IsochResourceData^post_29, ResourceIrp^0'=ResourceIrp^post_29, StackSize^0'=StackSize^post_29, __rho_10_^0'=__rho_10_^post_29, __rho_11_^0'=__rho_11_^post_29, __rho_12_^0'=__rho_12_^post_29, __rho_1_^0'=__rho_1_^post_29, __rho_2_^0'=__rho_2_^post_29, __rho_3_^0'=__rho_3_^post_29, __rho_4_^0'=__rho_4_^post_29, __rho_5_^0'=__rho_5_^post_29, __rho_666_^0'=__rho_666_^post_29, __rho_7_^0'=__rho_7_^post_29, __rho_8_^0'=__rho_8_^post_29, __rho_9_^0'=__rho_9_^post_29, a11^0'=a11^post_29, a1818^0'=a1818^post_29, a2525^0'=a2525^post_29, a2828^0'=a2828^post_29, a3131^0'=a3131^post_29, a3232^0'=a3232^post_29, a3434^0'=a3434^post_29, a3737^0'=a3737^post_29, a3838^0'=a3838^post_29, a4343^0'=a4343^post_29, a4545^0'=a4545^post_29, a77^0'=a77^post_29, b22^0'=b22^post_29, b2626^0'=b2626^post_29, b2929^0'=b2929^post_29, b3333^0'=b3333^post_29, b3535^0'=b3535^post_29, i^0'=i^post_29, i___01313^0'=i___01313^post_29, i___01717^0'=i___01717^post_29, i___02020^0'=i___02020^post_29, i___02424^0'=i___02424^post_29, i___04040^0'=i___04040^post_29, i___04747^0'=i___04747^post_29, i___099^0'=i___099^post_29, ioA^0'=ioA^post_29, ioR^0'=ioR^post_29, k1^0'=k1^post_29, k2^0'=k2^post_29, k3^0'=k3^post_29, k4^0'=k4^post_29, k5^0'=k5^post_29, keA^0'=keA^post_29, keR^0'=keR^post_29, ntStatus^0'=ntStatus^post_29, pIrb^0'=pIrb^post_29, phi_io_compl^0'=phi_io_compl^post_29, phi_nSUC_ret^0'=phi_nSUC_ret^post_29, prevCancel^0'=prevCancel^post_29, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_29, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_29, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_29, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_29, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_29, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_29, [ AsyncAddressData^0==AsyncAddressData^post_29 && BusResetIrp^0==BusResetIrp^post_29 && CromData^0==CromData^post_29 && DeviceObject^0==DeviceObject^post_29 && Irp^0==Irp^post_29 && Irql^0==Irql^post_29 && IsochDetachData^0==IsochDetachData^post_29 && IsochResourceData^0==IsochResourceData^post_29 && ResourceIrp^0==ResourceIrp^post_29 && StackSize^0==StackSize^post_29 && __rho_10_^0==__rho_10_^post_29 && __rho_11_^0==__rho_11_^post_29 && __rho_12_^0==__rho_12_^post_29 && __rho_1_^0==__rho_1_^post_29 && __rho_2_^0==__rho_2_^post_29 && __rho_3_^0==__rho_3_^post_29 && __rho_4_^0==__rho_4_^post_29 && __rho_5_^0==__rho_5_^post_29 && __rho_666_^0==__rho_666_^post_29 && __rho_7_^0==__rho_7_^post_29 && __rho_8_^0==__rho_8_^post_29 && __rho_9_^0==__rho_9_^post_29 && a11^0==a11^post_29 && a1818^0==a1818^post_29 && a2525^0==a2525^post_29 && a2828^0==a2828^post_29 && a3131^0==a3131^post_29 && a3232^0==a3232^post_29 && a3434^0==a3434^post_29 && a3737^0==a3737^post_29 && a3838^0==a3838^post_29 && a4343^0==a4343^post_29 && a4545^0==a4545^post_29 && a77^0==a77^post_29 && b22^0==b22^post_29 && b2626^0==b2626^post_29 && b2929^0==b2929^post_29 && b3333^0==b3333^post_29 && b3535^0==b3535^post_29 && i^0==i^post_29 && i___01313^0==i___01313^post_29 && i___01717^0==i___01717^post_29 && i___02020^0==i___02020^post_29 && i___02424^0==i___02424^post_29 && i___04040^0==i___04040^post_29 && i___04747^0==i___04747^post_29 && i___099^0==i___099^post_29 && ioA^0==ioA^post_29 && ioR^0==ioR^post_29 && k1^0==k1^post_29 && k2^0==k2^post_29 && k3^0==k3^post_29 && k4^0==k4^post_29 && k5^0==k5^post_29 && keA^0==keA^post_29 && keR^0==keR^post_29 && ntStatus^0==ntStatus^post_29 && pIrb^0==pIrb^post_29 && phi_io_compl^0==phi_io_compl^post_29 && phi_nSUC_ret^0==phi_nSUC_ret^post_29 && prevCancel^0==prevCancel^post_29 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_29 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_29 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_29 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_29 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_29 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_29 ], cost: 1
     37: l20 -> l19 : AsyncAddressData^0'=AsyncAddressData^post_38, BusResetIrp^0'=BusResetIrp^post_38, CromData^0'=CromData^post_38, DeviceObject^0'=DeviceObject^post_38, Irp^0'=Irp^post_38, Irql^0'=Irql^post_38, IsochDetachData^0'=IsochDetachData^post_38, IsochResourceData^0'=IsochResourceData^post_38, ResourceIrp^0'=ResourceIrp^post_38, StackSize^0'=StackSize^post_38, __rho_10_^0'=__rho_10_^post_38, __rho_11_^0'=__rho_11_^post_38, __rho_12_^0'=__rho_12_^post_38, __rho_1_^0'=__rho_1_^post_38, __rho_2_^0'=__rho_2_^post_38, __rho_3_^0'=__rho_3_^post_38, __rho_4_^0'=__rho_4_^post_38, __rho_5_^0'=__rho_5_^post_38, __rho_666_^0'=__rho_666_^post_38, __rho_7_^0'=__rho_7_^post_38, __rho_8_^0'=__rho_8_^post_38, __rho_9_^0'=__rho_9_^post_38, a11^0'=a11^post_38, a1818^0'=a1818^post_38, a2525^0'=a2525^post_38, a2828^0'=a2828^post_38, a3131^0'=a3131^post_38, a3232^0'=a3232^post_38, a3434^0'=a3434^post_38, a3737^0'=a3737^post_38, a3838^0'=a3838^post_38, a4343^0'=a4343^post_38, a4545^0'=a4545^post_38, a77^0'=a77^post_38, b22^0'=b22^post_38, b2626^0'=b2626^post_38, b2929^0'=b2929^post_38, b3333^0'=b3333^post_38, b3535^0'=b3535^post_38, i^0'=i^post_38, i___01313^0'=i___01313^post_38, i___01717^0'=i___01717^post_38, i___02020^0'=i___02020^post_38, i___02424^0'=i___02424^post_38, i___04040^0'=i___04040^post_38, i___04747^0'=i___04747^post_38, i___099^0'=i___099^post_38, ioA^0'=ioA^post_38, ioR^0'=ioR^post_38, k1^0'=k1^post_38, k2^0'=k2^post_38, k3^0'=k3^post_38, k4^0'=k4^post_38, k5^0'=k5^post_38, keA^0'=keA^post_38, keR^0'=keR^post_38, ntStatus^0'=ntStatus^post_38, pIrb^0'=pIrb^post_38, phi_io_compl^0'=phi_io_compl^post_38, phi_nSUC_ret^0'=phi_nSUC_ret^post_38, prevCancel^0'=prevCancel^post_38, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_38, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_38, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_38, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_38, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_38, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_38, [ 1<=k5^0 && prevCancel^1_1==0 && BusResetIrp^post_38==BusResetIrp^post_38 && k5^post_38==-1+k5^0 && a4343^post_38==0 && ret_IoSetCancelRoutine4444^post_38==0 && prevCancel^post_38==ret_IoSetCancelRoutine4444^post_38 && phi_io_compl^post_38==1 && a4545^post_38==BusResetIrp^post_38 && AsyncAddressData^0==AsyncAddressData^post_38 && CromData^0==CromData^post_38 && DeviceObject^0==DeviceObject^post_38 && Irp^0==Irp^post_38 && Irql^0==Irql^post_38 && IsochDetachData^0==IsochDetachData^post_38 && IsochResourceData^0==IsochResourceData^post_38 && ResourceIrp^0==ResourceIrp^post_38 && StackSize^0==StackSize^post_38 && __rho_10_^0==__rho_10_^post_38 && __rho_11_^0==__rho_11_^post_38 && __rho_12_^0==__rho_12_^post_38 && __rho_1_^0==__rho_1_^post_38 && __rho_2_^0==__rho_2_^post_38 && __rho_3_^0==__rho_3_^post_38 && __rho_4_^0==__rho_4_^post_38 && __rho_5_^0==__rho_5_^post_38 && __rho_666_^0==__rho_666_^post_38 && __rho_7_^0==__rho_7_^post_38 && __rho_8_^0==__rho_8_^post_38 && __rho_9_^0==__rho_9_^post_38 && a11^0==a11^post_38 && a1818^0==a1818^post_38 && a2525^0==a2525^post_38 && a2828^0==a2828^post_38 && a3131^0==a3131^post_38 && a3232^0==a3232^post_38 && a3434^0==a3434^post_38 && a3737^0==a3737^post_38 && a3838^0==a3838^post_38 && a77^0==a77^post_38 && b22^0==b22^post_38 && b2626^0==b2626^post_38 && b2929^0==b2929^post_38 && b3333^0==b3333^post_38 && b3535^0==b3535^post_38 && i^0==i^post_38 && i___01313^0==i___01313^post_38 && i___01717^0==i___01717^post_38 && i___02020^0==i___02020^post_38 && i___02424^0==i___02424^post_38 && i___04040^0==i___04040^post_38 && i___04747^0==i___04747^post_38 && i___099^0==i___099^post_38 && ioA^0==ioA^post_38 && ioR^0==ioR^post_38 && k1^0==k1^post_38 && k2^0==k2^post_38 && k3^0==k3^post_38 && k4^0==k4^post_38 && keA^0==keA^post_38 && keR^0==keR^post_38 && ntStatus^0==ntStatus^post_38 && pIrb^0==pIrb^post_38 && phi_nSUC_ret^0==phi_nSUC_ret^post_38 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_38 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_38 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_38 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_38 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_38 ], cost: 1
     38: l20 -> l26 : AsyncAddressData^0'=AsyncAddressData^post_39, BusResetIrp^0'=BusResetIrp^post_39, CromData^0'=CromData^post_39, DeviceObject^0'=DeviceObject^post_39, Irp^0'=Irp^post_39, Irql^0'=Irql^post_39, IsochDetachData^0'=IsochDetachData^post_39, IsochResourceData^0'=IsochResourceData^post_39, ResourceIrp^0'=ResourceIrp^post_39, StackSize^0'=StackSize^post_39, __rho_10_^0'=__rho_10_^post_39, __rho_11_^0'=__rho_11_^post_39, __rho_12_^0'=__rho_12_^post_39, __rho_1_^0'=__rho_1_^post_39, __rho_2_^0'=__rho_2_^post_39, __rho_3_^0'=__rho_3_^post_39, __rho_4_^0'=__rho_4_^post_39, __rho_5_^0'=__rho_5_^post_39, __rho_666_^0'=__rho_666_^post_39, __rho_7_^0'=__rho_7_^post_39, __rho_8_^0'=__rho_8_^post_39, __rho_9_^0'=__rho_9_^post_39, a11^0'=a11^post_39, a1818^0'=a1818^post_39, a2525^0'=a2525^post_39, a2828^0'=a2828^post_39, a3131^0'=a3131^post_39, a3232^0'=a3232^post_39, a3434^0'=a3434^post_39, a3737^0'=a3737^post_39, a3838^0'=a3838^post_39, a4343^0'=a4343^post_39, a4545^0'=a4545^post_39, a77^0'=a77^post_39, b22^0'=b22^post_39, b2626^0'=b2626^post_39, b2929^0'=b2929^post_39, b3333^0'=b3333^post_39, b3535^0'=b3535^post_39, i^0'=i^post_39, i___01313^0'=i___01313^post_39, i___01717^0'=i___01717^post_39, i___02020^0'=i___02020^post_39, i___02424^0'=i___02424^post_39, i___04040^0'=i___04040^post_39, i___04747^0'=i___04747^post_39, i___099^0'=i___099^post_39, ioA^0'=ioA^post_39, ioR^0'=ioR^post_39, k1^0'=k1^post_39, k2^0'=k2^post_39, k3^0'=k3^post_39, k4^0'=k4^post_39, k5^0'=k5^post_39, keA^0'=keA^post_39, keR^0'=keR^post_39, ntStatus^0'=ntStatus^post_39, pIrb^0'=pIrb^post_39, phi_io_compl^0'=phi_io_compl^post_39, phi_nSUC_ret^0'=phi_nSUC_ret^post_39, prevCancel^0'=prevCancel^post_39, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_39, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_39, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_39, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_39, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_39, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_39, [ k5^0<=0 && i___04747^post_39==Irql^0 && keR^1_3_2==1 && keR^post_39==0 && AsyncAddressData^0==AsyncAddressData^post_39 && BusResetIrp^0==BusResetIrp^post_39 && CromData^0==CromData^post_39 && DeviceObject^0==DeviceObject^post_39 && Irp^0==Irp^post_39 && Irql^0==Irql^post_39 && IsochDetachData^0==IsochDetachData^post_39 && IsochResourceData^0==IsochResourceData^post_39 && ResourceIrp^0==ResourceIrp^post_39 && StackSize^0==StackSize^post_39 && __rho_10_^0==__rho_10_^post_39 && __rho_11_^0==__rho_11_^post_39 && __rho_12_^0==__rho_12_^post_39 && __rho_1_^0==__rho_1_^post_39 && __rho_2_^0==__rho_2_^post_39 && __rho_3_^0==__rho_3_^post_39 && __rho_4_^0==__rho_4_^post_39 && __rho_5_^0==__rho_5_^post_39 && __rho_666_^0==__rho_666_^post_39 && __rho_7_^0==__rho_7_^post_39 && __rho_8_^0==__rho_8_^post_39 && __rho_9_^0==__rho_9_^post_39 && a11^0==a11^post_39 && a1818^0==a1818^post_39 && a2525^0==a2525^post_39 && a2828^0==a2828^post_39 && a3131^0==a3131^post_39 && a3232^0==a3232^post_39 && a3434^0==a3434^post_39 && a3737^0==a3737^post_39 && a3838^0==a3838^post_39 && a4343^0==a4343^post_39 && a4545^0==a4545^post_39 && a77^0==a77^post_39 && b22^0==b22^post_39 && b2626^0==b2626^post_39 && b2929^0==b2929^post_39 && b3333^0==b3333^post_39 && b3535^0==b3535^post_39 && i^0==i^post_39 && i___01313^0==i___01313^post_39 && i___01717^0==i___01717^post_39 && i___02020^0==i___02020^post_39 && i___02424^0==i___02424^post_39 && i___04040^0==i___04040^post_39 && i___099^0==i___099^post_39 && ioA^0==ioA^post_39 && ioR^0==ioR^post_39 && k1^0==k1^post_39 && k2^0==k2^post_39 && k3^0==k3^post_39 && k4^0==k4^post_39 && k5^0==k5^post_39 && keA^0==keA^post_39 && ntStatus^0==ntStatus^post_39 && pIrb^0==pIrb^post_39 && phi_io_compl^0==phi_io_compl^post_39 && phi_nSUC_ret^0==phi_nSUC_ret^post_39 && prevCancel^0==prevCancel^post_39 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_39 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_39 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_39 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_39 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_39 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_39 ], cost: 1
     29: l21 -> l10 : AsyncAddressData^0'=AsyncAddressData^post_30, BusResetIrp^0'=BusResetIrp^post_30, CromData^0'=CromData^post_30, DeviceObject^0'=DeviceObject^post_30, Irp^0'=Irp^post_30, Irql^0'=Irql^post_30, IsochDetachData^0'=IsochDetachData^post_30, IsochResourceData^0'=IsochResourceData^post_30, ResourceIrp^0'=ResourceIrp^post_30, StackSize^0'=StackSize^post_30, __rho_10_^0'=__rho_10_^post_30, __rho_11_^0'=__rho_11_^post_30, __rho_12_^0'=__rho_12_^post_30, __rho_1_^0'=__rho_1_^post_30, __rho_2_^0'=__rho_2_^post_30, __rho_3_^0'=__rho_3_^post_30, __rho_4_^0'=__rho_4_^post_30, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_30, __rho_7_^0'=__rho_7_^post_30, __rho_8_^0'=__rho_8_^post_30, __rho_9_^0'=__rho_9_^post_30, a11^0'=a11^post_30, a1818^0'=a1818^post_30, a2525^0'=a2525^post_30, a2828^0'=a2828^post_30, a3131^0'=a3131^post_30, a3232^0'=a3232^post_30, a3434^0'=a3434^post_30, a3737^0'=a3737^post_30, a3838^0'=a3838^post_30, a4343^0'=a4343^post_30, a4545^0'=a4545^post_30, a77^0'=a77^post_30, b22^0'=b22^post_30, b2626^0'=b2626^post_30, b2929^0'=b2929^post_30, b3333^0'=b3333^post_30, b3535^0'=b3535^post_30, i^0'=i^post_30, i___01313^0'=i___01313^post_30, i___01717^0'=i___01717^post_30, i___02020^0'=i___02020^post_30, i___02424^0'=i___02424^post_30, i___04040^0'=i___04040^post_30, i___04747^0'=i___04747^post_30, i___099^0'=i___099^post_30, ioA^0'=ioA^post_30, ioR^0'=ioR^post_30, k1^0'=k1^post_30, k2^0'=k2^post_30, k3^0'=k3^post_30, k4^0'=k4^post_30, k5^0'=k5^post_30, keA^0'=keA^post_30, keR^0'=keR^post_30, ntStatus^0'=ntStatus^post_30, pIrb^0'=pIrb^post_30, phi_io_compl^0'=phi_io_compl^post_30, phi_nSUC_ret^0'=phi_nSUC_ret^post_30, prevCancel^0'=prevCancel^post_30, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_30, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_30, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_30, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_30, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_30, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_30, [ ret_IoSetDeviceInterfaceState44^post_30==0 && ntStatus^post_30==ret_IoSetDeviceInterfaceState44^post_30 && keA^1_4==1 && keA^post_30==0 && __rho_5_^post_30==__rho_5_^post_30 && k1^post_30==__rho_5_^post_30 && AsyncAddressData^0==AsyncAddressData^post_30 && BusResetIrp^0==BusResetIrp^post_30 && CromData^0==CromData^post_30 && DeviceObject^0==DeviceObject^post_30 && Irp^0==Irp^post_30 && Irql^0==Irql^post_30 && IsochDetachData^0==IsochDetachData^post_30 && IsochResourceData^0==IsochResourceData^post_30 && ResourceIrp^0==ResourceIrp^post_30 && StackSize^0==StackSize^post_30 && __rho_10_^0==__rho_10_^post_30 && __rho_11_^0==__rho_11_^post_30 && __rho_12_^0==__rho_12_^post_30 && __rho_1_^0==__rho_1_^post_30 && __rho_2_^0==__rho_2_^post_30 && __rho_3_^0==__rho_3_^post_30 && __rho_4_^0==__rho_4_^post_30 && __rho_666_^0==__rho_666_^post_30 && __rho_7_^0==__rho_7_^post_30 && __rho_8_^0==__rho_8_^post_30 && __rho_9_^0==__rho_9_^post_30 && a11^0==a11^post_30 && a1818^0==a1818^post_30 && a2525^0==a2525^post_30 && a2828^0==a2828^post_30 && a3131^0==a3131^post_30 && a3232^0==a3232^post_30 && a3434^0==a3434^post_30 && a3737^0==a3737^post_30 && a3838^0==a3838^post_30 && a4343^0==a4343^post_30 && a4545^0==a4545^post_30 && a77^0==a77^post_30 && b22^0==b22^post_30 && b2626^0==b2626^post_30 && b2929^0==b2929^post_30 && b3333^0==b3333^post_30 && b3535^0==b3535^post_30 && i^0==i^post_30 && i___01313^0==i___01313^post_30 && i___01717^0==i___01717^post_30 && i___02020^0==i___02020^post_30 && i___02424^0==i___02424^post_30 && i___04040^0==i___04040^post_30 && i___04747^0==i___04747^post_30 && i___099^0==i___099^post_30 && ioA^0==ioA^post_30 && ioR^0==ioR^post_30 && k2^0==k2^post_30 && k3^0==k3^post_30 && k4^0==k4^post_30 && k5^0==k5^post_30 && keR^0==keR^post_30 && pIrb^0==pIrb^post_30 && phi_io_compl^0==phi_io_compl^post_30 && phi_nSUC_ret^0==phi_nSUC_ret^post_30 && prevCancel^0==prevCancel^post_30 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_30 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_30 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_30 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_30 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_30 ], cost: 1
     31: l24 -> l25 : AsyncAddressData^0'=AsyncAddressData^post_32, BusResetIrp^0'=BusResetIrp^post_32, CromData^0'=CromData^post_32, DeviceObject^0'=DeviceObject^post_32, Irp^0'=Irp^post_32, Irql^0'=Irql^post_32, IsochDetachData^0'=IsochDetachData^post_32, IsochResourceData^0'=IsochResourceData^post_32, ResourceIrp^0'=ResourceIrp^post_32, StackSize^0'=StackSize^post_32, __rho_10_^0'=__rho_10_^post_32, __rho_11_^0'=__rho_11_^post_32, __rho_12_^0'=__rho_12_^post_32, __rho_1_^0'=__rho_1_^post_32, __rho_2_^0'=__rho_2_^post_32, __rho_3_^0'=__rho_3_^post_32, __rho_4_^0'=__rho_4_^post_32, __rho_5_^0'=__rho_5_^post_32, __rho_666_^0'=__rho_666_^post_32, __rho_7_^0'=__rho_7_^post_32, __rho_8_^0'=__rho_8_^post_32, __rho_9_^0'=__rho_9_^post_32, a11^0'=a11^post_32, a1818^0'=a1818^post_32, a2525^0'=a2525^post_32, a2828^0'=a2828^post_32, a3131^0'=a3131^post_32, a3232^0'=a3232^post_32, a3434^0'=a3434^post_32, a3737^0'=a3737^post_32, a3838^0'=a3838^post_32, a4343^0'=a4343^post_32, a4545^0'=a4545^post_32, a77^0'=a77^post_32, b22^0'=b22^post_32, b2626^0'=b2626^post_32, b2929^0'=b2929^post_32, b3333^0'=b3333^post_32, b3535^0'=b3535^post_32, i^0'=i^post_32, i___01313^0'=i___01313^post_32, i___01717^0'=i___01717^post_32, i___02020^0'=i___02020^post_32, i___02424^0'=i___02424^post_32, i___04040^0'=i___04040^post_32, i___04747^0'=i___04747^post_32, i___099^0'=i___099^post_32, ioA^0'=ioA^post_32, ioR^0'=ioR^post_32, k1^0'=k1^post_32, k2^0'=k2^post_32, k3^0'=k3^post_32, k4^0'=k4^post_32, k5^0'=k5^post_32, keA^0'=keA^post_32, keR^0'=keR^post_32, ntStatus^0'=ntStatus^post_32, pIrb^0'=pIrb^post_32, phi_io_compl^0'=phi_io_compl^post_32, phi_nSUC_ret^0'=phi_nSUC_ret^post_32, prevCancel^0'=prevCancel^post_32, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_32, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_32, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_32, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_32, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_32, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_32, [ phi_nSUC_ret^post_32==1 && AsyncAddressData^0==AsyncAddressData^post_32 && BusResetIrp^0==BusResetIrp^post_32 && CromData^0==CromData^post_32 && DeviceObject^0==DeviceObject^post_32 && Irp^0==Irp^post_32 && Irql^0==Irql^post_32 && IsochDetachData^0==IsochDetachData^post_32 && IsochResourceData^0==IsochResourceData^post_32 && ResourceIrp^0==ResourceIrp^post_32 && StackSize^0==StackSize^post_32 && __rho_10_^0==__rho_10_^post_32 && __rho_11_^0==__rho_11_^post_32 && __rho_12_^0==__rho_12_^post_32 && __rho_1_^0==__rho_1_^post_32 && __rho_2_^0==__rho_2_^post_32 && __rho_3_^0==__rho_3_^post_32 && __rho_4_^0==__rho_4_^post_32 && __rho_5_^0==__rho_5_^post_32 && __rho_666_^0==__rho_666_^post_32 && __rho_7_^0==__rho_7_^post_32 && __rho_8_^0==__rho_8_^post_32 && __rho_9_^0==__rho_9_^post_32 && a11^0==a11^post_32 && a1818^0==a1818^post_32 && a2525^0==a2525^post_32 && a2828^0==a2828^post_32 && a3131^0==a3131^post_32 && a3232^0==a3232^post_32 && a3434^0==a3434^post_32 && a3737^0==a3737^post_32 && a3838^0==a3838^post_32 && a4343^0==a4343^post_32 && a4545^0==a4545^post_32 && a77^0==a77^post_32 && b22^0==b22^post_32 && b2626^0==b2626^post_32 && b2929^0==b2929^post_32 && b3333^0==b3333^post_32 && b3535^0==b3535^post_32 && i^0==i^post_32 && i___01313^0==i___01313^post_32 && i___01717^0==i___01717^post_32 && i___02020^0==i___02020^post_32 && i___02424^0==i___02424^post_32 && i___04040^0==i___04040^post_32 && i___04747^0==i___04747^post_32 && i___099^0==i___099^post_32 && ioA^0==ioA^post_32 && ioR^0==ioR^post_32 && k1^0==k1^post_32 && k2^0==k2^post_32 && k3^0==k3^post_32 && k4^0==k4^post_32 && k5^0==k5^post_32 && keA^0==keA^post_32 && keR^0==keR^post_32 && ntStatus^0==ntStatus^post_32 && pIrb^0==pIrb^post_32 && phi_io_compl^0==phi_io_compl^post_32 && prevCancel^0==prevCancel^post_32 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_32 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_32 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_32 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_32 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_32 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_32 ], cost: 1
     35: l25 -> l27 : AsyncAddressData^0'=AsyncAddressData^post_36, BusResetIrp^0'=BusResetIrp^post_36, CromData^0'=CromData^post_36, DeviceObject^0'=DeviceObject^post_36, Irp^0'=Irp^post_36, Irql^0'=Irql^post_36, IsochDetachData^0'=IsochDetachData^post_36, IsochResourceData^0'=IsochResourceData^post_36, ResourceIrp^0'=ResourceIrp^post_36, StackSize^0'=StackSize^post_36, __rho_10_^0'=__rho_10_^post_36, __rho_11_^0'=__rho_11_^post_36, __rho_12_^0'=__rho_12_^post_36, __rho_1_^0'=__rho_1_^post_36, __rho_2_^0'=__rho_2_^post_36, __rho_3_^0'=__rho_3_^post_36, __rho_4_^0'=__rho_4_^post_36, __rho_5_^0'=__rho_5_^post_36, __rho_666_^0'=__rho_666_^post_36, __rho_7_^0'=__rho_7_^post_36, __rho_8_^0'=__rho_8_^post_36, __rho_9_^0'=__rho_9_^post_36, a11^0'=a11^post_36, a1818^0'=a1818^post_36, a2525^0'=a2525^post_36, a2828^0'=a2828^post_36, a3131^0'=a3131^post_36, a3232^0'=a3232^post_36, a3434^0'=a3434^post_36, a3737^0'=a3737^post_36, a3838^0'=a3838^post_36, a4343^0'=a4343^post_36, a4545^0'=a4545^post_36, a77^0'=a77^post_36, b22^0'=b22^post_36, b2626^0'=b2626^post_36, b2929^0'=b2929^post_36, b3333^0'=b3333^post_36, b3535^0'=b3535^post_36, i^0'=i^post_36, i___01313^0'=i___01313^post_36, i___01717^0'=i___01717^post_36, i___02020^0'=i___02020^post_36, i___02424^0'=i___02424^post_36, i___04040^0'=i___04040^post_36, i___04747^0'=i___04747^post_36, i___099^0'=i___099^post_36, ioA^0'=ioA^post_36, ioR^0'=ioR^post_36, k1^0'=k1^post_36, k2^0'=k2^post_36, k3^0'=k3^post_36, k4^0'=k4^post_36, k5^0'=k5^post_36, keA^0'=keA^post_36, keR^0'=keR^post_36, ntStatus^0'=ntStatus^post_36, pIrb^0'=pIrb^post_36, phi_io_compl^0'=phi_io_compl^post_36, phi_nSUC_ret^0'=phi_nSUC_ret^post_36, prevCancel^0'=prevCancel^post_36, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_36, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_36, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_36, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_36, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_36, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_36, [ AsyncAddressData^0==AsyncAddressData^post_36 && BusResetIrp^0==BusResetIrp^post_36 && CromData^0==CromData^post_36 && DeviceObject^0==DeviceObject^post_36 && Irp^0==Irp^post_36 && Irql^0==Irql^post_36 && IsochDetachData^0==IsochDetachData^post_36 && IsochResourceData^0==IsochResourceData^post_36 && ResourceIrp^0==ResourceIrp^post_36 && StackSize^0==StackSize^post_36 && __rho_10_^0==__rho_10_^post_36 && __rho_11_^0==__rho_11_^post_36 && __rho_12_^0==__rho_12_^post_36 && __rho_1_^0==__rho_1_^post_36 && __rho_2_^0==__rho_2_^post_36 && __rho_3_^0==__rho_3_^post_36 && __rho_4_^0==__rho_4_^post_36 && __rho_5_^0==__rho_5_^post_36 && __rho_666_^0==__rho_666_^post_36 && __rho_7_^0==__rho_7_^post_36 && __rho_8_^0==__rho_8_^post_36 && __rho_9_^0==__rho_9_^post_36 && a11^0==a11^post_36 && a1818^0==a1818^post_36 && a2525^0==a2525^post_36 && a2828^0==a2828^post_36 && a3131^0==a3131^post_36 && a3232^0==a3232^post_36 && a3434^0==a3434^post_36 && a3737^0==a3737^post_36 && a3838^0==a3838^post_36 && a4343^0==a4343^post_36 && a4545^0==a4545^post_36 && a77^0==a77^post_36 && b22^0==b22^post_36 && b2626^0==b2626^post_36 && b2929^0==b2929^post_36 && b3333^0==b3333^post_36 && b3535^0==b3535^post_36 && i^0==i^post_36 && i___01313^0==i___01313^post_36 && i___01717^0==i___01717^post_36 && i___02020^0==i___02020^post_36 && i___02424^0==i___02424^post_36 && i___04040^0==i___04040^post_36 && i___04747^0==i___04747^post_36 && i___099^0==i___099^post_36 && ioA^0==ioA^post_36 && ioR^0==ioR^post_36 && k1^0==k1^post_36 && k2^0==k2^post_36 && k3^0==k3^post_36 && k4^0==k4^post_36 && k5^0==k5^post_36 && keA^0==keA^post_36 && keR^0==keR^post_36 && ntStatus^0==ntStatus^post_36 && pIrb^0==pIrb^post_36 && phi_io_compl^0==phi_io_compl^post_36 && phi_nSUC_ret^0==phi_nSUC_ret^post_36 && prevCancel^0==prevCancel^post_36 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_36 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_36 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_36 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_36 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_36 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_36 ], cost: 1
     32: l26 -> l25 : AsyncAddressData^0'=AsyncAddressData^post_33, BusResetIrp^0'=BusResetIrp^post_33, CromData^0'=CromData^post_33, DeviceObject^0'=DeviceObject^post_33, Irp^0'=Irp^post_33, Irql^0'=Irql^post_33, IsochDetachData^0'=IsochDetachData^post_33, IsochResourceData^0'=IsochResourceData^post_33, ResourceIrp^0'=ResourceIrp^post_33, StackSize^0'=StackSize^post_33, __rho_10_^0'=__rho_10_^post_33, __rho_11_^0'=__rho_11_^post_33, __rho_12_^0'=__rho_12_^post_33, __rho_1_^0'=__rho_1_^post_33, __rho_2_^0'=__rho_2_^post_33, __rho_3_^0'=__rho_3_^post_33, __rho_4_^0'=__rho_4_^post_33, __rho_5_^0'=__rho_5_^post_33, __rho_666_^0'=__rho_666_^post_33, __rho_7_^0'=__rho_7_^post_33, __rho_8_^0'=__rho_8_^post_33, __rho_9_^0'=__rho_9_^post_33, a11^0'=a11^post_33, a1818^0'=a1818^post_33, a2525^0'=a2525^post_33, a2828^0'=a2828^post_33, a3131^0'=a3131^post_33, a3232^0'=a3232^post_33, a3434^0'=a3434^post_33, a3737^0'=a3737^post_33, a3838^0'=a3838^post_33, a4343^0'=a4343^post_33, a4545^0'=a4545^post_33, a77^0'=a77^post_33, b22^0'=b22^post_33, b2626^0'=b2626^post_33, b2929^0'=b2929^post_33, b3333^0'=b3333^post_33, b3535^0'=b3535^post_33, i^0'=i^post_33, i___01313^0'=i___01313^post_33, i___01717^0'=i___01717^post_33, i___02020^0'=i___02020^post_33, i___02424^0'=i___02424^post_33, i___04040^0'=i___04040^post_33, i___04747^0'=i___04747^post_33, i___099^0'=i___099^post_33, ioA^0'=ioA^post_33, ioR^0'=ioR^post_33, k1^0'=k1^post_33, k2^0'=k2^post_33, k3^0'=k3^post_33, k4^0'=k4^post_33, k5^0'=k5^post_33, keA^0'=keA^post_33, keR^0'=keR^post_33, ntStatus^0'=ntStatus^post_33, pIrb^0'=pIrb^post_33, phi_io_compl^0'=phi_io_compl^post_33, phi_nSUC_ret^0'=phi_nSUC_ret^post_33, prevCancel^0'=prevCancel^post_33, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_33, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_33, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_33, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_33, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_33, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_33, [ ntStatus^0<=2 && 2<=ntStatus^0 && AsyncAddressData^0==AsyncAddressData^post_33 && BusResetIrp^0==BusResetIrp^post_33 && CromData^0==CromData^post_33 && DeviceObject^0==DeviceObject^post_33 && Irp^0==Irp^post_33 && Irql^0==Irql^post_33 && IsochDetachData^0==IsochDetachData^post_33 && IsochResourceData^0==IsochResourceData^post_33 && ResourceIrp^0==ResourceIrp^post_33 && StackSize^0==StackSize^post_33 && __rho_10_^0==__rho_10_^post_33 && __rho_11_^0==__rho_11_^post_33 && __rho_12_^0==__rho_12_^post_33 && __rho_1_^0==__rho_1_^post_33 && __rho_2_^0==__rho_2_^post_33 && __rho_3_^0==__rho_3_^post_33 && __rho_4_^0==__rho_4_^post_33 && __rho_5_^0==__rho_5_^post_33 && __rho_666_^0==__rho_666_^post_33 && __rho_7_^0==__rho_7_^post_33 && __rho_8_^0==__rho_8_^post_33 && __rho_9_^0==__rho_9_^post_33 && a11^0==a11^post_33 && a1818^0==a1818^post_33 && a2525^0==a2525^post_33 && a2828^0==a2828^post_33 && a3131^0==a3131^post_33 && a3232^0==a3232^post_33 && a3434^0==a3434^post_33 && a3737^0==a3737^post_33 && a3838^0==a3838^post_33 && a4343^0==a4343^post_33 && a4545^0==a4545^post_33 && a77^0==a77^post_33 && b22^0==b22^post_33 && b2626^0==b2626^post_33 && b2929^0==b2929^post_33 && b3333^0==b3333^post_33 && b3535^0==b3535^post_33 && i^0==i^post_33 && i___01313^0==i___01313^post_33 && i___01717^0==i___01717^post_33 && i___02020^0==i___02020^post_33 && i___02424^0==i___02424^post_33 && i___04040^0==i___04040^post_33 && i___04747^0==i___04747^post_33 && i___099^0==i___099^post_33 && ioA^0==ioA^post_33 && ioR^0==ioR^post_33 && k1^0==k1^post_33 && k2^0==k2^post_33 && k3^0==k3^post_33 && k4^0==k4^post_33 && k5^0==k5^post_33 && keA^0==keA^post_33 && keR^0==keR^post_33 && ntStatus^0==ntStatus^post_33 && pIrb^0==pIrb^post_33 && phi_io_compl^0==phi_io_compl^post_33 && phi_nSUC_ret^0==phi_nSUC_ret^post_33 && prevCancel^0==prevCancel^post_33 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_33 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_33 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_33 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_33 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_33 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_33 ], cost: 1
     33: l26 -> l24 : AsyncAddressData^0'=AsyncAddressData^post_34, BusResetIrp^0'=BusResetIrp^post_34, CromData^0'=CromData^post_34, DeviceObject^0'=DeviceObject^post_34, Irp^0'=Irp^post_34, Irql^0'=Irql^post_34, IsochDetachData^0'=IsochDetachData^post_34, IsochResourceData^0'=IsochResourceData^post_34, ResourceIrp^0'=ResourceIrp^post_34, StackSize^0'=StackSize^post_34, __rho_10_^0'=__rho_10_^post_34, __rho_11_^0'=__rho_11_^post_34, __rho_12_^0'=__rho_12_^post_34, __rho_1_^0'=__rho_1_^post_34, __rho_2_^0'=__rho_2_^post_34, __rho_3_^0'=__rho_3_^post_34, __rho_4_^0'=__rho_4_^post_34, __rho_5_^0'=__rho_5_^post_34, __rho_666_^0'=__rho_666_^post_34, __rho_7_^0'=__rho_7_^post_34, __rho_8_^0'=__rho_8_^post_34, __rho_9_^0'=__rho_9_^post_34, a11^0'=a11^post_34, a1818^0'=a1818^post_34, a2525^0'=a2525^post_34, a2828^0'=a2828^post_34, a3131^0'=a3131^post_34, a3232^0'=a3232^post_34, a3434^0'=a3434^post_34, a3737^0'=a3737^post_34, a3838^0'=a3838^post_34, a4343^0'=a4343^post_34, a4545^0'=a4545^post_34, a77^0'=a77^post_34, b22^0'=b22^post_34, b2626^0'=b2626^post_34, b2929^0'=b2929^post_34, b3333^0'=b3333^post_34, b3535^0'=b3535^post_34, i^0'=i^post_34, i___01313^0'=i___01313^post_34, i___01717^0'=i___01717^post_34, i___02020^0'=i___02020^post_34, i___02424^0'=i___02424^post_34, i___04040^0'=i___04040^post_34, i___04747^0'=i___04747^post_34, i___099^0'=i___099^post_34, ioA^0'=ioA^post_34, ioR^0'=ioR^post_34, k1^0'=k1^post_34, k2^0'=k2^post_34, k3^0'=k3^post_34, k4^0'=k4^post_34, k5^0'=k5^post_34, keA^0'=keA^post_34, keR^0'=keR^post_34, ntStatus^0'=ntStatus^post_34, pIrb^0'=pIrb^post_34, phi_io_compl^0'=phi_io_compl^post_34, phi_nSUC_ret^0'=phi_nSUC_ret^post_34, prevCancel^0'=prevCancel^post_34, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_34, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_34, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_34, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_34, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_34, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_34, [ 3<=ntStatus^0 && AsyncAddressData^0==AsyncAddressData^post_34 && BusResetIrp^0==BusResetIrp^post_34 && CromData^0==CromData^post_34 && DeviceObject^0==DeviceObject^post_34 && Irp^0==Irp^post_34 && Irql^0==Irql^post_34 && IsochDetachData^0==IsochDetachData^post_34 && IsochResourceData^0==IsochResourceData^post_34 && ResourceIrp^0==ResourceIrp^post_34 && StackSize^0==StackSize^post_34 && __rho_10_^0==__rho_10_^post_34 && __rho_11_^0==__rho_11_^post_34 && __rho_12_^0==__rho_12_^post_34 && __rho_1_^0==__rho_1_^post_34 && __rho_2_^0==__rho_2_^post_34 && __rho_3_^0==__rho_3_^post_34 && __rho_4_^0==__rho_4_^post_34 && __rho_5_^0==__rho_5_^post_34 && __rho_666_^0==__rho_666_^post_34 && __rho_7_^0==__rho_7_^post_34 && __rho_8_^0==__rho_8_^post_34 && __rho_9_^0==__rho_9_^post_34 && a11^0==a11^post_34 && a1818^0==a1818^post_34 && a2525^0==a2525^post_34 && a2828^0==a2828^post_34 && a3131^0==a3131^post_34 && a3232^0==a3232^post_34 && a3434^0==a3434^post_34 && a3737^0==a3737^post_34 && a3838^0==a3838^post_34 && a4343^0==a4343^post_34 && a4545^0==a4545^post_34 && a77^0==a77^post_34 && b22^0==b22^post_34 && b2626^0==b2626^post_34 && b2929^0==b2929^post_34 && b3333^0==b3333^post_34 && b3535^0==b3535^post_34 && i^0==i^post_34 && i___01313^0==i___01313^post_34 && i___01717^0==i___01717^post_34 && i___02020^0==i___02020^post_34 && i___02424^0==i___02424^post_34 && i___04040^0==i___04040^post_34 && i___04747^0==i___04747^post_34 && i___099^0==i___099^post_34 && ioA^0==ioA^post_34 && ioR^0==ioR^post_34 && k1^0==k1^post_34 && k2^0==k2^post_34 && k3^0==k3^post_34 && k4^0==k4^post_34 && k5^0==k5^post_34 && keA^0==keA^post_34 && keR^0==keR^post_34 && ntStatus^0==ntStatus^post_34 && pIrb^0==pIrb^post_34 && phi_io_compl^0==phi_io_compl^post_34 && phi_nSUC_ret^0==phi_nSUC_ret^post_34 && prevCancel^0==prevCancel^post_34 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_34 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_34 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_34 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_34 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_34 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_34 ], cost: 1
     34: l26 -> l24 : AsyncAddressData^0'=AsyncAddressData^post_35, BusResetIrp^0'=BusResetIrp^post_35, CromData^0'=CromData^post_35, DeviceObject^0'=DeviceObject^post_35, Irp^0'=Irp^post_35, Irql^0'=Irql^post_35, IsochDetachData^0'=IsochDetachData^post_35, IsochResourceData^0'=IsochResourceData^post_35, ResourceIrp^0'=ResourceIrp^post_35, StackSize^0'=StackSize^post_35, __rho_10_^0'=__rho_10_^post_35, __rho_11_^0'=__rho_11_^post_35, __rho_12_^0'=__rho_12_^post_35, __rho_1_^0'=__rho_1_^post_35, __rho_2_^0'=__rho_2_^post_35, __rho_3_^0'=__rho_3_^post_35, __rho_4_^0'=__rho_4_^post_35, __rho_5_^0'=__rho_5_^post_35, __rho_666_^0'=__rho_666_^post_35, __rho_7_^0'=__rho_7_^post_35, __rho_8_^0'=__rho_8_^post_35, __rho_9_^0'=__rho_9_^post_35, a11^0'=a11^post_35, a1818^0'=a1818^post_35, a2525^0'=a2525^post_35, a2828^0'=a2828^post_35, a3131^0'=a3131^post_35, a3232^0'=a3232^post_35, a3434^0'=a3434^post_35, a3737^0'=a3737^post_35, a3838^0'=a3838^post_35, a4343^0'=a4343^post_35, a4545^0'=a4545^post_35, a77^0'=a77^post_35, b22^0'=b22^post_35, b2626^0'=b2626^post_35, b2929^0'=b2929^post_35, b3333^0'=b3333^post_35, b3535^0'=b3535^post_35, i^0'=i^post_35, i___01313^0'=i___01313^post_35, i___01717^0'=i___01717^post_35, i___02020^0'=i___02020^post_35, i___02424^0'=i___02424^post_35, i___04040^0'=i___04040^post_35, i___04747^0'=i___04747^post_35, i___099^0'=i___099^post_35, ioA^0'=ioA^post_35, ioR^0'=ioR^post_35, k1^0'=k1^post_35, k2^0'=k2^post_35, k3^0'=k3^post_35, k4^0'=k4^post_35, k5^0'=k5^post_35, keA^0'=keA^post_35, keR^0'=keR^post_35, ntStatus^0'=ntStatus^post_35, pIrb^0'=pIrb^post_35, phi_io_compl^0'=phi_io_compl^post_35, phi_nSUC_ret^0'=phi_nSUC_ret^post_35, prevCancel^0'=prevCancel^post_35, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_35, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_35, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_35, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_35, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_35, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_35, [ 1+ntStatus^0<=2 && AsyncAddressData^0==AsyncAddressData^post_35 && BusResetIrp^0==BusResetIrp^post_35 && CromData^0==CromData^post_35 && DeviceObject^0==DeviceObject^post_35 && Irp^0==Irp^post_35 && Irql^0==Irql^post_35 && IsochDetachData^0==IsochDetachData^post_35 && IsochResourceData^0==IsochResourceData^post_35 && ResourceIrp^0==ResourceIrp^post_35 && StackSize^0==StackSize^post_35 && __rho_10_^0==__rho_10_^post_35 && __rho_11_^0==__rho_11_^post_35 && __rho_12_^0==__rho_12_^post_35 && __rho_1_^0==__rho_1_^post_35 && __rho_2_^0==__rho_2_^post_35 && __rho_3_^0==__rho_3_^post_35 && __rho_4_^0==__rho_4_^post_35 && __rho_5_^0==__rho_5_^post_35 && __rho_666_^0==__rho_666_^post_35 && __rho_7_^0==__rho_7_^post_35 && __rho_8_^0==__rho_8_^post_35 && __rho_9_^0==__rho_9_^post_35 && a11^0==a11^post_35 && a1818^0==a1818^post_35 && a2525^0==a2525^post_35 && a2828^0==a2828^post_35 && a3131^0==a3131^post_35 && a3232^0==a3232^post_35 && a3434^0==a3434^post_35 && a3737^0==a3737^post_35 && a3838^0==a3838^post_35 && a4343^0==a4343^post_35 && a4545^0==a4545^post_35 && a77^0==a77^post_35 && b22^0==b22^post_35 && b2626^0==b2626^post_35 && b2929^0==b2929^post_35 && b3333^0==b3333^post_35 && b3535^0==b3535^post_35 && i^0==i^post_35 && i___01313^0==i___01313^post_35 && i___01717^0==i___01717^post_35 && i___02020^0==i___02020^post_35 && i___02424^0==i___02424^post_35 && i___04040^0==i___04040^post_35 && i___04747^0==i___04747^post_35 && i___099^0==i___099^post_35 && ioA^0==ioA^post_35 && ioR^0==ioR^post_35 && k1^0==k1^post_35 && k2^0==k2^post_35 && k3^0==k3^post_35 && k4^0==k4^post_35 && k5^0==k5^post_35 && keA^0==keA^post_35 && keR^0==keR^post_35 && ntStatus^0==ntStatus^post_35 && pIrb^0==pIrb^post_35 && phi_io_compl^0==phi_io_compl^post_35 && phi_nSUC_ret^0==phi_nSUC_ret^post_35 && prevCancel^0==prevCancel^post_35 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_35 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_35 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_35 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_35 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_35 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_35 ], cost: 1
     36: l27 -> l25 : AsyncAddressData^0'=AsyncAddressData^post_37, BusResetIrp^0'=BusResetIrp^post_37, CromData^0'=CromData^post_37, DeviceObject^0'=DeviceObject^post_37, Irp^0'=Irp^post_37, Irql^0'=Irql^post_37, IsochDetachData^0'=IsochDetachData^post_37, IsochResourceData^0'=IsochResourceData^post_37, ResourceIrp^0'=ResourceIrp^post_37, StackSize^0'=StackSize^post_37, __rho_10_^0'=__rho_10_^post_37, __rho_11_^0'=__rho_11_^post_37, __rho_12_^0'=__rho_12_^post_37, __rho_1_^0'=__rho_1_^post_37, __rho_2_^0'=__rho_2_^post_37, __rho_3_^0'=__rho_3_^post_37, __rho_4_^0'=__rho_4_^post_37, __rho_5_^0'=__rho_5_^post_37, __rho_666_^0'=__rho_666_^post_37, __rho_7_^0'=__rho_7_^post_37, __rho_8_^0'=__rho_8_^post_37, __rho_9_^0'=__rho_9_^post_37, a11^0'=a11^post_37, a1818^0'=a1818^post_37, a2525^0'=a2525^post_37, a2828^0'=a2828^post_37, a3131^0'=a3131^post_37, a3232^0'=a3232^post_37, a3434^0'=a3434^post_37, a3737^0'=a3737^post_37, a3838^0'=a3838^post_37, a4343^0'=a4343^post_37, a4545^0'=a4545^post_37, a77^0'=a77^post_37, b22^0'=b22^post_37, b2626^0'=b2626^post_37, b2929^0'=b2929^post_37, b3333^0'=b3333^post_37, b3535^0'=b3535^post_37, i^0'=i^post_37, i___01313^0'=i___01313^post_37, i___01717^0'=i___01717^post_37, i___02020^0'=i___02020^post_37, i___02424^0'=i___02424^post_37, i___04040^0'=i___04040^post_37, i___04747^0'=i___04747^post_37, i___099^0'=i___099^post_37, ioA^0'=ioA^post_37, ioR^0'=ioR^post_37, k1^0'=k1^post_37, k2^0'=k2^post_37, k3^0'=k3^post_37, k4^0'=k4^post_37, k5^0'=k5^post_37, keA^0'=keA^post_37, keR^0'=keR^post_37, ntStatus^0'=ntStatus^post_37, pIrb^0'=pIrb^post_37, phi_io_compl^0'=phi_io_compl^post_37, phi_nSUC_ret^0'=phi_nSUC_ret^post_37, prevCancel^0'=prevCancel^post_37, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_37, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_37, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_37, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_37, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_37, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_37, [ AsyncAddressData^0==AsyncAddressData^post_37 && BusResetIrp^0==BusResetIrp^post_37 && CromData^0==CromData^post_37 && DeviceObject^0==DeviceObject^post_37 && Irp^0==Irp^post_37 && Irql^0==Irql^post_37 && IsochDetachData^0==IsochDetachData^post_37 && IsochResourceData^0==IsochResourceData^post_37 && ResourceIrp^0==ResourceIrp^post_37 && StackSize^0==StackSize^post_37 && __rho_10_^0==__rho_10_^post_37 && __rho_11_^0==__rho_11_^post_37 && __rho_12_^0==__rho_12_^post_37 && __rho_1_^0==__rho_1_^post_37 && __rho_2_^0==__rho_2_^post_37 && __rho_3_^0==__rho_3_^post_37 && __rho_4_^0==__rho_4_^post_37 && __rho_5_^0==__rho_5_^post_37 && __rho_666_^0==__rho_666_^post_37 && __rho_7_^0==__rho_7_^post_37 && __rho_8_^0==__rho_8_^post_37 && __rho_9_^0==__rho_9_^post_37 && a11^0==a11^post_37 && a1818^0==a1818^post_37 && a2525^0==a2525^post_37 && a2828^0==a2828^post_37 && a3131^0==a3131^post_37 && a3232^0==a3232^post_37 && a3434^0==a3434^post_37 && a3737^0==a3737^post_37 && a3838^0==a3838^post_37 && a4343^0==a4343^post_37 && a4545^0==a4545^post_37 && a77^0==a77^post_37 && b22^0==b22^post_37 && b2626^0==b2626^post_37 && b2929^0==b2929^post_37 && b3333^0==b3333^post_37 && b3535^0==b3535^post_37 && i^0==i^post_37 && i___01313^0==i___01313^post_37 && i___01717^0==i___01717^post_37 && i___02020^0==i___02020^post_37 && i___02424^0==i___02424^post_37 && i___04040^0==i___04040^post_37 && i___04747^0==i___04747^post_37 && i___099^0==i___099^post_37 && ioA^0==ioA^post_37 && ioR^0==ioR^post_37 && k1^0==k1^post_37 && k2^0==k2^post_37 && k3^0==k3^post_37 && k4^0==k4^post_37 && k5^0==k5^post_37 && keA^0==keA^post_37 && keR^0==keR^post_37 && ntStatus^0==ntStatus^post_37 && pIrb^0==pIrb^post_37 && phi_io_compl^0==phi_io_compl^post_37 && phi_nSUC_ret^0==phi_nSUC_ret^post_37 && prevCancel^0==prevCancel^post_37 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_37 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_37 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_37 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_37 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_37 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_37 ], cost: 1
     39: l28 -> l21 : AsyncAddressData^0'=AsyncAddressData^post_40, BusResetIrp^0'=BusResetIrp^post_40, CromData^0'=CromData^post_40, DeviceObject^0'=DeviceObject^post_40, Irp^0'=Irp^post_40, Irql^0'=Irql^post_40, IsochDetachData^0'=IsochDetachData^post_40, IsochResourceData^0'=IsochResourceData^post_40, ResourceIrp^0'=ResourceIrp^post_40, StackSize^0'=StackSize^post_40, __rho_10_^0'=__rho_10_^post_40, __rho_11_^0'=__rho_11_^post_40, __rho_12_^0'=__rho_12_^post_40, __rho_1_^0'=__rho_1_^post_40, __rho_2_^0'=__rho_2_^post_40, __rho_3_^0'=__rho_3_^post_40, __rho_4_^0'=__rho_4_^post_40, __rho_5_^0'=__rho_5_^post_40, __rho_666_^0'=__rho_666_^post_40, __rho_7_^0'=__rho_7_^post_40, __rho_8_^0'=__rho_8_^post_40, __rho_9_^0'=__rho_9_^post_40, a11^0'=a11^post_40, a1818^0'=a1818^post_40, a2525^0'=a2525^post_40, a2828^0'=a2828^post_40, a3131^0'=a3131^post_40, a3232^0'=a3232^post_40, a3434^0'=a3434^post_40, a3737^0'=a3737^post_40, a3838^0'=a3838^post_40, a4343^0'=a4343^post_40, a4545^0'=a4545^post_40, a77^0'=a77^post_40, b22^0'=b22^post_40, b2626^0'=b2626^post_40, b2929^0'=b2929^post_40, b3333^0'=b3333^post_40, b3535^0'=b3535^post_40, i^0'=i^post_40, i___01313^0'=i___01313^post_40, i___01717^0'=i___01717^post_40, i___02020^0'=i___02020^post_40, i___02424^0'=i___02424^post_40, i___04040^0'=i___04040^post_40, i___04747^0'=i___04747^post_40, i___099^0'=i___099^post_40, ioA^0'=ioA^post_40, ioR^0'=ioR^post_40, k1^0'=k1^post_40, k2^0'=k2^post_40, k3^0'=k3^post_40, k4^0'=k4^post_40, k5^0'=k5^post_40, keA^0'=keA^post_40, keR^0'=keR^post_40, ntStatus^0'=ntStatus^post_40, pIrb^0'=pIrb^post_40, phi_io_compl^0'=phi_io_compl^post_40, phi_nSUC_ret^0'=phi_nSUC_ret^post_40, prevCancel^0'=prevCancel^post_40, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_40, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_40, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_40, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_40, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_40, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_40, [ __rho_1_^0<=0 && AsyncAddressData^0==AsyncAddressData^post_40 && BusResetIrp^0==BusResetIrp^post_40 && CromData^0==CromData^post_40 && DeviceObject^0==DeviceObject^post_40 && Irp^0==Irp^post_40 && Irql^0==Irql^post_40 && IsochDetachData^0==IsochDetachData^post_40 && IsochResourceData^0==IsochResourceData^post_40 && ResourceIrp^0==ResourceIrp^post_40 && StackSize^0==StackSize^post_40 && __rho_10_^0==__rho_10_^post_40 && __rho_11_^0==__rho_11_^post_40 && __rho_12_^0==__rho_12_^post_40 && __rho_1_^0==__rho_1_^post_40 && __rho_2_^0==__rho_2_^post_40 && __rho_3_^0==__rho_3_^post_40 && __rho_4_^0==__rho_4_^post_40 && __rho_5_^0==__rho_5_^post_40 && __rho_666_^0==__rho_666_^post_40 && __rho_7_^0==__rho_7_^post_40 && __rho_8_^0==__rho_8_^post_40 && __rho_9_^0==__rho_9_^post_40 && a11^0==a11^post_40 && a1818^0==a1818^post_40 && a2525^0==a2525^post_40 && a2828^0==a2828^post_40 && a3131^0==a3131^post_40 && a3232^0==a3232^post_40 && a3434^0==a3434^post_40 && a3737^0==a3737^post_40 && a3838^0==a3838^post_40 && a4343^0==a4343^post_40 && a4545^0==a4545^post_40 && a77^0==a77^post_40 && b22^0==b22^post_40 && b2626^0==b2626^post_40 && b2929^0==b2929^post_40 && b3333^0==b3333^post_40 && b3535^0==b3535^post_40 && i^0==i^post_40 && i___01313^0==i___01313^post_40 && i___01717^0==i___01717^post_40 && i___02020^0==i___02020^post_40 && i___02424^0==i___02424^post_40 && i___04040^0==i___04040^post_40 && i___04747^0==i___04747^post_40 && i___099^0==i___099^post_40 && ioA^0==ioA^post_40 && ioR^0==ioR^post_40 && k1^0==k1^post_40 && k2^0==k2^post_40 && k3^0==k3^post_40 && k4^0==k4^post_40 && k5^0==k5^post_40 && keA^0==keA^post_40 && keR^0==keR^post_40 && ntStatus^0==ntStatus^post_40 && pIrb^0==pIrb^post_40 && phi_io_compl^0==phi_io_compl^post_40 && phi_nSUC_ret^0==phi_nSUC_ret^post_40 && prevCancel^0==prevCancel^post_40 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_40 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_40 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_40 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_40 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_40 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_40 ], cost: 1
     40: l28 -> l21 : AsyncAddressData^0'=AsyncAddressData^post_41, BusResetIrp^0'=BusResetIrp^post_41, CromData^0'=CromData^post_41, DeviceObject^0'=DeviceObject^post_41, Irp^0'=Irp^post_41, Irql^0'=Irql^post_41, IsochDetachData^0'=IsochDetachData^post_41, IsochResourceData^0'=IsochResourceData^post_41, ResourceIrp^0'=ResourceIrp^post_41, StackSize^0'=StackSize^post_41, __rho_10_^0'=__rho_10_^post_41, __rho_11_^0'=__rho_11_^post_41, __rho_12_^0'=__rho_12_^post_41, __rho_1_^0'=__rho_1_^post_41, __rho_2_^0'=__rho_2_^post_41, __rho_3_^0'=__rho_3_^post_41, __rho_4_^0'=__rho_4_^post_41, __rho_5_^0'=__rho_5_^post_41, __rho_666_^0'=__rho_666_^post_41, __rho_7_^0'=__rho_7_^post_41, __rho_8_^0'=__rho_8_^post_41, __rho_9_^0'=__rho_9_^post_41, a11^0'=a11^post_41, a1818^0'=a1818^post_41, a2525^0'=a2525^post_41, a2828^0'=a2828^post_41, a3131^0'=a3131^post_41, a3232^0'=a3232^post_41, a3434^0'=a3434^post_41, a3737^0'=a3737^post_41, a3838^0'=a3838^post_41, a4343^0'=a4343^post_41, a4545^0'=a4545^post_41, a77^0'=a77^post_41, b22^0'=b22^post_41, b2626^0'=b2626^post_41, b2929^0'=b2929^post_41, b3333^0'=b3333^post_41, b3535^0'=b3535^post_41, i^0'=i^post_41, i___01313^0'=i___01313^post_41, i___01717^0'=i___01717^post_41, i___02020^0'=i___02020^post_41, i___02424^0'=i___02424^post_41, i___04040^0'=i___04040^post_41, i___04747^0'=i___04747^post_41, i___099^0'=i___099^post_41, ioA^0'=ioA^post_41, ioR^0'=ioR^post_41, k1^0'=k1^post_41, k2^0'=k2^post_41, k3^0'=k3^post_41, k4^0'=k4^post_41, k5^0'=k5^post_41, keA^0'=keA^post_41, keR^0'=keR^post_41, ntStatus^0'=ntStatus^post_41, pIrb^0'=pIrb^post_41, phi_io_compl^0'=phi_io_compl^post_41, phi_nSUC_ret^0'=phi_nSUC_ret^post_41, prevCancel^0'=prevCancel^post_41, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_41, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_41, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_41, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_41, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_41, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_41, [ 1<=__rho_1_^0 && a11^post_41==DeviceObject^0 && b22^post_41==Irp^0 && ret_t1394Diag_PnpStopDevice33^post_41==0 && ntStatus^post_41==ret_t1394Diag_PnpStopDevice33^post_41 && AsyncAddressData^0==AsyncAddressData^post_41 && BusResetIrp^0==BusResetIrp^post_41 && CromData^0==CromData^post_41 && DeviceObject^0==DeviceObject^post_41 && Irp^0==Irp^post_41 && Irql^0==Irql^post_41 && IsochDetachData^0==IsochDetachData^post_41 && IsochResourceData^0==IsochResourceData^post_41 && ResourceIrp^0==ResourceIrp^post_41 && StackSize^0==StackSize^post_41 && __rho_10_^0==__rho_10_^post_41 && __rho_11_^0==__rho_11_^post_41 && __rho_12_^0==__rho_12_^post_41 && __rho_1_^0==__rho_1_^post_41 && __rho_2_^0==__rho_2_^post_41 && __rho_3_^0==__rho_3_^post_41 && __rho_4_^0==__rho_4_^post_41 && __rho_5_^0==__rho_5_^post_41 && __rho_666_^0==__rho_666_^post_41 && __rho_7_^0==__rho_7_^post_41 && __rho_8_^0==__rho_8_^post_41 && __rho_9_^0==__rho_9_^post_41 && a1818^0==a1818^post_41 && a2525^0==a2525^post_41 && a2828^0==a2828^post_41 && a3131^0==a3131^post_41 && a3232^0==a3232^post_41 && a3434^0==a3434^post_41 && a3737^0==a3737^post_41 && a3838^0==a3838^post_41 && a4343^0==a4343^post_41 && a4545^0==a4545^post_41 && a77^0==a77^post_41 && b2626^0==b2626^post_41 && b2929^0==b2929^post_41 && b3333^0==b3333^post_41 && b3535^0==b3535^post_41 && i^0==i^post_41 && i___01313^0==i___01313^post_41 && i___01717^0==i___01717^post_41 && i___02020^0==i___02020^post_41 && i___02424^0==i___02424^post_41 && i___04040^0==i___04040^post_41 && i___04747^0==i___04747^post_41 && i___099^0==i___099^post_41 && ioA^0==ioA^post_41 && ioR^0==ioR^post_41 && k1^0==k1^post_41 && k2^0==k2^post_41 && k3^0==k3^post_41 && k4^0==k4^post_41 && k5^0==k5^post_41 && keA^0==keA^post_41 && keR^0==keR^post_41 && pIrb^0==pIrb^post_41 && phi_io_compl^0==phi_io_compl^post_41 && phi_nSUC_ret^0==phi_nSUC_ret^post_41 && prevCancel^0==prevCancel^post_41 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_41 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_41 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_41 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_41 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_41 ], cost: 1
     41: l29 -> l1 : AsyncAddressData^0'=AsyncAddressData^post_42, BusResetIrp^0'=BusResetIrp^post_42, CromData^0'=CromData^post_42, DeviceObject^0'=DeviceObject^post_42, Irp^0'=Irp^post_42, Irql^0'=Irql^post_42, IsochDetachData^0'=IsochDetachData^post_42, IsochResourceData^0'=IsochResourceData^post_42, ResourceIrp^0'=ResourceIrp^post_42, StackSize^0'=StackSize^post_42, __rho_10_^0'=__rho_10_^post_42, __rho_11_^0'=__rho_11_^post_42, __rho_12_^0'=__rho_12_^post_42, __rho_1_^0'=__rho_1_^post_42, __rho_2_^0'=__rho_2_^post_42, __rho_3_^0'=__rho_3_^post_42, __rho_4_^0'=__rho_4_^post_42, __rho_5_^0'=__rho_5_^post_42, __rho_666_^0'=__rho_666_^post_42, __rho_7_^0'=__rho_7_^post_42, __rho_8_^0'=__rho_8_^post_42, __rho_9_^0'=__rho_9_^post_42, a11^0'=a11^post_42, a1818^0'=a1818^post_42, a2525^0'=a2525^post_42, a2828^0'=a2828^post_42, a3131^0'=a3131^post_42, a3232^0'=a3232^post_42, a3434^0'=a3434^post_42, a3737^0'=a3737^post_42, a3838^0'=a3838^post_42, a4343^0'=a4343^post_42, a4545^0'=a4545^post_42, a77^0'=a77^post_42, b22^0'=b22^post_42, b2626^0'=b2626^post_42, b2929^0'=b2929^post_42, b3333^0'=b3333^post_42, b3535^0'=b3535^post_42, i^0'=i^post_42, i___01313^0'=i___01313^post_42, i___01717^0'=i___01717^post_42, i___02020^0'=i___02020^post_42, i___02424^0'=i___02424^post_42, i___04040^0'=i___04040^post_42, i___04747^0'=i___04747^post_42, i___099^0'=i___099^post_42, ioA^0'=ioA^post_42, ioR^0'=ioR^post_42, k1^0'=k1^post_42, k2^0'=k2^post_42, k3^0'=k3^post_42, k4^0'=k4^post_42, k5^0'=k5^post_42, keA^0'=keA^post_42, keR^0'=keR^post_42, ntStatus^0'=ntStatus^post_42, pIrb^0'=pIrb^post_42, phi_io_compl^0'=phi_io_compl^post_42, phi_nSUC_ret^0'=phi_nSUC_ret^post_42, prevCancel^0'=prevCancel^post_42, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_42, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_42, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_42, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_42, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_42, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_42, [ 1<=pIrb^0 && a3232^post_42==pIrb^0 && b3333^post_42==0 && a3434^post_42==ResourceIrp^0 && b3535^post_42==pIrb^0 && ret_t1394_SubmitIrpSynch3636^post_42==0 && ntStatus^post_42==ret_t1394_SubmitIrpSynch3636^post_42 && a3737^post_42==pIrb^0 && a3838^post_42==ResourceIrp^0 && AsyncAddressData^0==AsyncAddressData^post_42 && BusResetIrp^0==BusResetIrp^post_42 && CromData^0==CromData^post_42 && DeviceObject^0==DeviceObject^post_42 && Irp^0==Irp^post_42 && Irql^0==Irql^post_42 && IsochDetachData^0==IsochDetachData^post_42 && IsochResourceData^0==IsochResourceData^post_42 && ResourceIrp^0==ResourceIrp^post_42 && StackSize^0==StackSize^post_42 && __rho_10_^0==__rho_10_^post_42 && __rho_11_^0==__rho_11_^post_42 && __rho_12_^0==__rho_12_^post_42 && __rho_1_^0==__rho_1_^post_42 && __rho_2_^0==__rho_2_^post_42 && __rho_3_^0==__rho_3_^post_42 && __rho_4_^0==__rho_4_^post_42 && __rho_5_^0==__rho_5_^post_42 && __rho_666_^0==__rho_666_^post_42 && __rho_7_^0==__rho_7_^post_42 && __rho_8_^0==__rho_8_^post_42 && __rho_9_^0==__rho_9_^post_42 && a11^0==a11^post_42 && a1818^0==a1818^post_42 && a2525^0==a2525^post_42 && a2828^0==a2828^post_42 && a3131^0==a3131^post_42 && a4343^0==a4343^post_42 && a4545^0==a4545^post_42 && a77^0==a77^post_42 && b22^0==b22^post_42 && b2626^0==b2626^post_42 && b2929^0==b2929^post_42 && i^0==i^post_42 && i___01313^0==i___01313^post_42 && i___01717^0==i___01717^post_42 && i___02020^0==i___02020^post_42 && i___02424^0==i___02424^post_42 && i___04040^0==i___04040^post_42 && i___04747^0==i___04747^post_42 && i___099^0==i___099^post_42 && ioA^0==ioA^post_42 && ioR^0==ioR^post_42 && k1^0==k1^post_42 && k2^0==k2^post_42 && k3^0==k3^post_42 && k4^0==k4^post_42 && k5^0==k5^post_42 && keA^0==keA^post_42 && keR^0==keR^post_42 && pIrb^0==pIrb^post_42 && phi_io_compl^0==phi_io_compl^post_42 && phi_nSUC_ret^0==phi_nSUC_ret^post_42 && prevCancel^0==prevCancel^post_42 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_42 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_42 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_42 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_42 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_42 ], cost: 1
     42: l29 -> l1 : AsyncAddressData^0'=AsyncAddressData^post_43, BusResetIrp^0'=BusResetIrp^post_43, CromData^0'=CromData^post_43, DeviceObject^0'=DeviceObject^post_43, Irp^0'=Irp^post_43, Irql^0'=Irql^post_43, IsochDetachData^0'=IsochDetachData^post_43, IsochResourceData^0'=IsochResourceData^post_43, ResourceIrp^0'=ResourceIrp^post_43, StackSize^0'=StackSize^post_43, __rho_10_^0'=__rho_10_^post_43, __rho_11_^0'=__rho_11_^post_43, __rho_12_^0'=__rho_12_^post_43, __rho_1_^0'=__rho_1_^post_43, __rho_2_^0'=__rho_2_^post_43, __rho_3_^0'=__rho_3_^post_43, __rho_4_^0'=__rho_4_^post_43, __rho_5_^0'=__rho_5_^post_43, __rho_666_^0'=__rho_666_^post_43, __rho_7_^0'=__rho_7_^post_43, __rho_8_^0'=__rho_8_^post_43, __rho_9_^0'=__rho_9_^post_43, a11^0'=a11^post_43, a1818^0'=a1818^post_43, a2525^0'=a2525^post_43, a2828^0'=a2828^post_43, a3131^0'=a3131^post_43, a3232^0'=a3232^post_43, a3434^0'=a3434^post_43, a3737^0'=a3737^post_43, a3838^0'=a3838^post_43, a4343^0'=a4343^post_43, a4545^0'=a4545^post_43, a77^0'=a77^post_43, b22^0'=b22^post_43, b2626^0'=b2626^post_43, b2929^0'=b2929^post_43, b3333^0'=b3333^post_43, b3535^0'=b3535^post_43, i^0'=i^post_43, i___01313^0'=i___01313^post_43, i___01717^0'=i___01717^post_43, i___02020^0'=i___02020^post_43, i___02424^0'=i___02424^post_43, i___04040^0'=i___04040^post_43, i___04747^0'=i___04747^post_43, i___099^0'=i___099^post_43, ioA^0'=ioA^post_43, ioR^0'=ioR^post_43, k1^0'=k1^post_43, k2^0'=k2^post_43, k3^0'=k3^post_43, k4^0'=k4^post_43, k5^0'=k5^post_43, keA^0'=keA^post_43, keR^0'=keR^post_43, ntStatus^0'=ntStatus^post_43, pIrb^0'=pIrb^post_43, phi_io_compl^0'=phi_io_compl^post_43, phi_nSUC_ret^0'=phi_nSUC_ret^post_43, prevCancel^0'=prevCancel^post_43, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_43, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_43, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_43, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_43, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_43, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_43, [ pIrb^0<=0 && a3131^post_43==ResourceIrp^0 && AsyncAddressData^0==AsyncAddressData^post_43 && BusResetIrp^0==BusResetIrp^post_43 && CromData^0==CromData^post_43 && DeviceObject^0==DeviceObject^post_43 && Irp^0==Irp^post_43 && Irql^0==Irql^post_43 && IsochDetachData^0==IsochDetachData^post_43 && IsochResourceData^0==IsochResourceData^post_43 && ResourceIrp^0==ResourceIrp^post_43 && StackSize^0==StackSize^post_43 && __rho_10_^0==__rho_10_^post_43 && __rho_11_^0==__rho_11_^post_43 && __rho_12_^0==__rho_12_^post_43 && __rho_1_^0==__rho_1_^post_43 && __rho_2_^0==__rho_2_^post_43 && __rho_3_^0==__rho_3_^post_43 && __rho_4_^0==__rho_4_^post_43 && __rho_5_^0==__rho_5_^post_43 && __rho_666_^0==__rho_666_^post_43 && __rho_7_^0==__rho_7_^post_43 && __rho_8_^0==__rho_8_^post_43 && __rho_9_^0==__rho_9_^post_43 && a11^0==a11^post_43 && a1818^0==a1818^post_43 && a2525^0==a2525^post_43 && a2828^0==a2828^post_43 && a3232^0==a3232^post_43 && a3434^0==a3434^post_43 && a3737^0==a3737^post_43 && a3838^0==a3838^post_43 && a4343^0==a4343^post_43 && a4545^0==a4545^post_43 && a77^0==a77^post_43 && b22^0==b22^post_43 && b2626^0==b2626^post_43 && b2929^0==b2929^post_43 && b3333^0==b3333^post_43 && b3535^0==b3535^post_43 && i^0==i^post_43 && i___01313^0==i___01313^post_43 && i___01717^0==i___01717^post_43 && i___02020^0==i___02020^post_43 && i___02424^0==i___02424^post_43 && i___04040^0==i___04040^post_43 && i___04747^0==i___04747^post_43 && i___099^0==i___099^post_43 && ioA^0==ioA^post_43 && ioR^0==ioR^post_43 && k1^0==k1^post_43 && k2^0==k2^post_43 && k3^0==k3^post_43 && k4^0==k4^post_43 && k5^0==k5^post_43 && keA^0==keA^post_43 && keR^0==keR^post_43 && ntStatus^0==ntStatus^post_43 && pIrb^0==pIrb^post_43 && phi_io_compl^0==phi_io_compl^post_43 && phi_nSUC_ret^0==phi_nSUC_ret^post_43 && prevCancel^0==prevCancel^post_43 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_43 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_43 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_43 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_43 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_43 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_43 ], cost: 1
     43: l30 -> l29 : AsyncAddressData^0'=AsyncAddressData^post_44, BusResetIrp^0'=BusResetIrp^post_44, CromData^0'=CromData^post_44, DeviceObject^0'=DeviceObject^post_44, Irp^0'=Irp^post_44, Irql^0'=Irql^post_44, IsochDetachData^0'=IsochDetachData^post_44, IsochResourceData^0'=IsochResourceData^post_44, ResourceIrp^0'=ResourceIrp^post_44, StackSize^0'=StackSize^post_44, __rho_10_^0'=__rho_10_^post_44, __rho_11_^0'=__rho_11_^post_44, __rho_12_^0'=__rho_12_^post_44, __rho_1_^0'=__rho_1_^post_44, __rho_2_^0'=__rho_2_^post_44, __rho_3_^0'=__rho_3_^post_44, __rho_4_^0'=__rho_4_^post_44, __rho_5_^0'=__rho_5_^post_44, __rho_666_^0'=__rho_666_^post_44, __rho_7_^0'=__rho_7_^post_44, __rho_8_^0'=__rho_8_^post_44, __rho_9_^0'=__rho_9_^post_44, a11^0'=a11^post_44, a1818^0'=a1818^post_44, a2525^0'=a2525^post_44, a2828^0'=a2828^post_44, a3131^0'=a3131^post_44, a3232^0'=a3232^post_44, a3434^0'=a3434^post_44, a3737^0'=a3737^post_44, a3838^0'=a3838^post_44, a4343^0'=a4343^post_44, a4545^0'=a4545^post_44, a77^0'=a77^post_44, b22^0'=b22^post_44, b2626^0'=b2626^post_44, b2929^0'=b2929^post_44, b3333^0'=b3333^post_44, b3535^0'=b3535^post_44, i^0'=i^post_44, i___01313^0'=i___01313^post_44, i___01717^0'=i___01717^post_44, i___02020^0'=i___02020^post_44, i___02424^0'=i___02424^post_44, i___04040^0'=i___04040^post_44, i___04747^0'=i___04747^post_44, i___099^0'=i___099^post_44, ioA^0'=ioA^post_44, ioR^0'=ioR^post_44, k1^0'=k1^post_44, k2^0'=k2^post_44, k3^0'=k3^post_44, k4^0'=k4^post_44, k5^0'=k5^post_44, keA^0'=keA^post_44, keR^0'=keR^post_44, ntStatus^0'=ntStatus^post_44, pIrb^0'=pIrb^post_44, phi_io_compl^0'=phi_io_compl^post_44, phi_nSUC_ret^0'=phi_nSUC_ret^post_44, prevCancel^0'=prevCancel^post_44, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_44, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_44, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_44, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_44, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_44, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_44, [ a2828^post_44==1 && b2929^post_44==0 && ret_ExAllocatePool3030^post_44==0 && pIrb^post_44==ret_ExAllocatePool3030^post_44 && AsyncAddressData^0==AsyncAddressData^post_44 && BusResetIrp^0==BusResetIrp^post_44 && CromData^0==CromData^post_44 && DeviceObject^0==DeviceObject^post_44 && Irp^0==Irp^post_44 && Irql^0==Irql^post_44 && IsochDetachData^0==IsochDetachData^post_44 && IsochResourceData^0==IsochResourceData^post_44 && ResourceIrp^0==ResourceIrp^post_44 && StackSize^0==StackSize^post_44 && __rho_10_^0==__rho_10_^post_44 && __rho_11_^0==__rho_11_^post_44 && __rho_12_^0==__rho_12_^post_44 && __rho_1_^0==__rho_1_^post_44 && __rho_2_^0==__rho_2_^post_44 && __rho_3_^0==__rho_3_^post_44 && __rho_4_^0==__rho_4_^post_44 && __rho_5_^0==__rho_5_^post_44 && __rho_666_^0==__rho_666_^post_44 && __rho_7_^0==__rho_7_^post_44 && __rho_8_^0==__rho_8_^post_44 && __rho_9_^0==__rho_9_^post_44 && a11^0==a11^post_44 && a1818^0==a1818^post_44 && a2525^0==a2525^post_44 && a3131^0==a3131^post_44 && a3232^0==a3232^post_44 && a3434^0==a3434^post_44 && a3737^0==a3737^post_44 && a3838^0==a3838^post_44 && a4343^0==a4343^post_44 && a4545^0==a4545^post_44 && a77^0==a77^post_44 && b22^0==b22^post_44 && b2626^0==b2626^post_44 && b3333^0==b3333^post_44 && b3535^0==b3535^post_44 && i^0==i^post_44 && i___01313^0==i___01313^post_44 && i___01717^0==i___01717^post_44 && i___02020^0==i___02020^post_44 && i___02424^0==i___02424^post_44 && i___04040^0==i___04040^post_44 && i___04747^0==i___04747^post_44 && i___099^0==i___099^post_44 && ioA^0==ioA^post_44 && ioR^0==ioR^post_44 && k1^0==k1^post_44 && k2^0==k2^post_44 && k3^0==k3^post_44 && k4^0==k4^post_44 && k5^0==k5^post_44 && keA^0==keA^post_44 && keR^0==keR^post_44 && ntStatus^0==ntStatus^post_44 && phi_io_compl^0==phi_io_compl^post_44 && phi_nSUC_ret^0==phi_nSUC_ret^post_44 && prevCancel^0==prevCancel^post_44 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_44 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_44 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_44 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_44 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_44 ], cost: 1
     44: l31 -> l30 : AsyncAddressData^0'=AsyncAddressData^post_45, BusResetIrp^0'=BusResetIrp^post_45, CromData^0'=CromData^post_45, DeviceObject^0'=DeviceObject^post_45, Irp^0'=Irp^post_45, Irql^0'=Irql^post_45, IsochDetachData^0'=IsochDetachData^post_45, IsochResourceData^0'=IsochResourceData^post_45, ResourceIrp^0'=ResourceIrp^post_45, StackSize^0'=StackSize^post_45, __rho_10_^0'=__rho_10_^post_45, __rho_11_^0'=__rho_11_^post_45, __rho_12_^0'=__rho_12_^post_45, __rho_1_^0'=__rho_1_^post_45, __rho_2_^0'=__rho_2_^post_45, __rho_3_^0'=__rho_3_^post_45, __rho_4_^0'=__rho_4_^post_45, __rho_5_^0'=__rho_5_^post_45, __rho_666_^0'=__rho_666_^post_45, __rho_7_^0'=__rho_7_^post_45, __rho_8_^0'=__rho_8_^post_45, __rho_9_^0'=__rho_9_^post_45, a11^0'=a11^post_45, a1818^0'=a1818^post_45, a2525^0'=a2525^post_45, a2828^0'=a2828^post_45, a3131^0'=a3131^post_45, a3232^0'=a3232^post_45, a3434^0'=a3434^post_45, a3737^0'=a3737^post_45, a3838^0'=a3838^post_45, a4343^0'=a4343^post_45, a4545^0'=a4545^post_45, a77^0'=a77^post_45, b22^0'=b22^post_45, b2626^0'=b2626^post_45, b2929^0'=b2929^post_45, b3333^0'=b3333^post_45, b3535^0'=b3535^post_45, i^0'=i^post_45, i___01313^0'=i___01313^post_45, i___01717^0'=i___01717^post_45, i___02020^0'=i___02020^post_45, i___02424^0'=i___02424^post_45, i___04040^0'=i___04040^post_45, i___04747^0'=i___04747^post_45, i___099^0'=i___099^post_45, ioA^0'=ioA^post_45, ioR^0'=ioR^post_45, k1^0'=k1^post_45, k2^0'=k2^post_45, k3^0'=k3^post_45, k4^0'=k4^post_45, k5^0'=k5^post_45, keA^0'=keA^post_45, keR^0'=keR^post_45, ntStatus^0'=ntStatus^post_45, pIrb^0'=pIrb^post_45, phi_io_compl^0'=phi_io_compl^post_45, phi_nSUC_ret^0'=phi_nSUC_ret^post_45, prevCancel^0'=prevCancel^post_45, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_45, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_45, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_45, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_45, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_45, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_45, [ 1<=ResourceIrp^0 && AsyncAddressData^0==AsyncAddressData^post_45 && BusResetIrp^0==BusResetIrp^post_45 && CromData^0==CromData^post_45 && DeviceObject^0==DeviceObject^post_45 && Irp^0==Irp^post_45 && Irql^0==Irql^post_45 && IsochDetachData^0==IsochDetachData^post_45 && IsochResourceData^0==IsochResourceData^post_45 && ResourceIrp^0==ResourceIrp^post_45 && StackSize^0==StackSize^post_45 && __rho_10_^0==__rho_10_^post_45 && __rho_11_^0==__rho_11_^post_45 && __rho_12_^0==__rho_12_^post_45 && __rho_1_^0==__rho_1_^post_45 && __rho_2_^0==__rho_2_^post_45 && __rho_3_^0==__rho_3_^post_45 && __rho_4_^0==__rho_4_^post_45 && __rho_5_^0==__rho_5_^post_45 && __rho_666_^0==__rho_666_^post_45 && __rho_7_^0==__rho_7_^post_45 && __rho_8_^0==__rho_8_^post_45 && __rho_9_^0==__rho_9_^post_45 && a11^0==a11^post_45 && a1818^0==a1818^post_45 && a2525^0==a2525^post_45 && a2828^0==a2828^post_45 && a3131^0==a3131^post_45 && a3232^0==a3232^post_45 && a3434^0==a3434^post_45 && a3737^0==a3737^post_45 && a3838^0==a3838^post_45 && a4343^0==a4343^post_45 && a4545^0==a4545^post_45 && a77^0==a77^post_45 && b22^0==b22^post_45 && b2626^0==b2626^post_45 && b2929^0==b2929^post_45 && b3333^0==b3333^post_45 && b3535^0==b3535^post_45 && i^0==i^post_45 && i___01313^0==i___01313^post_45 && i___01717^0==i___01717^post_45 && i___02020^0==i___02020^post_45 && i___02424^0==i___02424^post_45 && i___04040^0==i___04040^post_45 && i___04747^0==i___04747^post_45 && i___099^0==i___099^post_45 && ioA^0==ioA^post_45 && ioR^0==ioR^post_45 && k1^0==k1^post_45 && k2^0==k2^post_45 && k3^0==k3^post_45 && k4^0==k4^post_45 && k5^0==k5^post_45 && keA^0==keA^post_45 && keR^0==keR^post_45 && ntStatus^0==ntStatus^post_45 && pIrb^0==pIrb^post_45 && phi_io_compl^0==phi_io_compl^post_45 && phi_nSUC_ret^0==phi_nSUC_ret^post_45 && prevCancel^0==prevCancel^post_45 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_45 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_45 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_45 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_45 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_45 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_45 ], cost: 1
     45: l31 -> l30 : AsyncAddressData^0'=AsyncAddressData^post_46, BusResetIrp^0'=BusResetIrp^post_46, CromData^0'=CromData^post_46, DeviceObject^0'=DeviceObject^post_46, Irp^0'=Irp^post_46, Irql^0'=Irql^post_46, IsochDetachData^0'=IsochDetachData^post_46, IsochResourceData^0'=IsochResourceData^post_46, ResourceIrp^0'=ResourceIrp^post_46, StackSize^0'=StackSize^post_46, __rho_10_^0'=__rho_10_^post_46, __rho_11_^0'=__rho_11_^post_46, __rho_12_^0'=__rho_12_^post_46, __rho_1_^0'=__rho_1_^post_46, __rho_2_^0'=__rho_2_^post_46, __rho_3_^0'=__rho_3_^post_46, __rho_4_^0'=__rho_4_^post_46, __rho_5_^0'=__rho_5_^post_46, __rho_666_^0'=__rho_666_^post_46, __rho_7_^0'=__rho_7_^post_46, __rho_8_^0'=__rho_8_^post_46, __rho_9_^0'=__rho_9_^post_46, a11^0'=a11^post_46, a1818^0'=a1818^post_46, a2525^0'=a2525^post_46, a2828^0'=a2828^post_46, a3131^0'=a3131^post_46, a3232^0'=a3232^post_46, a3434^0'=a3434^post_46, a3737^0'=a3737^post_46, a3838^0'=a3838^post_46, a4343^0'=a4343^post_46, a4545^0'=a4545^post_46, a77^0'=a77^post_46, b22^0'=b22^post_46, b2626^0'=b2626^post_46, b2929^0'=b2929^post_46, b3333^0'=b3333^post_46, b3535^0'=b3535^post_46, i^0'=i^post_46, i___01313^0'=i___01313^post_46, i___01717^0'=i___01717^post_46, i___02020^0'=i___02020^post_46, i___02424^0'=i___02424^post_46, i___04040^0'=i___04040^post_46, i___04747^0'=i___04747^post_46, i___099^0'=i___099^post_46, ioA^0'=ioA^post_46, ioR^0'=ioR^post_46, k1^0'=k1^post_46, k2^0'=k2^post_46, k3^0'=k3^post_46, k4^0'=k4^post_46, k5^0'=k5^post_46, keA^0'=keA^post_46, keR^0'=keR^post_46, ntStatus^0'=ntStatus^post_46, pIrb^0'=pIrb^post_46, phi_io_compl^0'=phi_io_compl^post_46, phi_nSUC_ret^0'=phi_nSUC_ret^post_46, prevCancel^0'=prevCancel^post_46, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_46, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_46, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_46, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_46, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_46, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_46, [ 1+ResourceIrp^0<=0 && AsyncAddressData^0==AsyncAddressData^post_46 && BusResetIrp^0==BusResetIrp^post_46 && CromData^0==CromData^post_46 && DeviceObject^0==DeviceObject^post_46 && Irp^0==Irp^post_46 && Irql^0==Irql^post_46 && IsochDetachData^0==IsochDetachData^post_46 && IsochResourceData^0==IsochResourceData^post_46 && ResourceIrp^0==ResourceIrp^post_46 && StackSize^0==StackSize^post_46 && __rho_10_^0==__rho_10_^post_46 && __rho_11_^0==__rho_11_^post_46 && __rho_12_^0==__rho_12_^post_46 && __rho_1_^0==__rho_1_^post_46 && __rho_2_^0==__rho_2_^post_46 && __rho_3_^0==__rho_3_^post_46 && __rho_4_^0==__rho_4_^post_46 && __rho_5_^0==__rho_5_^post_46 && __rho_666_^0==__rho_666_^post_46 && __rho_7_^0==__rho_7_^post_46 && __rho_8_^0==__rho_8_^post_46 && __rho_9_^0==__rho_9_^post_46 && a11^0==a11^post_46 && a1818^0==a1818^post_46 && a2525^0==a2525^post_46 && a2828^0==a2828^post_46 && a3131^0==a3131^post_46 && a3232^0==a3232^post_46 && a3434^0==a3434^post_46 && a3737^0==a3737^post_46 && a3838^0==a3838^post_46 && a4343^0==a4343^post_46 && a4545^0==a4545^post_46 && a77^0==a77^post_46 && b22^0==b22^post_46 && b2626^0==b2626^post_46 && b2929^0==b2929^post_46 && b3333^0==b3333^post_46 && b3535^0==b3535^post_46 && i^0==i^post_46 && i___01313^0==i___01313^post_46 && i___01717^0==i___01717^post_46 && i___02020^0==i___02020^post_46 && i___02424^0==i___02424^post_46 && i___04040^0==i___04040^post_46 && i___04747^0==i___04747^post_46 && i___099^0==i___099^post_46 && ioA^0==ioA^post_46 && ioR^0==ioR^post_46 && k1^0==k1^post_46 && k2^0==k2^post_46 && k3^0==k3^post_46 && k4^0==k4^post_46 && k5^0==k5^post_46 && keA^0==keA^post_46 && keR^0==keR^post_46 && ntStatus^0==ntStatus^post_46 && pIrb^0==pIrb^post_46 && phi_io_compl^0==phi_io_compl^post_46 && phi_nSUC_ret^0==phi_nSUC_ret^post_46 && prevCancel^0==prevCancel^post_46 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_46 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_46 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_46 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_46 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_46 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_46 ], cost: 1
     46: l31 -> l1 : AsyncAddressData^0'=AsyncAddressData^post_47, BusResetIrp^0'=BusResetIrp^post_47, CromData^0'=CromData^post_47, DeviceObject^0'=DeviceObject^post_47, Irp^0'=Irp^post_47, Irql^0'=Irql^post_47, IsochDetachData^0'=IsochDetachData^post_47, IsochResourceData^0'=IsochResourceData^post_47, ResourceIrp^0'=ResourceIrp^post_47, StackSize^0'=StackSize^post_47, __rho_10_^0'=__rho_10_^post_47, __rho_11_^0'=__rho_11_^post_47, __rho_12_^0'=__rho_12_^post_47, __rho_1_^0'=__rho_1_^post_47, __rho_2_^0'=__rho_2_^post_47, __rho_3_^0'=__rho_3_^post_47, __rho_4_^0'=__rho_4_^post_47, __rho_5_^0'=__rho_5_^post_47, __rho_666_^0'=__rho_666_^post_47, __rho_7_^0'=__rho_7_^post_47, __rho_8_^0'=__rho_8_^post_47, __rho_9_^0'=__rho_9_^post_47, a11^0'=a11^post_47, a1818^0'=a1818^post_47, a2525^0'=a2525^post_47, a2828^0'=a2828^post_47, a3131^0'=a3131^post_47, a3232^0'=a3232^post_47, a3434^0'=a3434^post_47, a3737^0'=a3737^post_47, a3838^0'=a3838^post_47, a4343^0'=a4343^post_47, a4545^0'=a4545^post_47, a77^0'=a77^post_47, b22^0'=b22^post_47, b2626^0'=b2626^post_47, b2929^0'=b2929^post_47, b3333^0'=b3333^post_47, b3535^0'=b3535^post_47, i^0'=i^post_47, i___01313^0'=i___01313^post_47, i___01717^0'=i___01717^post_47, i___02020^0'=i___02020^post_47, i___02424^0'=i___02424^post_47, i___04040^0'=i___04040^post_47, i___04747^0'=i___04747^post_47, i___099^0'=i___099^post_47, ioA^0'=ioA^post_47, ioR^0'=ioR^post_47, k1^0'=k1^post_47, k2^0'=k2^post_47, k3^0'=k3^post_47, k4^0'=k4^post_47, k5^0'=k5^post_47, keA^0'=keA^post_47, keR^0'=keR^post_47, ntStatus^0'=ntStatus^post_47, pIrb^0'=pIrb^post_47, phi_io_compl^0'=phi_io_compl^post_47, phi_nSUC_ret^0'=phi_nSUC_ret^post_47, prevCancel^0'=prevCancel^post_47, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_47, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_47, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_47, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_47, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_47, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_47, [ ResourceIrp^0<=0 && 0<=ResourceIrp^0 && AsyncAddressData^0==AsyncAddressData^post_47 && BusResetIrp^0==BusResetIrp^post_47 && CromData^0==CromData^post_47 && DeviceObject^0==DeviceObject^post_47 && Irp^0==Irp^post_47 && Irql^0==Irql^post_47 && IsochDetachData^0==IsochDetachData^post_47 && IsochResourceData^0==IsochResourceData^post_47 && ResourceIrp^0==ResourceIrp^post_47 && StackSize^0==StackSize^post_47 && __rho_10_^0==__rho_10_^post_47 && __rho_11_^0==__rho_11_^post_47 && __rho_12_^0==__rho_12_^post_47 && __rho_1_^0==__rho_1_^post_47 && __rho_2_^0==__rho_2_^post_47 && __rho_3_^0==__rho_3_^post_47 && __rho_4_^0==__rho_4_^post_47 && __rho_5_^0==__rho_5_^post_47 && __rho_666_^0==__rho_666_^post_47 && __rho_7_^0==__rho_7_^post_47 && __rho_8_^0==__rho_8_^post_47 && __rho_9_^0==__rho_9_^post_47 && a11^0==a11^post_47 && a1818^0==a1818^post_47 && a2525^0==a2525^post_47 && a2828^0==a2828^post_47 && a3131^0==a3131^post_47 && a3232^0==a3232^post_47 && a3434^0==a3434^post_47 && a3737^0==a3737^post_47 && a3838^0==a3838^post_47 && a4343^0==a4343^post_47 && a4545^0==a4545^post_47 && a77^0==a77^post_47 && b22^0==b22^post_47 && b2626^0==b2626^post_47 && b2929^0==b2929^post_47 && b3333^0==b3333^post_47 && b3535^0==b3535^post_47 && i^0==i^post_47 && i___01313^0==i___01313^post_47 && i___01717^0==i___01717^post_47 && i___02020^0==i___02020^post_47 && i___02424^0==i___02424^post_47 && i___04040^0==i___04040^post_47 && i___04747^0==i___04747^post_47 && i___099^0==i___099^post_47 && ioA^0==ioA^post_47 && ioR^0==ioR^post_47 && k1^0==k1^post_47 && k2^0==k2^post_47 && k3^0==k3^post_47 && k4^0==k4^post_47 && k5^0==k5^post_47 && keA^0==keA^post_47 && keR^0==keR^post_47 && ntStatus^0==ntStatus^post_47 && pIrb^0==pIrb^post_47 && phi_io_compl^0==phi_io_compl^post_47 && phi_nSUC_ret^0==phi_nSUC_ret^post_47 && prevCancel^0==prevCancel^post_47 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_47 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_47 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_47 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_47 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_47 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_47 ], cost: 1
     47: l32 -> l1 : AsyncAddressData^0'=AsyncAddressData^post_48, BusResetIrp^0'=BusResetIrp^post_48, CromData^0'=CromData^post_48, DeviceObject^0'=DeviceObject^post_48, Irp^0'=Irp^post_48, Irql^0'=Irql^post_48, IsochDetachData^0'=IsochDetachData^post_48, IsochResourceData^0'=IsochResourceData^post_48, ResourceIrp^0'=ResourceIrp^post_48, StackSize^0'=StackSize^post_48, __rho_10_^0'=__rho_10_^post_48, __rho_11_^0'=__rho_11_^post_48, __rho_12_^0'=__rho_12_^post_48, __rho_1_^0'=__rho_1_^post_48, __rho_2_^0'=__rho_2_^post_48, __rho_3_^0'=__rho_3_^post_48, __rho_4_^0'=__rho_4_^post_48, __rho_5_^0'=__rho_5_^post_48, __rho_666_^0'=__rho_666_^post_48, __rho_7_^0'=__rho_7_^post_48, __rho_8_^0'=__rho_8_^post_48, __rho_9_^0'=__rho_9_^post_48, a11^0'=a11^post_48, a1818^0'=a1818^post_48, a2525^0'=a2525^post_48, a2828^0'=a2828^post_48, a3131^0'=a3131^post_48, a3232^0'=a3232^post_48, a3434^0'=a3434^post_48, a3737^0'=a3737^post_48, a3838^0'=a3838^post_48, a4343^0'=a4343^post_48, a4545^0'=a4545^post_48, a77^0'=a77^post_48, b22^0'=b22^post_48, b2626^0'=b2626^post_48, b2929^0'=b2929^post_48, b3333^0'=b3333^post_48, b3535^0'=b3535^post_48, i^0'=i^post_48, i___01313^0'=i___01313^post_48, i___01717^0'=i___01717^post_48, i___02020^0'=i___02020^post_48, i___02424^0'=i___02424^post_48, i___04040^0'=i___04040^post_48, i___04747^0'=i___04747^post_48, i___099^0'=i___099^post_48, ioA^0'=ioA^post_48, ioR^0'=ioR^post_48, k1^0'=k1^post_48, k2^0'=k2^post_48, k3^0'=k3^post_48, k4^0'=k4^post_48, k5^0'=k5^post_48, keA^0'=keA^post_48, keR^0'=keR^post_48, ntStatus^0'=ntStatus^post_48, pIrb^0'=pIrb^post_48, phi_io_compl^0'=phi_io_compl^post_48, phi_nSUC_ret^0'=phi_nSUC_ret^post_48, prevCancel^0'=prevCancel^post_48, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_48, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_48, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_48, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_48, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_48, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_48, [ IsochResourceData^0<=0 && AsyncAddressData^0==AsyncAddressData^post_48 && BusResetIrp^0==BusResetIrp^post_48 && CromData^0==CromData^post_48 && DeviceObject^0==DeviceObject^post_48 && Irp^0==Irp^post_48 && Irql^0==Irql^post_48 && IsochDetachData^0==IsochDetachData^post_48 && IsochResourceData^0==IsochResourceData^post_48 && ResourceIrp^0==ResourceIrp^post_48 && StackSize^0==StackSize^post_48 && __rho_10_^0==__rho_10_^post_48 && __rho_11_^0==__rho_11_^post_48 && __rho_12_^0==__rho_12_^post_48 && __rho_1_^0==__rho_1_^post_48 && __rho_2_^0==__rho_2_^post_48 && __rho_3_^0==__rho_3_^post_48 && __rho_4_^0==__rho_4_^post_48 && __rho_5_^0==__rho_5_^post_48 && __rho_666_^0==__rho_666_^post_48 && __rho_7_^0==__rho_7_^post_48 && __rho_8_^0==__rho_8_^post_48 && __rho_9_^0==__rho_9_^post_48 && a11^0==a11^post_48 && a1818^0==a1818^post_48 && a2525^0==a2525^post_48 && a2828^0==a2828^post_48 && a3131^0==a3131^post_48 && a3232^0==a3232^post_48 && a3434^0==a3434^post_48 && a3737^0==a3737^post_48 && a3838^0==a3838^post_48 && a4343^0==a4343^post_48 && a4545^0==a4545^post_48 && a77^0==a77^post_48 && b22^0==b22^post_48 && b2626^0==b2626^post_48 && b2929^0==b2929^post_48 && b3333^0==b3333^post_48 && b3535^0==b3535^post_48 && i^0==i^post_48 && i___01313^0==i___01313^post_48 && i___01717^0==i___01717^post_48 && i___02020^0==i___02020^post_48 && i___02424^0==i___02424^post_48 && i___04040^0==i___04040^post_48 && i___04747^0==i___04747^post_48 && i___099^0==i___099^post_48 && ioA^0==ioA^post_48 && ioR^0==ioR^post_48 && k1^0==k1^post_48 && k2^0==k2^post_48 && k3^0==k3^post_48 && k4^0==k4^post_48 && k5^0==k5^post_48 && keA^0==keA^post_48 && keR^0==keR^post_48 && ntStatus^0==ntStatus^post_48 && pIrb^0==pIrb^post_48 && phi_io_compl^0==phi_io_compl^post_48 && phi_nSUC_ret^0==phi_nSUC_ret^post_48 && prevCancel^0==prevCancel^post_48 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_48 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_48 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_48 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_48 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_48 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_48 ], cost: 1
     48: l32 -> l31 : AsyncAddressData^0'=AsyncAddressData^post_49, BusResetIrp^0'=BusResetIrp^post_49, CromData^0'=CromData^post_49, DeviceObject^0'=DeviceObject^post_49, Irp^0'=Irp^post_49, Irql^0'=Irql^post_49, IsochDetachData^0'=IsochDetachData^post_49, IsochResourceData^0'=IsochResourceData^post_49, ResourceIrp^0'=ResourceIrp^post_49, StackSize^0'=StackSize^post_49, __rho_10_^0'=__rho_10_^post_49, __rho_11_^0'=__rho_11_^post_49, __rho_12_^0'=__rho_12_^post_49, __rho_1_^0'=__rho_1_^post_49, __rho_2_^0'=__rho_2_^post_49, __rho_3_^0'=__rho_3_^post_49, __rho_4_^0'=__rho_4_^post_49, __rho_5_^0'=__rho_5_^post_49, __rho_666_^0'=__rho_666_^post_49, __rho_7_^0'=__rho_7_^post_49, __rho_8_^0'=__rho_8_^post_49, __rho_9_^0'=__rho_9_^post_49, a11^0'=a11^post_49, a1818^0'=a1818^post_49, a2525^0'=a2525^post_49, a2828^0'=a2828^post_49, a3131^0'=a3131^post_49, a3232^0'=a3232^post_49, a3434^0'=a3434^post_49, a3737^0'=a3737^post_49, a3838^0'=a3838^post_49, a4343^0'=a4343^post_49, a4545^0'=a4545^post_49, a77^0'=a77^post_49, b22^0'=b22^post_49, b2626^0'=b2626^post_49, b2929^0'=b2929^post_49, b3333^0'=b3333^post_49, b3535^0'=b3535^post_49, i^0'=i^post_49, i___01313^0'=i___01313^post_49, i___01717^0'=i___01717^post_49, i___02020^0'=i___02020^post_49, i___02424^0'=i___02424^post_49, i___04040^0'=i___04040^post_49, i___04747^0'=i___04747^post_49, i___099^0'=i___099^post_49, ioA^0'=ioA^post_49, ioR^0'=ioR^post_49, k1^0'=k1^post_49, k2^0'=k2^post_49, k3^0'=k3^post_49, k4^0'=k4^post_49, k5^0'=k5^post_49, keA^0'=keA^post_49, keR^0'=keR^post_49, ntStatus^0'=ntStatus^post_49, pIrb^0'=pIrb^post_49, phi_io_compl^0'=phi_io_compl^post_49, phi_nSUC_ret^0'=phi_nSUC_ret^post_49, prevCancel^0'=prevCancel^post_49, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_49, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_49, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_49, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_49, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_49, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_49, [ 1<=IsochResourceData^0 && pIrb^post_49==pIrb^post_49 && ResourceIrp^1_1==ResourceIrp^1_1 && StackSize^post_49==StackSize^post_49 && a2525^post_49==StackSize^post_49 && b2626^post_49==0 && ret_IoAllocateIrp2727^post_49==0 && ResourceIrp^post_49==ret_IoAllocateIrp2727^post_49 && AsyncAddressData^0==AsyncAddressData^post_49 && BusResetIrp^0==BusResetIrp^post_49 && CromData^0==CromData^post_49 && DeviceObject^0==DeviceObject^post_49 && Irp^0==Irp^post_49 && Irql^0==Irql^post_49 && IsochDetachData^0==IsochDetachData^post_49 && IsochResourceData^0==IsochResourceData^post_49 && __rho_10_^0==__rho_10_^post_49 && __rho_11_^0==__rho_11_^post_49 && __rho_12_^0==__rho_12_^post_49 && __rho_1_^0==__rho_1_^post_49 && __rho_2_^0==__rho_2_^post_49 && __rho_3_^0==__rho_3_^post_49 && __rho_4_^0==__rho_4_^post_49 && __rho_5_^0==__rho_5_^post_49 && __rho_666_^0==__rho_666_^post_49 && __rho_7_^0==__rho_7_^post_49 && __rho_8_^0==__rho_8_^post_49 && __rho_9_^0==__rho_9_^post_49 && a11^0==a11^post_49 && a1818^0==a1818^post_49 && a2828^0==a2828^post_49 && a3131^0==a3131^post_49 && a3232^0==a3232^post_49 && a3434^0==a3434^post_49 && a3737^0==a3737^post_49 && a3838^0==a3838^post_49 && a4343^0==a4343^post_49 && a4545^0==a4545^post_49 && a77^0==a77^post_49 && b22^0==b22^post_49 && b2929^0==b2929^post_49 && b3333^0==b3333^post_49 && b3535^0==b3535^post_49 && i^0==i^post_49 && i___01313^0==i___01313^post_49 && i___01717^0==i___01717^post_49 && i___02020^0==i___02020^post_49 && i___02424^0==i___02424^post_49 && i___04040^0==i___04040^post_49 && i___04747^0==i___04747^post_49 && i___099^0==i___099^post_49 && ioA^0==ioA^post_49 && ioR^0==ioR^post_49 && k1^0==k1^post_49 && k2^0==k2^post_49 && k3^0==k3^post_49 && k4^0==k4^post_49 && k5^0==k5^post_49 && keA^0==keA^post_49 && keR^0==keR^post_49 && ntStatus^0==ntStatus^post_49 && phi_io_compl^0==phi_io_compl^post_49 && phi_nSUC_ret^0==phi_nSUC_ret^post_49 && prevCancel^0==prevCancel^post_49 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_49 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_49 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_49 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_49 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_49 ], cost: 1
     51: l33 -> l28 : AsyncAddressData^0'=AsyncAddressData^post_52, BusResetIrp^0'=BusResetIrp^post_52, CromData^0'=CromData^post_52, DeviceObject^0'=DeviceObject^post_52, Irp^0'=Irp^post_52, Irql^0'=Irql^post_52, IsochDetachData^0'=IsochDetachData^post_52, IsochResourceData^0'=IsochResourceData^post_52, ResourceIrp^0'=ResourceIrp^post_52, StackSize^0'=StackSize^post_52, __rho_10_^0'=__rho_10_^post_52, __rho_11_^0'=__rho_11_^post_52, __rho_12_^0'=__rho_12_^post_52, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_52, __rho_3_^0'=__rho_3_^post_52, __rho_4_^0'=__rho_4_^post_52, __rho_5_^0'=__rho_5_^post_52, __rho_666_^0'=__rho_666_^post_52, __rho_7_^0'=__rho_7_^post_52, __rho_8_^0'=__rho_8_^post_52, __rho_9_^0'=__rho_9_^post_52, a11^0'=a11^post_52, a1818^0'=a1818^post_52, a2525^0'=a2525^post_52, a2828^0'=a2828^post_52, a3131^0'=a3131^post_52, a3232^0'=a3232^post_52, a3434^0'=a3434^post_52, a3737^0'=a3737^post_52, a3838^0'=a3838^post_52, a4343^0'=a4343^post_52, a4545^0'=a4545^post_52, a77^0'=a77^post_52, b22^0'=b22^post_52, b2626^0'=b2626^post_52, b2929^0'=b2929^post_52, b3333^0'=b3333^post_52, b3535^0'=b3535^post_52, i^0'=i^post_52, i___01313^0'=i___01313^post_52, i___01717^0'=i___01717^post_52, i___02020^0'=i___02020^post_52, i___02424^0'=i___02424^post_52, i___04040^0'=i___04040^post_52, i___04747^0'=i___04747^post_52, i___099^0'=i___099^post_52, ioA^0'=ioA^post_52, ioR^0'=ioR^post_52, k1^0'=k1^post_52, k2^0'=k2^post_52, k3^0'=k3^post_52, k4^0'=k4^post_52, k5^0'=k5^post_52, keA^0'=keA^post_52, keR^0'=keR^post_52, ntStatus^0'=ntStatus^post_52, pIrb^0'=pIrb^post_52, phi_io_compl^0'=phi_io_compl^post_52, phi_nSUC_ret^0'=phi_nSUC_ret^post_52, prevCancel^0'=prevCancel^post_52, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_52, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_52, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_52, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_52, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_52, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_52, [ ioR^post_52==0 && ioA^post_52==ioR^post_52 && keR^post_52==ioA^post_52 && keA^post_52==keR^post_52 && phi_nSUC_ret^post_52==0 && phi_io_compl^post_52==0 && __rho_666_^post_52==__rho_666_^post_52 && __rho_1_^post_52==__rho_1_^post_52 && AsyncAddressData^0==AsyncAddressData^post_52 && BusResetIrp^0==BusResetIrp^post_52 && CromData^0==CromData^post_52 && DeviceObject^0==DeviceObject^post_52 && Irp^0==Irp^post_52 && Irql^0==Irql^post_52 && IsochDetachData^0==IsochDetachData^post_52 && IsochResourceData^0==IsochResourceData^post_52 && ResourceIrp^0==ResourceIrp^post_52 && StackSize^0==StackSize^post_52 && __rho_10_^0==__rho_10_^post_52 && __rho_11_^0==__rho_11_^post_52 && __rho_12_^0==__rho_12_^post_52 && __rho_2_^0==__rho_2_^post_52 && __rho_3_^0==__rho_3_^post_52 && __rho_4_^0==__rho_4_^post_52 && __rho_5_^0==__rho_5_^post_52 && __rho_7_^0==__rho_7_^post_52 && __rho_8_^0==__rho_8_^post_52 && __rho_9_^0==__rho_9_^post_52 && a11^0==a11^post_52 && a1818^0==a1818^post_52 && a2525^0==a2525^post_52 && a2828^0==a2828^post_52 && a3131^0==a3131^post_52 && a3232^0==a3232^post_52 && a3434^0==a3434^post_52 && a3737^0==a3737^post_52 && a3838^0==a3838^post_52 && a4343^0==a4343^post_52 && a4545^0==a4545^post_52 && a77^0==a77^post_52 && b22^0==b22^post_52 && b2626^0==b2626^post_52 && b2929^0==b2929^post_52 && b3333^0==b3333^post_52 && b3535^0==b3535^post_52 && i^0==i^post_52 && i___01313^0==i___01313^post_52 && i___01717^0==i___01717^post_52 && i___02020^0==i___02020^post_52 && i___02424^0==i___02424^post_52 && i___04040^0==i___04040^post_52 && i___04747^0==i___04747^post_52 && i___099^0==i___099^post_52 && k1^0==k1^post_52 && k2^0==k2^post_52 && k3^0==k3^post_52 && k4^0==k4^post_52 && k5^0==k5^post_52 && ntStatus^0==ntStatus^post_52 && pIrb^0==pIrb^post_52 && prevCancel^0==prevCancel^post_52 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_52 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_52 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_52 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_52 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_52 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_52 ], cost: 1
     52: l34 -> l33 : AsyncAddressData^0'=AsyncAddressData^post_53, BusResetIrp^0'=BusResetIrp^post_53, CromData^0'=CromData^post_53, DeviceObject^0'=DeviceObject^post_53, Irp^0'=Irp^post_53, Irql^0'=Irql^post_53, IsochDetachData^0'=IsochDetachData^post_53, IsochResourceData^0'=IsochResourceData^post_53, ResourceIrp^0'=ResourceIrp^post_53, StackSize^0'=StackSize^post_53, __rho_10_^0'=__rho_10_^post_53, __rho_11_^0'=__rho_11_^post_53, __rho_12_^0'=__rho_12_^post_53, __rho_1_^0'=__rho_1_^post_53, __rho_2_^0'=__rho_2_^post_53, __rho_3_^0'=__rho_3_^post_53, __rho_4_^0'=__rho_4_^post_53, __rho_5_^0'=__rho_5_^post_53, __rho_666_^0'=__rho_666_^post_53, __rho_7_^0'=__rho_7_^post_53, __rho_8_^0'=__rho_8_^post_53, __rho_9_^0'=__rho_9_^post_53, a11^0'=a11^post_53, a1818^0'=a1818^post_53, a2525^0'=a2525^post_53, a2828^0'=a2828^post_53, a3131^0'=a3131^post_53, a3232^0'=a3232^post_53, a3434^0'=a3434^post_53, a3737^0'=a3737^post_53, a3838^0'=a3838^post_53, a4343^0'=a4343^post_53, a4545^0'=a4545^post_53, a77^0'=a77^post_53, b22^0'=b22^post_53, b2626^0'=b2626^post_53, b2929^0'=b2929^post_53, b3333^0'=b3333^post_53, b3535^0'=b3535^post_53, i^0'=i^post_53, i___01313^0'=i___01313^post_53, i___01717^0'=i___01717^post_53, i___02020^0'=i___02020^post_53, i___02424^0'=i___02424^post_53, i___04040^0'=i___04040^post_53, i___04747^0'=i___04747^post_53, i___099^0'=i___099^post_53, ioA^0'=ioA^post_53, ioR^0'=ioR^post_53, k1^0'=k1^post_53, k2^0'=k2^post_53, k3^0'=k3^post_53, k4^0'=k4^post_53, k5^0'=k5^post_53, keA^0'=keA^post_53, keR^0'=keR^post_53, ntStatus^0'=ntStatus^post_53, pIrb^0'=pIrb^post_53, phi_io_compl^0'=phi_io_compl^post_53, phi_nSUC_ret^0'=phi_nSUC_ret^post_53, prevCancel^0'=prevCancel^post_53, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_53, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_53, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_53, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_53, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_53, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_53, [ AsyncAddressData^0==AsyncAddressData^post_53 && BusResetIrp^0==BusResetIrp^post_53 && CromData^0==CromData^post_53 && DeviceObject^0==DeviceObject^post_53 && Irp^0==Irp^post_53 && Irql^0==Irql^post_53 && IsochDetachData^0==IsochDetachData^post_53 && IsochResourceData^0==IsochResourceData^post_53 && ResourceIrp^0==ResourceIrp^post_53 && StackSize^0==StackSize^post_53 && __rho_10_^0==__rho_10_^post_53 && __rho_11_^0==__rho_11_^post_53 && __rho_12_^0==__rho_12_^post_53 && __rho_1_^0==__rho_1_^post_53 && __rho_2_^0==__rho_2_^post_53 && __rho_3_^0==__rho_3_^post_53 && __rho_4_^0==__rho_4_^post_53 && __rho_5_^0==__rho_5_^post_53 && __rho_666_^0==__rho_666_^post_53 && __rho_7_^0==__rho_7_^post_53 && __rho_8_^0==__rho_8_^post_53 && __rho_9_^0==__rho_9_^post_53 && a11^0==a11^post_53 && a1818^0==a1818^post_53 && a2525^0==a2525^post_53 && a2828^0==a2828^post_53 && a3131^0==a3131^post_53 && a3232^0==a3232^post_53 && a3434^0==a3434^post_53 && a3737^0==a3737^post_53 && a3838^0==a3838^post_53 && a4343^0==a4343^post_53 && a4545^0==a4545^post_53 && a77^0==a77^post_53 && b22^0==b22^post_53 && b2626^0==b2626^post_53 && b2929^0==b2929^post_53 && b3333^0==b3333^post_53 && b3535^0==b3535^post_53 && i^0==i^post_53 && i___01313^0==i___01313^post_53 && i___01717^0==i___01717^post_53 && i___02020^0==i___02020^post_53 && i___02424^0==i___02424^post_53 && i___04040^0==i___04040^post_53 && i___04747^0==i___04747^post_53 && i___099^0==i___099^post_53 && ioA^0==ioA^post_53 && ioR^0==ioR^post_53 && k1^0==k1^post_53 && k2^0==k2^post_53 && k3^0==k3^post_53 && k4^0==k4^post_53 && k5^0==k5^post_53 && keA^0==keA^post_53 && keR^0==keR^post_53 && ntStatus^0==ntStatus^post_53 && pIrb^0==pIrb^post_53 && phi_io_compl^0==phi_io_compl^post_53 && phi_nSUC_ret^0==phi_nSUC_ret^post_53 && prevCancel^0==prevCancel^post_53 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_53 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_53 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_53 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_53 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_53 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_53 ], cost: 1

Simplified all rules, resulting in:
   Start location: l34
      0: l0 -> l1 : __rho_11_^0'=__rho_11_^post_1, i___02020^0'=Irql^0, k4^0'=__rho_11_^post_1, keR^0'=0, [ k3^0<=0 ], cost: 1
      1: l0 -> l2 : IsochDetachData^0'=IsochDetachData^post_2, a1818^0'=IsochDetachData^post_2, i^0'=i^post_2, i___01717^0'=Irql^0, k3^0'=-1+k3^0, keR^0'=0, [ 1<=k3^0 ], cost: 1
     23: l1 -> l17 : keA^0'=0, [], cost: 1
     16: l2 -> l0 : keA^0'=0, [], cost: 1
      2: l3 -> l4 : [ AsyncAddressData^0<=0 ], cost: 1
      3: l3 -> l4 : [ 1<=AsyncAddressData^0 ], cost: 1
     15: l4 -> l12 : [], cost: 1
      4: l5 -> l3 : [ __rho_9_^0<=0 ], cost: 1
      5: l5 -> l3 : [ 1<=__rho_9_^0 ], cost: 1
      6: l6 -> l5 : __rho_9_^0'=__rho_9_^post_7, [], cost: 1
      7: l7 -> l6 : [ __rho_8_^0<=0 ], cost: 1
      8: l7 -> l6 : [ 1<=__rho_8_^0 ], cost: 1
      9: l8 -> l7 : __rho_8_^0'=__rho_8_^post_10, [], cost: 1
     10: l9 -> l8 : [ __rho_7_^0<=0 ], cost: 1
     11: l9 -> l8 : [ 1<=__rho_7_^0 ], cost: 1
     12: l10 -> l11 : [], cost: 1
     26: l11 -> l18 : CromData^0'=CromData^post_27, k1^0'=-1+k1^0, [ 1<=k1^0 ], cost: 1
     27: l11 -> l4 : __rho_4_^0'=__rho_4_^post_28, i___099^0'=Irql^0, k2^0'=__rho_4_^post_28, keA^0'=0, keR^0'=0, [ k1^0<=0 ], cost: 1
     13: l12 -> l9 : AsyncAddressData^0'=AsyncAddressData^post_14, __rho_7_^0'=__rho_7_^post_14, k2^0'=-1+k2^0, [ 1<=k2^0 ], cost: 1
     14: l12 -> l2 : __rho_10_^0'=__rho_10_^post_15, i___01313^0'=Irql^0, k3^0'=__rho_10_^post_15, keR^0'=0, [ k2^0<=0 ], cost: 1
     17: l13 -> l10 : a77^0'=CromData^0, [], cost: 1
     18: l14 -> l13 : [ __rho_3_^0<=0 ], cost: 1
     19: l14 -> l13 : [ 1<=__rho_3_^0 ], cost: 1
     20: l15 -> l14 : __rho_3_^0'=__rho_3_^post_21, [], cost: 1
     21: l16 -> l15 : [ __rho_2_^0<=0 ], cost: 1
     22: l16 -> l15 : [ 1<=__rho_2_^0 ], cost: 1
     49: l17 -> l19 : AsyncAddressData^0'=AsyncAddressData^post_50, BusResetIrp^0'=BusResetIrp^post_50, CromData^0'=CromData^post_50, DeviceObject^0'=DeviceObject^post_50, Irp^0'=Irp^post_50, Irql^0'=Irql^post_50, IsochDetachData^0'=IsochDetachData^post_50, IsochResourceData^0'=IsochResourceData^post_50, ResourceIrp^0'=ResourceIrp^post_50, StackSize^0'=StackSize^post_50, __rho_10_^0'=__rho_10_^post_50, __rho_11_^0'=__rho_11_^post_50, __rho_12_^0'=__rho_12_^post_50, __rho_1_^0'=__rho_1_^post_50, __rho_2_^0'=__rho_2_^post_50, __rho_3_^0'=__rho_3_^post_50, __rho_4_^0'=__rho_4_^post_50, __rho_5_^0'=__rho_5_^post_50, __rho_666_^0'=__rho_666_^post_50, __rho_7_^0'=__rho_7_^post_50, __rho_8_^0'=__rho_8_^post_50, __rho_9_^0'=__rho_9_^post_50, a11^0'=a11^post_50, a1818^0'=a1818^post_50, a2525^0'=a2525^post_50, a2828^0'=a2828^post_50, a3131^0'=a3131^post_50, a3232^0'=a3232^post_50, a3434^0'=a3434^post_50, a3737^0'=a3737^post_50, a3838^0'=a3838^post_50, a4343^0'=a4343^post_50, a4545^0'=a4545^post_50, a77^0'=a77^post_50, b22^0'=b22^post_50, b2626^0'=b2626^post_50, b2929^0'=b2929^post_50, b3333^0'=b3333^post_50, b3535^0'=b3535^post_50, i^0'=i^post_50, i___01313^0'=i___01313^post_50, i___01717^0'=i___01717^post_50, i___02020^0'=i___02020^post_50, i___02424^0'=i___02424^post_50, i___04040^0'=i___04040^post_50, i___04747^0'=i___04747^post_50, i___099^0'=i___099^post_50, ioA^0'=ioA^post_50, ioR^0'=ioR^post_50, k1^0'=k1^post_50, k2^0'=k2^post_50, k3^0'=k3^post_50, k4^0'=k4^post_50, k5^0'=k5^post_50, keA^0'=keA^post_50, keR^0'=keR^post_50, ntStatus^0'=ntStatus^post_50, pIrb^0'=pIrb^post_50, phi_io_compl^0'=phi_io_compl^post_50, phi_nSUC_ret^0'=phi_nSUC_ret^post_50, prevCancel^0'=prevCancel^post_50, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_50, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_50, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_50, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_50, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_50, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_50, [ k4^0<=0 && i___04040^post_50==Irql^0 && keR^1_4_1==1 && keR^post_50==0 && keA^1_5==1 && keA^post_50==0 && __rho_12_^post_50==__rho_12_^post_50 && k5^post_50==__rho_12_^post_50 && AsyncAddressData^0==AsyncAddressData^post_50 && BusResetIrp^0==BusResetIrp^post_50 && CromData^0==CromData^post_50 && DeviceObject^0==DeviceObject^post_50 && Irp^0==Irp^post_50 && Irql^0==Irql^post_50 && IsochDetachData^0==IsochDetachData^post_50 && IsochResourceData^0==IsochResourceData^post_50 && ResourceIrp^0==ResourceIrp^post_50 && StackSize^0==StackSize^post_50 && __rho_10_^0==__rho_10_^post_50 && __rho_11_^0==__rho_11_^post_50 && __rho_1_^0==__rho_1_^post_50 && __rho_2_^0==__rho_2_^post_50 && __rho_3_^0==__rho_3_^post_50 && __rho_4_^0==__rho_4_^post_50 && __rho_5_^0==__rho_5_^post_50 && __rho_666_^0==__rho_666_^post_50 && __rho_7_^0==__rho_7_^post_50 && __rho_8_^0==__rho_8_^post_50 && __rho_9_^0==__rho_9_^post_50 && a11^0==a11^post_50 && a1818^0==a1818^post_50 && a2525^0==a2525^post_50 && a2828^0==a2828^post_50 && a3131^0==a3131^post_50 && a3232^0==a3232^post_50 && a3434^0==a3434^post_50 && a3737^0==a3737^post_50 && a3838^0==a3838^post_50 && a4343^0==a4343^post_50 && a4545^0==a4545^post_50 && a77^0==a77^post_50 && b22^0==b22^post_50 && b2626^0==b2626^post_50 && b2929^0==b2929^post_50 && b3333^0==b3333^post_50 && b3535^0==b3535^post_50 && i^0==i^post_50 && i___01313^0==i___01313^post_50 && i___01717^0==i___01717^post_50 && i___02020^0==i___02020^post_50 && i___02424^0==i___02424^post_50 && i___04747^0==i___04747^post_50 && i___099^0==i___099^post_50 && ioA^0==ioA^post_50 && ioR^0==ioR^post_50 && k1^0==k1^post_50 && k2^0==k2^post_50 && k3^0==k3^post_50 && k4^0==k4^post_50 && ntStatus^0==ntStatus^post_50 && pIrb^0==pIrb^post_50 && phi_io_compl^0==phi_io_compl^post_50 && phi_nSUC_ret^0==phi_nSUC_ret^post_50 && prevCancel^0==prevCancel^post_50 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_50 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_50 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_50 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_50 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_50 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_50 ], cost: 1
     50: l17 -> l32 : AsyncAddressData^0'=AsyncAddressData^post_51, BusResetIrp^0'=BusResetIrp^post_51, CromData^0'=CromData^post_51, DeviceObject^0'=DeviceObject^post_51, Irp^0'=Irp^post_51, Irql^0'=Irql^post_51, IsochDetachData^0'=IsochDetachData^post_51, IsochResourceData^0'=IsochResourceData^post_51, ResourceIrp^0'=ResourceIrp^post_51, StackSize^0'=StackSize^post_51, __rho_10_^0'=__rho_10_^post_51, __rho_11_^0'=__rho_11_^post_51, __rho_12_^0'=__rho_12_^post_51, __rho_1_^0'=__rho_1_^post_51, __rho_2_^0'=__rho_2_^post_51, __rho_3_^0'=__rho_3_^post_51, __rho_4_^0'=__rho_4_^post_51, __rho_5_^0'=__rho_5_^post_51, __rho_666_^0'=__rho_666_^post_51, __rho_7_^0'=__rho_7_^post_51, __rho_8_^0'=__rho_8_^post_51, __rho_9_^0'=__rho_9_^post_51, a11^0'=a11^post_51, a1818^0'=a1818^post_51, a2525^0'=a2525^post_51, a2828^0'=a2828^post_51, a3131^0'=a3131^post_51, a3232^0'=a3232^post_51, a3434^0'=a3434^post_51, a3737^0'=a3737^post_51, a3838^0'=a3838^post_51, a4343^0'=a4343^post_51, a4545^0'=a4545^post_51, a77^0'=a77^post_51, b22^0'=b22^post_51, b2626^0'=b2626^post_51, b2929^0'=b2929^post_51, b3333^0'=b3333^post_51, b3535^0'=b3535^post_51, i^0'=i^post_51, i___01313^0'=i___01313^post_51, i___01717^0'=i___01717^post_51, i___02020^0'=i___02020^post_51, i___02424^0'=i___02424^post_51, i___04040^0'=i___04040^post_51, i___04747^0'=i___04747^post_51, i___099^0'=i___099^post_51, ioA^0'=ioA^post_51, ioR^0'=ioR^post_51, k1^0'=k1^post_51, k2^0'=k2^post_51, k3^0'=k3^post_51, k4^0'=k4^post_51, k5^0'=k5^post_51, keA^0'=keA^post_51, keR^0'=keR^post_51, ntStatus^0'=ntStatus^post_51, pIrb^0'=pIrb^post_51, phi_io_compl^0'=phi_io_compl^post_51, phi_nSUC_ret^0'=phi_nSUC_ret^post_51, prevCancel^0'=prevCancel^post_51, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_51, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_51, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_51, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_51, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_51, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_51, [ 1<=k4^0 && IsochResourceData^post_51==IsochResourceData^post_51 && k4^post_51==-1+k4^0 && i___02424^post_51==Irql^0 && keR^1_4_2==1 && keR^post_51==0 && AsyncAddressData^0==AsyncAddressData^post_51 && BusResetIrp^0==BusResetIrp^post_51 && CromData^0==CromData^post_51 && DeviceObject^0==DeviceObject^post_51 && Irp^0==Irp^post_51 && Irql^0==Irql^post_51 && IsochDetachData^0==IsochDetachData^post_51 && ResourceIrp^0==ResourceIrp^post_51 && StackSize^0==StackSize^post_51 && __rho_10_^0==__rho_10_^post_51 && __rho_11_^0==__rho_11_^post_51 && __rho_12_^0==__rho_12_^post_51 && __rho_1_^0==__rho_1_^post_51 && __rho_2_^0==__rho_2_^post_51 && __rho_3_^0==__rho_3_^post_51 && __rho_4_^0==__rho_4_^post_51 && __rho_5_^0==__rho_5_^post_51 && __rho_666_^0==__rho_666_^post_51 && __rho_7_^0==__rho_7_^post_51 && __rho_8_^0==__rho_8_^post_51 && __rho_9_^0==__rho_9_^post_51 && a11^0==a11^post_51 && a1818^0==a1818^post_51 && a2525^0==a2525^post_51 && a2828^0==a2828^post_51 && a3131^0==a3131^post_51 && a3232^0==a3232^post_51 && a3434^0==a3434^post_51 && a3737^0==a3737^post_51 && a3838^0==a3838^post_51 && a4343^0==a4343^post_51 && a4545^0==a4545^post_51 && a77^0==a77^post_51 && b22^0==b22^post_51 && b2626^0==b2626^post_51 && b2929^0==b2929^post_51 && b3333^0==b3333^post_51 && b3535^0==b3535^post_51 && i^0==i^post_51 && i___01313^0==i___01313^post_51 && i___01717^0==i___01717^post_51 && i___02020^0==i___02020^post_51 && i___04040^0==i___04040^post_51 && i___04747^0==i___04747^post_51 && i___099^0==i___099^post_51 && ioA^0==ioA^post_51 && ioR^0==ioR^post_51 && k1^0==k1^post_51 && k2^0==k2^post_51 && k3^0==k3^post_51 && k5^0==k5^post_51 && keA^0==keA^post_51 && ntStatus^0==ntStatus^post_51 && pIrb^0==pIrb^post_51 && phi_io_compl^0==phi_io_compl^post_51 && phi_nSUC_ret^0==phi_nSUC_ret^post_51 && prevCancel^0==prevCancel^post_51 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_51 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_51 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_51 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_51 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_51 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_51 ], cost: 1
     24: l18 -> l10 : [ CromData^0<=0 ], cost: 1
     25: l18 -> l16 : __rho_2_^0'=__rho_2_^post_26, [ 1<=CromData^0 ], cost: 1
     28: l19 -> l20 : [], cost: 1
     37: l20 -> l19 : BusResetIrp^0'=BusResetIrp^post_38, a4343^0'=0, a4545^0'=BusResetIrp^post_38, k5^0'=-1+k5^0, phi_io_compl^0'=1, prevCancel^0'=0, ret_IoSetCancelRoutine4444^0'=0, [ 1<=k5^0 ], cost: 1
     38: l20 -> l26 : i___04747^0'=Irql^0, keR^0'=0, [ k5^0<=0 ], cost: 1
     29: l21 -> l10 : __rho_5_^0'=__rho_5_^post_30, k1^0'=__rho_5_^post_30, keA^0'=0, ntStatus^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, [], cost: 1
     31: l24 -> l25 : phi_nSUC_ret^0'=1, [], cost: 1
     35: l25 -> l27 : [], cost: 1
     32: l26 -> l25 : [ -2+ntStatus^0==0 ], cost: 1
     33: l26 -> l24 : [ 3<=ntStatus^0 ], cost: 1
     34: l26 -> l24 : [ 1+ntStatus^0<=2 ], cost: 1
     36: l27 -> l25 : [], cost: 1
     39: l28 -> l21 : [ __rho_1_^0<=0 ], cost: 1
     40: l28 -> l21 : a11^0'=DeviceObject^0, b22^0'=Irp^0, ntStatus^0'=0, ret_t1394Diag_PnpStopDevice33^0'=0, [ 1<=__rho_1_^0 ], cost: 1
     41: l29 -> l1 : a3232^0'=pIrb^0, a3434^0'=ResourceIrp^0, a3737^0'=pIrb^0, a3838^0'=ResourceIrp^0, b3333^0'=0, b3535^0'=pIrb^0, ntStatus^0'=0, ret_t1394_SubmitIrpSynch3636^0'=0, [ 1<=pIrb^0 ], cost: 1
     42: l29 -> l1 : a3131^0'=ResourceIrp^0, [ pIrb^0<=0 ], cost: 1
     43: l30 -> l29 : a2828^0'=1, b2929^0'=0, pIrb^0'=0, ret_ExAllocatePool3030^0'=0, [], cost: 1
     44: l31 -> l30 : [ 1<=ResourceIrp^0 ], cost: 1
     45: l31 -> l30 : [ 1+ResourceIrp^0<=0 ], cost: 1
     46: l31 -> l1 : [ ResourceIrp^0==0 ], cost: 1
     47: l32 -> l1 : [ IsochResourceData^0<=0 ], cost: 1
     48: l32 -> l31 : ResourceIrp^0'=0, StackSize^0'=a2525^post_49, a2525^0'=a2525^post_49, b2626^0'=0, pIrb^0'=pIrb^post_49, ret_IoAllocateIrp2727^0'=0, [ 1<=IsochResourceData^0 ], cost: 1
     51: l33 -> l28 : AsyncAddressData^0'=AsyncAddressData^post_52, BusResetIrp^0'=BusResetIrp^post_52, CromData^0'=CromData^post_52, DeviceObject^0'=DeviceObject^post_52, Irp^0'=Irp^post_52, Irql^0'=Irql^post_52, IsochDetachData^0'=IsochDetachData^post_52, IsochResourceData^0'=IsochResourceData^post_52, ResourceIrp^0'=ResourceIrp^post_52, StackSize^0'=StackSize^post_52, __rho_10_^0'=__rho_10_^post_52, __rho_11_^0'=__rho_11_^post_52, __rho_12_^0'=__rho_12_^post_52, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_52, __rho_3_^0'=__rho_3_^post_52, __rho_4_^0'=__rho_4_^post_52, __rho_5_^0'=__rho_5_^post_52, __rho_666_^0'=__rho_666_^post_52, __rho_7_^0'=__rho_7_^post_52, __rho_8_^0'=__rho_8_^post_52, __rho_9_^0'=__rho_9_^post_52, a11^0'=a11^post_52, a1818^0'=a1818^post_52, a2525^0'=a2525^post_52, a2828^0'=a2828^post_52, a3131^0'=a3131^post_52, a3232^0'=a3232^post_52, a3434^0'=a3434^post_52, a3737^0'=a3737^post_52, a3838^0'=a3838^post_52, a4343^0'=a4343^post_52, a4545^0'=a4545^post_52, a77^0'=a77^post_52, b22^0'=b22^post_52, b2626^0'=b2626^post_52, b2929^0'=b2929^post_52, b3333^0'=b3333^post_52, b3535^0'=b3535^post_52, i^0'=i^post_52, i___01313^0'=i___01313^post_52, i___01717^0'=i___01717^post_52, i___02020^0'=i___02020^post_52, i___02424^0'=i___02424^post_52, i___04040^0'=i___04040^post_52, i___04747^0'=i___04747^post_52, i___099^0'=i___099^post_52, ioA^0'=ioA^post_52, ioR^0'=ioR^post_52, k1^0'=k1^post_52, k2^0'=k2^post_52, k3^0'=k3^post_52, k4^0'=k4^post_52, k5^0'=k5^post_52, keA^0'=keA^post_52, keR^0'=keR^post_52, ntStatus^0'=ntStatus^post_52, pIrb^0'=pIrb^post_52, phi_io_compl^0'=phi_io_compl^post_52, phi_nSUC_ret^0'=phi_nSUC_ret^post_52, prevCancel^0'=prevCancel^post_52, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_52, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_52, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_52, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_52, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_52, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_52, [ ioR^post_52==0 && ioA^post_52==ioR^post_52 && keR^post_52==ioA^post_52 && keA^post_52==keR^post_52 && phi_nSUC_ret^post_52==0 && phi_io_compl^post_52==0 && __rho_666_^post_52==__rho_666_^post_52 && __rho_1_^post_52==__rho_1_^post_52 && AsyncAddressData^0==AsyncAddressData^post_52 && BusResetIrp^0==BusResetIrp^post_52 && CromData^0==CromData^post_52 && DeviceObject^0==DeviceObject^post_52 && Irp^0==Irp^post_52 && Irql^0==Irql^post_52 && IsochDetachData^0==IsochDetachData^post_52 && IsochResourceData^0==IsochResourceData^post_52 && ResourceIrp^0==ResourceIrp^post_52 && StackSize^0==StackSize^post_52 && __rho_10_^0==__rho_10_^post_52 && __rho_11_^0==__rho_11_^post_52 && __rho_12_^0==__rho_12_^post_52 && __rho_2_^0==__rho_2_^post_52 && __rho_3_^0==__rho_3_^post_52 && __rho_4_^0==__rho_4_^post_52 && __rho_5_^0==__rho_5_^post_52 && __rho_7_^0==__rho_7_^post_52 && __rho_8_^0==__rho_8_^post_52 && __rho_9_^0==__rho_9_^post_52 && a11^0==a11^post_52 && a1818^0==a1818^post_52 && a2525^0==a2525^post_52 && a2828^0==a2828^post_52 && a3131^0==a3131^post_52 && a3232^0==a3232^post_52 && a3434^0==a3434^post_52 && a3737^0==a3737^post_52 && a3838^0==a3838^post_52 && a4343^0==a4343^post_52 && a4545^0==a4545^post_52 && a77^0==a77^post_52 && b22^0==b22^post_52 && b2626^0==b2626^post_52 && b2929^0==b2929^post_52 && b3333^0==b3333^post_52 && b3535^0==b3535^post_52 && i^0==i^post_52 && i___01313^0==i___01313^post_52 && i___01717^0==i___01717^post_52 && i___02020^0==i___02020^post_52 && i___02424^0==i___02424^post_52 && i___04040^0==i___04040^post_52 && i___04747^0==i___04747^post_52 && i___099^0==i___099^post_52 && k1^0==k1^post_52 && k2^0==k2^post_52 && k3^0==k3^post_52 && k4^0==k4^post_52 && k5^0==k5^post_52 && ntStatus^0==ntStatus^post_52 && pIrb^0==pIrb^post_52 && prevCancel^0==prevCancel^post_52 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_52 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_52 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_52 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_52 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_52 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_52 ], cost: 1
     52: l34 -> l33 : AsyncAddressData^0'=AsyncAddressData^post_53, BusResetIrp^0'=BusResetIrp^post_53, CromData^0'=CromData^post_53, DeviceObject^0'=DeviceObject^post_53, Irp^0'=Irp^post_53, Irql^0'=Irql^post_53, IsochDetachData^0'=IsochDetachData^post_53, IsochResourceData^0'=IsochResourceData^post_53, ResourceIrp^0'=ResourceIrp^post_53, StackSize^0'=StackSize^post_53, __rho_10_^0'=__rho_10_^post_53, __rho_11_^0'=__rho_11_^post_53, __rho_12_^0'=__rho_12_^post_53, __rho_1_^0'=__rho_1_^post_53, __rho_2_^0'=__rho_2_^post_53, __rho_3_^0'=__rho_3_^post_53, __rho_4_^0'=__rho_4_^post_53, __rho_5_^0'=__rho_5_^post_53, __rho_666_^0'=__rho_666_^post_53, __rho_7_^0'=__rho_7_^post_53, __rho_8_^0'=__rho_8_^post_53, __rho_9_^0'=__rho_9_^post_53, a11^0'=a11^post_53, a1818^0'=a1818^post_53, a2525^0'=a2525^post_53, a2828^0'=a2828^post_53, a3131^0'=a3131^post_53, a3232^0'=a3232^post_53, a3434^0'=a3434^post_53, a3737^0'=a3737^post_53, a3838^0'=a3838^post_53, a4343^0'=a4343^post_53, a4545^0'=a4545^post_53, a77^0'=a77^post_53, b22^0'=b22^post_53, b2626^0'=b2626^post_53, b2929^0'=b2929^post_53, b3333^0'=b3333^post_53, b3535^0'=b3535^post_53, i^0'=i^post_53, i___01313^0'=i___01313^post_53, i___01717^0'=i___01717^post_53, i___02020^0'=i___02020^post_53, i___02424^0'=i___02424^post_53, i___04040^0'=i___04040^post_53, i___04747^0'=i___04747^post_53, i___099^0'=i___099^post_53, ioA^0'=ioA^post_53, ioR^0'=ioR^post_53, k1^0'=k1^post_53, k2^0'=k2^post_53, k3^0'=k3^post_53, k4^0'=k4^post_53, k5^0'=k5^post_53, keA^0'=keA^post_53, keR^0'=keR^post_53, ntStatus^0'=ntStatus^post_53, pIrb^0'=pIrb^post_53, phi_io_compl^0'=phi_io_compl^post_53, phi_nSUC_ret^0'=phi_nSUC_ret^post_53, prevCancel^0'=prevCancel^post_53, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_53, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_53, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_53, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_53, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_53, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_53, [ AsyncAddressData^0==AsyncAddressData^post_53 && BusResetIrp^0==BusResetIrp^post_53 && CromData^0==CromData^post_53 && DeviceObject^0==DeviceObject^post_53 && Irp^0==Irp^post_53 && Irql^0==Irql^post_53 && IsochDetachData^0==IsochDetachData^post_53 && IsochResourceData^0==IsochResourceData^post_53 && ResourceIrp^0==ResourceIrp^post_53 && StackSize^0==StackSize^post_53 && __rho_10_^0==__rho_10_^post_53 && __rho_11_^0==__rho_11_^post_53 && __rho_12_^0==__rho_12_^post_53 && __rho_1_^0==__rho_1_^post_53 && __rho_2_^0==__rho_2_^post_53 && __rho_3_^0==__rho_3_^post_53 && __rho_4_^0==__rho_4_^post_53 && __rho_5_^0==__rho_5_^post_53 && __rho_666_^0==__rho_666_^post_53 && __rho_7_^0==__rho_7_^post_53 && __rho_8_^0==__rho_8_^post_53 && __rho_9_^0==__rho_9_^post_53 && a11^0==a11^post_53 && a1818^0==a1818^post_53 && a2525^0==a2525^post_53 && a2828^0==a2828^post_53 && a3131^0==a3131^post_53 && a3232^0==a3232^post_53 && a3434^0==a3434^post_53 && a3737^0==a3737^post_53 && a3838^0==a3838^post_53 && a4343^0==a4343^post_53 && a4545^0==a4545^post_53 && a77^0==a77^post_53 && b22^0==b22^post_53 && b2626^0==b2626^post_53 && b2929^0==b2929^post_53 && b3333^0==b3333^post_53 && b3535^0==b3535^post_53 && i^0==i^post_53 && i___01313^0==i___01313^post_53 && i___01717^0==i___01717^post_53 && i___02020^0==i___02020^post_53 && i___02424^0==i___02424^post_53 && i___04040^0==i___04040^post_53 && i___04747^0==i___04747^post_53 && i___099^0==i___099^post_53 && ioA^0==ioA^post_53 && ioR^0==ioR^post_53 && k1^0==k1^post_53 && k2^0==k2^post_53 && k3^0==k3^post_53 && k4^0==k4^post_53 && k5^0==k5^post_53 && keA^0==keA^post_53 && keR^0==keR^post_53 && ntStatus^0==ntStatus^post_53 && pIrb^0==pIrb^post_53 && phi_io_compl^0==phi_io_compl^post_53 && phi_nSUC_ret^0==phi_nSUC_ret^post_53 && prevCancel^0==prevCancel^post_53 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_53 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_53 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_53 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_53 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_53 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_53 ], cost: 1

### Simplification by acceleration and chaining ###

Eliminated locations (on linear paths):
   Start location: l34
      0: l0 -> l1 : __rho_11_^0'=__rho_11_^post_1, i___02020^0'=Irql^0, k4^0'=__rho_11_^post_1, keR^0'=0, [ k3^0<=0 ], cost: 1
      1: l0 -> l2 : IsochDetachData^0'=IsochDetachData^post_2, a1818^0'=IsochDetachData^post_2, i^0'=i^post_2, i___01717^0'=Irql^0, k3^0'=-1+k3^0, keR^0'=0, [ 1<=k3^0 ], cost: 1
     23: l1 -> l17 : keA^0'=0, [], cost: 1
     16: l2 -> l0 : keA^0'=0, [], cost: 1
      2: l3 -> l4 : [ AsyncAddressData^0<=0 ], cost: 1
      3: l3 -> l4 : [ 1<=AsyncAddressData^0 ], cost: 1
     15: l4 -> l12 : [], cost: 1
      4: l5 -> l3 : [ __rho_9_^0<=0 ], cost: 1
      5: l5 -> l3 : [ 1<=__rho_9_^0 ], cost: 1
      6: l6 -> l5 : __rho_9_^0'=__rho_9_^post_7, [], cost: 1
      7: l7 -> l6 : [ __rho_8_^0<=0 ], cost: 1
      8: l7 -> l6 : [ 1<=__rho_8_^0 ], cost: 1
      9: l8 -> l7 : __rho_8_^0'=__rho_8_^post_10, [], cost: 1
     10: l9 -> l8 : [ __rho_7_^0<=0 ], cost: 1
     11: l9 -> l8 : [ 1<=__rho_7_^0 ], cost: 1
     12: l10 -> l11 : [], cost: 1
     26: l11 -> l18 : CromData^0'=CromData^post_27, k1^0'=-1+k1^0, [ 1<=k1^0 ], cost: 1
     27: l11 -> l4 : __rho_4_^0'=__rho_4_^post_28, i___099^0'=Irql^0, k2^0'=__rho_4_^post_28, keA^0'=0, keR^0'=0, [ k1^0<=0 ], cost: 1
     13: l12 -> l9 : AsyncAddressData^0'=AsyncAddressData^post_14, __rho_7_^0'=__rho_7_^post_14, k2^0'=-1+k2^0, [ 1<=k2^0 ], cost: 1
     14: l12 -> l2 : __rho_10_^0'=__rho_10_^post_15, i___01313^0'=Irql^0, k3^0'=__rho_10_^post_15, keR^0'=0, [ k2^0<=0 ], cost: 1
     17: l13 -> l10 : a77^0'=CromData^0, [], cost: 1
     18: l14 -> l13 : [ __rho_3_^0<=0 ], cost: 1
     19: l14 -> l13 : [ 1<=__rho_3_^0 ], cost: 1
     20: l15 -> l14 : __rho_3_^0'=__rho_3_^post_21, [], cost: 1
     21: l16 -> l15 : [ __rho_2_^0<=0 ], cost: 1
     22: l16 -> l15 : [ 1<=__rho_2_^0 ], cost: 1
     49: l17 -> l19 : AsyncAddressData^0'=AsyncAddressData^post_50, BusResetIrp^0'=BusResetIrp^post_50, CromData^0'=CromData^post_50, DeviceObject^0'=DeviceObject^post_50, Irp^0'=Irp^post_50, Irql^0'=Irql^post_50, IsochDetachData^0'=IsochDetachData^post_50, IsochResourceData^0'=IsochResourceData^post_50, ResourceIrp^0'=ResourceIrp^post_50, StackSize^0'=StackSize^post_50, __rho_10_^0'=__rho_10_^post_50, __rho_11_^0'=__rho_11_^post_50, __rho_12_^0'=__rho_12_^post_50, __rho_1_^0'=__rho_1_^post_50, __rho_2_^0'=__rho_2_^post_50, __rho_3_^0'=__rho_3_^post_50, __rho_4_^0'=__rho_4_^post_50, __rho_5_^0'=__rho_5_^post_50, __rho_666_^0'=__rho_666_^post_50, __rho_7_^0'=__rho_7_^post_50, __rho_8_^0'=__rho_8_^post_50, __rho_9_^0'=__rho_9_^post_50, a11^0'=a11^post_50, a1818^0'=a1818^post_50, a2525^0'=a2525^post_50, a2828^0'=a2828^post_50, a3131^0'=a3131^post_50, a3232^0'=a3232^post_50, a3434^0'=a3434^post_50, a3737^0'=a3737^post_50, a3838^0'=a3838^post_50, a4343^0'=a4343^post_50, a4545^0'=a4545^post_50, a77^0'=a77^post_50, b22^0'=b22^post_50, b2626^0'=b2626^post_50, b2929^0'=b2929^post_50, b3333^0'=b3333^post_50, b3535^0'=b3535^post_50, i^0'=i^post_50, i___01313^0'=i___01313^post_50, i___01717^0'=i___01717^post_50, i___02020^0'=i___02020^post_50, i___02424^0'=i___02424^post_50, i___04040^0'=i___04040^post_50, i___04747^0'=i___04747^post_50, i___099^0'=i___099^post_50, ioA^0'=ioA^post_50, ioR^0'=ioR^post_50, k1^0'=k1^post_50, k2^0'=k2^post_50, k3^0'=k3^post_50, k4^0'=k4^post_50, k5^0'=k5^post_50, keA^0'=keA^post_50, keR^0'=keR^post_50, ntStatus^0'=ntStatus^post_50, pIrb^0'=pIrb^post_50, phi_io_compl^0'=phi_io_compl^post_50, phi_nSUC_ret^0'=phi_nSUC_ret^post_50, prevCancel^0'=prevCancel^post_50, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_50, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_50, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_50, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_50, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_50, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_50, [ k4^0<=0 && i___04040^post_50==Irql^0 && keR^1_4_1==1 && keR^post_50==0 && keA^1_5==1 && keA^post_50==0 && __rho_12_^post_50==__rho_12_^post_50 && k5^post_50==__rho_12_^post_50 && AsyncAddressData^0==AsyncAddressData^post_50 && BusResetIrp^0==BusResetIrp^post_50 && CromData^0==CromData^post_50 && DeviceObject^0==DeviceObject^post_50 && Irp^0==Irp^post_50 && Irql^0==Irql^post_50 && IsochDetachData^0==IsochDetachData^post_50 && IsochResourceData^0==IsochResourceData^post_50 && ResourceIrp^0==ResourceIrp^post_50 && StackSize^0==StackSize^post_50 && __rho_10_^0==__rho_10_^post_50 && __rho_11_^0==__rho_11_^post_50 && __rho_1_^0==__rho_1_^post_50 && __rho_2_^0==__rho_2_^post_50 && __rho_3_^0==__rho_3_^post_50 && __rho_4_^0==__rho_4_^post_50 && __rho_5_^0==__rho_5_^post_50 && __rho_666_^0==__rho_666_^post_50 && __rho_7_^0==__rho_7_^post_50 && __rho_8_^0==__rho_8_^post_50 && __rho_9_^0==__rho_9_^post_50 && a11^0==a11^post_50 && a1818^0==a1818^post_50 && a2525^0==a2525^post_50 && a2828^0==a2828^post_50 && a3131^0==a3131^post_50 && a3232^0==a3232^post_50 && a3434^0==a3434^post_50 && a3737^0==a3737^post_50 && a3838^0==a3838^post_50 && a4343^0==a4343^post_50 && a4545^0==a4545^post_50 && a77^0==a77^post_50 && b22^0==b22^post_50 && b2626^0==b2626^post_50 && b2929^0==b2929^post_50 && b3333^0==b3333^post_50 && b3535^0==b3535^post_50 && i^0==i^post_50 && i___01313^0==i___01313^post_50 && i___01717^0==i___01717^post_50 && i___02020^0==i___02020^post_50 && i___02424^0==i___02424^post_50 && i___04747^0==i___04747^post_50 && i___099^0==i___099^post_50 && ioA^0==ioA^post_50 && ioR^0==ioR^post_50 && k1^0==k1^post_50 && k2^0==k2^post_50 && k3^0==k3^post_50 && k4^0==k4^post_50 && ntStatus^0==ntStatus^post_50 && pIrb^0==pIrb^post_50 && phi_io_compl^0==phi_io_compl^post_50 && phi_nSUC_ret^0==phi_nSUC_ret^post_50 && prevCancel^0==prevCancel^post_50 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_50 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_50 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_50 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_50 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_50 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_50 ], cost: 1
     50: l17 -> l32 : AsyncAddressData^0'=AsyncAddressData^post_51, BusResetIrp^0'=BusResetIrp^post_51, CromData^0'=CromData^post_51, DeviceObject^0'=DeviceObject^post_51, Irp^0'=Irp^post_51, Irql^0'=Irql^post_51, IsochDetachData^0'=IsochDetachData^post_51, IsochResourceData^0'=IsochResourceData^post_51, ResourceIrp^0'=ResourceIrp^post_51, StackSize^0'=StackSize^post_51, __rho_10_^0'=__rho_10_^post_51, __rho_11_^0'=__rho_11_^post_51, __rho_12_^0'=__rho_12_^post_51, __rho_1_^0'=__rho_1_^post_51, __rho_2_^0'=__rho_2_^post_51, __rho_3_^0'=__rho_3_^post_51, __rho_4_^0'=__rho_4_^post_51, __rho_5_^0'=__rho_5_^post_51, __rho_666_^0'=__rho_666_^post_51, __rho_7_^0'=__rho_7_^post_51, __rho_8_^0'=__rho_8_^post_51, __rho_9_^0'=__rho_9_^post_51, a11^0'=a11^post_51, a1818^0'=a1818^post_51, a2525^0'=a2525^post_51, a2828^0'=a2828^post_51, a3131^0'=a3131^post_51, a3232^0'=a3232^post_51, a3434^0'=a3434^post_51, a3737^0'=a3737^post_51, a3838^0'=a3838^post_51, a4343^0'=a4343^post_51, a4545^0'=a4545^post_51, a77^0'=a77^post_51, b22^0'=b22^post_51, b2626^0'=b2626^post_51, b2929^0'=b2929^post_51, b3333^0'=b3333^post_51, b3535^0'=b3535^post_51, i^0'=i^post_51, i___01313^0'=i___01313^post_51, i___01717^0'=i___01717^post_51, i___02020^0'=i___02020^post_51, i___02424^0'=i___02424^post_51, i___04040^0'=i___04040^post_51, i___04747^0'=i___04747^post_51, i___099^0'=i___099^post_51, ioA^0'=ioA^post_51, ioR^0'=ioR^post_51, k1^0'=k1^post_51, k2^0'=k2^post_51, k3^0'=k3^post_51, k4^0'=k4^post_51, k5^0'=k5^post_51, keA^0'=keA^post_51, keR^0'=keR^post_51, ntStatus^0'=ntStatus^post_51, pIrb^0'=pIrb^post_51, phi_io_compl^0'=phi_io_compl^post_51, phi_nSUC_ret^0'=phi_nSUC_ret^post_51, prevCancel^0'=prevCancel^post_51, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_51, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_51, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_51, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_51, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_51, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_51, [ 1<=k4^0 && IsochResourceData^post_51==IsochResourceData^post_51 && k4^post_51==-1+k4^0 && i___02424^post_51==Irql^0 && keR^1_4_2==1 && keR^post_51==0 && AsyncAddressData^0==AsyncAddressData^post_51 && BusResetIrp^0==BusResetIrp^post_51 && CromData^0==CromData^post_51 && DeviceObject^0==DeviceObject^post_51 && Irp^0==Irp^post_51 && Irql^0==Irql^post_51 && IsochDetachData^0==IsochDetachData^post_51 && ResourceIrp^0==ResourceIrp^post_51 && StackSize^0==StackSize^post_51 && __rho_10_^0==__rho_10_^post_51 && __rho_11_^0==__rho_11_^post_51 && __rho_12_^0==__rho_12_^post_51 && __rho_1_^0==__rho_1_^post_51 && __rho_2_^0==__rho_2_^post_51 && __rho_3_^0==__rho_3_^post_51 && __rho_4_^0==__rho_4_^post_51 && __rho_5_^0==__rho_5_^post_51 && __rho_666_^0==__rho_666_^post_51 && __rho_7_^0==__rho_7_^post_51 && __rho_8_^0==__rho_8_^post_51 && __rho_9_^0==__rho_9_^post_51 && a11^0==a11^post_51 && a1818^0==a1818^post_51 && a2525^0==a2525^post_51 && a2828^0==a2828^post_51 && a3131^0==a3131^post_51 && a3232^0==a3232^post_51 && a3434^0==a3434^post_51 && a3737^0==a3737^post_51 && a3838^0==a3838^post_51 && a4343^0==a4343^post_51 && a4545^0==a4545^post_51 && a77^0==a77^post_51 && b22^0==b22^post_51 && b2626^0==b2626^post_51 && b2929^0==b2929^post_51 && b3333^0==b3333^post_51 && b3535^0==b3535^post_51 && i^0==i^post_51 && i___01313^0==i___01313^post_51 && i___01717^0==i___01717^post_51 && i___02020^0==i___02020^post_51 && i___04040^0==i___04040^post_51 && i___04747^0==i___04747^post_51 && i___099^0==i___099^post_51 && ioA^0==ioA^post_51 && ioR^0==ioR^post_51 && k1^0==k1^post_51 && k2^0==k2^post_51 && k3^0==k3^post_51 && k5^0==k5^post_51 && keA^0==keA^post_51 && ntStatus^0==ntStatus^post_51 && pIrb^0==pIrb^post_51 && phi_io_compl^0==phi_io_compl^post_51 && phi_nSUC_ret^0==phi_nSUC_ret^post_51 && prevCancel^0==prevCancel^post_51 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_51 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_51 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_51 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_51 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_51 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_51 ], cost: 1
     24: l18 -> l10 : [ CromData^0<=0 ], cost: 1
     25: l18 -> l16 : __rho_2_^0'=__rho_2_^post_26, [ 1<=CromData^0 ], cost: 1
     28: l19 -> l20 : [], cost: 1
     37: l20 -> l19 : BusResetIrp^0'=BusResetIrp^post_38, a4343^0'=0, a4545^0'=BusResetIrp^post_38, k5^0'=-1+k5^0, phi_io_compl^0'=1, prevCancel^0'=0, ret_IoSetCancelRoutine4444^0'=0, [ 1<=k5^0 ], cost: 1
     38: l20 -> l26 : i___04747^0'=Irql^0, keR^0'=0, [ k5^0<=0 ], cost: 1
     29: l21 -> l10 : __rho_5_^0'=__rho_5_^post_30, k1^0'=__rho_5_^post_30, keA^0'=0, ntStatus^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, [], cost: 1
     31: l24 -> l25 : phi_nSUC_ret^0'=1, [], cost: 1
     54: l25 -> l25 : [], cost: 2
     32: l26 -> l25 : [ -2+ntStatus^0==0 ], cost: 1
     33: l26 -> l24 : [ 3<=ntStatus^0 ], cost: 1
     34: l26 -> l24 : [ 1+ntStatus^0<=2 ], cost: 1
     39: l28 -> l21 : [ __rho_1_^0<=0 ], cost: 1
     40: l28 -> l21 : a11^0'=DeviceObject^0, b22^0'=Irp^0, ntStatus^0'=0, ret_t1394Diag_PnpStopDevice33^0'=0, [ 1<=__rho_1_^0 ], cost: 1
     41: l29 -> l1 : a3232^0'=pIrb^0, a3434^0'=ResourceIrp^0, a3737^0'=pIrb^0, a3838^0'=ResourceIrp^0, b3333^0'=0, b3535^0'=pIrb^0, ntStatus^0'=0, ret_t1394_SubmitIrpSynch3636^0'=0, [ 1<=pIrb^0 ], cost: 1
     42: l29 -> l1 : a3131^0'=ResourceIrp^0, [ pIrb^0<=0 ], cost: 1
     43: l30 -> l29 : a2828^0'=1, b2929^0'=0, pIrb^0'=0, ret_ExAllocatePool3030^0'=0, [], cost: 1
     44: l31 -> l30 : [ 1<=ResourceIrp^0 ], cost: 1
     45: l31 -> l30 : [ 1+ResourceIrp^0<=0 ], cost: 1
     46: l31 -> l1 : [ ResourceIrp^0==0 ], cost: 1
     47: l32 -> l1 : [ IsochResourceData^0<=0 ], cost: 1
     48: l32 -> l31 : ResourceIrp^0'=0, StackSize^0'=a2525^post_49, a2525^0'=a2525^post_49, b2626^0'=0, pIrb^0'=pIrb^post_49, ret_IoAllocateIrp2727^0'=0, [ 1<=IsochResourceData^0 ], cost: 1
     53: l34 -> l28 : AsyncAddressData^0'=AsyncAddressData^post_52, BusResetIrp^0'=BusResetIrp^post_52, CromData^0'=CromData^post_52, DeviceObject^0'=DeviceObject^post_52, Irp^0'=Irp^post_52, Irql^0'=Irql^post_52, IsochDetachData^0'=IsochDetachData^post_52, IsochResourceData^0'=IsochResourceData^post_52, ResourceIrp^0'=ResourceIrp^post_52, StackSize^0'=StackSize^post_52, __rho_10_^0'=__rho_10_^post_52, __rho_11_^0'=__rho_11_^post_52, __rho_12_^0'=__rho_12_^post_52, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_52, __rho_3_^0'=__rho_3_^post_52, __rho_4_^0'=__rho_4_^post_52, __rho_5_^0'=__rho_5_^post_52, __rho_666_^0'=__rho_666_^post_52, __rho_7_^0'=__rho_7_^post_52, __rho_8_^0'=__rho_8_^post_52, __rho_9_^0'=__rho_9_^post_52, a11^0'=a11^post_52, a1818^0'=a1818^post_52, a2525^0'=a2525^post_52, a2828^0'=a2828^post_52, a3131^0'=a3131^post_52, a3232^0'=a3232^post_52, a3434^0'=a3434^post_52, a3737^0'=a3737^post_52, a3838^0'=a3838^post_52, a4343^0'=a4343^post_52, a4545^0'=a4545^post_52, a77^0'=a77^post_52, b22^0'=b22^post_52, b2626^0'=b2626^post_52, b2929^0'=b2929^post_52, b3333^0'=b3333^post_52, b3535^0'=b3535^post_52, i^0'=i^post_52, i___01313^0'=i___01313^post_52, i___01717^0'=i___01717^post_52, i___02020^0'=i___02020^post_52, i___02424^0'=i___02424^post_52, i___04040^0'=i___04040^post_52, i___04747^0'=i___04747^post_52, i___099^0'=i___099^post_52, ioA^0'=ioA^post_52, ioR^0'=ioR^post_52, k1^0'=k1^post_52, k2^0'=k2^post_52, k3^0'=k3^post_52, k4^0'=k4^post_52, k5^0'=k5^post_52, keA^0'=keA^post_52, keR^0'=keR^post_52, ntStatus^0'=ntStatus^post_52, pIrb^0'=pIrb^post_52, phi_io_compl^0'=phi_io_compl^post_52, phi_nSUC_ret^0'=phi_nSUC_ret^post_52, prevCancel^0'=prevCancel^post_52, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_52, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_52, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_52, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_52, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_52, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_52, [ AsyncAddressData^0==AsyncAddressData^post_53 && BusResetIrp^0==BusResetIrp^post_53 && CromData^0==CromData^post_53 && DeviceObject^0==DeviceObject^post_53 && Irp^0==Irp^post_53 && Irql^0==Irql^post_53 && IsochDetachData^0==IsochDetachData^post_53 && IsochResourceData^0==IsochResourceData^post_53 && ResourceIrp^0==ResourceIrp^post_53 && StackSize^0==StackSize^post_53 && __rho_10_^0==__rho_10_^post_53 && __rho_11_^0==__rho_11_^post_53 && __rho_12_^0==__rho_12_^post_53 && __rho_1_^0==__rho_1_^post_53 && __rho_2_^0==__rho_2_^post_53 && __rho_3_^0==__rho_3_^post_53 && __rho_4_^0==__rho_4_^post_53 && __rho_5_^0==__rho_5_^post_53 && __rho_666_^0==__rho_666_^post_53 && __rho_7_^0==__rho_7_^post_53 && __rho_8_^0==__rho_8_^post_53 && __rho_9_^0==__rho_9_^post_53 && a11^0==a11^post_53 && a1818^0==a1818^post_53 && a2525^0==a2525^post_53 && a2828^0==a2828^post_53 && a3131^0==a3131^post_53 && a3232^0==a3232^post_53 && a3434^0==a3434^post_53 && a3737^0==a3737^post_53 && a3838^0==a3838^post_53 && a4343^0==a4343^post_53 && a4545^0==a4545^post_53 && a77^0==a77^post_53 && b22^0==b22^post_53 && b2626^0==b2626^post_53 && b2929^0==b2929^post_53 && b3333^0==b3333^post_53 && b3535^0==b3535^post_53 && i^0==i^post_53 && i___01313^0==i___01313^post_53 && i___01717^0==i___01717^post_53 && i___02020^0==i___02020^post_53 && i___02424^0==i___02424^post_53 && i___04040^0==i___04040^post_53 && i___04747^0==i___04747^post_53 && i___099^0==i___099^post_53 && ioA^0==ioA^post_53 && ioR^0==ioR^post_53 && k1^0==k1^post_53 && k2^0==k2^post_53 && k3^0==k3^post_53 && k4^0==k4^post_53 && k5^0==k5^post_53 && keA^0==keA^post_53 && keR^0==keR^post_53 && ntStatus^0==ntStatus^post_53 && pIrb^0==pIrb^post_53 && phi_io_compl^0==phi_io_compl^post_53 && phi_nSUC_ret^0==phi_nSUC_ret^post_53 && prevCancel^0==prevCancel^post_53 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_53 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_53 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_53 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_53 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_53 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_53 && ioR^post_52==0 && ioA^post_52==ioR^post_52 && keR^post_52==ioA^post_52 && keA^post_52==keR^post_52 && phi_nSUC_ret^post_52==0 && phi_io_compl^post_52==0 && AsyncAddressData^post_53==AsyncAddressData^post_52 && BusResetIrp^post_53==BusResetIrp^post_52 && CromData^post_53==CromData^post_52 && DeviceObject^post_53==DeviceObject^post_52 && Irp^post_53==Irp^post_52 && Irql^post_53==Irql^post_52 && IsochDetachData^post_53==IsochDetachData^post_52 && IsochResourceData^post_53==IsochResourceData^post_52 && ResourceIrp^post_53==ResourceIrp^post_52 && StackSize^post_53==StackSize^post_52 && __rho_10_^post_53==__rho_10_^post_52 && __rho_11_^post_53==__rho_11_^post_52 && __rho_12_^post_53==__rho_12_^post_52 && __rho_2_^post_53==__rho_2_^post_52 && __rho_3_^post_53==__rho_3_^post_52 && __rho_4_^post_53==__rho_4_^post_52 && __rho_5_^post_53==__rho_5_^post_52 && __rho_7_^post_53==__rho_7_^post_52 && __rho_8_^post_53==__rho_8_^post_52 && __rho_9_^post_53==__rho_9_^post_52 && a11^post_53==a11^post_52 && a1818^post_53==a1818^post_52 && a2525^post_53==a2525^post_52 && a2828^post_53==a2828^post_52 && a3131^post_53==a3131^post_52 && a3232^post_53==a3232^post_52 && a3434^post_53==a3434^post_52 && a3737^post_53==a3737^post_52 && a3838^post_53==a3838^post_52 && a4343^post_53==a4343^post_52 && a4545^post_53==a4545^post_52 && a77^post_53==a77^post_52 && b22^post_53==b22^post_52 && b2626^post_53==b2626^post_52 && b2929^post_53==b2929^post_52 && b3333^post_53==b3333^post_52 && b3535^post_53==b3535^post_52 && i^post_53==i^post_52 && i___01313^post_53==i___01313^post_52 && i___01717^post_53==i___01717^post_52 && i___02020^post_53==i___02020^post_52 && i___02424^post_53==i___02424^post_52 && i___04040^post_53==i___04040^post_52 && i___04747^post_53==i___04747^post_52 && i___099^post_53==i___099^post_52 && k1^post_53==k1^post_52 && k2^post_53==k2^post_52 && k3^post_53==k3^post_52 && k4^post_53==k4^post_52 && k5^post_53==k5^post_52 && ntStatus^post_53==ntStatus^post_52 && pIrb^post_53==pIrb^post_52 && prevCancel^post_53==prevCancel^post_52 && ret_ExAllocatePool3030^post_53==ret_ExAllocatePool3030^post_52 && ret_IoAllocateIrp2727^post_53==ret_IoAllocateIrp2727^post_52 && ret_IoSetCancelRoutine4444^post_53==ret_IoSetCancelRoutine4444^post_52 && ret_IoSetDeviceInterfaceState44^post_53==ret_IoSetDeviceInterfaceState44^post_52 && ret_t1394Diag_PnpStopDevice33^post_53==ret_t1394Diag_PnpStopDevice33^post_52 && ret_t1394_SubmitIrpSynch3636^post_53==ret_t1394_SubmitIrpSynch3636^post_52 ], cost: 2

Accelerating simple loops of location 25.
   Accelerating the following rules:
     54: l25 -> l25 : [], cost: 2

   Accelerated rule 54 with non-termination, yielding the new rule 55.
[accelerate] Nesting with 0 inner and 0 outer candidates
   Removing the simple loops: 54.

Accelerated all simple loops using metering functions (where possible):
   Start location: l34
      0: l0 -> l1 : __rho_11_^0'=__rho_11_^post_1, i___02020^0'=Irql^0, k4^0'=__rho_11_^post_1, keR^0'=0, [ k3^0<=0 ], cost: 1
      1: l0 -> l2 : IsochDetachData^0'=IsochDetachData^post_2, a1818^0'=IsochDetachData^post_2, i^0'=i^post_2, i___01717^0'=Irql^0, k3^0'=-1+k3^0, keR^0'=0, [ 1<=k3^0 ], cost: 1
     23: l1 -> l17 : keA^0'=0, [], cost: 1
     16: l2 -> l0 : keA^0'=0, [], cost: 1
      2: l3 -> l4 : [ AsyncAddressData^0<=0 ], cost: 1
      3: l3 -> l4 : [ 1<=AsyncAddressData^0 ], cost: 1
     15: l4 -> l12 : [], cost: 1
      4: l5 -> l3 : [ __rho_9_^0<=0 ], cost: 1
      5: l5 -> l3 : [ 1<=__rho_9_^0 ], cost: 1
      6: l6 -> l5 : __rho_9_^0'=__rho_9_^post_7, [], cost: 1
      7: l7 -> l6 : [ __rho_8_^0<=0 ], cost: 1
      8: l7 -> l6 : [ 1<=__rho_8_^0 ], cost: 1
      9: l8 -> l7 : __rho_8_^0'=__rho_8_^post_10, [], cost: 1
     10: l9 -> l8 : [ __rho_7_^0<=0 ], cost: 1
     11: l9 -> l8 : [ 1<=__rho_7_^0 ], cost: 1
     12: l10 -> l11 : [], cost: 1
     26: l11 -> l18 : CromData^0'=CromData^post_27, k1^0'=-1+k1^0, [ 1<=k1^0 ], cost: 1
     27: l11 -> l4 : __rho_4_^0'=__rho_4_^post_28, i___099^0'=Irql^0, k2^0'=__rho_4_^post_28, keA^0'=0, keR^0'=0, [ k1^0<=0 ], cost: 1
     13: l12 -> l9 : AsyncAddressData^0'=AsyncAddressData^post_14, __rho_7_^0'=__rho_7_^post_14, k2^0'=-1+k2^0, [ 1<=k2^0 ], cost: 1
     14: l12 -> l2 : __rho_10_^0'=__rho_10_^post_15, i___01313^0'=Irql^0, k3^0'=__rho_10_^post_15, keR^0'=0, [ k2^0<=0 ], cost: 1
     17: l13 -> l10 : a77^0'=CromData^0, [], cost: 1
     18: l14 -> l13 : [ __rho_3_^0<=0 ], cost: 1
     19: l14 -> l13 : [ 1<=__rho_3_^0 ], cost: 1
     20: l15 -> l14 : __rho_3_^0'=__rho_3_^post_21, [], cost: 1
     21: l16 -> l15 : [ __rho_2_^0<=0 ], cost: 1
     22: l16 -> l15 : [ 1<=__rho_2_^0 ], cost: 1
     49: l17 -> l19 : AsyncAddressData^0'=AsyncAddressData^post_50, BusResetIrp^0'=BusResetIrp^post_50, CromData^0'=CromData^post_50, DeviceObject^0'=DeviceObject^post_50, Irp^0'=Irp^post_50, Irql^0'=Irql^post_50, IsochDetachData^0'=IsochDetachData^post_50, IsochResourceData^0'=IsochResourceData^post_50, ResourceIrp^0'=ResourceIrp^post_50, StackSize^0'=StackSize^post_50, __rho_10_^0'=__rho_10_^post_50, __rho_11_^0'=__rho_11_^post_50, __rho_12_^0'=__rho_12_^post_50, __rho_1_^0'=__rho_1_^post_50, __rho_2_^0'=__rho_2_^post_50, __rho_3_^0'=__rho_3_^post_50, __rho_4_^0'=__rho_4_^post_50, __rho_5_^0'=__rho_5_^post_50, __rho_666_^0'=__rho_666_^post_50, __rho_7_^0'=__rho_7_^post_50, __rho_8_^0'=__rho_8_^post_50, __rho_9_^0'=__rho_9_^post_50, a11^0'=a11^post_50, a1818^0'=a1818^post_50, a2525^0'=a2525^post_50, a2828^0'=a2828^post_50, a3131^0'=a3131^post_50, a3232^0'=a3232^post_50, a3434^0'=a3434^post_50, a3737^0'=a3737^post_50, a3838^0'=a3838^post_50, a4343^0'=a4343^post_50, a4545^0'=a4545^post_50, a77^0'=a77^post_50, b22^0'=b22^post_50, b2626^0'=b2626^post_50, b2929^0'=b2929^post_50, b3333^0'=b3333^post_50, b3535^0'=b3535^post_50, i^0'=i^post_50, i___01313^0'=i___01313^post_50, i___01717^0'=i___01717^post_50, i___02020^0'=i___02020^post_50, i___02424^0'=i___02424^post_50, i___04040^0'=i___04040^post_50, i___04747^0'=i___04747^post_50, i___099^0'=i___099^post_50, ioA^0'=ioA^post_50, ioR^0'=ioR^post_50, k1^0'=k1^post_50, k2^0'=k2^post_50, k3^0'=k3^post_50, k4^0'=k4^post_50, k5^0'=k5^post_50, keA^0'=keA^post_50, keR^0'=keR^post_50, ntStatus^0'=ntStatus^post_50, pIrb^0'=pIrb^post_50, phi_io_compl^0'=phi_io_compl^post_50, phi_nSUC_ret^0'=phi_nSUC_ret^post_50, prevCancel^0'=prevCancel^post_50, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_50, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_50, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_50, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_50, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_50, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_50, [ k4^0<=0 && i___04040^post_50==Irql^0 && keR^1_4_1==1 && keR^post_50==0 && keA^1_5==1 && keA^post_50==0 && __rho_12_^post_50==__rho_12_^post_50 && k5^post_50==__rho_12_^post_50 && AsyncAddressData^0==AsyncAddressData^post_50 && BusResetIrp^0==BusResetIrp^post_50 && CromData^0==CromData^post_50 && DeviceObject^0==DeviceObject^post_50 && Irp^0==Irp^post_50 && Irql^0==Irql^post_50 && IsochDetachData^0==IsochDetachData^post_50 && IsochResourceData^0==IsochResourceData^post_50 && ResourceIrp^0==ResourceIrp^post_50 && StackSize^0==StackSize^post_50 && __rho_10_^0==__rho_10_^post_50 && __rho_11_^0==__rho_11_^post_50 && __rho_1_^0==__rho_1_^post_50 && __rho_2_^0==__rho_2_^post_50 && __rho_3_^0==__rho_3_^post_50 && __rho_4_^0==__rho_4_^post_50 && __rho_5_^0==__rho_5_^post_50 && __rho_666_^0==__rho_666_^post_50 && __rho_7_^0==__rho_7_^post_50 && __rho_8_^0==__rho_8_^post_50 && __rho_9_^0==__rho_9_^post_50 && a11^0==a11^post_50 && a1818^0==a1818^post_50 && a2525^0==a2525^post_50 && a2828^0==a2828^post_50 && a3131^0==a3131^post_50 && a3232^0==a3232^post_50 && a3434^0==a3434^post_50 && a3737^0==a3737^post_50 && a3838^0==a3838^post_50 && a4343^0==a4343^post_50 && a4545^0==a4545^post_50 && a77^0==a77^post_50 && b22^0==b22^post_50 && b2626^0==b2626^post_50 && b2929^0==b2929^post_50 && b3333^0==b3333^post_50 && b3535^0==b3535^post_50 && i^0==i^post_50 && i___01313^0==i___01313^post_50 && i___01717^0==i___01717^post_50 && i___02020^0==i___02020^post_50 && i___02424^0==i___02424^post_50 && i___04747^0==i___04747^post_50 && i___099^0==i___099^post_50 && ioA^0==ioA^post_50 && ioR^0==ioR^post_50 && k1^0==k1^post_50 && k2^0==k2^post_50 && k3^0==k3^post_50 && k4^0==k4^post_50 && ntStatus^0==ntStatus^post_50 && pIrb^0==pIrb^post_50 && phi_io_compl^0==phi_io_compl^post_50 && phi_nSUC_ret^0==phi_nSUC_ret^post_50 && prevCancel^0==prevCancel^post_50 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_50 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_50 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_50 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_50 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_50 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_50 ], cost: 1
     50: l17 -> l32 : AsyncAddressData^0'=AsyncAddressData^post_51, BusResetIrp^0'=BusResetIrp^post_51, CromData^0'=CromData^post_51, DeviceObject^0'=DeviceObject^post_51, Irp^0'=Irp^post_51, Irql^0'=Irql^post_51, IsochDetachData^0'=IsochDetachData^post_51, IsochResourceData^0'=IsochResourceData^post_51, ResourceIrp^0'=ResourceIrp^post_51, StackSize^0'=StackSize^post_51, __rho_10_^0'=__rho_10_^post_51, __rho_11_^0'=__rho_11_^post_51, __rho_12_^0'=__rho_12_^post_51, __rho_1_^0'=__rho_1_^post_51, __rho_2_^0'=__rho_2_^post_51, __rho_3_^0'=__rho_3_^post_51, __rho_4_^0'=__rho_4_^post_51, __rho_5_^0'=__rho_5_^post_51, __rho_666_^0'=__rho_666_^post_51, __rho_7_^0'=__rho_7_^post_51, __rho_8_^0'=__rho_8_^post_51, __rho_9_^0'=__rho_9_^post_51, a11^0'=a11^post_51, a1818^0'=a1818^post_51, a2525^0'=a2525^post_51, a2828^0'=a2828^post_51, a3131^0'=a3131^post_51, a3232^0'=a3232^post_51, a3434^0'=a3434^post_51, a3737^0'=a3737^post_51, a3838^0'=a3838^post_51, a4343^0'=a4343^post_51, a4545^0'=a4545^post_51, a77^0'=a77^post_51, b22^0'=b22^post_51, b2626^0'=b2626^post_51, b2929^0'=b2929^post_51, b3333^0'=b3333^post_51, b3535^0'=b3535^post_51, i^0'=i^post_51, i___01313^0'=i___01313^post_51, i___01717^0'=i___01717^post_51, i___02020^0'=i___02020^post_51, i___02424^0'=i___02424^post_51, i___04040^0'=i___04040^post_51, i___04747^0'=i___04747^post_51, i___099^0'=i___099^post_51, ioA^0'=ioA^post_51, ioR^0'=ioR^post_51, k1^0'=k1^post_51, k2^0'=k2^post_51, k3^0'=k3^post_51, k4^0'=k4^post_51, k5^0'=k5^post_51, keA^0'=keA^post_51, keR^0'=keR^post_51, ntStatus^0'=ntStatus^post_51, pIrb^0'=pIrb^post_51, phi_io_compl^0'=phi_io_compl^post_51, phi_nSUC_ret^0'=phi_nSUC_ret^post_51, prevCancel^0'=prevCancel^post_51, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_51, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_51, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_51, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_51, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_51, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_51, [ 1<=k4^0 && IsochResourceData^post_51==IsochResourceData^post_51 && k4^post_51==-1+k4^0 && i___02424^post_51==Irql^0 && keR^1_4_2==1 && keR^post_51==0 && AsyncAddressData^0==AsyncAddressData^post_51 && BusResetIrp^0==BusResetIrp^post_51 && CromData^0==CromData^post_51 && DeviceObject^0==DeviceObject^post_51 && Irp^0==Irp^post_51 && Irql^0==Irql^post_51 && IsochDetachData^0==IsochDetachData^post_51 && ResourceIrp^0==ResourceIrp^post_51 && StackSize^0==StackSize^post_51 && __rho_10_^0==__rho_10_^post_51 && __rho_11_^0==__rho_11_^post_51 && __rho_12_^0==__rho_12_^post_51 && __rho_1_^0==__rho_1_^post_51 && __rho_2_^0==__rho_2_^post_51 && __rho_3_^0==__rho_3_^post_51 && __rho_4_^0==__rho_4_^post_51 && __rho_5_^0==__rho_5_^post_51 && __rho_666_^0==__rho_666_^post_51 && __rho_7_^0==__rho_7_^post_51 && __rho_8_^0==__rho_8_^post_51 && __rho_9_^0==__rho_9_^post_51 && a11^0==a11^post_51 && a1818^0==a1818^post_51 && a2525^0==a2525^post_51 && a2828^0==a2828^post_51 && a3131^0==a3131^post_51 && a3232^0==a3232^post_51 && a3434^0==a3434^post_51 && a3737^0==a3737^post_51 && a3838^0==a3838^post_51 && a4343^0==a4343^post_51 && a4545^0==a4545^post_51 && a77^0==a77^post_51 && b22^0==b22^post_51 && b2626^0==b2626^post_51 && b2929^0==b2929^post_51 && b3333^0==b3333^post_51 && b3535^0==b3535^post_51 && i^0==i^post_51 && i___01313^0==i___01313^post_51 && i___01717^0==i___01717^post_51 && i___02020^0==i___02020^post_51 && i___04040^0==i___04040^post_51 && i___04747^0==i___04747^post_51 && i___099^0==i___099^post_51 && ioA^0==ioA^post_51 && ioR^0==ioR^post_51 && k1^0==k1^post_51 && k2^0==k2^post_51 && k3^0==k3^post_51 && k5^0==k5^post_51 && keA^0==keA^post_51 && ntStatus^0==ntStatus^post_51 && pIrb^0==pIrb^post_51 && phi_io_compl^0==phi_io_compl^post_51 && phi_nSUC_ret^0==phi_nSUC_ret^post_51 && prevCancel^0==prevCancel^post_51 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_51 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_51 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_51 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_51 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_51 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_51 ], cost: 1
     24: l18 -> l10 : [ CromData^0<=0 ], cost: 1
     25: l18 -> l16 : __rho_2_^0'=__rho_2_^post_26, [ 1<=CromData^0 ], cost: 1
     28: l19 -> l20 : [], cost: 1
     37: l20 -> l19 : BusResetIrp^0'=BusResetIrp^post_38, a4343^0'=0, a4545^0'=BusResetIrp^post_38, k5^0'=-1+k5^0, phi_io_compl^0'=1, prevCancel^0'=0, ret_IoSetCancelRoutine4444^0'=0, [ 1<=k5^0 ], cost: 1
     38: l20 -> l26 : i___04747^0'=Irql^0, keR^0'=0, [ k5^0<=0 ], cost: 1
     29: l21 -> l10 : __rho_5_^0'=__rho_5_^post_30, k1^0'=__rho_5_^post_30, keA^0'=0, ntStatus^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, [], cost: 1
     31: l24 -> l25 : phi_nSUC_ret^0'=1, [], cost: 1
     55: l25 -> [35] : [], cost: NONTERM
     32: l26 -> l25 : [ -2+ntStatus^0==0 ], cost: 1
     33: l26 -> l24 : [ 3<=ntStatus^0 ], cost: 1
     34: l26 -> l24 : [ 1+ntStatus^0<=2 ], cost: 1
     39: l28 -> l21 : [ __rho_1_^0<=0 ], cost: 1
     40: l28 -> l21 : a11^0'=DeviceObject^0, b22^0'=Irp^0, ntStatus^0'=0, ret_t1394Diag_PnpStopDevice33^0'=0, [ 1<=__rho_1_^0 ], cost: 1
     41: l29 -> l1 : a3232^0'=pIrb^0, a3434^0'=ResourceIrp^0, a3737^0'=pIrb^0, a3838^0'=ResourceIrp^0, b3333^0'=0, b3535^0'=pIrb^0, ntStatus^0'=0, ret_t1394_SubmitIrpSynch3636^0'=0, [ 1<=pIrb^0 ], cost: 1
     42: l29 -> l1 : a3131^0'=ResourceIrp^0, [ pIrb^0<=0 ], cost: 1
     43: l30 -> l29 : a2828^0'=1, b2929^0'=0, pIrb^0'=0, ret_ExAllocatePool3030^0'=0, [], cost: 1
     44: l31 -> l30 : [ 1<=ResourceIrp^0 ], cost: 1
     45: l31 -> l30 : [ 1+ResourceIrp^0<=0 ], cost: 1
     46: l31 -> l1 : [ ResourceIrp^0==0 ], cost: 1
     47: l32 -> l1 : [ IsochResourceData^0<=0 ], cost: 1
     48: l32 -> l31 : ResourceIrp^0'=0, StackSize^0'=a2525^post_49, a2525^0'=a2525^post_49, b2626^0'=0, pIrb^0'=pIrb^post_49, ret_IoAllocateIrp2727^0'=0, [ 1<=IsochResourceData^0 ], cost: 1
     53: l34 -> l28 : AsyncAddressData^0'=AsyncAddressData^post_52, BusResetIrp^0'=BusResetIrp^post_52, CromData^0'=CromData^post_52, DeviceObject^0'=DeviceObject^post_52, Irp^0'=Irp^post_52, Irql^0'=Irql^post_52, IsochDetachData^0'=IsochDetachData^post_52, IsochResourceData^0'=IsochResourceData^post_52, ResourceIrp^0'=ResourceIrp^post_52, StackSize^0'=StackSize^post_52, __rho_10_^0'=__rho_10_^post_52, __rho_11_^0'=__rho_11_^post_52, __rho_12_^0'=__rho_12_^post_52, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_52, __rho_3_^0'=__rho_3_^post_52, __rho_4_^0'=__rho_4_^post_52, __rho_5_^0'=__rho_5_^post_52, __rho_666_^0'=__rho_666_^post_52, __rho_7_^0'=__rho_7_^post_52, __rho_8_^0'=__rho_8_^post_52, __rho_9_^0'=__rho_9_^post_52, a11^0'=a11^post_52, a1818^0'=a1818^post_52, a2525^0'=a2525^post_52, a2828^0'=a2828^post_52, a3131^0'=a3131^post_52, a3232^0'=a3232^post_52, a3434^0'=a3434^post_52, a3737^0'=a3737^post_52, a3838^0'=a3838^post_52, a4343^0'=a4343^post_52, a4545^0'=a4545^post_52, a77^0'=a77^post_52, b22^0'=b22^post_52, b2626^0'=b2626^post_52, b2929^0'=b2929^post_52, b3333^0'=b3333^post_52, b3535^0'=b3535^post_52, i^0'=i^post_52, i___01313^0'=i___01313^post_52, i___01717^0'=i___01717^post_52, i___02020^0'=i___02020^post_52, i___02424^0'=i___02424^post_52, i___04040^0'=i___04040^post_52, i___04747^0'=i___04747^post_52, i___099^0'=i___099^post_52, ioA^0'=ioA^post_52, ioR^0'=ioR^post_52, k1^0'=k1^post_52, k2^0'=k2^post_52, k3^0'=k3^post_52, k4^0'=k4^post_52, k5^0'=k5^post_52, keA^0'=keA^post_52, keR^0'=keR^post_52, ntStatus^0'=ntStatus^post_52, pIrb^0'=pIrb^post_52, phi_io_compl^0'=phi_io_compl^post_52, phi_nSUC_ret^0'=phi_nSUC_ret^post_52, prevCancel^0'=prevCancel^post_52, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_52, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_52, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_52, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_52, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_52, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_52, [ AsyncAddressData^0==AsyncAddressData^post_53 && BusResetIrp^0==BusResetIrp^post_53 && CromData^0==CromData^post_53 && DeviceObject^0==DeviceObject^post_53 && Irp^0==Irp^post_53 && Irql^0==Irql^post_53 && IsochDetachData^0==IsochDetachData^post_53 && IsochResourceData^0==IsochResourceData^post_53 && ResourceIrp^0==ResourceIrp^post_53 && StackSize^0==StackSize^post_53 && __rho_10_^0==__rho_10_^post_53 && __rho_11_^0==__rho_11_^post_53 && __rho_12_^0==__rho_12_^post_53 && __rho_1_^0==__rho_1_^post_53 && __rho_2_^0==__rho_2_^post_53 && __rho_3_^0==__rho_3_^post_53 && __rho_4_^0==__rho_4_^post_53 && __rho_5_^0==__rho_5_^post_53 && __rho_666_^0==__rho_666_^post_53 && __rho_7_^0==__rho_7_^post_53 && __rho_8_^0==__rho_8_^post_53 && __rho_9_^0==__rho_9_^post_53 && a11^0==a11^post_53 && a1818^0==a1818^post_53 && a2525^0==a2525^post_53 && a2828^0==a2828^post_53 && a3131^0==a3131^post_53 && a3232^0==a3232^post_53 && a3434^0==a3434^post_53 && a3737^0==a3737^post_53 && a3838^0==a3838^post_53 && a4343^0==a4343^post_53 && a4545^0==a4545^post_53 && a77^0==a77^post_53 && b22^0==b22^post_53 && b2626^0==b2626^post_53 && b2929^0==b2929^post_53 && b3333^0==b3333^post_53 && b3535^0==b3535^post_53 && i^0==i^post_53 && i___01313^0==i___01313^post_53 && i___01717^0==i___01717^post_53 && i___02020^0==i___02020^post_53 && i___02424^0==i___02424^post_53 && i___04040^0==i___04040^post_53 && i___04747^0==i___04747^post_53 && i___099^0==i___099^post_53 && ioA^0==ioA^post_53 && ioR^0==ioR^post_53 && k1^0==k1^post_53 && k2^0==k2^post_53 && k3^0==k3^post_53 && k4^0==k4^post_53 && k5^0==k5^post_53 && keA^0==keA^post_53 && keR^0==keR^post_53 && ntStatus^0==ntStatus^post_53 && pIrb^0==pIrb^post_53 && phi_io_compl^0==phi_io_compl^post_53 && phi_nSUC_ret^0==phi_nSUC_ret^post_53 && prevCancel^0==prevCancel^post_53 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_53 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_53 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_53 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_53 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_53 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_53 && ioR^post_52==0 && ioA^post_52==ioR^post_52 && keR^post_52==ioA^post_52 && keA^post_52==keR^post_52 && phi_nSUC_ret^post_52==0 && phi_io_compl^post_52==0 && AsyncAddressData^post_53==AsyncAddressData^post_52 && BusResetIrp^post_53==BusResetIrp^post_52 && CromData^post_53==CromData^post_52 && DeviceObject^post_53==DeviceObject^post_52 && Irp^post_53==Irp^post_52 && Irql^post_53==Irql^post_52 && IsochDetachData^post_53==IsochDetachData^post_52 && IsochResourceData^post_53==IsochResourceData^post_52 && ResourceIrp^post_53==ResourceIrp^post_52 && StackSize^post_53==StackSize^post_52 && __rho_10_^post_53==__rho_10_^post_52 && __rho_11_^post_53==__rho_11_^post_52 && __rho_12_^post_53==__rho_12_^post_52 && __rho_2_^post_53==__rho_2_^post_52 && __rho_3_^post_53==__rho_3_^post_52 && __rho_4_^post_53==__rho_4_^post_52 && __rho_5_^post_53==__rho_5_^post_52 && __rho_7_^post_53==__rho_7_^post_52 && __rho_8_^post_53==__rho_8_^post_52 && __rho_9_^post_53==__rho_9_^post_52 && a11^post_53==a11^post_52 && a1818^post_53==a1818^post_52 && a2525^post_53==a2525^post_52 && a2828^post_53==a2828^post_52 && a3131^post_53==a3131^post_52 && a3232^post_53==a3232^post_52 && a3434^post_53==a3434^post_52 && a3737^post_53==a3737^post_52 && a3838^post_53==a3838^post_52 && a4343^post_53==a4343^post_52 && a4545^post_53==a4545^post_52 && a77^post_53==a77^post_52 && b22^post_53==b22^post_52 && b2626^post_53==b2626^post_52 && b2929^post_53==b2929^post_52 && b3333^post_53==b3333^post_52 && b3535^post_53==b3535^post_52 && i^post_53==i^post_52 && i___01313^post_53==i___01313^post_52 && i___01717^post_53==i___01717^post_52 && i___02020^post_53==i___02020^post_52 && i___02424^post_53==i___02424^post_52 && i___04040^post_53==i___04040^post_52 && i___04747^post_53==i___04747^post_52 && i___099^post_53==i___099^post_52 && k1^post_53==k1^post_52 && k2^post_53==k2^post_52 && k3^post_53==k3^post_52 && k4^post_53==k4^post_52 && k5^post_53==k5^post_52 && ntStatus^post_53==ntStatus^post_52 && pIrb^post_53==pIrb^post_52 && prevCancel^post_53==prevCancel^post_52 && ret_ExAllocatePool3030^post_53==ret_ExAllocatePool3030^post_52 && ret_IoAllocateIrp2727^post_53==ret_IoAllocateIrp2727^post_52 && ret_IoSetCancelRoutine4444^post_53==ret_IoSetCancelRoutine4444^post_52 && ret_IoSetDeviceInterfaceState44^post_53==ret_IoSetDeviceInterfaceState44^post_52 && ret_t1394Diag_PnpStopDevice33^post_53==ret_t1394Diag_PnpStopDevice33^post_52 && ret_t1394_SubmitIrpSynch3636^post_53==ret_t1394_SubmitIrpSynch3636^post_52 ], cost: 2

Chained accelerated rules (with incoming rules):
   Start location: l34
      0: l0 -> l1 : __rho_11_^0'=__rho_11_^post_1, i___02020^0'=Irql^0, k4^0'=__rho_11_^post_1, keR^0'=0, [ k3^0<=0 ], cost: 1
      1: l0 -> l2 : IsochDetachData^0'=IsochDetachData^post_2, a1818^0'=IsochDetachData^post_2, i^0'=i^post_2, i___01717^0'=Irql^0, k3^0'=-1+k3^0, keR^0'=0, [ 1<=k3^0 ], cost: 1
     23: l1 -> l17 : keA^0'=0, [], cost: 1
     16: l2 -> l0 : keA^0'=0, [], cost: 1
      2: l3 -> l4 : [ AsyncAddressData^0<=0 ], cost: 1
      3: l3 -> l4 : [ 1<=AsyncAddressData^0 ], cost: 1
     15: l4 -> l12 : [], cost: 1
      4: l5 -> l3 : [ __rho_9_^0<=0 ], cost: 1
      5: l5 -> l3 : [ 1<=__rho_9_^0 ], cost: 1
      6: l6 -> l5 : __rho_9_^0'=__rho_9_^post_7, [], cost: 1
      7: l7 -> l6 : [ __rho_8_^0<=0 ], cost: 1
      8: l7 -> l6 : [ 1<=__rho_8_^0 ], cost: 1
      9: l8 -> l7 : __rho_8_^0'=__rho_8_^post_10, [], cost: 1
     10: l9 -> l8 : [ __rho_7_^0<=0 ], cost: 1
     11: l9 -> l8 : [ 1<=__rho_7_^0 ], cost: 1
     12: l10 -> l11 : [], cost: 1
     26: l11 -> l18 : CromData^0'=CromData^post_27, k1^0'=-1+k1^0, [ 1<=k1^0 ], cost: 1
     27: l11 -> l4 : __rho_4_^0'=__rho_4_^post_28, i___099^0'=Irql^0, k2^0'=__rho_4_^post_28, keA^0'=0, keR^0'=0, [ k1^0<=0 ], cost: 1
     13: l12 -> l9 : AsyncAddressData^0'=AsyncAddressData^post_14, __rho_7_^0'=__rho_7_^post_14, k2^0'=-1+k2^0, [ 1<=k2^0 ], cost: 1
     14: l12 -> l2 : __rho_10_^0'=__rho_10_^post_15, i___01313^0'=Irql^0, k3^0'=__rho_10_^post_15, keR^0'=0, [ k2^0<=0 ], cost: 1
     17: l13 -> l10 : a77^0'=CromData^0, [], cost: 1
     18: l14 -> l13 : [ __rho_3_^0<=0 ], cost: 1
     19: l14 -> l13 : [ 1<=__rho_3_^0 ], cost: 1
     20: l15 -> l14 : __rho_3_^0'=__rho_3_^post_21, [], cost: 1
     21: l16 -> l15 : [ __rho_2_^0<=0 ], cost: 1
     22: l16 -> l15 : [ 1<=__rho_2_^0 ], cost: 1
     49: l17 -> l19 : AsyncAddressData^0'=AsyncAddressData^post_50, BusResetIrp^0'=BusResetIrp^post_50, CromData^0'=CromData^post_50, DeviceObject^0'=DeviceObject^post_50, Irp^0'=Irp^post_50, Irql^0'=Irql^post_50, IsochDetachData^0'=IsochDetachData^post_50, IsochResourceData^0'=IsochResourceData^post_50, ResourceIrp^0'=ResourceIrp^post_50, StackSize^0'=StackSize^post_50, __rho_10_^0'=__rho_10_^post_50, __rho_11_^0'=__rho_11_^post_50, __rho_12_^0'=__rho_12_^post_50, __rho_1_^0'=__rho_1_^post_50, __rho_2_^0'=__rho_2_^post_50, __rho_3_^0'=__rho_3_^post_50, __rho_4_^0'=__rho_4_^post_50, __rho_5_^0'=__rho_5_^post_50, __rho_666_^0'=__rho_666_^post_50, __rho_7_^0'=__rho_7_^post_50, __rho_8_^0'=__rho_8_^post_50, __rho_9_^0'=__rho_9_^post_50, a11^0'=a11^post_50, a1818^0'=a1818^post_50, a2525^0'=a2525^post_50, a2828^0'=a2828^post_50, a3131^0'=a3131^post_50, a3232^0'=a3232^post_50, a3434^0'=a3434^post_50, a3737^0'=a3737^post_50, a3838^0'=a3838^post_50, a4343^0'=a4343^post_50, a4545^0'=a4545^post_50, a77^0'=a77^post_50, b22^0'=b22^post_50, b2626^0'=b2626^post_50, b2929^0'=b2929^post_50, b3333^0'=b3333^post_50, b3535^0'=b3535^post_50, i^0'=i^post_50, i___01313^0'=i___01313^post_50, i___01717^0'=i___01717^post_50, i___02020^0'=i___02020^post_50, i___02424^0'=i___02424^post_50, i___04040^0'=i___04040^post_50, i___04747^0'=i___04747^post_50, i___099^0'=i___099^post_50, ioA^0'=ioA^post_50, ioR^0'=ioR^post_50, k1^0'=k1^post_50, k2^0'=k2^post_50, k3^0'=k3^post_50, k4^0'=k4^post_50, k5^0'=k5^post_50, keA^0'=keA^post_50, keR^0'=keR^post_50, ntStatus^0'=ntStatus^post_50, pIrb^0'=pIrb^post_50, phi_io_compl^0'=phi_io_compl^post_50, phi_nSUC_ret^0'=phi_nSUC_ret^post_50, prevCancel^0'=prevCancel^post_50, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_50, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_50, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_50, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_50, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_50, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_50, [ k4^0<=0 && i___04040^post_50==Irql^0 && keR^1_4_1==1 && keR^post_50==0 && keA^1_5==1 && keA^post_50==0 && __rho_12_^post_50==__rho_12_^post_50 && k5^post_50==__rho_12_^post_50 && AsyncAddressData^0==AsyncAddressData^post_50 && BusResetIrp^0==BusResetIrp^post_50 && CromData^0==CromData^post_50 && DeviceObject^0==DeviceObject^post_50 && Irp^0==Irp^post_50 && Irql^0==Irql^post_50 && IsochDetachData^0==IsochDetachData^post_50 && IsochResourceData^0==IsochResourceData^post_50 && ResourceIrp^0==ResourceIrp^post_50 && StackSize^0==StackSize^post_50 && __rho_10_^0==__rho_10_^post_50 && __rho_11_^0==__rho_11_^post_50 && __rho_1_^0==__rho_1_^post_50 && __rho_2_^0==__rho_2_^post_50 && __rho_3_^0==__rho_3_^post_50 && __rho_4_^0==__rho_4_^post_50 && __rho_5_^0==__rho_5_^post_50 && __rho_666_^0==__rho_666_^post_50 && __rho_7_^0==__rho_7_^post_50 && __rho_8_^0==__rho_8_^post_50 && __rho_9_^0==__rho_9_^post_50 && a11^0==a11^post_50 && a1818^0==a1818^post_50 && a2525^0==a2525^post_50 && a2828^0==a2828^post_50 && a3131^0==a3131^post_50 && a3232^0==a3232^post_50 && a3434^0==a3434^post_50 && a3737^0==a3737^post_50 && a3838^0==a3838^post_50 && a4343^0==a4343^post_50 && a4545^0==a4545^post_50 && a77^0==a77^post_50 && b22^0==b22^post_50 && b2626^0==b2626^post_50 && b2929^0==b2929^post_50 && b3333^0==b3333^post_50 && b3535^0==b3535^post_50 && i^0==i^post_50 && i___01313^0==i___01313^post_50 && i___01717^0==i___01717^post_50 && i___02020^0==i___02020^post_50 && i___02424^0==i___02424^post_50 && i___04747^0==i___04747^post_50 && i___099^0==i___099^post_50 && ioA^0==ioA^post_50 && ioR^0==ioR^post_50 && k1^0==k1^post_50 && k2^0==k2^post_50 && k3^0==k3^post_50 && k4^0==k4^post_50 && ntStatus^0==ntStatus^post_50 && pIrb^0==pIrb^post_50 && phi_io_compl^0==phi_io_compl^post_50 && phi_nSUC_ret^0==phi_nSUC_ret^post_50 && prevCancel^0==prevCancel^post_50 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_50 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_50 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_50 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_50 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_50 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_50 ], cost: 1
     50: l17 -> l32 : AsyncAddressData^0'=AsyncAddressData^post_51, BusResetIrp^0'=BusResetIrp^post_51, CromData^0'=CromData^post_51, DeviceObject^0'=DeviceObject^post_51, Irp^0'=Irp^post_51, Irql^0'=Irql^post_51, IsochDetachData^0'=IsochDetachData^post_51, IsochResourceData^0'=IsochResourceData^post_51, ResourceIrp^0'=ResourceIrp^post_51, StackSize^0'=StackSize^post_51, __rho_10_^0'=__rho_10_^post_51, __rho_11_^0'=__rho_11_^post_51, __rho_12_^0'=__rho_12_^post_51, __rho_1_^0'=__rho_1_^post_51, __rho_2_^0'=__rho_2_^post_51, __rho_3_^0'=__rho_3_^post_51, __rho_4_^0'=__rho_4_^post_51, __rho_5_^0'=__rho_5_^post_51, __rho_666_^0'=__rho_666_^post_51, __rho_7_^0'=__rho_7_^post_51, __rho_8_^0'=__rho_8_^post_51, __rho_9_^0'=__rho_9_^post_51, a11^0'=a11^post_51, a1818^0'=a1818^post_51, a2525^0'=a2525^post_51, a2828^0'=a2828^post_51, a3131^0'=a3131^post_51, a3232^0'=a3232^post_51, a3434^0'=a3434^post_51, a3737^0'=a3737^post_51, a3838^0'=a3838^post_51, a4343^0'=a4343^post_51, a4545^0'=a4545^post_51, a77^0'=a77^post_51, b22^0'=b22^post_51, b2626^0'=b2626^post_51, b2929^0'=b2929^post_51, b3333^0'=b3333^post_51, b3535^0'=b3535^post_51, i^0'=i^post_51, i___01313^0'=i___01313^post_51, i___01717^0'=i___01717^post_51, i___02020^0'=i___02020^post_51, i___02424^0'=i___02424^post_51, i___04040^0'=i___04040^post_51, i___04747^0'=i___04747^post_51, i___099^0'=i___099^post_51, ioA^0'=ioA^post_51, ioR^0'=ioR^post_51, k1^0'=k1^post_51, k2^0'=k2^post_51, k3^0'=k3^post_51, k4^0'=k4^post_51, k5^0'=k5^post_51, keA^0'=keA^post_51, keR^0'=keR^post_51, ntStatus^0'=ntStatus^post_51, pIrb^0'=pIrb^post_51, phi_io_compl^0'=phi_io_compl^post_51, phi_nSUC_ret^0'=phi_nSUC_ret^post_51, prevCancel^0'=prevCancel^post_51, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_51, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_51, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_51, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_51, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_51, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_51, [ 1<=k4^0 && IsochResourceData^post_51==IsochResourceData^post_51 && k4^post_51==-1+k4^0 && i___02424^post_51==Irql^0 && keR^1_4_2==1 && keR^post_51==0 && AsyncAddressData^0==AsyncAddressData^post_51 && BusResetIrp^0==BusResetIrp^post_51 && CromData^0==CromData^post_51 && DeviceObject^0==DeviceObject^post_51 && Irp^0==Irp^post_51 && Irql^0==Irql^post_51 && IsochDetachData^0==IsochDetachData^post_51 && ResourceIrp^0==ResourceIrp^post_51 && StackSize^0==StackSize^post_51 && __rho_10_^0==__rho_10_^post_51 && __rho_11_^0==__rho_11_^post_51 && __rho_12_^0==__rho_12_^post_51 && __rho_1_^0==__rho_1_^post_51 && __rho_2_^0==__rho_2_^post_51 && __rho_3_^0==__rho_3_^post_51 && __rho_4_^0==__rho_4_^post_51 && __rho_5_^0==__rho_5_^post_51 && __rho_666_^0==__rho_666_^post_51 && __rho_7_^0==__rho_7_^post_51 && __rho_8_^0==__rho_8_^post_51 && __rho_9_^0==__rho_9_^post_51 && a11^0==a11^post_51 && a1818^0==a1818^post_51 && a2525^0==a2525^post_51 && a2828^0==a2828^post_51 && a3131^0==a3131^post_51 && a3232^0==a3232^post_51 && a3434^0==a3434^post_51 && a3737^0==a3737^post_51 && a3838^0==a3838^post_51 && a4343^0==a4343^post_51 && a4545^0==a4545^post_51 && a77^0==a77^post_51 && b22^0==b22^post_51 && b2626^0==b2626^post_51 && b2929^0==b2929^post_51 && b3333^0==b3333^post_51 && b3535^0==b3535^post_51 && i^0==i^post_51 && i___01313^0==i___01313^post_51 && i___01717^0==i___01717^post_51 && i___02020^0==i___02020^post_51 && i___04040^0==i___04040^post_51 && i___04747^0==i___04747^post_51 && i___099^0==i___099^post_51 && ioA^0==ioA^post_51 && ioR^0==ioR^post_51 && k1^0==k1^post_51 && k2^0==k2^post_51 && k3^0==k3^post_51 && k5^0==k5^post_51 && keA^0==keA^post_51 && ntStatus^0==ntStatus^post_51 && pIrb^0==pIrb^post_51 && phi_io_compl^0==phi_io_compl^post_51 && phi_nSUC_ret^0==phi_nSUC_ret^post_51 && prevCancel^0==prevCancel^post_51 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_51 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_51 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_51 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_51 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_51 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_51 ], cost: 1
     24: l18 -> l10 : [ CromData^0<=0 ], cost: 1
     25: l18 -> l16 : __rho_2_^0'=__rho_2_^post_26, [ 1<=CromData^0 ], cost: 1
     28: l19 -> l20 : [], cost: 1
     37: l20 -> l19 : BusResetIrp^0'=BusResetIrp^post_38, a4343^0'=0, a4545^0'=BusResetIrp^post_38, k5^0'=-1+k5^0, phi_io_compl^0'=1, prevCancel^0'=0, ret_IoSetCancelRoutine4444^0'=0, [ 1<=k5^0 ], cost: 1
     38: l20 -> l26 : i___04747^0'=Irql^0, keR^0'=0, [ k5^0<=0 ], cost: 1
     29: l21 -> l10 : __rho_5_^0'=__rho_5_^post_30, k1^0'=__rho_5_^post_30, keA^0'=0, ntStatus^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, [], cost: 1
     31: l24 -> l25 : phi_nSUC_ret^0'=1, [], cost: 1
     56: l24 -> [35] : [], cost: NONTERM
     32: l26 -> l25 : [ -2+ntStatus^0==0 ], cost: 1
     33: l26 -> l24 : [ 3<=ntStatus^0 ], cost: 1
     34: l26 -> l24 : [ 1+ntStatus^0<=2 ], cost: 1
     57: l26 -> [35] : [ -2+ntStatus^0==0 ], cost: NONTERM
     39: l28 -> l21 : [ __rho_1_^0<=0 ], cost: 1
     40: l28 -> l21 : a11^0'=DeviceObject^0, b22^0'=Irp^0, ntStatus^0'=0, ret_t1394Diag_PnpStopDevice33^0'=0, [ 1<=__rho_1_^0 ], cost: 1
     41: l29 -> l1 : a3232^0'=pIrb^0, a3434^0'=ResourceIrp^0, a3737^0'=pIrb^0, a3838^0'=ResourceIrp^0, b3333^0'=0, b3535^0'=pIrb^0, ntStatus^0'=0, ret_t1394_SubmitIrpSynch3636^0'=0, [ 1<=pIrb^0 ], cost: 1
     42: l29 -> l1 : a3131^0'=ResourceIrp^0, [ pIrb^0<=0 ], cost: 1
     43: l30 -> l29 : a2828^0'=1, b2929^0'=0, pIrb^0'=0, ret_ExAllocatePool3030^0'=0, [], cost: 1
     44: l31 -> l30 : [ 1<=ResourceIrp^0 ], cost: 1
     45: l31 -> l30 : [ 1+ResourceIrp^0<=0 ], cost: 1
     46: l31 -> l1 : [ ResourceIrp^0==0 ], cost: 1
     47: l32 -> l1 : [ IsochResourceData^0<=0 ], cost: 1
     48: l32 -> l31 : ResourceIrp^0'=0, StackSize^0'=a2525^post_49, a2525^0'=a2525^post_49, b2626^0'=0, pIrb^0'=pIrb^post_49, ret_IoAllocateIrp2727^0'=0, [ 1<=IsochResourceData^0 ], cost: 1
     53: l34 -> l28 : AsyncAddressData^0'=AsyncAddressData^post_52, BusResetIrp^0'=BusResetIrp^post_52, CromData^0'=CromData^post_52, DeviceObject^0'=DeviceObject^post_52, Irp^0'=Irp^post_52, Irql^0'=Irql^post_52, IsochDetachData^0'=IsochDetachData^post_52, IsochResourceData^0'=IsochResourceData^post_52, ResourceIrp^0'=ResourceIrp^post_52, StackSize^0'=StackSize^post_52, __rho_10_^0'=__rho_10_^post_52, __rho_11_^0'=__rho_11_^post_52, __rho_12_^0'=__rho_12_^post_52, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_52, __rho_3_^0'=__rho_3_^post_52, __rho_4_^0'=__rho_4_^post_52, __rho_5_^0'=__rho_5_^post_52, __rho_666_^0'=__rho_666_^post_52, __rho_7_^0'=__rho_7_^post_52, __rho_8_^0'=__rho_8_^post_52, __rho_9_^0'=__rho_9_^post_52, a11^0'=a11^post_52, a1818^0'=a1818^post_52, a2525^0'=a2525^post_52, a2828^0'=a2828^post_52, a3131^0'=a3131^post_52, a3232^0'=a3232^post_52, a3434^0'=a3434^post_52, a3737^0'=a3737^post_52, a3838^0'=a3838^post_52, a4343^0'=a4343^post_52, a4545^0'=a4545^post_52, a77^0'=a77^post_52, b22^0'=b22^post_52, b2626^0'=b2626^post_52, b2929^0'=b2929^post_52, b3333^0'=b3333^post_52, b3535^0'=b3535^post_52, i^0'=i^post_52, i___01313^0'=i___01313^post_52, i___01717^0'=i___01717^post_52, i___02020^0'=i___02020^post_52, i___02424^0'=i___02424^post_52, i___04040^0'=i___04040^post_52, i___04747^0'=i___04747^post_52, i___099^0'=i___099^post_52, ioA^0'=ioA^post_52, ioR^0'=ioR^post_52, k1^0'=k1^post_52, k2^0'=k2^post_52, k3^0'=k3^post_52, k4^0'=k4^post_52, k5^0'=k5^post_52, keA^0'=keA^post_52, keR^0'=keR^post_52, ntStatus^0'=ntStatus^post_52, pIrb^0'=pIrb^post_52, phi_io_compl^0'=phi_io_compl^post_52, phi_nSUC_ret^0'=phi_nSUC_ret^post_52, prevCancel^0'=prevCancel^post_52, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_52, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_52, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_52, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_52, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_52, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_52, [ AsyncAddressData^0==AsyncAddressData^post_53 && BusResetIrp^0==BusResetIrp^post_53 && CromData^0==CromData^post_53 && DeviceObject^0==DeviceObject^post_53 && Irp^0==Irp^post_53 && Irql^0==Irql^post_53 && IsochDetachData^0==IsochDetachData^post_53 && IsochResourceData^0==IsochResourceData^post_53 && ResourceIrp^0==ResourceIrp^post_53 && StackSize^0==StackSize^post_53 && __rho_10_^0==__rho_10_^post_53 && __rho_11_^0==__rho_11_^post_53 && __rho_12_^0==__rho_12_^post_53 && __rho_1_^0==__rho_1_^post_53 && __rho_2_^0==__rho_2_^post_53 && __rho_3_^0==__rho_3_^post_53 && __rho_4_^0==__rho_4_^post_53 && __rho_5_^0==__rho_5_^post_53 && __rho_666_^0==__rho_666_^post_53 && __rho_7_^0==__rho_7_^post_53 && __rho_8_^0==__rho_8_^post_53 && __rho_9_^0==__rho_9_^post_53 && a11^0==a11^post_53 && a1818^0==a1818^post_53 && a2525^0==a2525^post_53 && a2828^0==a2828^post_53 && a3131^0==a3131^post_53 && a3232^0==a3232^post_53 && a3434^0==a3434^post_53 && a3737^0==a3737^post_53 && a3838^0==a3838^post_53 && a4343^0==a4343^post_53 && a4545^0==a4545^post_53 && a77^0==a77^post_53 && b22^0==b22^post_53 && b2626^0==b2626^post_53 && b2929^0==b2929^post_53 && b3333^0==b3333^post_53 && b3535^0==b3535^post_53 && i^0==i^post_53 && i___01313^0==i___01313^post_53 && i___01717^0==i___01717^post_53 && i___02020^0==i___02020^post_53 && i___02424^0==i___02424^post_53 && i___04040^0==i___04040^post_53 && i___04747^0==i___04747^post_53 && i___099^0==i___099^post_53 && ioA^0==ioA^post_53 && ioR^0==ioR^post_53 && k1^0==k1^post_53 && k2^0==k2^post_53 && k3^0==k3^post_53 && k4^0==k4^post_53 && k5^0==k5^post_53 && keA^0==keA^post_53 && keR^0==keR^post_53 && ntStatus^0==ntStatus^post_53 && pIrb^0==pIrb^post_53 && phi_io_compl^0==phi_io_compl^post_53 && phi_nSUC_ret^0==phi_nSUC_ret^post_53 && prevCancel^0==prevCancel^post_53 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_53 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_53 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_53 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_53 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_53 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_53 && ioR^post_52==0 && ioA^post_52==ioR^post_52 && keR^post_52==ioA^post_52 && keA^post_52==keR^post_52 && phi_nSUC_ret^post_52==0 && phi_io_compl^post_52==0 && AsyncAddressData^post_53==AsyncAddressData^post_52 && BusResetIrp^post_53==BusResetIrp^post_52 && CromData^post_53==CromData^post_52 && DeviceObject^post_53==DeviceObject^post_52 && Irp^post_53==Irp^post_52 && Irql^post_53==Irql^post_52 && IsochDetachData^post_53==IsochDetachData^post_52 && IsochResourceData^post_53==IsochResourceData^post_52 && ResourceIrp^post_53==ResourceIrp^post_52 && StackSize^post_53==StackSize^post_52 && __rho_10_^post_53==__rho_10_^post_52 && __rho_11_^post_53==__rho_11_^post_52 && __rho_12_^post_53==__rho_12_^post_52 && __rho_2_^post_53==__rho_2_^post_52 && __rho_3_^post_53==__rho_3_^post_52 && __rho_4_^post_53==__rho_4_^post_52 && __rho_5_^post_53==__rho_5_^post_52 && __rho_7_^post_53==__rho_7_^post_52 && __rho_8_^post_53==__rho_8_^post_52 && __rho_9_^post_53==__rho_9_^post_52 && a11^post_53==a11^post_52 && a1818^post_53==a1818^post_52 && a2525^post_53==a2525^post_52 && a2828^post_53==a2828^post_52 && a3131^post_53==a3131^post_52 && a3232^post_53==a3232^post_52 && a3434^post_53==a3434^post_52 && a3737^post_53==a3737^post_52 && a3838^post_53==a3838^post_52 && a4343^post_53==a4343^post_52 && a4545^post_53==a4545^post_52 && a77^post_53==a77^post_52 && b22^post_53==b22^post_52 && b2626^post_53==b2626^post_52 && b2929^post_53==b2929^post_52 && b3333^post_53==b3333^post_52 && b3535^post_53==b3535^post_52 && i^post_53==i^post_52 && i___01313^post_53==i___01313^post_52 && i___01717^post_53==i___01717^post_52 && i___02020^post_53==i___02020^post_52 && i___02424^post_53==i___02424^post_52 && i___04040^post_53==i___04040^post_52 && i___04747^post_53==i___04747^post_52 && i___099^post_53==i___099^post_52 && k1^post_53==k1^post_52 && k2^post_53==k2^post_52 && k3^post_53==k3^post_52 && k4^post_53==k4^post_52 && k5^post_53==k5^post_52 && ntStatus^post_53==ntStatus^post_52 && pIrb^post_53==pIrb^post_52 && prevCancel^post_53==prevCancel^post_52 && ret_ExAllocatePool3030^post_53==ret_ExAllocatePool3030^post_52 && ret_IoAllocateIrp2727^post_53==ret_IoAllocateIrp2727^post_52 && ret_IoSetCancelRoutine4444^post_53==ret_IoSetCancelRoutine4444^post_52 && ret_IoSetDeviceInterfaceState44^post_53==ret_IoSetDeviceInterfaceState44^post_52 && ret_t1394Diag_PnpStopDevice33^post_53==ret_t1394Diag_PnpStopDevice33^post_52 && ret_t1394_SubmitIrpSynch3636^post_53==ret_t1394_SubmitIrpSynch3636^post_52 ], cost: 2

Removed unreachable locations (and leaf rules with constant cost):
   Start location: l34
      0: l0 -> l1 : __rho_11_^0'=__rho_11_^post_1, i___02020^0'=Irql^0, k4^0'=__rho_11_^post_1, keR^0'=0, [ k3^0<=0 ], cost: 1
      1: l0 -> l2 : IsochDetachData^0'=IsochDetachData^post_2, a1818^0'=IsochDetachData^post_2, i^0'=i^post_2, i___01717^0'=Irql^0, k3^0'=-1+k3^0, keR^0'=0, [ 1<=k3^0 ], cost: 1
     23: l1 -> l17 : keA^0'=0, [], cost: 1
     16: l2 -> l0 : keA^0'=0, [], cost: 1
      2: l3 -> l4 : [ AsyncAddressData^0<=0 ], cost: 1
      3: l3 -> l4 : [ 1<=AsyncAddressData^0 ], cost: 1
     15: l4 -> l12 : [], cost: 1
      4: l5 -> l3 : [ __rho_9_^0<=0 ], cost: 1
      5: l5 -> l3 : [ 1<=__rho_9_^0 ], cost: 1
      6: l6 -> l5 : __rho_9_^0'=__rho_9_^post_7, [], cost: 1
      7: l7 -> l6 : [ __rho_8_^0<=0 ], cost: 1
      8: l7 -> l6 : [ 1<=__rho_8_^0 ], cost: 1
      9: l8 -> l7 : __rho_8_^0'=__rho_8_^post_10, [], cost: 1
     10: l9 -> l8 : [ __rho_7_^0<=0 ], cost: 1
     11: l9 -> l8 : [ 1<=__rho_7_^0 ], cost: 1
     12: l10 -> l11 : [], cost: 1
     26: l11 -> l18 : CromData^0'=CromData^post_27, k1^0'=-1+k1^0, [ 1<=k1^0 ], cost: 1
     27: l11 -> l4 : __rho_4_^0'=__rho_4_^post_28, i___099^0'=Irql^0, k2^0'=__rho_4_^post_28, keA^0'=0, keR^0'=0, [ k1^0<=0 ], cost: 1
     13: l12 -> l9 : AsyncAddressData^0'=AsyncAddressData^post_14, __rho_7_^0'=__rho_7_^post_14, k2^0'=-1+k2^0, [ 1<=k2^0 ], cost: 1
     14: l12 -> l2 : __rho_10_^0'=__rho_10_^post_15, i___01313^0'=Irql^0, k3^0'=__rho_10_^post_15, keR^0'=0, [ k2^0<=0 ], cost: 1
     17: l13 -> l10 : a77^0'=CromData^0, [], cost: 1
     18: l14 -> l13 : [ __rho_3_^0<=0 ], cost: 1
     19: l14 -> l13 : [ 1<=__rho_3_^0 ], cost: 1
     20: l15 -> l14 : __rho_3_^0'=__rho_3_^post_21, [], cost: 1
     21: l16 -> l15 : [ __rho_2_^0<=0 ], cost: 1
     22: l16 -> l15 : [ 1<=__rho_2_^0 ], cost: 1
     49: l17 -> l19 : AsyncAddressData^0'=AsyncAddressData^post_50, BusResetIrp^0'=BusResetIrp^post_50, CromData^0'=CromData^post_50, DeviceObject^0'=DeviceObject^post_50, Irp^0'=Irp^post_50, Irql^0'=Irql^post_50, IsochDetachData^0'=IsochDetachData^post_50, IsochResourceData^0'=IsochResourceData^post_50, ResourceIrp^0'=ResourceIrp^post_50, StackSize^0'=StackSize^post_50, __rho_10_^0'=__rho_10_^post_50, __rho_11_^0'=__rho_11_^post_50, __rho_12_^0'=__rho_12_^post_50, __rho_1_^0'=__rho_1_^post_50, __rho_2_^0'=__rho_2_^post_50, __rho_3_^0'=__rho_3_^post_50, __rho_4_^0'=__rho_4_^post_50, __rho_5_^0'=__rho_5_^post_50, __rho_666_^0'=__rho_666_^post_50, __rho_7_^0'=__rho_7_^post_50, __rho_8_^0'=__rho_8_^post_50, __rho_9_^0'=__rho_9_^post_50, a11^0'=a11^post_50, a1818^0'=a1818^post_50, a2525^0'=a2525^post_50, a2828^0'=a2828^post_50, a3131^0'=a3131^post_50, a3232^0'=a3232^post_50, a3434^0'=a3434^post_50, a3737^0'=a3737^post_50, a3838^0'=a3838^post_50, a4343^0'=a4343^post_50, a4545^0'=a4545^post_50, a77^0'=a77^post_50, b22^0'=b22^post_50, b2626^0'=b2626^post_50, b2929^0'=b2929^post_50, b3333^0'=b3333^post_50, b3535^0'=b3535^post_50, i^0'=i^post_50, i___01313^0'=i___01313^post_50, i___01717^0'=i___01717^post_50, i___02020^0'=i___02020^post_50, i___02424^0'=i___02424^post_50, i___04040^0'=i___04040^post_50, i___04747^0'=i___04747^post_50, i___099^0'=i___099^post_50, ioA^0'=ioA^post_50, ioR^0'=ioR^post_50, k1^0'=k1^post_50, k2^0'=k2^post_50, k3^0'=k3^post_50, k4^0'=k4^post_50, k5^0'=k5^post_50, keA^0'=keA^post_50, keR^0'=keR^post_50, ntStatus^0'=ntStatus^post_50, pIrb^0'=pIrb^post_50, phi_io_compl^0'=phi_io_compl^post_50, phi_nSUC_ret^0'=phi_nSUC_ret^post_50, prevCancel^0'=prevCancel^post_50, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_50, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_50, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_50, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_50, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_50, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_50, [ k4^0<=0 && i___04040^post_50==Irql^0 && keR^1_4_1==1 && keR^post_50==0 && keA^1_5==1 && keA^post_50==0 && __rho_12_^post_50==__rho_12_^post_50 && k5^post_50==__rho_12_^post_50 && AsyncAddressData^0==AsyncAddressData^post_50 && BusResetIrp^0==BusResetIrp^post_50 && CromData^0==CromData^post_50 && DeviceObject^0==DeviceObject^post_50 && Irp^0==Irp^post_50 && Irql^0==Irql^post_50 && IsochDetachData^0==IsochDetachData^post_50 && IsochResourceData^0==IsochResourceData^post_50 && ResourceIrp^0==ResourceIrp^post_50 && StackSize^0==StackSize^post_50 && __rho_10_^0==__rho_10_^post_50 && __rho_11_^0==__rho_11_^post_50 && __rho_1_^0==__rho_1_^post_50 && __rho_2_^0==__rho_2_^post_50 && __rho_3_^0==__rho_3_^post_50 && __rho_4_^0==__rho_4_^post_50 && __rho_5_^0==__rho_5_^post_50 && __rho_666_^0==__rho_666_^post_50 && __rho_7_^0==__rho_7_^post_50 && __rho_8_^0==__rho_8_^post_50 && __rho_9_^0==__rho_9_^post_50 && a11^0==a11^post_50 && a1818^0==a1818^post_50 && a2525^0==a2525^post_50 && a2828^0==a2828^post_50 && a3131^0==a3131^post_50 && a3232^0==a3232^post_50 && a3434^0==a3434^post_50 && a3737^0==a3737^post_50 && a3838^0==a3838^post_50 && a4343^0==a4343^post_50 && a4545^0==a4545^post_50 && a77^0==a77^post_50 && b22^0==b22^post_50 && b2626^0==b2626^post_50 && b2929^0==b2929^post_50 && b3333^0==b3333^post_50 && b3535^0==b3535^post_50 && i^0==i^post_50 && i___01313^0==i___01313^post_50 && i___01717^0==i___01717^post_50 && i___02020^0==i___02020^post_50 && i___02424^0==i___02424^post_50 && i___04747^0==i___04747^post_50 && i___099^0==i___099^post_50 && ioA^0==ioA^post_50 && ioR^0==ioR^post_50 && k1^0==k1^post_50 && k2^0==k2^post_50 && k3^0==k3^post_50 && k4^0==k4^post_50 && ntStatus^0==ntStatus^post_50 && pIrb^0==pIrb^post_50 && phi_io_compl^0==phi_io_compl^post_50 && phi_nSUC_ret^0==phi_nSUC_ret^post_50 && prevCancel^0==prevCancel^post_50 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_50 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_50 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_50 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_50 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_50 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_50 ], cost: 1
     50: l17 -> l32 : AsyncAddressData^0'=AsyncAddressData^post_51, BusResetIrp^0'=BusResetIrp^post_51, CromData^0'=CromData^post_51, DeviceObject^0'=DeviceObject^post_51, Irp^0'=Irp^post_51, Irql^0'=Irql^post_51, IsochDetachData^0'=IsochDetachData^post_51, IsochResourceData^0'=IsochResourceData^post_51, ResourceIrp^0'=ResourceIrp^post_51, StackSize^0'=StackSize^post_51, __rho_10_^0'=__rho_10_^post_51, __rho_11_^0'=__rho_11_^post_51, __rho_12_^0'=__rho_12_^post_51, __rho_1_^0'=__rho_1_^post_51, __rho_2_^0'=__rho_2_^post_51, __rho_3_^0'=__rho_3_^post_51, __rho_4_^0'=__rho_4_^post_51, __rho_5_^0'=__rho_5_^post_51, __rho_666_^0'=__rho_666_^post_51, __rho_7_^0'=__rho_7_^post_51, __rho_8_^0'=__rho_8_^post_51, __rho_9_^0'=__rho_9_^post_51, a11^0'=a11^post_51, a1818^0'=a1818^post_51, a2525^0'=a2525^post_51, a2828^0'=a2828^post_51, a3131^0'=a3131^post_51, a3232^0'=a3232^post_51, a3434^0'=a3434^post_51, a3737^0'=a3737^post_51, a3838^0'=a3838^post_51, a4343^0'=a4343^post_51, a4545^0'=a4545^post_51, a77^0'=a77^post_51, b22^0'=b22^post_51, b2626^0'=b2626^post_51, b2929^0'=b2929^post_51, b3333^0'=b3333^post_51, b3535^0'=b3535^post_51, i^0'=i^post_51, i___01313^0'=i___01313^post_51, i___01717^0'=i___01717^post_51, i___02020^0'=i___02020^post_51, i___02424^0'=i___02424^post_51, i___04040^0'=i___04040^post_51, i___04747^0'=i___04747^post_51, i___099^0'=i___099^post_51, ioA^0'=ioA^post_51, ioR^0'=ioR^post_51, k1^0'=k1^post_51, k2^0'=k2^post_51, k3^0'=k3^post_51, k4^0'=k4^post_51, k5^0'=k5^post_51, keA^0'=keA^post_51, keR^0'=keR^post_51, ntStatus^0'=ntStatus^post_51, pIrb^0'=pIrb^post_51, phi_io_compl^0'=phi_io_compl^post_51, phi_nSUC_ret^0'=phi_nSUC_ret^post_51, prevCancel^0'=prevCancel^post_51, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_51, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_51, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_51, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_51, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_51, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_51, [ 1<=k4^0 && IsochResourceData^post_51==IsochResourceData^post_51 && k4^post_51==-1+k4^0 && i___02424^post_51==Irql^0 && keR^1_4_2==1 && keR^post_51==0 && AsyncAddressData^0==AsyncAddressData^post_51 && BusResetIrp^0==BusResetIrp^post_51 && CromData^0==CromData^post_51 && DeviceObject^0==DeviceObject^post_51 && Irp^0==Irp^post_51 && Irql^0==Irql^post_51 && IsochDetachData^0==IsochDetachData^post_51 && ResourceIrp^0==ResourceIrp^post_51 && StackSize^0==StackSize^post_51 && __rho_10_^0==__rho_10_^post_51 && __rho_11_^0==__rho_11_^post_51 && __rho_12_^0==__rho_12_^post_51 && __rho_1_^0==__rho_1_^post_51 && __rho_2_^0==__rho_2_^post_51 && __rho_3_^0==__rho_3_^post_51 && __rho_4_^0==__rho_4_^post_51 && __rho_5_^0==__rho_5_^post_51 && __rho_666_^0==__rho_666_^post_51 && __rho_7_^0==__rho_7_^post_51 && __rho_8_^0==__rho_8_^post_51 && __rho_9_^0==__rho_9_^post_51 && a11^0==a11^post_51 && a1818^0==a1818^post_51 && a2525^0==a2525^post_51 && a2828^0==a2828^post_51 && a3131^0==a3131^post_51 && a3232^0==a3232^post_51 && a3434^0==a3434^post_51 && a3737^0==a3737^post_51 && a3838^0==a3838^post_51 && a4343^0==a4343^post_51 && a4545^0==a4545^post_51 && a77^0==a77^post_51 && b22^0==b22^post_51 && b2626^0==b2626^post_51 && b2929^0==b2929^post_51 && b3333^0==b3333^post_51 && b3535^0==b3535^post_51 && i^0==i^post_51 && i___01313^0==i___01313^post_51 && i___01717^0==i___01717^post_51 && i___02020^0==i___02020^post_51 && i___04040^0==i___04040^post_51 && i___04747^0==i___04747^post_51 && i___099^0==i___099^post_51 && ioA^0==ioA^post_51 && ioR^0==ioR^post_51 && k1^0==k1^post_51 && k2^0==k2^post_51 && k3^0==k3^post_51 && k5^0==k5^post_51 && keA^0==keA^post_51 && ntStatus^0==ntStatus^post_51 && pIrb^0==pIrb^post_51 && phi_io_compl^0==phi_io_compl^post_51 && phi_nSUC_ret^0==phi_nSUC_ret^post_51 && prevCancel^0==prevCancel^post_51 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_51 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_51 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_51 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_51 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_51 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_51 ], cost: 1
     24: l18 -> l10 : [ CromData^0<=0 ], cost: 1
     25: l18 -> l16 : __rho_2_^0'=__rho_2_^post_26, [ 1<=CromData^0 ], cost: 1
     28: l19 -> l20 : [], cost: 1
     37: l20 -> l19 : BusResetIrp^0'=BusResetIrp^post_38, a4343^0'=0, a4545^0'=BusResetIrp^post_38, k5^0'=-1+k5^0, phi_io_compl^0'=1, prevCancel^0'=0, ret_IoSetCancelRoutine4444^0'=0, [ 1<=k5^0 ], cost: 1
     38: l20 -> l26 : i___04747^0'=Irql^0, keR^0'=0, [ k5^0<=0 ], cost: 1
     29: l21 -> l10 : __rho_5_^0'=__rho_5_^post_30, k1^0'=__rho_5_^post_30, keA^0'=0, ntStatus^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, [], cost: 1
     56: l24 -> [35] : [], cost: NONTERM
     33: l26 -> l24 : [ 3<=ntStatus^0 ], cost: 1
     34: l26 -> l24 : [ 1+ntStatus^0<=2 ], cost: 1
     57: l26 -> [35] : [ -2+ntStatus^0==0 ], cost: NONTERM
     39: l28 -> l21 : [ __rho_1_^0<=0 ], cost: 1
     40: l28 -> l21 : a11^0'=DeviceObject^0, b22^0'=Irp^0, ntStatus^0'=0, ret_t1394Diag_PnpStopDevice33^0'=0, [ 1<=__rho_1_^0 ], cost: 1
     41: l29 -> l1 : a3232^0'=pIrb^0, a3434^0'=ResourceIrp^0, a3737^0'=pIrb^0, a3838^0'=ResourceIrp^0, b3333^0'=0, b3535^0'=pIrb^0, ntStatus^0'=0, ret_t1394_SubmitIrpSynch3636^0'=0, [ 1<=pIrb^0 ], cost: 1
     42: l29 -> l1 : a3131^0'=ResourceIrp^0, [ pIrb^0<=0 ], cost: 1
     43: l30 -> l29 : a2828^0'=1, b2929^0'=0, pIrb^0'=0, ret_ExAllocatePool3030^0'=0, [], cost: 1
     44: l31 -> l30 : [ 1<=ResourceIrp^0 ], cost: 1
     45: l31 -> l30 : [ 1+ResourceIrp^0<=0 ], cost: 1
     46: l31 -> l1 : [ ResourceIrp^0==0 ], cost: 1
     47: l32 -> l1 : [ IsochResourceData^0<=0 ], cost: 1
     48: l32 -> l31 : ResourceIrp^0'=0, StackSize^0'=a2525^post_49, a2525^0'=a2525^post_49, b2626^0'=0, pIrb^0'=pIrb^post_49, ret_IoAllocateIrp2727^0'=0, [ 1<=IsochResourceData^0 ], cost: 1
     53: l34 -> l28 : AsyncAddressData^0'=AsyncAddressData^post_52, BusResetIrp^0'=BusResetIrp^post_52, CromData^0'=CromData^post_52, DeviceObject^0'=DeviceObject^post_52, Irp^0'=Irp^post_52, Irql^0'=Irql^post_52, IsochDetachData^0'=IsochDetachData^post_52, IsochResourceData^0'=IsochResourceData^post_52, ResourceIrp^0'=ResourceIrp^post_52, StackSize^0'=StackSize^post_52, __rho_10_^0'=__rho_10_^post_52, __rho_11_^0'=__rho_11_^post_52, __rho_12_^0'=__rho_12_^post_52, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_52, __rho_3_^0'=__rho_3_^post_52, __rho_4_^0'=__rho_4_^post_52, __rho_5_^0'=__rho_5_^post_52, __rho_666_^0'=__rho_666_^post_52, __rho_7_^0'=__rho_7_^post_52, __rho_8_^0'=__rho_8_^post_52, __rho_9_^0'=__rho_9_^post_52, a11^0'=a11^post_52, a1818^0'=a1818^post_52, a2525^0'=a2525^post_52, a2828^0'=a2828^post_52, a3131^0'=a3131^post_52, a3232^0'=a3232^post_52, a3434^0'=a3434^post_52, a3737^0'=a3737^post_52, a3838^0'=a3838^post_52, a4343^0'=a4343^post_52, a4545^0'=a4545^post_52, a77^0'=a77^post_52, b22^0'=b22^post_52, b2626^0'=b2626^post_52, b2929^0'=b2929^post_52, b3333^0'=b3333^post_52, b3535^0'=b3535^post_52, i^0'=i^post_52, i___01313^0'=i___01313^post_52, i___01717^0'=i___01717^post_52, i___02020^0'=i___02020^post_52, i___02424^0'=i___02424^post_52, i___04040^0'=i___04040^post_52, i___04747^0'=i___04747^post_52, i___099^0'=i___099^post_52, ioA^0'=ioA^post_52, ioR^0'=ioR^post_52, k1^0'=k1^post_52, k2^0'=k2^post_52, k3^0'=k3^post_52, k4^0'=k4^post_52, k5^0'=k5^post_52, keA^0'=keA^post_52, keR^0'=keR^post_52, ntStatus^0'=ntStatus^post_52, pIrb^0'=pIrb^post_52, phi_io_compl^0'=phi_io_compl^post_52, phi_nSUC_ret^0'=phi_nSUC_ret^post_52, prevCancel^0'=prevCancel^post_52, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_52, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_52, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_52, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_52, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_52, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_52, [ AsyncAddressData^0==AsyncAddressData^post_53 && BusResetIrp^0==BusResetIrp^post_53 && CromData^0==CromData^post_53 && DeviceObject^0==DeviceObject^post_53 && Irp^0==Irp^post_53 && Irql^0==Irql^post_53 && IsochDetachData^0==IsochDetachData^post_53 && IsochResourceData^0==IsochResourceData^post_53 && ResourceIrp^0==ResourceIrp^post_53 && StackSize^0==StackSize^post_53 && __rho_10_^0==__rho_10_^post_53 && __rho_11_^0==__rho_11_^post_53 && __rho_12_^0==__rho_12_^post_53 && __rho_1_^0==__rho_1_^post_53 && __rho_2_^0==__rho_2_^post_53 && __rho_3_^0==__rho_3_^post_53 && __rho_4_^0==__rho_4_^post_53 && __rho_5_^0==__rho_5_^post_53 && __rho_666_^0==__rho_666_^post_53 && __rho_7_^0==__rho_7_^post_53 && __rho_8_^0==__rho_8_^post_53 && __rho_9_^0==__rho_9_^post_53 && a11^0==a11^post_53 && a1818^0==a1818^post_53 && a2525^0==a2525^post_53 && a2828^0==a2828^post_53 && a3131^0==a3131^post_53 && a3232^0==a3232^post_53 && a3434^0==a3434^post_53 && a3737^0==a3737^post_53 && a3838^0==a3838^post_53 && a4343^0==a4343^post_53 && a4545^0==a4545^post_53 && a77^0==a77^post_53 && b22^0==b22^post_53 && b2626^0==b2626^post_53 && b2929^0==b2929^post_53 && b3333^0==b3333^post_53 && b3535^0==b3535^post_53 && i^0==i^post_53 && i___01313^0==i___01313^post_53 && i___01717^0==i___01717^post_53 && i___02020^0==i___02020^post_53 && i___02424^0==i___02424^post_53 && i___04040^0==i___04040^post_53 && i___04747^0==i___04747^post_53 && i___099^0==i___099^post_53 && ioA^0==ioA^post_53 && ioR^0==ioR^post_53 && k1^0==k1^post_53 && k2^0==k2^post_53 && k3^0==k3^post_53 && k4^0==k4^post_53 && k5^0==k5^post_53 && keA^0==keA^post_53 && keR^0==keR^post_53 && ntStatus^0==ntStatus^post_53 && pIrb^0==pIrb^post_53 && phi_io_compl^0==phi_io_compl^post_53 && phi_nSUC_ret^0==phi_nSUC_ret^post_53 && prevCancel^0==prevCancel^post_53 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_53 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_53 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_53 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_53 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_53 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_53 && ioR^post_52==0 && ioA^post_52==ioR^post_52 && keR^post_52==ioA^post_52 && keA^post_52==keR^post_52 && phi_nSUC_ret^post_52==0 && phi_io_compl^post_52==0 && AsyncAddressData^post_53==AsyncAddressData^post_52 && BusResetIrp^post_53==BusResetIrp^post_52 && CromData^post_53==CromData^post_52 && DeviceObject^post_53==DeviceObject^post_52 && Irp^post_53==Irp^post_52 && Irql^post_53==Irql^post_52 && IsochDetachData^post_53==IsochDetachData^post_52 && IsochResourceData^post_53==IsochResourceData^post_52 && ResourceIrp^post_53==ResourceIrp^post_52 && StackSize^post_53==StackSize^post_52 && __rho_10_^post_53==__rho_10_^post_52 && __rho_11_^post_53==__rho_11_^post_52 && __rho_12_^post_53==__rho_12_^post_52 && __rho_2_^post_53==__rho_2_^post_52 && __rho_3_^post_53==__rho_3_^post_52 && __rho_4_^post_53==__rho_4_^post_52 && __rho_5_^post_53==__rho_5_^post_52 && __rho_7_^post_53==__rho_7_^post_52 && __rho_8_^post_53==__rho_8_^post_52 && __rho_9_^post_53==__rho_9_^post_52 && a11^post_53==a11^post_52 && a1818^post_53==a1818^post_52 && a2525^post_53==a2525^post_52 && a2828^post_53==a2828^post_52 && a3131^post_53==a3131^post_52 && a3232^post_53==a3232^post_52 && a3434^post_53==a3434^post_52 && a3737^post_53==a3737^post_52 && a3838^post_53==a3838^post_52 && a4343^post_53==a4343^post_52 && a4545^post_53==a4545^post_52 && a77^post_53==a77^post_52 && b22^post_53==b22^post_52 && b2626^post_53==b2626^post_52 && b2929^post_53==b2929^post_52 && b3333^post_53==b3333^post_52 && b3535^post_53==b3535^post_52 && i^post_53==i^post_52 && i___01313^post_53==i___01313^post_52 && i___01717^post_53==i___01717^post_52 && i___02020^post_53==i___02020^post_52 && i___02424^post_53==i___02424^post_52 && i___04040^post_53==i___04040^post_52 && i___04747^post_53==i___04747^post_52 && i___099^post_53==i___099^post_52 && k1^post_53==k1^post_52 && k2^post_53==k2^post_52 && k3^post_53==k3^post_52 && k4^post_53==k4^post_52 && k5^post_53==k5^post_52 && ntStatus^post_53==ntStatus^post_52 && pIrb^post_53==pIrb^post_52 && prevCancel^post_53==prevCancel^post_52 && ret_ExAllocatePool3030^post_53==ret_ExAllocatePool3030^post_52 && ret_IoAllocateIrp2727^post_53==ret_IoAllocateIrp2727^post_52 && ret_IoSetCancelRoutine4444^post_53==ret_IoSetCancelRoutine4444^post_52 && ret_IoSetDeviceInterfaceState44^post_53==ret_IoSetDeviceInterfaceState44^post_52 && ret_t1394Diag_PnpStopDevice33^post_53==ret_t1394Diag_PnpStopDevice33^post_52 && ret_t1394_SubmitIrpSynch3636^post_53==ret_t1394_SubmitIrpSynch3636^post_52 ], cost: 2

Eliminated locations (on tree-shaped paths):
   Start location: l34
     66: l1 -> l19 : AsyncAddressData^0'=AsyncAddressData^post_50, BusResetIrp^0'=BusResetIrp^post_50, CromData^0'=CromData^post_50, DeviceObject^0'=DeviceObject^post_50, Irp^0'=Irp^post_50, Irql^0'=Irql^post_50, IsochDetachData^0'=IsochDetachData^post_50, IsochResourceData^0'=IsochResourceData^post_50, ResourceIrp^0'=ResourceIrp^post_50, StackSize^0'=StackSize^post_50, __rho_10_^0'=__rho_10_^post_50, __rho_11_^0'=__rho_11_^post_50, __rho_12_^0'=__rho_12_^post_50, __rho_1_^0'=__rho_1_^post_50, __rho_2_^0'=__rho_2_^post_50, __rho_3_^0'=__rho_3_^post_50, __rho_4_^0'=__rho_4_^post_50, __rho_5_^0'=__rho_5_^post_50, __rho_666_^0'=__rho_666_^post_50, __rho_7_^0'=__rho_7_^post_50, __rho_8_^0'=__rho_8_^post_50, __rho_9_^0'=__rho_9_^post_50, a11^0'=a11^post_50, a1818^0'=a1818^post_50, a2525^0'=a2525^post_50, a2828^0'=a2828^post_50, a3131^0'=a3131^post_50, a3232^0'=a3232^post_50, a3434^0'=a3434^post_50, a3737^0'=a3737^post_50, a3838^0'=a3838^post_50, a4343^0'=a4343^post_50, a4545^0'=a4545^post_50, a77^0'=a77^post_50, b22^0'=b22^post_50, b2626^0'=b2626^post_50, b2929^0'=b2929^post_50, b3333^0'=b3333^post_50, b3535^0'=b3535^post_50, i^0'=i^post_50, i___01313^0'=i___01313^post_50, i___01717^0'=i___01717^post_50, i___02020^0'=i___02020^post_50, i___02424^0'=i___02424^post_50, i___04040^0'=i___04040^post_50, i___04747^0'=i___04747^post_50, i___099^0'=i___099^post_50, ioA^0'=ioA^post_50, ioR^0'=ioR^post_50, k1^0'=k1^post_50, k2^0'=k2^post_50, k3^0'=k3^post_50, k4^0'=k4^post_50, k5^0'=k5^post_50, keA^0'=keA^post_50, keR^0'=keR^post_50, ntStatus^0'=ntStatus^post_50, pIrb^0'=pIrb^post_50, phi_io_compl^0'=phi_io_compl^post_50, phi_nSUC_ret^0'=phi_nSUC_ret^post_50, prevCancel^0'=prevCancel^post_50, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_50, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_50, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_50, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_50, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_50, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_50, [ k4^0<=0 && i___04040^post_50==Irql^0 && keR^1_4_1==1 && keR^post_50==0 && keA^1_5==1 && keA^post_50==0 && k5^post_50==__rho_12_^post_50 && AsyncAddressData^0==AsyncAddressData^post_50 && BusResetIrp^0==BusResetIrp^post_50 && CromData^0==CromData^post_50 && DeviceObject^0==DeviceObject^post_50 && Irp^0==Irp^post_50 && Irql^0==Irql^post_50 && IsochDetachData^0==IsochDetachData^post_50 && IsochResourceData^0==IsochResourceData^post_50 && ResourceIrp^0==ResourceIrp^post_50 && StackSize^0==StackSize^post_50 && __rho_10_^0==__rho_10_^post_50 && __rho_11_^0==__rho_11_^post_50 && __rho_1_^0==__rho_1_^post_50 && __rho_2_^0==__rho_2_^post_50 && __rho_3_^0==__rho_3_^post_50 && __rho_4_^0==__rho_4_^post_50 && __rho_5_^0==__rho_5_^post_50 && __rho_666_^0==__rho_666_^post_50 && __rho_7_^0==__rho_7_^post_50 && __rho_8_^0==__rho_8_^post_50 && __rho_9_^0==__rho_9_^post_50 && a11^0==a11^post_50 && a1818^0==a1818^post_50 && a2525^0==a2525^post_50 && a2828^0==a2828^post_50 && a3131^0==a3131^post_50 && a3232^0==a3232^post_50 && a3434^0==a3434^post_50 && a3737^0==a3737^post_50 && a3838^0==a3838^post_50 && a4343^0==a4343^post_50 && a4545^0==a4545^post_50 && a77^0==a77^post_50 && b22^0==b22^post_50 && b2626^0==b2626^post_50 && b2929^0==b2929^post_50 && b3333^0==b3333^post_50 && b3535^0==b3535^post_50 && i^0==i^post_50 && i___01313^0==i___01313^post_50 && i___01717^0==i___01717^post_50 && i___02020^0==i___02020^post_50 && i___02424^0==i___02424^post_50 && i___04747^0==i___04747^post_50 && i___099^0==i___099^post_50 && ioA^0==ioA^post_50 && ioR^0==ioR^post_50 && k1^0==k1^post_50 && k2^0==k2^post_50 && k3^0==k3^post_50 && k4^0==k4^post_50 && ntStatus^0==ntStatus^post_50 && pIrb^0==pIrb^post_50 && phi_io_compl^0==phi_io_compl^post_50 && phi_nSUC_ret^0==phi_nSUC_ret^post_50 && prevCancel^0==prevCancel^post_50 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_50 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_50 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_50 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_50 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_50 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_50 ], cost: 2
     67: l1 -> l32 : AsyncAddressData^0'=AsyncAddressData^post_51, BusResetIrp^0'=BusResetIrp^post_51, CromData^0'=CromData^post_51, DeviceObject^0'=DeviceObject^post_51, Irp^0'=Irp^post_51, Irql^0'=Irql^post_51, IsochDetachData^0'=IsochDetachData^post_51, IsochResourceData^0'=IsochResourceData^post_51, ResourceIrp^0'=ResourceIrp^post_51, StackSize^0'=StackSize^post_51, __rho_10_^0'=__rho_10_^post_51, __rho_11_^0'=__rho_11_^post_51, __rho_12_^0'=__rho_12_^post_51, __rho_1_^0'=__rho_1_^post_51, __rho_2_^0'=__rho_2_^post_51, __rho_3_^0'=__rho_3_^post_51, __rho_4_^0'=__rho_4_^post_51, __rho_5_^0'=__rho_5_^post_51, __rho_666_^0'=__rho_666_^post_51, __rho_7_^0'=__rho_7_^post_51, __rho_8_^0'=__rho_8_^post_51, __rho_9_^0'=__rho_9_^post_51, a11^0'=a11^post_51, a1818^0'=a1818^post_51, a2525^0'=a2525^post_51, a2828^0'=a2828^post_51, a3131^0'=a3131^post_51, a3232^0'=a3232^post_51, a3434^0'=a3434^post_51, a3737^0'=a3737^post_51, a3838^0'=a3838^post_51, a4343^0'=a4343^post_51, a4545^0'=a4545^post_51, a77^0'=a77^post_51, b22^0'=b22^post_51, b2626^0'=b2626^post_51, b2929^0'=b2929^post_51, b3333^0'=b3333^post_51, b3535^0'=b3535^post_51, i^0'=i^post_51, i___01313^0'=i___01313^post_51, i___01717^0'=i___01717^post_51, i___02020^0'=i___02020^post_51, i___02424^0'=i___02424^post_51, i___04040^0'=i___04040^post_51, i___04747^0'=i___04747^post_51, i___099^0'=i___099^post_51, ioA^0'=ioA^post_51, ioR^0'=ioR^post_51, k1^0'=k1^post_51, k2^0'=k2^post_51, k3^0'=k3^post_51, k4^0'=k4^post_51, k5^0'=k5^post_51, keA^0'=keA^post_51, keR^0'=keR^post_51, ntStatus^0'=ntStatus^post_51, pIrb^0'=pIrb^post_51, phi_io_compl^0'=phi_io_compl^post_51, phi_nSUC_ret^0'=phi_nSUC_ret^post_51, prevCancel^0'=prevCancel^post_51, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_51, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_51, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_51, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_51, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_51, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_51, [ 1<=k4^0 && k4^post_51==-1+k4^0 && i___02424^post_51==Irql^0 && keR^1_4_2==1 && keR^post_51==0 && AsyncAddressData^0==AsyncAddressData^post_51 && BusResetIrp^0==BusResetIrp^post_51 && CromData^0==CromData^post_51 && DeviceObject^0==DeviceObject^post_51 && Irp^0==Irp^post_51 && Irql^0==Irql^post_51 && IsochDetachData^0==IsochDetachData^post_51 && ResourceIrp^0==ResourceIrp^post_51 && StackSize^0==StackSize^post_51 && __rho_10_^0==__rho_10_^post_51 && __rho_11_^0==__rho_11_^post_51 && __rho_12_^0==__rho_12_^post_51 && __rho_1_^0==__rho_1_^post_51 && __rho_2_^0==__rho_2_^post_51 && __rho_3_^0==__rho_3_^post_51 && __rho_4_^0==__rho_4_^post_51 && __rho_5_^0==__rho_5_^post_51 && __rho_666_^0==__rho_666_^post_51 && __rho_7_^0==__rho_7_^post_51 && __rho_8_^0==__rho_8_^post_51 && __rho_9_^0==__rho_9_^post_51 && a11^0==a11^post_51 && a1818^0==a1818^post_51 && a2525^0==a2525^post_51 && a2828^0==a2828^post_51 && a3131^0==a3131^post_51 && a3232^0==a3232^post_51 && a3434^0==a3434^post_51 && a3737^0==a3737^post_51 && a3838^0==a3838^post_51 && a4343^0==a4343^post_51 && a4545^0==a4545^post_51 && a77^0==a77^post_51 && b22^0==b22^post_51 && b2626^0==b2626^post_51 && b2929^0==b2929^post_51 && b3333^0==b3333^post_51 && b3535^0==b3535^post_51 && i^0==i^post_51 && i___01313^0==i___01313^post_51 && i___01717^0==i___01717^post_51 && i___02020^0==i___02020^post_51 && i___04040^0==i___04040^post_51 && i___04747^0==i___04747^post_51 && i___099^0==i___099^post_51 && ioA^0==ioA^post_51 && ioR^0==ioR^post_51 && k1^0==k1^post_51 && k2^0==k2^post_51 && k3^0==k3^post_51 && k5^0==k5^post_51 && 0==keA^post_51 && ntStatus^0==ntStatus^post_51 && pIrb^0==pIrb^post_51 && phi_io_compl^0==phi_io_compl^post_51 && phi_nSUC_ret^0==phi_nSUC_ret^post_51 && prevCancel^0==prevCancel^post_51 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_51 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_51 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_51 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_51 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_51 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_51 ], cost: 2
     64: l2 -> l1 : __rho_11_^0'=__rho_11_^post_1, i___02020^0'=Irql^0, k4^0'=__rho_11_^post_1, keA^0'=0, keR^0'=0, [ k3^0<=0 ], cost: 2
     65: l2 -> l2 : IsochDetachData^0'=IsochDetachData^post_2, a1818^0'=IsochDetachData^post_2, i^0'=i^post_2, i___01717^0'=Irql^0, k3^0'=-1+k3^0, keA^0'=0, keR^0'=0, [ 1<=k3^0 ], cost: 2
     62: l4 -> l9 : AsyncAddressData^0'=AsyncAddressData^post_14, __rho_7_^0'=__rho_7_^post_14, k2^0'=-1+k2^0, [ 1<=k2^0 ], cost: 2
     63: l4 -> l2 : __rho_10_^0'=__rho_10_^post_15, i___01313^0'=Irql^0, k3^0'=__rho_10_^post_15, keR^0'=0, [ k2^0<=0 ], cost: 2
     77: l5 -> l4 : [ __rho_9_^0<=0 && AsyncAddressData^0<=0 ], cost: 2
     78: l5 -> l4 : [ __rho_9_^0<=0 && 1<=AsyncAddressData^0 ], cost: 2
     79: l5 -> l4 : [ 1<=__rho_9_^0 && AsyncAddressData^0<=0 ], cost: 2
     80: l5 -> l4 : [ 1<=__rho_9_^0 && 1<=AsyncAddressData^0 ], cost: 2
     75: l7 -> l5 : __rho_9_^0'=__rho_9_^post_7, [ __rho_8_^0<=0 ], cost: 2
     76: l7 -> l5 : __rho_9_^0'=__rho_9_^post_7, [ 1<=__rho_8_^0 ], cost: 2
     73: l9 -> l7 : __rho_8_^0'=__rho_8_^post_10, [ __rho_7_^0<=0 ], cost: 2
     74: l9 -> l7 : __rho_8_^0'=__rho_8_^post_10, [ 1<=__rho_7_^0 ], cost: 2
     60: l10 -> l18 : CromData^0'=CromData^post_27, k1^0'=-1+k1^0, [ 1<=k1^0 ], cost: 2
     61: l10 -> l4 : __rho_4_^0'=__rho_4_^post_28, i___099^0'=Irql^0, k2^0'=__rho_4_^post_28, keA^0'=0, keR^0'=0, [ k1^0<=0 ], cost: 2
     17: l13 -> l10 : a77^0'=CromData^0, [], cost: 1
     83: l15 -> l13 : __rho_3_^0'=__rho_3_^post_21, [ __rho_3_^post_21<=0 ], cost: 2
     84: l15 -> l13 : __rho_3_^0'=__rho_3_^post_21, [ 1<=__rho_3_^post_21 ], cost: 2
     24: l18 -> l10 : [ CromData^0<=0 ], cost: 1
     81: l18 -> l15 : __rho_2_^0'=__rho_2_^post_26, [ 1<=CromData^0 && __rho_2_^post_26<=0 ], cost: 2
     82: l18 -> l15 : __rho_2_^0'=__rho_2_^post_26, [ 1<=CromData^0 && 1<=__rho_2_^post_26 ], cost: 2
     68: l19 -> l19 : BusResetIrp^0'=BusResetIrp^post_38, a4343^0'=0, a4545^0'=BusResetIrp^post_38, k5^0'=-1+k5^0, phi_io_compl^0'=1, prevCancel^0'=0, ret_IoSetCancelRoutine4444^0'=0, [ 1<=k5^0 ], cost: 2
     69: l19 -> l26 : i___04747^0'=Irql^0, keR^0'=0, [ k5^0<=0 ], cost: 2
     29: l21 -> l10 : __rho_5_^0'=__rho_5_^post_30, k1^0'=__rho_5_^post_30, keA^0'=0, ntStatus^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, [], cost: 1
     57: l26 -> [35] : [ -2+ntStatus^0==0 ], cost: NONTERM
     70: l26 -> [35] : [ 3<=ntStatus^0 ], cost: NONTERM
     71: l26 -> [35] : [ 1+ntStatus^0<=2 ], cost: NONTERM
     41: l29 -> l1 : a3232^0'=pIrb^0, a3434^0'=ResourceIrp^0, a3737^0'=pIrb^0, a3838^0'=ResourceIrp^0, b3333^0'=0, b3535^0'=pIrb^0, ntStatus^0'=0, ret_t1394_SubmitIrpSynch3636^0'=0, [ 1<=pIrb^0 ], cost: 1
     42: l29 -> l1 : a3131^0'=ResourceIrp^0, [ pIrb^0<=0 ], cost: 1
     43: l30 -> l29 : a2828^0'=1, b2929^0'=0, pIrb^0'=0, ret_ExAllocatePool3030^0'=0, [], cost: 1
     47: l32 -> l1 : [ IsochResourceData^0<=0 ], cost: 1
     72: l32 -> l1 : ResourceIrp^0'=0, StackSize^0'=a2525^post_49, a2525^0'=a2525^post_49, b2626^0'=0, pIrb^0'=pIrb^post_49, ret_IoAllocateIrp2727^0'=0, [ 1<=IsochResourceData^0 ], cost: 2
     58: l34 -> l21 : AsyncAddressData^0'=AsyncAddressData^post_52, BusResetIrp^0'=BusResetIrp^post_52, CromData^0'=CromData^post_52, DeviceObject^0'=DeviceObject^post_52, Irp^0'=Irp^post_52, Irql^0'=Irql^post_52, IsochDetachData^0'=IsochDetachData^post_52, IsochResourceData^0'=IsochResourceData^post_52, ResourceIrp^0'=ResourceIrp^post_52, StackSize^0'=StackSize^post_52, __rho_10_^0'=__rho_10_^post_52, __rho_11_^0'=__rho_11_^post_52, __rho_12_^0'=__rho_12_^post_52, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_52, __rho_3_^0'=__rho_3_^post_52, __rho_4_^0'=__rho_4_^post_52, __rho_5_^0'=__rho_5_^post_52, __rho_666_^0'=__rho_666_^post_52, __rho_7_^0'=__rho_7_^post_52, __rho_8_^0'=__rho_8_^post_52, __rho_9_^0'=__rho_9_^post_52, a11^0'=a11^post_52, a1818^0'=a1818^post_52, a2525^0'=a2525^post_52, a2828^0'=a2828^post_52, a3131^0'=a3131^post_52, a3232^0'=a3232^post_52, a3434^0'=a3434^post_52, a3737^0'=a3737^post_52, a3838^0'=a3838^post_52, a4343^0'=a4343^post_52, a4545^0'=a4545^post_52, a77^0'=a77^post_52, b22^0'=b22^post_52, b2626^0'=b2626^post_52, b2929^0'=b2929^post_52, b3333^0'=b3333^post_52, b3535^0'=b3535^post_52, i^0'=i^post_52, i___01313^0'=i___01313^post_52, i___01717^0'=i___01717^post_52, i___02020^0'=i___02020^post_52, i___02424^0'=i___02424^post_52, i___04040^0'=i___04040^post_52, i___04747^0'=i___04747^post_52, i___099^0'=i___099^post_52, ioA^0'=ioA^post_52, ioR^0'=ioR^post_52, k1^0'=k1^post_52, k2^0'=k2^post_52, k3^0'=k3^post_52, k4^0'=k4^post_52, k5^0'=k5^post_52, keA^0'=keA^post_52, keR^0'=keR^post_52, ntStatus^0'=ntStatus^post_52, pIrb^0'=pIrb^post_52, phi_io_compl^0'=phi_io_compl^post_52, phi_nSUC_ret^0'=phi_nSUC_ret^post_52, prevCancel^0'=prevCancel^post_52, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_52, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_52, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_52, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_52, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_52, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_52, [ AsyncAddressData^0==AsyncAddressData^post_53 && BusResetIrp^0==BusResetIrp^post_53 && CromData^0==CromData^post_53 && DeviceObject^0==DeviceObject^post_53 && Irp^0==Irp^post_53 && Irql^0==Irql^post_53 && IsochDetachData^0==IsochDetachData^post_53 && IsochResourceData^0==IsochResourceData^post_53 && ResourceIrp^0==ResourceIrp^post_53 && StackSize^0==StackSize^post_53 && __rho_10_^0==__rho_10_^post_53 && __rho_11_^0==__rho_11_^post_53 && __rho_12_^0==__rho_12_^post_53 && __rho_1_^0==__rho_1_^post_53 && __rho_2_^0==__rho_2_^post_53 && __rho_3_^0==__rho_3_^post_53 && __rho_4_^0==__rho_4_^post_53 && __rho_5_^0==__rho_5_^post_53 && __rho_666_^0==__rho_666_^post_53 && __rho_7_^0==__rho_7_^post_53 && __rho_8_^0==__rho_8_^post_53 && __rho_9_^0==__rho_9_^post_53 && a11^0==a11^post_53 && a1818^0==a1818^post_53 && a2525^0==a2525^post_53 && a2828^0==a2828^post_53 && a3131^0==a3131^post_53 && a3232^0==a3232^post_53 && a3434^0==a3434^post_53 && a3737^0==a3737^post_53 && a3838^0==a3838^post_53 && a4343^0==a4343^post_53 && a4545^0==a4545^post_53 && a77^0==a77^post_53 && b22^0==b22^post_53 && b2626^0==b2626^post_53 && b2929^0==b2929^post_53 && b3333^0==b3333^post_53 && b3535^0==b3535^post_53 && i^0==i^post_53 && i___01313^0==i___01313^post_53 && i___01717^0==i___01717^post_53 && i___02020^0==i___02020^post_53 && i___02424^0==i___02424^post_53 && i___04040^0==i___04040^post_53 && i___04747^0==i___04747^post_53 && i___099^0==i___099^post_53 && ioA^0==ioA^post_53 && ioR^0==ioR^post_53 && k1^0==k1^post_53 && k2^0==k2^post_53 && k3^0==k3^post_53 && k4^0==k4^post_53 && k5^0==k5^post_53 && keA^0==keA^post_53 && keR^0==keR^post_53 && ntStatus^0==ntStatus^post_53 && pIrb^0==pIrb^post_53 && phi_io_compl^0==phi_io_compl^post_53 && phi_nSUC_ret^0==phi_nSUC_ret^post_53 && prevCancel^0==prevCancel^post_53 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_53 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_53 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_53 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_53 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_53 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_53 && ioR^post_52==0 && ioA^post_52==ioR^post_52 && keR^post_52==ioA^post_52 && keA^post_52==keR^post_52 && phi_nSUC_ret^post_52==0 && phi_io_compl^post_52==0 && AsyncAddressData^post_53==AsyncAddressData^post_52 && BusResetIrp^post_53==BusResetIrp^post_52 && CromData^post_53==CromData^post_52 && DeviceObject^post_53==DeviceObject^post_52 && Irp^post_53==Irp^post_52 && Irql^post_53==Irql^post_52 && IsochDetachData^post_53==IsochDetachData^post_52 && IsochResourceData^post_53==IsochResourceData^post_52 && ResourceIrp^post_53==ResourceIrp^post_52 && StackSize^post_53==StackSize^post_52 && __rho_10_^post_53==__rho_10_^post_52 && __rho_11_^post_53==__rho_11_^post_52 && __rho_12_^post_53==__rho_12_^post_52 && __rho_2_^post_53==__rho_2_^post_52 && __rho_3_^post_53==__rho_3_^post_52 && __rho_4_^post_53==__rho_4_^post_52 && __rho_5_^post_53==__rho_5_^post_52 && __rho_7_^post_53==__rho_7_^post_52 && __rho_8_^post_53==__rho_8_^post_52 && __rho_9_^post_53==__rho_9_^post_52 && a11^post_53==a11^post_52 && a1818^post_53==a1818^post_52 && a2525^post_53==a2525^post_52 && a2828^post_53==a2828^post_52 && a3131^post_53==a3131^post_52 && a3232^post_53==a3232^post_52 && a3434^post_53==a3434^post_52 && a3737^post_53==a3737^post_52 && a3838^post_53==a3838^post_52 && a4343^post_53==a4343^post_52 && a4545^post_53==a4545^post_52 && a77^post_53==a77^post_52 && b22^post_53==b22^post_52 && b2626^post_53==b2626^post_52 && b2929^post_53==b2929^post_52 && b3333^post_53==b3333^post_52 && b3535^post_53==b3535^post_52 && i^post_53==i^post_52 && i___01313^post_53==i___01313^post_52 && i___01717^post_53==i___01717^post_52 && i___02020^post_53==i___02020^post_52 && i___02424^post_53==i___02424^post_52 && i___04040^post_53==i___04040^post_52 && i___04747^post_53==i___04747^post_52 && i___099^post_53==i___099^post_52 && k1^post_53==k1^post_52 && k2^post_53==k2^post_52 && k3^post_53==k3^post_52 && k4^post_53==k4^post_52 && k5^post_53==k5^post_52 && ntStatus^post_53==ntStatus^post_52 && pIrb^post_53==pIrb^post_52 && prevCancel^post_53==prevCancel^post_52 && ret_ExAllocatePool3030^post_53==ret_ExAllocatePool3030^post_52 && ret_IoAllocateIrp2727^post_53==ret_IoAllocateIrp2727^post_52 && ret_IoSetCancelRoutine4444^post_53==ret_IoSetCancelRoutine4444^post_52 && ret_IoSetDeviceInterfaceState44^post_53==ret_IoSetDeviceInterfaceState44^post_52 && ret_t1394Diag_PnpStopDevice33^post_53==ret_t1394Diag_PnpStopDevice33^post_52 && ret_t1394_SubmitIrpSynch3636^post_53==ret_t1394_SubmitIrpSynch3636^post_52 && __rho_1_^post_52<=0 ], cost: 3
     59: l34 -> l21 : AsyncAddressData^0'=AsyncAddressData^post_52, BusResetIrp^0'=BusResetIrp^post_52, CromData^0'=CromData^post_52, DeviceObject^0'=DeviceObject^post_52, Irp^0'=Irp^post_52, Irql^0'=Irql^post_52, IsochDetachData^0'=IsochDetachData^post_52, IsochResourceData^0'=IsochResourceData^post_52, ResourceIrp^0'=ResourceIrp^post_52, StackSize^0'=StackSize^post_52, __rho_10_^0'=__rho_10_^post_52, __rho_11_^0'=__rho_11_^post_52, __rho_12_^0'=__rho_12_^post_52, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_52, __rho_3_^0'=__rho_3_^post_52, __rho_4_^0'=__rho_4_^post_52, __rho_5_^0'=__rho_5_^post_52, __rho_666_^0'=__rho_666_^post_52, __rho_7_^0'=__rho_7_^post_52, __rho_8_^0'=__rho_8_^post_52, __rho_9_^0'=__rho_9_^post_52, a11^0'=DeviceObject^post_52, a1818^0'=a1818^post_52, a2525^0'=a2525^post_52, a2828^0'=a2828^post_52, a3131^0'=a3131^post_52, a3232^0'=a3232^post_52, a3434^0'=a3434^post_52, a3737^0'=a3737^post_52, a3838^0'=a3838^post_52, a4343^0'=a4343^post_52, a4545^0'=a4545^post_52, a77^0'=a77^post_52, b22^0'=Irp^post_52, b2626^0'=b2626^post_52, b2929^0'=b2929^post_52, b3333^0'=b3333^post_52, b3535^0'=b3535^post_52, i^0'=i^post_52, i___01313^0'=i___01313^post_52, i___01717^0'=i___01717^post_52, i___02020^0'=i___02020^post_52, i___02424^0'=i___02424^post_52, i___04040^0'=i___04040^post_52, i___04747^0'=i___04747^post_52, i___099^0'=i___099^post_52, ioA^0'=ioA^post_52, ioR^0'=ioR^post_52, k1^0'=k1^post_52, k2^0'=k2^post_52, k3^0'=k3^post_52, k4^0'=k4^post_52, k5^0'=k5^post_52, keA^0'=keA^post_52, keR^0'=keR^post_52, ntStatus^0'=0, pIrb^0'=pIrb^post_52, phi_io_compl^0'=phi_io_compl^post_52, phi_nSUC_ret^0'=phi_nSUC_ret^post_52, prevCancel^0'=prevCancel^post_52, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_52, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_52, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_52, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_52, ret_t1394Diag_PnpStopDevice33^0'=0, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_52, [ AsyncAddressData^0==AsyncAddressData^post_53 && BusResetIrp^0==BusResetIrp^post_53 && CromData^0==CromData^post_53 && DeviceObject^0==DeviceObject^post_53 && Irp^0==Irp^post_53 && Irql^0==Irql^post_53 && IsochDetachData^0==IsochDetachData^post_53 && IsochResourceData^0==IsochResourceData^post_53 && ResourceIrp^0==ResourceIrp^post_53 && StackSize^0==StackSize^post_53 && __rho_10_^0==__rho_10_^post_53 && __rho_11_^0==__rho_11_^post_53 && __rho_12_^0==__rho_12_^post_53 && __rho_1_^0==__rho_1_^post_53 && __rho_2_^0==__rho_2_^post_53 && __rho_3_^0==__rho_3_^post_53 && __rho_4_^0==__rho_4_^post_53 && __rho_5_^0==__rho_5_^post_53 && __rho_666_^0==__rho_666_^post_53 && __rho_7_^0==__rho_7_^post_53 && __rho_8_^0==__rho_8_^post_53 && __rho_9_^0==__rho_9_^post_53 && a11^0==a11^post_53 && a1818^0==a1818^post_53 && a2525^0==a2525^post_53 && a2828^0==a2828^post_53 && a3131^0==a3131^post_53 && a3232^0==a3232^post_53 && a3434^0==a3434^post_53 && a3737^0==a3737^post_53 && a3838^0==a3838^post_53 && a4343^0==a4343^post_53 && a4545^0==a4545^post_53 && a77^0==a77^post_53 && b22^0==b22^post_53 && b2626^0==b2626^post_53 && b2929^0==b2929^post_53 && b3333^0==b3333^post_53 && b3535^0==b3535^post_53 && i^0==i^post_53 && i___01313^0==i___01313^post_53 && i___01717^0==i___01717^post_53 && i___02020^0==i___02020^post_53 && i___02424^0==i___02424^post_53 && i___04040^0==i___04040^post_53 && i___04747^0==i___04747^post_53 && i___099^0==i___099^post_53 && ioA^0==ioA^post_53 && ioR^0==ioR^post_53 && k1^0==k1^post_53 && k2^0==k2^post_53 && k3^0==k3^post_53 && k4^0==k4^post_53 && k5^0==k5^post_53 && keA^0==keA^post_53 && keR^0==keR^post_53 && ntStatus^0==ntStatus^post_53 && pIrb^0==pIrb^post_53 && phi_io_compl^0==phi_io_compl^post_53 && phi_nSUC_ret^0==phi_nSUC_ret^post_53 && prevCancel^0==prevCancel^post_53 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_53 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_53 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_53 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_53 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_53 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_53 && ioR^post_52==0 && ioA^post_52==ioR^post_52 && keR^post_52==ioA^post_52 && keA^post_52==keR^post_52 && phi_nSUC_ret^post_52==0 && phi_io_compl^post_52==0 && AsyncAddressData^post_53==AsyncAddressData^post_52 && BusResetIrp^post_53==BusResetIrp^post_52 && CromData^post_53==CromData^post_52 && DeviceObject^post_53==DeviceObject^post_52 && Irp^post_53==Irp^post_52 && Irql^post_53==Irql^post_52 && IsochDetachData^post_53==IsochDetachData^post_52 && IsochResourceData^post_53==IsochResourceData^post_52 && ResourceIrp^post_53==ResourceIrp^post_52 && StackSize^post_53==StackSize^post_52 && __rho_10_^post_53==__rho_10_^post_52 && __rho_11_^post_53==__rho_11_^post_52 && __rho_12_^post_53==__rho_12_^post_52 && __rho_2_^post_53==__rho_2_^post_52 && __rho_3_^post_53==__rho_3_^post_52 && __rho_4_^post_53==__rho_4_^post_52 && __rho_5_^post_53==__rho_5_^post_52 && __rho_7_^post_53==__rho_7_^post_52 && __rho_8_^post_53==__rho_8_^post_52 && __rho_9_^post_53==__rho_9_^post_52 && a11^post_53==a11^post_52 && a1818^post_53==a1818^post_52 && a2525^post_53==a2525^post_52 && a2828^post_53==a2828^post_52 && a3131^post_53==a3131^post_52 && a3232^post_53==a3232^post_52 && a3434^post_53==a3434^post_52 && a3737^post_53==a3737^post_52 && a3838^post_53==a3838^post_52 && a4343^post_53==a4343^post_52 && a4545^post_53==a4545^post_52 && a77^post_53==a77^post_52 && b22^post_53==b22^post_52 && b2626^post_53==b2626^post_52 && b2929^post_53==b2929^post_52 && b3333^post_53==b3333^post_52 && b3535^post_53==b3535^post_52 && i^post_53==i^post_52 && i___01313^post_53==i___01313^post_52 && i___01717^post_53==i___01717^post_52 && i___02020^post_53==i___02020^post_52 && i___02424^post_53==i___02424^post_52 && i___04040^post_53==i___04040^post_52 && i___04747^post_53==i___04747^post_52 && i___099^post_53==i___099^post_52 && k1^post_53==k1^post_52 && k2^post_53==k2^post_52 && k3^post_53==k3^post_52 && k4^post_53==k4^post_52 && k5^post_53==k5^post_52 && ntStatus^post_53==ntStatus^post_52 && pIrb^post_53==pIrb^post_52 && prevCancel^post_53==prevCancel^post_52 && ret_ExAllocatePool3030^post_53==ret_ExAllocatePool3030^post_52 && ret_IoAllocateIrp2727^post_53==ret_IoAllocateIrp2727^post_52 && ret_IoSetCancelRoutine4444^post_53==ret_IoSetCancelRoutine4444^post_52 && ret_IoSetDeviceInterfaceState44^post_53==ret_IoSetDeviceInterfaceState44^post_52 && ret_t1394Diag_PnpStopDevice33^post_53==ret_t1394Diag_PnpStopDevice33^post_52 && ret_t1394_SubmitIrpSynch3636^post_53==ret_t1394_SubmitIrpSynch3636^post_52 && 1<=__rho_1_^post_52 ], cost: 3

Merged rules:
   Start location: l34
     66: l1 -> l19 : AsyncAddressData^0'=AsyncAddressData^post_50, BusResetIrp^0'=BusResetIrp^post_50, CromData^0'=CromData^post_50, DeviceObject^0'=DeviceObject^post_50, Irp^0'=Irp^post_50, Irql^0'=Irql^post_50, IsochDetachData^0'=IsochDetachData^post_50, IsochResourceData^0'=IsochResourceData^post_50, ResourceIrp^0'=ResourceIrp^post_50, StackSize^0'=StackSize^post_50, __rho_10_^0'=__rho_10_^post_50, __rho_11_^0'=__rho_11_^post_50, __rho_12_^0'=__rho_12_^post_50, __rho_1_^0'=__rho_1_^post_50, __rho_2_^0'=__rho_2_^post_50, __rho_3_^0'=__rho_3_^post_50, __rho_4_^0'=__rho_4_^post_50, __rho_5_^0'=__rho_5_^post_50, __rho_666_^0'=__rho_666_^post_50, __rho_7_^0'=__rho_7_^post_50, __rho_8_^0'=__rho_8_^post_50, __rho_9_^0'=__rho_9_^post_50, a11^0'=a11^post_50, a1818^0'=a1818^post_50, a2525^0'=a2525^post_50, a2828^0'=a2828^post_50, a3131^0'=a3131^post_50, a3232^0'=a3232^post_50, a3434^0'=a3434^post_50, a3737^0'=a3737^post_50, a3838^0'=a3838^post_50, a4343^0'=a4343^post_50, a4545^0'=a4545^post_50, a77^0'=a77^post_50, b22^0'=b22^post_50, b2626^0'=b2626^post_50, b2929^0'=b2929^post_50, b3333^0'=b3333^post_50, b3535^0'=b3535^post_50, i^0'=i^post_50, i___01313^0'=i___01313^post_50, i___01717^0'=i___01717^post_50, i___02020^0'=i___02020^post_50, i___02424^0'=i___02424^post_50, i___04040^0'=i___04040^post_50, i___04747^0'=i___04747^post_50, i___099^0'=i___099^post_50, ioA^0'=ioA^post_50, ioR^0'=ioR^post_50, k1^0'=k1^post_50, k2^0'=k2^post_50, k3^0'=k3^post_50, k4^0'=k4^post_50, k5^0'=k5^post_50, keA^0'=keA^post_50, keR^0'=keR^post_50, ntStatus^0'=ntStatus^post_50, pIrb^0'=pIrb^post_50, phi_io_compl^0'=phi_io_compl^post_50, phi_nSUC_ret^0'=phi_nSUC_ret^post_50, prevCancel^0'=prevCancel^post_50, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_50, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_50, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_50, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_50, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_50, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_50, [ k4^0<=0 && i___04040^post_50==Irql^0 && keR^1_4_1==1 && keR^post_50==0 && keA^1_5==1 && keA^post_50==0 && k5^post_50==__rho_12_^post_50 && AsyncAddressData^0==AsyncAddressData^post_50 && BusResetIrp^0==BusResetIrp^post_50 && CromData^0==CromData^post_50 && DeviceObject^0==DeviceObject^post_50 && Irp^0==Irp^post_50 && Irql^0==Irql^post_50 && IsochDetachData^0==IsochDetachData^post_50 && IsochResourceData^0==IsochResourceData^post_50 && ResourceIrp^0==ResourceIrp^post_50 && StackSize^0==StackSize^post_50 && __rho_10_^0==__rho_10_^post_50 && __rho_11_^0==__rho_11_^post_50 && __rho_1_^0==__rho_1_^post_50 && __rho_2_^0==__rho_2_^post_50 && __rho_3_^0==__rho_3_^post_50 && __rho_4_^0==__rho_4_^post_50 && __rho_5_^0==__rho_5_^post_50 && __rho_666_^0==__rho_666_^post_50 && __rho_7_^0==__rho_7_^post_50 && __rho_8_^0==__rho_8_^post_50 && __rho_9_^0==__rho_9_^post_50 && a11^0==a11^post_50 && a1818^0==a1818^post_50 && a2525^0==a2525^post_50 && a2828^0==a2828^post_50 && a3131^0==a3131^post_50 && a3232^0==a3232^post_50 && a3434^0==a3434^post_50 && a3737^0==a3737^post_50 && a3838^0==a3838^post_50 && a4343^0==a4343^post_50 && a4545^0==a4545^post_50 && a77^0==a77^post_50 && b22^0==b22^post_50 && b2626^0==b2626^post_50 && b2929^0==b2929^post_50 && b3333^0==b3333^post_50 && b3535^0==b3535^post_50 && i^0==i^post_50 && i___01313^0==i___01313^post_50 && i___01717^0==i___01717^post_50 && i___02020^0==i___02020^post_50 && i___02424^0==i___02424^post_50 && i___04747^0==i___04747^post_50 && i___099^0==i___099^post_50 && ioA^0==ioA^post_50 && ioR^0==ioR^post_50 && k1^0==k1^post_50 && k2^0==k2^post_50 && k3^0==k3^post_50 && k4^0==k4^post_50 && ntStatus^0==ntStatus^post_50 && pIrb^0==pIrb^post_50 && phi_io_compl^0==phi_io_compl^post_50 && phi_nSUC_ret^0==phi_nSUC_ret^post_50 && prevCancel^0==prevCancel^post_50 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_50 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_50 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_50 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_50 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_50 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_50 ], cost: 2
     67: l1 -> l32 : AsyncAddressData^0'=AsyncAddressData^post_51, BusResetIrp^0'=BusResetIrp^post_51, CromData^0'=CromData^post_51, DeviceObject^0'=DeviceObject^post_51, Irp^0'=Irp^post_51, Irql^0'=Irql^post_51, IsochDetachData^0'=IsochDetachData^post_51, IsochResourceData^0'=IsochResourceData^post_51, ResourceIrp^0'=ResourceIrp^post_51, StackSize^0'=StackSize^post_51, __rho_10_^0'=__rho_10_^post_51, __rho_11_^0'=__rho_11_^post_51, __rho_12_^0'=__rho_12_^post_51, __rho_1_^0'=__rho_1_^post_51, __rho_2_^0'=__rho_2_^post_51, __rho_3_^0'=__rho_3_^post_51, __rho_4_^0'=__rho_4_^post_51, __rho_5_^0'=__rho_5_^post_51, __rho_666_^0'=__rho_666_^post_51, __rho_7_^0'=__rho_7_^post_51, __rho_8_^0'=__rho_8_^post_51, __rho_9_^0'=__rho_9_^post_51, a11^0'=a11^post_51, a1818^0'=a1818^post_51, a2525^0'=a2525^post_51, a2828^0'=a2828^post_51, a3131^0'=a3131^post_51, a3232^0'=a3232^post_51, a3434^0'=a3434^post_51, a3737^0'=a3737^post_51, a3838^0'=a3838^post_51, a4343^0'=a4343^post_51, a4545^0'=a4545^post_51, a77^0'=a77^post_51, b22^0'=b22^post_51, b2626^0'=b2626^post_51, b2929^0'=b2929^post_51, b3333^0'=b3333^post_51, b3535^0'=b3535^post_51, i^0'=i^post_51, i___01313^0'=i___01313^post_51, i___01717^0'=i___01717^post_51, i___02020^0'=i___02020^post_51, i___02424^0'=i___02424^post_51, i___04040^0'=i___04040^post_51, i___04747^0'=i___04747^post_51, i___099^0'=i___099^post_51, ioA^0'=ioA^post_51, ioR^0'=ioR^post_51, k1^0'=k1^post_51, k2^0'=k2^post_51, k3^0'=k3^post_51, k4^0'=k4^post_51, k5^0'=k5^post_51, keA^0'=keA^post_51, keR^0'=keR^post_51, ntStatus^0'=ntStatus^post_51, pIrb^0'=pIrb^post_51, phi_io_compl^0'=phi_io_compl^post_51, phi_nSUC_ret^0'=phi_nSUC_ret^post_51, prevCancel^0'=prevCancel^post_51, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_51, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_51, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_51, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_51, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_51, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_51, [ 1<=k4^0 && k4^post_51==-1+k4^0 && i___02424^post_51==Irql^0 && keR^1_4_2==1 && keR^post_51==0 && AsyncAddressData^0==AsyncAddressData^post_51 && BusResetIrp^0==BusResetIrp^post_51 && CromData^0==CromData^post_51 && DeviceObject^0==DeviceObject^post_51 && Irp^0==Irp^post_51 && Irql^0==Irql^post_51 && IsochDetachData^0==IsochDetachData^post_51 && ResourceIrp^0==ResourceIrp^post_51 && StackSize^0==StackSize^post_51 && __rho_10_^0==__rho_10_^post_51 && __rho_11_^0==__rho_11_^post_51 && __rho_12_^0==__rho_12_^post_51 && __rho_1_^0==__rho_1_^post_51 && __rho_2_^0==__rho_2_^post_51 && __rho_3_^0==__rho_3_^post_51 && __rho_4_^0==__rho_4_^post_51 && __rho_5_^0==__rho_5_^post_51 && __rho_666_^0==__rho_666_^post_51 && __rho_7_^0==__rho_7_^post_51 && __rho_8_^0==__rho_8_^post_51 && __rho_9_^0==__rho_9_^post_51 && a11^0==a11^post_51 && a1818^0==a1818^post_51 && a2525^0==a2525^post_51 && a2828^0==a2828^post_51 && a3131^0==a3131^post_51 && a3232^0==a3232^post_51 && a3434^0==a3434^post_51 && a3737^0==a3737^post_51 && a3838^0==a3838^post_51 && a4343^0==a4343^post_51 && a4545^0==a4545^post_51 && a77^0==a77^post_51 && b22^0==b22^post_51 && b2626^0==b2626^post_51 && b2929^0==b2929^post_51 && b3333^0==b3333^post_51 && b3535^0==b3535^post_51 && i^0==i^post_51 && i___01313^0==i___01313^post_51 && i___01717^0==i___01717^post_51 && i___02020^0==i___02020^post_51 && i___04040^0==i___04040^post_51 && i___04747^0==i___04747^post_51 && i___099^0==i___099^post_51 && ioA^0==ioA^post_51 && ioR^0==ioR^post_51 && k1^0==k1^post_51 && k2^0==k2^post_51 && k3^0==k3^post_51 && k5^0==k5^post_51 && 0==keA^post_51 && ntStatus^0==ntStatus^post_51 && pIrb^0==pIrb^post_51 && phi_io_compl^0==phi_io_compl^post_51 && phi_nSUC_ret^0==phi_nSUC_ret^post_51 && prevCancel^0==prevCancel^post_51 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_51 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_51 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_51 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_51 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_51 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_51 ], cost: 2
     64: l2 -> l1 : __rho_11_^0'=__rho_11_^post_1, i___02020^0'=Irql^0, k4^0'=__rho_11_^post_1, keA^0'=0, keR^0'=0, [ k3^0<=0 ], cost: 2
     65: l2 -> l2 : IsochDetachData^0'=IsochDetachData^post_2, a1818^0'=IsochDetachData^post_2, i^0'=i^post_2, i___01717^0'=Irql^0, k3^0'=-1+k3^0, keA^0'=0, keR^0'=0, [ 1<=k3^0 ], cost: 2
     62: l4 -> l9 : AsyncAddressData^0'=AsyncAddressData^post_14, __rho_7_^0'=__rho_7_^post_14, k2^0'=-1+k2^0, [ 1<=k2^0 ], cost: 2
     63: l4 -> l2 : __rho_10_^0'=__rho_10_^post_15, i___01313^0'=Irql^0, k3^0'=__rho_10_^post_15, keR^0'=0, [ k2^0<=0 ], cost: 2
     87: l5 -> l4 : [], cost: 2
     88: l7 -> l5 : __rho_9_^0'=__rho_9_^post_7, [], cost: 2
     89: l9 -> l7 : __rho_8_^0'=__rho_8_^post_10, [], cost: 2
     60: l10 -> l18 : CromData^0'=CromData^post_27, k1^0'=-1+k1^0, [ 1<=k1^0 ], cost: 2
     61: l10 -> l4 : __rho_4_^0'=__rho_4_^post_28, i___099^0'=Irql^0, k2^0'=__rho_4_^post_28, keA^0'=0, keR^0'=0, [ k1^0<=0 ], cost: 2
     17: l13 -> l10 : a77^0'=CromData^0, [], cost: 1
     90: l15 -> l13 : __rho_3_^0'=__rho_3_^post_21, [], cost: 2
     24: l18 -> l10 : [ CromData^0<=0 ], cost: 1
     91: l18 -> l15 : __rho_2_^0'=__rho_2_^post_26, [ 1<=CromData^0 ], cost: 2
     68: l19 -> l19 : BusResetIrp^0'=BusResetIrp^post_38, a4343^0'=0, a4545^0'=BusResetIrp^post_38, k5^0'=-1+k5^0, phi_io_compl^0'=1, prevCancel^0'=0, ret_IoSetCancelRoutine4444^0'=0, [ 1<=k5^0 ], cost: 2
     69: l19 -> l26 : i___04747^0'=Irql^0, keR^0'=0, [ k5^0<=0 ], cost: 2
     29: l21 -> l10 : __rho_5_^0'=__rho_5_^post_30, k1^0'=__rho_5_^post_30, keA^0'=0, ntStatus^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, [], cost: 1
     57: l26 -> [35] : [ -2+ntStatus^0==0 ], cost: NONTERM
     70: l26 -> [35] : [ 3<=ntStatus^0 ], cost: NONTERM
     71: l26 -> [35] : [ 1+ntStatus^0<=2 ], cost: NONTERM
     41: l29 -> l1 : a3232^0'=pIrb^0, a3434^0'=ResourceIrp^0, a3737^0'=pIrb^0, a3838^0'=ResourceIrp^0, b3333^0'=0, b3535^0'=pIrb^0, ntStatus^0'=0, ret_t1394_SubmitIrpSynch3636^0'=0, [ 1<=pIrb^0 ], cost: 1
     42: l29 -> l1 : a3131^0'=ResourceIrp^0, [ pIrb^0<=0 ], cost: 1
     43: l30 -> l29 : a2828^0'=1, b2929^0'=0, pIrb^0'=0, ret_ExAllocatePool3030^0'=0, [], cost: 1
     47: l32 -> l1 : [ IsochResourceData^0<=0 ], cost: 1
     72: l32 -> l1 : ResourceIrp^0'=0, StackSize^0'=a2525^post_49, a2525^0'=a2525^post_49, b2626^0'=0, pIrb^0'=pIrb^post_49, ret_IoAllocateIrp2727^0'=0, [ 1<=IsochResourceData^0 ], cost: 2
     58: l34 -> l21 : AsyncAddressData^0'=AsyncAddressData^post_52, BusResetIrp^0'=BusResetIrp^post_52, CromData^0'=CromData^post_52, DeviceObject^0'=DeviceObject^post_52, Irp^0'=Irp^post_52, Irql^0'=Irql^post_52, IsochDetachData^0'=IsochDetachData^post_52, IsochResourceData^0'=IsochResourceData^post_52, ResourceIrp^0'=ResourceIrp^post_52, StackSize^0'=StackSize^post_52, __rho_10_^0'=__rho_10_^post_52, __rho_11_^0'=__rho_11_^post_52, __rho_12_^0'=__rho_12_^post_52, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_52, __rho_3_^0'=__rho_3_^post_52, __rho_4_^0'=__rho_4_^post_52, __rho_5_^0'=__rho_5_^post_52, __rho_666_^0'=__rho_666_^post_52, __rho_7_^0'=__rho_7_^post_52, __rho_8_^0'=__rho_8_^post_52, __rho_9_^0'=__rho_9_^post_52, a11^0'=a11^post_52, a1818^0'=a1818^post_52, a2525^0'=a2525^post_52, a2828^0'=a2828^post_52, a3131^0'=a3131^post_52, a3232^0'=a3232^post_52, a3434^0'=a3434^post_52, a3737^0'=a3737^post_52, a3838^0'=a3838^post_52, a4343^0'=a4343^post_52, a4545^0'=a4545^post_52, a77^0'=a77^post_52, b22^0'=b22^post_52, b2626^0'=b2626^post_52, b2929^0'=b2929^post_52, b3333^0'=b3333^post_52, b3535^0'=b3535^post_52, i^0'=i^post_52, i___01313^0'=i___01313^post_52, i___01717^0'=i___01717^post_52, i___02020^0'=i___02020^post_52, i___02424^0'=i___02424^post_52, i___04040^0'=i___04040^post_52, i___04747^0'=i___04747^post_52, i___099^0'=i___099^post_52, ioA^0'=ioA^post_52, ioR^0'=ioR^post_52, k1^0'=k1^post_52, k2^0'=k2^post_52, k3^0'=k3^post_52, k4^0'=k4^post_52, k5^0'=k5^post_52, keA^0'=keA^post_52, keR^0'=keR^post_52, ntStatus^0'=ntStatus^post_52, pIrb^0'=pIrb^post_52, phi_io_compl^0'=phi_io_compl^post_52, phi_nSUC_ret^0'=phi_nSUC_ret^post_52, prevCancel^0'=prevCancel^post_52, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_52, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_52, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_52, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_52, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_52, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_52, [ AsyncAddressData^0==AsyncAddressData^post_53 && BusResetIrp^0==BusResetIrp^post_53 && CromData^0==CromData^post_53 && DeviceObject^0==DeviceObject^post_53 && Irp^0==Irp^post_53 && Irql^0==Irql^post_53 && IsochDetachData^0==IsochDetachData^post_53 && IsochResourceData^0==IsochResourceData^post_53 && ResourceIrp^0==ResourceIrp^post_53 && StackSize^0==StackSize^post_53 && __rho_10_^0==__rho_10_^post_53 && __rho_11_^0==__rho_11_^post_53 && __rho_12_^0==__rho_12_^post_53 && __rho_1_^0==__rho_1_^post_53 && __rho_2_^0==__rho_2_^post_53 && __rho_3_^0==__rho_3_^post_53 && __rho_4_^0==__rho_4_^post_53 && __rho_5_^0==__rho_5_^post_53 && __rho_666_^0==__rho_666_^post_53 && __rho_7_^0==__rho_7_^post_53 && __rho_8_^0==__rho_8_^post_53 && __rho_9_^0==__rho_9_^post_53 && a11^0==a11^post_53 && a1818^0==a1818^post_53 && a2525^0==a2525^post_53 && a2828^0==a2828^post_53 && a3131^0==a3131^post_53 && a3232^0==a3232^post_53 && a3434^0==a3434^post_53 && a3737^0==a3737^post_53 && a3838^0==a3838^post_53 && a4343^0==a4343^post_53 && a4545^0==a4545^post_53 && a77^0==a77^post_53 && b22^0==b22^post_53 && b2626^0==b2626^post_53 && b2929^0==b2929^post_53 && b3333^0==b3333^post_53 && b3535^0==b3535^post_53 && i^0==i^post_53 && i___01313^0==i___01313^post_53 && i___01717^0==i___01717^post_53 && i___02020^0==i___02020^post_53 && i___02424^0==i___02424^post_53 && i___04040^0==i___04040^post_53 && i___04747^0==i___04747^post_53 && i___099^0==i___099^post_53 && ioA^0==ioA^post_53 && ioR^0==ioR^post_53 && k1^0==k1^post_53 && k2^0==k2^post_53 && k3^0==k3^post_53 && k4^0==k4^post_53 && k5^0==k5^post_53 && keA^0==keA^post_53 && keR^0==keR^post_53 && ntStatus^0==ntStatus^post_53 && pIrb^0==pIrb^post_53 && phi_io_compl^0==phi_io_compl^post_53 && phi_nSUC_ret^0==phi_nSUC_ret^post_53 && prevCancel^0==prevCancel^post_53 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_53 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_53 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_53 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_53 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_53 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_53 && ioR^post_52==0 && ioA^post_52==ioR^post_52 && keR^post_52==ioA^post_52 && keA^post_52==keR^post_52 && phi_nSUC_ret^post_52==0 && phi_io_compl^post_52==0 && AsyncAddressData^post_53==AsyncAddressData^post_52 && BusResetIrp^post_53==BusResetIrp^post_52 && CromData^post_53==CromData^post_52 && DeviceObject^post_53==DeviceObject^post_52 && Irp^post_53==Irp^post_52 && Irql^post_53==Irql^post_52 && IsochDetachData^post_53==IsochDetachData^post_52 && IsochResourceData^post_53==IsochResourceData^post_52 && ResourceIrp^post_53==ResourceIrp^post_52 && StackSize^post_53==StackSize^post_52 && __rho_10_^post_53==__rho_10_^post_52 && __rho_11_^post_53==__rho_11_^post_52 && __rho_12_^post_53==__rho_12_^post_52 && __rho_2_^post_53==__rho_2_^post_52 && __rho_3_^post_53==__rho_3_^post_52 && __rho_4_^post_53==__rho_4_^post_52 && __rho_5_^post_53==__rho_5_^post_52 && __rho_7_^post_53==__rho_7_^post_52 && __rho_8_^post_53==__rho_8_^post_52 && __rho_9_^post_53==__rho_9_^post_52 && a11^post_53==a11^post_52 && a1818^post_53==a1818^post_52 && a2525^post_53==a2525^post_52 && a2828^post_53==a2828^post_52 && a3131^post_53==a3131^post_52 && a3232^post_53==a3232^post_52 && a3434^post_53==a3434^post_52 && a3737^post_53==a3737^post_52 && a3838^post_53==a3838^post_52 && a4343^post_53==a4343^post_52 && a4545^post_53==a4545^post_52 && a77^post_53==a77^post_52 && b22^post_53==b22^post_52 && b2626^post_53==b2626^post_52 && b2929^post_53==b2929^post_52 && b3333^post_53==b3333^post_52 && b3535^post_53==b3535^post_52 && i^post_53==i^post_52 && i___01313^post_53==i___01313^post_52 && i___01717^post_53==i___01717^post_52 && i___02020^post_53==i___02020^post_52 && i___02424^post_53==i___02424^post_52 && i___04040^post_53==i___04040^post_52 && i___04747^post_53==i___04747^post_52 && i___099^post_53==i___099^post_52 && k1^post_53==k1^post_52 && k2^post_53==k2^post_52 && k3^post_53==k3^post_52 && k4^post_53==k4^post_52 && k5^post_53==k5^post_52 && ntStatus^post_53==ntStatus^post_52 && pIrb^post_53==pIrb^post_52 && prevCancel^post_53==prevCancel^post_52 && ret_ExAllocatePool3030^post_53==ret_ExAllocatePool3030^post_52 && ret_IoAllocateIrp2727^post_53==ret_IoAllocateIrp2727^post_52 && ret_IoSetCancelRoutine4444^post_53==ret_IoSetCancelRoutine4444^post_52 && ret_IoSetDeviceInterfaceState44^post_53==ret_IoSetDeviceInterfaceState44^post_52 && ret_t1394Diag_PnpStopDevice33^post_53==ret_t1394Diag_PnpStopDevice33^post_52 && ret_t1394_SubmitIrpSynch3636^post_53==ret_t1394_SubmitIrpSynch3636^post_52 && __rho_1_^post_52<=0 ], cost: 3
     59: l34 -> l21 : AsyncAddressData^0'=AsyncAddressData^post_52, BusResetIrp^0'=BusResetIrp^post_52, CromData^0'=CromData^post_52, DeviceObject^0'=DeviceObject^post_52, Irp^0'=Irp^post_52, Irql^0'=Irql^post_52, IsochDetachData^0'=IsochDetachData^post_52, IsochResourceData^0'=IsochResourceData^post_52, ResourceIrp^0'=ResourceIrp^post_52, StackSize^0'=StackSize^post_52, __rho_10_^0'=__rho_10_^post_52, __rho_11_^0'=__rho_11_^post_52, __rho_12_^0'=__rho_12_^post_52, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_52, __rho_3_^0'=__rho_3_^post_52, __rho_4_^0'=__rho_4_^post_52, __rho_5_^0'=__rho_5_^post_52, __rho_666_^0'=__rho_666_^post_52, __rho_7_^0'=__rho_7_^post_52, __rho_8_^0'=__rho_8_^post_52, __rho_9_^0'=__rho_9_^post_52, a11^0'=DeviceObject^post_52, a1818^0'=a1818^post_52, a2525^0'=a2525^post_52, a2828^0'=a2828^post_52, a3131^0'=a3131^post_52, a3232^0'=a3232^post_52, a3434^0'=a3434^post_52, a3737^0'=a3737^post_52, a3838^0'=a3838^post_52, a4343^0'=a4343^post_52, a4545^0'=a4545^post_52, a77^0'=a77^post_52, b22^0'=Irp^post_52, b2626^0'=b2626^post_52, b2929^0'=b2929^post_52, b3333^0'=b3333^post_52, b3535^0'=b3535^post_52, i^0'=i^post_52, i___01313^0'=i___01313^post_52, i___01717^0'=i___01717^post_52, i___02020^0'=i___02020^post_52, i___02424^0'=i___02424^post_52, i___04040^0'=i___04040^post_52, i___04747^0'=i___04747^post_52, i___099^0'=i___099^post_52, ioA^0'=ioA^post_52, ioR^0'=ioR^post_52, k1^0'=k1^post_52, k2^0'=k2^post_52, k3^0'=k3^post_52, k4^0'=k4^post_52, k5^0'=k5^post_52, keA^0'=keA^post_52, keR^0'=keR^post_52, ntStatus^0'=0, pIrb^0'=pIrb^post_52, phi_io_compl^0'=phi_io_compl^post_52, phi_nSUC_ret^0'=phi_nSUC_ret^post_52, prevCancel^0'=prevCancel^post_52, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_52, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_52, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_52, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_52, ret_t1394Diag_PnpStopDevice33^0'=0, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_52, [ AsyncAddressData^0==AsyncAddressData^post_53 && BusResetIrp^0==BusResetIrp^post_53 && CromData^0==CromData^post_53 && DeviceObject^0==DeviceObject^post_53 && Irp^0==Irp^post_53 && Irql^0==Irql^post_53 && IsochDetachData^0==IsochDetachData^post_53 && IsochResourceData^0==IsochResourceData^post_53 && ResourceIrp^0==ResourceIrp^post_53 && StackSize^0==StackSize^post_53 && __rho_10_^0==__rho_10_^post_53 && __rho_11_^0==__rho_11_^post_53 && __rho_12_^0==__rho_12_^post_53 && __rho_1_^0==__rho_1_^post_53 && __rho_2_^0==__rho_2_^post_53 && __rho_3_^0==__rho_3_^post_53 && __rho_4_^0==__rho_4_^post_53 && __rho_5_^0==__rho_5_^post_53 && __rho_666_^0==__rho_666_^post_53 && __rho_7_^0==__rho_7_^post_53 && __rho_8_^0==__rho_8_^post_53 && __rho_9_^0==__rho_9_^post_53 && a11^0==a11^post_53 && a1818^0==a1818^post_53 && a2525^0==a2525^post_53 && a2828^0==a2828^post_53 && a3131^0==a3131^post_53 && a3232^0==a3232^post_53 && a3434^0==a3434^post_53 && a3737^0==a3737^post_53 && a3838^0==a3838^post_53 && a4343^0==a4343^post_53 && a4545^0==a4545^post_53 && a77^0==a77^post_53 && b22^0==b22^post_53 && b2626^0==b2626^post_53 && b2929^0==b2929^post_53 && b3333^0==b3333^post_53 && b3535^0==b3535^post_53 && i^0==i^post_53 && i___01313^0==i___01313^post_53 && i___01717^0==i___01717^post_53 && i___02020^0==i___02020^post_53 && i___02424^0==i___02424^post_53 && i___04040^0==i___04040^post_53 && i___04747^0==i___04747^post_53 && i___099^0==i___099^post_53 && ioA^0==ioA^post_53 && ioR^0==ioR^post_53 && k1^0==k1^post_53 && k2^0==k2^post_53 && k3^0==k3^post_53 && k4^0==k4^post_53 && k5^0==k5^post_53 && keA^0==keA^post_53 && keR^0==keR^post_53 && ntStatus^0==ntStatus^post_53 && pIrb^0==pIrb^post_53 && phi_io_compl^0==phi_io_compl^post_53 && phi_nSUC_ret^0==phi_nSUC_ret^post_53 && prevCancel^0==prevCancel^post_53 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_53 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_53 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_53 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_53 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_53 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_53 && ioR^post_52==0 && ioA^post_52==ioR^post_52 && keR^post_52==ioA^post_52 && keA^post_52==keR^post_52 && phi_nSUC_ret^post_52==0 && phi_io_compl^post_52==0 && AsyncAddressData^post_53==AsyncAddressData^post_52 && BusResetIrp^post_53==BusResetIrp^post_52 && CromData^post_53==CromData^post_52 && DeviceObject^post_53==DeviceObject^post_52 && Irp^post_53==Irp^post_52 && Irql^post_53==Irql^post_52 && IsochDetachData^post_53==IsochDetachData^post_52 && IsochResourceData^post_53==IsochResourceData^post_52 && ResourceIrp^post_53==ResourceIrp^post_52 && StackSize^post_53==StackSize^post_52 && __rho_10_^post_53==__rho_10_^post_52 && __rho_11_^post_53==__rho_11_^post_52 && __rho_12_^post_53==__rho_12_^post_52 && __rho_2_^post_53==__rho_2_^post_52 && __rho_3_^post_53==__rho_3_^post_52 && __rho_4_^post_53==__rho_4_^post_52 && __rho_5_^post_53==__rho_5_^post_52 && __rho_7_^post_53==__rho_7_^post_52 && __rho_8_^post_53==__rho_8_^post_52 && __rho_9_^post_53==__rho_9_^post_52 && a11^post_53==a11^post_52 && a1818^post_53==a1818^post_52 && a2525^post_53==a2525^post_52 && a2828^post_53==a2828^post_52 && a3131^post_53==a3131^post_52 && a3232^post_53==a3232^post_52 && a3434^post_53==a3434^post_52 && a3737^post_53==a3737^post_52 && a3838^post_53==a3838^post_52 && a4343^post_53==a4343^post_52 && a4545^post_53==a4545^post_52 && a77^post_53==a77^post_52 && b22^post_53==b22^post_52 && b2626^post_53==b2626^post_52 && b2929^post_53==b2929^post_52 && b3333^post_53==b3333^post_52 && b3535^post_53==b3535^post_52 && i^post_53==i^post_52 && i___01313^post_53==i___01313^post_52 && i___01717^post_53==i___01717^post_52 && i___02020^post_53==i___02020^post_52 && i___02424^post_53==i___02424^post_52 && i___04040^post_53==i___04040^post_52 && i___04747^post_53==i___04747^post_52 && i___099^post_53==i___099^post_52 && k1^post_53==k1^post_52 && k2^post_53==k2^post_52 && k3^post_53==k3^post_52 && k4^post_53==k4^post_52 && k5^post_53==k5^post_52 && ntStatus^post_53==ntStatus^post_52 && pIrb^post_53==pIrb^post_52 && prevCancel^post_53==prevCancel^post_52 && ret_ExAllocatePool3030^post_53==ret_ExAllocatePool3030^post_52 && ret_IoAllocateIrp2727^post_53==ret_IoAllocateIrp2727^post_52 && ret_IoSetCancelRoutine4444^post_53==ret_IoSetCancelRoutine4444^post_52 && ret_IoSetDeviceInterfaceState44^post_53==ret_IoSetDeviceInterfaceState44^post_52 && ret_t1394Diag_PnpStopDevice33^post_53==ret_t1394Diag_PnpStopDevice33^post_52 && ret_t1394_SubmitIrpSynch3636^post_53==ret_t1394_SubmitIrpSynch3636^post_52 && 1<=__rho_1_^post_52 ], cost: 3

Applied pruning (of leafs and parallel rules):
   Start location: l34
     66: l1 -> l19 : AsyncAddressData^0'=AsyncAddressData^post_50, BusResetIrp^0'=BusResetIrp^post_50, CromData^0'=CromData^post_50, DeviceObject^0'=DeviceObject^post_50, Irp^0'=Irp^post_50, Irql^0'=Irql^post_50, IsochDetachData^0'=IsochDetachData^post_50, IsochResourceData^0'=IsochResourceData^post_50, ResourceIrp^0'=ResourceIrp^post_50, StackSize^0'=StackSize^post_50, __rho_10_^0'=__rho_10_^post_50, __rho_11_^0'=__rho_11_^post_50, __rho_12_^0'=__rho_12_^post_50, __rho_1_^0'=__rho_1_^post_50, __rho_2_^0'=__rho_2_^post_50, __rho_3_^0'=__rho_3_^post_50, __rho_4_^0'=__rho_4_^post_50, __rho_5_^0'=__rho_5_^post_50, __rho_666_^0'=__rho_666_^post_50, __rho_7_^0'=__rho_7_^post_50, __rho_8_^0'=__rho_8_^post_50, __rho_9_^0'=__rho_9_^post_50, a11^0'=a11^post_50, a1818^0'=a1818^post_50, a2525^0'=a2525^post_50, a2828^0'=a2828^post_50, a3131^0'=a3131^post_50, a3232^0'=a3232^post_50, a3434^0'=a3434^post_50, a3737^0'=a3737^post_50, a3838^0'=a3838^post_50, a4343^0'=a4343^post_50, a4545^0'=a4545^post_50, a77^0'=a77^post_50, b22^0'=b22^post_50, b2626^0'=b2626^post_50, b2929^0'=b2929^post_50, b3333^0'=b3333^post_50, b3535^0'=b3535^post_50, i^0'=i^post_50, i___01313^0'=i___01313^post_50, i___01717^0'=i___01717^post_50, i___02020^0'=i___02020^post_50, i___02424^0'=i___02424^post_50, i___04040^0'=i___04040^post_50, i___04747^0'=i___04747^post_50, i___099^0'=i___099^post_50, ioA^0'=ioA^post_50, ioR^0'=ioR^post_50, k1^0'=k1^post_50, k2^0'=k2^post_50, k3^0'=k3^post_50, k4^0'=k4^post_50, k5^0'=k5^post_50, keA^0'=keA^post_50, keR^0'=keR^post_50, ntStatus^0'=ntStatus^post_50, pIrb^0'=pIrb^post_50, phi_io_compl^0'=phi_io_compl^post_50, phi_nSUC_ret^0'=phi_nSUC_ret^post_50, prevCancel^0'=prevCancel^post_50, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_50, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_50, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_50, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_50, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_50, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_50, [ k4^0<=0 && i___04040^post_50==Irql^0 && keR^1_4_1==1 && keR^post_50==0 && keA^1_5==1 && keA^post_50==0 && k5^post_50==__rho_12_^post_50 && AsyncAddressData^0==AsyncAddressData^post_50 && BusResetIrp^0==BusResetIrp^post_50 && CromData^0==CromData^post_50 && DeviceObject^0==DeviceObject^post_50 && Irp^0==Irp^post_50 && Irql^0==Irql^post_50 && IsochDetachData^0==IsochDetachData^post_50 && IsochResourceData^0==IsochResourceData^post_50 && ResourceIrp^0==ResourceIrp^post_50 && StackSize^0==StackSize^post_50 && __rho_10_^0==__rho_10_^post_50 && __rho_11_^0==__rho_11_^post_50 && __rho_1_^0==__rho_1_^post_50 && __rho_2_^0==__rho_2_^post_50 && __rho_3_^0==__rho_3_^post_50 && __rho_4_^0==__rho_4_^post_50 && __rho_5_^0==__rho_5_^post_50 && __rho_666_^0==__rho_666_^post_50 && __rho_7_^0==__rho_7_^post_50 && __rho_8_^0==__rho_8_^post_50 && __rho_9_^0==__rho_9_^post_50 && a11^0==a11^post_50 && a1818^0==a1818^post_50 && a2525^0==a2525^post_50 && a2828^0==a2828^post_50 && a3131^0==a3131^post_50 && a3232^0==a3232^post_50 && a3434^0==a3434^post_50 && a3737^0==a3737^post_50 && a3838^0==a3838^post_50 && a4343^0==a4343^post_50 && a4545^0==a4545^post_50 && a77^0==a77^post_50 && b22^0==b22^post_50 && b2626^0==b2626^post_50 && b2929^0==b2929^post_50 && b3333^0==b3333^post_50 && b3535^0==b3535^post_50 && i^0==i^post_50 && i___01313^0==i___01313^post_50 && i___01717^0==i___01717^post_50 && i___02020^0==i___02020^post_50 && i___02424^0==i___02424^post_50 && i___04747^0==i___04747^post_50 && i___099^0==i___099^post_50 && ioA^0==ioA^post_50 && ioR^0==ioR^post_50 && k1^0==k1^post_50 && k2^0==k2^post_50 && k3^0==k3^post_50 && k4^0==k4^post_50 && ntStatus^0==ntStatus^post_50 && pIrb^0==pIrb^post_50 && phi_io_compl^0==phi_io_compl^post_50 && phi_nSUC_ret^0==phi_nSUC_ret^post_50 && prevCancel^0==prevCancel^post_50 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_50 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_50 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_50 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_50 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_50 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_50 ], cost: 2
     67: l1 -> l32 : AsyncAddressData^0'=AsyncAddressData^post_51, BusResetIrp^0'=BusResetIrp^post_51, CromData^0'=CromData^post_51, DeviceObject^0'=DeviceObject^post_51, Irp^0'=Irp^post_51, Irql^0'=Irql^post_51, IsochDetachData^0'=IsochDetachData^post_51, IsochResourceData^0'=IsochResourceData^post_51, ResourceIrp^0'=ResourceIrp^post_51, StackSize^0'=StackSize^post_51, __rho_10_^0'=__rho_10_^post_51, __rho_11_^0'=__rho_11_^post_51, __rho_12_^0'=__rho_12_^post_51, __rho_1_^0'=__rho_1_^post_51, __rho_2_^0'=__rho_2_^post_51, __rho_3_^0'=__rho_3_^post_51, __rho_4_^0'=__rho_4_^post_51, __rho_5_^0'=__rho_5_^post_51, __rho_666_^0'=__rho_666_^post_51, __rho_7_^0'=__rho_7_^post_51, __rho_8_^0'=__rho_8_^post_51, __rho_9_^0'=__rho_9_^post_51, a11^0'=a11^post_51, a1818^0'=a1818^post_51, a2525^0'=a2525^post_51, a2828^0'=a2828^post_51, a3131^0'=a3131^post_51, a3232^0'=a3232^post_51, a3434^0'=a3434^post_51, a3737^0'=a3737^post_51, a3838^0'=a3838^post_51, a4343^0'=a4343^post_51, a4545^0'=a4545^post_51, a77^0'=a77^post_51, b22^0'=b22^post_51, b2626^0'=b2626^post_51, b2929^0'=b2929^post_51, b3333^0'=b3333^post_51, b3535^0'=b3535^post_51, i^0'=i^post_51, i___01313^0'=i___01313^post_51, i___01717^0'=i___01717^post_51, i___02020^0'=i___02020^post_51, i___02424^0'=i___02424^post_51, i___04040^0'=i___04040^post_51, i___04747^0'=i___04747^post_51, i___099^0'=i___099^post_51, ioA^0'=ioA^post_51, ioR^0'=ioR^post_51, k1^0'=k1^post_51, k2^0'=k2^post_51, k3^0'=k3^post_51, k4^0'=k4^post_51, k5^0'=k5^post_51, keA^0'=keA^post_51, keR^0'=keR^post_51, ntStatus^0'=ntStatus^post_51, pIrb^0'=pIrb^post_51, phi_io_compl^0'=phi_io_compl^post_51, phi_nSUC_ret^0'=phi_nSUC_ret^post_51, prevCancel^0'=prevCancel^post_51, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_51, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_51, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_51, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_51, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_51, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_51, [ 1<=k4^0 && k4^post_51==-1+k4^0 && i___02424^post_51==Irql^0 && keR^1_4_2==1 && keR^post_51==0 && AsyncAddressData^0==AsyncAddressData^post_51 && BusResetIrp^0==BusResetIrp^post_51 && CromData^0==CromData^post_51 && DeviceObject^0==DeviceObject^post_51 && Irp^0==Irp^post_51 && Irql^0==Irql^post_51 && IsochDetachData^0==IsochDetachData^post_51 && ResourceIrp^0==ResourceIrp^post_51 && StackSize^0==StackSize^post_51 && __rho_10_^0==__rho_10_^post_51 && __rho_11_^0==__rho_11_^post_51 && __rho_12_^0==__rho_12_^post_51 && __rho_1_^0==__rho_1_^post_51 && __rho_2_^0==__rho_2_^post_51 && __rho_3_^0==__rho_3_^post_51 && __rho_4_^0==__rho_4_^post_51 && __rho_5_^0==__rho_5_^post_51 && __rho_666_^0==__rho_666_^post_51 && __rho_7_^0==__rho_7_^post_51 && __rho_8_^0==__rho_8_^post_51 && __rho_9_^0==__rho_9_^post_51 && a11^0==a11^post_51 && a1818^0==a1818^post_51 && a2525^0==a2525^post_51 && a2828^0==a2828^post_51 && a3131^0==a3131^post_51 && a3232^0==a3232^post_51 && a3434^0==a3434^post_51 && a3737^0==a3737^post_51 && a3838^0==a3838^post_51 && a4343^0==a4343^post_51 && a4545^0==a4545^post_51 && a77^0==a77^post_51 && b22^0==b22^post_51 && b2626^0==b2626^post_51 && b2929^0==b2929^post_51 && b3333^0==b3333^post_51 && b3535^0==b3535^post_51 && i^0==i^post_51 && i___01313^0==i___01313^post_51 && i___01717^0==i___01717^post_51 && i___02020^0==i___02020^post_51 && i___04040^0==i___04040^post_51 && i___04747^0==i___04747^post_51 && i___099^0==i___099^post_51 && ioA^0==ioA^post_51 && ioR^0==ioR^post_51 && k1^0==k1^post_51 && k2^0==k2^post_51 && k3^0==k3^post_51 && k5^0==k5^post_51 && 0==keA^post_51 && ntStatus^0==ntStatus^post_51 && pIrb^0==pIrb^post_51 && phi_io_compl^0==phi_io_compl^post_51 && phi_nSUC_ret^0==phi_nSUC_ret^post_51 && prevCancel^0==prevCancel^post_51 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_51 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_51 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_51 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_51 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_51 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_51 ], cost: 2
     64: l2 -> l1 : __rho_11_^0'=__rho_11_^post_1, i___02020^0'=Irql^0, k4^0'=__rho_11_^post_1, keA^0'=0, keR^0'=0, [ k3^0<=0 ], cost: 2
     65: l2 -> l2 : IsochDetachData^0'=IsochDetachData^post_2, a1818^0'=IsochDetachData^post_2, i^0'=i^post_2, i___01717^0'=Irql^0, k3^0'=-1+k3^0, keA^0'=0, keR^0'=0, [ 1<=k3^0 ], cost: 2
     62: l4 -> l9 : AsyncAddressData^0'=AsyncAddressData^post_14, __rho_7_^0'=__rho_7_^post_14, k2^0'=-1+k2^0, [ 1<=k2^0 ], cost: 2
     63: l4 -> l2 : __rho_10_^0'=__rho_10_^post_15, i___01313^0'=Irql^0, k3^0'=__rho_10_^post_15, keR^0'=0, [ k2^0<=0 ], cost: 2
     87: l5 -> l4 : [], cost: 2
     88: l7 -> l5 : __rho_9_^0'=__rho_9_^post_7, [], cost: 2
     89: l9 -> l7 : __rho_8_^0'=__rho_8_^post_10, [], cost: 2
     60: l10 -> l18 : CromData^0'=CromData^post_27, k1^0'=-1+k1^0, [ 1<=k1^0 ], cost: 2
     61: l10 -> l4 : __rho_4_^0'=__rho_4_^post_28, i___099^0'=Irql^0, k2^0'=__rho_4_^post_28, keA^0'=0, keR^0'=0, [ k1^0<=0 ], cost: 2
     17: l13 -> l10 : a77^0'=CromData^0, [], cost: 1
     90: l15 -> l13 : __rho_3_^0'=__rho_3_^post_21, [], cost: 2
     24: l18 -> l10 : [ CromData^0<=0 ], cost: 1
     91: l18 -> l15 : __rho_2_^0'=__rho_2_^post_26, [ 1<=CromData^0 ], cost: 2
     68: l19 -> l19 : BusResetIrp^0'=BusResetIrp^post_38, a4343^0'=0, a4545^0'=BusResetIrp^post_38, k5^0'=-1+k5^0, phi_io_compl^0'=1, prevCancel^0'=0, ret_IoSetCancelRoutine4444^0'=0, [ 1<=k5^0 ], cost: 2
     69: l19 -> l26 : i___04747^0'=Irql^0, keR^0'=0, [ k5^0<=0 ], cost: 2
     29: l21 -> l10 : __rho_5_^0'=__rho_5_^post_30, k1^0'=__rho_5_^post_30, keA^0'=0, ntStatus^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, [], cost: 1
     57: l26 -> [35] : [ -2+ntStatus^0==0 ], cost: NONTERM
     70: l26 -> [35] : [ 3<=ntStatus^0 ], cost: NONTERM
     71: l26 -> [35] : [ 1+ntStatus^0<=2 ], cost: NONTERM
     47: l32 -> l1 : [ IsochResourceData^0<=0 ], cost: 1
     72: l32 -> l1 : ResourceIrp^0'=0, StackSize^0'=a2525^post_49, a2525^0'=a2525^post_49, b2626^0'=0, pIrb^0'=pIrb^post_49, ret_IoAllocateIrp2727^0'=0, [ 1<=IsochResourceData^0 ], cost: 2
     58: l34 -> l21 : AsyncAddressData^0'=AsyncAddressData^post_52, BusResetIrp^0'=BusResetIrp^post_52, CromData^0'=CromData^post_52, DeviceObject^0'=DeviceObject^post_52, Irp^0'=Irp^post_52, Irql^0'=Irql^post_52, IsochDetachData^0'=IsochDetachData^post_52, IsochResourceData^0'=IsochResourceData^post_52, ResourceIrp^0'=ResourceIrp^post_52, StackSize^0'=StackSize^post_52, __rho_10_^0'=__rho_10_^post_52, __rho_11_^0'=__rho_11_^post_52, __rho_12_^0'=__rho_12_^post_52, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_52, __rho_3_^0'=__rho_3_^post_52, __rho_4_^0'=__rho_4_^post_52, __rho_5_^0'=__rho_5_^post_52, __rho_666_^0'=__rho_666_^post_52, __rho_7_^0'=__rho_7_^post_52, __rho_8_^0'=__rho_8_^post_52, __rho_9_^0'=__rho_9_^post_52, a11^0'=a11^post_52, a1818^0'=a1818^post_52, a2525^0'=a2525^post_52, a2828^0'=a2828^post_52, a3131^0'=a3131^post_52, a3232^0'=a3232^post_52, a3434^0'=a3434^post_52, a3737^0'=a3737^post_52, a3838^0'=a3838^post_52, a4343^0'=a4343^post_52, a4545^0'=a4545^post_52, a77^0'=a77^post_52, b22^0'=b22^post_52, b2626^0'=b2626^post_52, b2929^0'=b2929^post_52, b3333^0'=b3333^post_52, b3535^0'=b3535^post_52, i^0'=i^post_52, i___01313^0'=i___01313^post_52, i___01717^0'=i___01717^post_52, i___02020^0'=i___02020^post_52, i___02424^0'=i___02424^post_52, i___04040^0'=i___04040^post_52, i___04747^0'=i___04747^post_52, i___099^0'=i___099^post_52, ioA^0'=ioA^post_52, ioR^0'=ioR^post_52, k1^0'=k1^post_52, k2^0'=k2^post_52, k3^0'=k3^post_52, k4^0'=k4^post_52, k5^0'=k5^post_52, keA^0'=keA^post_52, keR^0'=keR^post_52, ntStatus^0'=ntStatus^post_52, pIrb^0'=pIrb^post_52, phi_io_compl^0'=phi_io_compl^post_52, phi_nSUC_ret^0'=phi_nSUC_ret^post_52, prevCancel^0'=prevCancel^post_52, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_52, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_52, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_52, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_52, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_52, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_52, [ AsyncAddressData^0==AsyncAddressData^post_53 && BusResetIrp^0==BusResetIrp^post_53 && CromData^0==CromData^post_53 && DeviceObject^0==DeviceObject^post_53 && Irp^0==Irp^post_53 && Irql^0==Irql^post_53 && IsochDetachData^0==IsochDetachData^post_53 && IsochResourceData^0==IsochResourceData^post_53 && ResourceIrp^0==ResourceIrp^post_53 && StackSize^0==StackSize^post_53 && __rho_10_^0==__rho_10_^post_53 && __rho_11_^0==__rho_11_^post_53 && __rho_12_^0==__rho_12_^post_53 && __rho_1_^0==__rho_1_^post_53 && __rho_2_^0==__rho_2_^post_53 && __rho_3_^0==__rho_3_^post_53 && __rho_4_^0==__rho_4_^post_53 && __rho_5_^0==__rho_5_^post_53 && __rho_666_^0==__rho_666_^post_53 && __rho_7_^0==__rho_7_^post_53 && __rho_8_^0==__rho_8_^post_53 && __rho_9_^0==__rho_9_^post_53 && a11^0==a11^post_53 && a1818^0==a1818^post_53 && a2525^0==a2525^post_53 && a2828^0==a2828^post_53 && a3131^0==a3131^post_53 && a3232^0==a3232^post_53 && a3434^0==a3434^post_53 && a3737^0==a3737^post_53 && a3838^0==a3838^post_53 && a4343^0==a4343^post_53 && a4545^0==a4545^post_53 && a77^0==a77^post_53 && b22^0==b22^post_53 && b2626^0==b2626^post_53 && b2929^0==b2929^post_53 && b3333^0==b3333^post_53 && b3535^0==b3535^post_53 && i^0==i^post_53 && i___01313^0==i___01313^post_53 && i___01717^0==i___01717^post_53 && i___02020^0==i___02020^post_53 && i___02424^0==i___02424^post_53 && i___04040^0==i___04040^post_53 && i___04747^0==i___04747^post_53 && i___099^0==i___099^post_53 && ioA^0==ioA^post_53 && ioR^0==ioR^post_53 && k1^0==k1^post_53 && k2^0==k2^post_53 && k3^0==k3^post_53 && k4^0==k4^post_53 && k5^0==k5^post_53 && keA^0==keA^post_53 && keR^0==keR^post_53 && ntStatus^0==ntStatus^post_53 && pIrb^0==pIrb^post_53 && phi_io_compl^0==phi_io_compl^post_53 && phi_nSUC_ret^0==phi_nSUC_ret^post_53 && prevCancel^0==prevCancel^post_53 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_53 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_53 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_53 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_53 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_53 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_53 && ioR^post_52==0 && ioA^post_52==ioR^post_52 && keR^post_52==ioA^post_52 && keA^post_52==keR^post_52 && phi_nSUC_ret^post_52==0 && phi_io_compl^post_52==0 && AsyncAddressData^post_53==AsyncAddressData^post_52 && BusResetIrp^post_53==BusResetIrp^post_52 && CromData^post_53==CromData^post_52 && DeviceObject^post_53==DeviceObject^post_52 && Irp^post_53==Irp^post_52 && Irql^post_53==Irql^post_52 && IsochDetachData^post_53==IsochDetachData^post_52 && IsochResourceData^post_53==IsochResourceData^post_52 && ResourceIrp^post_53==ResourceIrp^post_52 && StackSize^post_53==StackSize^post_52 && __rho_10_^post_53==__rho_10_^post_52 && __rho_11_^post_53==__rho_11_^post_52 && __rho_12_^post_53==__rho_12_^post_52 && __rho_2_^post_53==__rho_2_^post_52 && __rho_3_^post_53==__rho_3_^post_52 && __rho_4_^post_53==__rho_4_^post_52 && __rho_5_^post_53==__rho_5_^post_52 && __rho_7_^post_53==__rho_7_^post_52 && __rho_8_^post_53==__rho_8_^post_52 && __rho_9_^post_53==__rho_9_^post_52 && a11^post_53==a11^post_52 && a1818^post_53==a1818^post_52 && a2525^post_53==a2525^post_52 && a2828^post_53==a2828^post_52 && a3131^post_53==a3131^post_52 && a3232^post_53==a3232^post_52 && a3434^post_53==a3434^post_52 && a3737^post_53==a3737^post_52 && a3838^post_53==a3838^post_52 && a4343^post_53==a4343^post_52 && a4545^post_53==a4545^post_52 && a77^post_53==a77^post_52 && b22^post_53==b22^post_52 && b2626^post_53==b2626^post_52 && b2929^post_53==b2929^post_52 && b3333^post_53==b3333^post_52 && b3535^post_53==b3535^post_52 && i^post_53==i^post_52 && i___01313^post_53==i___01313^post_52 && i___01717^post_53==i___01717^post_52 && i___02020^post_53==i___02020^post_52 && i___02424^post_53==i___02424^post_52 && i___04040^post_53==i___04040^post_52 && i___04747^post_53==i___04747^post_52 && i___099^post_53==i___099^post_52 && k1^post_53==k1^post_52 && k2^post_53==k2^post_52 && k3^post_53==k3^post_52 && k4^post_53==k4^post_52 && k5^post_53==k5^post_52 && ntStatus^post_53==ntStatus^post_52 && pIrb^post_53==pIrb^post_52 && prevCancel^post_53==prevCancel^post_52 && ret_ExAllocatePool3030^post_53==ret_ExAllocatePool3030^post_52 && ret_IoAllocateIrp2727^post_53==ret_IoAllocateIrp2727^post_52 && ret_IoSetCancelRoutine4444^post_53==ret_IoSetCancelRoutine4444^post_52 && ret_IoSetDeviceInterfaceState44^post_53==ret_IoSetDeviceInterfaceState44^post_52 && ret_t1394Diag_PnpStopDevice33^post_53==ret_t1394Diag_PnpStopDevice33^post_52 && ret_t1394_SubmitIrpSynch3636^post_53==ret_t1394_SubmitIrpSynch3636^post_52 && __rho_1_^post_52<=0 ], cost: 3
     59: l34 -> l21 : AsyncAddressData^0'=AsyncAddressData^post_52, BusResetIrp^0'=BusResetIrp^post_52, CromData^0'=CromData^post_52, DeviceObject^0'=DeviceObject^post_52, Irp^0'=Irp^post_52, Irql^0'=Irql^post_52, IsochDetachData^0'=IsochDetachData^post_52, IsochResourceData^0'=IsochResourceData^post_52, ResourceIrp^0'=ResourceIrp^post_52, StackSize^0'=StackSize^post_52, __rho_10_^0'=__rho_10_^post_52, __rho_11_^0'=__rho_11_^post_52, __rho_12_^0'=__rho_12_^post_52, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_52, __rho_3_^0'=__rho_3_^post_52, __rho_4_^0'=__rho_4_^post_52, __rho_5_^0'=__rho_5_^post_52, __rho_666_^0'=__rho_666_^post_52, __rho_7_^0'=__rho_7_^post_52, __rho_8_^0'=__rho_8_^post_52, __rho_9_^0'=__rho_9_^post_52, a11^0'=DeviceObject^post_52, a1818^0'=a1818^post_52, a2525^0'=a2525^post_52, a2828^0'=a2828^post_52, a3131^0'=a3131^post_52, a3232^0'=a3232^post_52, a3434^0'=a3434^post_52, a3737^0'=a3737^post_52, a3838^0'=a3838^post_52, a4343^0'=a4343^post_52, a4545^0'=a4545^post_52, a77^0'=a77^post_52, b22^0'=Irp^post_52, b2626^0'=b2626^post_52, b2929^0'=b2929^post_52, b3333^0'=b3333^post_52, b3535^0'=b3535^post_52, i^0'=i^post_52, i___01313^0'=i___01313^post_52, i___01717^0'=i___01717^post_52, i___02020^0'=i___02020^post_52, i___02424^0'=i___02424^post_52, i___04040^0'=i___04040^post_52, i___04747^0'=i___04747^post_52, i___099^0'=i___099^post_52, ioA^0'=ioA^post_52, ioR^0'=ioR^post_52, k1^0'=k1^post_52, k2^0'=k2^post_52, k3^0'=k3^post_52, k4^0'=k4^post_52, k5^0'=k5^post_52, keA^0'=keA^post_52, keR^0'=keR^post_52, ntStatus^0'=0, pIrb^0'=pIrb^post_52, phi_io_compl^0'=phi_io_compl^post_52, phi_nSUC_ret^0'=phi_nSUC_ret^post_52, prevCancel^0'=prevCancel^post_52, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_52, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_52, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_52, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_52, ret_t1394Diag_PnpStopDevice33^0'=0, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_52, [ AsyncAddressData^0==AsyncAddressData^post_53 && BusResetIrp^0==BusResetIrp^post_53 && CromData^0==CromData^post_53 && DeviceObject^0==DeviceObject^post_53 && Irp^0==Irp^post_53 && Irql^0==Irql^post_53 && IsochDetachData^0==IsochDetachData^post_53 && IsochResourceData^0==IsochResourceData^post_53 && ResourceIrp^0==ResourceIrp^post_53 && StackSize^0==StackSize^post_53 && __rho_10_^0==__rho_10_^post_53 && __rho_11_^0==__rho_11_^post_53 && __rho_12_^0==__rho_12_^post_53 && __rho_1_^0==__rho_1_^post_53 && __rho_2_^0==__rho_2_^post_53 && __rho_3_^0==__rho_3_^post_53 && __rho_4_^0==__rho_4_^post_53 && __rho_5_^0==__rho_5_^post_53 && __rho_666_^0==__rho_666_^post_53 && __rho_7_^0==__rho_7_^post_53 && __rho_8_^0==__rho_8_^post_53 && __rho_9_^0==__rho_9_^post_53 && a11^0==a11^post_53 && a1818^0==a1818^post_53 && a2525^0==a2525^post_53 && a2828^0==a2828^post_53 && a3131^0==a3131^post_53 && a3232^0==a3232^post_53 && a3434^0==a3434^post_53 && a3737^0==a3737^post_53 && a3838^0==a3838^post_53 && a4343^0==a4343^post_53 && a4545^0==a4545^post_53 && a77^0==a77^post_53 && b22^0==b22^post_53 && b2626^0==b2626^post_53 && b2929^0==b2929^post_53 && b3333^0==b3333^post_53 && b3535^0==b3535^post_53 && i^0==i^post_53 && i___01313^0==i___01313^post_53 && i___01717^0==i___01717^post_53 && i___02020^0==i___02020^post_53 && i___02424^0==i___02424^post_53 && i___04040^0==i___04040^post_53 && i___04747^0==i___04747^post_53 && i___099^0==i___099^post_53 && ioA^0==ioA^post_53 && ioR^0==ioR^post_53 && k1^0==k1^post_53 && k2^0==k2^post_53 && k3^0==k3^post_53 && k4^0==k4^post_53 && k5^0==k5^post_53 && keA^0==keA^post_53 && keR^0==keR^post_53 && ntStatus^0==ntStatus^post_53 && pIrb^0==pIrb^post_53 && phi_io_compl^0==phi_io_compl^post_53 && phi_nSUC_ret^0==phi_nSUC_ret^post_53 && prevCancel^0==prevCancel^post_53 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_53 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_53 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_53 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_53 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_53 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_53 && ioR^post_52==0 && ioA^post_52==ioR^post_52 && keR^post_52==ioA^post_52 && keA^post_52==keR^post_52 && phi_nSUC_ret^post_52==0 && phi_io_compl^post_52==0 && AsyncAddressData^post_53==AsyncAddressData^post_52 && BusResetIrp^post_53==BusResetIrp^post_52 && CromData^post_53==CromData^post_52 && DeviceObject^post_53==DeviceObject^post_52 && Irp^post_53==Irp^post_52 && Irql^post_53==Irql^post_52 && IsochDetachData^post_53==IsochDetachData^post_52 && IsochResourceData^post_53==IsochResourceData^post_52 && ResourceIrp^post_53==ResourceIrp^post_52 && StackSize^post_53==StackSize^post_52 && __rho_10_^post_53==__rho_10_^post_52 && __rho_11_^post_53==__rho_11_^post_52 && __rho_12_^post_53==__rho_12_^post_52 && __rho_2_^post_53==__rho_2_^post_52 && __rho_3_^post_53==__rho_3_^post_52 && __rho_4_^post_53==__rho_4_^post_52 && __rho_5_^post_53==__rho_5_^post_52 && __rho_7_^post_53==__rho_7_^post_52 && __rho_8_^post_53==__rho_8_^post_52 && __rho_9_^post_53==__rho_9_^post_52 && a11^post_53==a11^post_52 && a1818^post_53==a1818^post_52 && a2525^post_53==a2525^post_52 && a2828^post_53==a2828^post_52 && a3131^post_53==a3131^post_52 && a3232^post_53==a3232^post_52 && a3434^post_53==a3434^post_52 && a3737^post_53==a3737^post_52 && a3838^post_53==a3838^post_52 && a4343^post_53==a4343^post_52 && a4545^post_53==a4545^post_52 && a77^post_53==a77^post_52 && b22^post_53==b22^post_52 && b2626^post_53==b2626^post_52 && b2929^post_53==b2929^post_52 && b3333^post_53==b3333^post_52 && b3535^post_53==b3535^post_52 && i^post_53==i^post_52 && i___01313^post_53==i___01313^post_52 && i___01717^post_53==i___01717^post_52 && i___02020^post_53==i___02020^post_52 && i___02424^post_53==i___02424^post_52 && i___04040^post_53==i___04040^post_52 && i___04747^post_53==i___04747^post_52 && i___099^post_53==i___099^post_52 && k1^post_53==k1^post_52 && k2^post_53==k2^post_52 && k3^post_53==k3^post_52 && k4^post_53==k4^post_52 && k5^post_53==k5^post_52 && ntStatus^post_53==ntStatus^post_52 && pIrb^post_53==pIrb^post_52 && prevCancel^post_53==prevCancel^post_52 && ret_ExAllocatePool3030^post_53==ret_ExAllocatePool3030^post_52 && ret_IoAllocateIrp2727^post_53==ret_IoAllocateIrp2727^post_52 && ret_IoSetCancelRoutine4444^post_53==ret_IoSetCancelRoutine4444^post_52 && ret_IoSetDeviceInterfaceState44^post_53==ret_IoSetDeviceInterfaceState44^post_52 && ret_t1394Diag_PnpStopDevice33^post_53==ret_t1394Diag_PnpStopDevice33^post_52 && ret_t1394_SubmitIrpSynch3636^post_53==ret_t1394_SubmitIrpSynch3636^post_52 && 1<=__rho_1_^post_52 ], cost: 3

Accelerating simple loops of location 2.
   Accelerating the following rules:
     65: l2 -> l2 : IsochDetachData^0'=IsochDetachData^post_2, a1818^0'=IsochDetachData^post_2, i^0'=i^post_2, i___01717^0'=Irql^0, k3^0'=-1+k3^0, keA^0'=0, keR^0'=0, [ 1<=k3^0 ], cost: 2

   Accelerated rule 65 with backward acceleration, yielding the new rule 92.
[accelerate] Nesting with 1 inner and 1 outer candidates
   Removing the simple loops: 65.

Accelerating simple loops of location 19.
   Accelerating the following rules:
     68: l19 -> l19 : BusResetIrp^0'=BusResetIrp^post_38, a4343^0'=0, a4545^0'=BusResetIrp^post_38, k5^0'=-1+k5^0, phi_io_compl^0'=1, prevCancel^0'=0, ret_IoSetCancelRoutine4444^0'=0, [ 1<=k5^0 ], cost: 2

   Accelerated rule 68 with backward acceleration, yielding the new rule 93.
[accelerate] Nesting with 1 inner and 1 outer candidates
   Removing the simple loops: 68.

Accelerated all simple loops using metering functions (where possible):
   Start location: l34
     66: l1 -> l19 : AsyncAddressData^0'=AsyncAddressData^post_50, BusResetIrp^0'=BusResetIrp^post_50, CromData^0'=CromData^post_50, DeviceObject^0'=DeviceObject^post_50, Irp^0'=Irp^post_50, Irql^0'=Irql^post_50, IsochDetachData^0'=IsochDetachData^post_50, IsochResourceData^0'=IsochResourceData^post_50, ResourceIrp^0'=ResourceIrp^post_50, StackSize^0'=StackSize^post_50, __rho_10_^0'=__rho_10_^post_50, __rho_11_^0'=__rho_11_^post_50, __rho_12_^0'=__rho_12_^post_50, __rho_1_^0'=__rho_1_^post_50, __rho_2_^0'=__rho_2_^post_50, __rho_3_^0'=__rho_3_^post_50, __rho_4_^0'=__rho_4_^post_50, __rho_5_^0'=__rho_5_^post_50, __rho_666_^0'=__rho_666_^post_50, __rho_7_^0'=__rho_7_^post_50, __rho_8_^0'=__rho_8_^post_50, __rho_9_^0'=__rho_9_^post_50, a11^0'=a11^post_50, a1818^0'=a1818^post_50, a2525^0'=a2525^post_50, a2828^0'=a2828^post_50, a3131^0'=a3131^post_50, a3232^0'=a3232^post_50, a3434^0'=a3434^post_50, a3737^0'=a3737^post_50, a3838^0'=a3838^post_50, a4343^0'=a4343^post_50, a4545^0'=a4545^post_50, a77^0'=a77^post_50, b22^0'=b22^post_50, b2626^0'=b2626^post_50, b2929^0'=b2929^post_50, b3333^0'=b3333^post_50, b3535^0'=b3535^post_50, i^0'=i^post_50, i___01313^0'=i___01313^post_50, i___01717^0'=i___01717^post_50, i___02020^0'=i___02020^post_50, i___02424^0'=i___02424^post_50, i___04040^0'=i___04040^post_50, i___04747^0'=i___04747^post_50, i___099^0'=i___099^post_50, ioA^0'=ioA^post_50, ioR^0'=ioR^post_50, k1^0'=k1^post_50, k2^0'=k2^post_50, k3^0'=k3^post_50, k4^0'=k4^post_50, k5^0'=k5^post_50, keA^0'=keA^post_50, keR^0'=keR^post_50, ntStatus^0'=ntStatus^post_50, pIrb^0'=pIrb^post_50, phi_io_compl^0'=phi_io_compl^post_50, phi_nSUC_ret^0'=phi_nSUC_ret^post_50, prevCancel^0'=prevCancel^post_50, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_50, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_50, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_50, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_50, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_50, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_50, [ k4^0<=0 && i___04040^post_50==Irql^0 && keR^1_4_1==1 && keR^post_50==0 && keA^1_5==1 && keA^post_50==0 && k5^post_50==__rho_12_^post_50 && AsyncAddressData^0==AsyncAddressData^post_50 && BusResetIrp^0==BusResetIrp^post_50 && CromData^0==CromData^post_50 && DeviceObject^0==DeviceObject^post_50 && Irp^0==Irp^post_50 && Irql^0==Irql^post_50 && IsochDetachData^0==IsochDetachData^post_50 && IsochResourceData^0==IsochResourceData^post_50 && ResourceIrp^0==ResourceIrp^post_50 && StackSize^0==StackSize^post_50 && __rho_10_^0==__rho_10_^post_50 && __rho_11_^0==__rho_11_^post_50 && __rho_1_^0==__rho_1_^post_50 && __rho_2_^0==__rho_2_^post_50 && __rho_3_^0==__rho_3_^post_50 && __rho_4_^0==__rho_4_^post_50 && __rho_5_^0==__rho_5_^post_50 && __rho_666_^0==__rho_666_^post_50 && __rho_7_^0==__rho_7_^post_50 && __rho_8_^0==__rho_8_^post_50 && __rho_9_^0==__rho_9_^post_50 && a11^0==a11^post_50 && a1818^0==a1818^post_50 && a2525^0==a2525^post_50 && a2828^0==a2828^post_50 && a3131^0==a3131^post_50 && a3232^0==a3232^post_50 && a3434^0==a3434^post_50 && a3737^0==a3737^post_50 && a3838^0==a3838^post_50 && a4343^0==a4343^post_50 && a4545^0==a4545^post_50 && a77^0==a77^post_50 && b22^0==b22^post_50 && b2626^0==b2626^post_50 && b2929^0==b2929^post_50 && b3333^0==b3333^post_50 && b3535^0==b3535^post_50 && i^0==i^post_50 && i___01313^0==i___01313^post_50 && i___01717^0==i___01717^post_50 && i___02020^0==i___02020^post_50 && i___02424^0==i___02424^post_50 && i___04747^0==i___04747^post_50 && i___099^0==i___099^post_50 && ioA^0==ioA^post_50 && ioR^0==ioR^post_50 && k1^0==k1^post_50 && k2^0==k2^post_50 && k3^0==k3^post_50 && k4^0==k4^post_50 && ntStatus^0==ntStatus^post_50 && pIrb^0==pIrb^post_50 && phi_io_compl^0==phi_io_compl^post_50 && phi_nSUC_ret^0==phi_nSUC_ret^post_50 && prevCancel^0==prevCancel^post_50 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_50 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_50 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_50 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_50 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_50 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_50 ], cost: 2
     67: l1 -> l32 : AsyncAddressData^0'=AsyncAddressData^post_51, BusResetIrp^0'=BusResetIrp^post_51, CromData^0'=CromData^post_51, DeviceObject^0'=DeviceObject^post_51, Irp^0'=Irp^post_51, Irql^0'=Irql^post_51, IsochDetachData^0'=IsochDetachData^post_51, IsochResourceData^0'=IsochResourceData^post_51, ResourceIrp^0'=ResourceIrp^post_51, StackSize^0'=StackSize^post_51, __rho_10_^0'=__rho_10_^post_51, __rho_11_^0'=__rho_11_^post_51, __rho_12_^0'=__rho_12_^post_51, __rho_1_^0'=__rho_1_^post_51, __rho_2_^0'=__rho_2_^post_51, __rho_3_^0'=__rho_3_^post_51, __rho_4_^0'=__rho_4_^post_51, __rho_5_^0'=__rho_5_^post_51, __rho_666_^0'=__rho_666_^post_51, __rho_7_^0'=__rho_7_^post_51, __rho_8_^0'=__rho_8_^post_51, __rho_9_^0'=__rho_9_^post_51, a11^0'=a11^post_51, a1818^0'=a1818^post_51, a2525^0'=a2525^post_51, a2828^0'=a2828^post_51, a3131^0'=a3131^post_51, a3232^0'=a3232^post_51, a3434^0'=a3434^post_51, a3737^0'=a3737^post_51, a3838^0'=a3838^post_51, a4343^0'=a4343^post_51, a4545^0'=a4545^post_51, a77^0'=a77^post_51, b22^0'=b22^post_51, b2626^0'=b2626^post_51, b2929^0'=b2929^post_51, b3333^0'=b3333^post_51, b3535^0'=b3535^post_51, i^0'=i^post_51, i___01313^0'=i___01313^post_51, i___01717^0'=i___01717^post_51, i___02020^0'=i___02020^post_51, i___02424^0'=i___02424^post_51, i___04040^0'=i___04040^post_51, i___04747^0'=i___04747^post_51, i___099^0'=i___099^post_51, ioA^0'=ioA^post_51, ioR^0'=ioR^post_51, k1^0'=k1^post_51, k2^0'=k2^post_51, k3^0'=k3^post_51, k4^0'=k4^post_51, k5^0'=k5^post_51, keA^0'=keA^post_51, keR^0'=keR^post_51, ntStatus^0'=ntStatus^post_51, pIrb^0'=pIrb^post_51, phi_io_compl^0'=phi_io_compl^post_51, phi_nSUC_ret^0'=phi_nSUC_ret^post_51, prevCancel^0'=prevCancel^post_51, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_51, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_51, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_51, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_51, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_51, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_51, [ 1<=k4^0 && k4^post_51==-1+k4^0 && i___02424^post_51==Irql^0 && keR^1_4_2==1 && keR^post_51==0 && AsyncAddressData^0==AsyncAddressData^post_51 && BusResetIrp^0==BusResetIrp^post_51 && CromData^0==CromData^post_51 && DeviceObject^0==DeviceObject^post_51 && Irp^0==Irp^post_51 && Irql^0==Irql^post_51 && IsochDetachData^0==IsochDetachData^post_51 && ResourceIrp^0==ResourceIrp^post_51 && StackSize^0==StackSize^post_51 && __rho_10_^0==__rho_10_^post_51 && __rho_11_^0==__rho_11_^post_51 && __rho_12_^0==__rho_12_^post_51 && __rho_1_^0==__rho_1_^post_51 && __rho_2_^0==__rho_2_^post_51 && __rho_3_^0==__rho_3_^post_51 && __rho_4_^0==__rho_4_^post_51 && __rho_5_^0==__rho_5_^post_51 && __rho_666_^0==__rho_666_^post_51 && __rho_7_^0==__rho_7_^post_51 && __rho_8_^0==__rho_8_^post_51 && __rho_9_^0==__rho_9_^post_51 && a11^0==a11^post_51 && a1818^0==a1818^post_51 && a2525^0==a2525^post_51 && a2828^0==a2828^post_51 && a3131^0==a3131^post_51 && a3232^0==a3232^post_51 && a3434^0==a3434^post_51 && a3737^0==a3737^post_51 && a3838^0==a3838^post_51 && a4343^0==a4343^post_51 && a4545^0==a4545^post_51 && a77^0==a77^post_51 && b22^0==b22^post_51 && b2626^0==b2626^post_51 && b2929^0==b2929^post_51 && b3333^0==b3333^post_51 && b3535^0==b3535^post_51 && i^0==i^post_51 && i___01313^0==i___01313^post_51 && i___01717^0==i___01717^post_51 && i___02020^0==i___02020^post_51 && i___04040^0==i___04040^post_51 && i___04747^0==i___04747^post_51 && i___099^0==i___099^post_51 && ioA^0==ioA^post_51 && ioR^0==ioR^post_51 && k1^0==k1^post_51 && k2^0==k2^post_51 && k3^0==k3^post_51 && k5^0==k5^post_51 && 0==keA^post_51 && ntStatus^0==ntStatus^post_51 && pIrb^0==pIrb^post_51 && phi_io_compl^0==phi_io_compl^post_51 && phi_nSUC_ret^0==phi_nSUC_ret^post_51 && prevCancel^0==prevCancel^post_51 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_51 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_51 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_51 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_51 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_51 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_51 ], cost: 2
     64: l2 -> l1 : __rho_11_^0'=__rho_11_^post_1, i___02020^0'=Irql^0, k4^0'=__rho_11_^post_1, keA^0'=0, keR^0'=0, [ k3^0<=0 ], cost: 2
     92: l2 -> l2 : IsochDetachData^0'=IsochDetachData^post_2, a1818^0'=IsochDetachData^post_2, i^0'=i^post_2, i___01717^0'=Irql^0, k3^0'=0, keA^0'=0, keR^0'=0, [ k3^0>=1 ], cost: 2*k3^0
     62: l4 -> l9 : AsyncAddressData^0'=AsyncAddressData^post_14, __rho_7_^0'=__rho_7_^post_14, k2^0'=-1+k2^0, [ 1<=k2^0 ], cost: 2
     63: l4 -> l2 : __rho_10_^0'=__rho_10_^post_15, i___01313^0'=Irql^0, k3^0'=__rho_10_^post_15, keR^0'=0, [ k2^0<=0 ], cost: 2
     87: l5 -> l4 : [], cost: 2
     88: l7 -> l5 : __rho_9_^0'=__rho_9_^post_7, [], cost: 2
     89: l9 -> l7 : __rho_8_^0'=__rho_8_^post_10, [], cost: 2
     60: l10 -> l18 : CromData^0'=CromData^post_27, k1^0'=-1+k1^0, [ 1<=k1^0 ], cost: 2
     61: l10 -> l4 : __rho_4_^0'=__rho_4_^post_28, i___099^0'=Irql^0, k2^0'=__rho_4_^post_28, keA^0'=0, keR^0'=0, [ k1^0<=0 ], cost: 2
     17: l13 -> l10 : a77^0'=CromData^0, [], cost: 1
     90: l15 -> l13 : __rho_3_^0'=__rho_3_^post_21, [], cost: 2
     24: l18 -> l10 : [ CromData^0<=0 ], cost: 1
     91: l18 -> l15 : __rho_2_^0'=__rho_2_^post_26, [ 1<=CromData^0 ], cost: 2
     69: l19 -> l26 : i___04747^0'=Irql^0, keR^0'=0, [ k5^0<=0 ], cost: 2
     93: l19 -> l19 : BusResetIrp^0'=BusResetIrp^post_38, a4343^0'=0, a4545^0'=BusResetIrp^post_38, k5^0'=0, phi_io_compl^0'=1, prevCancel^0'=0, ret_IoSetCancelRoutine4444^0'=0, [ k5^0>=1 ], cost: 2*k5^0
     29: l21 -> l10 : __rho_5_^0'=__rho_5_^post_30, k1^0'=__rho_5_^post_30, keA^0'=0, ntStatus^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, [], cost: 1
     57: l26 -> [35] : [ -2+ntStatus^0==0 ], cost: NONTERM
     70: l26 -> [35] : [ 3<=ntStatus^0 ], cost: NONTERM
     71: l26 -> [35] : [ 1+ntStatus^0<=2 ], cost: NONTERM
     47: l32 -> l1 : [ IsochResourceData^0<=0 ], cost: 1
     72: l32 -> l1 : ResourceIrp^0'=0, StackSize^0'=a2525^post_49, a2525^0'=a2525^post_49, b2626^0'=0, pIrb^0'=pIrb^post_49, ret_IoAllocateIrp2727^0'=0, [ 1<=IsochResourceData^0 ], cost: 2
     58: l34 -> l21 : AsyncAddressData^0'=AsyncAddressData^post_52, BusResetIrp^0'=BusResetIrp^post_52, CromData^0'=CromData^post_52, DeviceObject^0'=DeviceObject^post_52, Irp^0'=Irp^post_52, Irql^0'=Irql^post_52, IsochDetachData^0'=IsochDetachData^post_52, IsochResourceData^0'=IsochResourceData^post_52, ResourceIrp^0'=ResourceIrp^post_52, StackSize^0'=StackSize^post_52, __rho_10_^0'=__rho_10_^post_52, __rho_11_^0'=__rho_11_^post_52, __rho_12_^0'=__rho_12_^post_52, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_52, __rho_3_^0'=__rho_3_^post_52, __rho_4_^0'=__rho_4_^post_52, __rho_5_^0'=__rho_5_^post_52, __rho_666_^0'=__rho_666_^post_52, __rho_7_^0'=__rho_7_^post_52, __rho_8_^0'=__rho_8_^post_52, __rho_9_^0'=__rho_9_^post_52, a11^0'=a11^post_52, a1818^0'=a1818^post_52, a2525^0'=a2525^post_52, a2828^0'=a2828^post_52, a3131^0'=a3131^post_52, a3232^0'=a3232^post_52, a3434^0'=a3434^post_52, a3737^0'=a3737^post_52, a3838^0'=a3838^post_52, a4343^0'=a4343^post_52, a4545^0'=a4545^post_52, a77^0'=a77^post_52, b22^0'=b22^post_52, b2626^0'=b2626^post_52, b2929^0'=b2929^post_52, b3333^0'=b3333^post_52, b3535^0'=b3535^post_52, i^0'=i^post_52, i___01313^0'=i___01313^post_52, i___01717^0'=i___01717^post_52, i___02020^0'=i___02020^post_52, i___02424^0'=i___02424^post_52, i___04040^0'=i___04040^post_52, i___04747^0'=i___04747^post_52, i___099^0'=i___099^post_52, ioA^0'=ioA^post_52, ioR^0'=ioR^post_52, k1^0'=k1^post_52, k2^0'=k2^post_52, k3^0'=k3^post_52, k4^0'=k4^post_52, k5^0'=k5^post_52, keA^0'=keA^post_52, keR^0'=keR^post_52, ntStatus^0'=ntStatus^post_52, pIrb^0'=pIrb^post_52, phi_io_compl^0'=phi_io_compl^post_52, phi_nSUC_ret^0'=phi_nSUC_ret^post_52, prevCancel^0'=prevCancel^post_52, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_52, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_52, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_52, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_52, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_52, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_52, [ AsyncAddressData^0==AsyncAddressData^post_53 && BusResetIrp^0==BusResetIrp^post_53 && CromData^0==CromData^post_53 && DeviceObject^0==DeviceObject^post_53 && Irp^0==Irp^post_53 && Irql^0==Irql^post_53 && IsochDetachData^0==IsochDetachData^post_53 && IsochResourceData^0==IsochResourceData^post_53 && ResourceIrp^0==ResourceIrp^post_53 && StackSize^0==StackSize^post_53 && __rho_10_^0==__rho_10_^post_53 && __rho_11_^0==__rho_11_^post_53 && __rho_12_^0==__rho_12_^post_53 && __rho_1_^0==__rho_1_^post_53 && __rho_2_^0==__rho_2_^post_53 && __rho_3_^0==__rho_3_^post_53 && __rho_4_^0==__rho_4_^post_53 && __rho_5_^0==__rho_5_^post_53 && __rho_666_^0==__rho_666_^post_53 && __rho_7_^0==__rho_7_^post_53 && __rho_8_^0==__rho_8_^post_53 && __rho_9_^0==__rho_9_^post_53 && a11^0==a11^post_53 && a1818^0==a1818^post_53 && a2525^0==a2525^post_53 && a2828^0==a2828^post_53 && a3131^0==a3131^post_53 && a3232^0==a3232^post_53 && a3434^0==a3434^post_53 && a3737^0==a3737^post_53 && a3838^0==a3838^post_53 && a4343^0==a4343^post_53 && a4545^0==a4545^post_53 && a77^0==a77^post_53 && b22^0==b22^post_53 && b2626^0==b2626^post_53 && b2929^0==b2929^post_53 && b3333^0==b3333^post_53 && b3535^0==b3535^post_53 && i^0==i^post_53 && i___01313^0==i___01313^post_53 && i___01717^0==i___01717^post_53 && i___02020^0==i___02020^post_53 && i___02424^0==i___02424^post_53 && i___04040^0==i___04040^post_53 && i___04747^0==i___04747^post_53 && i___099^0==i___099^post_53 && ioA^0==ioA^post_53 && ioR^0==ioR^post_53 && k1^0==k1^post_53 && k2^0==k2^post_53 && k3^0==k3^post_53 && k4^0==k4^post_53 && k5^0==k5^post_53 && keA^0==keA^post_53 && keR^0==keR^post_53 && ntStatus^0==ntStatus^post_53 && pIrb^0==pIrb^post_53 && phi_io_compl^0==phi_io_compl^post_53 && phi_nSUC_ret^0==phi_nSUC_ret^post_53 && prevCancel^0==prevCancel^post_53 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_53 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_53 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_53 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_53 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_53 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_53 && ioR^post_52==0 && ioA^post_52==ioR^post_52 && keR^post_52==ioA^post_52 && keA^post_52==keR^post_52 && phi_nSUC_ret^post_52==0 && phi_io_compl^post_52==0 && AsyncAddressData^post_53==AsyncAddressData^post_52 && BusResetIrp^post_53==BusResetIrp^post_52 && CromData^post_53==CromData^post_52 && DeviceObject^post_53==DeviceObject^post_52 && Irp^post_53==Irp^post_52 && Irql^post_53==Irql^post_52 && IsochDetachData^post_53==IsochDetachData^post_52 && IsochResourceData^post_53==IsochResourceData^post_52 && ResourceIrp^post_53==ResourceIrp^post_52 && StackSize^post_53==StackSize^post_52 && __rho_10_^post_53==__rho_10_^post_52 && __rho_11_^post_53==__rho_11_^post_52 && __rho_12_^post_53==__rho_12_^post_52 && __rho_2_^post_53==__rho_2_^post_52 && __rho_3_^post_53==__rho_3_^post_52 && __rho_4_^post_53==__rho_4_^post_52 && __rho_5_^post_53==__rho_5_^post_52 && __rho_7_^post_53==__rho_7_^post_52 && __rho_8_^post_53==__rho_8_^post_52 && __rho_9_^post_53==__rho_9_^post_52 && a11^post_53==a11^post_52 && a1818^post_53==a1818^post_52 && a2525^post_53==a2525^post_52 && a2828^post_53==a2828^post_52 && a3131^post_53==a3131^post_52 && a3232^post_53==a3232^post_52 && a3434^post_53==a3434^post_52 && a3737^post_53==a3737^post_52 && a3838^post_53==a3838^post_52 && a4343^post_53==a4343^post_52 && a4545^post_53==a4545^post_52 && a77^post_53==a77^post_52 && b22^post_53==b22^post_52 && b2626^post_53==b2626^post_52 && b2929^post_53==b2929^post_52 && b3333^post_53==b3333^post_52 && b3535^post_53==b3535^post_52 && i^post_53==i^post_52 && i___01313^post_53==i___01313^post_52 && i___01717^post_53==i___01717^post_52 && i___02020^post_53==i___02020^post_52 && i___02424^post_53==i___02424^post_52 && i___04040^post_53==i___04040^post_52 && i___04747^post_53==i___04747^post_52 && i___099^post_53==i___099^post_52 && k1^post_53==k1^post_52 && k2^post_53==k2^post_52 && k3^post_53==k3^post_52 && k4^post_53==k4^post_52 && k5^post_53==k5^post_52 && ntStatus^post_53==ntStatus^post_52 && pIrb^post_53==pIrb^post_52 && prevCancel^post_53==prevCancel^post_52 && ret_ExAllocatePool3030^post_53==ret_ExAllocatePool3030^post_52 && ret_IoAllocateIrp2727^post_53==ret_IoAllocateIrp2727^post_52 && ret_IoSetCancelRoutine4444^post_53==ret_IoSetCancelRoutine4444^post_52 && ret_IoSetDeviceInterfaceState44^post_53==ret_IoSetDeviceInterfaceState44^post_52 && ret_t1394Diag_PnpStopDevice33^post_53==ret_t1394Diag_PnpStopDevice33^post_52 && ret_t1394_SubmitIrpSynch3636^post_53==ret_t1394_SubmitIrpSynch3636^post_52 && __rho_1_^post_52<=0 ], cost: 3
     59: l34 -> l21 : AsyncAddressData^0'=AsyncAddressData^post_52, BusResetIrp^0'=BusResetIrp^post_52, CromData^0'=CromData^post_52, DeviceObject^0'=DeviceObject^post_52, Irp^0'=Irp^post_52, Irql^0'=Irql^post_52, IsochDetachData^0'=IsochDetachData^post_52, IsochResourceData^0'=IsochResourceData^post_52, ResourceIrp^0'=ResourceIrp^post_52, StackSize^0'=StackSize^post_52, __rho_10_^0'=__rho_10_^post_52, __rho_11_^0'=__rho_11_^post_52, __rho_12_^0'=__rho_12_^post_52, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_52, __rho_3_^0'=__rho_3_^post_52, __rho_4_^0'=__rho_4_^post_52, __rho_5_^0'=__rho_5_^post_52, __rho_666_^0'=__rho_666_^post_52, __rho_7_^0'=__rho_7_^post_52, __rho_8_^0'=__rho_8_^post_52, __rho_9_^0'=__rho_9_^post_52, a11^0'=DeviceObject^post_52, a1818^0'=a1818^post_52, a2525^0'=a2525^post_52, a2828^0'=a2828^post_52, a3131^0'=a3131^post_52, a3232^0'=a3232^post_52, a3434^0'=a3434^post_52, a3737^0'=a3737^post_52, a3838^0'=a3838^post_52, a4343^0'=a4343^post_52, a4545^0'=a4545^post_52, a77^0'=a77^post_52, b22^0'=Irp^post_52, b2626^0'=b2626^post_52, b2929^0'=b2929^post_52, b3333^0'=b3333^post_52, b3535^0'=b3535^post_52, i^0'=i^post_52, i___01313^0'=i___01313^post_52, i___01717^0'=i___01717^post_52, i___02020^0'=i___02020^post_52, i___02424^0'=i___02424^post_52, i___04040^0'=i___04040^post_52, i___04747^0'=i___04747^post_52, i___099^0'=i___099^post_52, ioA^0'=ioA^post_52, ioR^0'=ioR^post_52, k1^0'=k1^post_52, k2^0'=k2^post_52, k3^0'=k3^post_52, k4^0'=k4^post_52, k5^0'=k5^post_52, keA^0'=keA^post_52, keR^0'=keR^post_52, ntStatus^0'=0, pIrb^0'=pIrb^post_52, phi_io_compl^0'=phi_io_compl^post_52, phi_nSUC_ret^0'=phi_nSUC_ret^post_52, prevCancel^0'=prevCancel^post_52, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_52, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_52, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_52, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_52, ret_t1394Diag_PnpStopDevice33^0'=0, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_52, [ AsyncAddressData^0==AsyncAddressData^post_53 && BusResetIrp^0==BusResetIrp^post_53 && CromData^0==CromData^post_53 && DeviceObject^0==DeviceObject^post_53 && Irp^0==Irp^post_53 && Irql^0==Irql^post_53 && IsochDetachData^0==IsochDetachData^post_53 && IsochResourceData^0==IsochResourceData^post_53 && ResourceIrp^0==ResourceIrp^post_53 && StackSize^0==StackSize^post_53 && __rho_10_^0==__rho_10_^post_53 && __rho_11_^0==__rho_11_^post_53 && __rho_12_^0==__rho_12_^post_53 && __rho_1_^0==__rho_1_^post_53 && __rho_2_^0==__rho_2_^post_53 && __rho_3_^0==__rho_3_^post_53 && __rho_4_^0==__rho_4_^post_53 && __rho_5_^0==__rho_5_^post_53 && __rho_666_^0==__rho_666_^post_53 && __rho_7_^0==__rho_7_^post_53 && __rho_8_^0==__rho_8_^post_53 && __rho_9_^0==__rho_9_^post_53 && a11^0==a11^post_53 && a1818^0==a1818^post_53 && a2525^0==a2525^post_53 && a2828^0==a2828^post_53 && a3131^0==a3131^post_53 && a3232^0==a3232^post_53 && a3434^0==a3434^post_53 && a3737^0==a3737^post_53 && a3838^0==a3838^post_53 && a4343^0==a4343^post_53 && a4545^0==a4545^post_53 && a77^0==a77^post_53 && b22^0==b22^post_53 && b2626^0==b2626^post_53 && b2929^0==b2929^post_53 && b3333^0==b3333^post_53 && b3535^0==b3535^post_53 && i^0==i^post_53 && i___01313^0==i___01313^post_53 && i___01717^0==i___01717^post_53 && i___02020^0==i___02020^post_53 && i___02424^0==i___02424^post_53 && i___04040^0==i___04040^post_53 && i___04747^0==i___04747^post_53 && i___099^0==i___099^post_53 && ioA^0==ioA^post_53 && ioR^0==ioR^post_53 && k1^0==k1^post_53 && k2^0==k2^post_53 && k3^0==k3^post_53 && k4^0==k4^post_53 && k5^0==k5^post_53 && keA^0==keA^post_53 && keR^0==keR^post_53 && ntStatus^0==ntStatus^post_53 && pIrb^0==pIrb^post_53 && phi_io_compl^0==phi_io_compl^post_53 && phi_nSUC_ret^0==phi_nSUC_ret^post_53 && prevCancel^0==prevCancel^post_53 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_53 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_53 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_53 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_53 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_53 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_53 && ioR^post_52==0 && ioA^post_52==ioR^post_52 && keR^post_52==ioA^post_52 && keA^post_52==keR^post_52 && phi_nSUC_ret^post_52==0 && phi_io_compl^post_52==0 && AsyncAddressData^post_53==AsyncAddressData^post_52 && BusResetIrp^post_53==BusResetIrp^post_52 && CromData^post_53==CromData^post_52 && DeviceObject^post_53==DeviceObject^post_52 && Irp^post_53==Irp^post_52 && Irql^post_53==Irql^post_52 && IsochDetachData^post_53==IsochDetachData^post_52 && IsochResourceData^post_53==IsochResourceData^post_52 && ResourceIrp^post_53==ResourceIrp^post_52 && StackSize^post_53==StackSize^post_52 && __rho_10_^post_53==__rho_10_^post_52 && __rho_11_^post_53==__rho_11_^post_52 && __rho_12_^post_53==__rho_12_^post_52 && __rho_2_^post_53==__rho_2_^post_52 && __rho_3_^post_53==__rho_3_^post_52 && __rho_4_^post_53==__rho_4_^post_52 && __rho_5_^post_53==__rho_5_^post_52 && __rho_7_^post_53==__rho_7_^post_52 && __rho_8_^post_53==__rho_8_^post_52 && __rho_9_^post_53==__rho_9_^post_52 && a11^post_53==a11^post_52 && a1818^post_53==a1818^post_52 && a2525^post_53==a2525^post_52 && a2828^post_53==a2828^post_52 && a3131^post_53==a3131^post_52 && a3232^post_53==a3232^post_52 && a3434^post_53==a3434^post_52 && a3737^post_53==a3737^post_52 && a3838^post_53==a3838^post_52 && a4343^post_53==a4343^post_52 && a4545^post_53==a4545^post_52 && a77^post_53==a77^post_52 && b22^post_53==b22^post_52 && b2626^post_53==b2626^post_52 && b2929^post_53==b2929^post_52 && b3333^post_53==b3333^post_52 && b3535^post_53==b3535^post_52 && i^post_53==i^post_52 && i___01313^post_53==i___01313^post_52 && i___01717^post_53==i___01717^post_52 && i___02020^post_53==i___02020^post_52 && i___02424^post_53==i___02424^post_52 && i___04040^post_53==i___04040^post_52 && i___04747^post_53==i___04747^post_52 && i___099^post_53==i___099^post_52 && k1^post_53==k1^post_52 && k2^post_53==k2^post_52 && k3^post_53==k3^post_52 && k4^post_53==k4^post_52 && k5^post_53==k5^post_52 && ntStatus^post_53==ntStatus^post_52 && pIrb^post_53==pIrb^post_52 && prevCancel^post_53==prevCancel^post_52 && ret_ExAllocatePool3030^post_53==ret_ExAllocatePool3030^post_52 && ret_IoAllocateIrp2727^post_53==ret_IoAllocateIrp2727^post_52 && ret_IoSetCancelRoutine4444^post_53==ret_IoSetCancelRoutine4444^post_52 && ret_IoSetDeviceInterfaceState44^post_53==ret_IoSetDeviceInterfaceState44^post_52 && ret_t1394Diag_PnpStopDevice33^post_53==ret_t1394Diag_PnpStopDevice33^post_52 && ret_t1394_SubmitIrpSynch3636^post_53==ret_t1394_SubmitIrpSynch3636^post_52 && 1<=__rho_1_^post_52 ], cost: 3

Chained accelerated rules (with incoming rules):
   Start location: l34
     66: l1 -> l19 : AsyncAddressData^0'=AsyncAddressData^post_50, BusResetIrp^0'=BusResetIrp^post_50, CromData^0'=CromData^post_50, DeviceObject^0'=DeviceObject^post_50, Irp^0'=Irp^post_50, Irql^0'=Irql^post_50, IsochDetachData^0'=IsochDetachData^post_50, IsochResourceData^0'=IsochResourceData^post_50, ResourceIrp^0'=ResourceIrp^post_50, StackSize^0'=StackSize^post_50, __rho_10_^0'=__rho_10_^post_50, __rho_11_^0'=__rho_11_^post_50, __rho_12_^0'=__rho_12_^post_50, __rho_1_^0'=__rho_1_^post_50, __rho_2_^0'=__rho_2_^post_50, __rho_3_^0'=__rho_3_^post_50, __rho_4_^0'=__rho_4_^post_50, __rho_5_^0'=__rho_5_^post_50, __rho_666_^0'=__rho_666_^post_50, __rho_7_^0'=__rho_7_^post_50, __rho_8_^0'=__rho_8_^post_50, __rho_9_^0'=__rho_9_^post_50, a11^0'=a11^post_50, a1818^0'=a1818^post_50, a2525^0'=a2525^post_50, a2828^0'=a2828^post_50, a3131^0'=a3131^post_50, a3232^0'=a3232^post_50, a3434^0'=a3434^post_50, a3737^0'=a3737^post_50, a3838^0'=a3838^post_50, a4343^0'=a4343^post_50, a4545^0'=a4545^post_50, a77^0'=a77^post_50, b22^0'=b22^post_50, b2626^0'=b2626^post_50, b2929^0'=b2929^post_50, b3333^0'=b3333^post_50, b3535^0'=b3535^post_50, i^0'=i^post_50, i___01313^0'=i___01313^post_50, i___01717^0'=i___01717^post_50, i___02020^0'=i___02020^post_50, i___02424^0'=i___02424^post_50, i___04040^0'=i___04040^post_50, i___04747^0'=i___04747^post_50, i___099^0'=i___099^post_50, ioA^0'=ioA^post_50, ioR^0'=ioR^post_50, k1^0'=k1^post_50, k2^0'=k2^post_50, k3^0'=k3^post_50, k4^0'=k4^post_50, k5^0'=k5^post_50, keA^0'=keA^post_50, keR^0'=keR^post_50, ntStatus^0'=ntStatus^post_50, pIrb^0'=pIrb^post_50, phi_io_compl^0'=phi_io_compl^post_50, phi_nSUC_ret^0'=phi_nSUC_ret^post_50, prevCancel^0'=prevCancel^post_50, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_50, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_50, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_50, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_50, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_50, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_50, [ k4^0<=0 && i___04040^post_50==Irql^0 && keR^1_4_1==1 && keR^post_50==0 && keA^1_5==1 && keA^post_50==0 && k5^post_50==__rho_12_^post_50 && AsyncAddressData^0==AsyncAddressData^post_50 && BusResetIrp^0==BusResetIrp^post_50 && CromData^0==CromData^post_50 && DeviceObject^0==DeviceObject^post_50 && Irp^0==Irp^post_50 && Irql^0==Irql^post_50 && IsochDetachData^0==IsochDetachData^post_50 && IsochResourceData^0==IsochResourceData^post_50 && ResourceIrp^0==ResourceIrp^post_50 && StackSize^0==StackSize^post_50 && __rho_10_^0==__rho_10_^post_50 && __rho_11_^0==__rho_11_^post_50 && __rho_1_^0==__rho_1_^post_50 && __rho_2_^0==__rho_2_^post_50 && __rho_3_^0==__rho_3_^post_50 && __rho_4_^0==__rho_4_^post_50 && __rho_5_^0==__rho_5_^post_50 && __rho_666_^0==__rho_666_^post_50 && __rho_7_^0==__rho_7_^post_50 && __rho_8_^0==__rho_8_^post_50 && __rho_9_^0==__rho_9_^post_50 && a11^0==a11^post_50 && a1818^0==a1818^post_50 && a2525^0==a2525^post_50 && a2828^0==a2828^post_50 && a3131^0==a3131^post_50 && a3232^0==a3232^post_50 && a3434^0==a3434^post_50 && a3737^0==a3737^post_50 && a3838^0==a3838^post_50 && a4343^0==a4343^post_50 && a4545^0==a4545^post_50 && a77^0==a77^post_50 && b22^0==b22^post_50 && b2626^0==b2626^post_50 && b2929^0==b2929^post_50 && b3333^0==b3333^post_50 && b3535^0==b3535^post_50 && i^0==i^post_50 && i___01313^0==i___01313^post_50 && i___01717^0==i___01717^post_50 && i___02020^0==i___02020^post_50 && i___02424^0==i___02424^post_50 && i___04747^0==i___04747^post_50 && i___099^0==i___099^post_50 && ioA^0==ioA^post_50 && ioR^0==ioR^post_50 && k1^0==k1^post_50 && k2^0==k2^post_50 && k3^0==k3^post_50 && k4^0==k4^post_50 && ntStatus^0==ntStatus^post_50 && pIrb^0==pIrb^post_50 && phi_io_compl^0==phi_io_compl^post_50 && phi_nSUC_ret^0==phi_nSUC_ret^post_50 && prevCancel^0==prevCancel^post_50 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_50 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_50 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_50 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_50 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_50 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_50 ], cost: 2
     67: l1 -> l32 : AsyncAddressData^0'=AsyncAddressData^post_51, BusResetIrp^0'=BusResetIrp^post_51, CromData^0'=CromData^post_51, DeviceObject^0'=DeviceObject^post_51, Irp^0'=Irp^post_51, Irql^0'=Irql^post_51, IsochDetachData^0'=IsochDetachData^post_51, IsochResourceData^0'=IsochResourceData^post_51, ResourceIrp^0'=ResourceIrp^post_51, StackSize^0'=StackSize^post_51, __rho_10_^0'=__rho_10_^post_51, __rho_11_^0'=__rho_11_^post_51, __rho_12_^0'=__rho_12_^post_51, __rho_1_^0'=__rho_1_^post_51, __rho_2_^0'=__rho_2_^post_51, __rho_3_^0'=__rho_3_^post_51, __rho_4_^0'=__rho_4_^post_51, __rho_5_^0'=__rho_5_^post_51, __rho_666_^0'=__rho_666_^post_51, __rho_7_^0'=__rho_7_^post_51, __rho_8_^0'=__rho_8_^post_51, __rho_9_^0'=__rho_9_^post_51, a11^0'=a11^post_51, a1818^0'=a1818^post_51, a2525^0'=a2525^post_51, a2828^0'=a2828^post_51, a3131^0'=a3131^post_51, a3232^0'=a3232^post_51, a3434^0'=a3434^post_51, a3737^0'=a3737^post_51, a3838^0'=a3838^post_51, a4343^0'=a4343^post_51, a4545^0'=a4545^post_51, a77^0'=a77^post_51, b22^0'=b22^post_51, b2626^0'=b2626^post_51, b2929^0'=b2929^post_51, b3333^0'=b3333^post_51, b3535^0'=b3535^post_51, i^0'=i^post_51, i___01313^0'=i___01313^post_51, i___01717^0'=i___01717^post_51, i___02020^0'=i___02020^post_51, i___02424^0'=i___02424^post_51, i___04040^0'=i___04040^post_51, i___04747^0'=i___04747^post_51, i___099^0'=i___099^post_51, ioA^0'=ioA^post_51, ioR^0'=ioR^post_51, k1^0'=k1^post_51, k2^0'=k2^post_51, k3^0'=k3^post_51, k4^0'=k4^post_51, k5^0'=k5^post_51, keA^0'=keA^post_51, keR^0'=keR^post_51, ntStatus^0'=ntStatus^post_51, pIrb^0'=pIrb^post_51, phi_io_compl^0'=phi_io_compl^post_51, phi_nSUC_ret^0'=phi_nSUC_ret^post_51, prevCancel^0'=prevCancel^post_51, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_51, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_51, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_51, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_51, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_51, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_51, [ 1<=k4^0 && k4^post_51==-1+k4^0 && i___02424^post_51==Irql^0 && keR^1_4_2==1 && keR^post_51==0 && AsyncAddressData^0==AsyncAddressData^post_51 && BusResetIrp^0==BusResetIrp^post_51 && CromData^0==CromData^post_51 && DeviceObject^0==DeviceObject^post_51 && Irp^0==Irp^post_51 && Irql^0==Irql^post_51 && IsochDetachData^0==IsochDetachData^post_51 && ResourceIrp^0==ResourceIrp^post_51 && StackSize^0==StackSize^post_51 && __rho_10_^0==__rho_10_^post_51 && __rho_11_^0==__rho_11_^post_51 && __rho_12_^0==__rho_12_^post_51 && __rho_1_^0==__rho_1_^post_51 && __rho_2_^0==__rho_2_^post_51 && __rho_3_^0==__rho_3_^post_51 && __rho_4_^0==__rho_4_^post_51 && __rho_5_^0==__rho_5_^post_51 && __rho_666_^0==__rho_666_^post_51 && __rho_7_^0==__rho_7_^post_51 && __rho_8_^0==__rho_8_^post_51 && __rho_9_^0==__rho_9_^post_51 && a11^0==a11^post_51 && a1818^0==a1818^post_51 && a2525^0==a2525^post_51 && a2828^0==a2828^post_51 && a3131^0==a3131^post_51 && a3232^0==a3232^post_51 && a3434^0==a3434^post_51 && a3737^0==a3737^post_51 && a3838^0==a3838^post_51 && a4343^0==a4343^post_51 && a4545^0==a4545^post_51 && a77^0==a77^post_51 && b22^0==b22^post_51 && b2626^0==b2626^post_51 && b2929^0==b2929^post_51 && b3333^0==b3333^post_51 && b3535^0==b3535^post_51 && i^0==i^post_51 && i___01313^0==i___01313^post_51 && i___01717^0==i___01717^post_51 && i___02020^0==i___02020^post_51 && i___04040^0==i___04040^post_51 && i___04747^0==i___04747^post_51 && i___099^0==i___099^post_51 && ioA^0==ioA^post_51 && ioR^0==ioR^post_51 && k1^0==k1^post_51 && k2^0==k2^post_51 && k3^0==k3^post_51 && k5^0==k5^post_51 && 0==keA^post_51 && ntStatus^0==ntStatus^post_51 && pIrb^0==pIrb^post_51 && phi_io_compl^0==phi_io_compl^post_51 && phi_nSUC_ret^0==phi_nSUC_ret^post_51 && prevCancel^0==prevCancel^post_51 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_51 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_51 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_51 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_51 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_51 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_51 ], cost: 2
     95: l1 -> l19 : BusResetIrp^0'=BusResetIrp^post_38, __rho_12_^0'=k5^post_50, a4343^0'=0, a4545^0'=BusResetIrp^post_38, i___04040^0'=Irql^0, k5^0'=0, keA^0'=0, keR^0'=0, phi_io_compl^0'=1, prevCancel^0'=0, ret_IoSetCancelRoutine4444^0'=0, [ k4^0<=0 && k5^post_50>=1 ], cost: 2+2*k5^post_50
     64: l2 -> l1 : __rho_11_^0'=__rho_11_^post_1, i___02020^0'=Irql^0, k4^0'=__rho_11_^post_1, keA^0'=0, keR^0'=0, [ k3^0<=0 ], cost: 2
     62: l4 -> l9 : AsyncAddressData^0'=AsyncAddressData^post_14, __rho_7_^0'=__rho_7_^post_14, k2^0'=-1+k2^0, [ 1<=k2^0 ], cost: 2
     63: l4 -> l2 : __rho_10_^0'=__rho_10_^post_15, i___01313^0'=Irql^0, k3^0'=__rho_10_^post_15, keR^0'=0, [ k2^0<=0 ], cost: 2
     94: l4 -> l2 : IsochDetachData^0'=IsochDetachData^post_2, __rho_10_^0'=__rho_10_^post_15, a1818^0'=IsochDetachData^post_2, i^0'=i^post_2, i___01313^0'=Irql^0, i___01717^0'=Irql^0, k3^0'=0, keA^0'=0, keR^0'=0, [ k2^0<=0 && __rho_10_^post_15>=1 ], cost: 2+2*__rho_10_^post_15
     87: l5 -> l4 : [], cost: 2
     88: l7 -> l5 : __rho_9_^0'=__rho_9_^post_7, [], cost: 2
     89: l9 -> l7 : __rho_8_^0'=__rho_8_^post_10, [], cost: 2
     60: l10 -> l18 : CromData^0'=CromData^post_27, k1^0'=-1+k1^0, [ 1<=k1^0 ], cost: 2
     61: l10 -> l4 : __rho_4_^0'=__rho_4_^post_28, i___099^0'=Irql^0, k2^0'=__rho_4_^post_28, keA^0'=0, keR^0'=0, [ k1^0<=0 ], cost: 2
     17: l13 -> l10 : a77^0'=CromData^0, [], cost: 1
     90: l15 -> l13 : __rho_3_^0'=__rho_3_^post_21, [], cost: 2
     24: l18 -> l10 : [ CromData^0<=0 ], cost: 1
     91: l18 -> l15 : __rho_2_^0'=__rho_2_^post_26, [ 1<=CromData^0 ], cost: 2
     69: l19 -> l26 : i___04747^0'=Irql^0, keR^0'=0, [ k5^0<=0 ], cost: 2
     29: l21 -> l10 : __rho_5_^0'=__rho_5_^post_30, k1^0'=__rho_5_^post_30, keA^0'=0, ntStatus^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, [], cost: 1
     57: l26 -> [35] : [ -2+ntStatus^0==0 ], cost: NONTERM
     70: l26 -> [35] : [ 3<=ntStatus^0 ], cost: NONTERM
     71: l26 -> [35] : [ 1+ntStatus^0<=2 ], cost: NONTERM
     47: l32 -> l1 : [ IsochResourceData^0<=0 ], cost: 1
     72: l32 -> l1 : ResourceIrp^0'=0, StackSize^0'=a2525^post_49, a2525^0'=a2525^post_49, b2626^0'=0, pIrb^0'=pIrb^post_49, ret_IoAllocateIrp2727^0'=0, [ 1<=IsochResourceData^0 ], cost: 2
     58: l34 -> l21 : AsyncAddressData^0'=AsyncAddressData^post_52, BusResetIrp^0'=BusResetIrp^post_52, CromData^0'=CromData^post_52, DeviceObject^0'=DeviceObject^post_52, Irp^0'=Irp^post_52, Irql^0'=Irql^post_52, IsochDetachData^0'=IsochDetachData^post_52, IsochResourceData^0'=IsochResourceData^post_52, ResourceIrp^0'=ResourceIrp^post_52, StackSize^0'=StackSize^post_52, __rho_10_^0'=__rho_10_^post_52, __rho_11_^0'=__rho_11_^post_52, __rho_12_^0'=__rho_12_^post_52, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_52, __rho_3_^0'=__rho_3_^post_52, __rho_4_^0'=__rho_4_^post_52, __rho_5_^0'=__rho_5_^post_52, __rho_666_^0'=__rho_666_^post_52, __rho_7_^0'=__rho_7_^post_52, __rho_8_^0'=__rho_8_^post_52, __rho_9_^0'=__rho_9_^post_52, a11^0'=a11^post_52, a1818^0'=a1818^post_52, a2525^0'=a2525^post_52, a2828^0'=a2828^post_52, a3131^0'=a3131^post_52, a3232^0'=a3232^post_52, a3434^0'=a3434^post_52, a3737^0'=a3737^post_52, a3838^0'=a3838^post_52, a4343^0'=a4343^post_52, a4545^0'=a4545^post_52, a77^0'=a77^post_52, b22^0'=b22^post_52, b2626^0'=b2626^post_52, b2929^0'=b2929^post_52, b3333^0'=b3333^post_52, b3535^0'=b3535^post_52, i^0'=i^post_52, i___01313^0'=i___01313^post_52, i___01717^0'=i___01717^post_52, i___02020^0'=i___02020^post_52, i___02424^0'=i___02424^post_52, i___04040^0'=i___04040^post_52, i___04747^0'=i___04747^post_52, i___099^0'=i___099^post_52, ioA^0'=ioA^post_52, ioR^0'=ioR^post_52, k1^0'=k1^post_52, k2^0'=k2^post_52, k3^0'=k3^post_52, k4^0'=k4^post_52, k5^0'=k5^post_52, keA^0'=keA^post_52, keR^0'=keR^post_52, ntStatus^0'=ntStatus^post_52, pIrb^0'=pIrb^post_52, phi_io_compl^0'=phi_io_compl^post_52, phi_nSUC_ret^0'=phi_nSUC_ret^post_52, prevCancel^0'=prevCancel^post_52, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_52, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_52, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_52, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_52, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_52, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_52, [ AsyncAddressData^0==AsyncAddressData^post_53 && BusResetIrp^0==BusResetIrp^post_53 && CromData^0==CromData^post_53 && DeviceObject^0==DeviceObject^post_53 && Irp^0==Irp^post_53 && Irql^0==Irql^post_53 && IsochDetachData^0==IsochDetachData^post_53 && IsochResourceData^0==IsochResourceData^post_53 && ResourceIrp^0==ResourceIrp^post_53 && StackSize^0==StackSize^post_53 && __rho_10_^0==__rho_10_^post_53 && __rho_11_^0==__rho_11_^post_53 && __rho_12_^0==__rho_12_^post_53 && __rho_1_^0==__rho_1_^post_53 && __rho_2_^0==__rho_2_^post_53 && __rho_3_^0==__rho_3_^post_53 && __rho_4_^0==__rho_4_^post_53 && __rho_5_^0==__rho_5_^post_53 && __rho_666_^0==__rho_666_^post_53 && __rho_7_^0==__rho_7_^post_53 && __rho_8_^0==__rho_8_^post_53 && __rho_9_^0==__rho_9_^post_53 && a11^0==a11^post_53 && a1818^0==a1818^post_53 && a2525^0==a2525^post_53 && a2828^0==a2828^post_53 && a3131^0==a3131^post_53 && a3232^0==a3232^post_53 && a3434^0==a3434^post_53 && a3737^0==a3737^post_53 && a3838^0==a3838^post_53 && a4343^0==a4343^post_53 && a4545^0==a4545^post_53 && a77^0==a77^post_53 && b22^0==b22^post_53 && b2626^0==b2626^post_53 && b2929^0==b2929^post_53 && b3333^0==b3333^post_53 && b3535^0==b3535^post_53 && i^0==i^post_53 && i___01313^0==i___01313^post_53 && i___01717^0==i___01717^post_53 && i___02020^0==i___02020^post_53 && i___02424^0==i___02424^post_53 && i___04040^0==i___04040^post_53 && i___04747^0==i___04747^post_53 && i___099^0==i___099^post_53 && ioA^0==ioA^post_53 && ioR^0==ioR^post_53 && k1^0==k1^post_53 && k2^0==k2^post_53 && k3^0==k3^post_53 && k4^0==k4^post_53 && k5^0==k5^post_53 && keA^0==keA^post_53 && keR^0==keR^post_53 && ntStatus^0==ntStatus^post_53 && pIrb^0==pIrb^post_53 && phi_io_compl^0==phi_io_compl^post_53 && phi_nSUC_ret^0==phi_nSUC_ret^post_53 && prevCancel^0==prevCancel^post_53 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_53 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_53 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_53 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_53 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_53 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_53 && ioR^post_52==0 && ioA^post_52==ioR^post_52 && keR^post_52==ioA^post_52 && keA^post_52==keR^post_52 && phi_nSUC_ret^post_52==0 && phi_io_compl^post_52==0 && AsyncAddressData^post_53==AsyncAddressData^post_52 && BusResetIrp^post_53==BusResetIrp^post_52 && CromData^post_53==CromData^post_52 && DeviceObject^post_53==DeviceObject^post_52 && Irp^post_53==Irp^post_52 && Irql^post_53==Irql^post_52 && IsochDetachData^post_53==IsochDetachData^post_52 && IsochResourceData^post_53==IsochResourceData^post_52 && ResourceIrp^post_53==ResourceIrp^post_52 && StackSize^post_53==StackSize^post_52 && __rho_10_^post_53==__rho_10_^post_52 && __rho_11_^post_53==__rho_11_^post_52 && __rho_12_^post_53==__rho_12_^post_52 && __rho_2_^post_53==__rho_2_^post_52 && __rho_3_^post_53==__rho_3_^post_52 && __rho_4_^post_53==__rho_4_^post_52 && __rho_5_^post_53==__rho_5_^post_52 && __rho_7_^post_53==__rho_7_^post_52 && __rho_8_^post_53==__rho_8_^post_52 && __rho_9_^post_53==__rho_9_^post_52 && a11^post_53==a11^post_52 && a1818^post_53==a1818^post_52 && a2525^post_53==a2525^post_52 && a2828^post_53==a2828^post_52 && a3131^post_53==a3131^post_52 && a3232^post_53==a3232^post_52 && a3434^post_53==a3434^post_52 && a3737^post_53==a3737^post_52 && a3838^post_53==a3838^post_52 && a4343^post_53==a4343^post_52 && a4545^post_53==a4545^post_52 && a77^post_53==a77^post_52 && b22^post_53==b22^post_52 && b2626^post_53==b2626^post_52 && b2929^post_53==b2929^post_52 && b3333^post_53==b3333^post_52 && b3535^post_53==b3535^post_52 && i^post_53==i^post_52 && i___01313^post_53==i___01313^post_52 && i___01717^post_53==i___01717^post_52 && i___02020^post_53==i___02020^post_52 && i___02424^post_53==i___02424^post_52 && i___04040^post_53==i___04040^post_52 && i___04747^post_53==i___04747^post_52 && i___099^post_53==i___099^post_52 && k1^post_53==k1^post_52 && k2^post_53==k2^post_52 && k3^post_53==k3^post_52 && k4^post_53==k4^post_52 && k5^post_53==k5^post_52 && ntStatus^post_53==ntStatus^post_52 && pIrb^post_53==pIrb^post_52 && prevCancel^post_53==prevCancel^post_52 && ret_ExAllocatePool3030^post_53==ret_ExAllocatePool3030^post_52 && ret_IoAllocateIrp2727^post_53==ret_IoAllocateIrp2727^post_52 && ret_IoSetCancelRoutine4444^post_53==ret_IoSetCancelRoutine4444^post_52 && ret_IoSetDeviceInterfaceState44^post_53==ret_IoSetDeviceInterfaceState44^post_52 && ret_t1394Diag_PnpStopDevice33^post_53==ret_t1394Diag_PnpStopDevice33^post_52 && ret_t1394_SubmitIrpSynch3636^post_53==ret_t1394_SubmitIrpSynch3636^post_52 && __rho_1_^post_52<=0 ], cost: 3
     59: l34 -> l21 : AsyncAddressData^0'=AsyncAddressData^post_52, BusResetIrp^0'=BusResetIrp^post_52, CromData^0'=CromData^post_52, DeviceObject^0'=DeviceObject^post_52, Irp^0'=Irp^post_52, Irql^0'=Irql^post_52, IsochDetachData^0'=IsochDetachData^post_52, IsochResourceData^0'=IsochResourceData^post_52, ResourceIrp^0'=ResourceIrp^post_52, StackSize^0'=StackSize^post_52, __rho_10_^0'=__rho_10_^post_52, __rho_11_^0'=__rho_11_^post_52, __rho_12_^0'=__rho_12_^post_52, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_52, __rho_3_^0'=__rho_3_^post_52, __rho_4_^0'=__rho_4_^post_52, __rho_5_^0'=__rho_5_^post_52, __rho_666_^0'=__rho_666_^post_52, __rho_7_^0'=__rho_7_^post_52, __rho_8_^0'=__rho_8_^post_52, __rho_9_^0'=__rho_9_^post_52, a11^0'=DeviceObject^post_52, a1818^0'=a1818^post_52, a2525^0'=a2525^post_52, a2828^0'=a2828^post_52, a3131^0'=a3131^post_52, a3232^0'=a3232^post_52, a3434^0'=a3434^post_52, a3737^0'=a3737^post_52, a3838^0'=a3838^post_52, a4343^0'=a4343^post_52, a4545^0'=a4545^post_52, a77^0'=a77^post_52, b22^0'=Irp^post_52, b2626^0'=b2626^post_52, b2929^0'=b2929^post_52, b3333^0'=b3333^post_52, b3535^0'=b3535^post_52, i^0'=i^post_52, i___01313^0'=i___01313^post_52, i___01717^0'=i___01717^post_52, i___02020^0'=i___02020^post_52, i___02424^0'=i___02424^post_52, i___04040^0'=i___04040^post_52, i___04747^0'=i___04747^post_52, i___099^0'=i___099^post_52, ioA^0'=ioA^post_52, ioR^0'=ioR^post_52, k1^0'=k1^post_52, k2^0'=k2^post_52, k3^0'=k3^post_52, k4^0'=k4^post_52, k5^0'=k5^post_52, keA^0'=keA^post_52, keR^0'=keR^post_52, ntStatus^0'=0, pIrb^0'=pIrb^post_52, phi_io_compl^0'=phi_io_compl^post_52, phi_nSUC_ret^0'=phi_nSUC_ret^post_52, prevCancel^0'=prevCancel^post_52, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_52, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_52, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_52, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_52, ret_t1394Diag_PnpStopDevice33^0'=0, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_52, [ AsyncAddressData^0==AsyncAddressData^post_53 && BusResetIrp^0==BusResetIrp^post_53 && CromData^0==CromData^post_53 && DeviceObject^0==DeviceObject^post_53 && Irp^0==Irp^post_53 && Irql^0==Irql^post_53 && IsochDetachData^0==IsochDetachData^post_53 && IsochResourceData^0==IsochResourceData^post_53 && ResourceIrp^0==ResourceIrp^post_53 && StackSize^0==StackSize^post_53 && __rho_10_^0==__rho_10_^post_53 && __rho_11_^0==__rho_11_^post_53 && __rho_12_^0==__rho_12_^post_53 && __rho_1_^0==__rho_1_^post_53 && __rho_2_^0==__rho_2_^post_53 && __rho_3_^0==__rho_3_^post_53 && __rho_4_^0==__rho_4_^post_53 && __rho_5_^0==__rho_5_^post_53 && __rho_666_^0==__rho_666_^post_53 && __rho_7_^0==__rho_7_^post_53 && __rho_8_^0==__rho_8_^post_53 && __rho_9_^0==__rho_9_^post_53 && a11^0==a11^post_53 && a1818^0==a1818^post_53 && a2525^0==a2525^post_53 && a2828^0==a2828^post_53 && a3131^0==a3131^post_53 && a3232^0==a3232^post_53 && a3434^0==a3434^post_53 && a3737^0==a3737^post_53 && a3838^0==a3838^post_53 && a4343^0==a4343^post_53 && a4545^0==a4545^post_53 && a77^0==a77^post_53 && b22^0==b22^post_53 && b2626^0==b2626^post_53 && b2929^0==b2929^post_53 && b3333^0==b3333^post_53 && b3535^0==b3535^post_53 && i^0==i^post_53 && i___01313^0==i___01313^post_53 && i___01717^0==i___01717^post_53 && i___02020^0==i___02020^post_53 && i___02424^0==i___02424^post_53 && i___04040^0==i___04040^post_53 && i___04747^0==i___04747^post_53 && i___099^0==i___099^post_53 && ioA^0==ioA^post_53 && ioR^0==ioR^post_53 && k1^0==k1^post_53 && k2^0==k2^post_53 && k3^0==k3^post_53 && k4^0==k4^post_53 && k5^0==k5^post_53 && keA^0==keA^post_53 && keR^0==keR^post_53 && ntStatus^0==ntStatus^post_53 && pIrb^0==pIrb^post_53 && phi_io_compl^0==phi_io_compl^post_53 && phi_nSUC_ret^0==phi_nSUC_ret^post_53 && prevCancel^0==prevCancel^post_53 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_53 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_53 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_53 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_53 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_53 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_53 && ioR^post_52==0 && ioA^post_52==ioR^post_52 && keR^post_52==ioA^post_52 && keA^post_52==keR^post_52 && phi_nSUC_ret^post_52==0 && phi_io_compl^post_52==0 && AsyncAddressData^post_53==AsyncAddressData^post_52 && BusResetIrp^post_53==BusResetIrp^post_52 && CromData^post_53==CromData^post_52 && DeviceObject^post_53==DeviceObject^post_52 && Irp^post_53==Irp^post_52 && Irql^post_53==Irql^post_52 && IsochDetachData^post_53==IsochDetachData^post_52 && IsochResourceData^post_53==IsochResourceData^post_52 && ResourceIrp^post_53==ResourceIrp^post_52 && StackSize^post_53==StackSize^post_52 && __rho_10_^post_53==__rho_10_^post_52 && __rho_11_^post_53==__rho_11_^post_52 && __rho_12_^post_53==__rho_12_^post_52 && __rho_2_^post_53==__rho_2_^post_52 && __rho_3_^post_53==__rho_3_^post_52 && __rho_4_^post_53==__rho_4_^post_52 && __rho_5_^post_53==__rho_5_^post_52 && __rho_7_^post_53==__rho_7_^post_52 && __rho_8_^post_53==__rho_8_^post_52 && __rho_9_^post_53==__rho_9_^post_52 && a11^post_53==a11^post_52 && a1818^post_53==a1818^post_52 && a2525^post_53==a2525^post_52 && a2828^post_53==a2828^post_52 && a3131^post_53==a3131^post_52 && a3232^post_53==a3232^post_52 && a3434^post_53==a3434^post_52 && a3737^post_53==a3737^post_52 && a3838^post_53==a3838^post_52 && a4343^post_53==a4343^post_52 && a4545^post_53==a4545^post_52 && a77^post_53==a77^post_52 && b22^post_53==b22^post_52 && b2626^post_53==b2626^post_52 && b2929^post_53==b2929^post_52 && b3333^post_53==b3333^post_52 && b3535^post_53==b3535^post_52 && i^post_53==i^post_52 && i___01313^post_53==i___01313^post_52 && i___01717^post_53==i___01717^post_52 && i___02020^post_53==i___02020^post_52 && i___02424^post_53==i___02424^post_52 && i___04040^post_53==i___04040^post_52 && i___04747^post_53==i___04747^post_52 && i___099^post_53==i___099^post_52 && k1^post_53==k1^post_52 && k2^post_53==k2^post_52 && k3^post_53==k3^post_52 && k4^post_53==k4^post_52 && k5^post_53==k5^post_52 && ntStatus^post_53==ntStatus^post_52 && pIrb^post_53==pIrb^post_52 && prevCancel^post_53==prevCancel^post_52 && ret_ExAllocatePool3030^post_53==ret_ExAllocatePool3030^post_52 && ret_IoAllocateIrp2727^post_53==ret_IoAllocateIrp2727^post_52 && ret_IoSetCancelRoutine4444^post_53==ret_IoSetCancelRoutine4444^post_52 && ret_IoSetDeviceInterfaceState44^post_53==ret_IoSetDeviceInterfaceState44^post_52 && ret_t1394Diag_PnpStopDevice33^post_53==ret_t1394Diag_PnpStopDevice33^post_52 && ret_t1394_SubmitIrpSynch3636^post_53==ret_t1394_SubmitIrpSynch3636^post_52 && 1<=__rho_1_^post_52 ], cost: 3

Eliminated locations (on linear paths):
   Start location: l34
     66: l1 -> l19 : AsyncAddressData^0'=AsyncAddressData^post_50, BusResetIrp^0'=BusResetIrp^post_50, CromData^0'=CromData^post_50, DeviceObject^0'=DeviceObject^post_50, Irp^0'=Irp^post_50, Irql^0'=Irql^post_50, IsochDetachData^0'=IsochDetachData^post_50, IsochResourceData^0'=IsochResourceData^post_50, ResourceIrp^0'=ResourceIrp^post_50, StackSize^0'=StackSize^post_50, __rho_10_^0'=__rho_10_^post_50, __rho_11_^0'=__rho_11_^post_50, __rho_12_^0'=__rho_12_^post_50, __rho_1_^0'=__rho_1_^post_50, __rho_2_^0'=__rho_2_^post_50, __rho_3_^0'=__rho_3_^post_50, __rho_4_^0'=__rho_4_^post_50, __rho_5_^0'=__rho_5_^post_50, __rho_666_^0'=__rho_666_^post_50, __rho_7_^0'=__rho_7_^post_50, __rho_8_^0'=__rho_8_^post_50, __rho_9_^0'=__rho_9_^post_50, a11^0'=a11^post_50, a1818^0'=a1818^post_50, a2525^0'=a2525^post_50, a2828^0'=a2828^post_50, a3131^0'=a3131^post_50, a3232^0'=a3232^post_50, a3434^0'=a3434^post_50, a3737^0'=a3737^post_50, a3838^0'=a3838^post_50, a4343^0'=a4343^post_50, a4545^0'=a4545^post_50, a77^0'=a77^post_50, b22^0'=b22^post_50, b2626^0'=b2626^post_50, b2929^0'=b2929^post_50, b3333^0'=b3333^post_50, b3535^0'=b3535^post_50, i^0'=i^post_50, i___01313^0'=i___01313^post_50, i___01717^0'=i___01717^post_50, i___02020^0'=i___02020^post_50, i___02424^0'=i___02424^post_50, i___04040^0'=i___04040^post_50, i___04747^0'=i___04747^post_50, i___099^0'=i___099^post_50, ioA^0'=ioA^post_50, ioR^0'=ioR^post_50, k1^0'=k1^post_50, k2^0'=k2^post_50, k3^0'=k3^post_50, k4^0'=k4^post_50, k5^0'=k5^post_50, keA^0'=keA^post_50, keR^0'=keR^post_50, ntStatus^0'=ntStatus^post_50, pIrb^0'=pIrb^post_50, phi_io_compl^0'=phi_io_compl^post_50, phi_nSUC_ret^0'=phi_nSUC_ret^post_50, prevCancel^0'=prevCancel^post_50, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_50, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_50, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_50, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_50, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_50, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_50, [ k4^0<=0 && i___04040^post_50==Irql^0 && keR^1_4_1==1 && keR^post_50==0 && keA^1_5==1 && keA^post_50==0 && k5^post_50==__rho_12_^post_50 && AsyncAddressData^0==AsyncAddressData^post_50 && BusResetIrp^0==BusResetIrp^post_50 && CromData^0==CromData^post_50 && DeviceObject^0==DeviceObject^post_50 && Irp^0==Irp^post_50 && Irql^0==Irql^post_50 && IsochDetachData^0==IsochDetachData^post_50 && IsochResourceData^0==IsochResourceData^post_50 && ResourceIrp^0==ResourceIrp^post_50 && StackSize^0==StackSize^post_50 && __rho_10_^0==__rho_10_^post_50 && __rho_11_^0==__rho_11_^post_50 && __rho_1_^0==__rho_1_^post_50 && __rho_2_^0==__rho_2_^post_50 && __rho_3_^0==__rho_3_^post_50 && __rho_4_^0==__rho_4_^post_50 && __rho_5_^0==__rho_5_^post_50 && __rho_666_^0==__rho_666_^post_50 && __rho_7_^0==__rho_7_^post_50 && __rho_8_^0==__rho_8_^post_50 && __rho_9_^0==__rho_9_^post_50 && a11^0==a11^post_50 && a1818^0==a1818^post_50 && a2525^0==a2525^post_50 && a2828^0==a2828^post_50 && a3131^0==a3131^post_50 && a3232^0==a3232^post_50 && a3434^0==a3434^post_50 && a3737^0==a3737^post_50 && a3838^0==a3838^post_50 && a4343^0==a4343^post_50 && a4545^0==a4545^post_50 && a77^0==a77^post_50 && b22^0==b22^post_50 && b2626^0==b2626^post_50 && b2929^0==b2929^post_50 && b3333^0==b3333^post_50 && b3535^0==b3535^post_50 && i^0==i^post_50 && i___01313^0==i___01313^post_50 && i___01717^0==i___01717^post_50 && i___02020^0==i___02020^post_50 && i___02424^0==i___02424^post_50 && i___04747^0==i___04747^post_50 && i___099^0==i___099^post_50 && ioA^0==ioA^post_50 && ioR^0==ioR^post_50 && k1^0==k1^post_50 && k2^0==k2^post_50 && k3^0==k3^post_50 && k4^0==k4^post_50 && ntStatus^0==ntStatus^post_50 && pIrb^0==pIrb^post_50 && phi_io_compl^0==phi_io_compl^post_50 && phi_nSUC_ret^0==phi_nSUC_ret^post_50 && prevCancel^0==prevCancel^post_50 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_50 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_50 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_50 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_50 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_50 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_50 ], cost: 2
     67: l1 -> l32 : AsyncAddressData^0'=AsyncAddressData^post_51, BusResetIrp^0'=BusResetIrp^post_51, CromData^0'=CromData^post_51, DeviceObject^0'=DeviceObject^post_51, Irp^0'=Irp^post_51, Irql^0'=Irql^post_51, IsochDetachData^0'=IsochDetachData^post_51, IsochResourceData^0'=IsochResourceData^post_51, ResourceIrp^0'=ResourceIrp^post_51, StackSize^0'=StackSize^post_51, __rho_10_^0'=__rho_10_^post_51, __rho_11_^0'=__rho_11_^post_51, __rho_12_^0'=__rho_12_^post_51, __rho_1_^0'=__rho_1_^post_51, __rho_2_^0'=__rho_2_^post_51, __rho_3_^0'=__rho_3_^post_51, __rho_4_^0'=__rho_4_^post_51, __rho_5_^0'=__rho_5_^post_51, __rho_666_^0'=__rho_666_^post_51, __rho_7_^0'=__rho_7_^post_51, __rho_8_^0'=__rho_8_^post_51, __rho_9_^0'=__rho_9_^post_51, a11^0'=a11^post_51, a1818^0'=a1818^post_51, a2525^0'=a2525^post_51, a2828^0'=a2828^post_51, a3131^0'=a3131^post_51, a3232^0'=a3232^post_51, a3434^0'=a3434^post_51, a3737^0'=a3737^post_51, a3838^0'=a3838^post_51, a4343^0'=a4343^post_51, a4545^0'=a4545^post_51, a77^0'=a77^post_51, b22^0'=b22^post_51, b2626^0'=b2626^post_51, b2929^0'=b2929^post_51, b3333^0'=b3333^post_51, b3535^0'=b3535^post_51, i^0'=i^post_51, i___01313^0'=i___01313^post_51, i___01717^0'=i___01717^post_51, i___02020^0'=i___02020^post_51, i___02424^0'=i___02424^post_51, i___04040^0'=i___04040^post_51, i___04747^0'=i___04747^post_51, i___099^0'=i___099^post_51, ioA^0'=ioA^post_51, ioR^0'=ioR^post_51, k1^0'=k1^post_51, k2^0'=k2^post_51, k3^0'=k3^post_51, k4^0'=k4^post_51, k5^0'=k5^post_51, keA^0'=keA^post_51, keR^0'=keR^post_51, ntStatus^0'=ntStatus^post_51, pIrb^0'=pIrb^post_51, phi_io_compl^0'=phi_io_compl^post_51, phi_nSUC_ret^0'=phi_nSUC_ret^post_51, prevCancel^0'=prevCancel^post_51, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_51, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_51, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_51, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_51, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_51, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_51, [ 1<=k4^0 && k4^post_51==-1+k4^0 && i___02424^post_51==Irql^0 && keR^1_4_2==1 && keR^post_51==0 && AsyncAddressData^0==AsyncAddressData^post_51 && BusResetIrp^0==BusResetIrp^post_51 && CromData^0==CromData^post_51 && DeviceObject^0==DeviceObject^post_51 && Irp^0==Irp^post_51 && Irql^0==Irql^post_51 && IsochDetachData^0==IsochDetachData^post_51 && ResourceIrp^0==ResourceIrp^post_51 && StackSize^0==StackSize^post_51 && __rho_10_^0==__rho_10_^post_51 && __rho_11_^0==__rho_11_^post_51 && __rho_12_^0==__rho_12_^post_51 && __rho_1_^0==__rho_1_^post_51 && __rho_2_^0==__rho_2_^post_51 && __rho_3_^0==__rho_3_^post_51 && __rho_4_^0==__rho_4_^post_51 && __rho_5_^0==__rho_5_^post_51 && __rho_666_^0==__rho_666_^post_51 && __rho_7_^0==__rho_7_^post_51 && __rho_8_^0==__rho_8_^post_51 && __rho_9_^0==__rho_9_^post_51 && a11^0==a11^post_51 && a1818^0==a1818^post_51 && a2525^0==a2525^post_51 && a2828^0==a2828^post_51 && a3131^0==a3131^post_51 && a3232^0==a3232^post_51 && a3434^0==a3434^post_51 && a3737^0==a3737^post_51 && a3838^0==a3838^post_51 && a4343^0==a4343^post_51 && a4545^0==a4545^post_51 && a77^0==a77^post_51 && b22^0==b22^post_51 && b2626^0==b2626^post_51 && b2929^0==b2929^post_51 && b3333^0==b3333^post_51 && b3535^0==b3535^post_51 && i^0==i^post_51 && i___01313^0==i___01313^post_51 && i___01717^0==i___01717^post_51 && i___02020^0==i___02020^post_51 && i___04040^0==i___04040^post_51 && i___04747^0==i___04747^post_51 && i___099^0==i___099^post_51 && ioA^0==ioA^post_51 && ioR^0==ioR^post_51 && k1^0==k1^post_51 && k2^0==k2^post_51 && k3^0==k3^post_51 && k5^0==k5^post_51 && 0==keA^post_51 && ntStatus^0==ntStatus^post_51 && pIrb^0==pIrb^post_51 && phi_io_compl^0==phi_io_compl^post_51 && phi_nSUC_ret^0==phi_nSUC_ret^post_51 && prevCancel^0==prevCancel^post_51 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_51 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_51 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_51 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_51 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_51 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_51 ], cost: 2
     95: l1 -> l19 : BusResetIrp^0'=BusResetIrp^post_38, __rho_12_^0'=k5^post_50, a4343^0'=0, a4545^0'=BusResetIrp^post_38, i___04040^0'=Irql^0, k5^0'=0, keA^0'=0, keR^0'=0, phi_io_compl^0'=1, prevCancel^0'=0, ret_IoSetCancelRoutine4444^0'=0, [ k4^0<=0 && k5^post_50>=1 ], cost: 2+2*k5^post_50
     64: l2 -> l1 : __rho_11_^0'=__rho_11_^post_1, i___02020^0'=Irql^0, k4^0'=__rho_11_^post_1, keA^0'=0, keR^0'=0, [ k3^0<=0 ], cost: 2
     63: l4 -> l2 : __rho_10_^0'=__rho_10_^post_15, i___01313^0'=Irql^0, k3^0'=__rho_10_^post_15, keR^0'=0, [ k2^0<=0 ], cost: 2
     94: l4 -> l2 : IsochDetachData^0'=IsochDetachData^post_2, __rho_10_^0'=__rho_10_^post_15, a1818^0'=IsochDetachData^post_2, i^0'=i^post_2, i___01313^0'=Irql^0, i___01717^0'=Irql^0, k3^0'=0, keA^0'=0, keR^0'=0, [ k2^0<=0 && __rho_10_^post_15>=1 ], cost: 2+2*__rho_10_^post_15
     98: l4 -> l4 : AsyncAddressData^0'=AsyncAddressData^post_14, __rho_7_^0'=__rho_7_^post_14, __rho_8_^0'=__rho_8_^post_10, __rho_9_^0'=__rho_9_^post_7, k2^0'=-1+k2^0, [ 1<=k2^0 ], cost: 8
     60: l10 -> l18 : CromData^0'=CromData^post_27, k1^0'=-1+k1^0, [ 1<=k1^0 ], cost: 2
     61: l10 -> l4 : __rho_4_^0'=__rho_4_^post_28, i___099^0'=Irql^0, k2^0'=__rho_4_^post_28, keA^0'=0, keR^0'=0, [ k1^0<=0 ], cost: 2
     24: l18 -> l10 : [ CromData^0<=0 ], cost: 1
    100: l18 -> l10 : __rho_2_^0'=__rho_2_^post_26, __rho_3_^0'=__rho_3_^post_21, a77^0'=CromData^0, [ 1<=CromData^0 ], cost: 5
     69: l19 -> l26 : i___04747^0'=Irql^0, keR^0'=0, [ k5^0<=0 ], cost: 2
     29: l21 -> l10 : __rho_5_^0'=__rho_5_^post_30, k1^0'=__rho_5_^post_30, keA^0'=0, ntStatus^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, [], cost: 1
     57: l26 -> [35] : [ -2+ntStatus^0==0 ], cost: NONTERM
     70: l26 -> [35] : [ 3<=ntStatus^0 ], cost: NONTERM
     71: l26 -> [35] : [ 1+ntStatus^0<=2 ], cost: NONTERM
     47: l32 -> l1 : [ IsochResourceData^0<=0 ], cost: 1
     72: l32 -> l1 : ResourceIrp^0'=0, StackSize^0'=a2525^post_49, a2525^0'=a2525^post_49, b2626^0'=0, pIrb^0'=pIrb^post_49, ret_IoAllocateIrp2727^0'=0, [ 1<=IsochResourceData^0 ], cost: 2
     58: l34 -> l21 : AsyncAddressData^0'=AsyncAddressData^post_52, BusResetIrp^0'=BusResetIrp^post_52, CromData^0'=CromData^post_52, DeviceObject^0'=DeviceObject^post_52, Irp^0'=Irp^post_52, Irql^0'=Irql^post_52, IsochDetachData^0'=IsochDetachData^post_52, IsochResourceData^0'=IsochResourceData^post_52, ResourceIrp^0'=ResourceIrp^post_52, StackSize^0'=StackSize^post_52, __rho_10_^0'=__rho_10_^post_52, __rho_11_^0'=__rho_11_^post_52, __rho_12_^0'=__rho_12_^post_52, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_52, __rho_3_^0'=__rho_3_^post_52, __rho_4_^0'=__rho_4_^post_52, __rho_5_^0'=__rho_5_^post_52, __rho_666_^0'=__rho_666_^post_52, __rho_7_^0'=__rho_7_^post_52, __rho_8_^0'=__rho_8_^post_52, __rho_9_^0'=__rho_9_^post_52, a11^0'=a11^post_52, a1818^0'=a1818^post_52, a2525^0'=a2525^post_52, a2828^0'=a2828^post_52, a3131^0'=a3131^post_52, a3232^0'=a3232^post_52, a3434^0'=a3434^post_52, a3737^0'=a3737^post_52, a3838^0'=a3838^post_52, a4343^0'=a4343^post_52, a4545^0'=a4545^post_52, a77^0'=a77^post_52, b22^0'=b22^post_52, b2626^0'=b2626^post_52, b2929^0'=b2929^post_52, b3333^0'=b3333^post_52, b3535^0'=b3535^post_52, i^0'=i^post_52, i___01313^0'=i___01313^post_52, i___01717^0'=i___01717^post_52, i___02020^0'=i___02020^post_52, i___02424^0'=i___02424^post_52, i___04040^0'=i___04040^post_52, i___04747^0'=i___04747^post_52, i___099^0'=i___099^post_52, ioA^0'=ioA^post_52, ioR^0'=ioR^post_52, k1^0'=k1^post_52, k2^0'=k2^post_52, k3^0'=k3^post_52, k4^0'=k4^post_52, k5^0'=k5^post_52, keA^0'=keA^post_52, keR^0'=keR^post_52, ntStatus^0'=ntStatus^post_52, pIrb^0'=pIrb^post_52, phi_io_compl^0'=phi_io_compl^post_52, phi_nSUC_ret^0'=phi_nSUC_ret^post_52, prevCancel^0'=prevCancel^post_52, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_52, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_52, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_52, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_52, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_52, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_52, [ AsyncAddressData^0==AsyncAddressData^post_53 && BusResetIrp^0==BusResetIrp^post_53 && CromData^0==CromData^post_53 && DeviceObject^0==DeviceObject^post_53 && Irp^0==Irp^post_53 && Irql^0==Irql^post_53 && IsochDetachData^0==IsochDetachData^post_53 && IsochResourceData^0==IsochResourceData^post_53 && ResourceIrp^0==ResourceIrp^post_53 && StackSize^0==StackSize^post_53 && __rho_10_^0==__rho_10_^post_53 && __rho_11_^0==__rho_11_^post_53 && __rho_12_^0==__rho_12_^post_53 && __rho_1_^0==__rho_1_^post_53 && __rho_2_^0==__rho_2_^post_53 && __rho_3_^0==__rho_3_^post_53 && __rho_4_^0==__rho_4_^post_53 && __rho_5_^0==__rho_5_^post_53 && __rho_666_^0==__rho_666_^post_53 && __rho_7_^0==__rho_7_^post_53 && __rho_8_^0==__rho_8_^post_53 && __rho_9_^0==__rho_9_^post_53 && a11^0==a11^post_53 && a1818^0==a1818^post_53 && a2525^0==a2525^post_53 && a2828^0==a2828^post_53 && a3131^0==a3131^post_53 && a3232^0==a3232^post_53 && a3434^0==a3434^post_53 && a3737^0==a3737^post_53 && a3838^0==a3838^post_53 && a4343^0==a4343^post_53 && a4545^0==a4545^post_53 && a77^0==a77^post_53 && b22^0==b22^post_53 && b2626^0==b2626^post_53 && b2929^0==b2929^post_53 && b3333^0==b3333^post_53 && b3535^0==b3535^post_53 && i^0==i^post_53 && i___01313^0==i___01313^post_53 && i___01717^0==i___01717^post_53 && i___02020^0==i___02020^post_53 && i___02424^0==i___02424^post_53 && i___04040^0==i___04040^post_53 && i___04747^0==i___04747^post_53 && i___099^0==i___099^post_53 && ioA^0==ioA^post_53 && ioR^0==ioR^post_53 && k1^0==k1^post_53 && k2^0==k2^post_53 && k3^0==k3^post_53 && k4^0==k4^post_53 && k5^0==k5^post_53 && keA^0==keA^post_53 && keR^0==keR^post_53 && ntStatus^0==ntStatus^post_53 && pIrb^0==pIrb^post_53 && phi_io_compl^0==phi_io_compl^post_53 && phi_nSUC_ret^0==phi_nSUC_ret^post_53 && prevCancel^0==prevCancel^post_53 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_53 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_53 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_53 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_53 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_53 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_53 && ioR^post_52==0 && ioA^post_52==ioR^post_52 && keR^post_52==ioA^post_52 && keA^post_52==keR^post_52 && phi_nSUC_ret^post_52==0 && phi_io_compl^post_52==0 && AsyncAddressData^post_53==AsyncAddressData^post_52 && BusResetIrp^post_53==BusResetIrp^post_52 && CromData^post_53==CromData^post_52 && DeviceObject^post_53==DeviceObject^post_52 && Irp^post_53==Irp^post_52 && Irql^post_53==Irql^post_52 && IsochDetachData^post_53==IsochDetachData^post_52 && IsochResourceData^post_53==IsochResourceData^post_52 && ResourceIrp^post_53==ResourceIrp^post_52 && StackSize^post_53==StackSize^post_52 && __rho_10_^post_53==__rho_10_^post_52 && __rho_11_^post_53==__rho_11_^post_52 && __rho_12_^post_53==__rho_12_^post_52 && __rho_2_^post_53==__rho_2_^post_52 && __rho_3_^post_53==__rho_3_^post_52 && __rho_4_^post_53==__rho_4_^post_52 && __rho_5_^post_53==__rho_5_^post_52 && __rho_7_^post_53==__rho_7_^post_52 && __rho_8_^post_53==__rho_8_^post_52 && __rho_9_^post_53==__rho_9_^post_52 && a11^post_53==a11^post_52 && a1818^post_53==a1818^post_52 && a2525^post_53==a2525^post_52 && a2828^post_53==a2828^post_52 && a3131^post_53==a3131^post_52 && a3232^post_53==a3232^post_52 && a3434^post_53==a3434^post_52 && a3737^post_53==a3737^post_52 && a3838^post_53==a3838^post_52 && a4343^post_53==a4343^post_52 && a4545^post_53==a4545^post_52 && a77^post_53==a77^post_52 && b22^post_53==b22^post_52 && b2626^post_53==b2626^post_52 && b2929^post_53==b2929^post_52 && b3333^post_53==b3333^post_52 && b3535^post_53==b3535^post_52 && i^post_53==i^post_52 && i___01313^post_53==i___01313^post_52 && i___01717^post_53==i___01717^post_52 && i___02020^post_53==i___02020^post_52 && i___02424^post_53==i___02424^post_52 && i___04040^post_53==i___04040^post_52 && i___04747^post_53==i___04747^post_52 && i___099^post_53==i___099^post_52 && k1^post_53==k1^post_52 && k2^post_53==k2^post_52 && k3^post_53==k3^post_52 && k4^post_53==k4^post_52 && k5^post_53==k5^post_52 && ntStatus^post_53==ntStatus^post_52 && pIrb^post_53==pIrb^post_52 && prevCancel^post_53==prevCancel^post_52 && ret_ExAllocatePool3030^post_53==ret_ExAllocatePool3030^post_52 && ret_IoAllocateIrp2727^post_53==ret_IoAllocateIrp2727^post_52 && ret_IoSetCancelRoutine4444^post_53==ret_IoSetCancelRoutine4444^post_52 && ret_IoSetDeviceInterfaceState44^post_53==ret_IoSetDeviceInterfaceState44^post_52 && ret_t1394Diag_PnpStopDevice33^post_53==ret_t1394Diag_PnpStopDevice33^post_52 && ret_t1394_SubmitIrpSynch3636^post_53==ret_t1394_SubmitIrpSynch3636^post_52 && __rho_1_^post_52<=0 ], cost: 3
     59: l34 -> l21 : AsyncAddressData^0'=AsyncAddressData^post_52, BusResetIrp^0'=BusResetIrp^post_52, CromData^0'=CromData^post_52, DeviceObject^0'=DeviceObject^post_52, Irp^0'=Irp^post_52, Irql^0'=Irql^post_52, IsochDetachData^0'=IsochDetachData^post_52, IsochResourceData^0'=IsochResourceData^post_52, ResourceIrp^0'=ResourceIrp^post_52, StackSize^0'=StackSize^post_52, __rho_10_^0'=__rho_10_^post_52, __rho_11_^0'=__rho_11_^post_52, __rho_12_^0'=__rho_12_^post_52, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_52, __rho_3_^0'=__rho_3_^post_52, __rho_4_^0'=__rho_4_^post_52, __rho_5_^0'=__rho_5_^post_52, __rho_666_^0'=__rho_666_^post_52, __rho_7_^0'=__rho_7_^post_52, __rho_8_^0'=__rho_8_^post_52, __rho_9_^0'=__rho_9_^post_52, a11^0'=DeviceObject^post_52, a1818^0'=a1818^post_52, a2525^0'=a2525^post_52, a2828^0'=a2828^post_52, a3131^0'=a3131^post_52, a3232^0'=a3232^post_52, a3434^0'=a3434^post_52, a3737^0'=a3737^post_52, a3838^0'=a3838^post_52, a4343^0'=a4343^post_52, a4545^0'=a4545^post_52, a77^0'=a77^post_52, b22^0'=Irp^post_52, b2626^0'=b2626^post_52, b2929^0'=b2929^post_52, b3333^0'=b3333^post_52, b3535^0'=b3535^post_52, i^0'=i^post_52, i___01313^0'=i___01313^post_52, i___01717^0'=i___01717^post_52, i___02020^0'=i___02020^post_52, i___02424^0'=i___02424^post_52, i___04040^0'=i___04040^post_52, i___04747^0'=i___04747^post_52, i___099^0'=i___099^post_52, ioA^0'=ioA^post_52, ioR^0'=ioR^post_52, k1^0'=k1^post_52, k2^0'=k2^post_52, k3^0'=k3^post_52, k4^0'=k4^post_52, k5^0'=k5^post_52, keA^0'=keA^post_52, keR^0'=keR^post_52, ntStatus^0'=0, pIrb^0'=pIrb^post_52, phi_io_compl^0'=phi_io_compl^post_52, phi_nSUC_ret^0'=phi_nSUC_ret^post_52, prevCancel^0'=prevCancel^post_52, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_52, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_52, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_52, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_52, ret_t1394Diag_PnpStopDevice33^0'=0, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_52, [ AsyncAddressData^0==AsyncAddressData^post_53 && BusResetIrp^0==BusResetIrp^post_53 && CromData^0==CromData^post_53 && DeviceObject^0==DeviceObject^post_53 && Irp^0==Irp^post_53 && Irql^0==Irql^post_53 && IsochDetachData^0==IsochDetachData^post_53 && IsochResourceData^0==IsochResourceData^post_53 && ResourceIrp^0==ResourceIrp^post_53 && StackSize^0==StackSize^post_53 && __rho_10_^0==__rho_10_^post_53 && __rho_11_^0==__rho_11_^post_53 && __rho_12_^0==__rho_12_^post_53 && __rho_1_^0==__rho_1_^post_53 && __rho_2_^0==__rho_2_^post_53 && __rho_3_^0==__rho_3_^post_53 && __rho_4_^0==__rho_4_^post_53 && __rho_5_^0==__rho_5_^post_53 && __rho_666_^0==__rho_666_^post_53 && __rho_7_^0==__rho_7_^post_53 && __rho_8_^0==__rho_8_^post_53 && __rho_9_^0==__rho_9_^post_53 && a11^0==a11^post_53 && a1818^0==a1818^post_53 && a2525^0==a2525^post_53 && a2828^0==a2828^post_53 && a3131^0==a3131^post_53 && a3232^0==a3232^post_53 && a3434^0==a3434^post_53 && a3737^0==a3737^post_53 && a3838^0==a3838^post_53 && a4343^0==a4343^post_53 && a4545^0==a4545^post_53 && a77^0==a77^post_53 && b22^0==b22^post_53 && b2626^0==b2626^post_53 && b2929^0==b2929^post_53 && b3333^0==b3333^post_53 && b3535^0==b3535^post_53 && i^0==i^post_53 && i___01313^0==i___01313^post_53 && i___01717^0==i___01717^post_53 && i___02020^0==i___02020^post_53 && i___02424^0==i___02424^post_53 && i___04040^0==i___04040^post_53 && i___04747^0==i___04747^post_53 && i___099^0==i___099^post_53 && ioA^0==ioA^post_53 && ioR^0==ioR^post_53 && k1^0==k1^post_53 && k2^0==k2^post_53 && k3^0==k3^post_53 && k4^0==k4^post_53 && k5^0==k5^post_53 && keA^0==keA^post_53 && keR^0==keR^post_53 && ntStatus^0==ntStatus^post_53 && pIrb^0==pIrb^post_53 && phi_io_compl^0==phi_io_compl^post_53 && phi_nSUC_ret^0==phi_nSUC_ret^post_53 && prevCancel^0==prevCancel^post_53 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_53 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_53 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_53 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_53 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_53 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_53 && ioR^post_52==0 && ioA^post_52==ioR^post_52 && keR^post_52==ioA^post_52 && keA^post_52==keR^post_52 && phi_nSUC_ret^post_52==0 && phi_io_compl^post_52==0 && AsyncAddressData^post_53==AsyncAddressData^post_52 && BusResetIrp^post_53==BusResetIrp^post_52 && CromData^post_53==CromData^post_52 && DeviceObject^post_53==DeviceObject^post_52 && Irp^post_53==Irp^post_52 && Irql^post_53==Irql^post_52 && IsochDetachData^post_53==IsochDetachData^post_52 && IsochResourceData^post_53==IsochResourceData^post_52 && ResourceIrp^post_53==ResourceIrp^post_52 && StackSize^post_53==StackSize^post_52 && __rho_10_^post_53==__rho_10_^post_52 && __rho_11_^post_53==__rho_11_^post_52 && __rho_12_^post_53==__rho_12_^post_52 && __rho_2_^post_53==__rho_2_^post_52 && __rho_3_^post_53==__rho_3_^post_52 && __rho_4_^post_53==__rho_4_^post_52 && __rho_5_^post_53==__rho_5_^post_52 && __rho_7_^post_53==__rho_7_^post_52 && __rho_8_^post_53==__rho_8_^post_52 && __rho_9_^post_53==__rho_9_^post_52 && a11^post_53==a11^post_52 && a1818^post_53==a1818^post_52 && a2525^post_53==a2525^post_52 && a2828^post_53==a2828^post_52 && a3131^post_53==a3131^post_52 && a3232^post_53==a3232^post_52 && a3434^post_53==a3434^post_52 && a3737^post_53==a3737^post_52 && a3838^post_53==a3838^post_52 && a4343^post_53==a4343^post_52 && a4545^post_53==a4545^post_52 && a77^post_53==a77^post_52 && b22^post_53==b22^post_52 && b2626^post_53==b2626^post_52 && b2929^post_53==b2929^post_52 && b3333^post_53==b3333^post_52 && b3535^post_53==b3535^post_52 && i^post_53==i^post_52 && i___01313^post_53==i___01313^post_52 && i___01717^post_53==i___01717^post_52 && i___02020^post_53==i___02020^post_52 && i___02424^post_53==i___02424^post_52 && i___04040^post_53==i___04040^post_52 && i___04747^post_53==i___04747^post_52 && i___099^post_53==i___099^post_52 && k1^post_53==k1^post_52 && k2^post_53==k2^post_52 && k3^post_53==k3^post_52 && k4^post_53==k4^post_52 && k5^post_53==k5^post_52 && ntStatus^post_53==ntStatus^post_52 && pIrb^post_53==pIrb^post_52 && prevCancel^post_53==prevCancel^post_52 && ret_ExAllocatePool3030^post_53==ret_ExAllocatePool3030^post_52 && ret_IoAllocateIrp2727^post_53==ret_IoAllocateIrp2727^post_52 && ret_IoSetCancelRoutine4444^post_53==ret_IoSetCancelRoutine4444^post_52 && ret_IoSetDeviceInterfaceState44^post_53==ret_IoSetDeviceInterfaceState44^post_52 && ret_t1394Diag_PnpStopDevice33^post_53==ret_t1394Diag_PnpStopDevice33^post_52 && ret_t1394_SubmitIrpSynch3636^post_53==ret_t1394_SubmitIrpSynch3636^post_52 && 1<=__rho_1_^post_52 ], cost: 3

Accelerating simple loops of location 4.
   Accelerating the following rules:
     98: l4 -> l4 : AsyncAddressData^0'=AsyncAddressData^post_14, __rho_7_^0'=__rho_7_^post_14, __rho_8_^0'=__rho_8_^post_10, __rho_9_^0'=__rho_9_^post_7, k2^0'=-1+k2^0, [ 1<=k2^0 ], cost: 8

   Accelerated rule 98 with backward acceleration, yielding the new rule 101.
[accelerate] Nesting with 1 inner and 1 outer candidates
   Removing the simple loops: 98.

Accelerated all simple loops using metering functions (where possible):
   Start location: l34
     66: l1 -> l19 : AsyncAddressData^0'=AsyncAddressData^post_50, BusResetIrp^0'=BusResetIrp^post_50, CromData^0'=CromData^post_50, DeviceObject^0'=DeviceObject^post_50, Irp^0'=Irp^post_50, Irql^0'=Irql^post_50, IsochDetachData^0'=IsochDetachData^post_50, IsochResourceData^0'=IsochResourceData^post_50, ResourceIrp^0'=ResourceIrp^post_50, StackSize^0'=StackSize^post_50, __rho_10_^0'=__rho_10_^post_50, __rho_11_^0'=__rho_11_^post_50, __rho_12_^0'=__rho_12_^post_50, __rho_1_^0'=__rho_1_^post_50, __rho_2_^0'=__rho_2_^post_50, __rho_3_^0'=__rho_3_^post_50, __rho_4_^0'=__rho_4_^post_50, __rho_5_^0'=__rho_5_^post_50, __rho_666_^0'=__rho_666_^post_50, __rho_7_^0'=__rho_7_^post_50, __rho_8_^0'=__rho_8_^post_50, __rho_9_^0'=__rho_9_^post_50, a11^0'=a11^post_50, a1818^0'=a1818^post_50, a2525^0'=a2525^post_50, a2828^0'=a2828^post_50, a3131^0'=a3131^post_50, a3232^0'=a3232^post_50, a3434^0'=a3434^post_50, a3737^0'=a3737^post_50, a3838^0'=a3838^post_50, a4343^0'=a4343^post_50, a4545^0'=a4545^post_50, a77^0'=a77^post_50, b22^0'=b22^post_50, b2626^0'=b2626^post_50, b2929^0'=b2929^post_50, b3333^0'=b3333^post_50, b3535^0'=b3535^post_50, i^0'=i^post_50, i___01313^0'=i___01313^post_50, i___01717^0'=i___01717^post_50, i___02020^0'=i___02020^post_50, i___02424^0'=i___02424^post_50, i___04040^0'=i___04040^post_50, i___04747^0'=i___04747^post_50, i___099^0'=i___099^post_50, ioA^0'=ioA^post_50, ioR^0'=ioR^post_50, k1^0'=k1^post_50, k2^0'=k2^post_50, k3^0'=k3^post_50, k4^0'=k4^post_50, k5^0'=k5^post_50, keA^0'=keA^post_50, keR^0'=keR^post_50, ntStatus^0'=ntStatus^post_50, pIrb^0'=pIrb^post_50, phi_io_compl^0'=phi_io_compl^post_50, phi_nSUC_ret^0'=phi_nSUC_ret^post_50, prevCancel^0'=prevCancel^post_50, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_50, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_50, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_50, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_50, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_50, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_50, [ k4^0<=0 && i___04040^post_50==Irql^0 && keR^1_4_1==1 && keR^post_50==0 && keA^1_5==1 && keA^post_50==0 && k5^post_50==__rho_12_^post_50 && AsyncAddressData^0==AsyncAddressData^post_50 && BusResetIrp^0==BusResetIrp^post_50 && CromData^0==CromData^post_50 && DeviceObject^0==DeviceObject^post_50 && Irp^0==Irp^post_50 && Irql^0==Irql^post_50 && IsochDetachData^0==IsochDetachData^post_50 && IsochResourceData^0==IsochResourceData^post_50 && ResourceIrp^0==ResourceIrp^post_50 && StackSize^0==StackSize^post_50 && __rho_10_^0==__rho_10_^post_50 && __rho_11_^0==__rho_11_^post_50 && __rho_1_^0==__rho_1_^post_50 && __rho_2_^0==__rho_2_^post_50 && __rho_3_^0==__rho_3_^post_50 && __rho_4_^0==__rho_4_^post_50 && __rho_5_^0==__rho_5_^post_50 && __rho_666_^0==__rho_666_^post_50 && __rho_7_^0==__rho_7_^post_50 && __rho_8_^0==__rho_8_^post_50 && __rho_9_^0==__rho_9_^post_50 && a11^0==a11^post_50 && a1818^0==a1818^post_50 && a2525^0==a2525^post_50 && a2828^0==a2828^post_50 && a3131^0==a3131^post_50 && a3232^0==a3232^post_50 && a3434^0==a3434^post_50 && a3737^0==a3737^post_50 && a3838^0==a3838^post_50 && a4343^0==a4343^post_50 && a4545^0==a4545^post_50 && a77^0==a77^post_50 && b22^0==b22^post_50 && b2626^0==b2626^post_50 && b2929^0==b2929^post_50 && b3333^0==b3333^post_50 && b3535^0==b3535^post_50 && i^0==i^post_50 && i___01313^0==i___01313^post_50 && i___01717^0==i___01717^post_50 && i___02020^0==i___02020^post_50 && i___02424^0==i___02424^post_50 && i___04747^0==i___04747^post_50 && i___099^0==i___099^post_50 && ioA^0==ioA^post_50 && ioR^0==ioR^post_50 && k1^0==k1^post_50 && k2^0==k2^post_50 && k3^0==k3^post_50 && k4^0==k4^post_50 && ntStatus^0==ntStatus^post_50 && pIrb^0==pIrb^post_50 && phi_io_compl^0==phi_io_compl^post_50 && phi_nSUC_ret^0==phi_nSUC_ret^post_50 && prevCancel^0==prevCancel^post_50 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_50 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_50 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_50 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_50 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_50 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_50 ], cost: 2
     67: l1 -> l32 : AsyncAddressData^0'=AsyncAddressData^post_51, BusResetIrp^0'=BusResetIrp^post_51, CromData^0'=CromData^post_51, DeviceObject^0'=DeviceObject^post_51, Irp^0'=Irp^post_51, Irql^0'=Irql^post_51, IsochDetachData^0'=IsochDetachData^post_51, IsochResourceData^0'=IsochResourceData^post_51, ResourceIrp^0'=ResourceIrp^post_51, StackSize^0'=StackSize^post_51, __rho_10_^0'=__rho_10_^post_51, __rho_11_^0'=__rho_11_^post_51, __rho_12_^0'=__rho_12_^post_51, __rho_1_^0'=__rho_1_^post_51, __rho_2_^0'=__rho_2_^post_51, __rho_3_^0'=__rho_3_^post_51, __rho_4_^0'=__rho_4_^post_51, __rho_5_^0'=__rho_5_^post_51, __rho_666_^0'=__rho_666_^post_51, __rho_7_^0'=__rho_7_^post_51, __rho_8_^0'=__rho_8_^post_51, __rho_9_^0'=__rho_9_^post_51, a11^0'=a11^post_51, a1818^0'=a1818^post_51, a2525^0'=a2525^post_51, a2828^0'=a2828^post_51, a3131^0'=a3131^post_51, a3232^0'=a3232^post_51, a3434^0'=a3434^post_51, a3737^0'=a3737^post_51, a3838^0'=a3838^post_51, a4343^0'=a4343^post_51, a4545^0'=a4545^post_51, a77^0'=a77^post_51, b22^0'=b22^post_51, b2626^0'=b2626^post_51, b2929^0'=b2929^post_51, b3333^0'=b3333^post_51, b3535^0'=b3535^post_51, i^0'=i^post_51, i___01313^0'=i___01313^post_51, i___01717^0'=i___01717^post_51, i___02020^0'=i___02020^post_51, i___02424^0'=i___02424^post_51, i___04040^0'=i___04040^post_51, i___04747^0'=i___04747^post_51, i___099^0'=i___099^post_51, ioA^0'=ioA^post_51, ioR^0'=ioR^post_51, k1^0'=k1^post_51, k2^0'=k2^post_51, k3^0'=k3^post_51, k4^0'=k4^post_51, k5^0'=k5^post_51, keA^0'=keA^post_51, keR^0'=keR^post_51, ntStatus^0'=ntStatus^post_51, pIrb^0'=pIrb^post_51, phi_io_compl^0'=phi_io_compl^post_51, phi_nSUC_ret^0'=phi_nSUC_ret^post_51, prevCancel^0'=prevCancel^post_51, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_51, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_51, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_51, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_51, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_51, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_51, [ 1<=k4^0 && k4^post_51==-1+k4^0 && i___02424^post_51==Irql^0 && keR^1_4_2==1 && keR^post_51==0 && AsyncAddressData^0==AsyncAddressData^post_51 && BusResetIrp^0==BusResetIrp^post_51 && CromData^0==CromData^post_51 && DeviceObject^0==DeviceObject^post_51 && Irp^0==Irp^post_51 && Irql^0==Irql^post_51 && IsochDetachData^0==IsochDetachData^post_51 && ResourceIrp^0==ResourceIrp^post_51 && StackSize^0==StackSize^post_51 && __rho_10_^0==__rho_10_^post_51 && __rho_11_^0==__rho_11_^post_51 && __rho_12_^0==__rho_12_^post_51 && __rho_1_^0==__rho_1_^post_51 && __rho_2_^0==__rho_2_^post_51 && __rho_3_^0==__rho_3_^post_51 && __rho_4_^0==__rho_4_^post_51 && __rho_5_^0==__rho_5_^post_51 && __rho_666_^0==__rho_666_^post_51 && __rho_7_^0==__rho_7_^post_51 && __rho_8_^0==__rho_8_^post_51 && __rho_9_^0==__rho_9_^post_51 && a11^0==a11^post_51 && a1818^0==a1818^post_51 && a2525^0==a2525^post_51 && a2828^0==a2828^post_51 && a3131^0==a3131^post_51 && a3232^0==a3232^post_51 && a3434^0==a3434^post_51 && a3737^0==a3737^post_51 && a3838^0==a3838^post_51 && a4343^0==a4343^post_51 && a4545^0==a4545^post_51 && a77^0==a77^post_51 && b22^0==b22^post_51 && b2626^0==b2626^post_51 && b2929^0==b2929^post_51 && b3333^0==b3333^post_51 && b3535^0==b3535^post_51 && i^0==i^post_51 && i___01313^0==i___01313^post_51 && i___01717^0==i___01717^post_51 && i___02020^0==i___02020^post_51 && i___04040^0==i___04040^post_51 && i___04747^0==i___04747^post_51 && i___099^0==i___099^post_51 && ioA^0==ioA^post_51 && ioR^0==ioR^post_51 && k1^0==k1^post_51 && k2^0==k2^post_51 && k3^0==k3^post_51 && k5^0==k5^post_51 && 0==keA^post_51 && ntStatus^0==ntStatus^post_51 && pIrb^0==pIrb^post_51 && phi_io_compl^0==phi_io_compl^post_51 && phi_nSUC_ret^0==phi_nSUC_ret^post_51 && prevCancel^0==prevCancel^post_51 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_51 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_51 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_51 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_51 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_51 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_51 ], cost: 2
     95: l1 -> l19 : BusResetIrp^0'=BusResetIrp^post_38, __rho_12_^0'=k5^post_50, a4343^0'=0, a4545^0'=BusResetIrp^post_38, i___04040^0'=Irql^0, k5^0'=0, keA^0'=0, keR^0'=0, phi_io_compl^0'=1, prevCancel^0'=0, ret_IoSetCancelRoutine4444^0'=0, [ k4^0<=0 && k5^post_50>=1 ], cost: 2+2*k5^post_50
     64: l2 -> l1 : __rho_11_^0'=__rho_11_^post_1, i___02020^0'=Irql^0, k4^0'=__rho_11_^post_1, keA^0'=0, keR^0'=0, [ k3^0<=0 ], cost: 2
     63: l4 -> l2 : __rho_10_^0'=__rho_10_^post_15, i___01313^0'=Irql^0, k3^0'=__rho_10_^post_15, keR^0'=0, [ k2^0<=0 ], cost: 2
     94: l4 -> l2 : IsochDetachData^0'=IsochDetachData^post_2, __rho_10_^0'=__rho_10_^post_15, a1818^0'=IsochDetachData^post_2, i^0'=i^post_2, i___01313^0'=Irql^0, i___01717^0'=Irql^0, k3^0'=0, keA^0'=0, keR^0'=0, [ k2^0<=0 && __rho_10_^post_15>=1 ], cost: 2+2*__rho_10_^post_15
    101: l4 -> l4 : AsyncAddressData^0'=AsyncAddressData^post_14, __rho_7_^0'=__rho_7_^post_14, __rho_8_^0'=__rho_8_^post_10, __rho_9_^0'=__rho_9_^post_7, k2^0'=0, [ k2^0>=1 ], cost: 8*k2^0
     60: l10 -> l18 : CromData^0'=CromData^post_27, k1^0'=-1+k1^0, [ 1<=k1^0 ], cost: 2
     61: l10 -> l4 : __rho_4_^0'=__rho_4_^post_28, i___099^0'=Irql^0, k2^0'=__rho_4_^post_28, keA^0'=0, keR^0'=0, [ k1^0<=0 ], cost: 2
     24: l18 -> l10 : [ CromData^0<=0 ], cost: 1
    100: l18 -> l10 : __rho_2_^0'=__rho_2_^post_26, __rho_3_^0'=__rho_3_^post_21, a77^0'=CromData^0, [ 1<=CromData^0 ], cost: 5
     69: l19 -> l26 : i___04747^0'=Irql^0, keR^0'=0, [ k5^0<=0 ], cost: 2
     29: l21 -> l10 : __rho_5_^0'=__rho_5_^post_30, k1^0'=__rho_5_^post_30, keA^0'=0, ntStatus^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, [], cost: 1
     57: l26 -> [35] : [ -2+ntStatus^0==0 ], cost: NONTERM
     70: l26 -> [35] : [ 3<=ntStatus^0 ], cost: NONTERM
     71: l26 -> [35] : [ 1+ntStatus^0<=2 ], cost: NONTERM
     47: l32 -> l1 : [ IsochResourceData^0<=0 ], cost: 1
     72: l32 -> l1 : ResourceIrp^0'=0, StackSize^0'=a2525^post_49, a2525^0'=a2525^post_49, b2626^0'=0, pIrb^0'=pIrb^post_49, ret_IoAllocateIrp2727^0'=0, [ 1<=IsochResourceData^0 ], cost: 2
     58: l34 -> l21 : AsyncAddressData^0'=AsyncAddressData^post_52, BusResetIrp^0'=BusResetIrp^post_52, CromData^0'=CromData^post_52, DeviceObject^0'=DeviceObject^post_52, Irp^0'=Irp^post_52, Irql^0'=Irql^post_52, IsochDetachData^0'=IsochDetachData^post_52, IsochResourceData^0'=IsochResourceData^post_52, ResourceIrp^0'=ResourceIrp^post_52, StackSize^0'=StackSize^post_52, __rho_10_^0'=__rho_10_^post_52, __rho_11_^0'=__rho_11_^post_52, __rho_12_^0'=__rho_12_^post_52, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_52, __rho_3_^0'=__rho_3_^post_52, __rho_4_^0'=__rho_4_^post_52, __rho_5_^0'=__rho_5_^post_52, __rho_666_^0'=__rho_666_^post_52, __rho_7_^0'=__rho_7_^post_52, __rho_8_^0'=__rho_8_^post_52, __rho_9_^0'=__rho_9_^post_52, a11^0'=a11^post_52, a1818^0'=a1818^post_52, a2525^0'=a2525^post_52, a2828^0'=a2828^post_52, a3131^0'=a3131^post_52, a3232^0'=a3232^post_52, a3434^0'=a3434^post_52, a3737^0'=a3737^post_52, a3838^0'=a3838^post_52, a4343^0'=a4343^post_52, a4545^0'=a4545^post_52, a77^0'=a77^post_52, b22^0'=b22^post_52, b2626^0'=b2626^post_52, b2929^0'=b2929^post_52, b3333^0'=b3333^post_52, b3535^0'=b3535^post_52, i^0'=i^post_52, i___01313^0'=i___01313^post_52, i___01717^0'=i___01717^post_52, i___02020^0'=i___02020^post_52, i___02424^0'=i___02424^post_52, i___04040^0'=i___04040^post_52, i___04747^0'=i___04747^post_52, i___099^0'=i___099^post_52, ioA^0'=ioA^post_52, ioR^0'=ioR^post_52, k1^0'=k1^post_52, k2^0'=k2^post_52, k3^0'=k3^post_52, k4^0'=k4^post_52, k5^0'=k5^post_52, keA^0'=keA^post_52, keR^0'=keR^post_52, ntStatus^0'=ntStatus^post_52, pIrb^0'=pIrb^post_52, phi_io_compl^0'=phi_io_compl^post_52, phi_nSUC_ret^0'=phi_nSUC_ret^post_52, prevCancel^0'=prevCancel^post_52, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_52, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_52, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_52, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_52, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_52, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_52, [ AsyncAddressData^0==AsyncAddressData^post_53 && BusResetIrp^0==BusResetIrp^post_53 && CromData^0==CromData^post_53 && DeviceObject^0==DeviceObject^post_53 && Irp^0==Irp^post_53 && Irql^0==Irql^post_53 && IsochDetachData^0==IsochDetachData^post_53 && IsochResourceData^0==IsochResourceData^post_53 && ResourceIrp^0==ResourceIrp^post_53 && StackSize^0==StackSize^post_53 && __rho_10_^0==__rho_10_^post_53 && __rho_11_^0==__rho_11_^post_53 && __rho_12_^0==__rho_12_^post_53 && __rho_1_^0==__rho_1_^post_53 && __rho_2_^0==__rho_2_^post_53 && __rho_3_^0==__rho_3_^post_53 && __rho_4_^0==__rho_4_^post_53 && __rho_5_^0==__rho_5_^post_53 && __rho_666_^0==__rho_666_^post_53 && __rho_7_^0==__rho_7_^post_53 && __rho_8_^0==__rho_8_^post_53 && __rho_9_^0==__rho_9_^post_53 && a11^0==a11^post_53 && a1818^0==a1818^post_53 && a2525^0==a2525^post_53 && a2828^0==a2828^post_53 && a3131^0==a3131^post_53 && a3232^0==a3232^post_53 && a3434^0==a3434^post_53 && a3737^0==a3737^post_53 && a3838^0==a3838^post_53 && a4343^0==a4343^post_53 && a4545^0==a4545^post_53 && a77^0==a77^post_53 && b22^0==b22^post_53 && b2626^0==b2626^post_53 && b2929^0==b2929^post_53 && b3333^0==b3333^post_53 && b3535^0==b3535^post_53 && i^0==i^post_53 && i___01313^0==i___01313^post_53 && i___01717^0==i___01717^post_53 && i___02020^0==i___02020^post_53 && i___02424^0==i___02424^post_53 && i___04040^0==i___04040^post_53 && i___04747^0==i___04747^post_53 && i___099^0==i___099^post_53 && ioA^0==ioA^post_53 && ioR^0==ioR^post_53 && k1^0==k1^post_53 && k2^0==k2^post_53 && k3^0==k3^post_53 && k4^0==k4^post_53 && k5^0==k5^post_53 && keA^0==keA^post_53 && keR^0==keR^post_53 && ntStatus^0==ntStatus^post_53 && pIrb^0==pIrb^post_53 && phi_io_compl^0==phi_io_compl^post_53 && phi_nSUC_ret^0==phi_nSUC_ret^post_53 && prevCancel^0==prevCancel^post_53 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_53 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_53 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_53 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_53 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_53 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_53 && ioR^post_52==0 && ioA^post_52==ioR^post_52 && keR^post_52==ioA^post_52 && keA^post_52==keR^post_52 && phi_nSUC_ret^post_52==0 && phi_io_compl^post_52==0 && AsyncAddressData^post_53==AsyncAddressData^post_52 && BusResetIrp^post_53==BusResetIrp^post_52 && CromData^post_53==CromData^post_52 && DeviceObject^post_53==DeviceObject^post_52 && Irp^post_53==Irp^post_52 && Irql^post_53==Irql^post_52 && IsochDetachData^post_53==IsochDetachData^post_52 && IsochResourceData^post_53==IsochResourceData^post_52 && ResourceIrp^post_53==ResourceIrp^post_52 && StackSize^post_53==StackSize^post_52 && __rho_10_^post_53==__rho_10_^post_52 && __rho_11_^post_53==__rho_11_^post_52 && __rho_12_^post_53==__rho_12_^post_52 && __rho_2_^post_53==__rho_2_^post_52 && __rho_3_^post_53==__rho_3_^post_52 && __rho_4_^post_53==__rho_4_^post_52 && __rho_5_^post_53==__rho_5_^post_52 && __rho_7_^post_53==__rho_7_^post_52 && __rho_8_^post_53==__rho_8_^post_52 && __rho_9_^post_53==__rho_9_^post_52 && a11^post_53==a11^post_52 && a1818^post_53==a1818^post_52 && a2525^post_53==a2525^post_52 && a2828^post_53==a2828^post_52 && a3131^post_53==a3131^post_52 && a3232^post_53==a3232^post_52 && a3434^post_53==a3434^post_52 && a3737^post_53==a3737^post_52 && a3838^post_53==a3838^post_52 && a4343^post_53==a4343^post_52 && a4545^post_53==a4545^post_52 && a77^post_53==a77^post_52 && b22^post_53==b22^post_52 && b2626^post_53==b2626^post_52 && b2929^post_53==b2929^post_52 && b3333^post_53==b3333^post_52 && b3535^post_53==b3535^post_52 && i^post_53==i^post_52 && i___01313^post_53==i___01313^post_52 && i___01717^post_53==i___01717^post_52 && i___02020^post_53==i___02020^post_52 && i___02424^post_53==i___02424^post_52 && i___04040^post_53==i___04040^post_52 && i___04747^post_53==i___04747^post_52 && i___099^post_53==i___099^post_52 && k1^post_53==k1^post_52 && k2^post_53==k2^post_52 && k3^post_53==k3^post_52 && k4^post_53==k4^post_52 && k5^post_53==k5^post_52 && ntStatus^post_53==ntStatus^post_52 && pIrb^post_53==pIrb^post_52 && prevCancel^post_53==prevCancel^post_52 && ret_ExAllocatePool3030^post_53==ret_ExAllocatePool3030^post_52 && ret_IoAllocateIrp2727^post_53==ret_IoAllocateIrp2727^post_52 && ret_IoSetCancelRoutine4444^post_53==ret_IoSetCancelRoutine4444^post_52 && ret_IoSetDeviceInterfaceState44^post_53==ret_IoSetDeviceInterfaceState44^post_52 && ret_t1394Diag_PnpStopDevice33^post_53==ret_t1394Diag_PnpStopDevice33^post_52 && ret_t1394_SubmitIrpSynch3636^post_53==ret_t1394_SubmitIrpSynch3636^post_52 && __rho_1_^post_52<=0 ], cost: 3
     59: l34 -> l21 : AsyncAddressData^0'=AsyncAddressData^post_52, BusResetIrp^0'=BusResetIrp^post_52, CromData^0'=CromData^post_52, DeviceObject^0'=DeviceObject^post_52, Irp^0'=Irp^post_52, Irql^0'=Irql^post_52, IsochDetachData^0'=IsochDetachData^post_52, IsochResourceData^0'=IsochResourceData^post_52, ResourceIrp^0'=ResourceIrp^post_52, StackSize^0'=StackSize^post_52, __rho_10_^0'=__rho_10_^post_52, __rho_11_^0'=__rho_11_^post_52, __rho_12_^0'=__rho_12_^post_52, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_52, __rho_3_^0'=__rho_3_^post_52, __rho_4_^0'=__rho_4_^post_52, __rho_5_^0'=__rho_5_^post_52, __rho_666_^0'=__rho_666_^post_52, __rho_7_^0'=__rho_7_^post_52, __rho_8_^0'=__rho_8_^post_52, __rho_9_^0'=__rho_9_^post_52, a11^0'=DeviceObject^post_52, a1818^0'=a1818^post_52, a2525^0'=a2525^post_52, a2828^0'=a2828^post_52, a3131^0'=a3131^post_52, a3232^0'=a3232^post_52, a3434^0'=a3434^post_52, a3737^0'=a3737^post_52, a3838^0'=a3838^post_52, a4343^0'=a4343^post_52, a4545^0'=a4545^post_52, a77^0'=a77^post_52, b22^0'=Irp^post_52, b2626^0'=b2626^post_52, b2929^0'=b2929^post_52, b3333^0'=b3333^post_52, b3535^0'=b3535^post_52, i^0'=i^post_52, i___01313^0'=i___01313^post_52, i___01717^0'=i___01717^post_52, i___02020^0'=i___02020^post_52, i___02424^0'=i___02424^post_52, i___04040^0'=i___04040^post_52, i___04747^0'=i___04747^post_52, i___099^0'=i___099^post_52, ioA^0'=ioA^post_52, ioR^0'=ioR^post_52, k1^0'=k1^post_52, k2^0'=k2^post_52, k3^0'=k3^post_52, k4^0'=k4^post_52, k5^0'=k5^post_52, keA^0'=keA^post_52, keR^0'=keR^post_52, ntStatus^0'=0, pIrb^0'=pIrb^post_52, phi_io_compl^0'=phi_io_compl^post_52, phi_nSUC_ret^0'=phi_nSUC_ret^post_52, prevCancel^0'=prevCancel^post_52, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_52, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_52, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_52, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_52, ret_t1394Diag_PnpStopDevice33^0'=0, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_52, [ AsyncAddressData^0==AsyncAddressData^post_53 && BusResetIrp^0==BusResetIrp^post_53 && CromData^0==CromData^post_53 && DeviceObject^0==DeviceObject^post_53 && Irp^0==Irp^post_53 && Irql^0==Irql^post_53 && IsochDetachData^0==IsochDetachData^post_53 && IsochResourceData^0==IsochResourceData^post_53 && ResourceIrp^0==ResourceIrp^post_53 && StackSize^0==StackSize^post_53 && __rho_10_^0==__rho_10_^post_53 && __rho_11_^0==__rho_11_^post_53 && __rho_12_^0==__rho_12_^post_53 && __rho_1_^0==__rho_1_^post_53 && __rho_2_^0==__rho_2_^post_53 && __rho_3_^0==__rho_3_^post_53 && __rho_4_^0==__rho_4_^post_53 && __rho_5_^0==__rho_5_^post_53 && __rho_666_^0==__rho_666_^post_53 && __rho_7_^0==__rho_7_^post_53 && __rho_8_^0==__rho_8_^post_53 && __rho_9_^0==__rho_9_^post_53 && a11^0==a11^post_53 && a1818^0==a1818^post_53 && a2525^0==a2525^post_53 && a2828^0==a2828^post_53 && a3131^0==a3131^post_53 && a3232^0==a3232^post_53 && a3434^0==a3434^post_53 && a3737^0==a3737^post_53 && a3838^0==a3838^post_53 && a4343^0==a4343^post_53 && a4545^0==a4545^post_53 && a77^0==a77^post_53 && b22^0==b22^post_53 && b2626^0==b2626^post_53 && b2929^0==b2929^post_53 && b3333^0==b3333^post_53 && b3535^0==b3535^post_53 && i^0==i^post_53 && i___01313^0==i___01313^post_53 && i___01717^0==i___01717^post_53 && i___02020^0==i___02020^post_53 && i___02424^0==i___02424^post_53 && i___04040^0==i___04040^post_53 && i___04747^0==i___04747^post_53 && i___099^0==i___099^post_53 && ioA^0==ioA^post_53 && ioR^0==ioR^post_53 && k1^0==k1^post_53 && k2^0==k2^post_53 && k3^0==k3^post_53 && k4^0==k4^post_53 && k5^0==k5^post_53 && keA^0==keA^post_53 && keR^0==keR^post_53 && ntStatus^0==ntStatus^post_53 && pIrb^0==pIrb^post_53 && phi_io_compl^0==phi_io_compl^post_53 && phi_nSUC_ret^0==phi_nSUC_ret^post_53 && prevCancel^0==prevCancel^post_53 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_53 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_53 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_53 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_53 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_53 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_53 && ioR^post_52==0 && ioA^post_52==ioR^post_52 && keR^post_52==ioA^post_52 && keA^post_52==keR^post_52 && phi_nSUC_ret^post_52==0 && phi_io_compl^post_52==0 && AsyncAddressData^post_53==AsyncAddressData^post_52 && BusResetIrp^post_53==BusResetIrp^post_52 && CromData^post_53==CromData^post_52 && DeviceObject^post_53==DeviceObject^post_52 && Irp^post_53==Irp^post_52 && Irql^post_53==Irql^post_52 && IsochDetachData^post_53==IsochDetachData^post_52 && IsochResourceData^post_53==IsochResourceData^post_52 && ResourceIrp^post_53==ResourceIrp^post_52 && StackSize^post_53==StackSize^post_52 && __rho_10_^post_53==__rho_10_^post_52 && __rho_11_^post_53==__rho_11_^post_52 && __rho_12_^post_53==__rho_12_^post_52 && __rho_2_^post_53==__rho_2_^post_52 && __rho_3_^post_53==__rho_3_^post_52 && __rho_4_^post_53==__rho_4_^post_52 && __rho_5_^post_53==__rho_5_^post_52 && __rho_7_^post_53==__rho_7_^post_52 && __rho_8_^post_53==__rho_8_^post_52 && __rho_9_^post_53==__rho_9_^post_52 && a11^post_53==a11^post_52 && a1818^post_53==a1818^post_52 && a2525^post_53==a2525^post_52 && a2828^post_53==a2828^post_52 && a3131^post_53==a3131^post_52 && a3232^post_53==a3232^post_52 && a3434^post_53==a3434^post_52 && a3737^post_53==a3737^post_52 && a3838^post_53==a3838^post_52 && a4343^post_53==a4343^post_52 && a4545^post_53==a4545^post_52 && a77^post_53==a77^post_52 && b22^post_53==b22^post_52 && b2626^post_53==b2626^post_52 && b2929^post_53==b2929^post_52 && b3333^post_53==b3333^post_52 && b3535^post_53==b3535^post_52 && i^post_53==i^post_52 && i___01313^post_53==i___01313^post_52 && i___01717^post_53==i___01717^post_52 && i___02020^post_53==i___02020^post_52 && i___02424^post_53==i___02424^post_52 && i___04040^post_53==i___04040^post_52 && i___04747^post_53==i___04747^post_52 && i___099^post_53==i___099^post_52 && k1^post_53==k1^post_52 && k2^post_53==k2^post_52 && k3^post_53==k3^post_52 && k4^post_53==k4^post_52 && k5^post_53==k5^post_52 && ntStatus^post_53==ntStatus^post_52 && pIrb^post_53==pIrb^post_52 && prevCancel^post_53==prevCancel^post_52 && ret_ExAllocatePool3030^post_53==ret_ExAllocatePool3030^post_52 && ret_IoAllocateIrp2727^post_53==ret_IoAllocateIrp2727^post_52 && ret_IoSetCancelRoutine4444^post_53==ret_IoSetCancelRoutine4444^post_52 && ret_IoSetDeviceInterfaceState44^post_53==ret_IoSetDeviceInterfaceState44^post_52 && ret_t1394Diag_PnpStopDevice33^post_53==ret_t1394Diag_PnpStopDevice33^post_52 && ret_t1394_SubmitIrpSynch3636^post_53==ret_t1394_SubmitIrpSynch3636^post_52 && 1<=__rho_1_^post_52 ], cost: 3

Chained accelerated rules (with incoming rules):
   Start location: l34
     66: l1 -> l19 : AsyncAddressData^0'=AsyncAddressData^post_50, BusResetIrp^0'=BusResetIrp^post_50, CromData^0'=CromData^post_50, DeviceObject^0'=DeviceObject^post_50, Irp^0'=Irp^post_50, Irql^0'=Irql^post_50, IsochDetachData^0'=IsochDetachData^post_50, IsochResourceData^0'=IsochResourceData^post_50, ResourceIrp^0'=ResourceIrp^post_50, StackSize^0'=StackSize^post_50, __rho_10_^0'=__rho_10_^post_50, __rho_11_^0'=__rho_11_^post_50, __rho_12_^0'=__rho_12_^post_50, __rho_1_^0'=__rho_1_^post_50, __rho_2_^0'=__rho_2_^post_50, __rho_3_^0'=__rho_3_^post_50, __rho_4_^0'=__rho_4_^post_50, __rho_5_^0'=__rho_5_^post_50, __rho_666_^0'=__rho_666_^post_50, __rho_7_^0'=__rho_7_^post_50, __rho_8_^0'=__rho_8_^post_50, __rho_9_^0'=__rho_9_^post_50, a11^0'=a11^post_50, a1818^0'=a1818^post_50, a2525^0'=a2525^post_50, a2828^0'=a2828^post_50, a3131^0'=a3131^post_50, a3232^0'=a3232^post_50, a3434^0'=a3434^post_50, a3737^0'=a3737^post_50, a3838^0'=a3838^post_50, a4343^0'=a4343^post_50, a4545^0'=a4545^post_50, a77^0'=a77^post_50, b22^0'=b22^post_50, b2626^0'=b2626^post_50, b2929^0'=b2929^post_50, b3333^0'=b3333^post_50, b3535^0'=b3535^post_50, i^0'=i^post_50, i___01313^0'=i___01313^post_50, i___01717^0'=i___01717^post_50, i___02020^0'=i___02020^post_50, i___02424^0'=i___02424^post_50, i___04040^0'=i___04040^post_50, i___04747^0'=i___04747^post_50, i___099^0'=i___099^post_50, ioA^0'=ioA^post_50, ioR^0'=ioR^post_50, k1^0'=k1^post_50, k2^0'=k2^post_50, k3^0'=k3^post_50, k4^0'=k4^post_50, k5^0'=k5^post_50, keA^0'=keA^post_50, keR^0'=keR^post_50, ntStatus^0'=ntStatus^post_50, pIrb^0'=pIrb^post_50, phi_io_compl^0'=phi_io_compl^post_50, phi_nSUC_ret^0'=phi_nSUC_ret^post_50, prevCancel^0'=prevCancel^post_50, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_50, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_50, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_50, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_50, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_50, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_50, [ k4^0<=0 && i___04040^post_50==Irql^0 && keR^1_4_1==1 && keR^post_50==0 && keA^1_5==1 && keA^post_50==0 && k5^post_50==__rho_12_^post_50 && AsyncAddressData^0==AsyncAddressData^post_50 && BusResetIrp^0==BusResetIrp^post_50 && CromData^0==CromData^post_50 && DeviceObject^0==DeviceObject^post_50 && Irp^0==Irp^post_50 && Irql^0==Irql^post_50 && IsochDetachData^0==IsochDetachData^post_50 && IsochResourceData^0==IsochResourceData^post_50 && ResourceIrp^0==ResourceIrp^post_50 && StackSize^0==StackSize^post_50 && __rho_10_^0==__rho_10_^post_50 && __rho_11_^0==__rho_11_^post_50 && __rho_1_^0==__rho_1_^post_50 && __rho_2_^0==__rho_2_^post_50 && __rho_3_^0==__rho_3_^post_50 && __rho_4_^0==__rho_4_^post_50 && __rho_5_^0==__rho_5_^post_50 && __rho_666_^0==__rho_666_^post_50 && __rho_7_^0==__rho_7_^post_50 && __rho_8_^0==__rho_8_^post_50 && __rho_9_^0==__rho_9_^post_50 && a11^0==a11^post_50 && a1818^0==a1818^post_50 && a2525^0==a2525^post_50 && a2828^0==a2828^post_50 && a3131^0==a3131^post_50 && a3232^0==a3232^post_50 && a3434^0==a3434^post_50 && a3737^0==a3737^post_50 && a3838^0==a3838^post_50 && a4343^0==a4343^post_50 && a4545^0==a4545^post_50 && a77^0==a77^post_50 && b22^0==b22^post_50 && b2626^0==b2626^post_50 && b2929^0==b2929^post_50 && b3333^0==b3333^post_50 && b3535^0==b3535^post_50 && i^0==i^post_50 && i___01313^0==i___01313^post_50 && i___01717^0==i___01717^post_50 && i___02020^0==i___02020^post_50 && i___02424^0==i___02424^post_50 && i___04747^0==i___04747^post_50 && i___099^0==i___099^post_50 && ioA^0==ioA^post_50 && ioR^0==ioR^post_50 && k1^0==k1^post_50 && k2^0==k2^post_50 && k3^0==k3^post_50 && k4^0==k4^post_50 && ntStatus^0==ntStatus^post_50 && pIrb^0==pIrb^post_50 && phi_io_compl^0==phi_io_compl^post_50 && phi_nSUC_ret^0==phi_nSUC_ret^post_50 && prevCancel^0==prevCancel^post_50 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_50 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_50 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_50 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_50 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_50 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_50 ], cost: 2
     67: l1 -> l32 : AsyncAddressData^0'=AsyncAddressData^post_51, BusResetIrp^0'=BusResetIrp^post_51, CromData^0'=CromData^post_51, DeviceObject^0'=DeviceObject^post_51, Irp^0'=Irp^post_51, Irql^0'=Irql^post_51, IsochDetachData^0'=IsochDetachData^post_51, IsochResourceData^0'=IsochResourceData^post_51, ResourceIrp^0'=ResourceIrp^post_51, StackSize^0'=StackSize^post_51, __rho_10_^0'=__rho_10_^post_51, __rho_11_^0'=__rho_11_^post_51, __rho_12_^0'=__rho_12_^post_51, __rho_1_^0'=__rho_1_^post_51, __rho_2_^0'=__rho_2_^post_51, __rho_3_^0'=__rho_3_^post_51, __rho_4_^0'=__rho_4_^post_51, __rho_5_^0'=__rho_5_^post_51, __rho_666_^0'=__rho_666_^post_51, __rho_7_^0'=__rho_7_^post_51, __rho_8_^0'=__rho_8_^post_51, __rho_9_^0'=__rho_9_^post_51, a11^0'=a11^post_51, a1818^0'=a1818^post_51, a2525^0'=a2525^post_51, a2828^0'=a2828^post_51, a3131^0'=a3131^post_51, a3232^0'=a3232^post_51, a3434^0'=a3434^post_51, a3737^0'=a3737^post_51, a3838^0'=a3838^post_51, a4343^0'=a4343^post_51, a4545^0'=a4545^post_51, a77^0'=a77^post_51, b22^0'=b22^post_51, b2626^0'=b2626^post_51, b2929^0'=b2929^post_51, b3333^0'=b3333^post_51, b3535^0'=b3535^post_51, i^0'=i^post_51, i___01313^0'=i___01313^post_51, i___01717^0'=i___01717^post_51, i___02020^0'=i___02020^post_51, i___02424^0'=i___02424^post_51, i___04040^0'=i___04040^post_51, i___04747^0'=i___04747^post_51, i___099^0'=i___099^post_51, ioA^0'=ioA^post_51, ioR^0'=ioR^post_51, k1^0'=k1^post_51, k2^0'=k2^post_51, k3^0'=k3^post_51, k4^0'=k4^post_51, k5^0'=k5^post_51, keA^0'=keA^post_51, keR^0'=keR^post_51, ntStatus^0'=ntStatus^post_51, pIrb^0'=pIrb^post_51, phi_io_compl^0'=phi_io_compl^post_51, phi_nSUC_ret^0'=phi_nSUC_ret^post_51, prevCancel^0'=prevCancel^post_51, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_51, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_51, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_51, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_51, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_51, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_51, [ 1<=k4^0 && k4^post_51==-1+k4^0 && i___02424^post_51==Irql^0 && keR^1_4_2==1 && keR^post_51==0 && AsyncAddressData^0==AsyncAddressData^post_51 && BusResetIrp^0==BusResetIrp^post_51 && CromData^0==CromData^post_51 && DeviceObject^0==DeviceObject^post_51 && Irp^0==Irp^post_51 && Irql^0==Irql^post_51 && IsochDetachData^0==IsochDetachData^post_51 && ResourceIrp^0==ResourceIrp^post_51 && StackSize^0==StackSize^post_51 && __rho_10_^0==__rho_10_^post_51 && __rho_11_^0==__rho_11_^post_51 && __rho_12_^0==__rho_12_^post_51 && __rho_1_^0==__rho_1_^post_51 && __rho_2_^0==__rho_2_^post_51 && __rho_3_^0==__rho_3_^post_51 && __rho_4_^0==__rho_4_^post_51 && __rho_5_^0==__rho_5_^post_51 && __rho_666_^0==__rho_666_^post_51 && __rho_7_^0==__rho_7_^post_51 && __rho_8_^0==__rho_8_^post_51 && __rho_9_^0==__rho_9_^post_51 && a11^0==a11^post_51 && a1818^0==a1818^post_51 && a2525^0==a2525^post_51 && a2828^0==a2828^post_51 && a3131^0==a3131^post_51 && a3232^0==a3232^post_51 && a3434^0==a3434^post_51 && a3737^0==a3737^post_51 && a3838^0==a3838^post_51 && a4343^0==a4343^post_51 && a4545^0==a4545^post_51 && a77^0==a77^post_51 && b22^0==b22^post_51 && b2626^0==b2626^post_51 && b2929^0==b2929^post_51 && b3333^0==b3333^post_51 && b3535^0==b3535^post_51 && i^0==i^post_51 && i___01313^0==i___01313^post_51 && i___01717^0==i___01717^post_51 && i___02020^0==i___02020^post_51 && i___04040^0==i___04040^post_51 && i___04747^0==i___04747^post_51 && i___099^0==i___099^post_51 && ioA^0==ioA^post_51 && ioR^0==ioR^post_51 && k1^0==k1^post_51 && k2^0==k2^post_51 && k3^0==k3^post_51 && k5^0==k5^post_51 && 0==keA^post_51 && ntStatus^0==ntStatus^post_51 && pIrb^0==pIrb^post_51 && phi_io_compl^0==phi_io_compl^post_51 && phi_nSUC_ret^0==phi_nSUC_ret^post_51 && prevCancel^0==prevCancel^post_51 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_51 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_51 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_51 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_51 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_51 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_51 ], cost: 2
     95: l1 -> l19 : BusResetIrp^0'=BusResetIrp^post_38, __rho_12_^0'=k5^post_50, a4343^0'=0, a4545^0'=BusResetIrp^post_38, i___04040^0'=Irql^0, k5^0'=0, keA^0'=0, keR^0'=0, phi_io_compl^0'=1, prevCancel^0'=0, ret_IoSetCancelRoutine4444^0'=0, [ k4^0<=0 && k5^post_50>=1 ], cost: 2+2*k5^post_50
     64: l2 -> l1 : __rho_11_^0'=__rho_11_^post_1, i___02020^0'=Irql^0, k4^0'=__rho_11_^post_1, keA^0'=0, keR^0'=0, [ k3^0<=0 ], cost: 2
     63: l4 -> l2 : __rho_10_^0'=__rho_10_^post_15, i___01313^0'=Irql^0, k3^0'=__rho_10_^post_15, keR^0'=0, [ k2^0<=0 ], cost: 2
     94: l4 -> l2 : IsochDetachData^0'=IsochDetachData^post_2, __rho_10_^0'=__rho_10_^post_15, a1818^0'=IsochDetachData^post_2, i^0'=i^post_2, i___01313^0'=Irql^0, i___01717^0'=Irql^0, k3^0'=0, keA^0'=0, keR^0'=0, [ k2^0<=0 && __rho_10_^post_15>=1 ], cost: 2+2*__rho_10_^post_15
     60: l10 -> l18 : CromData^0'=CromData^post_27, k1^0'=-1+k1^0, [ 1<=k1^0 ], cost: 2
     61: l10 -> l4 : __rho_4_^0'=__rho_4_^post_28, i___099^0'=Irql^0, k2^0'=__rho_4_^post_28, keA^0'=0, keR^0'=0, [ k1^0<=0 ], cost: 2
    102: l10 -> l4 : AsyncAddressData^0'=AsyncAddressData^post_14, __rho_4_^0'=__rho_4_^post_28, __rho_7_^0'=__rho_7_^post_14, __rho_8_^0'=__rho_8_^post_10, __rho_9_^0'=__rho_9_^post_7, i___099^0'=Irql^0, k2^0'=0, keA^0'=0, keR^0'=0, [ k1^0<=0 && __rho_4_^post_28>=1 ], cost: 2+8*__rho_4_^post_28
     24: l18 -> l10 : [ CromData^0<=0 ], cost: 1
    100: l18 -> l10 : __rho_2_^0'=__rho_2_^post_26, __rho_3_^0'=__rho_3_^post_21, a77^0'=CromData^0, [ 1<=CromData^0 ], cost: 5
     69: l19 -> l26 : i___04747^0'=Irql^0, keR^0'=0, [ k5^0<=0 ], cost: 2
     29: l21 -> l10 : __rho_5_^0'=__rho_5_^post_30, k1^0'=__rho_5_^post_30, keA^0'=0, ntStatus^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, [], cost: 1
     57: l26 -> [35] : [ -2+ntStatus^0==0 ], cost: NONTERM
     70: l26 -> [35] : [ 3<=ntStatus^0 ], cost: NONTERM
     71: l26 -> [35] : [ 1+ntStatus^0<=2 ], cost: NONTERM
     47: l32 -> l1 : [ IsochResourceData^0<=0 ], cost: 1
     72: l32 -> l1 : ResourceIrp^0'=0, StackSize^0'=a2525^post_49, a2525^0'=a2525^post_49, b2626^0'=0, pIrb^0'=pIrb^post_49, ret_IoAllocateIrp2727^0'=0, [ 1<=IsochResourceData^0 ], cost: 2
     58: l34 -> l21 : AsyncAddressData^0'=AsyncAddressData^post_52, BusResetIrp^0'=BusResetIrp^post_52, CromData^0'=CromData^post_52, DeviceObject^0'=DeviceObject^post_52, Irp^0'=Irp^post_52, Irql^0'=Irql^post_52, IsochDetachData^0'=IsochDetachData^post_52, IsochResourceData^0'=IsochResourceData^post_52, ResourceIrp^0'=ResourceIrp^post_52, StackSize^0'=StackSize^post_52, __rho_10_^0'=__rho_10_^post_52, __rho_11_^0'=__rho_11_^post_52, __rho_12_^0'=__rho_12_^post_52, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_52, __rho_3_^0'=__rho_3_^post_52, __rho_4_^0'=__rho_4_^post_52, __rho_5_^0'=__rho_5_^post_52, __rho_666_^0'=__rho_666_^post_52, __rho_7_^0'=__rho_7_^post_52, __rho_8_^0'=__rho_8_^post_52, __rho_9_^0'=__rho_9_^post_52, a11^0'=a11^post_52, a1818^0'=a1818^post_52, a2525^0'=a2525^post_52, a2828^0'=a2828^post_52, a3131^0'=a3131^post_52, a3232^0'=a3232^post_52, a3434^0'=a3434^post_52, a3737^0'=a3737^post_52, a3838^0'=a3838^post_52, a4343^0'=a4343^post_52, a4545^0'=a4545^post_52, a77^0'=a77^post_52, b22^0'=b22^post_52, b2626^0'=b2626^post_52, b2929^0'=b2929^post_52, b3333^0'=b3333^post_52, b3535^0'=b3535^post_52, i^0'=i^post_52, i___01313^0'=i___01313^post_52, i___01717^0'=i___01717^post_52, i___02020^0'=i___02020^post_52, i___02424^0'=i___02424^post_52, i___04040^0'=i___04040^post_52, i___04747^0'=i___04747^post_52, i___099^0'=i___099^post_52, ioA^0'=ioA^post_52, ioR^0'=ioR^post_52, k1^0'=k1^post_52, k2^0'=k2^post_52, k3^0'=k3^post_52, k4^0'=k4^post_52, k5^0'=k5^post_52, keA^0'=keA^post_52, keR^0'=keR^post_52, ntStatus^0'=ntStatus^post_52, pIrb^0'=pIrb^post_52, phi_io_compl^0'=phi_io_compl^post_52, phi_nSUC_ret^0'=phi_nSUC_ret^post_52, prevCancel^0'=prevCancel^post_52, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_52, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_52, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_52, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_52, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_52, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_52, [ AsyncAddressData^0==AsyncAddressData^post_53 && BusResetIrp^0==BusResetIrp^post_53 && CromData^0==CromData^post_53 && DeviceObject^0==DeviceObject^post_53 && Irp^0==Irp^post_53 && Irql^0==Irql^post_53 && IsochDetachData^0==IsochDetachData^post_53 && IsochResourceData^0==IsochResourceData^post_53 && ResourceIrp^0==ResourceIrp^post_53 && StackSize^0==StackSize^post_53 && __rho_10_^0==__rho_10_^post_53 && __rho_11_^0==__rho_11_^post_53 && __rho_12_^0==__rho_12_^post_53 && __rho_1_^0==__rho_1_^post_53 && __rho_2_^0==__rho_2_^post_53 && __rho_3_^0==__rho_3_^post_53 && __rho_4_^0==__rho_4_^post_53 && __rho_5_^0==__rho_5_^post_53 && __rho_666_^0==__rho_666_^post_53 && __rho_7_^0==__rho_7_^post_53 && __rho_8_^0==__rho_8_^post_53 && __rho_9_^0==__rho_9_^post_53 && a11^0==a11^post_53 && a1818^0==a1818^post_53 && a2525^0==a2525^post_53 && a2828^0==a2828^post_53 && a3131^0==a3131^post_53 && a3232^0==a3232^post_53 && a3434^0==a3434^post_53 && a3737^0==a3737^post_53 && a3838^0==a3838^post_53 && a4343^0==a4343^post_53 && a4545^0==a4545^post_53 && a77^0==a77^post_53 && b22^0==b22^post_53 && b2626^0==b2626^post_53 && b2929^0==b2929^post_53 && b3333^0==b3333^post_53 && b3535^0==b3535^post_53 && i^0==i^post_53 && i___01313^0==i___01313^post_53 && i___01717^0==i___01717^post_53 && i___02020^0==i___02020^post_53 && i___02424^0==i___02424^post_53 && i___04040^0==i___04040^post_53 && i___04747^0==i___04747^post_53 && i___099^0==i___099^post_53 && ioA^0==ioA^post_53 && ioR^0==ioR^post_53 && k1^0==k1^post_53 && k2^0==k2^post_53 && k3^0==k3^post_53 && k4^0==k4^post_53 && k5^0==k5^post_53 && keA^0==keA^post_53 && keR^0==keR^post_53 && ntStatus^0==ntStatus^post_53 && pIrb^0==pIrb^post_53 && phi_io_compl^0==phi_io_compl^post_53 && phi_nSUC_ret^0==phi_nSUC_ret^post_53 && prevCancel^0==prevCancel^post_53 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_53 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_53 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_53 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_53 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_53 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_53 && ioR^post_52==0 && ioA^post_52==ioR^post_52 && keR^post_52==ioA^post_52 && keA^post_52==keR^post_52 && phi_nSUC_ret^post_52==0 && phi_io_compl^post_52==0 && AsyncAddressData^post_53==AsyncAddressData^post_52 && BusResetIrp^post_53==BusResetIrp^post_52 && CromData^post_53==CromData^post_52 && DeviceObject^post_53==DeviceObject^post_52 && Irp^post_53==Irp^post_52 && Irql^post_53==Irql^post_52 && IsochDetachData^post_53==IsochDetachData^post_52 && IsochResourceData^post_53==IsochResourceData^post_52 && ResourceIrp^post_53==ResourceIrp^post_52 && StackSize^post_53==StackSize^post_52 && __rho_10_^post_53==__rho_10_^post_52 && __rho_11_^post_53==__rho_11_^post_52 && __rho_12_^post_53==__rho_12_^post_52 && __rho_2_^post_53==__rho_2_^post_52 && __rho_3_^post_53==__rho_3_^post_52 && __rho_4_^post_53==__rho_4_^post_52 && __rho_5_^post_53==__rho_5_^post_52 && __rho_7_^post_53==__rho_7_^post_52 && __rho_8_^post_53==__rho_8_^post_52 && __rho_9_^post_53==__rho_9_^post_52 && a11^post_53==a11^post_52 && a1818^post_53==a1818^post_52 && a2525^post_53==a2525^post_52 && a2828^post_53==a2828^post_52 && a3131^post_53==a3131^post_52 && a3232^post_53==a3232^post_52 && a3434^post_53==a3434^post_52 && a3737^post_53==a3737^post_52 && a3838^post_53==a3838^post_52 && a4343^post_53==a4343^post_52 && a4545^post_53==a4545^post_52 && a77^post_53==a77^post_52 && b22^post_53==b22^post_52 && b2626^post_53==b2626^post_52 && b2929^post_53==b2929^post_52 && b3333^post_53==b3333^post_52 && b3535^post_53==b3535^post_52 && i^post_53==i^post_52 && i___01313^post_53==i___01313^post_52 && i___01717^post_53==i___01717^post_52 && i___02020^post_53==i___02020^post_52 && i___02424^post_53==i___02424^post_52 && i___04040^post_53==i___04040^post_52 && i___04747^post_53==i___04747^post_52 && i___099^post_53==i___099^post_52 && k1^post_53==k1^post_52 && k2^post_53==k2^post_52 && k3^post_53==k3^post_52 && k4^post_53==k4^post_52 && k5^post_53==k5^post_52 && ntStatus^post_53==ntStatus^post_52 && pIrb^post_53==pIrb^post_52 && prevCancel^post_53==prevCancel^post_52 && ret_ExAllocatePool3030^post_53==ret_ExAllocatePool3030^post_52 && ret_IoAllocateIrp2727^post_53==ret_IoAllocateIrp2727^post_52 && ret_IoSetCancelRoutine4444^post_53==ret_IoSetCancelRoutine4444^post_52 && ret_IoSetDeviceInterfaceState44^post_53==ret_IoSetDeviceInterfaceState44^post_52 && ret_t1394Diag_PnpStopDevice33^post_53==ret_t1394Diag_PnpStopDevice33^post_52 && ret_t1394_SubmitIrpSynch3636^post_53==ret_t1394_SubmitIrpSynch3636^post_52 && __rho_1_^post_52<=0 ], cost: 3
     59: l34 -> l21 : AsyncAddressData^0'=AsyncAddressData^post_52, BusResetIrp^0'=BusResetIrp^post_52, CromData^0'=CromData^post_52, DeviceObject^0'=DeviceObject^post_52, Irp^0'=Irp^post_52, Irql^0'=Irql^post_52, IsochDetachData^0'=IsochDetachData^post_52, IsochResourceData^0'=IsochResourceData^post_52, ResourceIrp^0'=ResourceIrp^post_52, StackSize^0'=StackSize^post_52, __rho_10_^0'=__rho_10_^post_52, __rho_11_^0'=__rho_11_^post_52, __rho_12_^0'=__rho_12_^post_52, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_52, __rho_3_^0'=__rho_3_^post_52, __rho_4_^0'=__rho_4_^post_52, __rho_5_^0'=__rho_5_^post_52, __rho_666_^0'=__rho_666_^post_52, __rho_7_^0'=__rho_7_^post_52, __rho_8_^0'=__rho_8_^post_52, __rho_9_^0'=__rho_9_^post_52, a11^0'=DeviceObject^post_52, a1818^0'=a1818^post_52, a2525^0'=a2525^post_52, a2828^0'=a2828^post_52, a3131^0'=a3131^post_52, a3232^0'=a3232^post_52, a3434^0'=a3434^post_52, a3737^0'=a3737^post_52, a3838^0'=a3838^post_52, a4343^0'=a4343^post_52, a4545^0'=a4545^post_52, a77^0'=a77^post_52, b22^0'=Irp^post_52, b2626^0'=b2626^post_52, b2929^0'=b2929^post_52, b3333^0'=b3333^post_52, b3535^0'=b3535^post_52, i^0'=i^post_52, i___01313^0'=i___01313^post_52, i___01717^0'=i___01717^post_52, i___02020^0'=i___02020^post_52, i___02424^0'=i___02424^post_52, i___04040^0'=i___04040^post_52, i___04747^0'=i___04747^post_52, i___099^0'=i___099^post_52, ioA^0'=ioA^post_52, ioR^0'=ioR^post_52, k1^0'=k1^post_52, k2^0'=k2^post_52, k3^0'=k3^post_52, k4^0'=k4^post_52, k5^0'=k5^post_52, keA^0'=keA^post_52, keR^0'=keR^post_52, ntStatus^0'=0, pIrb^0'=pIrb^post_52, phi_io_compl^0'=phi_io_compl^post_52, phi_nSUC_ret^0'=phi_nSUC_ret^post_52, prevCancel^0'=prevCancel^post_52, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_52, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_52, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_52, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_52, ret_t1394Diag_PnpStopDevice33^0'=0, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_52, [ AsyncAddressData^0==AsyncAddressData^post_53 && BusResetIrp^0==BusResetIrp^post_53 && CromData^0==CromData^post_53 && DeviceObject^0==DeviceObject^post_53 && Irp^0==Irp^post_53 && Irql^0==Irql^post_53 && IsochDetachData^0==IsochDetachData^post_53 && IsochResourceData^0==IsochResourceData^post_53 && ResourceIrp^0==ResourceIrp^post_53 && StackSize^0==StackSize^post_53 && __rho_10_^0==__rho_10_^post_53 && __rho_11_^0==__rho_11_^post_53 && __rho_12_^0==__rho_12_^post_53 && __rho_1_^0==__rho_1_^post_53 && __rho_2_^0==__rho_2_^post_53 && __rho_3_^0==__rho_3_^post_53 && __rho_4_^0==__rho_4_^post_53 && __rho_5_^0==__rho_5_^post_53 && __rho_666_^0==__rho_666_^post_53 && __rho_7_^0==__rho_7_^post_53 && __rho_8_^0==__rho_8_^post_53 && __rho_9_^0==__rho_9_^post_53 && a11^0==a11^post_53 && a1818^0==a1818^post_53 && a2525^0==a2525^post_53 && a2828^0==a2828^post_53 && a3131^0==a3131^post_53 && a3232^0==a3232^post_53 && a3434^0==a3434^post_53 && a3737^0==a3737^post_53 && a3838^0==a3838^post_53 && a4343^0==a4343^post_53 && a4545^0==a4545^post_53 && a77^0==a77^post_53 && b22^0==b22^post_53 && b2626^0==b2626^post_53 && b2929^0==b2929^post_53 && b3333^0==b3333^post_53 && b3535^0==b3535^post_53 && i^0==i^post_53 && i___01313^0==i___01313^post_53 && i___01717^0==i___01717^post_53 && i___02020^0==i___02020^post_53 && i___02424^0==i___02424^post_53 && i___04040^0==i___04040^post_53 && i___04747^0==i___04747^post_53 && i___099^0==i___099^post_53 && ioA^0==ioA^post_53 && ioR^0==ioR^post_53 && k1^0==k1^post_53 && k2^0==k2^post_53 && k3^0==k3^post_53 && k4^0==k4^post_53 && k5^0==k5^post_53 && keA^0==keA^post_53 && keR^0==keR^post_53 && ntStatus^0==ntStatus^post_53 && pIrb^0==pIrb^post_53 && phi_io_compl^0==phi_io_compl^post_53 && phi_nSUC_ret^0==phi_nSUC_ret^post_53 && prevCancel^0==prevCancel^post_53 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_53 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_53 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_53 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_53 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_53 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_53 && ioR^post_52==0 && ioA^post_52==ioR^post_52 && keR^post_52==ioA^post_52 && keA^post_52==keR^post_52 && phi_nSUC_ret^post_52==0 && phi_io_compl^post_52==0 && AsyncAddressData^post_53==AsyncAddressData^post_52 && BusResetIrp^post_53==BusResetIrp^post_52 && CromData^post_53==CromData^post_52 && DeviceObject^post_53==DeviceObject^post_52 && Irp^post_53==Irp^post_52 && Irql^post_53==Irql^post_52 && IsochDetachData^post_53==IsochDetachData^post_52 && IsochResourceData^post_53==IsochResourceData^post_52 && ResourceIrp^post_53==ResourceIrp^post_52 && StackSize^post_53==StackSize^post_52 && __rho_10_^post_53==__rho_10_^post_52 && __rho_11_^post_53==__rho_11_^post_52 && __rho_12_^post_53==__rho_12_^post_52 && __rho_2_^post_53==__rho_2_^post_52 && __rho_3_^post_53==__rho_3_^post_52 && __rho_4_^post_53==__rho_4_^post_52 && __rho_5_^post_53==__rho_5_^post_52 && __rho_7_^post_53==__rho_7_^post_52 && __rho_8_^post_53==__rho_8_^post_52 && __rho_9_^post_53==__rho_9_^post_52 && a11^post_53==a11^post_52 && a1818^post_53==a1818^post_52 && a2525^post_53==a2525^post_52 && a2828^post_53==a2828^post_52 && a3131^post_53==a3131^post_52 && a3232^post_53==a3232^post_52 && a3434^post_53==a3434^post_52 && a3737^post_53==a3737^post_52 && a3838^post_53==a3838^post_52 && a4343^post_53==a4343^post_52 && a4545^post_53==a4545^post_52 && a77^post_53==a77^post_52 && b22^post_53==b22^post_52 && b2626^post_53==b2626^post_52 && b2929^post_53==b2929^post_52 && b3333^post_53==b3333^post_52 && b3535^post_53==b3535^post_52 && i^post_53==i^post_52 && i___01313^post_53==i___01313^post_52 && i___01717^post_53==i___01717^post_52 && i___02020^post_53==i___02020^post_52 && i___02424^post_53==i___02424^post_52 && i___04040^post_53==i___04040^post_52 && i___04747^post_53==i___04747^post_52 && i___099^post_53==i___099^post_52 && k1^post_53==k1^post_52 && k2^post_53==k2^post_52 && k3^post_53==k3^post_52 && k4^post_53==k4^post_52 && k5^post_53==k5^post_52 && ntStatus^post_53==ntStatus^post_52 && pIrb^post_53==pIrb^post_52 && prevCancel^post_53==prevCancel^post_52 && ret_ExAllocatePool3030^post_53==ret_ExAllocatePool3030^post_52 && ret_IoAllocateIrp2727^post_53==ret_IoAllocateIrp2727^post_52 && ret_IoSetCancelRoutine4444^post_53==ret_IoSetCancelRoutine4444^post_52 && ret_IoSetDeviceInterfaceState44^post_53==ret_IoSetDeviceInterfaceState44^post_52 && ret_t1394Diag_PnpStopDevice33^post_53==ret_t1394Diag_PnpStopDevice33^post_52 && ret_t1394_SubmitIrpSynch3636^post_53==ret_t1394_SubmitIrpSynch3636^post_52 && 1<=__rho_1_^post_52 ], cost: 3

Eliminated locations (on tree-shaped paths):
   Start location: l34
    111: l1 -> l26 : AsyncAddressData^0'=AsyncAddressData^post_50, BusResetIrp^0'=BusResetIrp^post_50, CromData^0'=CromData^post_50, DeviceObject^0'=DeviceObject^post_50, Irp^0'=Irp^post_50, Irql^0'=Irql^post_50, IsochDetachData^0'=IsochDetachData^post_50, IsochResourceData^0'=IsochResourceData^post_50, ResourceIrp^0'=ResourceIrp^post_50, StackSize^0'=StackSize^post_50, __rho_10_^0'=__rho_10_^post_50, __rho_11_^0'=__rho_11_^post_50, __rho_12_^0'=__rho_12_^post_50, __rho_1_^0'=__rho_1_^post_50, __rho_2_^0'=__rho_2_^post_50, __rho_3_^0'=__rho_3_^post_50, __rho_4_^0'=__rho_4_^post_50, __rho_5_^0'=__rho_5_^post_50, __rho_666_^0'=__rho_666_^post_50, __rho_7_^0'=__rho_7_^post_50, __rho_8_^0'=__rho_8_^post_50, __rho_9_^0'=__rho_9_^post_50, a11^0'=a11^post_50, a1818^0'=a1818^post_50, a2525^0'=a2525^post_50, a2828^0'=a2828^post_50, a3131^0'=a3131^post_50, a3232^0'=a3232^post_50, a3434^0'=a3434^post_50, a3737^0'=a3737^post_50, a3838^0'=a3838^post_50, a4343^0'=a4343^post_50, a4545^0'=a4545^post_50, a77^0'=a77^post_50, b22^0'=b22^post_50, b2626^0'=b2626^post_50, b2929^0'=b2929^post_50, b3333^0'=b3333^post_50, b3535^0'=b3535^post_50, i^0'=i^post_50, i___01313^0'=i___01313^post_50, i___01717^0'=i___01717^post_50, i___02020^0'=i___02020^post_50, i___02424^0'=i___02424^post_50, i___04040^0'=i___04040^post_50, i___04747^0'=Irql^post_50, i___099^0'=i___099^post_50, ioA^0'=ioA^post_50, ioR^0'=ioR^post_50, k1^0'=k1^post_50, k2^0'=k2^post_50, k3^0'=k3^post_50, k4^0'=k4^post_50, k5^0'=k5^post_50, keA^0'=keA^post_50, keR^0'=0, ntStatus^0'=ntStatus^post_50, pIrb^0'=pIrb^post_50, phi_io_compl^0'=phi_io_compl^post_50, phi_nSUC_ret^0'=phi_nSUC_ret^post_50, prevCancel^0'=prevCancel^post_50, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_50, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_50, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_50, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_50, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_50, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_50, [ k4^0<=0 && i___04040^post_50==Irql^0 && keR^1_4_1==1 && keR^post_50==0 && keA^1_5==1 && keA^post_50==0 && k5^post_50==__rho_12_^post_50 && AsyncAddressData^0==AsyncAddressData^post_50 && BusResetIrp^0==BusResetIrp^post_50 && CromData^0==CromData^post_50 && DeviceObject^0==DeviceObject^post_50 && Irp^0==Irp^post_50 && Irql^0==Irql^post_50 && IsochDetachData^0==IsochDetachData^post_50 && IsochResourceData^0==IsochResourceData^post_50 && ResourceIrp^0==ResourceIrp^post_50 && StackSize^0==StackSize^post_50 && __rho_10_^0==__rho_10_^post_50 && __rho_11_^0==__rho_11_^post_50 && __rho_1_^0==__rho_1_^post_50 && __rho_2_^0==__rho_2_^post_50 && __rho_3_^0==__rho_3_^post_50 && __rho_4_^0==__rho_4_^post_50 && __rho_5_^0==__rho_5_^post_50 && __rho_666_^0==__rho_666_^post_50 && __rho_7_^0==__rho_7_^post_50 && __rho_8_^0==__rho_8_^post_50 && __rho_9_^0==__rho_9_^post_50 && a11^0==a11^post_50 && a1818^0==a1818^post_50 && a2525^0==a2525^post_50 && a2828^0==a2828^post_50 && a3131^0==a3131^post_50 && a3232^0==a3232^post_50 && a3434^0==a3434^post_50 && a3737^0==a3737^post_50 && a3838^0==a3838^post_50 && a4343^0==a4343^post_50 && a4545^0==a4545^post_50 && a77^0==a77^post_50 && b22^0==b22^post_50 && b2626^0==b2626^post_50 && b2929^0==b2929^post_50 && b3333^0==b3333^post_50 && b3535^0==b3535^post_50 && i^0==i^post_50 && i___01313^0==i___01313^post_50 && i___01717^0==i___01717^post_50 && i___02020^0==i___02020^post_50 && i___02424^0==i___02424^post_50 && i___04747^0==i___04747^post_50 && i___099^0==i___099^post_50 && ioA^0==ioA^post_50 && ioR^0==ioR^post_50 && k1^0==k1^post_50 && k2^0==k2^post_50 && k3^0==k3^post_50 && k4^0==k4^post_50 && ntStatus^0==ntStatus^post_50 && pIrb^0==pIrb^post_50 && phi_io_compl^0==phi_io_compl^post_50 && phi_nSUC_ret^0==phi_nSUC_ret^post_50 && prevCancel^0==prevCancel^post_50 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_50 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_50 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_50 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_50 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_50 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_50 && k5^post_50<=0 ], cost: 4
    112: l1 -> l26 : BusResetIrp^0'=BusResetIrp^post_38, __rho_12_^0'=k5^post_50, a4343^0'=0, a4545^0'=BusResetIrp^post_38, i___04040^0'=Irql^0, i___04747^0'=Irql^0, k5^0'=0, keA^0'=0, keR^0'=0, phi_io_compl^0'=1, prevCancel^0'=0, ret_IoSetCancelRoutine4444^0'=0, [ k4^0<=0 && k5^post_50>=1 ], cost: 4+2*k5^post_50
    113: l1 -> l1 : AsyncAddressData^0'=AsyncAddressData^post_51, BusResetIrp^0'=BusResetIrp^post_51, CromData^0'=CromData^post_51, DeviceObject^0'=DeviceObject^post_51, Irp^0'=Irp^post_51, Irql^0'=Irql^post_51, IsochDetachData^0'=IsochDetachData^post_51, IsochResourceData^0'=IsochResourceData^post_51, ResourceIrp^0'=ResourceIrp^post_51, StackSize^0'=StackSize^post_51, __rho_10_^0'=__rho_10_^post_51, __rho_11_^0'=__rho_11_^post_51, __rho_12_^0'=__rho_12_^post_51, __rho_1_^0'=__rho_1_^post_51, __rho_2_^0'=__rho_2_^post_51, __rho_3_^0'=__rho_3_^post_51, __rho_4_^0'=__rho_4_^post_51, __rho_5_^0'=__rho_5_^post_51, __rho_666_^0'=__rho_666_^post_51, __rho_7_^0'=__rho_7_^post_51, __rho_8_^0'=__rho_8_^post_51, __rho_9_^0'=__rho_9_^post_51, a11^0'=a11^post_51, a1818^0'=a1818^post_51, a2525^0'=a2525^post_51, a2828^0'=a2828^post_51, a3131^0'=a3131^post_51, a3232^0'=a3232^post_51, a3434^0'=a3434^post_51, a3737^0'=a3737^post_51, a3838^0'=a3838^post_51, a4343^0'=a4343^post_51, a4545^0'=a4545^post_51, a77^0'=a77^post_51, b22^0'=b22^post_51, b2626^0'=b2626^post_51, b2929^0'=b2929^post_51, b3333^0'=b3333^post_51, b3535^0'=b3535^post_51, i^0'=i^post_51, i___01313^0'=i___01313^post_51, i___01717^0'=i___01717^post_51, i___02020^0'=i___02020^post_51, i___02424^0'=i___02424^post_51, i___04040^0'=i___04040^post_51, i___04747^0'=i___04747^post_51, i___099^0'=i___099^post_51, ioA^0'=ioA^post_51, ioR^0'=ioR^post_51, k1^0'=k1^post_51, k2^0'=k2^post_51, k3^0'=k3^post_51, k4^0'=k4^post_51, k5^0'=k5^post_51, keA^0'=keA^post_51, keR^0'=keR^post_51, ntStatus^0'=ntStatus^post_51, pIrb^0'=pIrb^post_51, phi_io_compl^0'=phi_io_compl^post_51, phi_nSUC_ret^0'=phi_nSUC_ret^post_51, prevCancel^0'=prevCancel^post_51, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_51, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_51, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_51, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_51, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_51, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_51, [ 1<=k4^0 && k4^post_51==-1+k4^0 && i___02424^post_51==Irql^0 && keR^1_4_2==1 && keR^post_51==0 && AsyncAddressData^0==AsyncAddressData^post_51 && BusResetIrp^0==BusResetIrp^post_51 && CromData^0==CromData^post_51 && DeviceObject^0==DeviceObject^post_51 && Irp^0==Irp^post_51 && Irql^0==Irql^post_51 && IsochDetachData^0==IsochDetachData^post_51 && ResourceIrp^0==ResourceIrp^post_51 && StackSize^0==StackSize^post_51 && __rho_10_^0==__rho_10_^post_51 && __rho_11_^0==__rho_11_^post_51 && __rho_12_^0==__rho_12_^post_51 && __rho_1_^0==__rho_1_^post_51 && __rho_2_^0==__rho_2_^post_51 && __rho_3_^0==__rho_3_^post_51 && __rho_4_^0==__rho_4_^post_51 && __rho_5_^0==__rho_5_^post_51 && __rho_666_^0==__rho_666_^post_51 && __rho_7_^0==__rho_7_^post_51 && __rho_8_^0==__rho_8_^post_51 && __rho_9_^0==__rho_9_^post_51 && a11^0==a11^post_51 && a1818^0==a1818^post_51 && a2525^0==a2525^post_51 && a2828^0==a2828^post_51 && a3131^0==a3131^post_51 && a3232^0==a3232^post_51 && a3434^0==a3434^post_51 && a3737^0==a3737^post_51 && a3838^0==a3838^post_51 && a4343^0==a4343^post_51 && a4545^0==a4545^post_51 && a77^0==a77^post_51 && b22^0==b22^post_51 && b2626^0==b2626^post_51 && b2929^0==b2929^post_51 && b3333^0==b3333^post_51 && b3535^0==b3535^post_51 && i^0==i^post_51 && i___01313^0==i___01313^post_51 && i___01717^0==i___01717^post_51 && i___02020^0==i___02020^post_51 && i___04040^0==i___04040^post_51 && i___04747^0==i___04747^post_51 && i___099^0==i___099^post_51 && ioA^0==ioA^post_51 && ioR^0==ioR^post_51 && k1^0==k1^post_51 && k2^0==k2^post_51 && k3^0==k3^post_51 && k5^0==k5^post_51 && 0==keA^post_51 && ntStatus^0==ntStatus^post_51 && pIrb^0==pIrb^post_51 && phi_io_compl^0==phi_io_compl^post_51 && phi_nSUC_ret^0==phi_nSUC_ret^post_51 && prevCancel^0==prevCancel^post_51 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_51 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_51 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_51 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_51 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_51 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_51 && IsochResourceData^post_51<=0 ], cost: 3
    114: l1 -> l1 : AsyncAddressData^0'=AsyncAddressData^post_51, BusResetIrp^0'=BusResetIrp^post_51, CromData^0'=CromData^post_51, DeviceObject^0'=DeviceObject^post_51, Irp^0'=Irp^post_51, Irql^0'=Irql^post_51, IsochDetachData^0'=IsochDetachData^post_51, IsochResourceData^0'=IsochResourceData^post_51, ResourceIrp^0'=0, StackSize^0'=a2525^post_49, __rho_10_^0'=__rho_10_^post_51, __rho_11_^0'=__rho_11_^post_51, __rho_12_^0'=__rho_12_^post_51, __rho_1_^0'=__rho_1_^post_51, __rho_2_^0'=__rho_2_^post_51, __rho_3_^0'=__rho_3_^post_51, __rho_4_^0'=__rho_4_^post_51, __rho_5_^0'=__rho_5_^post_51, __rho_666_^0'=__rho_666_^post_51, __rho_7_^0'=__rho_7_^post_51, __rho_8_^0'=__rho_8_^post_51, __rho_9_^0'=__rho_9_^post_51, a11^0'=a11^post_51, a1818^0'=a1818^post_51, a2525^0'=a2525^post_49, a2828^0'=a2828^post_51, a3131^0'=a3131^post_51, a3232^0'=a3232^post_51, a3434^0'=a3434^post_51, a3737^0'=a3737^post_51, a3838^0'=a3838^post_51, a4343^0'=a4343^post_51, a4545^0'=a4545^post_51, a77^0'=a77^post_51, b22^0'=b22^post_51, b2626^0'=0, b2929^0'=b2929^post_51, b3333^0'=b3333^post_51, b3535^0'=b3535^post_51, i^0'=i^post_51, i___01313^0'=i___01313^post_51, i___01717^0'=i___01717^post_51, i___02020^0'=i___02020^post_51, i___02424^0'=i___02424^post_51, i___04040^0'=i___04040^post_51, i___04747^0'=i___04747^post_51, i___099^0'=i___099^post_51, ioA^0'=ioA^post_51, ioR^0'=ioR^post_51, k1^0'=k1^post_51, k2^0'=k2^post_51, k3^0'=k3^post_51, k4^0'=k4^post_51, k5^0'=k5^post_51, keA^0'=keA^post_51, keR^0'=keR^post_51, ntStatus^0'=ntStatus^post_51, pIrb^0'=pIrb^post_49, phi_io_compl^0'=phi_io_compl^post_51, phi_nSUC_ret^0'=phi_nSUC_ret^post_51, prevCancel^0'=prevCancel^post_51, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_51, ret_IoAllocateIrp2727^0'=0, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_51, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_51, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_51, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_51, [ 1<=k4^0 && k4^post_51==-1+k4^0 && i___02424^post_51==Irql^0 && keR^1_4_2==1 && keR^post_51==0 && AsyncAddressData^0==AsyncAddressData^post_51 && BusResetIrp^0==BusResetIrp^post_51 && CromData^0==CromData^post_51 && DeviceObject^0==DeviceObject^post_51 && Irp^0==Irp^post_51 && Irql^0==Irql^post_51 && IsochDetachData^0==IsochDetachData^post_51 && ResourceIrp^0==ResourceIrp^post_51 && StackSize^0==StackSize^post_51 && __rho_10_^0==__rho_10_^post_51 && __rho_11_^0==__rho_11_^post_51 && __rho_12_^0==__rho_12_^post_51 && __rho_1_^0==__rho_1_^post_51 && __rho_2_^0==__rho_2_^post_51 && __rho_3_^0==__rho_3_^post_51 && __rho_4_^0==__rho_4_^post_51 && __rho_5_^0==__rho_5_^post_51 && __rho_666_^0==__rho_666_^post_51 && __rho_7_^0==__rho_7_^post_51 && __rho_8_^0==__rho_8_^post_51 && __rho_9_^0==__rho_9_^post_51 && a11^0==a11^post_51 && a1818^0==a1818^post_51 && a2525^0==a2525^post_51 && a2828^0==a2828^post_51 && a3131^0==a3131^post_51 && a3232^0==a3232^post_51 && a3434^0==a3434^post_51 && a3737^0==a3737^post_51 && a3838^0==a3838^post_51 && a4343^0==a4343^post_51 && a4545^0==a4545^post_51 && a77^0==a77^post_51 && b22^0==b22^post_51 && b2626^0==b2626^post_51 && b2929^0==b2929^post_51 && b3333^0==b3333^post_51 && b3535^0==b3535^post_51 && i^0==i^post_51 && i___01313^0==i___01313^post_51 && i___01717^0==i___01717^post_51 && i___02020^0==i___02020^post_51 && i___04040^0==i___04040^post_51 && i___04747^0==i___04747^post_51 && i___099^0==i___099^post_51 && ioA^0==ioA^post_51 && ioR^0==ioR^post_51 && k1^0==k1^post_51 && k2^0==k2^post_51 && k3^0==k3^post_51 && k5^0==k5^post_51 && 0==keA^post_51 && ntStatus^0==ntStatus^post_51 && pIrb^0==pIrb^post_51 && phi_io_compl^0==phi_io_compl^post_51 && phi_nSUC_ret^0==phi_nSUC_ret^post_51 && prevCancel^0==prevCancel^post_51 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_51 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_51 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_51 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_51 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_51 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_51 && 1<=IsochResourceData^post_51 ], cost: 4
     64: l2 -> l1 : __rho_11_^0'=__rho_11_^post_1, i___02020^0'=Irql^0, k4^0'=__rho_11_^post_1, keA^0'=0, keR^0'=0, [ k3^0<=0 ], cost: 2
    105: l10 -> l2 : __rho_10_^0'=__rho_10_^post_15, __rho_4_^0'=__rho_4_^post_28, i___01313^0'=Irql^0, i___099^0'=Irql^0, k2^0'=__rho_4_^post_28, k3^0'=__rho_10_^post_15, keA^0'=0, keR^0'=0, [ k1^0<=0 && __rho_4_^post_28<=0 ], cost: 4
    106: l10 -> l2 : IsochDetachData^0'=IsochDetachData^post_2, __rho_10_^0'=__rho_10_^post_15, __rho_4_^0'=__rho_4_^post_28, a1818^0'=IsochDetachData^post_2, i^0'=i^post_2, i___01313^0'=Irql^0, i___01717^0'=Irql^0, i___099^0'=Irql^0, k2^0'=__rho_4_^post_28, k3^0'=0, keA^0'=0, keR^0'=0, [ k1^0<=0 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 ], cost: 4+2*__rho_10_^post_15
    107: l10 -> l2 : AsyncAddressData^0'=AsyncAddressData^post_14, __rho_10_^0'=__rho_10_^post_15, __rho_4_^0'=__rho_4_^post_28, __rho_7_^0'=__rho_7_^post_14, __rho_8_^0'=__rho_8_^post_10, __rho_9_^0'=__rho_9_^post_7, i___01313^0'=Irql^0, i___099^0'=Irql^0, k2^0'=0, k3^0'=__rho_10_^post_15, keA^0'=0, keR^0'=0, [ k1^0<=0 && __rho_4_^post_28>=1 ], cost: 4+8*__rho_4_^post_28
    108: l10 -> l2 : AsyncAddressData^0'=AsyncAddressData^post_14, IsochDetachData^0'=IsochDetachData^post_2, __rho_10_^0'=__rho_10_^post_15, __rho_4_^0'=__rho_4_^post_28, __rho_7_^0'=__rho_7_^post_14, __rho_8_^0'=__rho_8_^post_10, __rho_9_^0'=__rho_9_^post_7, a1818^0'=IsochDetachData^post_2, i^0'=i^post_2, i___01313^0'=Irql^0, i___01717^0'=Irql^0, i___099^0'=Irql^0, k2^0'=0, k3^0'=0, keA^0'=0, keR^0'=0, [ k1^0<=0 && __rho_4_^post_28>=1 && __rho_10_^post_15>=1 ], cost: 4+2*__rho_10_^post_15+8*__rho_4_^post_28
    109: l10 -> l10 : CromData^0'=CromData^post_27, k1^0'=-1+k1^0, [ 1<=k1^0 && CromData^post_27<=0 ], cost: 3
    110: l10 -> l10 : CromData^0'=CromData^post_27, __rho_2_^0'=__rho_2_^post_26, __rho_3_^0'=__rho_3_^post_21, a77^0'=CromData^post_27, k1^0'=-1+k1^0, [ 1<=k1^0 && 1<=CromData^post_27 ], cost: 7
     57: l26 -> [35] : [ -2+ntStatus^0==0 ], cost: NONTERM
     70: l26 -> [35] : [ 3<=ntStatus^0 ], cost: NONTERM
     71: l26 -> [35] : [ 1+ntStatus^0<=2 ], cost: NONTERM
    103: l34 -> l10 : AsyncAddressData^0'=AsyncAddressData^post_52, BusResetIrp^0'=BusResetIrp^post_52, CromData^0'=CromData^post_52, DeviceObject^0'=DeviceObject^post_52, Irp^0'=Irp^post_52, Irql^0'=Irql^post_52, IsochDetachData^0'=IsochDetachData^post_52, IsochResourceData^0'=IsochResourceData^post_52, ResourceIrp^0'=ResourceIrp^post_52, StackSize^0'=StackSize^post_52, __rho_10_^0'=__rho_10_^post_52, __rho_11_^0'=__rho_11_^post_52, __rho_12_^0'=__rho_12_^post_52, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_52, __rho_3_^0'=__rho_3_^post_52, __rho_4_^0'=__rho_4_^post_52, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, __rho_7_^0'=__rho_7_^post_52, __rho_8_^0'=__rho_8_^post_52, __rho_9_^0'=__rho_9_^post_52, a11^0'=a11^post_52, a1818^0'=a1818^post_52, a2525^0'=a2525^post_52, a2828^0'=a2828^post_52, a3131^0'=a3131^post_52, a3232^0'=a3232^post_52, a3434^0'=a3434^post_52, a3737^0'=a3737^post_52, a3838^0'=a3838^post_52, a4343^0'=a4343^post_52, a4545^0'=a4545^post_52, a77^0'=a77^post_52, b22^0'=b22^post_52, b2626^0'=b2626^post_52, b2929^0'=b2929^post_52, b3333^0'=b3333^post_52, b3535^0'=b3535^post_52, i^0'=i^post_52, i___01313^0'=i___01313^post_52, i___01717^0'=i___01717^post_52, i___02020^0'=i___02020^post_52, i___02424^0'=i___02424^post_52, i___04040^0'=i___04040^post_52, i___04747^0'=i___04747^post_52, i___099^0'=i___099^post_52, ioA^0'=ioA^post_52, ioR^0'=ioR^post_52, k1^0'=__rho_5_^post_30, k2^0'=k2^post_52, k3^0'=k3^post_52, k4^0'=k4^post_52, k5^0'=k5^post_52, keA^0'=0, keR^0'=keR^post_52, ntStatus^0'=0, pIrb^0'=pIrb^post_52, phi_io_compl^0'=phi_io_compl^post_52, phi_nSUC_ret^0'=phi_nSUC_ret^post_52, prevCancel^0'=prevCancel^post_52, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_52, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_52, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_52, ret_IoSetDeviceInterfaceState44^0'=0, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_52, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_52, [ AsyncAddressData^0==AsyncAddressData^post_53 && BusResetIrp^0==BusResetIrp^post_53 && CromData^0==CromData^post_53 && DeviceObject^0==DeviceObject^post_53 && Irp^0==Irp^post_53 && Irql^0==Irql^post_53 && IsochDetachData^0==IsochDetachData^post_53 && IsochResourceData^0==IsochResourceData^post_53 && ResourceIrp^0==ResourceIrp^post_53 && StackSize^0==StackSize^post_53 && __rho_10_^0==__rho_10_^post_53 && __rho_11_^0==__rho_11_^post_53 && __rho_12_^0==__rho_12_^post_53 && __rho_1_^0==__rho_1_^post_53 && __rho_2_^0==__rho_2_^post_53 && __rho_3_^0==__rho_3_^post_53 && __rho_4_^0==__rho_4_^post_53 && __rho_5_^0==__rho_5_^post_53 && __rho_666_^0==__rho_666_^post_53 && __rho_7_^0==__rho_7_^post_53 && __rho_8_^0==__rho_8_^post_53 && __rho_9_^0==__rho_9_^post_53 && a11^0==a11^post_53 && a1818^0==a1818^post_53 && a2525^0==a2525^post_53 && a2828^0==a2828^post_53 && a3131^0==a3131^post_53 && a3232^0==a3232^post_53 && a3434^0==a3434^post_53 && a3737^0==a3737^post_53 && a3838^0==a3838^post_53 && a4343^0==a4343^post_53 && a4545^0==a4545^post_53 && a77^0==a77^post_53 && b22^0==b22^post_53 && b2626^0==b2626^post_53 && b2929^0==b2929^post_53 && b3333^0==b3333^post_53 && b3535^0==b3535^post_53 && i^0==i^post_53 && i___01313^0==i___01313^post_53 && i___01717^0==i___01717^post_53 && i___02020^0==i___02020^post_53 && i___02424^0==i___02424^post_53 && i___04040^0==i___04040^post_53 && i___04747^0==i___04747^post_53 && i___099^0==i___099^post_53 && ioA^0==ioA^post_53 && ioR^0==ioR^post_53 && k1^0==k1^post_53 && k2^0==k2^post_53 && k3^0==k3^post_53 && k4^0==k4^post_53 && k5^0==k5^post_53 && keA^0==keA^post_53 && keR^0==keR^post_53 && ntStatus^0==ntStatus^post_53 && pIrb^0==pIrb^post_53 && phi_io_compl^0==phi_io_compl^post_53 && phi_nSUC_ret^0==phi_nSUC_ret^post_53 && prevCancel^0==prevCancel^post_53 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_53 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_53 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_53 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_53 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_53 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_53 && ioR^post_52==0 && ioA^post_52==ioR^post_52 && keR^post_52==ioA^post_52 && keA^post_52==keR^post_52 && phi_nSUC_ret^post_52==0 && phi_io_compl^post_52==0 && AsyncAddressData^post_53==AsyncAddressData^post_52 && BusResetIrp^post_53==BusResetIrp^post_52 && CromData^post_53==CromData^post_52 && DeviceObject^post_53==DeviceObject^post_52 && Irp^post_53==Irp^post_52 && Irql^post_53==Irql^post_52 && IsochDetachData^post_53==IsochDetachData^post_52 && IsochResourceData^post_53==IsochResourceData^post_52 && ResourceIrp^post_53==ResourceIrp^post_52 && StackSize^post_53==StackSize^post_52 && __rho_10_^post_53==__rho_10_^post_52 && __rho_11_^post_53==__rho_11_^post_52 && __rho_12_^post_53==__rho_12_^post_52 && __rho_2_^post_53==__rho_2_^post_52 && __rho_3_^post_53==__rho_3_^post_52 && __rho_4_^post_53==__rho_4_^post_52 && __rho_5_^post_53==__rho_5_^post_52 && __rho_7_^post_53==__rho_7_^post_52 && __rho_8_^post_53==__rho_8_^post_52 && __rho_9_^post_53==__rho_9_^post_52 && a11^post_53==a11^post_52 && a1818^post_53==a1818^post_52 && a2525^post_53==a2525^post_52 && a2828^post_53==a2828^post_52 && a3131^post_53==a3131^post_52 && a3232^post_53==a3232^post_52 && a3434^post_53==a3434^post_52 && a3737^post_53==a3737^post_52 && a3838^post_53==a3838^post_52 && a4343^post_53==a4343^post_52 && a4545^post_53==a4545^post_52 && a77^post_53==a77^post_52 && b22^post_53==b22^post_52 && b2626^post_53==b2626^post_52 && b2929^post_53==b2929^post_52 && b3333^post_53==b3333^post_52 && b3535^post_53==b3535^post_52 && i^post_53==i^post_52 && i___01313^post_53==i___01313^post_52 && i___01717^post_53==i___01717^post_52 && i___02020^post_53==i___02020^post_52 && i___02424^post_53==i___02424^post_52 && i___04040^post_53==i___04040^post_52 && i___04747^post_53==i___04747^post_52 && i___099^post_53==i___099^post_52 && k1^post_53==k1^post_52 && k2^post_53==k2^post_52 && k3^post_53==k3^post_52 && k4^post_53==k4^post_52 && k5^post_53==k5^post_52 && ntStatus^post_53==ntStatus^post_52 && pIrb^post_53==pIrb^post_52 && prevCancel^post_53==prevCancel^post_52 && ret_ExAllocatePool3030^post_53==ret_ExAllocatePool3030^post_52 && ret_IoAllocateIrp2727^post_53==ret_IoAllocateIrp2727^post_52 && ret_IoSetCancelRoutine4444^post_53==ret_IoSetCancelRoutine4444^post_52 && ret_IoSetDeviceInterfaceState44^post_53==ret_IoSetDeviceInterfaceState44^post_52 && ret_t1394Diag_PnpStopDevice33^post_53==ret_t1394Diag_PnpStopDevice33^post_52 && ret_t1394_SubmitIrpSynch3636^post_53==ret_t1394_SubmitIrpSynch3636^post_52 && __rho_1_^post_52<=0 ], cost: 4
    104: l34 -> l10 : AsyncAddressData^0'=AsyncAddressData^post_52, BusResetIrp^0'=BusResetIrp^post_52, CromData^0'=CromData^post_52, DeviceObject^0'=DeviceObject^post_52, Irp^0'=Irp^post_52, Irql^0'=Irql^post_52, IsochDetachData^0'=IsochDetachData^post_52, IsochResourceData^0'=IsochResourceData^post_52, ResourceIrp^0'=ResourceIrp^post_52, StackSize^0'=StackSize^post_52, __rho_10_^0'=__rho_10_^post_52, __rho_11_^0'=__rho_11_^post_52, __rho_12_^0'=__rho_12_^post_52, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_52, __rho_3_^0'=__rho_3_^post_52, __rho_4_^0'=__rho_4_^post_52, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, __rho_7_^0'=__rho_7_^post_52, __rho_8_^0'=__rho_8_^post_52, __rho_9_^0'=__rho_9_^post_52, a11^0'=DeviceObject^post_52, a1818^0'=a1818^post_52, a2525^0'=a2525^post_52, a2828^0'=a2828^post_52, a3131^0'=a3131^post_52, a3232^0'=a3232^post_52, a3434^0'=a3434^post_52, a3737^0'=a3737^post_52, a3838^0'=a3838^post_52, a4343^0'=a4343^post_52, a4545^0'=a4545^post_52, a77^0'=a77^post_52, b22^0'=Irp^post_52, b2626^0'=b2626^post_52, b2929^0'=b2929^post_52, b3333^0'=b3333^post_52, b3535^0'=b3535^post_52, i^0'=i^post_52, i___01313^0'=i___01313^post_52, i___01717^0'=i___01717^post_52, i___02020^0'=i___02020^post_52, i___02424^0'=i___02424^post_52, i___04040^0'=i___04040^post_52, i___04747^0'=i___04747^post_52, i___099^0'=i___099^post_52, ioA^0'=ioA^post_52, ioR^0'=ioR^post_52, k1^0'=__rho_5_^post_30, k2^0'=k2^post_52, k3^0'=k3^post_52, k4^0'=k4^post_52, k5^0'=k5^post_52, keA^0'=0, keR^0'=keR^post_52, ntStatus^0'=0, pIrb^0'=pIrb^post_52, phi_io_compl^0'=phi_io_compl^post_52, phi_nSUC_ret^0'=phi_nSUC_ret^post_52, prevCancel^0'=prevCancel^post_52, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_52, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_52, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_52, ret_IoSetDeviceInterfaceState44^0'=0, ret_t1394Diag_PnpStopDevice33^0'=0, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_52, [ AsyncAddressData^0==AsyncAddressData^post_53 && BusResetIrp^0==BusResetIrp^post_53 && CromData^0==CromData^post_53 && DeviceObject^0==DeviceObject^post_53 && Irp^0==Irp^post_53 && Irql^0==Irql^post_53 && IsochDetachData^0==IsochDetachData^post_53 && IsochResourceData^0==IsochResourceData^post_53 && ResourceIrp^0==ResourceIrp^post_53 && StackSize^0==StackSize^post_53 && __rho_10_^0==__rho_10_^post_53 && __rho_11_^0==__rho_11_^post_53 && __rho_12_^0==__rho_12_^post_53 && __rho_1_^0==__rho_1_^post_53 && __rho_2_^0==__rho_2_^post_53 && __rho_3_^0==__rho_3_^post_53 && __rho_4_^0==__rho_4_^post_53 && __rho_5_^0==__rho_5_^post_53 && __rho_666_^0==__rho_666_^post_53 && __rho_7_^0==__rho_7_^post_53 && __rho_8_^0==__rho_8_^post_53 && __rho_9_^0==__rho_9_^post_53 && a11^0==a11^post_53 && a1818^0==a1818^post_53 && a2525^0==a2525^post_53 && a2828^0==a2828^post_53 && a3131^0==a3131^post_53 && a3232^0==a3232^post_53 && a3434^0==a3434^post_53 && a3737^0==a3737^post_53 && a3838^0==a3838^post_53 && a4343^0==a4343^post_53 && a4545^0==a4545^post_53 && a77^0==a77^post_53 && b22^0==b22^post_53 && b2626^0==b2626^post_53 && b2929^0==b2929^post_53 && b3333^0==b3333^post_53 && b3535^0==b3535^post_53 && i^0==i^post_53 && i___01313^0==i___01313^post_53 && i___01717^0==i___01717^post_53 && i___02020^0==i___02020^post_53 && i___02424^0==i___02424^post_53 && i___04040^0==i___04040^post_53 && i___04747^0==i___04747^post_53 && i___099^0==i___099^post_53 && ioA^0==ioA^post_53 && ioR^0==ioR^post_53 && k1^0==k1^post_53 && k2^0==k2^post_53 && k3^0==k3^post_53 && k4^0==k4^post_53 && k5^0==k5^post_53 && keA^0==keA^post_53 && keR^0==keR^post_53 && ntStatus^0==ntStatus^post_53 && pIrb^0==pIrb^post_53 && phi_io_compl^0==phi_io_compl^post_53 && phi_nSUC_ret^0==phi_nSUC_ret^post_53 && prevCancel^0==prevCancel^post_53 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_53 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_53 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_53 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_53 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_53 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_53 && ioR^post_52==0 && ioA^post_52==ioR^post_52 && keR^post_52==ioA^post_52 && keA^post_52==keR^post_52 && phi_nSUC_ret^post_52==0 && phi_io_compl^post_52==0 && AsyncAddressData^post_53==AsyncAddressData^post_52 && BusResetIrp^post_53==BusResetIrp^post_52 && CromData^post_53==CromData^post_52 && DeviceObject^post_53==DeviceObject^post_52 && Irp^post_53==Irp^post_52 && Irql^post_53==Irql^post_52 && IsochDetachData^post_53==IsochDetachData^post_52 && IsochResourceData^post_53==IsochResourceData^post_52 && ResourceIrp^post_53==ResourceIrp^post_52 && StackSize^post_53==StackSize^post_52 && __rho_10_^post_53==__rho_10_^post_52 && __rho_11_^post_53==__rho_11_^post_52 && __rho_12_^post_53==__rho_12_^post_52 && __rho_2_^post_53==__rho_2_^post_52 && __rho_3_^post_53==__rho_3_^post_52 && __rho_4_^post_53==__rho_4_^post_52 && __rho_5_^post_53==__rho_5_^post_52 && __rho_7_^post_53==__rho_7_^post_52 && __rho_8_^post_53==__rho_8_^post_52 && __rho_9_^post_53==__rho_9_^post_52 && a11^post_53==a11^post_52 && a1818^post_53==a1818^post_52 && a2525^post_53==a2525^post_52 && a2828^post_53==a2828^post_52 && a3131^post_53==a3131^post_52 && a3232^post_53==a3232^post_52 && a3434^post_53==a3434^post_52 && a3737^post_53==a3737^post_52 && a3838^post_53==a3838^post_52 && a4343^post_53==a4343^post_52 && a4545^post_53==a4545^post_52 && a77^post_53==a77^post_52 && b22^post_53==b22^post_52 && b2626^post_53==b2626^post_52 && b2929^post_53==b2929^post_52 && b3333^post_53==b3333^post_52 && b3535^post_53==b3535^post_52 && i^post_53==i^post_52 && i___01313^post_53==i___01313^post_52 && i___01717^post_53==i___01717^post_52 && i___02020^post_53==i___02020^post_52 && i___02424^post_53==i___02424^post_52 && i___04040^post_53==i___04040^post_52 && i___04747^post_53==i___04747^post_52 && i___099^post_53==i___099^post_52 && k1^post_53==k1^post_52 && k2^post_53==k2^post_52 && k3^post_53==k3^post_52 && k4^post_53==k4^post_52 && k5^post_53==k5^post_52 && ntStatus^post_53==ntStatus^post_52 && pIrb^post_53==pIrb^post_52 && prevCancel^post_53==prevCancel^post_52 && ret_ExAllocatePool3030^post_53==ret_ExAllocatePool3030^post_52 && ret_IoAllocateIrp2727^post_53==ret_IoAllocateIrp2727^post_52 && ret_IoSetCancelRoutine4444^post_53==ret_IoSetCancelRoutine4444^post_52 && ret_IoSetDeviceInterfaceState44^post_53==ret_IoSetDeviceInterfaceState44^post_52 && ret_t1394Diag_PnpStopDevice33^post_53==ret_t1394Diag_PnpStopDevice33^post_52 && ret_t1394_SubmitIrpSynch3636^post_53==ret_t1394_SubmitIrpSynch3636^post_52 && 1<=__rho_1_^post_52 ], cost: 4

Accelerating simple loops of location 1.
   Simplified some of the simple loops (and removed duplicate rules).
   Accelerating the following rules:
    113: l1 -> l1 : IsochResourceData^0'=IsochResourceData^post_51, i___02424^0'=Irql^0, k4^0'=-1+k4^0, keA^0'=0, keR^0'=0, [ 1<=k4^0 && IsochResourceData^post_51<=0 ], cost: 3
    114: l1 -> l1 : IsochResourceData^0'=IsochResourceData^post_51, ResourceIrp^0'=0, StackSize^0'=a2525^post_49, a2525^0'=a2525^post_49, b2626^0'=0, i___02424^0'=Irql^0, k4^0'=-1+k4^0, keA^0'=0, keR^0'=0, pIrb^0'=pIrb^post_49, ret_IoAllocateIrp2727^0'=0, [ 1<=k4^0 && 1<=IsochResourceData^post_51 ], cost: 4

   Accelerated rule 113 with backward acceleration, yielding the new rule 115.
   Accelerated rule 114 with backward acceleration, yielding the new rule 116.
[accelerate] Nesting with 2 inner and 2 outer candidates
   Removing the simple loops: 113 114.

Accelerating simple loops of location 10.
   Accelerating the following rules:
    109: l10 -> l10 : CromData^0'=CromData^post_27, k1^0'=-1+k1^0, [ 1<=k1^0 && CromData^post_27<=0 ], cost: 3
    110: l10 -> l10 : CromData^0'=CromData^post_27, __rho_2_^0'=__rho_2_^post_26, __rho_3_^0'=__rho_3_^post_21, a77^0'=CromData^post_27, k1^0'=-1+k1^0, [ 1<=k1^0 && 1<=CromData^post_27 ], cost: 7

   Accelerated rule 109 with backward acceleration, yielding the new rule 117.
   Accelerated rule 110 with backward acceleration, yielding the new rule 118.
[accelerate] Nesting with 2 inner and 2 outer candidates
   Removing the simple loops: 109 110.

Accelerated all simple loops using metering functions (where possible):
   Start location: l34
    111: l1 -> l26 : AsyncAddressData^0'=AsyncAddressData^post_50, BusResetIrp^0'=BusResetIrp^post_50, CromData^0'=CromData^post_50, DeviceObject^0'=DeviceObject^post_50, Irp^0'=Irp^post_50, Irql^0'=Irql^post_50, IsochDetachData^0'=IsochDetachData^post_50, IsochResourceData^0'=IsochResourceData^post_50, ResourceIrp^0'=ResourceIrp^post_50, StackSize^0'=StackSize^post_50, __rho_10_^0'=__rho_10_^post_50, __rho_11_^0'=__rho_11_^post_50, __rho_12_^0'=__rho_12_^post_50, __rho_1_^0'=__rho_1_^post_50, __rho_2_^0'=__rho_2_^post_50, __rho_3_^0'=__rho_3_^post_50, __rho_4_^0'=__rho_4_^post_50, __rho_5_^0'=__rho_5_^post_50, __rho_666_^0'=__rho_666_^post_50, __rho_7_^0'=__rho_7_^post_50, __rho_8_^0'=__rho_8_^post_50, __rho_9_^0'=__rho_9_^post_50, a11^0'=a11^post_50, a1818^0'=a1818^post_50, a2525^0'=a2525^post_50, a2828^0'=a2828^post_50, a3131^0'=a3131^post_50, a3232^0'=a3232^post_50, a3434^0'=a3434^post_50, a3737^0'=a3737^post_50, a3838^0'=a3838^post_50, a4343^0'=a4343^post_50, a4545^0'=a4545^post_50, a77^0'=a77^post_50, b22^0'=b22^post_50, b2626^0'=b2626^post_50, b2929^0'=b2929^post_50, b3333^0'=b3333^post_50, b3535^0'=b3535^post_50, i^0'=i^post_50, i___01313^0'=i___01313^post_50, i___01717^0'=i___01717^post_50, i___02020^0'=i___02020^post_50, i___02424^0'=i___02424^post_50, i___04040^0'=i___04040^post_50, i___04747^0'=Irql^post_50, i___099^0'=i___099^post_50, ioA^0'=ioA^post_50, ioR^0'=ioR^post_50, k1^0'=k1^post_50, k2^0'=k2^post_50, k3^0'=k3^post_50, k4^0'=k4^post_50, k5^0'=k5^post_50, keA^0'=keA^post_50, keR^0'=0, ntStatus^0'=ntStatus^post_50, pIrb^0'=pIrb^post_50, phi_io_compl^0'=phi_io_compl^post_50, phi_nSUC_ret^0'=phi_nSUC_ret^post_50, prevCancel^0'=prevCancel^post_50, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_50, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_50, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_50, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_50, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_50, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_50, [ k4^0<=0 && i___04040^post_50==Irql^0 && keR^1_4_1==1 && keR^post_50==0 && keA^1_5==1 && keA^post_50==0 && k5^post_50==__rho_12_^post_50 && AsyncAddressData^0==AsyncAddressData^post_50 && BusResetIrp^0==BusResetIrp^post_50 && CromData^0==CromData^post_50 && DeviceObject^0==DeviceObject^post_50 && Irp^0==Irp^post_50 && Irql^0==Irql^post_50 && IsochDetachData^0==IsochDetachData^post_50 && IsochResourceData^0==IsochResourceData^post_50 && ResourceIrp^0==ResourceIrp^post_50 && StackSize^0==StackSize^post_50 && __rho_10_^0==__rho_10_^post_50 && __rho_11_^0==__rho_11_^post_50 && __rho_1_^0==__rho_1_^post_50 && __rho_2_^0==__rho_2_^post_50 && __rho_3_^0==__rho_3_^post_50 && __rho_4_^0==__rho_4_^post_50 && __rho_5_^0==__rho_5_^post_50 && __rho_666_^0==__rho_666_^post_50 && __rho_7_^0==__rho_7_^post_50 && __rho_8_^0==__rho_8_^post_50 && __rho_9_^0==__rho_9_^post_50 && a11^0==a11^post_50 && a1818^0==a1818^post_50 && a2525^0==a2525^post_50 && a2828^0==a2828^post_50 && a3131^0==a3131^post_50 && a3232^0==a3232^post_50 && a3434^0==a3434^post_50 && a3737^0==a3737^post_50 && a3838^0==a3838^post_50 && a4343^0==a4343^post_50 && a4545^0==a4545^post_50 && a77^0==a77^post_50 && b22^0==b22^post_50 && b2626^0==b2626^post_50 && b2929^0==b2929^post_50 && b3333^0==b3333^post_50 && b3535^0==b3535^post_50 && i^0==i^post_50 && i___01313^0==i___01313^post_50 && i___01717^0==i___01717^post_50 && i___02020^0==i___02020^post_50 && i___02424^0==i___02424^post_50 && i___04747^0==i___04747^post_50 && i___099^0==i___099^post_50 && ioA^0==ioA^post_50 && ioR^0==ioR^post_50 && k1^0==k1^post_50 && k2^0==k2^post_50 && k3^0==k3^post_50 && k4^0==k4^post_50 && ntStatus^0==ntStatus^post_50 && pIrb^0==pIrb^post_50 && phi_io_compl^0==phi_io_compl^post_50 && phi_nSUC_ret^0==phi_nSUC_ret^post_50 && prevCancel^0==prevCancel^post_50 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_50 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_50 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_50 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_50 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_50 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_50 && k5^post_50<=0 ], cost: 4
    112: l1 -> l26 : BusResetIrp^0'=BusResetIrp^post_38, __rho_12_^0'=k5^post_50, a4343^0'=0, a4545^0'=BusResetIrp^post_38, i___04040^0'=Irql^0, i___04747^0'=Irql^0, k5^0'=0, keA^0'=0, keR^0'=0, phi_io_compl^0'=1, prevCancel^0'=0, ret_IoSetCancelRoutine4444^0'=0, [ k4^0<=0 && k5^post_50>=1 ], cost: 4+2*k5^post_50
    115: l1 -> l1 : IsochResourceData^0'=IsochResourceData^post_51, i___02424^0'=Irql^0, k4^0'=0, keA^0'=0, keR^0'=0, [ IsochResourceData^post_51<=0 && k4^0>=1 ], cost: 3*k4^0
    116: l1 -> l1 : IsochResourceData^0'=IsochResourceData^post_51, ResourceIrp^0'=0, StackSize^0'=a2525^post_49, a2525^0'=a2525^post_49, b2626^0'=0, i___02424^0'=Irql^0, k4^0'=0, keA^0'=0, keR^0'=0, pIrb^0'=pIrb^post_49, ret_IoAllocateIrp2727^0'=0, [ 1<=IsochResourceData^post_51 && k4^0>=1 ], cost: 4*k4^0
     64: l2 -> l1 : __rho_11_^0'=__rho_11_^post_1, i___02020^0'=Irql^0, k4^0'=__rho_11_^post_1, keA^0'=0, keR^0'=0, [ k3^0<=0 ], cost: 2
    105: l10 -> l2 : __rho_10_^0'=__rho_10_^post_15, __rho_4_^0'=__rho_4_^post_28, i___01313^0'=Irql^0, i___099^0'=Irql^0, k2^0'=__rho_4_^post_28, k3^0'=__rho_10_^post_15, keA^0'=0, keR^0'=0, [ k1^0<=0 && __rho_4_^post_28<=0 ], cost: 4
    106: l10 -> l2 : IsochDetachData^0'=IsochDetachData^post_2, __rho_10_^0'=__rho_10_^post_15, __rho_4_^0'=__rho_4_^post_28, a1818^0'=IsochDetachData^post_2, i^0'=i^post_2, i___01313^0'=Irql^0, i___01717^0'=Irql^0, i___099^0'=Irql^0, k2^0'=__rho_4_^post_28, k3^0'=0, keA^0'=0, keR^0'=0, [ k1^0<=0 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 ], cost: 4+2*__rho_10_^post_15
    107: l10 -> l2 : AsyncAddressData^0'=AsyncAddressData^post_14, __rho_10_^0'=__rho_10_^post_15, __rho_4_^0'=__rho_4_^post_28, __rho_7_^0'=__rho_7_^post_14, __rho_8_^0'=__rho_8_^post_10, __rho_9_^0'=__rho_9_^post_7, i___01313^0'=Irql^0, i___099^0'=Irql^0, k2^0'=0, k3^0'=__rho_10_^post_15, keA^0'=0, keR^0'=0, [ k1^0<=0 && __rho_4_^post_28>=1 ], cost: 4+8*__rho_4_^post_28
    108: l10 -> l2 : AsyncAddressData^0'=AsyncAddressData^post_14, IsochDetachData^0'=IsochDetachData^post_2, __rho_10_^0'=__rho_10_^post_15, __rho_4_^0'=__rho_4_^post_28, __rho_7_^0'=__rho_7_^post_14, __rho_8_^0'=__rho_8_^post_10, __rho_9_^0'=__rho_9_^post_7, a1818^0'=IsochDetachData^post_2, i^0'=i^post_2, i___01313^0'=Irql^0, i___01717^0'=Irql^0, i___099^0'=Irql^0, k2^0'=0, k3^0'=0, keA^0'=0, keR^0'=0, [ k1^0<=0 && __rho_4_^post_28>=1 && __rho_10_^post_15>=1 ], cost: 4+2*__rho_10_^post_15+8*__rho_4_^post_28
    117: l10 -> l10 : CromData^0'=CromData^post_27, k1^0'=0, [ CromData^post_27<=0 && k1^0>=1 ], cost: 3*k1^0
    118: l10 -> l10 : CromData^0'=CromData^post_27, __rho_2_^0'=__rho_2_^post_26, __rho_3_^0'=__rho_3_^post_21, a77^0'=CromData^post_27, k1^0'=0, [ 1<=CromData^post_27 && k1^0>=1 ], cost: 7*k1^0
     57: l26 -> [35] : [ -2+ntStatus^0==0 ], cost: NONTERM
     70: l26 -> [35] : [ 3<=ntStatus^0 ], cost: NONTERM
     71: l26 -> [35] : [ 1+ntStatus^0<=2 ], cost: NONTERM
    103: l34 -> l10 : AsyncAddressData^0'=AsyncAddressData^post_52, BusResetIrp^0'=BusResetIrp^post_52, CromData^0'=CromData^post_52, DeviceObject^0'=DeviceObject^post_52, Irp^0'=Irp^post_52, Irql^0'=Irql^post_52, IsochDetachData^0'=IsochDetachData^post_52, IsochResourceData^0'=IsochResourceData^post_52, ResourceIrp^0'=ResourceIrp^post_52, StackSize^0'=StackSize^post_52, __rho_10_^0'=__rho_10_^post_52, __rho_11_^0'=__rho_11_^post_52, __rho_12_^0'=__rho_12_^post_52, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_52, __rho_3_^0'=__rho_3_^post_52, __rho_4_^0'=__rho_4_^post_52, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, __rho_7_^0'=__rho_7_^post_52, __rho_8_^0'=__rho_8_^post_52, __rho_9_^0'=__rho_9_^post_52, a11^0'=a11^post_52, a1818^0'=a1818^post_52, a2525^0'=a2525^post_52, a2828^0'=a2828^post_52, a3131^0'=a3131^post_52, a3232^0'=a3232^post_52, a3434^0'=a3434^post_52, a3737^0'=a3737^post_52, a3838^0'=a3838^post_52, a4343^0'=a4343^post_52, a4545^0'=a4545^post_52, a77^0'=a77^post_52, b22^0'=b22^post_52, b2626^0'=b2626^post_52, b2929^0'=b2929^post_52, b3333^0'=b3333^post_52, b3535^0'=b3535^post_52, i^0'=i^post_52, i___01313^0'=i___01313^post_52, i___01717^0'=i___01717^post_52, i___02020^0'=i___02020^post_52, i___02424^0'=i___02424^post_52, i___04040^0'=i___04040^post_52, i___04747^0'=i___04747^post_52, i___099^0'=i___099^post_52, ioA^0'=ioA^post_52, ioR^0'=ioR^post_52, k1^0'=__rho_5_^post_30, k2^0'=k2^post_52, k3^0'=k3^post_52, k4^0'=k4^post_52, k5^0'=k5^post_52, keA^0'=0, keR^0'=keR^post_52, ntStatus^0'=0, pIrb^0'=pIrb^post_52, phi_io_compl^0'=phi_io_compl^post_52, phi_nSUC_ret^0'=phi_nSUC_ret^post_52, prevCancel^0'=prevCancel^post_52, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_52, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_52, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_52, ret_IoSetDeviceInterfaceState44^0'=0, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_52, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_52, [ AsyncAddressData^0==AsyncAddressData^post_53 && BusResetIrp^0==BusResetIrp^post_53 && CromData^0==CromData^post_53 && DeviceObject^0==DeviceObject^post_53 && Irp^0==Irp^post_53 && Irql^0==Irql^post_53 && IsochDetachData^0==IsochDetachData^post_53 && IsochResourceData^0==IsochResourceData^post_53 && ResourceIrp^0==ResourceIrp^post_53 && StackSize^0==StackSize^post_53 && __rho_10_^0==__rho_10_^post_53 && __rho_11_^0==__rho_11_^post_53 && __rho_12_^0==__rho_12_^post_53 && __rho_1_^0==__rho_1_^post_53 && __rho_2_^0==__rho_2_^post_53 && __rho_3_^0==__rho_3_^post_53 && __rho_4_^0==__rho_4_^post_53 && __rho_5_^0==__rho_5_^post_53 && __rho_666_^0==__rho_666_^post_53 && __rho_7_^0==__rho_7_^post_53 && __rho_8_^0==__rho_8_^post_53 && __rho_9_^0==__rho_9_^post_53 && a11^0==a11^post_53 && a1818^0==a1818^post_53 && a2525^0==a2525^post_53 && a2828^0==a2828^post_53 && a3131^0==a3131^post_53 && a3232^0==a3232^post_53 && a3434^0==a3434^post_53 && a3737^0==a3737^post_53 && a3838^0==a3838^post_53 && a4343^0==a4343^post_53 && a4545^0==a4545^post_53 && a77^0==a77^post_53 && b22^0==b22^post_53 && b2626^0==b2626^post_53 && b2929^0==b2929^post_53 && b3333^0==b3333^post_53 && b3535^0==b3535^post_53 && i^0==i^post_53 && i___01313^0==i___01313^post_53 && i___01717^0==i___01717^post_53 && i___02020^0==i___02020^post_53 && i___02424^0==i___02424^post_53 && i___04040^0==i___04040^post_53 && i___04747^0==i___04747^post_53 && i___099^0==i___099^post_53 && ioA^0==ioA^post_53 && ioR^0==ioR^post_53 && k1^0==k1^post_53 && k2^0==k2^post_53 && k3^0==k3^post_53 && k4^0==k4^post_53 && k5^0==k5^post_53 && keA^0==keA^post_53 && keR^0==keR^post_53 && ntStatus^0==ntStatus^post_53 && pIrb^0==pIrb^post_53 && phi_io_compl^0==phi_io_compl^post_53 && phi_nSUC_ret^0==phi_nSUC_ret^post_53 && prevCancel^0==prevCancel^post_53 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_53 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_53 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_53 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_53 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_53 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_53 && ioR^post_52==0 && ioA^post_52==ioR^post_52 && keR^post_52==ioA^post_52 && keA^post_52==keR^post_52 && phi_nSUC_ret^post_52==0 && phi_io_compl^post_52==0 && AsyncAddressData^post_53==AsyncAddressData^post_52 && BusResetIrp^post_53==BusResetIrp^post_52 && CromData^post_53==CromData^post_52 && DeviceObject^post_53==DeviceObject^post_52 && Irp^post_53==Irp^post_52 && Irql^post_53==Irql^post_52 && IsochDetachData^post_53==IsochDetachData^post_52 && IsochResourceData^post_53==IsochResourceData^post_52 && ResourceIrp^post_53==ResourceIrp^post_52 && StackSize^post_53==StackSize^post_52 && __rho_10_^post_53==__rho_10_^post_52 && __rho_11_^post_53==__rho_11_^post_52 && __rho_12_^post_53==__rho_12_^post_52 && __rho_2_^post_53==__rho_2_^post_52 && __rho_3_^post_53==__rho_3_^post_52 && __rho_4_^post_53==__rho_4_^post_52 && __rho_5_^post_53==__rho_5_^post_52 && __rho_7_^post_53==__rho_7_^post_52 && __rho_8_^post_53==__rho_8_^post_52 && __rho_9_^post_53==__rho_9_^post_52 && a11^post_53==a11^post_52 && a1818^post_53==a1818^post_52 && a2525^post_53==a2525^post_52 && a2828^post_53==a2828^post_52 && a3131^post_53==a3131^post_52 && a3232^post_53==a3232^post_52 && a3434^post_53==a3434^post_52 && a3737^post_53==a3737^post_52 && a3838^post_53==a3838^post_52 && a4343^post_53==a4343^post_52 && a4545^post_53==a4545^post_52 && a77^post_53==a77^post_52 && b22^post_53==b22^post_52 && b2626^post_53==b2626^post_52 && b2929^post_53==b2929^post_52 && b3333^post_53==b3333^post_52 && b3535^post_53==b3535^post_52 && i^post_53==i^post_52 && i___01313^post_53==i___01313^post_52 && i___01717^post_53==i___01717^post_52 && i___02020^post_53==i___02020^post_52 && i___02424^post_53==i___02424^post_52 && i___04040^post_53==i___04040^post_52 && i___04747^post_53==i___04747^post_52 && i___099^post_53==i___099^post_52 && k1^post_53==k1^post_52 && k2^post_53==k2^post_52 && k3^post_53==k3^post_52 && k4^post_53==k4^post_52 && k5^post_53==k5^post_52 && ntStatus^post_53==ntStatus^post_52 && pIrb^post_53==pIrb^post_52 && prevCancel^post_53==prevCancel^post_52 && ret_ExAllocatePool3030^post_53==ret_ExAllocatePool3030^post_52 && ret_IoAllocateIrp2727^post_53==ret_IoAllocateIrp2727^post_52 && ret_IoSetCancelRoutine4444^post_53==ret_IoSetCancelRoutine4444^post_52 && ret_IoSetDeviceInterfaceState44^post_53==ret_IoSetDeviceInterfaceState44^post_52 && ret_t1394Diag_PnpStopDevice33^post_53==ret_t1394Diag_PnpStopDevice33^post_52 && ret_t1394_SubmitIrpSynch3636^post_53==ret_t1394_SubmitIrpSynch3636^post_52 && __rho_1_^post_52<=0 ], cost: 4
    104: l34 -> l10 : AsyncAddressData^0'=AsyncAddressData^post_52, BusResetIrp^0'=BusResetIrp^post_52, CromData^0'=CromData^post_52, DeviceObject^0'=DeviceObject^post_52, Irp^0'=Irp^post_52, Irql^0'=Irql^post_52, IsochDetachData^0'=IsochDetachData^post_52, IsochResourceData^0'=IsochResourceData^post_52, ResourceIrp^0'=ResourceIrp^post_52, StackSize^0'=StackSize^post_52, __rho_10_^0'=__rho_10_^post_52, __rho_11_^0'=__rho_11_^post_52, __rho_12_^0'=__rho_12_^post_52, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_52, __rho_3_^0'=__rho_3_^post_52, __rho_4_^0'=__rho_4_^post_52, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, __rho_7_^0'=__rho_7_^post_52, __rho_8_^0'=__rho_8_^post_52, __rho_9_^0'=__rho_9_^post_52, a11^0'=DeviceObject^post_52, a1818^0'=a1818^post_52, a2525^0'=a2525^post_52, a2828^0'=a2828^post_52, a3131^0'=a3131^post_52, a3232^0'=a3232^post_52, a3434^0'=a3434^post_52, a3737^0'=a3737^post_52, a3838^0'=a3838^post_52, a4343^0'=a4343^post_52, a4545^0'=a4545^post_52, a77^0'=a77^post_52, b22^0'=Irp^post_52, b2626^0'=b2626^post_52, b2929^0'=b2929^post_52, b3333^0'=b3333^post_52, b3535^0'=b3535^post_52, i^0'=i^post_52, i___01313^0'=i___01313^post_52, i___01717^0'=i___01717^post_52, i___02020^0'=i___02020^post_52, i___02424^0'=i___02424^post_52, i___04040^0'=i___04040^post_52, i___04747^0'=i___04747^post_52, i___099^0'=i___099^post_52, ioA^0'=ioA^post_52, ioR^0'=ioR^post_52, k1^0'=__rho_5_^post_30, k2^0'=k2^post_52, k3^0'=k3^post_52, k4^0'=k4^post_52, k5^0'=k5^post_52, keA^0'=0, keR^0'=keR^post_52, ntStatus^0'=0, pIrb^0'=pIrb^post_52, phi_io_compl^0'=phi_io_compl^post_52, phi_nSUC_ret^0'=phi_nSUC_ret^post_52, prevCancel^0'=prevCancel^post_52, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_52, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_52, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_52, ret_IoSetDeviceInterfaceState44^0'=0, ret_t1394Diag_PnpStopDevice33^0'=0, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_52, [ AsyncAddressData^0==AsyncAddressData^post_53 && BusResetIrp^0==BusResetIrp^post_53 && CromData^0==CromData^post_53 && DeviceObject^0==DeviceObject^post_53 && Irp^0==Irp^post_53 && Irql^0==Irql^post_53 && IsochDetachData^0==IsochDetachData^post_53 && IsochResourceData^0==IsochResourceData^post_53 && ResourceIrp^0==ResourceIrp^post_53 && StackSize^0==StackSize^post_53 && __rho_10_^0==__rho_10_^post_53 && __rho_11_^0==__rho_11_^post_53 && __rho_12_^0==__rho_12_^post_53 && __rho_1_^0==__rho_1_^post_53 && __rho_2_^0==__rho_2_^post_53 && __rho_3_^0==__rho_3_^post_53 && __rho_4_^0==__rho_4_^post_53 && __rho_5_^0==__rho_5_^post_53 && __rho_666_^0==__rho_666_^post_53 && __rho_7_^0==__rho_7_^post_53 && __rho_8_^0==__rho_8_^post_53 && __rho_9_^0==__rho_9_^post_53 && a11^0==a11^post_53 && a1818^0==a1818^post_53 && a2525^0==a2525^post_53 && a2828^0==a2828^post_53 && a3131^0==a3131^post_53 && a3232^0==a3232^post_53 && a3434^0==a3434^post_53 && a3737^0==a3737^post_53 && a3838^0==a3838^post_53 && a4343^0==a4343^post_53 && a4545^0==a4545^post_53 && a77^0==a77^post_53 && b22^0==b22^post_53 && b2626^0==b2626^post_53 && b2929^0==b2929^post_53 && b3333^0==b3333^post_53 && b3535^0==b3535^post_53 && i^0==i^post_53 && i___01313^0==i___01313^post_53 && i___01717^0==i___01717^post_53 && i___02020^0==i___02020^post_53 && i___02424^0==i___02424^post_53 && i___04040^0==i___04040^post_53 && i___04747^0==i___04747^post_53 && i___099^0==i___099^post_53 && ioA^0==ioA^post_53 && ioR^0==ioR^post_53 && k1^0==k1^post_53 && k2^0==k2^post_53 && k3^0==k3^post_53 && k4^0==k4^post_53 && k5^0==k5^post_53 && keA^0==keA^post_53 && keR^0==keR^post_53 && ntStatus^0==ntStatus^post_53 && pIrb^0==pIrb^post_53 && phi_io_compl^0==phi_io_compl^post_53 && phi_nSUC_ret^0==phi_nSUC_ret^post_53 && prevCancel^0==prevCancel^post_53 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_53 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_53 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_53 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_53 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_53 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_53 && ioR^post_52==0 && ioA^post_52==ioR^post_52 && keR^post_52==ioA^post_52 && keA^post_52==keR^post_52 && phi_nSUC_ret^post_52==0 && phi_io_compl^post_52==0 && AsyncAddressData^post_53==AsyncAddressData^post_52 && BusResetIrp^post_53==BusResetIrp^post_52 && CromData^post_53==CromData^post_52 && DeviceObject^post_53==DeviceObject^post_52 && Irp^post_53==Irp^post_52 && Irql^post_53==Irql^post_52 && IsochDetachData^post_53==IsochDetachData^post_52 && IsochResourceData^post_53==IsochResourceData^post_52 && ResourceIrp^post_53==ResourceIrp^post_52 && StackSize^post_53==StackSize^post_52 && __rho_10_^post_53==__rho_10_^post_52 && __rho_11_^post_53==__rho_11_^post_52 && __rho_12_^post_53==__rho_12_^post_52 && __rho_2_^post_53==__rho_2_^post_52 && __rho_3_^post_53==__rho_3_^post_52 && __rho_4_^post_53==__rho_4_^post_52 && __rho_5_^post_53==__rho_5_^post_52 && __rho_7_^post_53==__rho_7_^post_52 && __rho_8_^post_53==__rho_8_^post_52 && __rho_9_^post_53==__rho_9_^post_52 && a11^post_53==a11^post_52 && a1818^post_53==a1818^post_52 && a2525^post_53==a2525^post_52 && a2828^post_53==a2828^post_52 && a3131^post_53==a3131^post_52 && a3232^post_53==a3232^post_52 && a3434^post_53==a3434^post_52 && a3737^post_53==a3737^post_52 && a3838^post_53==a3838^post_52 && a4343^post_53==a4343^post_52 && a4545^post_53==a4545^post_52 && a77^post_53==a77^post_52 && b22^post_53==b22^post_52 && b2626^post_53==b2626^post_52 && b2929^post_53==b2929^post_52 && b3333^post_53==b3333^post_52 && b3535^post_53==b3535^post_52 && i^post_53==i^post_52 && i___01313^post_53==i___01313^post_52 && i___01717^post_53==i___01717^post_52 && i___02020^post_53==i___02020^post_52 && i___02424^post_53==i___02424^post_52 && i___04040^post_53==i___04040^post_52 && i___04747^post_53==i___04747^post_52 && i___099^post_53==i___099^post_52 && k1^post_53==k1^post_52 && k2^post_53==k2^post_52 && k3^post_53==k3^post_52 && k4^post_53==k4^post_52 && k5^post_53==k5^post_52 && ntStatus^post_53==ntStatus^post_52 && pIrb^post_53==pIrb^post_52 && prevCancel^post_53==prevCancel^post_52 && ret_ExAllocatePool3030^post_53==ret_ExAllocatePool3030^post_52 && ret_IoAllocateIrp2727^post_53==ret_IoAllocateIrp2727^post_52 && ret_IoSetCancelRoutine4444^post_53==ret_IoSetCancelRoutine4444^post_52 && ret_IoSetDeviceInterfaceState44^post_53==ret_IoSetDeviceInterfaceState44^post_52 && ret_t1394Diag_PnpStopDevice33^post_53==ret_t1394Diag_PnpStopDevice33^post_52 && ret_t1394_SubmitIrpSynch3636^post_53==ret_t1394_SubmitIrpSynch3636^post_52 && 1<=__rho_1_^post_52 ], cost: 4

Chained accelerated rules (with incoming rules):
   Start location: l34
    111: l1 -> l26 : AsyncAddressData^0'=AsyncAddressData^post_50, BusResetIrp^0'=BusResetIrp^post_50, CromData^0'=CromData^post_50, DeviceObject^0'=DeviceObject^post_50, Irp^0'=Irp^post_50, Irql^0'=Irql^post_50, IsochDetachData^0'=IsochDetachData^post_50, IsochResourceData^0'=IsochResourceData^post_50, ResourceIrp^0'=ResourceIrp^post_50, StackSize^0'=StackSize^post_50, __rho_10_^0'=__rho_10_^post_50, __rho_11_^0'=__rho_11_^post_50, __rho_12_^0'=__rho_12_^post_50, __rho_1_^0'=__rho_1_^post_50, __rho_2_^0'=__rho_2_^post_50, __rho_3_^0'=__rho_3_^post_50, __rho_4_^0'=__rho_4_^post_50, __rho_5_^0'=__rho_5_^post_50, __rho_666_^0'=__rho_666_^post_50, __rho_7_^0'=__rho_7_^post_50, __rho_8_^0'=__rho_8_^post_50, __rho_9_^0'=__rho_9_^post_50, a11^0'=a11^post_50, a1818^0'=a1818^post_50, a2525^0'=a2525^post_50, a2828^0'=a2828^post_50, a3131^0'=a3131^post_50, a3232^0'=a3232^post_50, a3434^0'=a3434^post_50, a3737^0'=a3737^post_50, a3838^0'=a3838^post_50, a4343^0'=a4343^post_50, a4545^0'=a4545^post_50, a77^0'=a77^post_50, b22^0'=b22^post_50, b2626^0'=b2626^post_50, b2929^0'=b2929^post_50, b3333^0'=b3333^post_50, b3535^0'=b3535^post_50, i^0'=i^post_50, i___01313^0'=i___01313^post_50, i___01717^0'=i___01717^post_50, i___02020^0'=i___02020^post_50, i___02424^0'=i___02424^post_50, i___04040^0'=i___04040^post_50, i___04747^0'=Irql^post_50, i___099^0'=i___099^post_50, ioA^0'=ioA^post_50, ioR^0'=ioR^post_50, k1^0'=k1^post_50, k2^0'=k2^post_50, k3^0'=k3^post_50, k4^0'=k4^post_50, k5^0'=k5^post_50, keA^0'=keA^post_50, keR^0'=0, ntStatus^0'=ntStatus^post_50, pIrb^0'=pIrb^post_50, phi_io_compl^0'=phi_io_compl^post_50, phi_nSUC_ret^0'=phi_nSUC_ret^post_50, prevCancel^0'=prevCancel^post_50, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_50, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_50, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_50, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_50, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_50, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_50, [ k4^0<=0 && i___04040^post_50==Irql^0 && keR^1_4_1==1 && keR^post_50==0 && keA^1_5==1 && keA^post_50==0 && k5^post_50==__rho_12_^post_50 && AsyncAddressData^0==AsyncAddressData^post_50 && BusResetIrp^0==BusResetIrp^post_50 && CromData^0==CromData^post_50 && DeviceObject^0==DeviceObject^post_50 && Irp^0==Irp^post_50 && Irql^0==Irql^post_50 && IsochDetachData^0==IsochDetachData^post_50 && IsochResourceData^0==IsochResourceData^post_50 && ResourceIrp^0==ResourceIrp^post_50 && StackSize^0==StackSize^post_50 && __rho_10_^0==__rho_10_^post_50 && __rho_11_^0==__rho_11_^post_50 && __rho_1_^0==__rho_1_^post_50 && __rho_2_^0==__rho_2_^post_50 && __rho_3_^0==__rho_3_^post_50 && __rho_4_^0==__rho_4_^post_50 && __rho_5_^0==__rho_5_^post_50 && __rho_666_^0==__rho_666_^post_50 && __rho_7_^0==__rho_7_^post_50 && __rho_8_^0==__rho_8_^post_50 && __rho_9_^0==__rho_9_^post_50 && a11^0==a11^post_50 && a1818^0==a1818^post_50 && a2525^0==a2525^post_50 && a2828^0==a2828^post_50 && a3131^0==a3131^post_50 && a3232^0==a3232^post_50 && a3434^0==a3434^post_50 && a3737^0==a3737^post_50 && a3838^0==a3838^post_50 && a4343^0==a4343^post_50 && a4545^0==a4545^post_50 && a77^0==a77^post_50 && b22^0==b22^post_50 && b2626^0==b2626^post_50 && b2929^0==b2929^post_50 && b3333^0==b3333^post_50 && b3535^0==b3535^post_50 && i^0==i^post_50 && i___01313^0==i___01313^post_50 && i___01717^0==i___01717^post_50 && i___02020^0==i___02020^post_50 && i___02424^0==i___02424^post_50 && i___04747^0==i___04747^post_50 && i___099^0==i___099^post_50 && ioA^0==ioA^post_50 && ioR^0==ioR^post_50 && k1^0==k1^post_50 && k2^0==k2^post_50 && k3^0==k3^post_50 && k4^0==k4^post_50 && ntStatus^0==ntStatus^post_50 && pIrb^0==pIrb^post_50 && phi_io_compl^0==phi_io_compl^post_50 && phi_nSUC_ret^0==phi_nSUC_ret^post_50 && prevCancel^0==prevCancel^post_50 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_50 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_50 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_50 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_50 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_50 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_50 && k5^post_50<=0 ], cost: 4
    112: l1 -> l26 : BusResetIrp^0'=BusResetIrp^post_38, __rho_12_^0'=k5^post_50, a4343^0'=0, a4545^0'=BusResetIrp^post_38, i___04040^0'=Irql^0, i___04747^0'=Irql^0, k5^0'=0, keA^0'=0, keR^0'=0, phi_io_compl^0'=1, prevCancel^0'=0, ret_IoSetCancelRoutine4444^0'=0, [ k4^0<=0 && k5^post_50>=1 ], cost: 4+2*k5^post_50
     64: l2 -> l1 : __rho_11_^0'=__rho_11_^post_1, i___02020^0'=Irql^0, k4^0'=__rho_11_^post_1, keA^0'=0, keR^0'=0, [ k3^0<=0 ], cost: 2
    119: l2 -> l1 : IsochResourceData^0'=IsochResourceData^post_51, __rho_11_^0'=__rho_11_^post_1, i___02020^0'=Irql^0, i___02424^0'=Irql^0, k4^0'=0, keA^0'=0, keR^0'=0, [ k3^0<=0 && IsochResourceData^post_51<=0 && __rho_11_^post_1>=1 ], cost: 2+3*__rho_11_^post_1
    120: l2 -> l1 : IsochResourceData^0'=IsochResourceData^post_51, ResourceIrp^0'=0, StackSize^0'=a2525^post_49, __rho_11_^0'=__rho_11_^post_1, a2525^0'=a2525^post_49, b2626^0'=0, i___02020^0'=Irql^0, i___02424^0'=Irql^0, k4^0'=0, keA^0'=0, keR^0'=0, pIrb^0'=pIrb^post_49, ret_IoAllocateIrp2727^0'=0, [ k3^0<=0 && 1<=IsochResourceData^post_51 && __rho_11_^post_1>=1 ], cost: 2+4*__rho_11_^post_1
    105: l10 -> l2 : __rho_10_^0'=__rho_10_^post_15, __rho_4_^0'=__rho_4_^post_28, i___01313^0'=Irql^0, i___099^0'=Irql^0, k2^0'=__rho_4_^post_28, k3^0'=__rho_10_^post_15, keA^0'=0, keR^0'=0, [ k1^0<=0 && __rho_4_^post_28<=0 ], cost: 4
    106: l10 -> l2 : IsochDetachData^0'=IsochDetachData^post_2, __rho_10_^0'=__rho_10_^post_15, __rho_4_^0'=__rho_4_^post_28, a1818^0'=IsochDetachData^post_2, i^0'=i^post_2, i___01313^0'=Irql^0, i___01717^0'=Irql^0, i___099^0'=Irql^0, k2^0'=__rho_4_^post_28, k3^0'=0, keA^0'=0, keR^0'=0, [ k1^0<=0 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 ], cost: 4+2*__rho_10_^post_15
    107: l10 -> l2 : AsyncAddressData^0'=AsyncAddressData^post_14, __rho_10_^0'=__rho_10_^post_15, __rho_4_^0'=__rho_4_^post_28, __rho_7_^0'=__rho_7_^post_14, __rho_8_^0'=__rho_8_^post_10, __rho_9_^0'=__rho_9_^post_7, i___01313^0'=Irql^0, i___099^0'=Irql^0, k2^0'=0, k3^0'=__rho_10_^post_15, keA^0'=0, keR^0'=0, [ k1^0<=0 && __rho_4_^post_28>=1 ], cost: 4+8*__rho_4_^post_28
    108: l10 -> l2 : AsyncAddressData^0'=AsyncAddressData^post_14, IsochDetachData^0'=IsochDetachData^post_2, __rho_10_^0'=__rho_10_^post_15, __rho_4_^0'=__rho_4_^post_28, __rho_7_^0'=__rho_7_^post_14, __rho_8_^0'=__rho_8_^post_10, __rho_9_^0'=__rho_9_^post_7, a1818^0'=IsochDetachData^post_2, i^0'=i^post_2, i___01313^0'=Irql^0, i___01717^0'=Irql^0, i___099^0'=Irql^0, k2^0'=0, k3^0'=0, keA^0'=0, keR^0'=0, [ k1^0<=0 && __rho_4_^post_28>=1 && __rho_10_^post_15>=1 ], cost: 4+2*__rho_10_^post_15+8*__rho_4_^post_28
     57: l26 -> [35] : [ -2+ntStatus^0==0 ], cost: NONTERM
     70: l26 -> [35] : [ 3<=ntStatus^0 ], cost: NONTERM
     71: l26 -> [35] : [ 1+ntStatus^0<=2 ], cost: NONTERM
    103: l34 -> l10 : AsyncAddressData^0'=AsyncAddressData^post_52, BusResetIrp^0'=BusResetIrp^post_52, CromData^0'=CromData^post_52, DeviceObject^0'=DeviceObject^post_52, Irp^0'=Irp^post_52, Irql^0'=Irql^post_52, IsochDetachData^0'=IsochDetachData^post_52, IsochResourceData^0'=IsochResourceData^post_52, ResourceIrp^0'=ResourceIrp^post_52, StackSize^0'=StackSize^post_52, __rho_10_^0'=__rho_10_^post_52, __rho_11_^0'=__rho_11_^post_52, __rho_12_^0'=__rho_12_^post_52, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_52, __rho_3_^0'=__rho_3_^post_52, __rho_4_^0'=__rho_4_^post_52, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, __rho_7_^0'=__rho_7_^post_52, __rho_8_^0'=__rho_8_^post_52, __rho_9_^0'=__rho_9_^post_52, a11^0'=a11^post_52, a1818^0'=a1818^post_52, a2525^0'=a2525^post_52, a2828^0'=a2828^post_52, a3131^0'=a3131^post_52, a3232^0'=a3232^post_52, a3434^0'=a3434^post_52, a3737^0'=a3737^post_52, a3838^0'=a3838^post_52, a4343^0'=a4343^post_52, a4545^0'=a4545^post_52, a77^0'=a77^post_52, b22^0'=b22^post_52, b2626^0'=b2626^post_52, b2929^0'=b2929^post_52, b3333^0'=b3333^post_52, b3535^0'=b3535^post_52, i^0'=i^post_52, i___01313^0'=i___01313^post_52, i___01717^0'=i___01717^post_52, i___02020^0'=i___02020^post_52, i___02424^0'=i___02424^post_52, i___04040^0'=i___04040^post_52, i___04747^0'=i___04747^post_52, i___099^0'=i___099^post_52, ioA^0'=ioA^post_52, ioR^0'=ioR^post_52, k1^0'=__rho_5_^post_30, k2^0'=k2^post_52, k3^0'=k3^post_52, k4^0'=k4^post_52, k5^0'=k5^post_52, keA^0'=0, keR^0'=keR^post_52, ntStatus^0'=0, pIrb^0'=pIrb^post_52, phi_io_compl^0'=phi_io_compl^post_52, phi_nSUC_ret^0'=phi_nSUC_ret^post_52, prevCancel^0'=prevCancel^post_52, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_52, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_52, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_52, ret_IoSetDeviceInterfaceState44^0'=0, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_52, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_52, [ AsyncAddressData^0==AsyncAddressData^post_53 && BusResetIrp^0==BusResetIrp^post_53 && CromData^0==CromData^post_53 && DeviceObject^0==DeviceObject^post_53 && Irp^0==Irp^post_53 && Irql^0==Irql^post_53 && IsochDetachData^0==IsochDetachData^post_53 && IsochResourceData^0==IsochResourceData^post_53 && ResourceIrp^0==ResourceIrp^post_53 && StackSize^0==StackSize^post_53 && __rho_10_^0==__rho_10_^post_53 && __rho_11_^0==__rho_11_^post_53 && __rho_12_^0==__rho_12_^post_53 && __rho_1_^0==__rho_1_^post_53 && __rho_2_^0==__rho_2_^post_53 && __rho_3_^0==__rho_3_^post_53 && __rho_4_^0==__rho_4_^post_53 && __rho_5_^0==__rho_5_^post_53 && __rho_666_^0==__rho_666_^post_53 && __rho_7_^0==__rho_7_^post_53 && __rho_8_^0==__rho_8_^post_53 && __rho_9_^0==__rho_9_^post_53 && a11^0==a11^post_53 && a1818^0==a1818^post_53 && a2525^0==a2525^post_53 && a2828^0==a2828^post_53 && a3131^0==a3131^post_53 && a3232^0==a3232^post_53 && a3434^0==a3434^post_53 && a3737^0==a3737^post_53 && a3838^0==a3838^post_53 && a4343^0==a4343^post_53 && a4545^0==a4545^post_53 && a77^0==a77^post_53 && b22^0==b22^post_53 && b2626^0==b2626^post_53 && b2929^0==b2929^post_53 && b3333^0==b3333^post_53 && b3535^0==b3535^post_53 && i^0==i^post_53 && i___01313^0==i___01313^post_53 && i___01717^0==i___01717^post_53 && i___02020^0==i___02020^post_53 && i___02424^0==i___02424^post_53 && i___04040^0==i___04040^post_53 && i___04747^0==i___04747^post_53 && i___099^0==i___099^post_53 && ioA^0==ioA^post_53 && ioR^0==ioR^post_53 && k1^0==k1^post_53 && k2^0==k2^post_53 && k3^0==k3^post_53 && k4^0==k4^post_53 && k5^0==k5^post_53 && keA^0==keA^post_53 && keR^0==keR^post_53 && ntStatus^0==ntStatus^post_53 && pIrb^0==pIrb^post_53 && phi_io_compl^0==phi_io_compl^post_53 && phi_nSUC_ret^0==phi_nSUC_ret^post_53 && prevCancel^0==prevCancel^post_53 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_53 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_53 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_53 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_53 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_53 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_53 && ioR^post_52==0 && ioA^post_52==ioR^post_52 && keR^post_52==ioA^post_52 && keA^post_52==keR^post_52 && phi_nSUC_ret^post_52==0 && phi_io_compl^post_52==0 && AsyncAddressData^post_53==AsyncAddressData^post_52 && BusResetIrp^post_53==BusResetIrp^post_52 && CromData^post_53==CromData^post_52 && DeviceObject^post_53==DeviceObject^post_52 && Irp^post_53==Irp^post_52 && Irql^post_53==Irql^post_52 && IsochDetachData^post_53==IsochDetachData^post_52 && IsochResourceData^post_53==IsochResourceData^post_52 && ResourceIrp^post_53==ResourceIrp^post_52 && StackSize^post_53==StackSize^post_52 && __rho_10_^post_53==__rho_10_^post_52 && __rho_11_^post_53==__rho_11_^post_52 && __rho_12_^post_53==__rho_12_^post_52 && __rho_2_^post_53==__rho_2_^post_52 && __rho_3_^post_53==__rho_3_^post_52 && __rho_4_^post_53==__rho_4_^post_52 && __rho_5_^post_53==__rho_5_^post_52 && __rho_7_^post_53==__rho_7_^post_52 && __rho_8_^post_53==__rho_8_^post_52 && __rho_9_^post_53==__rho_9_^post_52 && a11^post_53==a11^post_52 && a1818^post_53==a1818^post_52 && a2525^post_53==a2525^post_52 && a2828^post_53==a2828^post_52 && a3131^post_53==a3131^post_52 && a3232^post_53==a3232^post_52 && a3434^post_53==a3434^post_52 && a3737^post_53==a3737^post_52 && a3838^post_53==a3838^post_52 && a4343^post_53==a4343^post_52 && a4545^post_53==a4545^post_52 && a77^post_53==a77^post_52 && b22^post_53==b22^post_52 && b2626^post_53==b2626^post_52 && b2929^post_53==b2929^post_52 && b3333^post_53==b3333^post_52 && b3535^post_53==b3535^post_52 && i^post_53==i^post_52 && i___01313^post_53==i___01313^post_52 && i___01717^post_53==i___01717^post_52 && i___02020^post_53==i___02020^post_52 && i___02424^post_53==i___02424^post_52 && i___04040^post_53==i___04040^post_52 && i___04747^post_53==i___04747^post_52 && i___099^post_53==i___099^post_52 && k1^post_53==k1^post_52 && k2^post_53==k2^post_52 && k3^post_53==k3^post_52 && k4^post_53==k4^post_52 && k5^post_53==k5^post_52 && ntStatus^post_53==ntStatus^post_52 && pIrb^post_53==pIrb^post_52 && prevCancel^post_53==prevCancel^post_52 && ret_ExAllocatePool3030^post_53==ret_ExAllocatePool3030^post_52 && ret_IoAllocateIrp2727^post_53==ret_IoAllocateIrp2727^post_52 && ret_IoSetCancelRoutine4444^post_53==ret_IoSetCancelRoutine4444^post_52 && ret_IoSetDeviceInterfaceState44^post_53==ret_IoSetDeviceInterfaceState44^post_52 && ret_t1394Diag_PnpStopDevice33^post_53==ret_t1394Diag_PnpStopDevice33^post_52 && ret_t1394_SubmitIrpSynch3636^post_53==ret_t1394_SubmitIrpSynch3636^post_52 && __rho_1_^post_52<=0 ], cost: 4
    104: l34 -> l10 : AsyncAddressData^0'=AsyncAddressData^post_52, BusResetIrp^0'=BusResetIrp^post_52, CromData^0'=CromData^post_52, DeviceObject^0'=DeviceObject^post_52, Irp^0'=Irp^post_52, Irql^0'=Irql^post_52, IsochDetachData^0'=IsochDetachData^post_52, IsochResourceData^0'=IsochResourceData^post_52, ResourceIrp^0'=ResourceIrp^post_52, StackSize^0'=StackSize^post_52, __rho_10_^0'=__rho_10_^post_52, __rho_11_^0'=__rho_11_^post_52, __rho_12_^0'=__rho_12_^post_52, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_52, __rho_3_^0'=__rho_3_^post_52, __rho_4_^0'=__rho_4_^post_52, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, __rho_7_^0'=__rho_7_^post_52, __rho_8_^0'=__rho_8_^post_52, __rho_9_^0'=__rho_9_^post_52, a11^0'=DeviceObject^post_52, a1818^0'=a1818^post_52, a2525^0'=a2525^post_52, a2828^0'=a2828^post_52, a3131^0'=a3131^post_52, a3232^0'=a3232^post_52, a3434^0'=a3434^post_52, a3737^0'=a3737^post_52, a3838^0'=a3838^post_52, a4343^0'=a4343^post_52, a4545^0'=a4545^post_52, a77^0'=a77^post_52, b22^0'=Irp^post_52, b2626^0'=b2626^post_52, b2929^0'=b2929^post_52, b3333^0'=b3333^post_52, b3535^0'=b3535^post_52, i^0'=i^post_52, i___01313^0'=i___01313^post_52, i___01717^0'=i___01717^post_52, i___02020^0'=i___02020^post_52, i___02424^0'=i___02424^post_52, i___04040^0'=i___04040^post_52, i___04747^0'=i___04747^post_52, i___099^0'=i___099^post_52, ioA^0'=ioA^post_52, ioR^0'=ioR^post_52, k1^0'=__rho_5_^post_30, k2^0'=k2^post_52, k3^0'=k3^post_52, k4^0'=k4^post_52, k5^0'=k5^post_52, keA^0'=0, keR^0'=keR^post_52, ntStatus^0'=0, pIrb^0'=pIrb^post_52, phi_io_compl^0'=phi_io_compl^post_52, phi_nSUC_ret^0'=phi_nSUC_ret^post_52, prevCancel^0'=prevCancel^post_52, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_52, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_52, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_52, ret_IoSetDeviceInterfaceState44^0'=0, ret_t1394Diag_PnpStopDevice33^0'=0, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_52, [ AsyncAddressData^0==AsyncAddressData^post_53 && BusResetIrp^0==BusResetIrp^post_53 && CromData^0==CromData^post_53 && DeviceObject^0==DeviceObject^post_53 && Irp^0==Irp^post_53 && Irql^0==Irql^post_53 && IsochDetachData^0==IsochDetachData^post_53 && IsochResourceData^0==IsochResourceData^post_53 && ResourceIrp^0==ResourceIrp^post_53 && StackSize^0==StackSize^post_53 && __rho_10_^0==__rho_10_^post_53 && __rho_11_^0==__rho_11_^post_53 && __rho_12_^0==__rho_12_^post_53 && __rho_1_^0==__rho_1_^post_53 && __rho_2_^0==__rho_2_^post_53 && __rho_3_^0==__rho_3_^post_53 && __rho_4_^0==__rho_4_^post_53 && __rho_5_^0==__rho_5_^post_53 && __rho_666_^0==__rho_666_^post_53 && __rho_7_^0==__rho_7_^post_53 && __rho_8_^0==__rho_8_^post_53 && __rho_9_^0==__rho_9_^post_53 && a11^0==a11^post_53 && a1818^0==a1818^post_53 && a2525^0==a2525^post_53 && a2828^0==a2828^post_53 && a3131^0==a3131^post_53 && a3232^0==a3232^post_53 && a3434^0==a3434^post_53 && a3737^0==a3737^post_53 && a3838^0==a3838^post_53 && a4343^0==a4343^post_53 && a4545^0==a4545^post_53 && a77^0==a77^post_53 && b22^0==b22^post_53 && b2626^0==b2626^post_53 && b2929^0==b2929^post_53 && b3333^0==b3333^post_53 && b3535^0==b3535^post_53 && i^0==i^post_53 && i___01313^0==i___01313^post_53 && i___01717^0==i___01717^post_53 && i___02020^0==i___02020^post_53 && i___02424^0==i___02424^post_53 && i___04040^0==i___04040^post_53 && i___04747^0==i___04747^post_53 && i___099^0==i___099^post_53 && ioA^0==ioA^post_53 && ioR^0==ioR^post_53 && k1^0==k1^post_53 && k2^0==k2^post_53 && k3^0==k3^post_53 && k4^0==k4^post_53 && k5^0==k5^post_53 && keA^0==keA^post_53 && keR^0==keR^post_53 && ntStatus^0==ntStatus^post_53 && pIrb^0==pIrb^post_53 && phi_io_compl^0==phi_io_compl^post_53 && phi_nSUC_ret^0==phi_nSUC_ret^post_53 && prevCancel^0==prevCancel^post_53 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_53 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_53 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_53 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_53 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_53 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_53 && ioR^post_52==0 && ioA^post_52==ioR^post_52 && keR^post_52==ioA^post_52 && keA^post_52==keR^post_52 && phi_nSUC_ret^post_52==0 && phi_io_compl^post_52==0 && AsyncAddressData^post_53==AsyncAddressData^post_52 && BusResetIrp^post_53==BusResetIrp^post_52 && CromData^post_53==CromData^post_52 && DeviceObject^post_53==DeviceObject^post_52 && Irp^post_53==Irp^post_52 && Irql^post_53==Irql^post_52 && IsochDetachData^post_53==IsochDetachData^post_52 && IsochResourceData^post_53==IsochResourceData^post_52 && ResourceIrp^post_53==ResourceIrp^post_52 && StackSize^post_53==StackSize^post_52 && __rho_10_^post_53==__rho_10_^post_52 && __rho_11_^post_53==__rho_11_^post_52 && __rho_12_^post_53==__rho_12_^post_52 && __rho_2_^post_53==__rho_2_^post_52 && __rho_3_^post_53==__rho_3_^post_52 && __rho_4_^post_53==__rho_4_^post_52 && __rho_5_^post_53==__rho_5_^post_52 && __rho_7_^post_53==__rho_7_^post_52 && __rho_8_^post_53==__rho_8_^post_52 && __rho_9_^post_53==__rho_9_^post_52 && a11^post_53==a11^post_52 && a1818^post_53==a1818^post_52 && a2525^post_53==a2525^post_52 && a2828^post_53==a2828^post_52 && a3131^post_53==a3131^post_52 && a3232^post_53==a3232^post_52 && a3434^post_53==a3434^post_52 && a3737^post_53==a3737^post_52 && a3838^post_53==a3838^post_52 && a4343^post_53==a4343^post_52 && a4545^post_53==a4545^post_52 && a77^post_53==a77^post_52 && b22^post_53==b22^post_52 && b2626^post_53==b2626^post_52 && b2929^post_53==b2929^post_52 && b3333^post_53==b3333^post_52 && b3535^post_53==b3535^post_52 && i^post_53==i^post_52 && i___01313^post_53==i___01313^post_52 && i___01717^post_53==i___01717^post_52 && i___02020^post_53==i___02020^post_52 && i___02424^post_53==i___02424^post_52 && i___04040^post_53==i___04040^post_52 && i___04747^post_53==i___04747^post_52 && i___099^post_53==i___099^post_52 && k1^post_53==k1^post_52 && k2^post_53==k2^post_52 && k3^post_53==k3^post_52 && k4^post_53==k4^post_52 && k5^post_53==k5^post_52 && ntStatus^post_53==ntStatus^post_52 && pIrb^post_53==pIrb^post_52 && prevCancel^post_53==prevCancel^post_52 && ret_ExAllocatePool3030^post_53==ret_ExAllocatePool3030^post_52 && ret_IoAllocateIrp2727^post_53==ret_IoAllocateIrp2727^post_52 && ret_IoSetCancelRoutine4444^post_53==ret_IoSetCancelRoutine4444^post_52 && ret_IoSetDeviceInterfaceState44^post_53==ret_IoSetDeviceInterfaceState44^post_52 && ret_t1394Diag_PnpStopDevice33^post_53==ret_t1394Diag_PnpStopDevice33^post_52 && ret_t1394_SubmitIrpSynch3636^post_53==ret_t1394_SubmitIrpSynch3636^post_52 && 1<=__rho_1_^post_52 ], cost: 4
    121: l34 -> l10 : CromData^0'=CromData^post_27, __rho_1_^0'=__rho_1_^post_52, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, ioA^0'=0, ioR^0'=0, k1^0'=0, keA^0'=0, keR^0'=0, ntStatus^0'=0, phi_io_compl^0'=0, phi_nSUC_ret^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, [ __rho_1_^post_52<=0 && CromData^post_27<=0 && __rho_5_^post_30>=1 ], cost: 4+3*__rho_5_^post_30
    122: l34 -> l10 : CromData^0'=CromData^post_27, __rho_1_^0'=__rho_1_^post_52, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, a11^0'=DeviceObject^0, b22^0'=Irp^0, ioA^0'=0, ioR^0'=0, k1^0'=0, keA^0'=0, keR^0'=0, ntStatus^0'=0, phi_io_compl^0'=0, phi_nSUC_ret^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, ret_t1394Diag_PnpStopDevice33^0'=0, [ 1<=__rho_1_^post_52 && CromData^post_27<=0 && __rho_5_^post_30>=1 ], cost: 4+3*__rho_5_^post_30
    123: l34 -> l10 : CromData^0'=CromData^post_27, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_26, __rho_3_^0'=__rho_3_^post_21, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, a77^0'=CromData^post_27, ioA^0'=0, ioR^0'=0, k1^0'=0, keA^0'=0, keR^0'=0, ntStatus^0'=0, phi_io_compl^0'=0, phi_nSUC_ret^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, [ __rho_1_^post_52<=0 && 1<=CromData^post_27 && __rho_5_^post_30>=1 ], cost: 4+7*__rho_5_^post_30
    124: l34 -> l10 : CromData^0'=CromData^post_27, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_26, __rho_3_^0'=__rho_3_^post_21, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, a11^0'=DeviceObject^0, a77^0'=CromData^post_27, b22^0'=Irp^0, ioA^0'=0, ioR^0'=0, k1^0'=0, keA^0'=0, keR^0'=0, ntStatus^0'=0, phi_io_compl^0'=0, phi_nSUC_ret^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, ret_t1394Diag_PnpStopDevice33^0'=0, [ 1<=__rho_1_^post_52 && 1<=CromData^post_27 && __rho_5_^post_30>=1 ], cost: 4+7*__rho_5_^post_30

Eliminated locations (on tree-shaped paths):
   Start location: l34
    149: l2 -> l26 : AsyncAddressData^0'=AsyncAddressData^post_50, BusResetIrp^0'=BusResetIrp^post_50, CromData^0'=CromData^post_50, DeviceObject^0'=DeviceObject^post_50, Irp^0'=Irp^post_50, Irql^0'=Irql^post_50, IsochDetachData^0'=IsochDetachData^post_50, IsochResourceData^0'=IsochResourceData^post_50, ResourceIrp^0'=ResourceIrp^post_50, StackSize^0'=StackSize^post_50, __rho_10_^0'=__rho_10_^post_50, __rho_11_^0'=__rho_11_^post_50, __rho_12_^0'=__rho_12_^post_50, __rho_1_^0'=__rho_1_^post_50, __rho_2_^0'=__rho_2_^post_50, __rho_3_^0'=__rho_3_^post_50, __rho_4_^0'=__rho_4_^post_50, __rho_5_^0'=__rho_5_^post_50, __rho_666_^0'=__rho_666_^post_50, __rho_7_^0'=__rho_7_^post_50, __rho_8_^0'=__rho_8_^post_50, __rho_9_^0'=__rho_9_^post_50, a11^0'=a11^post_50, a1818^0'=a1818^post_50, a2525^0'=a2525^post_50, a2828^0'=a2828^post_50, a3131^0'=a3131^post_50, a3232^0'=a3232^post_50, a3434^0'=a3434^post_50, a3737^0'=a3737^post_50, a3838^0'=a3838^post_50, a4343^0'=a4343^post_50, a4545^0'=a4545^post_50, a77^0'=a77^post_50, b22^0'=b22^post_50, b2626^0'=b2626^post_50, b2929^0'=b2929^post_50, b3333^0'=b3333^post_50, b3535^0'=b3535^post_50, i^0'=i^post_50, i___01313^0'=i___01313^post_50, i___01717^0'=i___01717^post_50, i___02020^0'=i___02020^post_50, i___02424^0'=i___02424^post_50, i___04040^0'=i___04040^post_50, i___04747^0'=Irql^post_50, i___099^0'=i___099^post_50, ioA^0'=ioA^post_50, ioR^0'=ioR^post_50, k1^0'=k1^post_50, k2^0'=k2^post_50, k3^0'=k3^post_50, k4^0'=k4^post_50, k5^0'=k5^post_50, keA^0'=keA^post_50, keR^0'=0, ntStatus^0'=ntStatus^post_50, pIrb^0'=pIrb^post_50, phi_io_compl^0'=phi_io_compl^post_50, phi_nSUC_ret^0'=phi_nSUC_ret^post_50, prevCancel^0'=prevCancel^post_50, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_50, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_50, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_50, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_50, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_50, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_50, [ k3^0<=0 && __rho_11_^post_1<=0 && i___04040^post_50==Irql^0 && keR^1_4_1==1 && keR^post_50==0 && keA^1_5==1 && keA^post_50==0 && k5^post_50==__rho_12_^post_50 && AsyncAddressData^0==AsyncAddressData^post_50 && BusResetIrp^0==BusResetIrp^post_50 && CromData^0==CromData^post_50 && DeviceObject^0==DeviceObject^post_50 && Irp^0==Irp^post_50 && Irql^0==Irql^post_50 && IsochDetachData^0==IsochDetachData^post_50 && IsochResourceData^0==IsochResourceData^post_50 && ResourceIrp^0==ResourceIrp^post_50 && StackSize^0==StackSize^post_50 && __rho_10_^0==__rho_10_^post_50 && __rho_11_^post_1==__rho_11_^post_50 && __rho_1_^0==__rho_1_^post_50 && __rho_2_^0==__rho_2_^post_50 && __rho_3_^0==__rho_3_^post_50 && __rho_4_^0==__rho_4_^post_50 && __rho_5_^0==__rho_5_^post_50 && __rho_666_^0==__rho_666_^post_50 && __rho_7_^0==__rho_7_^post_50 && __rho_8_^0==__rho_8_^post_50 && __rho_9_^0==__rho_9_^post_50 && a11^0==a11^post_50 && a1818^0==a1818^post_50 && a2525^0==a2525^post_50 && a2828^0==a2828^post_50 && a3131^0==a3131^post_50 && a3232^0==a3232^post_50 && a3434^0==a3434^post_50 && a3737^0==a3737^post_50 && a3838^0==a3838^post_50 && a4343^0==a4343^post_50 && a4545^0==a4545^post_50 && a77^0==a77^post_50 && b22^0==b22^post_50 && b2626^0==b2626^post_50 && b2929^0==b2929^post_50 && b3333^0==b3333^post_50 && b3535^0==b3535^post_50 && i^0==i^post_50 && i___01313^0==i___01313^post_50 && i___01717^0==i___01717^post_50 && Irql^0==i___02020^post_50 && i___02424^0==i___02424^post_50 && i___04747^0==i___04747^post_50 && i___099^0==i___099^post_50 && ioA^0==ioA^post_50 && ioR^0==ioR^post_50 && k1^0==k1^post_50 && k2^0==k2^post_50 && k3^0==k3^post_50 && __rho_11_^post_1==k4^post_50 && ntStatus^0==ntStatus^post_50 && pIrb^0==pIrb^post_50 && phi_io_compl^0==phi_io_compl^post_50 && phi_nSUC_ret^0==phi_nSUC_ret^post_50 && prevCancel^0==prevCancel^post_50 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_50 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_50 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_50 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_50 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_50 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_50 && k5^post_50<=0 ], cost: 6
    150: l2 -> l26 : BusResetIrp^0'=BusResetIrp^post_38, __rho_11_^0'=__rho_11_^post_1, __rho_12_^0'=k5^post_50, a4343^0'=0, a4545^0'=BusResetIrp^post_38, i___02020^0'=Irql^0, i___04040^0'=Irql^0, i___04747^0'=Irql^0, k4^0'=__rho_11_^post_1, k5^0'=0, keA^0'=0, keR^0'=0, phi_io_compl^0'=1, prevCancel^0'=0, ret_IoSetCancelRoutine4444^0'=0, [ k3^0<=0 && __rho_11_^post_1<=0 && k5^post_50>=1 ], cost: 6+2*k5^post_50
    151: l2 -> l26 : AsyncAddressData^0'=AsyncAddressData^post_50, BusResetIrp^0'=BusResetIrp^post_50, CromData^0'=CromData^post_50, DeviceObject^0'=DeviceObject^post_50, Irp^0'=Irp^post_50, Irql^0'=Irql^post_50, IsochDetachData^0'=IsochDetachData^post_50, IsochResourceData^0'=IsochResourceData^post_50, ResourceIrp^0'=ResourceIrp^post_50, StackSize^0'=StackSize^post_50, __rho_10_^0'=__rho_10_^post_50, __rho_11_^0'=__rho_11_^post_50, __rho_12_^0'=__rho_12_^post_50, __rho_1_^0'=__rho_1_^post_50, __rho_2_^0'=__rho_2_^post_50, __rho_3_^0'=__rho_3_^post_50, __rho_4_^0'=__rho_4_^post_50, __rho_5_^0'=__rho_5_^post_50, __rho_666_^0'=__rho_666_^post_50, __rho_7_^0'=__rho_7_^post_50, __rho_8_^0'=__rho_8_^post_50, __rho_9_^0'=__rho_9_^post_50, a11^0'=a11^post_50, a1818^0'=a1818^post_50, a2525^0'=a2525^post_50, a2828^0'=a2828^post_50, a3131^0'=a3131^post_50, a3232^0'=a3232^post_50, a3434^0'=a3434^post_50, a3737^0'=a3737^post_50, a3838^0'=a3838^post_50, a4343^0'=a4343^post_50, a4545^0'=a4545^post_50, a77^0'=a77^post_50, b22^0'=b22^post_50, b2626^0'=b2626^post_50, b2929^0'=b2929^post_50, b3333^0'=b3333^post_50, b3535^0'=b3535^post_50, i^0'=i^post_50, i___01313^0'=i___01313^post_50, i___01717^0'=i___01717^post_50, i___02020^0'=i___02020^post_50, i___02424^0'=i___02424^post_50, i___04040^0'=i___04040^post_50, i___04747^0'=Irql^post_50, i___099^0'=i___099^post_50, ioA^0'=ioA^post_50, ioR^0'=ioR^post_50, k1^0'=k1^post_50, k2^0'=k2^post_50, k3^0'=k3^post_50, k4^0'=k4^post_50, k5^0'=k5^post_50, keA^0'=keA^post_50, keR^0'=0, ntStatus^0'=ntStatus^post_50, pIrb^0'=pIrb^post_50, phi_io_compl^0'=phi_io_compl^post_50, phi_nSUC_ret^0'=phi_nSUC_ret^post_50, prevCancel^0'=prevCancel^post_50, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_50, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_50, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_50, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_50, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_50, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_50, [ k3^0<=0 && IsochResourceData^post_51<=0 && __rho_11_^post_1>=1 && i___04040^post_50==Irql^0 && keR^1_4_1==1 && keR^post_50==0 && keA^1_5==1 && keA^post_50==0 && k5^post_50==__rho_12_^post_50 && AsyncAddressData^0==AsyncAddressData^post_50 && BusResetIrp^0==BusResetIrp^post_50 && CromData^0==CromData^post_50 && DeviceObject^0==DeviceObject^post_50 && Irp^0==Irp^post_50 && Irql^0==Irql^post_50 && IsochDetachData^0==IsochDetachData^post_50 && IsochResourceData^post_51==IsochResourceData^post_50 && ResourceIrp^0==ResourceIrp^post_50 && StackSize^0==StackSize^post_50 && __rho_10_^0==__rho_10_^post_50 && __rho_11_^post_1==__rho_11_^post_50 && __rho_1_^0==__rho_1_^post_50 && __rho_2_^0==__rho_2_^post_50 && __rho_3_^0==__rho_3_^post_50 && __rho_4_^0==__rho_4_^post_50 && __rho_5_^0==__rho_5_^post_50 && __rho_666_^0==__rho_666_^post_50 && __rho_7_^0==__rho_7_^post_50 && __rho_8_^0==__rho_8_^post_50 && __rho_9_^0==__rho_9_^post_50 && a11^0==a11^post_50 && a1818^0==a1818^post_50 && a2525^0==a2525^post_50 && a2828^0==a2828^post_50 && a3131^0==a3131^post_50 && a3232^0==a3232^post_50 && a3434^0==a3434^post_50 && a3737^0==a3737^post_50 && a3838^0==a3838^post_50 && a4343^0==a4343^post_50 && a4545^0==a4545^post_50 && a77^0==a77^post_50 && b22^0==b22^post_50 && b2626^0==b2626^post_50 && b2929^0==b2929^post_50 && b3333^0==b3333^post_50 && b3535^0==b3535^post_50 && i^0==i^post_50 && i___01313^0==i___01313^post_50 && i___01717^0==i___01717^post_50 && Irql^0==i___02020^post_50 && Irql^0==i___02424^post_50 && i___04747^0==i___04747^post_50 && i___099^0==i___099^post_50 && ioA^0==ioA^post_50 && ioR^0==ioR^post_50 && k1^0==k1^post_50 && k2^0==k2^post_50 && k3^0==k3^post_50 && 0==k4^post_50 && ntStatus^0==ntStatus^post_50 && pIrb^0==pIrb^post_50 && phi_io_compl^0==phi_io_compl^post_50 && phi_nSUC_ret^0==phi_nSUC_ret^post_50 && prevCancel^0==prevCancel^post_50 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_50 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_50 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_50 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_50 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_50 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_50 && k5^post_50<=0 ], cost: 6+3*__rho_11_^post_1
    152: l2 -> l26 : BusResetIrp^0'=BusResetIrp^post_38, IsochResourceData^0'=IsochResourceData^post_51, __rho_11_^0'=__rho_11_^post_1, __rho_12_^0'=k5^post_50, a4343^0'=0, a4545^0'=BusResetIrp^post_38, i___02020^0'=Irql^0, i___02424^0'=Irql^0, i___04040^0'=Irql^0, i___04747^0'=Irql^0, k4^0'=0, k5^0'=0, keA^0'=0, keR^0'=0, phi_io_compl^0'=1, prevCancel^0'=0, ret_IoSetCancelRoutine4444^0'=0, [ k3^0<=0 && IsochResourceData^post_51<=0 && __rho_11_^post_1>=1 && k5^post_50>=1 ], cost: 6+2*k5^post_50+3*__rho_11_^post_1
    153: l2 -> l26 : AsyncAddressData^0'=AsyncAddressData^post_50, BusResetIrp^0'=BusResetIrp^post_50, CromData^0'=CromData^post_50, DeviceObject^0'=DeviceObject^post_50, Irp^0'=Irp^post_50, Irql^0'=Irql^post_50, IsochDetachData^0'=IsochDetachData^post_50, IsochResourceData^0'=IsochResourceData^post_50, ResourceIrp^0'=ResourceIrp^post_50, StackSize^0'=StackSize^post_50, __rho_10_^0'=__rho_10_^post_50, __rho_11_^0'=__rho_11_^post_50, __rho_12_^0'=__rho_12_^post_50, __rho_1_^0'=__rho_1_^post_50, __rho_2_^0'=__rho_2_^post_50, __rho_3_^0'=__rho_3_^post_50, __rho_4_^0'=__rho_4_^post_50, __rho_5_^0'=__rho_5_^post_50, __rho_666_^0'=__rho_666_^post_50, __rho_7_^0'=__rho_7_^post_50, __rho_8_^0'=__rho_8_^post_50, __rho_9_^0'=__rho_9_^post_50, a11^0'=a11^post_50, a1818^0'=a1818^post_50, a2525^0'=a2525^post_50, a2828^0'=a2828^post_50, a3131^0'=a3131^post_50, a3232^0'=a3232^post_50, a3434^0'=a3434^post_50, a3737^0'=a3737^post_50, a3838^0'=a3838^post_50, a4343^0'=a4343^post_50, a4545^0'=a4545^post_50, a77^0'=a77^post_50, b22^0'=b22^post_50, b2626^0'=b2626^post_50, b2929^0'=b2929^post_50, b3333^0'=b3333^post_50, b3535^0'=b3535^post_50, i^0'=i^post_50, i___01313^0'=i___01313^post_50, i___01717^0'=i___01717^post_50, i___02020^0'=i___02020^post_50, i___02424^0'=i___02424^post_50, i___04040^0'=i___04040^post_50, i___04747^0'=Irql^post_50, i___099^0'=i___099^post_50, ioA^0'=ioA^post_50, ioR^0'=ioR^post_50, k1^0'=k1^post_50, k2^0'=k2^post_50, k3^0'=k3^post_50, k4^0'=k4^post_50, k5^0'=k5^post_50, keA^0'=keA^post_50, keR^0'=0, ntStatus^0'=ntStatus^post_50, pIrb^0'=pIrb^post_50, phi_io_compl^0'=phi_io_compl^post_50, phi_nSUC_ret^0'=phi_nSUC_ret^post_50, prevCancel^0'=prevCancel^post_50, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_50, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_50, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_50, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_50, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_50, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_50, [ k3^0<=0 && 1<=IsochResourceData^post_51 && __rho_11_^post_1>=1 && i___04040^post_50==Irql^0 && keR^1_4_1==1 && keR^post_50==0 && keA^1_5==1 && keA^post_50==0 && k5^post_50==__rho_12_^post_50 && AsyncAddressData^0==AsyncAddressData^post_50 && BusResetIrp^0==BusResetIrp^post_50 && CromData^0==CromData^post_50 && DeviceObject^0==DeviceObject^post_50 && Irp^0==Irp^post_50 && Irql^0==Irql^post_50 && IsochDetachData^0==IsochDetachData^post_50 && IsochResourceData^post_51==IsochResourceData^post_50 && 0==ResourceIrp^post_50 && a2525^post_49==StackSize^post_50 && __rho_10_^0==__rho_10_^post_50 && __rho_11_^post_1==__rho_11_^post_50 && __rho_1_^0==__rho_1_^post_50 && __rho_2_^0==__rho_2_^post_50 && __rho_3_^0==__rho_3_^post_50 && __rho_4_^0==__rho_4_^post_50 && __rho_5_^0==__rho_5_^post_50 && __rho_666_^0==__rho_666_^post_50 && __rho_7_^0==__rho_7_^post_50 && __rho_8_^0==__rho_8_^post_50 && __rho_9_^0==__rho_9_^post_50 && a11^0==a11^post_50 && a1818^0==a1818^post_50 && a2525^post_49==a2525^post_50 && a2828^0==a2828^post_50 && a3131^0==a3131^post_50 && a3232^0==a3232^post_50 && a3434^0==a3434^post_50 && a3737^0==a3737^post_50 && a3838^0==a3838^post_50 && a4343^0==a4343^post_50 && a4545^0==a4545^post_50 && a77^0==a77^post_50 && b22^0==b22^post_50 && 0==b2626^post_50 && b2929^0==b2929^post_50 && b3333^0==b3333^post_50 && b3535^0==b3535^post_50 && i^0==i^post_50 && i___01313^0==i___01313^post_50 && i___01717^0==i___01717^post_50 && Irql^0==i___02020^post_50 && Irql^0==i___02424^post_50 && i___04747^0==i___04747^post_50 && i___099^0==i___099^post_50 && ioA^0==ioA^post_50 && ioR^0==ioR^post_50 && k1^0==k1^post_50 && k2^0==k2^post_50 && k3^0==k3^post_50 && 0==k4^post_50 && ntStatus^0==ntStatus^post_50 && pIrb^post_49==pIrb^post_50 && phi_io_compl^0==phi_io_compl^post_50 && phi_nSUC_ret^0==phi_nSUC_ret^post_50 && prevCancel^0==prevCancel^post_50 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_50 && 0==ret_IoAllocateIrp2727^post_50 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_50 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_50 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_50 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_50 && k5^post_50<=0 ], cost: 6+4*__rho_11_^post_1
    154: l2 -> l26 : BusResetIrp^0'=BusResetIrp^post_38, IsochResourceData^0'=IsochResourceData^post_51, ResourceIrp^0'=0, StackSize^0'=a2525^post_49, __rho_11_^0'=__rho_11_^post_1, __rho_12_^0'=k5^post_50, a2525^0'=a2525^post_49, a4343^0'=0, a4545^0'=BusResetIrp^post_38, b2626^0'=0, i___02020^0'=Irql^0, i___02424^0'=Irql^0, i___04040^0'=Irql^0, i___04747^0'=Irql^0, k4^0'=0, k5^0'=0, keA^0'=0, keR^0'=0, pIrb^0'=pIrb^post_49, phi_io_compl^0'=1, prevCancel^0'=0, ret_IoAllocateIrp2727^0'=0, ret_IoSetCancelRoutine4444^0'=0, [ k3^0<=0 && 1<=IsochResourceData^post_51 && __rho_11_^post_1>=1 && k5^post_50>=1 ], cost: 6+2*k5^post_50+4*__rho_11_^post_1
     57: l26 -> [35] : [ -2+ntStatus^0==0 ], cost: NONTERM
     70: l26 -> [35] : [ 3<=ntStatus^0 ], cost: NONTERM
     71: l26 -> [35] : [ 1+ntStatus^0<=2 ], cost: NONTERM
    125: l34 -> l2 : AsyncAddressData^0'=AsyncAddressData^post_52, BusResetIrp^0'=BusResetIrp^post_52, CromData^0'=CromData^post_52, DeviceObject^0'=DeviceObject^post_52, Irp^0'=Irp^post_52, Irql^0'=Irql^post_52, IsochDetachData^0'=IsochDetachData^post_52, IsochResourceData^0'=IsochResourceData^post_52, ResourceIrp^0'=ResourceIrp^post_52, StackSize^0'=StackSize^post_52, __rho_10_^0'=__rho_10_^post_15, __rho_11_^0'=__rho_11_^post_52, __rho_12_^0'=__rho_12_^post_52, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_52, __rho_3_^0'=__rho_3_^post_52, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, __rho_7_^0'=__rho_7_^post_52, __rho_8_^0'=__rho_8_^post_52, __rho_9_^0'=__rho_9_^post_52, a11^0'=a11^post_52, a1818^0'=a1818^post_52, a2525^0'=a2525^post_52, a2828^0'=a2828^post_52, a3131^0'=a3131^post_52, a3232^0'=a3232^post_52, a3434^0'=a3434^post_52, a3737^0'=a3737^post_52, a3838^0'=a3838^post_52, a4343^0'=a4343^post_52, a4545^0'=a4545^post_52, a77^0'=a77^post_52, b22^0'=b22^post_52, b2626^0'=b2626^post_52, b2929^0'=b2929^post_52, b3333^0'=b3333^post_52, b3535^0'=b3535^post_52, i^0'=i^post_52, i___01313^0'=Irql^post_52, i___01717^0'=i___01717^post_52, i___02020^0'=i___02020^post_52, i___02424^0'=i___02424^post_52, i___04040^0'=i___04040^post_52, i___04747^0'=i___04747^post_52, i___099^0'=Irql^post_52, ioA^0'=ioA^post_52, ioR^0'=ioR^post_52, k1^0'=__rho_5_^post_30, k2^0'=__rho_4_^post_28, k3^0'=__rho_10_^post_15, k4^0'=k4^post_52, k5^0'=k5^post_52, keA^0'=0, keR^0'=0, ntStatus^0'=0, pIrb^0'=pIrb^post_52, phi_io_compl^0'=phi_io_compl^post_52, phi_nSUC_ret^0'=phi_nSUC_ret^post_52, prevCancel^0'=prevCancel^post_52, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_52, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_52, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_52, ret_IoSetDeviceInterfaceState44^0'=0, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_52, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_52, [ AsyncAddressData^0==AsyncAddressData^post_53 && BusResetIrp^0==BusResetIrp^post_53 && CromData^0==CromData^post_53 && DeviceObject^0==DeviceObject^post_53 && Irp^0==Irp^post_53 && Irql^0==Irql^post_53 && IsochDetachData^0==IsochDetachData^post_53 && IsochResourceData^0==IsochResourceData^post_53 && ResourceIrp^0==ResourceIrp^post_53 && StackSize^0==StackSize^post_53 && __rho_10_^0==__rho_10_^post_53 && __rho_11_^0==__rho_11_^post_53 && __rho_12_^0==__rho_12_^post_53 && __rho_1_^0==__rho_1_^post_53 && __rho_2_^0==__rho_2_^post_53 && __rho_3_^0==__rho_3_^post_53 && __rho_4_^0==__rho_4_^post_53 && __rho_5_^0==__rho_5_^post_53 && __rho_666_^0==__rho_666_^post_53 && __rho_7_^0==__rho_7_^post_53 && __rho_8_^0==__rho_8_^post_53 && __rho_9_^0==__rho_9_^post_53 && a11^0==a11^post_53 && a1818^0==a1818^post_53 && a2525^0==a2525^post_53 && a2828^0==a2828^post_53 && a3131^0==a3131^post_53 && a3232^0==a3232^post_53 && a3434^0==a3434^post_53 && a3737^0==a3737^post_53 && a3838^0==a3838^post_53 && a4343^0==a4343^post_53 && a4545^0==a4545^post_53 && a77^0==a77^post_53 && b22^0==b22^post_53 && b2626^0==b2626^post_53 && b2929^0==b2929^post_53 && b3333^0==b3333^post_53 && b3535^0==b3535^post_53 && i^0==i^post_53 && i___01313^0==i___01313^post_53 && i___01717^0==i___01717^post_53 && i___02020^0==i___02020^post_53 && i___02424^0==i___02424^post_53 && i___04040^0==i___04040^post_53 && i___04747^0==i___04747^post_53 && i___099^0==i___099^post_53 && ioA^0==ioA^post_53 && ioR^0==ioR^post_53 && k1^0==k1^post_53 && k2^0==k2^post_53 && k3^0==k3^post_53 && k4^0==k4^post_53 && k5^0==k5^post_53 && keA^0==keA^post_53 && keR^0==keR^post_53 && ntStatus^0==ntStatus^post_53 && pIrb^0==pIrb^post_53 && phi_io_compl^0==phi_io_compl^post_53 && phi_nSUC_ret^0==phi_nSUC_ret^post_53 && prevCancel^0==prevCancel^post_53 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_53 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_53 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_53 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_53 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_53 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_53 && ioR^post_52==0 && ioA^post_52==ioR^post_52 && keR^post_52==ioA^post_52 && keA^post_52==keR^post_52 && phi_nSUC_ret^post_52==0 && phi_io_compl^post_52==0 && AsyncAddressData^post_53==AsyncAddressData^post_52 && BusResetIrp^post_53==BusResetIrp^post_52 && CromData^post_53==CromData^post_52 && DeviceObject^post_53==DeviceObject^post_52 && Irp^post_53==Irp^post_52 && Irql^post_53==Irql^post_52 && IsochDetachData^post_53==IsochDetachData^post_52 && IsochResourceData^post_53==IsochResourceData^post_52 && ResourceIrp^post_53==ResourceIrp^post_52 && StackSize^post_53==StackSize^post_52 && __rho_10_^post_53==__rho_10_^post_52 && __rho_11_^post_53==__rho_11_^post_52 && __rho_12_^post_53==__rho_12_^post_52 && __rho_2_^post_53==__rho_2_^post_52 && __rho_3_^post_53==__rho_3_^post_52 && __rho_4_^post_53==__rho_4_^post_52 && __rho_5_^post_53==__rho_5_^post_52 && __rho_7_^post_53==__rho_7_^post_52 && __rho_8_^post_53==__rho_8_^post_52 && __rho_9_^post_53==__rho_9_^post_52 && a11^post_53==a11^post_52 && a1818^post_53==a1818^post_52 && a2525^post_53==a2525^post_52 && a2828^post_53==a2828^post_52 && a3131^post_53==a3131^post_52 && a3232^post_53==a3232^post_52 && a3434^post_53==a3434^post_52 && a3737^post_53==a3737^post_52 && a3838^post_53==a3838^post_52 && a4343^post_53==a4343^post_52 && a4545^post_53==a4545^post_52 && a77^post_53==a77^post_52 && b22^post_53==b22^post_52 && b2626^post_53==b2626^post_52 && b2929^post_53==b2929^post_52 && b3333^post_53==b3333^post_52 && b3535^post_53==b3535^post_52 && i^post_53==i^post_52 && i___01313^post_53==i___01313^post_52 && i___01717^post_53==i___01717^post_52 && i___02020^post_53==i___02020^post_52 && i___02424^post_53==i___02424^post_52 && i___04040^post_53==i___04040^post_52 && i___04747^post_53==i___04747^post_52 && i___099^post_53==i___099^post_52 && k1^post_53==k1^post_52 && k2^post_53==k2^post_52 && k3^post_53==k3^post_52 && k4^post_53==k4^post_52 && k5^post_53==k5^post_52 && ntStatus^post_53==ntStatus^post_52 && pIrb^post_53==pIrb^post_52 && prevCancel^post_53==prevCancel^post_52 && ret_ExAllocatePool3030^post_53==ret_ExAllocatePool3030^post_52 && ret_IoAllocateIrp2727^post_53==ret_IoAllocateIrp2727^post_52 && ret_IoSetCancelRoutine4444^post_53==ret_IoSetCancelRoutine4444^post_52 && ret_IoSetDeviceInterfaceState44^post_53==ret_IoSetDeviceInterfaceState44^post_52 && ret_t1394Diag_PnpStopDevice33^post_53==ret_t1394Diag_PnpStopDevice33^post_52 && ret_t1394_SubmitIrpSynch3636^post_53==ret_t1394_SubmitIrpSynch3636^post_52 && __rho_1_^post_52<=0 && __rho_5_^post_30<=0 && __rho_4_^post_28<=0 ], cost: 8
    126: l34 -> l2 : AsyncAddressData^0'=AsyncAddressData^post_52, BusResetIrp^0'=BusResetIrp^post_52, CromData^0'=CromData^post_52, DeviceObject^0'=DeviceObject^post_52, Irp^0'=Irp^post_52, Irql^0'=Irql^post_52, IsochDetachData^0'=IsochDetachData^post_2, IsochResourceData^0'=IsochResourceData^post_52, ResourceIrp^0'=ResourceIrp^post_52, StackSize^0'=StackSize^post_52, __rho_10_^0'=__rho_10_^post_15, __rho_11_^0'=__rho_11_^post_52, __rho_12_^0'=__rho_12_^post_52, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_52, __rho_3_^0'=__rho_3_^post_52, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, __rho_7_^0'=__rho_7_^post_52, __rho_8_^0'=__rho_8_^post_52, __rho_9_^0'=__rho_9_^post_52, a11^0'=a11^post_52, a1818^0'=IsochDetachData^post_2, a2525^0'=a2525^post_52, a2828^0'=a2828^post_52, a3131^0'=a3131^post_52, a3232^0'=a3232^post_52, a3434^0'=a3434^post_52, a3737^0'=a3737^post_52, a3838^0'=a3838^post_52, a4343^0'=a4343^post_52, a4545^0'=a4545^post_52, a77^0'=a77^post_52, b22^0'=b22^post_52, b2626^0'=b2626^post_52, b2929^0'=b2929^post_52, b3333^0'=b3333^post_52, b3535^0'=b3535^post_52, i^0'=i^post_2, i___01313^0'=Irql^post_52, i___01717^0'=Irql^post_52, i___02020^0'=i___02020^post_52, i___02424^0'=i___02424^post_52, i___04040^0'=i___04040^post_52, i___04747^0'=i___04747^post_52, i___099^0'=Irql^post_52, ioA^0'=ioA^post_52, ioR^0'=ioR^post_52, k1^0'=__rho_5_^post_30, k2^0'=__rho_4_^post_28, k3^0'=0, k4^0'=k4^post_52, k5^0'=k5^post_52, keA^0'=0, keR^0'=0, ntStatus^0'=0, pIrb^0'=pIrb^post_52, phi_io_compl^0'=phi_io_compl^post_52, phi_nSUC_ret^0'=phi_nSUC_ret^post_52, prevCancel^0'=prevCancel^post_52, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_52, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_52, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_52, ret_IoSetDeviceInterfaceState44^0'=0, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_52, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_52, [ AsyncAddressData^0==AsyncAddressData^post_53 && BusResetIrp^0==BusResetIrp^post_53 && CromData^0==CromData^post_53 && DeviceObject^0==DeviceObject^post_53 && Irp^0==Irp^post_53 && Irql^0==Irql^post_53 && IsochDetachData^0==IsochDetachData^post_53 && IsochResourceData^0==IsochResourceData^post_53 && ResourceIrp^0==ResourceIrp^post_53 && StackSize^0==StackSize^post_53 && __rho_10_^0==__rho_10_^post_53 && __rho_11_^0==__rho_11_^post_53 && __rho_12_^0==__rho_12_^post_53 && __rho_1_^0==__rho_1_^post_53 && __rho_2_^0==__rho_2_^post_53 && __rho_3_^0==__rho_3_^post_53 && __rho_4_^0==__rho_4_^post_53 && __rho_5_^0==__rho_5_^post_53 && __rho_666_^0==__rho_666_^post_53 && __rho_7_^0==__rho_7_^post_53 && __rho_8_^0==__rho_8_^post_53 && __rho_9_^0==__rho_9_^post_53 && a11^0==a11^post_53 && a1818^0==a1818^post_53 && a2525^0==a2525^post_53 && a2828^0==a2828^post_53 && a3131^0==a3131^post_53 && a3232^0==a3232^post_53 && a3434^0==a3434^post_53 && a3737^0==a3737^post_53 && a3838^0==a3838^post_53 && a4343^0==a4343^post_53 && a4545^0==a4545^post_53 && a77^0==a77^post_53 && b22^0==b22^post_53 && b2626^0==b2626^post_53 && b2929^0==b2929^post_53 && b3333^0==b3333^post_53 && b3535^0==b3535^post_53 && i^0==i^post_53 && i___01313^0==i___01313^post_53 && i___01717^0==i___01717^post_53 && i___02020^0==i___02020^post_53 && i___02424^0==i___02424^post_53 && i___04040^0==i___04040^post_53 && i___04747^0==i___04747^post_53 && i___099^0==i___099^post_53 && ioA^0==ioA^post_53 && ioR^0==ioR^post_53 && k1^0==k1^post_53 && k2^0==k2^post_53 && k3^0==k3^post_53 && k4^0==k4^post_53 && k5^0==k5^post_53 && keA^0==keA^post_53 && keR^0==keR^post_53 && ntStatus^0==ntStatus^post_53 && pIrb^0==pIrb^post_53 && phi_io_compl^0==phi_io_compl^post_53 && phi_nSUC_ret^0==phi_nSUC_ret^post_53 && prevCancel^0==prevCancel^post_53 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_53 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_53 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_53 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_53 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_53 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_53 && ioR^post_52==0 && ioA^post_52==ioR^post_52 && keR^post_52==ioA^post_52 && keA^post_52==keR^post_52 && phi_nSUC_ret^post_52==0 && phi_io_compl^post_52==0 && AsyncAddressData^post_53==AsyncAddressData^post_52 && BusResetIrp^post_53==BusResetIrp^post_52 && CromData^post_53==CromData^post_52 && DeviceObject^post_53==DeviceObject^post_52 && Irp^post_53==Irp^post_52 && Irql^post_53==Irql^post_52 && IsochDetachData^post_53==IsochDetachData^post_52 && IsochResourceData^post_53==IsochResourceData^post_52 && ResourceIrp^post_53==ResourceIrp^post_52 && StackSize^post_53==StackSize^post_52 && __rho_10_^post_53==__rho_10_^post_52 && __rho_11_^post_53==__rho_11_^post_52 && __rho_12_^post_53==__rho_12_^post_52 && __rho_2_^post_53==__rho_2_^post_52 && __rho_3_^post_53==__rho_3_^post_52 && __rho_4_^post_53==__rho_4_^post_52 && __rho_5_^post_53==__rho_5_^post_52 && __rho_7_^post_53==__rho_7_^post_52 && __rho_8_^post_53==__rho_8_^post_52 && __rho_9_^post_53==__rho_9_^post_52 && a11^post_53==a11^post_52 && a1818^post_53==a1818^post_52 && a2525^post_53==a2525^post_52 && a2828^post_53==a2828^post_52 && a3131^post_53==a3131^post_52 && a3232^post_53==a3232^post_52 && a3434^post_53==a3434^post_52 && a3737^post_53==a3737^post_52 && a3838^post_53==a3838^post_52 && a4343^post_53==a4343^post_52 && a4545^post_53==a4545^post_52 && a77^post_53==a77^post_52 && b22^post_53==b22^post_52 && b2626^post_53==b2626^post_52 && b2929^post_53==b2929^post_52 && b3333^post_53==b3333^post_52 && b3535^post_53==b3535^post_52 && i^post_53==i^post_52 && i___01313^post_53==i___01313^post_52 && i___01717^post_53==i___01717^post_52 && i___02020^post_53==i___02020^post_52 && i___02424^post_53==i___02424^post_52 && i___04040^post_53==i___04040^post_52 && i___04747^post_53==i___04747^post_52 && i___099^post_53==i___099^post_52 && k1^post_53==k1^post_52 && k2^post_53==k2^post_52 && k3^post_53==k3^post_52 && k4^post_53==k4^post_52 && k5^post_53==k5^post_52 && ntStatus^post_53==ntStatus^post_52 && pIrb^post_53==pIrb^post_52 && prevCancel^post_53==prevCancel^post_52 && ret_ExAllocatePool3030^post_53==ret_ExAllocatePool3030^post_52 && ret_IoAllocateIrp2727^post_53==ret_IoAllocateIrp2727^post_52 && ret_IoSetCancelRoutine4444^post_53==ret_IoSetCancelRoutine4444^post_52 && ret_IoSetDeviceInterfaceState44^post_53==ret_IoSetDeviceInterfaceState44^post_52 && ret_t1394Diag_PnpStopDevice33^post_53==ret_t1394Diag_PnpStopDevice33^post_52 && ret_t1394_SubmitIrpSynch3636^post_53==ret_t1394_SubmitIrpSynch3636^post_52 && __rho_1_^post_52<=0 && __rho_5_^post_30<=0 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 ], cost: 8+2*__rho_10_^post_15
    127: l34 -> l2 : AsyncAddressData^0'=AsyncAddressData^post_14, BusResetIrp^0'=BusResetIrp^post_52, CromData^0'=CromData^post_52, DeviceObject^0'=DeviceObject^post_52, Irp^0'=Irp^post_52, Irql^0'=Irql^post_52, IsochDetachData^0'=IsochDetachData^post_52, IsochResourceData^0'=IsochResourceData^post_52, ResourceIrp^0'=ResourceIrp^post_52, StackSize^0'=StackSize^post_52, __rho_10_^0'=__rho_10_^post_15, __rho_11_^0'=__rho_11_^post_52, __rho_12_^0'=__rho_12_^post_52, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_52, __rho_3_^0'=__rho_3_^post_52, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, __rho_7_^0'=__rho_7_^post_14, __rho_8_^0'=__rho_8_^post_10, __rho_9_^0'=__rho_9_^post_7, a11^0'=a11^post_52, a1818^0'=a1818^post_52, a2525^0'=a2525^post_52, a2828^0'=a2828^post_52, a3131^0'=a3131^post_52, a3232^0'=a3232^post_52, a3434^0'=a3434^post_52, a3737^0'=a3737^post_52, a3838^0'=a3838^post_52, a4343^0'=a4343^post_52, a4545^0'=a4545^post_52, a77^0'=a77^post_52, b22^0'=b22^post_52, b2626^0'=b2626^post_52, b2929^0'=b2929^post_52, b3333^0'=b3333^post_52, b3535^0'=b3535^post_52, i^0'=i^post_52, i___01313^0'=Irql^post_52, i___01717^0'=i___01717^post_52, i___02020^0'=i___02020^post_52, i___02424^0'=i___02424^post_52, i___04040^0'=i___04040^post_52, i___04747^0'=i___04747^post_52, i___099^0'=Irql^post_52, ioA^0'=ioA^post_52, ioR^0'=ioR^post_52, k1^0'=__rho_5_^post_30, k2^0'=0, k3^0'=__rho_10_^post_15, k4^0'=k4^post_52, k5^0'=k5^post_52, keA^0'=0, keR^0'=0, ntStatus^0'=0, pIrb^0'=pIrb^post_52, phi_io_compl^0'=phi_io_compl^post_52, phi_nSUC_ret^0'=phi_nSUC_ret^post_52, prevCancel^0'=prevCancel^post_52, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_52, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_52, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_52, ret_IoSetDeviceInterfaceState44^0'=0, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_52, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_52, [ AsyncAddressData^0==AsyncAddressData^post_53 && BusResetIrp^0==BusResetIrp^post_53 && CromData^0==CromData^post_53 && DeviceObject^0==DeviceObject^post_53 && Irp^0==Irp^post_53 && Irql^0==Irql^post_53 && IsochDetachData^0==IsochDetachData^post_53 && IsochResourceData^0==IsochResourceData^post_53 && ResourceIrp^0==ResourceIrp^post_53 && StackSize^0==StackSize^post_53 && __rho_10_^0==__rho_10_^post_53 && __rho_11_^0==__rho_11_^post_53 && __rho_12_^0==__rho_12_^post_53 && __rho_1_^0==__rho_1_^post_53 && __rho_2_^0==__rho_2_^post_53 && __rho_3_^0==__rho_3_^post_53 && __rho_4_^0==__rho_4_^post_53 && __rho_5_^0==__rho_5_^post_53 && __rho_666_^0==__rho_666_^post_53 && __rho_7_^0==__rho_7_^post_53 && __rho_8_^0==__rho_8_^post_53 && __rho_9_^0==__rho_9_^post_53 && a11^0==a11^post_53 && a1818^0==a1818^post_53 && a2525^0==a2525^post_53 && a2828^0==a2828^post_53 && a3131^0==a3131^post_53 && a3232^0==a3232^post_53 && a3434^0==a3434^post_53 && a3737^0==a3737^post_53 && a3838^0==a3838^post_53 && a4343^0==a4343^post_53 && a4545^0==a4545^post_53 && a77^0==a77^post_53 && b22^0==b22^post_53 && b2626^0==b2626^post_53 && b2929^0==b2929^post_53 && b3333^0==b3333^post_53 && b3535^0==b3535^post_53 && i^0==i^post_53 && i___01313^0==i___01313^post_53 && i___01717^0==i___01717^post_53 && i___02020^0==i___02020^post_53 && i___02424^0==i___02424^post_53 && i___04040^0==i___04040^post_53 && i___04747^0==i___04747^post_53 && i___099^0==i___099^post_53 && ioA^0==ioA^post_53 && ioR^0==ioR^post_53 && k1^0==k1^post_53 && k2^0==k2^post_53 && k3^0==k3^post_53 && k4^0==k4^post_53 && k5^0==k5^post_53 && keA^0==keA^post_53 && keR^0==keR^post_53 && ntStatus^0==ntStatus^post_53 && pIrb^0==pIrb^post_53 && phi_io_compl^0==phi_io_compl^post_53 && phi_nSUC_ret^0==phi_nSUC_ret^post_53 && prevCancel^0==prevCancel^post_53 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_53 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_53 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_53 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_53 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_53 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_53 && ioR^post_52==0 && ioA^post_52==ioR^post_52 && keR^post_52==ioA^post_52 && keA^post_52==keR^post_52 && phi_nSUC_ret^post_52==0 && phi_io_compl^post_52==0 && AsyncAddressData^post_53==AsyncAddressData^post_52 && BusResetIrp^post_53==BusResetIrp^post_52 && CromData^post_53==CromData^post_52 && DeviceObject^post_53==DeviceObject^post_52 && Irp^post_53==Irp^post_52 && Irql^post_53==Irql^post_52 && IsochDetachData^post_53==IsochDetachData^post_52 && IsochResourceData^post_53==IsochResourceData^post_52 && ResourceIrp^post_53==ResourceIrp^post_52 && StackSize^post_53==StackSize^post_52 && __rho_10_^post_53==__rho_10_^post_52 && __rho_11_^post_53==__rho_11_^post_52 && __rho_12_^post_53==__rho_12_^post_52 && __rho_2_^post_53==__rho_2_^post_52 && __rho_3_^post_53==__rho_3_^post_52 && __rho_4_^post_53==__rho_4_^post_52 && __rho_5_^post_53==__rho_5_^post_52 && __rho_7_^post_53==__rho_7_^post_52 && __rho_8_^post_53==__rho_8_^post_52 && __rho_9_^post_53==__rho_9_^post_52 && a11^post_53==a11^post_52 && a1818^post_53==a1818^post_52 && a2525^post_53==a2525^post_52 && a2828^post_53==a2828^post_52 && a3131^post_53==a3131^post_52 && a3232^post_53==a3232^post_52 && a3434^post_53==a3434^post_52 && a3737^post_53==a3737^post_52 && a3838^post_53==a3838^post_52 && a4343^post_53==a4343^post_52 && a4545^post_53==a4545^post_52 && a77^post_53==a77^post_52 && b22^post_53==b22^post_52 && b2626^post_53==b2626^post_52 && b2929^post_53==b2929^post_52 && b3333^post_53==b3333^post_52 && b3535^post_53==b3535^post_52 && i^post_53==i^post_52 && i___01313^post_53==i___01313^post_52 && i___01717^post_53==i___01717^post_52 && i___02020^post_53==i___02020^post_52 && i___02424^post_53==i___02424^post_52 && i___04040^post_53==i___04040^post_52 && i___04747^post_53==i___04747^post_52 && i___099^post_53==i___099^post_52 && k1^post_53==k1^post_52 && k2^post_53==k2^post_52 && k3^post_53==k3^post_52 && k4^post_53==k4^post_52 && k5^post_53==k5^post_52 && ntStatus^post_53==ntStatus^post_52 && pIrb^post_53==pIrb^post_52 && prevCancel^post_53==prevCancel^post_52 && ret_ExAllocatePool3030^post_53==ret_ExAllocatePool3030^post_52 && ret_IoAllocateIrp2727^post_53==ret_IoAllocateIrp2727^post_52 && ret_IoSetCancelRoutine4444^post_53==ret_IoSetCancelRoutine4444^post_52 && ret_IoSetDeviceInterfaceState44^post_53==ret_IoSetDeviceInterfaceState44^post_52 && ret_t1394Diag_PnpStopDevice33^post_53==ret_t1394Diag_PnpStopDevice33^post_52 && ret_t1394_SubmitIrpSynch3636^post_53==ret_t1394_SubmitIrpSynch3636^post_52 && __rho_1_^post_52<=0 && __rho_5_^post_30<=0 && __rho_4_^post_28>=1 ], cost: 8+8*__rho_4_^post_28
    128: l34 -> l2 : AsyncAddressData^0'=AsyncAddressData^post_14, BusResetIrp^0'=BusResetIrp^post_52, CromData^0'=CromData^post_52, DeviceObject^0'=DeviceObject^post_52, Irp^0'=Irp^post_52, Irql^0'=Irql^post_52, IsochDetachData^0'=IsochDetachData^post_2, IsochResourceData^0'=IsochResourceData^post_52, ResourceIrp^0'=ResourceIrp^post_52, StackSize^0'=StackSize^post_52, __rho_10_^0'=__rho_10_^post_15, __rho_11_^0'=__rho_11_^post_52, __rho_12_^0'=__rho_12_^post_52, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_52, __rho_3_^0'=__rho_3_^post_52, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, __rho_7_^0'=__rho_7_^post_14, __rho_8_^0'=__rho_8_^post_10, __rho_9_^0'=__rho_9_^post_7, a11^0'=a11^post_52, a1818^0'=IsochDetachData^post_2, a2525^0'=a2525^post_52, a2828^0'=a2828^post_52, a3131^0'=a3131^post_52, a3232^0'=a3232^post_52, a3434^0'=a3434^post_52, a3737^0'=a3737^post_52, a3838^0'=a3838^post_52, a4343^0'=a4343^post_52, a4545^0'=a4545^post_52, a77^0'=a77^post_52, b22^0'=b22^post_52, b2626^0'=b2626^post_52, b2929^0'=b2929^post_52, b3333^0'=b3333^post_52, b3535^0'=b3535^post_52, i^0'=i^post_2, i___01313^0'=Irql^post_52, i___01717^0'=Irql^post_52, i___02020^0'=i___02020^post_52, i___02424^0'=i___02424^post_52, i___04040^0'=i___04040^post_52, i___04747^0'=i___04747^post_52, i___099^0'=Irql^post_52, ioA^0'=ioA^post_52, ioR^0'=ioR^post_52, k1^0'=__rho_5_^post_30, k2^0'=0, k3^0'=0, k4^0'=k4^post_52, k5^0'=k5^post_52, keA^0'=0, keR^0'=0, ntStatus^0'=0, pIrb^0'=pIrb^post_52, phi_io_compl^0'=phi_io_compl^post_52, phi_nSUC_ret^0'=phi_nSUC_ret^post_52, prevCancel^0'=prevCancel^post_52, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_52, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_52, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_52, ret_IoSetDeviceInterfaceState44^0'=0, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_52, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_52, [ AsyncAddressData^0==AsyncAddressData^post_53 && BusResetIrp^0==BusResetIrp^post_53 && CromData^0==CromData^post_53 && DeviceObject^0==DeviceObject^post_53 && Irp^0==Irp^post_53 && Irql^0==Irql^post_53 && IsochDetachData^0==IsochDetachData^post_53 && IsochResourceData^0==IsochResourceData^post_53 && ResourceIrp^0==ResourceIrp^post_53 && StackSize^0==StackSize^post_53 && __rho_10_^0==__rho_10_^post_53 && __rho_11_^0==__rho_11_^post_53 && __rho_12_^0==__rho_12_^post_53 && __rho_1_^0==__rho_1_^post_53 && __rho_2_^0==__rho_2_^post_53 && __rho_3_^0==__rho_3_^post_53 && __rho_4_^0==__rho_4_^post_53 && __rho_5_^0==__rho_5_^post_53 && __rho_666_^0==__rho_666_^post_53 && __rho_7_^0==__rho_7_^post_53 && __rho_8_^0==__rho_8_^post_53 && __rho_9_^0==__rho_9_^post_53 && a11^0==a11^post_53 && a1818^0==a1818^post_53 && a2525^0==a2525^post_53 && a2828^0==a2828^post_53 && a3131^0==a3131^post_53 && a3232^0==a3232^post_53 && a3434^0==a3434^post_53 && a3737^0==a3737^post_53 && a3838^0==a3838^post_53 && a4343^0==a4343^post_53 && a4545^0==a4545^post_53 && a77^0==a77^post_53 && b22^0==b22^post_53 && b2626^0==b2626^post_53 && b2929^0==b2929^post_53 && b3333^0==b3333^post_53 && b3535^0==b3535^post_53 && i^0==i^post_53 && i___01313^0==i___01313^post_53 && i___01717^0==i___01717^post_53 && i___02020^0==i___02020^post_53 && i___02424^0==i___02424^post_53 && i___04040^0==i___04040^post_53 && i___04747^0==i___04747^post_53 && i___099^0==i___099^post_53 && ioA^0==ioA^post_53 && ioR^0==ioR^post_53 && k1^0==k1^post_53 && k2^0==k2^post_53 && k3^0==k3^post_53 && k4^0==k4^post_53 && k5^0==k5^post_53 && keA^0==keA^post_53 && keR^0==keR^post_53 && ntStatus^0==ntStatus^post_53 && pIrb^0==pIrb^post_53 && phi_io_compl^0==phi_io_compl^post_53 && phi_nSUC_ret^0==phi_nSUC_ret^post_53 && prevCancel^0==prevCancel^post_53 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_53 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_53 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_53 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_53 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_53 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_53 && ioR^post_52==0 && ioA^post_52==ioR^post_52 && keR^post_52==ioA^post_52 && keA^post_52==keR^post_52 && phi_nSUC_ret^post_52==0 && phi_io_compl^post_52==0 && AsyncAddressData^post_53==AsyncAddressData^post_52 && BusResetIrp^post_53==BusResetIrp^post_52 && CromData^post_53==CromData^post_52 && DeviceObject^post_53==DeviceObject^post_52 && Irp^post_53==Irp^post_52 && Irql^post_53==Irql^post_52 && IsochDetachData^post_53==IsochDetachData^post_52 && IsochResourceData^post_53==IsochResourceData^post_52 && ResourceIrp^post_53==ResourceIrp^post_52 && StackSize^post_53==StackSize^post_52 && __rho_10_^post_53==__rho_10_^post_52 && __rho_11_^post_53==__rho_11_^post_52 && __rho_12_^post_53==__rho_12_^post_52 && __rho_2_^post_53==__rho_2_^post_52 && __rho_3_^post_53==__rho_3_^post_52 && __rho_4_^post_53==__rho_4_^post_52 && __rho_5_^post_53==__rho_5_^post_52 && __rho_7_^post_53==__rho_7_^post_52 && __rho_8_^post_53==__rho_8_^post_52 && __rho_9_^post_53==__rho_9_^post_52 && a11^post_53==a11^post_52 && a1818^post_53==a1818^post_52 && a2525^post_53==a2525^post_52 && a2828^post_53==a2828^post_52 && a3131^post_53==a3131^post_52 && a3232^post_53==a3232^post_52 && a3434^post_53==a3434^post_52 && a3737^post_53==a3737^post_52 && a3838^post_53==a3838^post_52 && a4343^post_53==a4343^post_52 && a4545^post_53==a4545^post_52 && a77^post_53==a77^post_52 && b22^post_53==b22^post_52 && b2626^post_53==b2626^post_52 && b2929^post_53==b2929^post_52 && b3333^post_53==b3333^post_52 && b3535^post_53==b3535^post_52 && i^post_53==i^post_52 && i___01313^post_53==i___01313^post_52 && i___01717^post_53==i___01717^post_52 && i___02020^post_53==i___02020^post_52 && i___02424^post_53==i___02424^post_52 && i___04040^post_53==i___04040^post_52 && i___04747^post_53==i___04747^post_52 && i___099^post_53==i___099^post_52 && k1^post_53==k1^post_52 && k2^post_53==k2^post_52 && k3^post_53==k3^post_52 && k4^post_53==k4^post_52 && k5^post_53==k5^post_52 && ntStatus^post_53==ntStatus^post_52 && pIrb^post_53==pIrb^post_52 && prevCancel^post_53==prevCancel^post_52 && ret_ExAllocatePool3030^post_53==ret_ExAllocatePool3030^post_52 && ret_IoAllocateIrp2727^post_53==ret_IoAllocateIrp2727^post_52 && ret_IoSetCancelRoutine4444^post_53==ret_IoSetCancelRoutine4444^post_52 && ret_IoSetDeviceInterfaceState44^post_53==ret_IoSetDeviceInterfaceState44^post_52 && ret_t1394Diag_PnpStopDevice33^post_53==ret_t1394Diag_PnpStopDevice33^post_52 && ret_t1394_SubmitIrpSynch3636^post_53==ret_t1394_SubmitIrpSynch3636^post_52 && __rho_1_^post_52<=0 && __rho_5_^post_30<=0 && __rho_4_^post_28>=1 && __rho_10_^post_15>=1 ], cost: 8+2*__rho_10_^post_15+8*__rho_4_^post_28
    129: l34 -> l2 : AsyncAddressData^0'=AsyncAddressData^post_52, BusResetIrp^0'=BusResetIrp^post_52, CromData^0'=CromData^post_52, DeviceObject^0'=DeviceObject^post_52, Irp^0'=Irp^post_52, Irql^0'=Irql^post_52, IsochDetachData^0'=IsochDetachData^post_52, IsochResourceData^0'=IsochResourceData^post_52, ResourceIrp^0'=ResourceIrp^post_52, StackSize^0'=StackSize^post_52, __rho_10_^0'=__rho_10_^post_15, __rho_11_^0'=__rho_11_^post_52, __rho_12_^0'=__rho_12_^post_52, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_52, __rho_3_^0'=__rho_3_^post_52, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, __rho_7_^0'=__rho_7_^post_52, __rho_8_^0'=__rho_8_^post_52, __rho_9_^0'=__rho_9_^post_52, a11^0'=DeviceObject^post_52, a1818^0'=a1818^post_52, a2525^0'=a2525^post_52, a2828^0'=a2828^post_52, a3131^0'=a3131^post_52, a3232^0'=a3232^post_52, a3434^0'=a3434^post_52, a3737^0'=a3737^post_52, a3838^0'=a3838^post_52, a4343^0'=a4343^post_52, a4545^0'=a4545^post_52, a77^0'=a77^post_52, b22^0'=Irp^post_52, b2626^0'=b2626^post_52, b2929^0'=b2929^post_52, b3333^0'=b3333^post_52, b3535^0'=b3535^post_52, i^0'=i^post_52, i___01313^0'=Irql^post_52, i___01717^0'=i___01717^post_52, i___02020^0'=i___02020^post_52, i___02424^0'=i___02424^post_52, i___04040^0'=i___04040^post_52, i___04747^0'=i___04747^post_52, i___099^0'=Irql^post_52, ioA^0'=ioA^post_52, ioR^0'=ioR^post_52, k1^0'=__rho_5_^post_30, k2^0'=__rho_4_^post_28, k3^0'=__rho_10_^post_15, k4^0'=k4^post_52, k5^0'=k5^post_52, keA^0'=0, keR^0'=0, ntStatus^0'=0, pIrb^0'=pIrb^post_52, phi_io_compl^0'=phi_io_compl^post_52, phi_nSUC_ret^0'=phi_nSUC_ret^post_52, prevCancel^0'=prevCancel^post_52, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_52, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_52, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_52, ret_IoSetDeviceInterfaceState44^0'=0, ret_t1394Diag_PnpStopDevice33^0'=0, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_52, [ AsyncAddressData^0==AsyncAddressData^post_53 && BusResetIrp^0==BusResetIrp^post_53 && CromData^0==CromData^post_53 && DeviceObject^0==DeviceObject^post_53 && Irp^0==Irp^post_53 && Irql^0==Irql^post_53 && IsochDetachData^0==IsochDetachData^post_53 && IsochResourceData^0==IsochResourceData^post_53 && ResourceIrp^0==ResourceIrp^post_53 && StackSize^0==StackSize^post_53 && __rho_10_^0==__rho_10_^post_53 && __rho_11_^0==__rho_11_^post_53 && __rho_12_^0==__rho_12_^post_53 && __rho_1_^0==__rho_1_^post_53 && __rho_2_^0==__rho_2_^post_53 && __rho_3_^0==__rho_3_^post_53 && __rho_4_^0==__rho_4_^post_53 && __rho_5_^0==__rho_5_^post_53 && __rho_666_^0==__rho_666_^post_53 && __rho_7_^0==__rho_7_^post_53 && __rho_8_^0==__rho_8_^post_53 && __rho_9_^0==__rho_9_^post_53 && a11^0==a11^post_53 && a1818^0==a1818^post_53 && a2525^0==a2525^post_53 && a2828^0==a2828^post_53 && a3131^0==a3131^post_53 && a3232^0==a3232^post_53 && a3434^0==a3434^post_53 && a3737^0==a3737^post_53 && a3838^0==a3838^post_53 && a4343^0==a4343^post_53 && a4545^0==a4545^post_53 && a77^0==a77^post_53 && b22^0==b22^post_53 && b2626^0==b2626^post_53 && b2929^0==b2929^post_53 && b3333^0==b3333^post_53 && b3535^0==b3535^post_53 && i^0==i^post_53 && i___01313^0==i___01313^post_53 && i___01717^0==i___01717^post_53 && i___02020^0==i___02020^post_53 && i___02424^0==i___02424^post_53 && i___04040^0==i___04040^post_53 && i___04747^0==i___04747^post_53 && i___099^0==i___099^post_53 && ioA^0==ioA^post_53 && ioR^0==ioR^post_53 && k1^0==k1^post_53 && k2^0==k2^post_53 && k3^0==k3^post_53 && k4^0==k4^post_53 && k5^0==k5^post_53 && keA^0==keA^post_53 && keR^0==keR^post_53 && ntStatus^0==ntStatus^post_53 && pIrb^0==pIrb^post_53 && phi_io_compl^0==phi_io_compl^post_53 && phi_nSUC_ret^0==phi_nSUC_ret^post_53 && prevCancel^0==prevCancel^post_53 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_53 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_53 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_53 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_53 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_53 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_53 && ioR^post_52==0 && ioA^post_52==ioR^post_52 && keR^post_52==ioA^post_52 && keA^post_52==keR^post_52 && phi_nSUC_ret^post_52==0 && phi_io_compl^post_52==0 && AsyncAddressData^post_53==AsyncAddressData^post_52 && BusResetIrp^post_53==BusResetIrp^post_52 && CromData^post_53==CromData^post_52 && DeviceObject^post_53==DeviceObject^post_52 && Irp^post_53==Irp^post_52 && Irql^post_53==Irql^post_52 && IsochDetachData^post_53==IsochDetachData^post_52 && IsochResourceData^post_53==IsochResourceData^post_52 && ResourceIrp^post_53==ResourceIrp^post_52 && StackSize^post_53==StackSize^post_52 && __rho_10_^post_53==__rho_10_^post_52 && __rho_11_^post_53==__rho_11_^post_52 && __rho_12_^post_53==__rho_12_^post_52 && __rho_2_^post_53==__rho_2_^post_52 && __rho_3_^post_53==__rho_3_^post_52 && __rho_4_^post_53==__rho_4_^post_52 && __rho_5_^post_53==__rho_5_^post_52 && __rho_7_^post_53==__rho_7_^post_52 && __rho_8_^post_53==__rho_8_^post_52 && __rho_9_^post_53==__rho_9_^post_52 && a11^post_53==a11^post_52 && a1818^post_53==a1818^post_52 && a2525^post_53==a2525^post_52 && a2828^post_53==a2828^post_52 && a3131^post_53==a3131^post_52 && a3232^post_53==a3232^post_52 && a3434^post_53==a3434^post_52 && a3737^post_53==a3737^post_52 && a3838^post_53==a3838^post_52 && a4343^post_53==a4343^post_52 && a4545^post_53==a4545^post_52 && a77^post_53==a77^post_52 && b22^post_53==b22^post_52 && b2626^post_53==b2626^post_52 && b2929^post_53==b2929^post_52 && b3333^post_53==b3333^post_52 && b3535^post_53==b3535^post_52 && i^post_53==i^post_52 && i___01313^post_53==i___01313^post_52 && i___01717^post_53==i___01717^post_52 && i___02020^post_53==i___02020^post_52 && i___02424^post_53==i___02424^post_52 && i___04040^post_53==i___04040^post_52 && i___04747^post_53==i___04747^post_52 && i___099^post_53==i___099^post_52 && k1^post_53==k1^post_52 && k2^post_53==k2^post_52 && k3^post_53==k3^post_52 && k4^post_53==k4^post_52 && k5^post_53==k5^post_52 && ntStatus^post_53==ntStatus^post_52 && pIrb^post_53==pIrb^post_52 && prevCancel^post_53==prevCancel^post_52 && ret_ExAllocatePool3030^post_53==ret_ExAllocatePool3030^post_52 && ret_IoAllocateIrp2727^post_53==ret_IoAllocateIrp2727^post_52 && ret_IoSetCancelRoutine4444^post_53==ret_IoSetCancelRoutine4444^post_52 && ret_IoSetDeviceInterfaceState44^post_53==ret_IoSetDeviceInterfaceState44^post_52 && ret_t1394Diag_PnpStopDevice33^post_53==ret_t1394Diag_PnpStopDevice33^post_52 && ret_t1394_SubmitIrpSynch3636^post_53==ret_t1394_SubmitIrpSynch3636^post_52 && 1<=__rho_1_^post_52 && __rho_5_^post_30<=0 && __rho_4_^post_28<=0 ], cost: 8
    130: l34 -> l2 : AsyncAddressData^0'=AsyncAddressData^post_52, BusResetIrp^0'=BusResetIrp^post_52, CromData^0'=CromData^post_52, DeviceObject^0'=DeviceObject^post_52, Irp^0'=Irp^post_52, Irql^0'=Irql^post_52, IsochDetachData^0'=IsochDetachData^post_2, IsochResourceData^0'=IsochResourceData^post_52, ResourceIrp^0'=ResourceIrp^post_52, StackSize^0'=StackSize^post_52, __rho_10_^0'=__rho_10_^post_15, __rho_11_^0'=__rho_11_^post_52, __rho_12_^0'=__rho_12_^post_52, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_52, __rho_3_^0'=__rho_3_^post_52, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, __rho_7_^0'=__rho_7_^post_52, __rho_8_^0'=__rho_8_^post_52, __rho_9_^0'=__rho_9_^post_52, a11^0'=DeviceObject^post_52, a1818^0'=IsochDetachData^post_2, a2525^0'=a2525^post_52, a2828^0'=a2828^post_52, a3131^0'=a3131^post_52, a3232^0'=a3232^post_52, a3434^0'=a3434^post_52, a3737^0'=a3737^post_52, a3838^0'=a3838^post_52, a4343^0'=a4343^post_52, a4545^0'=a4545^post_52, a77^0'=a77^post_52, b22^0'=Irp^post_52, b2626^0'=b2626^post_52, b2929^0'=b2929^post_52, b3333^0'=b3333^post_52, b3535^0'=b3535^post_52, i^0'=i^post_2, i___01313^0'=Irql^post_52, i___01717^0'=Irql^post_52, i___02020^0'=i___02020^post_52, i___02424^0'=i___02424^post_52, i___04040^0'=i___04040^post_52, i___04747^0'=i___04747^post_52, i___099^0'=Irql^post_52, ioA^0'=ioA^post_52, ioR^0'=ioR^post_52, k1^0'=__rho_5_^post_30, k2^0'=__rho_4_^post_28, k3^0'=0, k4^0'=k4^post_52, k5^0'=k5^post_52, keA^0'=0, keR^0'=0, ntStatus^0'=0, pIrb^0'=pIrb^post_52, phi_io_compl^0'=phi_io_compl^post_52, phi_nSUC_ret^0'=phi_nSUC_ret^post_52, prevCancel^0'=prevCancel^post_52, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_52, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_52, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_52, ret_IoSetDeviceInterfaceState44^0'=0, ret_t1394Diag_PnpStopDevice33^0'=0, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_52, [ AsyncAddressData^0==AsyncAddressData^post_53 && BusResetIrp^0==BusResetIrp^post_53 && CromData^0==CromData^post_53 && DeviceObject^0==DeviceObject^post_53 && Irp^0==Irp^post_53 && Irql^0==Irql^post_53 && IsochDetachData^0==IsochDetachData^post_53 && IsochResourceData^0==IsochResourceData^post_53 && ResourceIrp^0==ResourceIrp^post_53 && StackSize^0==StackSize^post_53 && __rho_10_^0==__rho_10_^post_53 && __rho_11_^0==__rho_11_^post_53 && __rho_12_^0==__rho_12_^post_53 && __rho_1_^0==__rho_1_^post_53 && __rho_2_^0==__rho_2_^post_53 && __rho_3_^0==__rho_3_^post_53 && __rho_4_^0==__rho_4_^post_53 && __rho_5_^0==__rho_5_^post_53 && __rho_666_^0==__rho_666_^post_53 && __rho_7_^0==__rho_7_^post_53 && __rho_8_^0==__rho_8_^post_53 && __rho_9_^0==__rho_9_^post_53 && a11^0==a11^post_53 && a1818^0==a1818^post_53 && a2525^0==a2525^post_53 && a2828^0==a2828^post_53 && a3131^0==a3131^post_53 && a3232^0==a3232^post_53 && a3434^0==a3434^post_53 && a3737^0==a3737^post_53 && a3838^0==a3838^post_53 && a4343^0==a4343^post_53 && a4545^0==a4545^post_53 && a77^0==a77^post_53 && b22^0==b22^post_53 && b2626^0==b2626^post_53 && b2929^0==b2929^post_53 && b3333^0==b3333^post_53 && b3535^0==b3535^post_53 && i^0==i^post_53 && i___01313^0==i___01313^post_53 && i___01717^0==i___01717^post_53 && i___02020^0==i___02020^post_53 && i___02424^0==i___02424^post_53 && i___04040^0==i___04040^post_53 && i___04747^0==i___04747^post_53 && i___099^0==i___099^post_53 && ioA^0==ioA^post_53 && ioR^0==ioR^post_53 && k1^0==k1^post_53 && k2^0==k2^post_53 && k3^0==k3^post_53 && k4^0==k4^post_53 && k5^0==k5^post_53 && keA^0==keA^post_53 && keR^0==keR^post_53 && ntStatus^0==ntStatus^post_53 && pIrb^0==pIrb^post_53 && phi_io_compl^0==phi_io_compl^post_53 && phi_nSUC_ret^0==phi_nSUC_ret^post_53 && prevCancel^0==prevCancel^post_53 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_53 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_53 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_53 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_53 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_53 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_53 && ioR^post_52==0 && ioA^post_52==ioR^post_52 && keR^post_52==ioA^post_52 && keA^post_52==keR^post_52 && phi_nSUC_ret^post_52==0 && phi_io_compl^post_52==0 && AsyncAddressData^post_53==AsyncAddressData^post_52 && BusResetIrp^post_53==BusResetIrp^post_52 && CromData^post_53==CromData^post_52 && DeviceObject^post_53==DeviceObject^post_52 && Irp^post_53==Irp^post_52 && Irql^post_53==Irql^post_52 && IsochDetachData^post_53==IsochDetachData^post_52 && IsochResourceData^post_53==IsochResourceData^post_52 && ResourceIrp^post_53==ResourceIrp^post_52 && StackSize^post_53==StackSize^post_52 && __rho_10_^post_53==__rho_10_^post_52 && __rho_11_^post_53==__rho_11_^post_52 && __rho_12_^post_53==__rho_12_^post_52 && __rho_2_^post_53==__rho_2_^post_52 && __rho_3_^post_53==__rho_3_^post_52 && __rho_4_^post_53==__rho_4_^post_52 && __rho_5_^post_53==__rho_5_^post_52 && __rho_7_^post_53==__rho_7_^post_52 && __rho_8_^post_53==__rho_8_^post_52 && __rho_9_^post_53==__rho_9_^post_52 && a11^post_53==a11^post_52 && a1818^post_53==a1818^post_52 && a2525^post_53==a2525^post_52 && a2828^post_53==a2828^post_52 && a3131^post_53==a3131^post_52 && a3232^post_53==a3232^post_52 && a3434^post_53==a3434^post_52 && a3737^post_53==a3737^post_52 && a3838^post_53==a3838^post_52 && a4343^post_53==a4343^post_52 && a4545^post_53==a4545^post_52 && a77^post_53==a77^post_52 && b22^post_53==b22^post_52 && b2626^post_53==b2626^post_52 && b2929^post_53==b2929^post_52 && b3333^post_53==b3333^post_52 && b3535^post_53==b3535^post_52 && i^post_53==i^post_52 && i___01313^post_53==i___01313^post_52 && i___01717^post_53==i___01717^post_52 && i___02020^post_53==i___02020^post_52 && i___02424^post_53==i___02424^post_52 && i___04040^post_53==i___04040^post_52 && i___04747^post_53==i___04747^post_52 && i___099^post_53==i___099^post_52 && k1^post_53==k1^post_52 && k2^post_53==k2^post_52 && k3^post_53==k3^post_52 && k4^post_53==k4^post_52 && k5^post_53==k5^post_52 && ntStatus^post_53==ntStatus^post_52 && pIrb^post_53==pIrb^post_52 && prevCancel^post_53==prevCancel^post_52 && ret_ExAllocatePool3030^post_53==ret_ExAllocatePool3030^post_52 && ret_IoAllocateIrp2727^post_53==ret_IoAllocateIrp2727^post_52 && ret_IoSetCancelRoutine4444^post_53==ret_IoSetCancelRoutine4444^post_52 && ret_IoSetDeviceInterfaceState44^post_53==ret_IoSetDeviceInterfaceState44^post_52 && ret_t1394Diag_PnpStopDevice33^post_53==ret_t1394Diag_PnpStopDevice33^post_52 && ret_t1394_SubmitIrpSynch3636^post_53==ret_t1394_SubmitIrpSynch3636^post_52 && 1<=__rho_1_^post_52 && __rho_5_^post_30<=0 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 ], cost: 8+2*__rho_10_^post_15
    131: l34 -> l2 : AsyncAddressData^0'=AsyncAddressData^post_14, BusResetIrp^0'=BusResetIrp^post_52, CromData^0'=CromData^post_52, DeviceObject^0'=DeviceObject^post_52, Irp^0'=Irp^post_52, Irql^0'=Irql^post_52, IsochDetachData^0'=IsochDetachData^post_52, IsochResourceData^0'=IsochResourceData^post_52, ResourceIrp^0'=ResourceIrp^post_52, StackSize^0'=StackSize^post_52, __rho_10_^0'=__rho_10_^post_15, __rho_11_^0'=__rho_11_^post_52, __rho_12_^0'=__rho_12_^post_52, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_52, __rho_3_^0'=__rho_3_^post_52, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, __rho_7_^0'=__rho_7_^post_14, __rho_8_^0'=__rho_8_^post_10, __rho_9_^0'=__rho_9_^post_7, a11^0'=DeviceObject^post_52, a1818^0'=a1818^post_52, a2525^0'=a2525^post_52, a2828^0'=a2828^post_52, a3131^0'=a3131^post_52, a3232^0'=a3232^post_52, a3434^0'=a3434^post_52, a3737^0'=a3737^post_52, a3838^0'=a3838^post_52, a4343^0'=a4343^post_52, a4545^0'=a4545^post_52, a77^0'=a77^post_52, b22^0'=Irp^post_52, b2626^0'=b2626^post_52, b2929^0'=b2929^post_52, b3333^0'=b3333^post_52, b3535^0'=b3535^post_52, i^0'=i^post_52, i___01313^0'=Irql^post_52, i___01717^0'=i___01717^post_52, i___02020^0'=i___02020^post_52, i___02424^0'=i___02424^post_52, i___04040^0'=i___04040^post_52, i___04747^0'=i___04747^post_52, i___099^0'=Irql^post_52, ioA^0'=ioA^post_52, ioR^0'=ioR^post_52, k1^0'=__rho_5_^post_30, k2^0'=0, k3^0'=__rho_10_^post_15, k4^0'=k4^post_52, k5^0'=k5^post_52, keA^0'=0, keR^0'=0, ntStatus^0'=0, pIrb^0'=pIrb^post_52, phi_io_compl^0'=phi_io_compl^post_52, phi_nSUC_ret^0'=phi_nSUC_ret^post_52, prevCancel^0'=prevCancel^post_52, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_52, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_52, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_52, ret_IoSetDeviceInterfaceState44^0'=0, ret_t1394Diag_PnpStopDevice33^0'=0, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_52, [ AsyncAddressData^0==AsyncAddressData^post_53 && BusResetIrp^0==BusResetIrp^post_53 && CromData^0==CromData^post_53 && DeviceObject^0==DeviceObject^post_53 && Irp^0==Irp^post_53 && Irql^0==Irql^post_53 && IsochDetachData^0==IsochDetachData^post_53 && IsochResourceData^0==IsochResourceData^post_53 && ResourceIrp^0==ResourceIrp^post_53 && StackSize^0==StackSize^post_53 && __rho_10_^0==__rho_10_^post_53 && __rho_11_^0==__rho_11_^post_53 && __rho_12_^0==__rho_12_^post_53 && __rho_1_^0==__rho_1_^post_53 && __rho_2_^0==__rho_2_^post_53 && __rho_3_^0==__rho_3_^post_53 && __rho_4_^0==__rho_4_^post_53 && __rho_5_^0==__rho_5_^post_53 && __rho_666_^0==__rho_666_^post_53 && __rho_7_^0==__rho_7_^post_53 && __rho_8_^0==__rho_8_^post_53 && __rho_9_^0==__rho_9_^post_53 && a11^0==a11^post_53 && a1818^0==a1818^post_53 && a2525^0==a2525^post_53 && a2828^0==a2828^post_53 && a3131^0==a3131^post_53 && a3232^0==a3232^post_53 && a3434^0==a3434^post_53 && a3737^0==a3737^post_53 && a3838^0==a3838^post_53 && a4343^0==a4343^post_53 && a4545^0==a4545^post_53 && a77^0==a77^post_53 && b22^0==b22^post_53 && b2626^0==b2626^post_53 && b2929^0==b2929^post_53 && b3333^0==b3333^post_53 && b3535^0==b3535^post_53 && i^0==i^post_53 && i___01313^0==i___01313^post_53 && i___01717^0==i___01717^post_53 && i___02020^0==i___02020^post_53 && i___02424^0==i___02424^post_53 && i___04040^0==i___04040^post_53 && i___04747^0==i___04747^post_53 && i___099^0==i___099^post_53 && ioA^0==ioA^post_53 && ioR^0==ioR^post_53 && k1^0==k1^post_53 && k2^0==k2^post_53 && k3^0==k3^post_53 && k4^0==k4^post_53 && k5^0==k5^post_53 && keA^0==keA^post_53 && keR^0==keR^post_53 && ntStatus^0==ntStatus^post_53 && pIrb^0==pIrb^post_53 && phi_io_compl^0==phi_io_compl^post_53 && phi_nSUC_ret^0==phi_nSUC_ret^post_53 && prevCancel^0==prevCancel^post_53 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_53 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_53 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_53 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_53 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_53 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_53 && ioR^post_52==0 && ioA^post_52==ioR^post_52 && keR^post_52==ioA^post_52 && keA^post_52==keR^post_52 && phi_nSUC_ret^post_52==0 && phi_io_compl^post_52==0 && AsyncAddressData^post_53==AsyncAddressData^post_52 && BusResetIrp^post_53==BusResetIrp^post_52 && CromData^post_53==CromData^post_52 && DeviceObject^post_53==DeviceObject^post_52 && Irp^post_53==Irp^post_52 && Irql^post_53==Irql^post_52 && IsochDetachData^post_53==IsochDetachData^post_52 && IsochResourceData^post_53==IsochResourceData^post_52 && ResourceIrp^post_53==ResourceIrp^post_52 && StackSize^post_53==StackSize^post_52 && __rho_10_^post_53==__rho_10_^post_52 && __rho_11_^post_53==__rho_11_^post_52 && __rho_12_^post_53==__rho_12_^post_52 && __rho_2_^post_53==__rho_2_^post_52 && __rho_3_^post_53==__rho_3_^post_52 && __rho_4_^post_53==__rho_4_^post_52 && __rho_5_^post_53==__rho_5_^post_52 && __rho_7_^post_53==__rho_7_^post_52 && __rho_8_^post_53==__rho_8_^post_52 && __rho_9_^post_53==__rho_9_^post_52 && a11^post_53==a11^post_52 && a1818^post_53==a1818^post_52 && a2525^post_53==a2525^post_52 && a2828^post_53==a2828^post_52 && a3131^post_53==a3131^post_52 && a3232^post_53==a3232^post_52 && a3434^post_53==a3434^post_52 && a3737^post_53==a3737^post_52 && a3838^post_53==a3838^post_52 && a4343^post_53==a4343^post_52 && a4545^post_53==a4545^post_52 && a77^post_53==a77^post_52 && b22^post_53==b22^post_52 && b2626^post_53==b2626^post_52 && b2929^post_53==b2929^post_52 && b3333^post_53==b3333^post_52 && b3535^post_53==b3535^post_52 && i^post_53==i^post_52 && i___01313^post_53==i___01313^post_52 && i___01717^post_53==i___01717^post_52 && i___02020^post_53==i___02020^post_52 && i___02424^post_53==i___02424^post_52 && i___04040^post_53==i___04040^post_52 && i___04747^post_53==i___04747^post_52 && i___099^post_53==i___099^post_52 && k1^post_53==k1^post_52 && k2^post_53==k2^post_52 && k3^post_53==k3^post_52 && k4^post_53==k4^post_52 && k5^post_53==k5^post_52 && ntStatus^post_53==ntStatus^post_52 && pIrb^post_53==pIrb^post_52 && prevCancel^post_53==prevCancel^post_52 && ret_ExAllocatePool3030^post_53==ret_ExAllocatePool3030^post_52 && ret_IoAllocateIrp2727^post_53==ret_IoAllocateIrp2727^post_52 && ret_IoSetCancelRoutine4444^post_53==ret_IoSetCancelRoutine4444^post_52 && ret_IoSetDeviceInterfaceState44^post_53==ret_IoSetDeviceInterfaceState44^post_52 && ret_t1394Diag_PnpStopDevice33^post_53==ret_t1394Diag_PnpStopDevice33^post_52 && ret_t1394_SubmitIrpSynch3636^post_53==ret_t1394_SubmitIrpSynch3636^post_52 && 1<=__rho_1_^post_52 && __rho_5_^post_30<=0 && __rho_4_^post_28>=1 ], cost: 8+8*__rho_4_^post_28
    132: l34 -> l2 : AsyncAddressData^0'=AsyncAddressData^post_14, BusResetIrp^0'=BusResetIrp^post_52, CromData^0'=CromData^post_52, DeviceObject^0'=DeviceObject^post_52, Irp^0'=Irp^post_52, Irql^0'=Irql^post_52, IsochDetachData^0'=IsochDetachData^post_2, IsochResourceData^0'=IsochResourceData^post_52, ResourceIrp^0'=ResourceIrp^post_52, StackSize^0'=StackSize^post_52, __rho_10_^0'=__rho_10_^post_15, __rho_11_^0'=__rho_11_^post_52, __rho_12_^0'=__rho_12_^post_52, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_52, __rho_3_^0'=__rho_3_^post_52, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, __rho_7_^0'=__rho_7_^post_14, __rho_8_^0'=__rho_8_^post_10, __rho_9_^0'=__rho_9_^post_7, a11^0'=DeviceObject^post_52, a1818^0'=IsochDetachData^post_2, a2525^0'=a2525^post_52, a2828^0'=a2828^post_52, a3131^0'=a3131^post_52, a3232^0'=a3232^post_52, a3434^0'=a3434^post_52, a3737^0'=a3737^post_52, a3838^0'=a3838^post_52, a4343^0'=a4343^post_52, a4545^0'=a4545^post_52, a77^0'=a77^post_52, b22^0'=Irp^post_52, b2626^0'=b2626^post_52, b2929^0'=b2929^post_52, b3333^0'=b3333^post_52, b3535^0'=b3535^post_52, i^0'=i^post_2, i___01313^0'=Irql^post_52, i___01717^0'=Irql^post_52, i___02020^0'=i___02020^post_52, i___02424^0'=i___02424^post_52, i___04040^0'=i___04040^post_52, i___04747^0'=i___04747^post_52, i___099^0'=Irql^post_52, ioA^0'=ioA^post_52, ioR^0'=ioR^post_52, k1^0'=__rho_5_^post_30, k2^0'=0, k3^0'=0, k4^0'=k4^post_52, k5^0'=k5^post_52, keA^0'=0, keR^0'=0, ntStatus^0'=0, pIrb^0'=pIrb^post_52, phi_io_compl^0'=phi_io_compl^post_52, phi_nSUC_ret^0'=phi_nSUC_ret^post_52, prevCancel^0'=prevCancel^post_52, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_52, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_52, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_52, ret_IoSetDeviceInterfaceState44^0'=0, ret_t1394Diag_PnpStopDevice33^0'=0, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_52, [ AsyncAddressData^0==AsyncAddressData^post_53 && BusResetIrp^0==BusResetIrp^post_53 && CromData^0==CromData^post_53 && DeviceObject^0==DeviceObject^post_53 && Irp^0==Irp^post_53 && Irql^0==Irql^post_53 && IsochDetachData^0==IsochDetachData^post_53 && IsochResourceData^0==IsochResourceData^post_53 && ResourceIrp^0==ResourceIrp^post_53 && StackSize^0==StackSize^post_53 && __rho_10_^0==__rho_10_^post_53 && __rho_11_^0==__rho_11_^post_53 && __rho_12_^0==__rho_12_^post_53 && __rho_1_^0==__rho_1_^post_53 && __rho_2_^0==__rho_2_^post_53 && __rho_3_^0==__rho_3_^post_53 && __rho_4_^0==__rho_4_^post_53 && __rho_5_^0==__rho_5_^post_53 && __rho_666_^0==__rho_666_^post_53 && __rho_7_^0==__rho_7_^post_53 && __rho_8_^0==__rho_8_^post_53 && __rho_9_^0==__rho_9_^post_53 && a11^0==a11^post_53 && a1818^0==a1818^post_53 && a2525^0==a2525^post_53 && a2828^0==a2828^post_53 && a3131^0==a3131^post_53 && a3232^0==a3232^post_53 && a3434^0==a3434^post_53 && a3737^0==a3737^post_53 && a3838^0==a3838^post_53 && a4343^0==a4343^post_53 && a4545^0==a4545^post_53 && a77^0==a77^post_53 && b22^0==b22^post_53 && b2626^0==b2626^post_53 && b2929^0==b2929^post_53 && b3333^0==b3333^post_53 && b3535^0==b3535^post_53 && i^0==i^post_53 && i___01313^0==i___01313^post_53 && i___01717^0==i___01717^post_53 && i___02020^0==i___02020^post_53 && i___02424^0==i___02424^post_53 && i___04040^0==i___04040^post_53 && i___04747^0==i___04747^post_53 && i___099^0==i___099^post_53 && ioA^0==ioA^post_53 && ioR^0==ioR^post_53 && k1^0==k1^post_53 && k2^0==k2^post_53 && k3^0==k3^post_53 && k4^0==k4^post_53 && k5^0==k5^post_53 && keA^0==keA^post_53 && keR^0==keR^post_53 && ntStatus^0==ntStatus^post_53 && pIrb^0==pIrb^post_53 && phi_io_compl^0==phi_io_compl^post_53 && phi_nSUC_ret^0==phi_nSUC_ret^post_53 && prevCancel^0==prevCancel^post_53 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_53 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_53 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_53 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_53 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_53 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_53 && ioR^post_52==0 && ioA^post_52==ioR^post_52 && keR^post_52==ioA^post_52 && keA^post_52==keR^post_52 && phi_nSUC_ret^post_52==0 && phi_io_compl^post_52==0 && AsyncAddressData^post_53==AsyncAddressData^post_52 && BusResetIrp^post_53==BusResetIrp^post_52 && CromData^post_53==CromData^post_52 && DeviceObject^post_53==DeviceObject^post_52 && Irp^post_53==Irp^post_52 && Irql^post_53==Irql^post_52 && IsochDetachData^post_53==IsochDetachData^post_52 && IsochResourceData^post_53==IsochResourceData^post_52 && ResourceIrp^post_53==ResourceIrp^post_52 && StackSize^post_53==StackSize^post_52 && __rho_10_^post_53==__rho_10_^post_52 && __rho_11_^post_53==__rho_11_^post_52 && __rho_12_^post_53==__rho_12_^post_52 && __rho_2_^post_53==__rho_2_^post_52 && __rho_3_^post_53==__rho_3_^post_52 && __rho_4_^post_53==__rho_4_^post_52 && __rho_5_^post_53==__rho_5_^post_52 && __rho_7_^post_53==__rho_7_^post_52 && __rho_8_^post_53==__rho_8_^post_52 && __rho_9_^post_53==__rho_9_^post_52 && a11^post_53==a11^post_52 && a1818^post_53==a1818^post_52 && a2525^post_53==a2525^post_52 && a2828^post_53==a2828^post_52 && a3131^post_53==a3131^post_52 && a3232^post_53==a3232^post_52 && a3434^post_53==a3434^post_52 && a3737^post_53==a3737^post_52 && a3838^post_53==a3838^post_52 && a4343^post_53==a4343^post_52 && a4545^post_53==a4545^post_52 && a77^post_53==a77^post_52 && b22^post_53==b22^post_52 && b2626^post_53==b2626^post_52 && b2929^post_53==b2929^post_52 && b3333^post_53==b3333^post_52 && b3535^post_53==b3535^post_52 && i^post_53==i^post_52 && i___01313^post_53==i___01313^post_52 && i___01717^post_53==i___01717^post_52 && i___02020^post_53==i___02020^post_52 && i___02424^post_53==i___02424^post_52 && i___04040^post_53==i___04040^post_52 && i___04747^post_53==i___04747^post_52 && i___099^post_53==i___099^post_52 && k1^post_53==k1^post_52 && k2^post_53==k2^post_52 && k3^post_53==k3^post_52 && k4^post_53==k4^post_52 && k5^post_53==k5^post_52 && ntStatus^post_53==ntStatus^post_52 && pIrb^post_53==pIrb^post_52 && prevCancel^post_53==prevCancel^post_52 && ret_ExAllocatePool3030^post_53==ret_ExAllocatePool3030^post_52 && ret_IoAllocateIrp2727^post_53==ret_IoAllocateIrp2727^post_52 && ret_IoSetCancelRoutine4444^post_53==ret_IoSetCancelRoutine4444^post_52 && ret_IoSetDeviceInterfaceState44^post_53==ret_IoSetDeviceInterfaceState44^post_52 && ret_t1394Diag_PnpStopDevice33^post_53==ret_t1394Diag_PnpStopDevice33^post_52 && ret_t1394_SubmitIrpSynch3636^post_53==ret_t1394_SubmitIrpSynch3636^post_52 && 1<=__rho_1_^post_52 && __rho_5_^post_30<=0 && __rho_4_^post_28>=1 && __rho_10_^post_15>=1 ], cost: 8+2*__rho_10_^post_15+8*__rho_4_^post_28
    133: l34 -> l2 : CromData^0'=CromData^post_27, __rho_10_^0'=__rho_10_^post_15, __rho_1_^0'=__rho_1_^post_52, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, i___01313^0'=Irql^0, i___099^0'=Irql^0, ioA^0'=0, ioR^0'=0, k1^0'=0, k2^0'=__rho_4_^post_28, k3^0'=__rho_10_^post_15, keA^0'=0, keR^0'=0, ntStatus^0'=0, phi_io_compl^0'=0, phi_nSUC_ret^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, [ __rho_1_^post_52<=0 && CromData^post_27<=0 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 ], cost: 8+3*__rho_5_^post_30
    134: l34 -> l2 : CromData^0'=CromData^post_27, IsochDetachData^0'=IsochDetachData^post_2, __rho_10_^0'=__rho_10_^post_15, __rho_1_^0'=__rho_1_^post_52, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, a1818^0'=IsochDetachData^post_2, i^0'=i^post_2, i___01313^0'=Irql^0, i___01717^0'=Irql^0, i___099^0'=Irql^0, ioA^0'=0, ioR^0'=0, k1^0'=0, k2^0'=__rho_4_^post_28, k3^0'=0, keA^0'=0, keR^0'=0, ntStatus^0'=0, phi_io_compl^0'=0, phi_nSUC_ret^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, [ __rho_1_^post_52<=0 && CromData^post_27<=0 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 ], cost: 8+2*__rho_10_^post_15+3*__rho_5_^post_30
    135: l34 -> l2 : AsyncAddressData^0'=AsyncAddressData^post_14, CromData^0'=CromData^post_27, __rho_10_^0'=__rho_10_^post_15, __rho_1_^0'=__rho_1_^post_52, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, __rho_7_^0'=__rho_7_^post_14, __rho_8_^0'=__rho_8_^post_10, __rho_9_^0'=__rho_9_^post_7, i___01313^0'=Irql^0, i___099^0'=Irql^0, ioA^0'=0, ioR^0'=0, k1^0'=0, k2^0'=0, k3^0'=__rho_10_^post_15, keA^0'=0, keR^0'=0, ntStatus^0'=0, phi_io_compl^0'=0, phi_nSUC_ret^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, [ __rho_1_^post_52<=0 && CromData^post_27<=0 && __rho_5_^post_30>=1 && __rho_4_^post_28>=1 ], cost: 8+3*__rho_5_^post_30+8*__rho_4_^post_28
    136: l34 -> l2 : AsyncAddressData^0'=AsyncAddressData^post_14, CromData^0'=CromData^post_27, IsochDetachData^0'=IsochDetachData^post_2, __rho_10_^0'=__rho_10_^post_15, __rho_1_^0'=__rho_1_^post_52, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, __rho_7_^0'=__rho_7_^post_14, __rho_8_^0'=__rho_8_^post_10, __rho_9_^0'=__rho_9_^post_7, a1818^0'=IsochDetachData^post_2, i^0'=i^post_2, i___01313^0'=Irql^0, i___01717^0'=Irql^0, i___099^0'=Irql^0, ioA^0'=0, ioR^0'=0, k1^0'=0, k2^0'=0, k3^0'=0, keA^0'=0, keR^0'=0, ntStatus^0'=0, phi_io_compl^0'=0, phi_nSUC_ret^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, [ __rho_1_^post_52<=0 && CromData^post_27<=0 && __rho_5_^post_30>=1 && __rho_4_^post_28>=1 && __rho_10_^post_15>=1 ], cost: 8+2*__rho_10_^post_15+3*__rho_5_^post_30+8*__rho_4_^post_28
    137: l34 -> l2 : CromData^0'=CromData^post_27, __rho_10_^0'=__rho_10_^post_15, __rho_1_^0'=__rho_1_^post_52, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, a11^0'=DeviceObject^0, b22^0'=Irp^0, i___01313^0'=Irql^0, i___099^0'=Irql^0, ioA^0'=0, ioR^0'=0, k1^0'=0, k2^0'=__rho_4_^post_28, k3^0'=__rho_10_^post_15, keA^0'=0, keR^0'=0, ntStatus^0'=0, phi_io_compl^0'=0, phi_nSUC_ret^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, ret_t1394Diag_PnpStopDevice33^0'=0, [ 1<=__rho_1_^post_52 && CromData^post_27<=0 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 ], cost: 8+3*__rho_5_^post_30
    138: l34 -> l2 : CromData^0'=CromData^post_27, IsochDetachData^0'=IsochDetachData^post_2, __rho_10_^0'=__rho_10_^post_15, __rho_1_^0'=__rho_1_^post_52, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, a11^0'=DeviceObject^0, a1818^0'=IsochDetachData^post_2, b22^0'=Irp^0, i^0'=i^post_2, i___01313^0'=Irql^0, i___01717^0'=Irql^0, i___099^0'=Irql^0, ioA^0'=0, ioR^0'=0, k1^0'=0, k2^0'=__rho_4_^post_28, k3^0'=0, keA^0'=0, keR^0'=0, ntStatus^0'=0, phi_io_compl^0'=0, phi_nSUC_ret^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, ret_t1394Diag_PnpStopDevice33^0'=0, [ 1<=__rho_1_^post_52 && CromData^post_27<=0 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 ], cost: 8+2*__rho_10_^post_15+3*__rho_5_^post_30
    139: l34 -> l2 : AsyncAddressData^0'=AsyncAddressData^post_14, CromData^0'=CromData^post_27, __rho_10_^0'=__rho_10_^post_15, __rho_1_^0'=__rho_1_^post_52, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, __rho_7_^0'=__rho_7_^post_14, __rho_8_^0'=__rho_8_^post_10, __rho_9_^0'=__rho_9_^post_7, a11^0'=DeviceObject^0, b22^0'=Irp^0, i___01313^0'=Irql^0, i___099^0'=Irql^0, ioA^0'=0, ioR^0'=0, k1^0'=0, k2^0'=0, k3^0'=__rho_10_^post_15, keA^0'=0, keR^0'=0, ntStatus^0'=0, phi_io_compl^0'=0, phi_nSUC_ret^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, ret_t1394Diag_PnpStopDevice33^0'=0, [ 1<=__rho_1_^post_52 && CromData^post_27<=0 && __rho_5_^post_30>=1 && __rho_4_^post_28>=1 ], cost: 8+3*__rho_5_^post_30+8*__rho_4_^post_28
    140: l34 -> l2 : AsyncAddressData^0'=AsyncAddressData^post_14, CromData^0'=CromData^post_27, IsochDetachData^0'=IsochDetachData^post_2, __rho_10_^0'=__rho_10_^post_15, __rho_1_^0'=__rho_1_^post_52, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, __rho_7_^0'=__rho_7_^post_14, __rho_8_^0'=__rho_8_^post_10, __rho_9_^0'=__rho_9_^post_7, a11^0'=DeviceObject^0, a1818^0'=IsochDetachData^post_2, b22^0'=Irp^0, i^0'=i^post_2, i___01313^0'=Irql^0, i___01717^0'=Irql^0, i___099^0'=Irql^0, ioA^0'=0, ioR^0'=0, k1^0'=0, k2^0'=0, k3^0'=0, keA^0'=0, keR^0'=0, ntStatus^0'=0, phi_io_compl^0'=0, phi_nSUC_ret^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, ret_t1394Diag_PnpStopDevice33^0'=0, [ 1<=__rho_1_^post_52 && CromData^post_27<=0 && __rho_5_^post_30>=1 && __rho_4_^post_28>=1 && __rho_10_^post_15>=1 ], cost: 8+2*__rho_10_^post_15+3*__rho_5_^post_30+8*__rho_4_^post_28
    141: l34 -> l2 : CromData^0'=CromData^post_27, __rho_10_^0'=__rho_10_^post_15, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_26, __rho_3_^0'=__rho_3_^post_21, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, a77^0'=CromData^post_27, i___01313^0'=Irql^0, i___099^0'=Irql^0, ioA^0'=0, ioR^0'=0, k1^0'=0, k2^0'=__rho_4_^post_28, k3^0'=__rho_10_^post_15, keA^0'=0, keR^0'=0, ntStatus^0'=0, phi_io_compl^0'=0, phi_nSUC_ret^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, [ __rho_1_^post_52<=0 && 1<=CromData^post_27 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 ], cost: 8+7*__rho_5_^post_30
    142: l34 -> l2 : CromData^0'=CromData^post_27, IsochDetachData^0'=IsochDetachData^post_2, __rho_10_^0'=__rho_10_^post_15, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_26, __rho_3_^0'=__rho_3_^post_21, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, a1818^0'=IsochDetachData^post_2, a77^0'=CromData^post_27, i^0'=i^post_2, i___01313^0'=Irql^0, i___01717^0'=Irql^0, i___099^0'=Irql^0, ioA^0'=0, ioR^0'=0, k1^0'=0, k2^0'=__rho_4_^post_28, k3^0'=0, keA^0'=0, keR^0'=0, ntStatus^0'=0, phi_io_compl^0'=0, phi_nSUC_ret^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, [ __rho_1_^post_52<=0 && 1<=CromData^post_27 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 ], cost: 8+2*__rho_10_^post_15+7*__rho_5_^post_30
    143: l34 -> l2 : AsyncAddressData^0'=AsyncAddressData^post_14, CromData^0'=CromData^post_27, __rho_10_^0'=__rho_10_^post_15, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_26, __rho_3_^0'=__rho_3_^post_21, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, __rho_7_^0'=__rho_7_^post_14, __rho_8_^0'=__rho_8_^post_10, __rho_9_^0'=__rho_9_^post_7, a77^0'=CromData^post_27, i___01313^0'=Irql^0, i___099^0'=Irql^0, ioA^0'=0, ioR^0'=0, k1^0'=0, k2^0'=0, k3^0'=__rho_10_^post_15, keA^0'=0, keR^0'=0, ntStatus^0'=0, phi_io_compl^0'=0, phi_nSUC_ret^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, [ __rho_1_^post_52<=0 && 1<=CromData^post_27 && __rho_5_^post_30>=1 && __rho_4_^post_28>=1 ], cost: 8+7*__rho_5_^post_30+8*__rho_4_^post_28
    144: l34 -> l2 : AsyncAddressData^0'=AsyncAddressData^post_14, CromData^0'=CromData^post_27, IsochDetachData^0'=IsochDetachData^post_2, __rho_10_^0'=__rho_10_^post_15, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_26, __rho_3_^0'=__rho_3_^post_21, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, __rho_7_^0'=__rho_7_^post_14, __rho_8_^0'=__rho_8_^post_10, __rho_9_^0'=__rho_9_^post_7, a1818^0'=IsochDetachData^post_2, a77^0'=CromData^post_27, i^0'=i^post_2, i___01313^0'=Irql^0, i___01717^0'=Irql^0, i___099^0'=Irql^0, ioA^0'=0, ioR^0'=0, k1^0'=0, k2^0'=0, k3^0'=0, keA^0'=0, keR^0'=0, ntStatus^0'=0, phi_io_compl^0'=0, phi_nSUC_ret^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, [ __rho_1_^post_52<=0 && 1<=CromData^post_27 && __rho_5_^post_30>=1 && __rho_4_^post_28>=1 && __rho_10_^post_15>=1 ], cost: 8+2*__rho_10_^post_15+7*__rho_5_^post_30+8*__rho_4_^post_28
    145: l34 -> l2 : CromData^0'=CromData^post_27, __rho_10_^0'=__rho_10_^post_15, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_26, __rho_3_^0'=__rho_3_^post_21, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, a11^0'=DeviceObject^0, a77^0'=CromData^post_27, b22^0'=Irp^0, i___01313^0'=Irql^0, i___099^0'=Irql^0, ioA^0'=0, ioR^0'=0, k1^0'=0, k2^0'=__rho_4_^post_28, k3^0'=__rho_10_^post_15, keA^0'=0, keR^0'=0, ntStatus^0'=0, phi_io_compl^0'=0, phi_nSUC_ret^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, ret_t1394Diag_PnpStopDevice33^0'=0, [ 1<=__rho_1_^post_52 && 1<=CromData^post_27 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 ], cost: 8+7*__rho_5_^post_30
    146: l34 -> l2 : CromData^0'=CromData^post_27, IsochDetachData^0'=IsochDetachData^post_2, __rho_10_^0'=__rho_10_^post_15, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_26, __rho_3_^0'=__rho_3_^post_21, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, a11^0'=DeviceObject^0, a1818^0'=IsochDetachData^post_2, a77^0'=CromData^post_27, b22^0'=Irp^0, i^0'=i^post_2, i___01313^0'=Irql^0, i___01717^0'=Irql^0, i___099^0'=Irql^0, ioA^0'=0, ioR^0'=0, k1^0'=0, k2^0'=__rho_4_^post_28, k3^0'=0, keA^0'=0, keR^0'=0, ntStatus^0'=0, phi_io_compl^0'=0, phi_nSUC_ret^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, ret_t1394Diag_PnpStopDevice33^0'=0, [ 1<=__rho_1_^post_52 && 1<=CromData^post_27 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 ], cost: 8+2*__rho_10_^post_15+7*__rho_5_^post_30
    147: l34 -> l2 : AsyncAddressData^0'=AsyncAddressData^post_14, CromData^0'=CromData^post_27, __rho_10_^0'=__rho_10_^post_15, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_26, __rho_3_^0'=__rho_3_^post_21, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, __rho_7_^0'=__rho_7_^post_14, __rho_8_^0'=__rho_8_^post_10, __rho_9_^0'=__rho_9_^post_7, a11^0'=DeviceObject^0, a77^0'=CromData^post_27, b22^0'=Irp^0, i___01313^0'=Irql^0, i___099^0'=Irql^0, ioA^0'=0, ioR^0'=0, k1^0'=0, k2^0'=0, k3^0'=__rho_10_^post_15, keA^0'=0, keR^0'=0, ntStatus^0'=0, phi_io_compl^0'=0, phi_nSUC_ret^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, ret_t1394Diag_PnpStopDevice33^0'=0, [ 1<=__rho_1_^post_52 && 1<=CromData^post_27 && __rho_5_^post_30>=1 && __rho_4_^post_28>=1 ], cost: 8+7*__rho_5_^post_30+8*__rho_4_^post_28
    148: l34 -> l2 : AsyncAddressData^0'=AsyncAddressData^post_14, CromData^0'=CromData^post_27, IsochDetachData^0'=IsochDetachData^post_2, __rho_10_^0'=__rho_10_^post_15, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_26, __rho_3_^0'=__rho_3_^post_21, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, __rho_7_^0'=__rho_7_^post_14, __rho_8_^0'=__rho_8_^post_10, __rho_9_^0'=__rho_9_^post_7, a11^0'=DeviceObject^0, a1818^0'=IsochDetachData^post_2, a77^0'=CromData^post_27, b22^0'=Irp^0, i^0'=i^post_2, i___01313^0'=Irql^0, i___01717^0'=Irql^0, i___099^0'=Irql^0, ioA^0'=0, ioR^0'=0, k1^0'=0, k2^0'=0, k3^0'=0, keA^0'=0, keR^0'=0, ntStatus^0'=0, phi_io_compl^0'=0, phi_nSUC_ret^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, ret_t1394Diag_PnpStopDevice33^0'=0, [ 1<=__rho_1_^post_52 && 1<=CromData^post_27 && __rho_5_^post_30>=1 && __rho_4_^post_28>=1 && __rho_10_^post_15>=1 ], cost: 8+2*__rho_10_^post_15+7*__rho_5_^post_30+8*__rho_4_^post_28

Applied pruning (of leafs and parallel rules):
   Start location: l34
    150: l2 -> l26 : BusResetIrp^0'=BusResetIrp^post_38, __rho_11_^0'=__rho_11_^post_1, __rho_12_^0'=k5^post_50, a4343^0'=0, a4545^0'=BusResetIrp^post_38, i___02020^0'=Irql^0, i___04040^0'=Irql^0, i___04747^0'=Irql^0, k4^0'=__rho_11_^post_1, k5^0'=0, keA^0'=0, keR^0'=0, phi_io_compl^0'=1, prevCancel^0'=0, ret_IoSetCancelRoutine4444^0'=0, [ k3^0<=0 && __rho_11_^post_1<=0 && k5^post_50>=1 ], cost: 6+2*k5^post_50
    151: l2 -> l26 : AsyncAddressData^0'=AsyncAddressData^post_50, BusResetIrp^0'=BusResetIrp^post_50, CromData^0'=CromData^post_50, DeviceObject^0'=DeviceObject^post_50, Irp^0'=Irp^post_50, Irql^0'=Irql^post_50, IsochDetachData^0'=IsochDetachData^post_50, IsochResourceData^0'=IsochResourceData^post_50, ResourceIrp^0'=ResourceIrp^post_50, StackSize^0'=StackSize^post_50, __rho_10_^0'=__rho_10_^post_50, __rho_11_^0'=__rho_11_^post_50, __rho_12_^0'=__rho_12_^post_50, __rho_1_^0'=__rho_1_^post_50, __rho_2_^0'=__rho_2_^post_50, __rho_3_^0'=__rho_3_^post_50, __rho_4_^0'=__rho_4_^post_50, __rho_5_^0'=__rho_5_^post_50, __rho_666_^0'=__rho_666_^post_50, __rho_7_^0'=__rho_7_^post_50, __rho_8_^0'=__rho_8_^post_50, __rho_9_^0'=__rho_9_^post_50, a11^0'=a11^post_50, a1818^0'=a1818^post_50, a2525^0'=a2525^post_50, a2828^0'=a2828^post_50, a3131^0'=a3131^post_50, a3232^0'=a3232^post_50, a3434^0'=a3434^post_50, a3737^0'=a3737^post_50, a3838^0'=a3838^post_50, a4343^0'=a4343^post_50, a4545^0'=a4545^post_50, a77^0'=a77^post_50, b22^0'=b22^post_50, b2626^0'=b2626^post_50, b2929^0'=b2929^post_50, b3333^0'=b3333^post_50, b3535^0'=b3535^post_50, i^0'=i^post_50, i___01313^0'=i___01313^post_50, i___01717^0'=i___01717^post_50, i___02020^0'=i___02020^post_50, i___02424^0'=i___02424^post_50, i___04040^0'=i___04040^post_50, i___04747^0'=Irql^post_50, i___099^0'=i___099^post_50, ioA^0'=ioA^post_50, ioR^0'=ioR^post_50, k1^0'=k1^post_50, k2^0'=k2^post_50, k3^0'=k3^post_50, k4^0'=k4^post_50, k5^0'=k5^post_50, keA^0'=keA^post_50, keR^0'=0, ntStatus^0'=ntStatus^post_50, pIrb^0'=pIrb^post_50, phi_io_compl^0'=phi_io_compl^post_50, phi_nSUC_ret^0'=phi_nSUC_ret^post_50, prevCancel^0'=prevCancel^post_50, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_50, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_50, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_50, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_50, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_50, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_50, [ k3^0<=0 && IsochResourceData^post_51<=0 && __rho_11_^post_1>=1 && i___04040^post_50==Irql^0 && keR^1_4_1==1 && keR^post_50==0 && keA^1_5==1 && keA^post_50==0 && k5^post_50==__rho_12_^post_50 && AsyncAddressData^0==AsyncAddressData^post_50 && BusResetIrp^0==BusResetIrp^post_50 && CromData^0==CromData^post_50 && DeviceObject^0==DeviceObject^post_50 && Irp^0==Irp^post_50 && Irql^0==Irql^post_50 && IsochDetachData^0==IsochDetachData^post_50 && IsochResourceData^post_51==IsochResourceData^post_50 && ResourceIrp^0==ResourceIrp^post_50 && StackSize^0==StackSize^post_50 && __rho_10_^0==__rho_10_^post_50 && __rho_11_^post_1==__rho_11_^post_50 && __rho_1_^0==__rho_1_^post_50 && __rho_2_^0==__rho_2_^post_50 && __rho_3_^0==__rho_3_^post_50 && __rho_4_^0==__rho_4_^post_50 && __rho_5_^0==__rho_5_^post_50 && __rho_666_^0==__rho_666_^post_50 && __rho_7_^0==__rho_7_^post_50 && __rho_8_^0==__rho_8_^post_50 && __rho_9_^0==__rho_9_^post_50 && a11^0==a11^post_50 && a1818^0==a1818^post_50 && a2525^0==a2525^post_50 && a2828^0==a2828^post_50 && a3131^0==a3131^post_50 && a3232^0==a3232^post_50 && a3434^0==a3434^post_50 && a3737^0==a3737^post_50 && a3838^0==a3838^post_50 && a4343^0==a4343^post_50 && a4545^0==a4545^post_50 && a77^0==a77^post_50 && b22^0==b22^post_50 && b2626^0==b2626^post_50 && b2929^0==b2929^post_50 && b3333^0==b3333^post_50 && b3535^0==b3535^post_50 && i^0==i^post_50 && i___01313^0==i___01313^post_50 && i___01717^0==i___01717^post_50 && Irql^0==i___02020^post_50 && Irql^0==i___02424^post_50 && i___04747^0==i___04747^post_50 && i___099^0==i___099^post_50 && ioA^0==ioA^post_50 && ioR^0==ioR^post_50 && k1^0==k1^post_50 && k2^0==k2^post_50 && k3^0==k3^post_50 && 0==k4^post_50 && ntStatus^0==ntStatus^post_50 && pIrb^0==pIrb^post_50 && phi_io_compl^0==phi_io_compl^post_50 && phi_nSUC_ret^0==phi_nSUC_ret^post_50 && prevCancel^0==prevCancel^post_50 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_50 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_50 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_50 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_50 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_50 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_50 && k5^post_50<=0 ], cost: 6+3*__rho_11_^post_1
    152: l2 -> l26 : BusResetIrp^0'=BusResetIrp^post_38, IsochResourceData^0'=IsochResourceData^post_51, __rho_11_^0'=__rho_11_^post_1, __rho_12_^0'=k5^post_50, a4343^0'=0, a4545^0'=BusResetIrp^post_38, i___02020^0'=Irql^0, i___02424^0'=Irql^0, i___04040^0'=Irql^0, i___04747^0'=Irql^0, k4^0'=0, k5^0'=0, keA^0'=0, keR^0'=0, phi_io_compl^0'=1, prevCancel^0'=0, ret_IoSetCancelRoutine4444^0'=0, [ k3^0<=0 && IsochResourceData^post_51<=0 && __rho_11_^post_1>=1 && k5^post_50>=1 ], cost: 6+2*k5^post_50+3*__rho_11_^post_1
    153: l2 -> l26 : AsyncAddressData^0'=AsyncAddressData^post_50, BusResetIrp^0'=BusResetIrp^post_50, CromData^0'=CromData^post_50, DeviceObject^0'=DeviceObject^post_50, Irp^0'=Irp^post_50, Irql^0'=Irql^post_50, IsochDetachData^0'=IsochDetachData^post_50, IsochResourceData^0'=IsochResourceData^post_50, ResourceIrp^0'=ResourceIrp^post_50, StackSize^0'=StackSize^post_50, __rho_10_^0'=__rho_10_^post_50, __rho_11_^0'=__rho_11_^post_50, __rho_12_^0'=__rho_12_^post_50, __rho_1_^0'=__rho_1_^post_50, __rho_2_^0'=__rho_2_^post_50, __rho_3_^0'=__rho_3_^post_50, __rho_4_^0'=__rho_4_^post_50, __rho_5_^0'=__rho_5_^post_50, __rho_666_^0'=__rho_666_^post_50, __rho_7_^0'=__rho_7_^post_50, __rho_8_^0'=__rho_8_^post_50, __rho_9_^0'=__rho_9_^post_50, a11^0'=a11^post_50, a1818^0'=a1818^post_50, a2525^0'=a2525^post_50, a2828^0'=a2828^post_50, a3131^0'=a3131^post_50, a3232^0'=a3232^post_50, a3434^0'=a3434^post_50, a3737^0'=a3737^post_50, a3838^0'=a3838^post_50, a4343^0'=a4343^post_50, a4545^0'=a4545^post_50, a77^0'=a77^post_50, b22^0'=b22^post_50, b2626^0'=b2626^post_50, b2929^0'=b2929^post_50, b3333^0'=b3333^post_50, b3535^0'=b3535^post_50, i^0'=i^post_50, i___01313^0'=i___01313^post_50, i___01717^0'=i___01717^post_50, i___02020^0'=i___02020^post_50, i___02424^0'=i___02424^post_50, i___04040^0'=i___04040^post_50, i___04747^0'=Irql^post_50, i___099^0'=i___099^post_50, ioA^0'=ioA^post_50, ioR^0'=ioR^post_50, k1^0'=k1^post_50, k2^0'=k2^post_50, k3^0'=k3^post_50, k4^0'=k4^post_50, k5^0'=k5^post_50, keA^0'=keA^post_50, keR^0'=0, ntStatus^0'=ntStatus^post_50, pIrb^0'=pIrb^post_50, phi_io_compl^0'=phi_io_compl^post_50, phi_nSUC_ret^0'=phi_nSUC_ret^post_50, prevCancel^0'=prevCancel^post_50, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_50, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_50, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_50, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_50, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_50, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_50, [ k3^0<=0 && 1<=IsochResourceData^post_51 && __rho_11_^post_1>=1 && i___04040^post_50==Irql^0 && keR^1_4_1==1 && keR^post_50==0 && keA^1_5==1 && keA^post_50==0 && k5^post_50==__rho_12_^post_50 && AsyncAddressData^0==AsyncAddressData^post_50 && BusResetIrp^0==BusResetIrp^post_50 && CromData^0==CromData^post_50 && DeviceObject^0==DeviceObject^post_50 && Irp^0==Irp^post_50 && Irql^0==Irql^post_50 && IsochDetachData^0==IsochDetachData^post_50 && IsochResourceData^post_51==IsochResourceData^post_50 && 0==ResourceIrp^post_50 && a2525^post_49==StackSize^post_50 && __rho_10_^0==__rho_10_^post_50 && __rho_11_^post_1==__rho_11_^post_50 && __rho_1_^0==__rho_1_^post_50 && __rho_2_^0==__rho_2_^post_50 && __rho_3_^0==__rho_3_^post_50 && __rho_4_^0==__rho_4_^post_50 && __rho_5_^0==__rho_5_^post_50 && __rho_666_^0==__rho_666_^post_50 && __rho_7_^0==__rho_7_^post_50 && __rho_8_^0==__rho_8_^post_50 && __rho_9_^0==__rho_9_^post_50 && a11^0==a11^post_50 && a1818^0==a1818^post_50 && a2525^post_49==a2525^post_50 && a2828^0==a2828^post_50 && a3131^0==a3131^post_50 && a3232^0==a3232^post_50 && a3434^0==a3434^post_50 && a3737^0==a3737^post_50 && a3838^0==a3838^post_50 && a4343^0==a4343^post_50 && a4545^0==a4545^post_50 && a77^0==a77^post_50 && b22^0==b22^post_50 && 0==b2626^post_50 && b2929^0==b2929^post_50 && b3333^0==b3333^post_50 && b3535^0==b3535^post_50 && i^0==i^post_50 && i___01313^0==i___01313^post_50 && i___01717^0==i___01717^post_50 && Irql^0==i___02020^post_50 && Irql^0==i___02424^post_50 && i___04747^0==i___04747^post_50 && i___099^0==i___099^post_50 && ioA^0==ioA^post_50 && ioR^0==ioR^post_50 && k1^0==k1^post_50 && k2^0==k2^post_50 && k3^0==k3^post_50 && 0==k4^post_50 && ntStatus^0==ntStatus^post_50 && pIrb^post_49==pIrb^post_50 && phi_io_compl^0==phi_io_compl^post_50 && phi_nSUC_ret^0==phi_nSUC_ret^post_50 && prevCancel^0==prevCancel^post_50 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_50 && 0==ret_IoAllocateIrp2727^post_50 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_50 && ret_IoSetDeviceInterfaceState44^0==ret_IoSetDeviceInterfaceState44^post_50 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_50 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_50 && k5^post_50<=0 ], cost: 6+4*__rho_11_^post_1
    154: l2 -> l26 : BusResetIrp^0'=BusResetIrp^post_38, IsochResourceData^0'=IsochResourceData^post_51, ResourceIrp^0'=0, StackSize^0'=a2525^post_49, __rho_11_^0'=__rho_11_^post_1, __rho_12_^0'=k5^post_50, a2525^0'=a2525^post_49, a4343^0'=0, a4545^0'=BusResetIrp^post_38, b2626^0'=0, i___02020^0'=Irql^0, i___02424^0'=Irql^0, i___04040^0'=Irql^0, i___04747^0'=Irql^0, k4^0'=0, k5^0'=0, keA^0'=0, keR^0'=0, pIrb^0'=pIrb^post_49, phi_io_compl^0'=1, prevCancel^0'=0, ret_IoAllocateIrp2727^0'=0, ret_IoSetCancelRoutine4444^0'=0, [ k3^0<=0 && 1<=IsochResourceData^post_51 && __rho_11_^post_1>=1 && k5^post_50>=1 ], cost: 6+2*k5^post_50+4*__rho_11_^post_1
     57: l26 -> [35] : [ -2+ntStatus^0==0 ], cost: NONTERM
     70: l26 -> [35] : [ 3<=ntStatus^0 ], cost: NONTERM
     71: l26 -> [35] : [ 1+ntStatus^0<=2 ], cost: NONTERM
    134: l34 -> l2 : CromData^0'=CromData^post_27, IsochDetachData^0'=IsochDetachData^post_2, __rho_10_^0'=__rho_10_^post_15, __rho_1_^0'=__rho_1_^post_52, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, a1818^0'=IsochDetachData^post_2, i^0'=i^post_2, i___01313^0'=Irql^0, i___01717^0'=Irql^0, i___099^0'=Irql^0, ioA^0'=0, ioR^0'=0, k1^0'=0, k2^0'=__rho_4_^post_28, k3^0'=0, keA^0'=0, keR^0'=0, ntStatus^0'=0, phi_io_compl^0'=0, phi_nSUC_ret^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, [ __rho_1_^post_52<=0 && CromData^post_27<=0 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 ], cost: 8+2*__rho_10_^post_15+3*__rho_5_^post_30
    137: l34 -> l2 : CromData^0'=CromData^post_27, __rho_10_^0'=__rho_10_^post_15, __rho_1_^0'=__rho_1_^post_52, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, a11^0'=DeviceObject^0, b22^0'=Irp^0, i___01313^0'=Irql^0, i___099^0'=Irql^0, ioA^0'=0, ioR^0'=0, k1^0'=0, k2^0'=__rho_4_^post_28, k3^0'=__rho_10_^post_15, keA^0'=0, keR^0'=0, ntStatus^0'=0, phi_io_compl^0'=0, phi_nSUC_ret^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, ret_t1394Diag_PnpStopDevice33^0'=0, [ 1<=__rho_1_^post_52 && CromData^post_27<=0 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 ], cost: 8+3*__rho_5_^post_30
    138: l34 -> l2 : CromData^0'=CromData^post_27, IsochDetachData^0'=IsochDetachData^post_2, __rho_10_^0'=__rho_10_^post_15, __rho_1_^0'=__rho_1_^post_52, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, a11^0'=DeviceObject^0, a1818^0'=IsochDetachData^post_2, b22^0'=Irp^0, i^0'=i^post_2, i___01313^0'=Irql^0, i___01717^0'=Irql^0, i___099^0'=Irql^0, ioA^0'=0, ioR^0'=0, k1^0'=0, k2^0'=__rho_4_^post_28, k3^0'=0, keA^0'=0, keR^0'=0, ntStatus^0'=0, phi_io_compl^0'=0, phi_nSUC_ret^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, ret_t1394Diag_PnpStopDevice33^0'=0, [ 1<=__rho_1_^post_52 && CromData^post_27<=0 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 ], cost: 8+2*__rho_10_^post_15+3*__rho_5_^post_30
    142: l34 -> l2 : CromData^0'=CromData^post_27, IsochDetachData^0'=IsochDetachData^post_2, __rho_10_^0'=__rho_10_^post_15, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_26, __rho_3_^0'=__rho_3_^post_21, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, a1818^0'=IsochDetachData^post_2, a77^0'=CromData^post_27, i^0'=i^post_2, i___01313^0'=Irql^0, i___01717^0'=Irql^0, i___099^0'=Irql^0, ioA^0'=0, ioR^0'=0, k1^0'=0, k2^0'=__rho_4_^post_28, k3^0'=0, keA^0'=0, keR^0'=0, ntStatus^0'=0, phi_io_compl^0'=0, phi_nSUC_ret^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, [ __rho_1_^post_52<=0 && 1<=CromData^post_27 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 ], cost: 8+2*__rho_10_^post_15+7*__rho_5_^post_30
    146: l34 -> l2 : CromData^0'=CromData^post_27, IsochDetachData^0'=IsochDetachData^post_2, __rho_10_^0'=__rho_10_^post_15, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_26, __rho_3_^0'=__rho_3_^post_21, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, a11^0'=DeviceObject^0, a1818^0'=IsochDetachData^post_2, a77^0'=CromData^post_27, b22^0'=Irp^0, i^0'=i^post_2, i___01313^0'=Irql^0, i___01717^0'=Irql^0, i___099^0'=Irql^0, ioA^0'=0, ioR^0'=0, k1^0'=0, k2^0'=__rho_4_^post_28, k3^0'=0, keA^0'=0, keR^0'=0, ntStatus^0'=0, phi_io_compl^0'=0, phi_nSUC_ret^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, ret_t1394Diag_PnpStopDevice33^0'=0, [ 1<=__rho_1_^post_52 && 1<=CromData^post_27 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 ], cost: 8+2*__rho_10_^post_15+7*__rho_5_^post_30

Eliminated locations (on tree-shaped paths):
   Start location: l34
     57: l26 -> [35] : [ -2+ntStatus^0==0 ], cost: NONTERM
     70: l26 -> [35] : [ 3<=ntStatus^0 ], cost: NONTERM
     71: l26 -> [35] : [ 1+ntStatus^0<=2 ], cost: NONTERM
    155: l34 -> l26 : BusResetIrp^0'=BusResetIrp^post_38, CromData^0'=CromData^post_27, IsochDetachData^0'=IsochDetachData^post_2, __rho_10_^0'=__rho_10_^post_15, __rho_11_^0'=__rho_11_^post_1, __rho_12_^0'=k5^post_50, __rho_1_^0'=__rho_1_^post_52, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, a1818^0'=IsochDetachData^post_2, a4343^0'=0, a4545^0'=BusResetIrp^post_38, i^0'=i^post_2, i___01313^0'=Irql^0, i___01717^0'=Irql^0, i___02020^0'=Irql^0, i___04040^0'=Irql^0, i___04747^0'=Irql^0, i___099^0'=Irql^0, ioA^0'=0, ioR^0'=0, k1^0'=0, k2^0'=__rho_4_^post_28, k3^0'=0, k4^0'=__rho_11_^post_1, k5^0'=0, keA^0'=0, keR^0'=0, ntStatus^0'=0, phi_io_compl^0'=1, phi_nSUC_ret^0'=0, prevCancel^0'=0, ret_IoSetCancelRoutine4444^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, [ __rho_1_^post_52<=0 && CromData^post_27<=0 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 && __rho_11_^post_1<=0 && k5^post_50>=1 ], cost: 14+2*k5^post_50+2*__rho_10_^post_15+3*__rho_5_^post_30
    156: l34 -> l26 : AsyncAddressData^0'=AsyncAddressData^post_50, BusResetIrp^0'=BusResetIrp^post_50, CromData^0'=CromData^post_50, DeviceObject^0'=DeviceObject^post_50, Irp^0'=Irp^post_50, Irql^0'=Irql^post_50, IsochDetachData^0'=IsochDetachData^post_50, IsochResourceData^0'=IsochResourceData^post_50, ResourceIrp^0'=ResourceIrp^post_50, StackSize^0'=StackSize^post_50, __rho_10_^0'=__rho_10_^post_50, __rho_11_^0'=__rho_11_^post_50, __rho_12_^0'=__rho_12_^post_50, __rho_1_^0'=__rho_1_^post_50, __rho_2_^0'=__rho_2_^post_50, __rho_3_^0'=__rho_3_^post_50, __rho_4_^0'=__rho_4_^post_50, __rho_5_^0'=__rho_5_^post_50, __rho_666_^0'=__rho_666_^post_50, __rho_7_^0'=__rho_7_^post_50, __rho_8_^0'=__rho_8_^post_50, __rho_9_^0'=__rho_9_^post_50, a11^0'=a11^post_50, a1818^0'=a1818^post_50, a2525^0'=a2525^post_50, a2828^0'=a2828^post_50, a3131^0'=a3131^post_50, a3232^0'=a3232^post_50, a3434^0'=a3434^post_50, a3737^0'=a3737^post_50, a3838^0'=a3838^post_50, a4343^0'=a4343^post_50, a4545^0'=a4545^post_50, a77^0'=a77^post_50, b22^0'=b22^post_50, b2626^0'=b2626^post_50, b2929^0'=b2929^post_50, b3333^0'=b3333^post_50, b3535^0'=b3535^post_50, i^0'=i^post_50, i___01313^0'=i___01313^post_50, i___01717^0'=i___01717^post_50, i___02020^0'=i___02020^post_50, i___02424^0'=i___02424^post_50, i___04040^0'=i___04040^post_50, i___04747^0'=Irql^post_50, i___099^0'=i___099^post_50, ioA^0'=ioA^post_50, ioR^0'=ioR^post_50, k1^0'=k1^post_50, k2^0'=k2^post_50, k3^0'=k3^post_50, k4^0'=k4^post_50, k5^0'=k5^post_50, keA^0'=keA^post_50, keR^0'=0, ntStatus^0'=ntStatus^post_50, pIrb^0'=pIrb^post_50, phi_io_compl^0'=phi_io_compl^post_50, phi_nSUC_ret^0'=phi_nSUC_ret^post_50, prevCancel^0'=prevCancel^post_50, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_50, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_50, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_50, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_50, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_50, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_50, [ __rho_1_^post_52<=0 && CromData^post_27<=0 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 && IsochResourceData^post_51<=0 && __rho_11_^post_1>=1 && i___04040^post_50==Irql^0 && keR^1_4_1==1 && keR^post_50==0 && keA^1_5==1 && keA^post_50==0 && k5^post_50==__rho_12_^post_50 && AsyncAddressData^0==AsyncAddressData^post_50 && BusResetIrp^0==BusResetIrp^post_50 && CromData^post_27==CromData^post_50 && DeviceObject^0==DeviceObject^post_50 && Irp^0==Irp^post_50 && Irql^0==Irql^post_50 && IsochDetachData^post_2==IsochDetachData^post_50 && IsochResourceData^post_51==IsochResourceData^post_50 && ResourceIrp^0==ResourceIrp^post_50 && StackSize^0==StackSize^post_50 && __rho_10_^post_15==__rho_10_^post_50 && __rho_11_^post_1==__rho_11_^post_50 && __rho_1_^post_52==__rho_1_^post_50 && __rho_2_^0==__rho_2_^post_50 && __rho_3_^0==__rho_3_^post_50 && __rho_4_^post_28==__rho_4_^post_50 && __rho_5_^post_30==__rho_5_^post_50 && __rho_666_^post_52==__rho_666_^post_50 && __rho_7_^0==__rho_7_^post_50 && __rho_8_^0==__rho_8_^post_50 && __rho_9_^0==__rho_9_^post_50 && a11^0==a11^post_50 && IsochDetachData^post_2==a1818^post_50 && a2525^0==a2525^post_50 && a2828^0==a2828^post_50 && a3131^0==a3131^post_50 && a3232^0==a3232^post_50 && a3434^0==a3434^post_50 && a3737^0==a3737^post_50 && a3838^0==a3838^post_50 && a4343^0==a4343^post_50 && a4545^0==a4545^post_50 && a77^0==a77^post_50 && b22^0==b22^post_50 && b2626^0==b2626^post_50 && b2929^0==b2929^post_50 && b3333^0==b3333^post_50 && b3535^0==b3535^post_50 && i^post_2==i^post_50 && Irql^0==i___01313^post_50 && Irql^0==i___01717^post_50 && Irql^0==i___02020^post_50 && Irql^0==i___02424^post_50 && i___04747^0==i___04747^post_50 && Irql^0==i___099^post_50 && 0==ioA^post_50 && 0==ioR^post_50 && 0==k1^post_50 && __rho_4_^post_28==k2^post_50 && 0==k3^post_50 && 0==k4^post_50 && 0==ntStatus^post_50 && pIrb^0==pIrb^post_50 && 0==phi_io_compl^post_50 && 0==phi_nSUC_ret^post_50 && prevCancel^0==prevCancel^post_50 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_50 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_50 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_50 && 0==ret_IoSetDeviceInterfaceState44^post_50 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_50 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_50 && k5^post_50<=0 ], cost: 14+2*__rho_10_^post_15+3*__rho_5_^post_30+3*__rho_11_^post_1
    157: l34 -> l26 : BusResetIrp^0'=BusResetIrp^post_38, CromData^0'=CromData^post_27, IsochDetachData^0'=IsochDetachData^post_2, IsochResourceData^0'=IsochResourceData^post_51, __rho_10_^0'=__rho_10_^post_15, __rho_11_^0'=__rho_11_^post_1, __rho_12_^0'=k5^post_50, __rho_1_^0'=__rho_1_^post_52, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, a1818^0'=IsochDetachData^post_2, a4343^0'=0, a4545^0'=BusResetIrp^post_38, i^0'=i^post_2, i___01313^0'=Irql^0, i___01717^0'=Irql^0, i___02020^0'=Irql^0, i___02424^0'=Irql^0, i___04040^0'=Irql^0, i___04747^0'=Irql^0, i___099^0'=Irql^0, ioA^0'=0, ioR^0'=0, k1^0'=0, k2^0'=__rho_4_^post_28, k3^0'=0, k4^0'=0, k5^0'=0, keA^0'=0, keR^0'=0, ntStatus^0'=0, phi_io_compl^0'=1, phi_nSUC_ret^0'=0, prevCancel^0'=0, ret_IoSetCancelRoutine4444^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, [ __rho_1_^post_52<=0 && CromData^post_27<=0 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 && IsochResourceData^post_51<=0 && __rho_11_^post_1>=1 && k5^post_50>=1 ], cost: 14+2*k5^post_50+2*__rho_10_^post_15+3*__rho_5_^post_30+3*__rho_11_^post_1
    158: l34 -> l26 : AsyncAddressData^0'=AsyncAddressData^post_50, BusResetIrp^0'=BusResetIrp^post_50, CromData^0'=CromData^post_50, DeviceObject^0'=DeviceObject^post_50, Irp^0'=Irp^post_50, Irql^0'=Irql^post_50, IsochDetachData^0'=IsochDetachData^post_50, IsochResourceData^0'=IsochResourceData^post_50, ResourceIrp^0'=ResourceIrp^post_50, StackSize^0'=StackSize^post_50, __rho_10_^0'=__rho_10_^post_50, __rho_11_^0'=__rho_11_^post_50, __rho_12_^0'=__rho_12_^post_50, __rho_1_^0'=__rho_1_^post_50, __rho_2_^0'=__rho_2_^post_50, __rho_3_^0'=__rho_3_^post_50, __rho_4_^0'=__rho_4_^post_50, __rho_5_^0'=__rho_5_^post_50, __rho_666_^0'=__rho_666_^post_50, __rho_7_^0'=__rho_7_^post_50, __rho_8_^0'=__rho_8_^post_50, __rho_9_^0'=__rho_9_^post_50, a11^0'=a11^post_50, a1818^0'=a1818^post_50, a2525^0'=a2525^post_50, a2828^0'=a2828^post_50, a3131^0'=a3131^post_50, a3232^0'=a3232^post_50, a3434^0'=a3434^post_50, a3737^0'=a3737^post_50, a3838^0'=a3838^post_50, a4343^0'=a4343^post_50, a4545^0'=a4545^post_50, a77^0'=a77^post_50, b22^0'=b22^post_50, b2626^0'=b2626^post_50, b2929^0'=b2929^post_50, b3333^0'=b3333^post_50, b3535^0'=b3535^post_50, i^0'=i^post_50, i___01313^0'=i___01313^post_50, i___01717^0'=i___01717^post_50, i___02020^0'=i___02020^post_50, i___02424^0'=i___02424^post_50, i___04040^0'=i___04040^post_50, i___04747^0'=Irql^post_50, i___099^0'=i___099^post_50, ioA^0'=ioA^post_50, ioR^0'=ioR^post_50, k1^0'=k1^post_50, k2^0'=k2^post_50, k3^0'=k3^post_50, k4^0'=k4^post_50, k5^0'=k5^post_50, keA^0'=keA^post_50, keR^0'=0, ntStatus^0'=ntStatus^post_50, pIrb^0'=pIrb^post_50, phi_io_compl^0'=phi_io_compl^post_50, phi_nSUC_ret^0'=phi_nSUC_ret^post_50, prevCancel^0'=prevCancel^post_50, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_50, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_50, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_50, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_50, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_50, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_50, [ __rho_1_^post_52<=0 && CromData^post_27<=0 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 && 1<=IsochResourceData^post_51 && __rho_11_^post_1>=1 && i___04040^post_50==Irql^0 && keR^1_4_1==1 && keR^post_50==0 && keA^1_5==1 && keA^post_50==0 && k5^post_50==__rho_12_^post_50 && AsyncAddressData^0==AsyncAddressData^post_50 && BusResetIrp^0==BusResetIrp^post_50 && CromData^post_27==CromData^post_50 && DeviceObject^0==DeviceObject^post_50 && Irp^0==Irp^post_50 && Irql^0==Irql^post_50 && IsochDetachData^post_2==IsochDetachData^post_50 && IsochResourceData^post_51==IsochResourceData^post_50 && 0==ResourceIrp^post_50 && a2525^post_49==StackSize^post_50 && __rho_10_^post_15==__rho_10_^post_50 && __rho_11_^post_1==__rho_11_^post_50 && __rho_1_^post_52==__rho_1_^post_50 && __rho_2_^0==__rho_2_^post_50 && __rho_3_^0==__rho_3_^post_50 && __rho_4_^post_28==__rho_4_^post_50 && __rho_5_^post_30==__rho_5_^post_50 && __rho_666_^post_52==__rho_666_^post_50 && __rho_7_^0==__rho_7_^post_50 && __rho_8_^0==__rho_8_^post_50 && __rho_9_^0==__rho_9_^post_50 && a11^0==a11^post_50 && IsochDetachData^post_2==a1818^post_50 && a2525^post_49==a2525^post_50 && a2828^0==a2828^post_50 && a3131^0==a3131^post_50 && a3232^0==a3232^post_50 && a3434^0==a3434^post_50 && a3737^0==a3737^post_50 && a3838^0==a3838^post_50 && a4343^0==a4343^post_50 && a4545^0==a4545^post_50 && a77^0==a77^post_50 && b22^0==b22^post_50 && 0==b2626^post_50 && b2929^0==b2929^post_50 && b3333^0==b3333^post_50 && b3535^0==b3535^post_50 && i^post_2==i^post_50 && Irql^0==i___01313^post_50 && Irql^0==i___01717^post_50 && Irql^0==i___02020^post_50 && Irql^0==i___02424^post_50 && i___04747^0==i___04747^post_50 && Irql^0==i___099^post_50 && 0==ioA^post_50 && 0==ioR^post_50 && 0==k1^post_50 && __rho_4_^post_28==k2^post_50 && 0==k3^post_50 && 0==k4^post_50 && 0==ntStatus^post_50 && pIrb^post_49==pIrb^post_50 && 0==phi_io_compl^post_50 && 0==phi_nSUC_ret^post_50 && prevCancel^0==prevCancel^post_50 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_50 && 0==ret_IoAllocateIrp2727^post_50 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_50 && 0==ret_IoSetDeviceInterfaceState44^post_50 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_50 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_50 && k5^post_50<=0 ], cost: 14+2*__rho_10_^post_15+3*__rho_5_^post_30+4*__rho_11_^post_1
    159: l34 -> l26 : BusResetIrp^0'=BusResetIrp^post_38, CromData^0'=CromData^post_27, IsochDetachData^0'=IsochDetachData^post_2, IsochResourceData^0'=IsochResourceData^post_51, ResourceIrp^0'=0, StackSize^0'=a2525^post_49, __rho_10_^0'=__rho_10_^post_15, __rho_11_^0'=__rho_11_^post_1, __rho_12_^0'=k5^post_50, __rho_1_^0'=__rho_1_^post_52, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, a1818^0'=IsochDetachData^post_2, a2525^0'=a2525^post_49, a4343^0'=0, a4545^0'=BusResetIrp^post_38, b2626^0'=0, i^0'=i^post_2, i___01313^0'=Irql^0, i___01717^0'=Irql^0, i___02020^0'=Irql^0, i___02424^0'=Irql^0, i___04040^0'=Irql^0, i___04747^0'=Irql^0, i___099^0'=Irql^0, ioA^0'=0, ioR^0'=0, k1^0'=0, k2^0'=__rho_4_^post_28, k3^0'=0, k4^0'=0, k5^0'=0, keA^0'=0, keR^0'=0, ntStatus^0'=0, pIrb^0'=pIrb^post_49, phi_io_compl^0'=1, phi_nSUC_ret^0'=0, prevCancel^0'=0, ret_IoAllocateIrp2727^0'=0, ret_IoSetCancelRoutine4444^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, [ __rho_1_^post_52<=0 && CromData^post_27<=0 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 && 1<=IsochResourceData^post_51 && __rho_11_^post_1>=1 && k5^post_50>=1 ], cost: 14+2*k5^post_50+2*__rho_10_^post_15+3*__rho_5_^post_30+4*__rho_11_^post_1
    160: l34 -> l26 : BusResetIrp^0'=BusResetIrp^post_38, CromData^0'=CromData^post_27, __rho_10_^0'=__rho_10_^post_15, __rho_11_^0'=__rho_11_^post_1, __rho_12_^0'=k5^post_50, __rho_1_^0'=__rho_1_^post_52, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, a11^0'=DeviceObject^0, a4343^0'=0, a4545^0'=BusResetIrp^post_38, b22^0'=Irp^0, i___01313^0'=Irql^0, i___02020^0'=Irql^0, i___04040^0'=Irql^0, i___04747^0'=Irql^0, i___099^0'=Irql^0, ioA^0'=0, ioR^0'=0, k1^0'=0, k2^0'=__rho_4_^post_28, k3^0'=__rho_10_^post_15, k4^0'=__rho_11_^post_1, k5^0'=0, keA^0'=0, keR^0'=0, ntStatus^0'=0, phi_io_compl^0'=1, phi_nSUC_ret^0'=0, prevCancel^0'=0, ret_IoSetCancelRoutine4444^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, ret_t1394Diag_PnpStopDevice33^0'=0, [ 1<=__rho_1_^post_52 && CromData^post_27<=0 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15<=0 && __rho_11_^post_1<=0 && k5^post_50>=1 ], cost: 14+2*k5^post_50+3*__rho_5_^post_30
    161: l34 -> l26 : AsyncAddressData^0'=AsyncAddressData^post_50, BusResetIrp^0'=BusResetIrp^post_50, CromData^0'=CromData^post_50, DeviceObject^0'=DeviceObject^post_50, Irp^0'=Irp^post_50, Irql^0'=Irql^post_50, IsochDetachData^0'=IsochDetachData^post_50, IsochResourceData^0'=IsochResourceData^post_50, ResourceIrp^0'=ResourceIrp^post_50, StackSize^0'=StackSize^post_50, __rho_10_^0'=__rho_10_^post_50, __rho_11_^0'=__rho_11_^post_50, __rho_12_^0'=__rho_12_^post_50, __rho_1_^0'=__rho_1_^post_50, __rho_2_^0'=__rho_2_^post_50, __rho_3_^0'=__rho_3_^post_50, __rho_4_^0'=__rho_4_^post_50, __rho_5_^0'=__rho_5_^post_50, __rho_666_^0'=__rho_666_^post_50, __rho_7_^0'=__rho_7_^post_50, __rho_8_^0'=__rho_8_^post_50, __rho_9_^0'=__rho_9_^post_50, a11^0'=a11^post_50, a1818^0'=a1818^post_50, a2525^0'=a2525^post_50, a2828^0'=a2828^post_50, a3131^0'=a3131^post_50, a3232^0'=a3232^post_50, a3434^0'=a3434^post_50, a3737^0'=a3737^post_50, a3838^0'=a3838^post_50, a4343^0'=a4343^post_50, a4545^0'=a4545^post_50, a77^0'=a77^post_50, b22^0'=b22^post_50, b2626^0'=b2626^post_50, b2929^0'=b2929^post_50, b3333^0'=b3333^post_50, b3535^0'=b3535^post_50, i^0'=i^post_50, i___01313^0'=i___01313^post_50, i___01717^0'=i___01717^post_50, i___02020^0'=i___02020^post_50, i___02424^0'=i___02424^post_50, i___04040^0'=i___04040^post_50, i___04747^0'=Irql^post_50, i___099^0'=i___099^post_50, ioA^0'=ioA^post_50, ioR^0'=ioR^post_50, k1^0'=k1^post_50, k2^0'=k2^post_50, k3^0'=k3^post_50, k4^0'=k4^post_50, k5^0'=k5^post_50, keA^0'=keA^post_50, keR^0'=0, ntStatus^0'=ntStatus^post_50, pIrb^0'=pIrb^post_50, phi_io_compl^0'=phi_io_compl^post_50, phi_nSUC_ret^0'=phi_nSUC_ret^post_50, prevCancel^0'=prevCancel^post_50, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_50, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_50, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_50, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_50, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_50, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_50, [ 1<=__rho_1_^post_52 && CromData^post_27<=0 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15<=0 && IsochResourceData^post_51<=0 && __rho_11_^post_1>=1 && i___04040^post_50==Irql^0 && keR^1_4_1==1 && keR^post_50==0 && keA^1_5==1 && keA^post_50==0 && k5^post_50==__rho_12_^post_50 && AsyncAddressData^0==AsyncAddressData^post_50 && BusResetIrp^0==BusResetIrp^post_50 && CromData^post_27==CromData^post_50 && DeviceObject^0==DeviceObject^post_50 && Irp^0==Irp^post_50 && Irql^0==Irql^post_50 && IsochDetachData^0==IsochDetachData^post_50 && IsochResourceData^post_51==IsochResourceData^post_50 && ResourceIrp^0==ResourceIrp^post_50 && StackSize^0==StackSize^post_50 && __rho_10_^post_15==__rho_10_^post_50 && __rho_11_^post_1==__rho_11_^post_50 && __rho_1_^post_52==__rho_1_^post_50 && __rho_2_^0==__rho_2_^post_50 && __rho_3_^0==__rho_3_^post_50 && __rho_4_^post_28==__rho_4_^post_50 && __rho_5_^post_30==__rho_5_^post_50 && __rho_666_^post_52==__rho_666_^post_50 && __rho_7_^0==__rho_7_^post_50 && __rho_8_^0==__rho_8_^post_50 && __rho_9_^0==__rho_9_^post_50 && DeviceObject^0==a11^post_50 && a1818^0==a1818^post_50 && a2525^0==a2525^post_50 && a2828^0==a2828^post_50 && a3131^0==a3131^post_50 && a3232^0==a3232^post_50 && a3434^0==a3434^post_50 && a3737^0==a3737^post_50 && a3838^0==a3838^post_50 && a4343^0==a4343^post_50 && a4545^0==a4545^post_50 && a77^0==a77^post_50 && Irp^0==b22^post_50 && b2626^0==b2626^post_50 && b2929^0==b2929^post_50 && b3333^0==b3333^post_50 && b3535^0==b3535^post_50 && i^0==i^post_50 && Irql^0==i___01313^post_50 && i___01717^0==i___01717^post_50 && Irql^0==i___02020^post_50 && Irql^0==i___02424^post_50 && i___04747^0==i___04747^post_50 && Irql^0==i___099^post_50 && 0==ioA^post_50 && 0==ioR^post_50 && 0==k1^post_50 && __rho_4_^post_28==k2^post_50 && __rho_10_^post_15==k3^post_50 && 0==k4^post_50 && 0==ntStatus^post_50 && pIrb^0==pIrb^post_50 && 0==phi_io_compl^post_50 && 0==phi_nSUC_ret^post_50 && prevCancel^0==prevCancel^post_50 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_50 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_50 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_50 && 0==ret_IoSetDeviceInterfaceState44^post_50 && 0==ret_t1394Diag_PnpStopDevice33^post_50 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_50 && k5^post_50<=0 ], cost: 14+3*__rho_5_^post_30+3*__rho_11_^post_1
    162: l34 -> l26 : BusResetIrp^0'=BusResetIrp^post_38, CromData^0'=CromData^post_27, IsochResourceData^0'=IsochResourceData^post_51, __rho_10_^0'=__rho_10_^post_15, __rho_11_^0'=__rho_11_^post_1, __rho_12_^0'=k5^post_50, __rho_1_^0'=__rho_1_^post_52, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, a11^0'=DeviceObject^0, a4343^0'=0, a4545^0'=BusResetIrp^post_38, b22^0'=Irp^0, i___01313^0'=Irql^0, i___02020^0'=Irql^0, i___02424^0'=Irql^0, i___04040^0'=Irql^0, i___04747^0'=Irql^0, i___099^0'=Irql^0, ioA^0'=0, ioR^0'=0, k1^0'=0, k2^0'=__rho_4_^post_28, k3^0'=__rho_10_^post_15, k4^0'=0, k5^0'=0, keA^0'=0, keR^0'=0, ntStatus^0'=0, phi_io_compl^0'=1, phi_nSUC_ret^0'=0, prevCancel^0'=0, ret_IoSetCancelRoutine4444^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, ret_t1394Diag_PnpStopDevice33^0'=0, [ 1<=__rho_1_^post_52 && CromData^post_27<=0 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15<=0 && IsochResourceData^post_51<=0 && __rho_11_^post_1>=1 && k5^post_50>=1 ], cost: 14+2*k5^post_50+3*__rho_5_^post_30+3*__rho_11_^post_1
    163: l34 -> l26 : AsyncAddressData^0'=AsyncAddressData^post_50, BusResetIrp^0'=BusResetIrp^post_50, CromData^0'=CromData^post_50, DeviceObject^0'=DeviceObject^post_50, Irp^0'=Irp^post_50, Irql^0'=Irql^post_50, IsochDetachData^0'=IsochDetachData^post_50, IsochResourceData^0'=IsochResourceData^post_50, ResourceIrp^0'=ResourceIrp^post_50, StackSize^0'=StackSize^post_50, __rho_10_^0'=__rho_10_^post_50, __rho_11_^0'=__rho_11_^post_50, __rho_12_^0'=__rho_12_^post_50, __rho_1_^0'=__rho_1_^post_50, __rho_2_^0'=__rho_2_^post_50, __rho_3_^0'=__rho_3_^post_50, __rho_4_^0'=__rho_4_^post_50, __rho_5_^0'=__rho_5_^post_50, __rho_666_^0'=__rho_666_^post_50, __rho_7_^0'=__rho_7_^post_50, __rho_8_^0'=__rho_8_^post_50, __rho_9_^0'=__rho_9_^post_50, a11^0'=a11^post_50, a1818^0'=a1818^post_50, a2525^0'=a2525^post_50, a2828^0'=a2828^post_50, a3131^0'=a3131^post_50, a3232^0'=a3232^post_50, a3434^0'=a3434^post_50, a3737^0'=a3737^post_50, a3838^0'=a3838^post_50, a4343^0'=a4343^post_50, a4545^0'=a4545^post_50, a77^0'=a77^post_50, b22^0'=b22^post_50, b2626^0'=b2626^post_50, b2929^0'=b2929^post_50, b3333^0'=b3333^post_50, b3535^0'=b3535^post_50, i^0'=i^post_50, i___01313^0'=i___01313^post_50, i___01717^0'=i___01717^post_50, i___02020^0'=i___02020^post_50, i___02424^0'=i___02424^post_50, i___04040^0'=i___04040^post_50, i___04747^0'=Irql^post_50, i___099^0'=i___099^post_50, ioA^0'=ioA^post_50, ioR^0'=ioR^post_50, k1^0'=k1^post_50, k2^0'=k2^post_50, k3^0'=k3^post_50, k4^0'=k4^post_50, k5^0'=k5^post_50, keA^0'=keA^post_50, keR^0'=0, ntStatus^0'=ntStatus^post_50, pIrb^0'=pIrb^post_50, phi_io_compl^0'=phi_io_compl^post_50, phi_nSUC_ret^0'=phi_nSUC_ret^post_50, prevCancel^0'=prevCancel^post_50, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_50, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_50, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_50, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_50, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_50, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_50, [ 1<=__rho_1_^post_52 && CromData^post_27<=0 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15<=0 && 1<=IsochResourceData^post_51 && __rho_11_^post_1>=1 && i___04040^post_50==Irql^0 && keR^1_4_1==1 && keR^post_50==0 && keA^1_5==1 && keA^post_50==0 && k5^post_50==__rho_12_^post_50 && AsyncAddressData^0==AsyncAddressData^post_50 && BusResetIrp^0==BusResetIrp^post_50 && CromData^post_27==CromData^post_50 && DeviceObject^0==DeviceObject^post_50 && Irp^0==Irp^post_50 && Irql^0==Irql^post_50 && IsochDetachData^0==IsochDetachData^post_50 && IsochResourceData^post_51==IsochResourceData^post_50 && 0==ResourceIrp^post_50 && a2525^post_49==StackSize^post_50 && __rho_10_^post_15==__rho_10_^post_50 && __rho_11_^post_1==__rho_11_^post_50 && __rho_1_^post_52==__rho_1_^post_50 && __rho_2_^0==__rho_2_^post_50 && __rho_3_^0==__rho_3_^post_50 && __rho_4_^post_28==__rho_4_^post_50 && __rho_5_^post_30==__rho_5_^post_50 && __rho_666_^post_52==__rho_666_^post_50 && __rho_7_^0==__rho_7_^post_50 && __rho_8_^0==__rho_8_^post_50 && __rho_9_^0==__rho_9_^post_50 && DeviceObject^0==a11^post_50 && a1818^0==a1818^post_50 && a2525^post_49==a2525^post_50 && a2828^0==a2828^post_50 && a3131^0==a3131^post_50 && a3232^0==a3232^post_50 && a3434^0==a3434^post_50 && a3737^0==a3737^post_50 && a3838^0==a3838^post_50 && a4343^0==a4343^post_50 && a4545^0==a4545^post_50 && a77^0==a77^post_50 && Irp^0==b22^post_50 && 0==b2626^post_50 && b2929^0==b2929^post_50 && b3333^0==b3333^post_50 && b3535^0==b3535^post_50 && i^0==i^post_50 && Irql^0==i___01313^post_50 && i___01717^0==i___01717^post_50 && Irql^0==i___02020^post_50 && Irql^0==i___02424^post_50 && i___04747^0==i___04747^post_50 && Irql^0==i___099^post_50 && 0==ioA^post_50 && 0==ioR^post_50 && 0==k1^post_50 && __rho_4_^post_28==k2^post_50 && __rho_10_^post_15==k3^post_50 && 0==k4^post_50 && 0==ntStatus^post_50 && pIrb^post_49==pIrb^post_50 && 0==phi_io_compl^post_50 && 0==phi_nSUC_ret^post_50 && prevCancel^0==prevCancel^post_50 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_50 && 0==ret_IoAllocateIrp2727^post_50 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_50 && 0==ret_IoSetDeviceInterfaceState44^post_50 && 0==ret_t1394Diag_PnpStopDevice33^post_50 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_50 && k5^post_50<=0 ], cost: 14+3*__rho_5_^post_30+4*__rho_11_^post_1
    164: l34 -> l26 : BusResetIrp^0'=BusResetIrp^post_38, CromData^0'=CromData^post_27, IsochResourceData^0'=IsochResourceData^post_51, ResourceIrp^0'=0, StackSize^0'=a2525^post_49, __rho_10_^0'=__rho_10_^post_15, __rho_11_^0'=__rho_11_^post_1, __rho_12_^0'=k5^post_50, __rho_1_^0'=__rho_1_^post_52, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, a11^0'=DeviceObject^0, a2525^0'=a2525^post_49, a4343^0'=0, a4545^0'=BusResetIrp^post_38, b22^0'=Irp^0, b2626^0'=0, i___01313^0'=Irql^0, i___02020^0'=Irql^0, i___02424^0'=Irql^0, i___04040^0'=Irql^0, i___04747^0'=Irql^0, i___099^0'=Irql^0, ioA^0'=0, ioR^0'=0, k1^0'=0, k2^0'=__rho_4_^post_28, k3^0'=__rho_10_^post_15, k4^0'=0, k5^0'=0, keA^0'=0, keR^0'=0, ntStatus^0'=0, pIrb^0'=pIrb^post_49, phi_io_compl^0'=1, phi_nSUC_ret^0'=0, prevCancel^0'=0, ret_IoAllocateIrp2727^0'=0, ret_IoSetCancelRoutine4444^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, ret_t1394Diag_PnpStopDevice33^0'=0, [ 1<=__rho_1_^post_52 && CromData^post_27<=0 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15<=0 && 1<=IsochResourceData^post_51 && __rho_11_^post_1>=1 && k5^post_50>=1 ], cost: 14+2*k5^post_50+3*__rho_5_^post_30+4*__rho_11_^post_1
    165: l34 -> l26 : BusResetIrp^0'=BusResetIrp^post_38, CromData^0'=CromData^post_27, IsochDetachData^0'=IsochDetachData^post_2, __rho_10_^0'=__rho_10_^post_15, __rho_11_^0'=__rho_11_^post_1, __rho_12_^0'=k5^post_50, __rho_1_^0'=__rho_1_^post_52, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, a11^0'=DeviceObject^0, a1818^0'=IsochDetachData^post_2, a4343^0'=0, a4545^0'=BusResetIrp^post_38, b22^0'=Irp^0, i^0'=i^post_2, i___01313^0'=Irql^0, i___01717^0'=Irql^0, i___02020^0'=Irql^0, i___04040^0'=Irql^0, i___04747^0'=Irql^0, i___099^0'=Irql^0, ioA^0'=0, ioR^0'=0, k1^0'=0, k2^0'=__rho_4_^post_28, k3^0'=0, k4^0'=__rho_11_^post_1, k5^0'=0, keA^0'=0, keR^0'=0, ntStatus^0'=0, phi_io_compl^0'=1, phi_nSUC_ret^0'=0, prevCancel^0'=0, ret_IoSetCancelRoutine4444^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, ret_t1394Diag_PnpStopDevice33^0'=0, [ 1<=__rho_1_^post_52 && CromData^post_27<=0 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 && __rho_11_^post_1<=0 && k5^post_50>=1 ], cost: 14+2*k5^post_50+2*__rho_10_^post_15+3*__rho_5_^post_30
    166: l34 -> l26 : AsyncAddressData^0'=AsyncAddressData^post_50, BusResetIrp^0'=BusResetIrp^post_50, CromData^0'=CromData^post_50, DeviceObject^0'=DeviceObject^post_50, Irp^0'=Irp^post_50, Irql^0'=Irql^post_50, IsochDetachData^0'=IsochDetachData^post_50, IsochResourceData^0'=IsochResourceData^post_50, ResourceIrp^0'=ResourceIrp^post_50, StackSize^0'=StackSize^post_50, __rho_10_^0'=__rho_10_^post_50, __rho_11_^0'=__rho_11_^post_50, __rho_12_^0'=__rho_12_^post_50, __rho_1_^0'=__rho_1_^post_50, __rho_2_^0'=__rho_2_^post_50, __rho_3_^0'=__rho_3_^post_50, __rho_4_^0'=__rho_4_^post_50, __rho_5_^0'=__rho_5_^post_50, __rho_666_^0'=__rho_666_^post_50, __rho_7_^0'=__rho_7_^post_50, __rho_8_^0'=__rho_8_^post_50, __rho_9_^0'=__rho_9_^post_50, a11^0'=a11^post_50, a1818^0'=a1818^post_50, a2525^0'=a2525^post_50, a2828^0'=a2828^post_50, a3131^0'=a3131^post_50, a3232^0'=a3232^post_50, a3434^0'=a3434^post_50, a3737^0'=a3737^post_50, a3838^0'=a3838^post_50, a4343^0'=a4343^post_50, a4545^0'=a4545^post_50, a77^0'=a77^post_50, b22^0'=b22^post_50, b2626^0'=b2626^post_50, b2929^0'=b2929^post_50, b3333^0'=b3333^post_50, b3535^0'=b3535^post_50, i^0'=i^post_50, i___01313^0'=i___01313^post_50, i___01717^0'=i___01717^post_50, i___02020^0'=i___02020^post_50, i___02424^0'=i___02424^post_50, i___04040^0'=i___04040^post_50, i___04747^0'=Irql^post_50, i___099^0'=i___099^post_50, ioA^0'=ioA^post_50, ioR^0'=ioR^post_50, k1^0'=k1^post_50, k2^0'=k2^post_50, k3^0'=k3^post_50, k4^0'=k4^post_50, k5^0'=k5^post_50, keA^0'=keA^post_50, keR^0'=0, ntStatus^0'=ntStatus^post_50, pIrb^0'=pIrb^post_50, phi_io_compl^0'=phi_io_compl^post_50, phi_nSUC_ret^0'=phi_nSUC_ret^post_50, prevCancel^0'=prevCancel^post_50, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_50, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_50, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_50, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_50, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_50, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_50, [ 1<=__rho_1_^post_52 && CromData^post_27<=0 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 && IsochResourceData^post_51<=0 && __rho_11_^post_1>=1 && i___04040^post_50==Irql^0 && keR^1_4_1==1 && keR^post_50==0 && keA^1_5==1 && keA^post_50==0 && k5^post_50==__rho_12_^post_50 && AsyncAddressData^0==AsyncAddressData^post_50 && BusResetIrp^0==BusResetIrp^post_50 && CromData^post_27==CromData^post_50 && DeviceObject^0==DeviceObject^post_50 && Irp^0==Irp^post_50 && Irql^0==Irql^post_50 && IsochDetachData^post_2==IsochDetachData^post_50 && IsochResourceData^post_51==IsochResourceData^post_50 && ResourceIrp^0==ResourceIrp^post_50 && StackSize^0==StackSize^post_50 && __rho_10_^post_15==__rho_10_^post_50 && __rho_11_^post_1==__rho_11_^post_50 && __rho_1_^post_52==__rho_1_^post_50 && __rho_2_^0==__rho_2_^post_50 && __rho_3_^0==__rho_3_^post_50 && __rho_4_^post_28==__rho_4_^post_50 && __rho_5_^post_30==__rho_5_^post_50 && __rho_666_^post_52==__rho_666_^post_50 && __rho_7_^0==__rho_7_^post_50 && __rho_8_^0==__rho_8_^post_50 && __rho_9_^0==__rho_9_^post_50 && DeviceObject^0==a11^post_50 && IsochDetachData^post_2==a1818^post_50 && a2525^0==a2525^post_50 && a2828^0==a2828^post_50 && a3131^0==a3131^post_50 && a3232^0==a3232^post_50 && a3434^0==a3434^post_50 && a3737^0==a3737^post_50 && a3838^0==a3838^post_50 && a4343^0==a4343^post_50 && a4545^0==a4545^post_50 && a77^0==a77^post_50 && Irp^0==b22^post_50 && b2626^0==b2626^post_50 && b2929^0==b2929^post_50 && b3333^0==b3333^post_50 && b3535^0==b3535^post_50 && i^post_2==i^post_50 && Irql^0==i___01313^post_50 && Irql^0==i___01717^post_50 && Irql^0==i___02020^post_50 && Irql^0==i___02424^post_50 && i___04747^0==i___04747^post_50 && Irql^0==i___099^post_50 && 0==ioA^post_50 && 0==ioR^post_50 && 0==k1^post_50 && __rho_4_^post_28==k2^post_50 && 0==k3^post_50 && 0==k4^post_50 && 0==ntStatus^post_50 && pIrb^0==pIrb^post_50 && 0==phi_io_compl^post_50 && 0==phi_nSUC_ret^post_50 && prevCancel^0==prevCancel^post_50 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_50 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_50 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_50 && 0==ret_IoSetDeviceInterfaceState44^post_50 && 0==ret_t1394Diag_PnpStopDevice33^post_50 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_50 && k5^post_50<=0 ], cost: 14+2*__rho_10_^post_15+3*__rho_5_^post_30+3*__rho_11_^post_1
    167: l34 -> l26 : BusResetIrp^0'=BusResetIrp^post_38, CromData^0'=CromData^post_27, IsochDetachData^0'=IsochDetachData^post_2, IsochResourceData^0'=IsochResourceData^post_51, __rho_10_^0'=__rho_10_^post_15, __rho_11_^0'=__rho_11_^post_1, __rho_12_^0'=k5^post_50, __rho_1_^0'=__rho_1_^post_52, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, a11^0'=DeviceObject^0, a1818^0'=IsochDetachData^post_2, a4343^0'=0, a4545^0'=BusResetIrp^post_38, b22^0'=Irp^0, i^0'=i^post_2, i___01313^0'=Irql^0, i___01717^0'=Irql^0, i___02020^0'=Irql^0, i___02424^0'=Irql^0, i___04040^0'=Irql^0, i___04747^0'=Irql^0, i___099^0'=Irql^0, ioA^0'=0, ioR^0'=0, k1^0'=0, k2^0'=__rho_4_^post_28, k3^0'=0, k4^0'=0, k5^0'=0, keA^0'=0, keR^0'=0, ntStatus^0'=0, phi_io_compl^0'=1, phi_nSUC_ret^0'=0, prevCancel^0'=0, ret_IoSetCancelRoutine4444^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, ret_t1394Diag_PnpStopDevice33^0'=0, [ 1<=__rho_1_^post_52 && CromData^post_27<=0 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 && IsochResourceData^post_51<=0 && __rho_11_^post_1>=1 && k5^post_50>=1 ], cost: 14+2*k5^post_50+2*__rho_10_^post_15+3*__rho_5_^post_30+3*__rho_11_^post_1
    168: l34 -> l26 : AsyncAddressData^0'=AsyncAddressData^post_50, BusResetIrp^0'=BusResetIrp^post_50, CromData^0'=CromData^post_50, DeviceObject^0'=DeviceObject^post_50, Irp^0'=Irp^post_50, Irql^0'=Irql^post_50, IsochDetachData^0'=IsochDetachData^post_50, IsochResourceData^0'=IsochResourceData^post_50, ResourceIrp^0'=ResourceIrp^post_50, StackSize^0'=StackSize^post_50, __rho_10_^0'=__rho_10_^post_50, __rho_11_^0'=__rho_11_^post_50, __rho_12_^0'=__rho_12_^post_50, __rho_1_^0'=__rho_1_^post_50, __rho_2_^0'=__rho_2_^post_50, __rho_3_^0'=__rho_3_^post_50, __rho_4_^0'=__rho_4_^post_50, __rho_5_^0'=__rho_5_^post_50, __rho_666_^0'=__rho_666_^post_50, __rho_7_^0'=__rho_7_^post_50, __rho_8_^0'=__rho_8_^post_50, __rho_9_^0'=__rho_9_^post_50, a11^0'=a11^post_50, a1818^0'=a1818^post_50, a2525^0'=a2525^post_50, a2828^0'=a2828^post_50, a3131^0'=a3131^post_50, a3232^0'=a3232^post_50, a3434^0'=a3434^post_50, a3737^0'=a3737^post_50, a3838^0'=a3838^post_50, a4343^0'=a4343^post_50, a4545^0'=a4545^post_50, a77^0'=a77^post_50, b22^0'=b22^post_50, b2626^0'=b2626^post_50, b2929^0'=b2929^post_50, b3333^0'=b3333^post_50, b3535^0'=b3535^post_50, i^0'=i^post_50, i___01313^0'=i___01313^post_50, i___01717^0'=i___01717^post_50, i___02020^0'=i___02020^post_50, i___02424^0'=i___02424^post_50, i___04040^0'=i___04040^post_50, i___04747^0'=Irql^post_50, i___099^0'=i___099^post_50, ioA^0'=ioA^post_50, ioR^0'=ioR^post_50, k1^0'=k1^post_50, k2^0'=k2^post_50, k3^0'=k3^post_50, k4^0'=k4^post_50, k5^0'=k5^post_50, keA^0'=keA^post_50, keR^0'=0, ntStatus^0'=ntStatus^post_50, pIrb^0'=pIrb^post_50, phi_io_compl^0'=phi_io_compl^post_50, phi_nSUC_ret^0'=phi_nSUC_ret^post_50, prevCancel^0'=prevCancel^post_50, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_50, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_50, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_50, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_50, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_50, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_50, [ 1<=__rho_1_^post_52 && CromData^post_27<=0 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 && 1<=IsochResourceData^post_51 && __rho_11_^post_1>=1 && i___04040^post_50==Irql^0 && keR^1_4_1==1 && keR^post_50==0 && keA^1_5==1 && keA^post_50==0 && k5^post_50==__rho_12_^post_50 && AsyncAddressData^0==AsyncAddressData^post_50 && BusResetIrp^0==BusResetIrp^post_50 && CromData^post_27==CromData^post_50 && DeviceObject^0==DeviceObject^post_50 && Irp^0==Irp^post_50 && Irql^0==Irql^post_50 && IsochDetachData^post_2==IsochDetachData^post_50 && IsochResourceData^post_51==IsochResourceData^post_50 && 0==ResourceIrp^post_50 && a2525^post_49==StackSize^post_50 && __rho_10_^post_15==__rho_10_^post_50 && __rho_11_^post_1==__rho_11_^post_50 && __rho_1_^post_52==__rho_1_^post_50 && __rho_2_^0==__rho_2_^post_50 && __rho_3_^0==__rho_3_^post_50 && __rho_4_^post_28==__rho_4_^post_50 && __rho_5_^post_30==__rho_5_^post_50 && __rho_666_^post_52==__rho_666_^post_50 && __rho_7_^0==__rho_7_^post_50 && __rho_8_^0==__rho_8_^post_50 && __rho_9_^0==__rho_9_^post_50 && DeviceObject^0==a11^post_50 && IsochDetachData^post_2==a1818^post_50 && a2525^post_49==a2525^post_50 && a2828^0==a2828^post_50 && a3131^0==a3131^post_50 && a3232^0==a3232^post_50 && a3434^0==a3434^post_50 && a3737^0==a3737^post_50 && a3838^0==a3838^post_50 && a4343^0==a4343^post_50 && a4545^0==a4545^post_50 && a77^0==a77^post_50 && Irp^0==b22^post_50 && 0==b2626^post_50 && b2929^0==b2929^post_50 && b3333^0==b3333^post_50 && b3535^0==b3535^post_50 && i^post_2==i^post_50 && Irql^0==i___01313^post_50 && Irql^0==i___01717^post_50 && Irql^0==i___02020^post_50 && Irql^0==i___02424^post_50 && i___04747^0==i___04747^post_50 && Irql^0==i___099^post_50 && 0==ioA^post_50 && 0==ioR^post_50 && 0==k1^post_50 && __rho_4_^post_28==k2^post_50 && 0==k3^post_50 && 0==k4^post_50 && 0==ntStatus^post_50 && pIrb^post_49==pIrb^post_50 && 0==phi_io_compl^post_50 && 0==phi_nSUC_ret^post_50 && prevCancel^0==prevCancel^post_50 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_50 && 0==ret_IoAllocateIrp2727^post_50 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_50 && 0==ret_IoSetDeviceInterfaceState44^post_50 && 0==ret_t1394Diag_PnpStopDevice33^post_50 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_50 && k5^post_50<=0 ], cost: 14+2*__rho_10_^post_15+3*__rho_5_^post_30+4*__rho_11_^post_1
    169: l34 -> l26 : BusResetIrp^0'=BusResetIrp^post_38, CromData^0'=CromData^post_27, IsochDetachData^0'=IsochDetachData^post_2, IsochResourceData^0'=IsochResourceData^post_51, ResourceIrp^0'=0, StackSize^0'=a2525^post_49, __rho_10_^0'=__rho_10_^post_15, __rho_11_^0'=__rho_11_^post_1, __rho_12_^0'=k5^post_50, __rho_1_^0'=__rho_1_^post_52, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, a11^0'=DeviceObject^0, a1818^0'=IsochDetachData^post_2, a2525^0'=a2525^post_49, a4343^0'=0, a4545^0'=BusResetIrp^post_38, b22^0'=Irp^0, b2626^0'=0, i^0'=i^post_2, i___01313^0'=Irql^0, i___01717^0'=Irql^0, i___02020^0'=Irql^0, i___02424^0'=Irql^0, i___04040^0'=Irql^0, i___04747^0'=Irql^0, i___099^0'=Irql^0, ioA^0'=0, ioR^0'=0, k1^0'=0, k2^0'=__rho_4_^post_28, k3^0'=0, k4^0'=0, k5^0'=0, keA^0'=0, keR^0'=0, ntStatus^0'=0, pIrb^0'=pIrb^post_49, phi_io_compl^0'=1, phi_nSUC_ret^0'=0, prevCancel^0'=0, ret_IoAllocateIrp2727^0'=0, ret_IoSetCancelRoutine4444^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, ret_t1394Diag_PnpStopDevice33^0'=0, [ 1<=__rho_1_^post_52 && CromData^post_27<=0 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 && 1<=IsochResourceData^post_51 && __rho_11_^post_1>=1 && k5^post_50>=1 ], cost: 14+2*k5^post_50+2*__rho_10_^post_15+3*__rho_5_^post_30+4*__rho_11_^post_1
    170: l34 -> l26 : BusResetIrp^0'=BusResetIrp^post_38, CromData^0'=CromData^post_27, IsochDetachData^0'=IsochDetachData^post_2, __rho_10_^0'=__rho_10_^post_15, __rho_11_^0'=__rho_11_^post_1, __rho_12_^0'=k5^post_50, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_26, __rho_3_^0'=__rho_3_^post_21, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, a1818^0'=IsochDetachData^post_2, a4343^0'=0, a4545^0'=BusResetIrp^post_38, a77^0'=CromData^post_27, i^0'=i^post_2, i___01313^0'=Irql^0, i___01717^0'=Irql^0, i___02020^0'=Irql^0, i___04040^0'=Irql^0, i___04747^0'=Irql^0, i___099^0'=Irql^0, ioA^0'=0, ioR^0'=0, k1^0'=0, k2^0'=__rho_4_^post_28, k3^0'=0, k4^0'=__rho_11_^post_1, k5^0'=0, keA^0'=0, keR^0'=0, ntStatus^0'=0, phi_io_compl^0'=1, phi_nSUC_ret^0'=0, prevCancel^0'=0, ret_IoSetCancelRoutine4444^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, [ __rho_1_^post_52<=0 && 1<=CromData^post_27 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 && __rho_11_^post_1<=0 && k5^post_50>=1 ], cost: 14+2*k5^post_50+2*__rho_10_^post_15+7*__rho_5_^post_30
    171: l34 -> l26 : AsyncAddressData^0'=AsyncAddressData^post_50, BusResetIrp^0'=BusResetIrp^post_50, CromData^0'=CromData^post_50, DeviceObject^0'=DeviceObject^post_50, Irp^0'=Irp^post_50, Irql^0'=Irql^post_50, IsochDetachData^0'=IsochDetachData^post_50, IsochResourceData^0'=IsochResourceData^post_50, ResourceIrp^0'=ResourceIrp^post_50, StackSize^0'=StackSize^post_50, __rho_10_^0'=__rho_10_^post_50, __rho_11_^0'=__rho_11_^post_50, __rho_12_^0'=__rho_12_^post_50, __rho_1_^0'=__rho_1_^post_50, __rho_2_^0'=__rho_2_^post_50, __rho_3_^0'=__rho_3_^post_50, __rho_4_^0'=__rho_4_^post_50, __rho_5_^0'=__rho_5_^post_50, __rho_666_^0'=__rho_666_^post_50, __rho_7_^0'=__rho_7_^post_50, __rho_8_^0'=__rho_8_^post_50, __rho_9_^0'=__rho_9_^post_50, a11^0'=a11^post_50, a1818^0'=a1818^post_50, a2525^0'=a2525^post_50, a2828^0'=a2828^post_50, a3131^0'=a3131^post_50, a3232^0'=a3232^post_50, a3434^0'=a3434^post_50, a3737^0'=a3737^post_50, a3838^0'=a3838^post_50, a4343^0'=a4343^post_50, a4545^0'=a4545^post_50, a77^0'=a77^post_50, b22^0'=b22^post_50, b2626^0'=b2626^post_50, b2929^0'=b2929^post_50, b3333^0'=b3333^post_50, b3535^0'=b3535^post_50, i^0'=i^post_50, i___01313^0'=i___01313^post_50, i___01717^0'=i___01717^post_50, i___02020^0'=i___02020^post_50, i___02424^0'=i___02424^post_50, i___04040^0'=i___04040^post_50, i___04747^0'=Irql^post_50, i___099^0'=i___099^post_50, ioA^0'=ioA^post_50, ioR^0'=ioR^post_50, k1^0'=k1^post_50, k2^0'=k2^post_50, k3^0'=k3^post_50, k4^0'=k4^post_50, k5^0'=k5^post_50, keA^0'=keA^post_50, keR^0'=0, ntStatus^0'=ntStatus^post_50, pIrb^0'=pIrb^post_50, phi_io_compl^0'=phi_io_compl^post_50, phi_nSUC_ret^0'=phi_nSUC_ret^post_50, prevCancel^0'=prevCancel^post_50, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_50, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_50, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_50, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_50, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_50, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_50, [ __rho_1_^post_52<=0 && 1<=CromData^post_27 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 && IsochResourceData^post_51<=0 && __rho_11_^post_1>=1 && i___04040^post_50==Irql^0 && keR^1_4_1==1 && keR^post_50==0 && keA^1_5==1 && keA^post_50==0 && k5^post_50==__rho_12_^post_50 && AsyncAddressData^0==AsyncAddressData^post_50 && BusResetIrp^0==BusResetIrp^post_50 && CromData^post_27==CromData^post_50 && DeviceObject^0==DeviceObject^post_50 && Irp^0==Irp^post_50 && Irql^0==Irql^post_50 && IsochDetachData^post_2==IsochDetachData^post_50 && IsochResourceData^post_51==IsochResourceData^post_50 && ResourceIrp^0==ResourceIrp^post_50 && StackSize^0==StackSize^post_50 && __rho_10_^post_15==__rho_10_^post_50 && __rho_11_^post_1==__rho_11_^post_50 && __rho_1_^post_52==__rho_1_^post_50 && __rho_2_^post_26==__rho_2_^post_50 && __rho_3_^post_21==__rho_3_^post_50 && __rho_4_^post_28==__rho_4_^post_50 && __rho_5_^post_30==__rho_5_^post_50 && __rho_666_^post_52==__rho_666_^post_50 && __rho_7_^0==__rho_7_^post_50 && __rho_8_^0==__rho_8_^post_50 && __rho_9_^0==__rho_9_^post_50 && a11^0==a11^post_50 && IsochDetachData^post_2==a1818^post_50 && a2525^0==a2525^post_50 && a2828^0==a2828^post_50 && a3131^0==a3131^post_50 && a3232^0==a3232^post_50 && a3434^0==a3434^post_50 && a3737^0==a3737^post_50 && a3838^0==a3838^post_50 && a4343^0==a4343^post_50 && a4545^0==a4545^post_50 && CromData^post_27==a77^post_50 && b22^0==b22^post_50 && b2626^0==b2626^post_50 && b2929^0==b2929^post_50 && b3333^0==b3333^post_50 && b3535^0==b3535^post_50 && i^post_2==i^post_50 && Irql^0==i___01313^post_50 && Irql^0==i___01717^post_50 && Irql^0==i___02020^post_50 && Irql^0==i___02424^post_50 && i___04747^0==i___04747^post_50 && Irql^0==i___099^post_50 && 0==ioA^post_50 && 0==ioR^post_50 && 0==k1^post_50 && __rho_4_^post_28==k2^post_50 && 0==k3^post_50 && 0==k4^post_50 && 0==ntStatus^post_50 && pIrb^0==pIrb^post_50 && 0==phi_io_compl^post_50 && 0==phi_nSUC_ret^post_50 && prevCancel^0==prevCancel^post_50 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_50 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_50 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_50 && 0==ret_IoSetDeviceInterfaceState44^post_50 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_50 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_50 && k5^post_50<=0 ], cost: 14+2*__rho_10_^post_15+7*__rho_5_^post_30+3*__rho_11_^post_1
    172: l34 -> l26 : BusResetIrp^0'=BusResetIrp^post_38, CromData^0'=CromData^post_27, IsochDetachData^0'=IsochDetachData^post_2, IsochResourceData^0'=IsochResourceData^post_51, __rho_10_^0'=__rho_10_^post_15, __rho_11_^0'=__rho_11_^post_1, __rho_12_^0'=k5^post_50, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_26, __rho_3_^0'=__rho_3_^post_21, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, a1818^0'=IsochDetachData^post_2, a4343^0'=0, a4545^0'=BusResetIrp^post_38, a77^0'=CromData^post_27, i^0'=i^post_2, i___01313^0'=Irql^0, i___01717^0'=Irql^0, i___02020^0'=Irql^0, i___02424^0'=Irql^0, i___04040^0'=Irql^0, i___04747^0'=Irql^0, i___099^0'=Irql^0, ioA^0'=0, ioR^0'=0, k1^0'=0, k2^0'=__rho_4_^post_28, k3^0'=0, k4^0'=0, k5^0'=0, keA^0'=0, keR^0'=0, ntStatus^0'=0, phi_io_compl^0'=1, phi_nSUC_ret^0'=0, prevCancel^0'=0, ret_IoSetCancelRoutine4444^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, [ __rho_1_^post_52<=0 && 1<=CromData^post_27 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 && IsochResourceData^post_51<=0 && __rho_11_^post_1>=1 && k5^post_50>=1 ], cost: 14+2*k5^post_50+2*__rho_10_^post_15+7*__rho_5_^post_30+3*__rho_11_^post_1
    173: l34 -> l26 : AsyncAddressData^0'=AsyncAddressData^post_50, BusResetIrp^0'=BusResetIrp^post_50, CromData^0'=CromData^post_50, DeviceObject^0'=DeviceObject^post_50, Irp^0'=Irp^post_50, Irql^0'=Irql^post_50, IsochDetachData^0'=IsochDetachData^post_50, IsochResourceData^0'=IsochResourceData^post_50, ResourceIrp^0'=ResourceIrp^post_50, StackSize^0'=StackSize^post_50, __rho_10_^0'=__rho_10_^post_50, __rho_11_^0'=__rho_11_^post_50, __rho_12_^0'=__rho_12_^post_50, __rho_1_^0'=__rho_1_^post_50, __rho_2_^0'=__rho_2_^post_50, __rho_3_^0'=__rho_3_^post_50, __rho_4_^0'=__rho_4_^post_50, __rho_5_^0'=__rho_5_^post_50, __rho_666_^0'=__rho_666_^post_50, __rho_7_^0'=__rho_7_^post_50, __rho_8_^0'=__rho_8_^post_50, __rho_9_^0'=__rho_9_^post_50, a11^0'=a11^post_50, a1818^0'=a1818^post_50, a2525^0'=a2525^post_50, a2828^0'=a2828^post_50, a3131^0'=a3131^post_50, a3232^0'=a3232^post_50, a3434^0'=a3434^post_50, a3737^0'=a3737^post_50, a3838^0'=a3838^post_50, a4343^0'=a4343^post_50, a4545^0'=a4545^post_50, a77^0'=a77^post_50, b22^0'=b22^post_50, b2626^0'=b2626^post_50, b2929^0'=b2929^post_50, b3333^0'=b3333^post_50, b3535^0'=b3535^post_50, i^0'=i^post_50, i___01313^0'=i___01313^post_50, i___01717^0'=i___01717^post_50, i___02020^0'=i___02020^post_50, i___02424^0'=i___02424^post_50, i___04040^0'=i___04040^post_50, i___04747^0'=Irql^post_50, i___099^0'=i___099^post_50, ioA^0'=ioA^post_50, ioR^0'=ioR^post_50, k1^0'=k1^post_50, k2^0'=k2^post_50, k3^0'=k3^post_50, k4^0'=k4^post_50, k5^0'=k5^post_50, keA^0'=keA^post_50, keR^0'=0, ntStatus^0'=ntStatus^post_50, pIrb^0'=pIrb^post_50, phi_io_compl^0'=phi_io_compl^post_50, phi_nSUC_ret^0'=phi_nSUC_ret^post_50, prevCancel^0'=prevCancel^post_50, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_50, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_50, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_50, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_50, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_50, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_50, [ __rho_1_^post_52<=0 && 1<=CromData^post_27 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 && 1<=IsochResourceData^post_51 && __rho_11_^post_1>=1 && i___04040^post_50==Irql^0 && keR^1_4_1==1 && keR^post_50==0 && keA^1_5==1 && keA^post_50==0 && k5^post_50==__rho_12_^post_50 && AsyncAddressData^0==AsyncAddressData^post_50 && BusResetIrp^0==BusResetIrp^post_50 && CromData^post_27==CromData^post_50 && DeviceObject^0==DeviceObject^post_50 && Irp^0==Irp^post_50 && Irql^0==Irql^post_50 && IsochDetachData^post_2==IsochDetachData^post_50 && IsochResourceData^post_51==IsochResourceData^post_50 && 0==ResourceIrp^post_50 && a2525^post_49==StackSize^post_50 && __rho_10_^post_15==__rho_10_^post_50 && __rho_11_^post_1==__rho_11_^post_50 && __rho_1_^post_52==__rho_1_^post_50 && __rho_2_^post_26==__rho_2_^post_50 && __rho_3_^post_21==__rho_3_^post_50 && __rho_4_^post_28==__rho_4_^post_50 && __rho_5_^post_30==__rho_5_^post_50 && __rho_666_^post_52==__rho_666_^post_50 && __rho_7_^0==__rho_7_^post_50 && __rho_8_^0==__rho_8_^post_50 && __rho_9_^0==__rho_9_^post_50 && a11^0==a11^post_50 && IsochDetachData^post_2==a1818^post_50 && a2525^post_49==a2525^post_50 && a2828^0==a2828^post_50 && a3131^0==a3131^post_50 && a3232^0==a3232^post_50 && a3434^0==a3434^post_50 && a3737^0==a3737^post_50 && a3838^0==a3838^post_50 && a4343^0==a4343^post_50 && a4545^0==a4545^post_50 && CromData^post_27==a77^post_50 && b22^0==b22^post_50 && 0==b2626^post_50 && b2929^0==b2929^post_50 && b3333^0==b3333^post_50 && b3535^0==b3535^post_50 && i^post_2==i^post_50 && Irql^0==i___01313^post_50 && Irql^0==i___01717^post_50 && Irql^0==i___02020^post_50 && Irql^0==i___02424^post_50 && i___04747^0==i___04747^post_50 && Irql^0==i___099^post_50 && 0==ioA^post_50 && 0==ioR^post_50 && 0==k1^post_50 && __rho_4_^post_28==k2^post_50 && 0==k3^post_50 && 0==k4^post_50 && 0==ntStatus^post_50 && pIrb^post_49==pIrb^post_50 && 0==phi_io_compl^post_50 && 0==phi_nSUC_ret^post_50 && prevCancel^0==prevCancel^post_50 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_50 && 0==ret_IoAllocateIrp2727^post_50 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_50 && 0==ret_IoSetDeviceInterfaceState44^post_50 && ret_t1394Diag_PnpStopDevice33^0==ret_t1394Diag_PnpStopDevice33^post_50 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_50 && k5^post_50<=0 ], cost: 14+2*__rho_10_^post_15+7*__rho_5_^post_30+4*__rho_11_^post_1
    174: l34 -> l26 : BusResetIrp^0'=BusResetIrp^post_38, CromData^0'=CromData^post_27, IsochDetachData^0'=IsochDetachData^post_2, IsochResourceData^0'=IsochResourceData^post_51, ResourceIrp^0'=0, StackSize^0'=a2525^post_49, __rho_10_^0'=__rho_10_^post_15, __rho_11_^0'=__rho_11_^post_1, __rho_12_^0'=k5^post_50, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_26, __rho_3_^0'=__rho_3_^post_21, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, a1818^0'=IsochDetachData^post_2, a2525^0'=a2525^post_49, a4343^0'=0, a4545^0'=BusResetIrp^post_38, a77^0'=CromData^post_27, b2626^0'=0, i^0'=i^post_2, i___01313^0'=Irql^0, i___01717^0'=Irql^0, i___02020^0'=Irql^0, i___02424^0'=Irql^0, i___04040^0'=Irql^0, i___04747^0'=Irql^0, i___099^0'=Irql^0, ioA^0'=0, ioR^0'=0, k1^0'=0, k2^0'=__rho_4_^post_28, k3^0'=0, k4^0'=0, k5^0'=0, keA^0'=0, keR^0'=0, ntStatus^0'=0, pIrb^0'=pIrb^post_49, phi_io_compl^0'=1, phi_nSUC_ret^0'=0, prevCancel^0'=0, ret_IoAllocateIrp2727^0'=0, ret_IoSetCancelRoutine4444^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, [ __rho_1_^post_52<=0 && 1<=CromData^post_27 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 && 1<=IsochResourceData^post_51 && __rho_11_^post_1>=1 && k5^post_50>=1 ], cost: 14+2*k5^post_50+2*__rho_10_^post_15+7*__rho_5_^post_30+4*__rho_11_^post_1
    175: l34 -> l26 : BusResetIrp^0'=BusResetIrp^post_38, CromData^0'=CromData^post_27, IsochDetachData^0'=IsochDetachData^post_2, __rho_10_^0'=__rho_10_^post_15, __rho_11_^0'=__rho_11_^post_1, __rho_12_^0'=k5^post_50, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_26, __rho_3_^0'=__rho_3_^post_21, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, a11^0'=DeviceObject^0, a1818^0'=IsochDetachData^post_2, a4343^0'=0, a4545^0'=BusResetIrp^post_38, a77^0'=CromData^post_27, b22^0'=Irp^0, i^0'=i^post_2, i___01313^0'=Irql^0, i___01717^0'=Irql^0, i___02020^0'=Irql^0, i___04040^0'=Irql^0, i___04747^0'=Irql^0, i___099^0'=Irql^0, ioA^0'=0, ioR^0'=0, k1^0'=0, k2^0'=__rho_4_^post_28, k3^0'=0, k4^0'=__rho_11_^post_1, k5^0'=0, keA^0'=0, keR^0'=0, ntStatus^0'=0, phi_io_compl^0'=1, phi_nSUC_ret^0'=0, prevCancel^0'=0, ret_IoSetCancelRoutine4444^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, ret_t1394Diag_PnpStopDevice33^0'=0, [ 1<=__rho_1_^post_52 && 1<=CromData^post_27 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 && __rho_11_^post_1<=0 && k5^post_50>=1 ], cost: 14+2*k5^post_50+2*__rho_10_^post_15+7*__rho_5_^post_30
    176: l34 -> l26 : AsyncAddressData^0'=AsyncAddressData^post_50, BusResetIrp^0'=BusResetIrp^post_50, CromData^0'=CromData^post_50, DeviceObject^0'=DeviceObject^post_50, Irp^0'=Irp^post_50, Irql^0'=Irql^post_50, IsochDetachData^0'=IsochDetachData^post_50, IsochResourceData^0'=IsochResourceData^post_50, ResourceIrp^0'=ResourceIrp^post_50, StackSize^0'=StackSize^post_50, __rho_10_^0'=__rho_10_^post_50, __rho_11_^0'=__rho_11_^post_50, __rho_12_^0'=__rho_12_^post_50, __rho_1_^0'=__rho_1_^post_50, __rho_2_^0'=__rho_2_^post_50, __rho_3_^0'=__rho_3_^post_50, __rho_4_^0'=__rho_4_^post_50, __rho_5_^0'=__rho_5_^post_50, __rho_666_^0'=__rho_666_^post_50, __rho_7_^0'=__rho_7_^post_50, __rho_8_^0'=__rho_8_^post_50, __rho_9_^0'=__rho_9_^post_50, a11^0'=a11^post_50, a1818^0'=a1818^post_50, a2525^0'=a2525^post_50, a2828^0'=a2828^post_50, a3131^0'=a3131^post_50, a3232^0'=a3232^post_50, a3434^0'=a3434^post_50, a3737^0'=a3737^post_50, a3838^0'=a3838^post_50, a4343^0'=a4343^post_50, a4545^0'=a4545^post_50, a77^0'=a77^post_50, b22^0'=b22^post_50, b2626^0'=b2626^post_50, b2929^0'=b2929^post_50, b3333^0'=b3333^post_50, b3535^0'=b3535^post_50, i^0'=i^post_50, i___01313^0'=i___01313^post_50, i___01717^0'=i___01717^post_50, i___02020^0'=i___02020^post_50, i___02424^0'=i___02424^post_50, i___04040^0'=i___04040^post_50, i___04747^0'=Irql^post_50, i___099^0'=i___099^post_50, ioA^0'=ioA^post_50, ioR^0'=ioR^post_50, k1^0'=k1^post_50, k2^0'=k2^post_50, k3^0'=k3^post_50, k4^0'=k4^post_50, k5^0'=k5^post_50, keA^0'=keA^post_50, keR^0'=0, ntStatus^0'=ntStatus^post_50, pIrb^0'=pIrb^post_50, phi_io_compl^0'=phi_io_compl^post_50, phi_nSUC_ret^0'=phi_nSUC_ret^post_50, prevCancel^0'=prevCancel^post_50, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_50, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_50, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_50, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_50, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_50, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_50, [ 1<=__rho_1_^post_52 && 1<=CromData^post_27 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 && IsochResourceData^post_51<=0 && __rho_11_^post_1>=1 && i___04040^post_50==Irql^0 && keR^1_4_1==1 && keR^post_50==0 && keA^1_5==1 && keA^post_50==0 && k5^post_50==__rho_12_^post_50 && AsyncAddressData^0==AsyncAddressData^post_50 && BusResetIrp^0==BusResetIrp^post_50 && CromData^post_27==CromData^post_50 && DeviceObject^0==DeviceObject^post_50 && Irp^0==Irp^post_50 && Irql^0==Irql^post_50 && IsochDetachData^post_2==IsochDetachData^post_50 && IsochResourceData^post_51==IsochResourceData^post_50 && ResourceIrp^0==ResourceIrp^post_50 && StackSize^0==StackSize^post_50 && __rho_10_^post_15==__rho_10_^post_50 && __rho_11_^post_1==__rho_11_^post_50 && __rho_1_^post_52==__rho_1_^post_50 && __rho_2_^post_26==__rho_2_^post_50 && __rho_3_^post_21==__rho_3_^post_50 && __rho_4_^post_28==__rho_4_^post_50 && __rho_5_^post_30==__rho_5_^post_50 && __rho_666_^post_52==__rho_666_^post_50 && __rho_7_^0==__rho_7_^post_50 && __rho_8_^0==__rho_8_^post_50 && __rho_9_^0==__rho_9_^post_50 && DeviceObject^0==a11^post_50 && IsochDetachData^post_2==a1818^post_50 && a2525^0==a2525^post_50 && a2828^0==a2828^post_50 && a3131^0==a3131^post_50 && a3232^0==a3232^post_50 && a3434^0==a3434^post_50 && a3737^0==a3737^post_50 && a3838^0==a3838^post_50 && a4343^0==a4343^post_50 && a4545^0==a4545^post_50 && CromData^post_27==a77^post_50 && Irp^0==b22^post_50 && b2626^0==b2626^post_50 && b2929^0==b2929^post_50 && b3333^0==b3333^post_50 && b3535^0==b3535^post_50 && i^post_2==i^post_50 && Irql^0==i___01313^post_50 && Irql^0==i___01717^post_50 && Irql^0==i___02020^post_50 && Irql^0==i___02424^post_50 && i___04747^0==i___04747^post_50 && Irql^0==i___099^post_50 && 0==ioA^post_50 && 0==ioR^post_50 && 0==k1^post_50 && __rho_4_^post_28==k2^post_50 && 0==k3^post_50 && 0==k4^post_50 && 0==ntStatus^post_50 && pIrb^0==pIrb^post_50 && 0==phi_io_compl^post_50 && 0==phi_nSUC_ret^post_50 && prevCancel^0==prevCancel^post_50 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_50 && ret_IoAllocateIrp2727^0==ret_IoAllocateIrp2727^post_50 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_50 && 0==ret_IoSetDeviceInterfaceState44^post_50 && 0==ret_t1394Diag_PnpStopDevice33^post_50 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_50 && k5^post_50<=0 ], cost: 14+2*__rho_10_^post_15+7*__rho_5_^post_30+3*__rho_11_^post_1
    177: l34 -> l26 : BusResetIrp^0'=BusResetIrp^post_38, CromData^0'=CromData^post_27, IsochDetachData^0'=IsochDetachData^post_2, IsochResourceData^0'=IsochResourceData^post_51, __rho_10_^0'=__rho_10_^post_15, __rho_11_^0'=__rho_11_^post_1, __rho_12_^0'=k5^post_50, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_26, __rho_3_^0'=__rho_3_^post_21, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, a11^0'=DeviceObject^0, a1818^0'=IsochDetachData^post_2, a4343^0'=0, a4545^0'=BusResetIrp^post_38, a77^0'=CromData^post_27, b22^0'=Irp^0, i^0'=i^post_2, i___01313^0'=Irql^0, i___01717^0'=Irql^0, i___02020^0'=Irql^0, i___02424^0'=Irql^0, i___04040^0'=Irql^0, i___04747^0'=Irql^0, i___099^0'=Irql^0, ioA^0'=0, ioR^0'=0, k1^0'=0, k2^0'=__rho_4_^post_28, k3^0'=0, k4^0'=0, k5^0'=0, keA^0'=0, keR^0'=0, ntStatus^0'=0, phi_io_compl^0'=1, phi_nSUC_ret^0'=0, prevCancel^0'=0, ret_IoSetCancelRoutine4444^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, ret_t1394Diag_PnpStopDevice33^0'=0, [ 1<=__rho_1_^post_52 && 1<=CromData^post_27 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 && IsochResourceData^post_51<=0 && __rho_11_^post_1>=1 && k5^post_50>=1 ], cost: 14+2*k5^post_50+2*__rho_10_^post_15+7*__rho_5_^post_30+3*__rho_11_^post_1
    178: l34 -> l26 : AsyncAddressData^0'=AsyncAddressData^post_50, BusResetIrp^0'=BusResetIrp^post_50, CromData^0'=CromData^post_50, DeviceObject^0'=DeviceObject^post_50, Irp^0'=Irp^post_50, Irql^0'=Irql^post_50, IsochDetachData^0'=IsochDetachData^post_50, IsochResourceData^0'=IsochResourceData^post_50, ResourceIrp^0'=ResourceIrp^post_50, StackSize^0'=StackSize^post_50, __rho_10_^0'=__rho_10_^post_50, __rho_11_^0'=__rho_11_^post_50, __rho_12_^0'=__rho_12_^post_50, __rho_1_^0'=__rho_1_^post_50, __rho_2_^0'=__rho_2_^post_50, __rho_3_^0'=__rho_3_^post_50, __rho_4_^0'=__rho_4_^post_50, __rho_5_^0'=__rho_5_^post_50, __rho_666_^0'=__rho_666_^post_50, __rho_7_^0'=__rho_7_^post_50, __rho_8_^0'=__rho_8_^post_50, __rho_9_^0'=__rho_9_^post_50, a11^0'=a11^post_50, a1818^0'=a1818^post_50, a2525^0'=a2525^post_50, a2828^0'=a2828^post_50, a3131^0'=a3131^post_50, a3232^0'=a3232^post_50, a3434^0'=a3434^post_50, a3737^0'=a3737^post_50, a3838^0'=a3838^post_50, a4343^0'=a4343^post_50, a4545^0'=a4545^post_50, a77^0'=a77^post_50, b22^0'=b22^post_50, b2626^0'=b2626^post_50, b2929^0'=b2929^post_50, b3333^0'=b3333^post_50, b3535^0'=b3535^post_50, i^0'=i^post_50, i___01313^0'=i___01313^post_50, i___01717^0'=i___01717^post_50, i___02020^0'=i___02020^post_50, i___02424^0'=i___02424^post_50, i___04040^0'=i___04040^post_50, i___04747^0'=Irql^post_50, i___099^0'=i___099^post_50, ioA^0'=ioA^post_50, ioR^0'=ioR^post_50, k1^0'=k1^post_50, k2^0'=k2^post_50, k3^0'=k3^post_50, k4^0'=k4^post_50, k5^0'=k5^post_50, keA^0'=keA^post_50, keR^0'=0, ntStatus^0'=ntStatus^post_50, pIrb^0'=pIrb^post_50, phi_io_compl^0'=phi_io_compl^post_50, phi_nSUC_ret^0'=phi_nSUC_ret^post_50, prevCancel^0'=prevCancel^post_50, ret_ExAllocatePool3030^0'=ret_ExAllocatePool3030^post_50, ret_IoAllocateIrp2727^0'=ret_IoAllocateIrp2727^post_50, ret_IoSetCancelRoutine4444^0'=ret_IoSetCancelRoutine4444^post_50, ret_IoSetDeviceInterfaceState44^0'=ret_IoSetDeviceInterfaceState44^post_50, ret_t1394Diag_PnpStopDevice33^0'=ret_t1394Diag_PnpStopDevice33^post_50, ret_t1394_SubmitIrpSynch3636^0'=ret_t1394_SubmitIrpSynch3636^post_50, [ 1<=__rho_1_^post_52 && 1<=CromData^post_27 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 && 1<=IsochResourceData^post_51 && __rho_11_^post_1>=1 && i___04040^post_50==Irql^0 && keR^1_4_1==1 && keR^post_50==0 && keA^1_5==1 && keA^post_50==0 && k5^post_50==__rho_12_^post_50 && AsyncAddressData^0==AsyncAddressData^post_50 && BusResetIrp^0==BusResetIrp^post_50 && CromData^post_27==CromData^post_50 && DeviceObject^0==DeviceObject^post_50 && Irp^0==Irp^post_50 && Irql^0==Irql^post_50 && IsochDetachData^post_2==IsochDetachData^post_50 && IsochResourceData^post_51==IsochResourceData^post_50 && 0==ResourceIrp^post_50 && a2525^post_49==StackSize^post_50 && __rho_10_^post_15==__rho_10_^post_50 && __rho_11_^post_1==__rho_11_^post_50 && __rho_1_^post_52==__rho_1_^post_50 && __rho_2_^post_26==__rho_2_^post_50 && __rho_3_^post_21==__rho_3_^post_50 && __rho_4_^post_28==__rho_4_^post_50 && __rho_5_^post_30==__rho_5_^post_50 && __rho_666_^post_52==__rho_666_^post_50 && __rho_7_^0==__rho_7_^post_50 && __rho_8_^0==__rho_8_^post_50 && __rho_9_^0==__rho_9_^post_50 && DeviceObject^0==a11^post_50 && IsochDetachData^post_2==a1818^post_50 && a2525^post_49==a2525^post_50 && a2828^0==a2828^post_50 && a3131^0==a3131^post_50 && a3232^0==a3232^post_50 && a3434^0==a3434^post_50 && a3737^0==a3737^post_50 && a3838^0==a3838^post_50 && a4343^0==a4343^post_50 && a4545^0==a4545^post_50 && CromData^post_27==a77^post_50 && Irp^0==b22^post_50 && 0==b2626^post_50 && b2929^0==b2929^post_50 && b3333^0==b3333^post_50 && b3535^0==b3535^post_50 && i^post_2==i^post_50 && Irql^0==i___01313^post_50 && Irql^0==i___01717^post_50 && Irql^0==i___02020^post_50 && Irql^0==i___02424^post_50 && i___04747^0==i___04747^post_50 && Irql^0==i___099^post_50 && 0==ioA^post_50 && 0==ioR^post_50 && 0==k1^post_50 && __rho_4_^post_28==k2^post_50 && 0==k3^post_50 && 0==k4^post_50 && 0==ntStatus^post_50 && pIrb^post_49==pIrb^post_50 && 0==phi_io_compl^post_50 && 0==phi_nSUC_ret^post_50 && prevCancel^0==prevCancel^post_50 && ret_ExAllocatePool3030^0==ret_ExAllocatePool3030^post_50 && 0==ret_IoAllocateIrp2727^post_50 && ret_IoSetCancelRoutine4444^0==ret_IoSetCancelRoutine4444^post_50 && 0==ret_IoSetDeviceInterfaceState44^post_50 && 0==ret_t1394Diag_PnpStopDevice33^post_50 && ret_t1394_SubmitIrpSynch3636^0==ret_t1394_SubmitIrpSynch3636^post_50 && k5^post_50<=0 ], cost: 14+2*__rho_10_^post_15+7*__rho_5_^post_30+4*__rho_11_^post_1
    179: l34 -> l26 : BusResetIrp^0'=BusResetIrp^post_38, CromData^0'=CromData^post_27, IsochDetachData^0'=IsochDetachData^post_2, IsochResourceData^0'=IsochResourceData^post_51, ResourceIrp^0'=0, StackSize^0'=a2525^post_49, __rho_10_^0'=__rho_10_^post_15, __rho_11_^0'=__rho_11_^post_1, __rho_12_^0'=k5^post_50, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_26, __rho_3_^0'=__rho_3_^post_21, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, a11^0'=DeviceObject^0, a1818^0'=IsochDetachData^post_2, a2525^0'=a2525^post_49, a4343^0'=0, a4545^0'=BusResetIrp^post_38, a77^0'=CromData^post_27, b22^0'=Irp^0, b2626^0'=0, i^0'=i^post_2, i___01313^0'=Irql^0, i___01717^0'=Irql^0, i___02020^0'=Irql^0, i___02424^0'=Irql^0, i___04040^0'=Irql^0, i___04747^0'=Irql^0, i___099^0'=Irql^0, ioA^0'=0, ioR^0'=0, k1^0'=0, k2^0'=__rho_4_^post_28, k3^0'=0, k4^0'=0, k5^0'=0, keA^0'=0, keR^0'=0, ntStatus^0'=0, pIrb^0'=pIrb^post_49, phi_io_compl^0'=1, phi_nSUC_ret^0'=0, prevCancel^0'=0, ret_IoAllocateIrp2727^0'=0, ret_IoSetCancelRoutine4444^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, ret_t1394Diag_PnpStopDevice33^0'=0, [ 1<=__rho_1_^post_52 && 1<=CromData^post_27 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 && 1<=IsochResourceData^post_51 && __rho_11_^post_1>=1 && k5^post_50>=1 ], cost: 14+2*k5^post_50+2*__rho_10_^post_15+7*__rho_5_^post_30+4*__rho_11_^post_1

Applied pruning (of leafs and parallel rules):
   Start location: l34
     57: l26 -> [35] : [ -2+ntStatus^0==0 ], cost: NONTERM
     70: l26 -> [35] : [ 3<=ntStatus^0 ], cost: NONTERM
     71: l26 -> [35] : [ 1+ntStatus^0<=2 ], cost: NONTERM
    162: l34 -> l26 : BusResetIrp^0'=BusResetIrp^post_38, CromData^0'=CromData^post_27, IsochResourceData^0'=IsochResourceData^post_51, __rho_10_^0'=__rho_10_^post_15, __rho_11_^0'=__rho_11_^post_1, __rho_12_^0'=k5^post_50, __rho_1_^0'=__rho_1_^post_52, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, a11^0'=DeviceObject^0, a4343^0'=0, a4545^0'=BusResetIrp^post_38, b22^0'=Irp^0, i___01313^0'=Irql^0, i___02020^0'=Irql^0, i___02424^0'=Irql^0, i___04040^0'=Irql^0, i___04747^0'=Irql^0, i___099^0'=Irql^0, ioA^0'=0, ioR^0'=0, k1^0'=0, k2^0'=__rho_4_^post_28, k3^0'=__rho_10_^post_15, k4^0'=0, k5^0'=0, keA^0'=0, keR^0'=0, ntStatus^0'=0, phi_io_compl^0'=1, phi_nSUC_ret^0'=0, prevCancel^0'=0, ret_IoSetCancelRoutine4444^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, ret_t1394Diag_PnpStopDevice33^0'=0, [ 1<=__rho_1_^post_52 && CromData^post_27<=0 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15<=0 && IsochResourceData^post_51<=0 && __rho_11_^post_1>=1 && k5^post_50>=1 ], cost: 14+2*k5^post_50+3*__rho_5_^post_30+3*__rho_11_^post_1
    169: l34 -> l26 : BusResetIrp^0'=BusResetIrp^post_38, CromData^0'=CromData^post_27, IsochDetachData^0'=IsochDetachData^post_2, IsochResourceData^0'=IsochResourceData^post_51, ResourceIrp^0'=0, StackSize^0'=a2525^post_49, __rho_10_^0'=__rho_10_^post_15, __rho_11_^0'=__rho_11_^post_1, __rho_12_^0'=k5^post_50, __rho_1_^0'=__rho_1_^post_52, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, a11^0'=DeviceObject^0, a1818^0'=IsochDetachData^post_2, a2525^0'=a2525^post_49, a4343^0'=0, a4545^0'=BusResetIrp^post_38, b22^0'=Irp^0, b2626^0'=0, i^0'=i^post_2, i___01313^0'=Irql^0, i___01717^0'=Irql^0, i___02020^0'=Irql^0, i___02424^0'=Irql^0, i___04040^0'=Irql^0, i___04747^0'=Irql^0, i___099^0'=Irql^0, ioA^0'=0, ioR^0'=0, k1^0'=0, k2^0'=__rho_4_^post_28, k3^0'=0, k4^0'=0, k5^0'=0, keA^0'=0, keR^0'=0, ntStatus^0'=0, pIrb^0'=pIrb^post_49, phi_io_compl^0'=1, phi_nSUC_ret^0'=0, prevCancel^0'=0, ret_IoAllocateIrp2727^0'=0, ret_IoSetCancelRoutine4444^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, ret_t1394Diag_PnpStopDevice33^0'=0, [ 1<=__rho_1_^post_52 && CromData^post_27<=0 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 && 1<=IsochResourceData^post_51 && __rho_11_^post_1>=1 && k5^post_50>=1 ], cost: 14+2*k5^post_50+2*__rho_10_^post_15+3*__rho_5_^post_30+4*__rho_11_^post_1
    172: l34 -> l26 : BusResetIrp^0'=BusResetIrp^post_38, CromData^0'=CromData^post_27, IsochDetachData^0'=IsochDetachData^post_2, IsochResourceData^0'=IsochResourceData^post_51, __rho_10_^0'=__rho_10_^post_15, __rho_11_^0'=__rho_11_^post_1, __rho_12_^0'=k5^post_50, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_26, __rho_3_^0'=__rho_3_^post_21, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, a1818^0'=IsochDetachData^post_2, a4343^0'=0, a4545^0'=BusResetIrp^post_38, a77^0'=CromData^post_27, i^0'=i^post_2, i___01313^0'=Irql^0, i___01717^0'=Irql^0, i___02020^0'=Irql^0, i___02424^0'=Irql^0, i___04040^0'=Irql^0, i___04747^0'=Irql^0, i___099^0'=Irql^0, ioA^0'=0, ioR^0'=0, k1^0'=0, k2^0'=__rho_4_^post_28, k3^0'=0, k4^0'=0, k5^0'=0, keA^0'=0, keR^0'=0, ntStatus^0'=0, phi_io_compl^0'=1, phi_nSUC_ret^0'=0, prevCancel^0'=0, ret_IoSetCancelRoutine4444^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, [ __rho_1_^post_52<=0 && 1<=CromData^post_27 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 && IsochResourceData^post_51<=0 && __rho_11_^post_1>=1 && k5^post_50>=1 ], cost: 14+2*k5^post_50+2*__rho_10_^post_15+7*__rho_5_^post_30+3*__rho_11_^post_1
    175: l34 -> l26 : BusResetIrp^0'=BusResetIrp^post_38, CromData^0'=CromData^post_27, IsochDetachData^0'=IsochDetachData^post_2, __rho_10_^0'=__rho_10_^post_15, __rho_11_^0'=__rho_11_^post_1, __rho_12_^0'=k5^post_50, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_26, __rho_3_^0'=__rho_3_^post_21, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, a11^0'=DeviceObject^0, a1818^0'=IsochDetachData^post_2, a4343^0'=0, a4545^0'=BusResetIrp^post_38, a77^0'=CromData^post_27, b22^0'=Irp^0, i^0'=i^post_2, i___01313^0'=Irql^0, i___01717^0'=Irql^0, i___02020^0'=Irql^0, i___04040^0'=Irql^0, i___04747^0'=Irql^0, i___099^0'=Irql^0, ioA^0'=0, ioR^0'=0, k1^0'=0, k2^0'=__rho_4_^post_28, k3^0'=0, k4^0'=__rho_11_^post_1, k5^0'=0, keA^0'=0, keR^0'=0, ntStatus^0'=0, phi_io_compl^0'=1, phi_nSUC_ret^0'=0, prevCancel^0'=0, ret_IoSetCancelRoutine4444^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, ret_t1394Diag_PnpStopDevice33^0'=0, [ 1<=__rho_1_^post_52 && 1<=CromData^post_27 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 && __rho_11_^post_1<=0 && k5^post_50>=1 ], cost: 14+2*k5^post_50+2*__rho_10_^post_15+7*__rho_5_^post_30
    177: l34 -> l26 : BusResetIrp^0'=BusResetIrp^post_38, CromData^0'=CromData^post_27, IsochDetachData^0'=IsochDetachData^post_2, IsochResourceData^0'=IsochResourceData^post_51, __rho_10_^0'=__rho_10_^post_15, __rho_11_^0'=__rho_11_^post_1, __rho_12_^0'=k5^post_50, __rho_1_^0'=__rho_1_^post_52, __rho_2_^0'=__rho_2_^post_26, __rho_3_^0'=__rho_3_^post_21, __rho_4_^0'=__rho_4_^post_28, __rho_5_^0'=__rho_5_^post_30, __rho_666_^0'=__rho_666_^post_52, a11^0'=DeviceObject^0, a1818^0'=IsochDetachData^post_2, a4343^0'=0, a4545^0'=BusResetIrp^post_38, a77^0'=CromData^post_27, b22^0'=Irp^0, i^0'=i^post_2, i___01313^0'=Irql^0, i___01717^0'=Irql^0, i___02020^0'=Irql^0, i___02424^0'=Irql^0, i___04040^0'=Irql^0, i___04747^0'=Irql^0, i___099^0'=Irql^0, ioA^0'=0, ioR^0'=0, k1^0'=0, k2^0'=__rho_4_^post_28, k3^0'=0, k4^0'=0, k5^0'=0, keA^0'=0, keR^0'=0, ntStatus^0'=0, phi_io_compl^0'=1, phi_nSUC_ret^0'=0, prevCancel^0'=0, ret_IoSetCancelRoutine4444^0'=0, ret_IoSetDeviceInterfaceState44^0'=0, ret_t1394Diag_PnpStopDevice33^0'=0, [ 1<=__rho_1_^post_52 && 1<=CromData^post_27 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 && IsochResourceData^post_51<=0 && __rho_11_^post_1>=1 && k5^post_50>=1 ], cost: 14+2*k5^post_50+2*__rho_10_^post_15+7*__rho_5_^post_30+3*__rho_11_^post_1

Eliminated locations (on tree-shaped paths):
   Start location: l34
    180: l34 -> [35] : [ 1<=__rho_1_^post_52 && CromData^post_27<=0 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15<=0 && IsochResourceData^post_51<=0 && __rho_11_^post_1>=1 && k5^post_50>=1 ], cost: NONTERM
    181: l34 -> [35] : [ 1<=__rho_1_^post_52 && CromData^post_27<=0 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 && 1<=IsochResourceData^post_51 && __rho_11_^post_1>=1 && k5^post_50>=1 ], cost: NONTERM
    182: l34 -> [35] : [ __rho_1_^post_52<=0 && 1<=CromData^post_27 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 && IsochResourceData^post_51<=0 && __rho_11_^post_1>=1 && k5^post_50>=1 ], cost: NONTERM
    183: l34 -> [35] : [ 1<=__rho_1_^post_52 && 1<=CromData^post_27 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 && __rho_11_^post_1<=0 && k5^post_50>=1 ], cost: NONTERM
    184: l34 -> [35] : [ 1<=__rho_1_^post_52 && 1<=CromData^post_27 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 && IsochResourceData^post_51<=0 && __rho_11_^post_1>=1 && k5^post_50>=1 ], cost: NONTERM
    185: l34 -> [41] : [ 1<=__rho_1_^post_52 && CromData^post_27<=0 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15<=0 && IsochResourceData^post_51<=0 && __rho_11_^post_1>=1 && k5^post_50>=1 ], cost: 14+2*k5^post_50+3*__rho_5_^post_30+3*__rho_11_^post_1
    186: l34 -> [41] : [ 1<=__rho_1_^post_52 && CromData^post_27<=0 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 && 1<=IsochResourceData^post_51 && __rho_11_^post_1>=1 && k5^post_50>=1 ], cost: 14+2*k5^post_50+2*__rho_10_^post_15+3*__rho_5_^post_30+4*__rho_11_^post_1
    187: l34 -> [41] : [ __rho_1_^post_52<=0 && 1<=CromData^post_27 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 && IsochResourceData^post_51<=0 && __rho_11_^post_1>=1 && k5^post_50>=1 ], cost: 14+2*k5^post_50+2*__rho_10_^post_15+7*__rho_5_^post_30+3*__rho_11_^post_1
    188: l34 -> [41] : [ 1<=__rho_1_^post_52 && 1<=CromData^post_27 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 && __rho_11_^post_1<=0 && k5^post_50>=1 ], cost: 14+2*k5^post_50+2*__rho_10_^post_15+7*__rho_5_^post_30
    189: l34 -> [41] : [ 1<=__rho_1_^post_52 && 1<=CromData^post_27 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 && IsochResourceData^post_51<=0 && __rho_11_^post_1>=1 && k5^post_50>=1 ], cost: 14+2*k5^post_50+2*__rho_10_^post_15+7*__rho_5_^post_30+3*__rho_11_^post_1

### Computing asymptotic complexity ###

Fully simplified ITS problem
   Start location: l34
    180: l34 -> [35] : [ 1<=__rho_1_^post_52 && CromData^post_27<=0 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15<=0 && IsochResourceData^post_51<=0 && __rho_11_^post_1>=1 && k5^post_50>=1 ], cost: NONTERM
    181: l34 -> [35] : [ 1<=__rho_1_^post_52 && CromData^post_27<=0 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 && 1<=IsochResourceData^post_51 && __rho_11_^post_1>=1 && k5^post_50>=1 ], cost: NONTERM
    182: l34 -> [35] : [ __rho_1_^post_52<=0 && 1<=CromData^post_27 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 && IsochResourceData^post_51<=0 && __rho_11_^post_1>=1 && k5^post_50>=1 ], cost: NONTERM
    183: l34 -> [35] : [ 1<=__rho_1_^post_52 && 1<=CromData^post_27 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 && __rho_11_^post_1<=0 && k5^post_50>=1 ], cost: NONTERM
    184: l34 -> [35] : [ 1<=__rho_1_^post_52 && 1<=CromData^post_27 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 && IsochResourceData^post_51<=0 && __rho_11_^post_1>=1 && k5^post_50>=1 ], cost: NONTERM
    185: l34 -> [41] : [ 1<=__rho_1_^post_52 && CromData^post_27<=0 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15<=0 && IsochResourceData^post_51<=0 && __rho_11_^post_1>=1 && k5^post_50>=1 ], cost: 14+2*k5^post_50+3*__rho_5_^post_30+3*__rho_11_^post_1
    186: l34 -> [41] : [ 1<=__rho_1_^post_52 && CromData^post_27<=0 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 && 1<=IsochResourceData^post_51 && __rho_11_^post_1>=1 && k5^post_50>=1 ], cost: 14+2*k5^post_50+2*__rho_10_^post_15+3*__rho_5_^post_30+4*__rho_11_^post_1
    187: l34 -> [41] : [ __rho_1_^post_52<=0 && 1<=CromData^post_27 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 && IsochResourceData^post_51<=0 && __rho_11_^post_1>=1 && k5^post_50>=1 ], cost: 14+2*k5^post_50+2*__rho_10_^post_15+7*__rho_5_^post_30+3*__rho_11_^post_1
    188: l34 -> [41] : [ 1<=__rho_1_^post_52 && 1<=CromData^post_27 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 && __rho_11_^post_1<=0 && k5^post_50>=1 ], cost: 14+2*k5^post_50+2*__rho_10_^post_15+7*__rho_5_^post_30
    189: l34 -> [41] : [ 1<=__rho_1_^post_52 && 1<=CromData^post_27 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 && IsochResourceData^post_51<=0 && __rho_11_^post_1>=1 && k5^post_50>=1 ], cost: 14+2*k5^post_50+2*__rho_10_^post_15+7*__rho_5_^post_30+3*__rho_11_^post_1

Computing asymptotic complexity for rule 183
   Guard is satisfiable, yielding nontermination
   Resulting cost NONTERM has complexity: Nonterm

Found new complexity Nonterm.

Obtained the following overall complexity (w.r.t. the length of the input n):
   Complexity:  Nonterm
   Cpx degree:  Nonterm
   Solved cost: NONTERM
   Rule cost:   NONTERM
   Rule guard:  [ 1<=__rho_1_^post_52 && 1<=CromData^post_27 && __rho_5_^post_30>=1 && __rho_4_^post_28<=0 && __rho_10_^post_15>=1 && __rho_11_^post_1<=0 && k5^post_50>=1 ]

NO