NO

### Pre-processing the ITS problem ###

Initial linear ITS problem
   Start location: l12
      0: l0 -> l1 : Dc_6^0'=Dc_6^post_1, InterfaceType_5^0'=InterfaceType_5^post_1, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_1, Result_4^0'=Result_4^post_1, ___cil_tmp2_11^0'=___cil_tmp2_11^post_1, ___retres1_10^0'=___retres1_10^post_1, cnt_29^0'=cnt_29^post_1, cnt_34^0'=cnt_34^post_1, ct_115^0'=ct_115^post_1, ct_15^0'=ct_15^post_1, ct_64^0'=ct_64^post_1, fdoExtension_7^0'=fdoExtension_7^post_1, lt_12^0'=lt_12^post_1, lt_13^0'=lt_13^post_1, lt_14^0'=lt_14^post_1, lt_16^0'=lt_16^post_1, lt_17^0'=lt_17^post_1, lt_18^0'=lt_18^post_1, lt_19^0'=lt_19^post_1, lt_20^0'=lt_20^post_1, ntStatus_8^0'=ntStatus_8^post_1, [ MaximumInterfaceType_9^post_1==MaximumInterfaceType_9^post_1 && ntStatus_8^post_1==ntStatus_8^post_1 && fdoExtension_7^post_1==fdoExtension_7^post_1 && Dc_6^post_1==Dc_6^post_1 && InterfaceType_5^post_1==InterfaceType_5^post_1 && Result_4^0==Result_4^post_1 && ___cil_tmp2_11^0==___cil_tmp2_11^post_1 && ___retres1_10^0==___retres1_10^post_1 && cnt_29^0==cnt_29^post_1 && cnt_34^0==cnt_34^post_1 && ct_115^0==ct_115^post_1 && ct_15^0==ct_15^post_1 && ct_64^0==ct_64^post_1 && lt_12^0==lt_12^post_1 && lt_13^0==lt_13^post_1 && lt_14^0==lt_14^post_1 && lt_16^0==lt_16^post_1 && lt_17^0==lt_17^post_1 && lt_18^0==lt_18^post_1 && lt_19^0==lt_19^post_1 && lt_20^0==lt_20^post_1 ], cost: 1
      1: l1 -> l2 : Dc_6^0'=Dc_6^post_2, InterfaceType_5^0'=InterfaceType_5^post_2, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_2, Result_4^0'=Result_4^post_2, ___cil_tmp2_11^0'=___cil_tmp2_11^post_2, ___retres1_10^0'=___retres1_10^post_2, cnt_29^0'=cnt_29^post_2, cnt_34^0'=cnt_34^post_2, ct_115^0'=ct_115^post_2, ct_15^0'=ct_15^post_2, ct_64^0'=ct_64^post_2, fdoExtension_7^0'=fdoExtension_7^post_2, lt_12^0'=lt_12^post_2, lt_13^0'=lt_13^post_2, lt_14^0'=lt_14^post_2, lt_16^0'=lt_16^post_2, lt_17^0'=lt_17^post_2, lt_18^0'=lt_18^post_2, lt_19^0'=lt_19^post_2, lt_20^0'=lt_20^post_2, ntStatus_8^0'=ntStatus_8^post_2, [ lt_19^1_1==cnt_29^0 && lt_20^1_1==cnt_34^0 && 0<=-1+lt_20^1_1-lt_19^1_1 && lt_19^post_2==lt_19^post_2 && lt_20^post_2==lt_20^post_2 && lt_18^1_1==cnt_29^0 && lt_18^post_2==lt_18^post_2 && lt_16^1_1==1+cnt_29^0 && lt_17^1_1==cnt_34^0 && 1+lt_16^1_1-lt_17^1_1<=0 && lt_16^post_2==lt_16^post_2 && lt_17^post_2==lt_17^post_2 && ct_15^1_1==ct_15^1_1 && ct_15^post_2==ct_15^post_2 && lt_14^1_1==ct_115^0 && lt_14^1_1<=0 && lt_14^post_2==lt_14^post_2 && Dc_6^0==Dc_6^post_2 && InterfaceType_5^0==InterfaceType_5^post_2 && MaximumInterfaceType_9^0==MaximumInterfaceType_9^post_2 && Result_4^0==Result_4^post_2 && ___cil_tmp2_11^0==___cil_tmp2_11^post_2 && ___retres1_10^0==___retres1_10^post_2 && cnt_29^0==cnt_29^post_2 && cnt_34^0==cnt_34^post_2 && ct_115^0==ct_115^post_2 && ct_64^0==ct_64^post_2 && fdoExtension_7^0==fdoExtension_7^post_2 && lt_12^0==lt_12^post_2 && lt_13^0==lt_13^post_2 && ntStatus_8^0==ntStatus_8^post_2 ], cost: 1
      3: l1 -> l3 : Dc_6^0'=Dc_6^post_4, InterfaceType_5^0'=InterfaceType_5^post_4, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_4, Result_4^0'=Result_4^post_4, ___cil_tmp2_11^0'=___cil_tmp2_11^post_4, ___retres1_10^0'=___retres1_10^post_4, cnt_29^0'=cnt_29^post_4, cnt_34^0'=cnt_34^post_4, ct_115^0'=ct_115^post_4, ct_15^0'=ct_15^post_4, ct_64^0'=ct_64^post_4, fdoExtension_7^0'=fdoExtension_7^post_4, lt_12^0'=lt_12^post_4, lt_13^0'=lt_13^post_4, lt_14^0'=lt_14^post_4, lt_16^0'=lt_16^post_4, lt_17^0'=lt_17^post_4, lt_18^0'=lt_18^post_4, lt_19^0'=lt_19^post_4, lt_20^0'=lt_20^post_4, ntStatus_8^0'=ntStatus_8^post_4, [ lt_19^1_2_1==cnt_29^0 && lt_20^1_2_1==cnt_34^0 && 0<=-1+lt_20^1_2_1-lt_19^1_2_1 && lt_19^post_4==lt_19^post_4 && lt_20^post_4==lt_20^post_4 && lt_18^1_2_1==cnt_29^0 && lt_18^post_4==lt_18^post_4 && lt_16^1_2_1==1+cnt_29^0 && lt_17^1_2_1==cnt_34^0 && 1+lt_16^1_2_1-lt_17^1_2_1<=0 && lt_16^post_4==lt_16^post_4 && lt_17^post_4==lt_17^post_4 && ct_15^1_2==ct_15^1_2 && ct_15^post_4==ct_15^post_4 && lt_14^1_2_1==ct_115^0 && 0<=-1+lt_14^1_2_1 && lt_14^post_4==lt_14^post_4 && lt_13^1_1==ct_115^0 && lt_13^1_1<=256 && 256<=lt_13^1_1 && lt_13^post_4==lt_13^post_4 && Dc_6^0==Dc_6^post_4 && InterfaceType_5^0==InterfaceType_5^post_4 && MaximumInterfaceType_9^0==MaximumInterfaceType_9^post_4 && Result_4^0==Result_4^post_4 && ___cil_tmp2_11^0==___cil_tmp2_11^post_4 && ___retres1_10^0==___retres1_10^post_4 && cnt_29^0==cnt_29^post_4 && cnt_34^0==cnt_34^post_4 && ct_115^0==ct_115^post_4 && ct_64^0==ct_64^post_4 && fdoExtension_7^0==fdoExtension_7^post_4 && lt_12^0==lt_12^post_4 && ntStatus_8^0==ntStatus_8^post_4 ], cost: 1
      5: l1 -> l4 : Dc_6^0'=Dc_6^post_6, InterfaceType_5^0'=InterfaceType_5^post_6, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_6, Result_4^0'=Result_4^post_6, ___cil_tmp2_11^0'=___cil_tmp2_11^post_6, ___retres1_10^0'=___retres1_10^post_6, cnt_29^0'=cnt_29^post_6, cnt_34^0'=cnt_34^post_6, ct_115^0'=ct_115^post_6, ct_15^0'=ct_15^post_6, ct_64^0'=ct_64^post_6, fdoExtension_7^0'=fdoExtension_7^post_6, lt_12^0'=lt_12^post_6, lt_13^0'=lt_13^post_6, lt_14^0'=lt_14^post_6, lt_16^0'=lt_16^post_6, lt_17^0'=lt_17^post_6, lt_18^0'=lt_18^post_6, lt_19^0'=lt_19^post_6, lt_20^0'=lt_20^post_6, ntStatus_8^0'=ntStatus_8^post_6, [ lt_19^1_3_1==cnt_29^0 && lt_20^1_3_1==cnt_34^0 && 0<=-1-lt_19^1_3_1+lt_20^1_3_1 && lt_19^post_6==lt_19^post_6 && lt_20^post_6==lt_20^post_6 && lt_18^1_3_1==cnt_29^0 && lt_18^post_6==lt_18^post_6 && lt_16^1_3_1==1+cnt_29^0 && lt_17^1_3_1==cnt_34^0 && 0<=lt_16^1_3_1-lt_17^1_3_1 && lt_16^post_6==lt_16^post_6 && lt_17^post_6==lt_17^post_6 && ct_15^1_3==ct_15^1_3 && ct_15^post_6==ct_15^post_6 && lt_14^1_3_1==ct_64^0 && lt_14^1_3_1<=0 && lt_14^post_6==lt_14^post_6 && Dc_6^0==Dc_6^post_6 && InterfaceType_5^0==InterfaceType_5^post_6 && MaximumInterfaceType_9^0==MaximumInterfaceType_9^post_6 && Result_4^0==Result_4^post_6 && ___cil_tmp2_11^0==___cil_tmp2_11^post_6 && ___retres1_10^0==___retres1_10^post_6 && cnt_29^0==cnt_29^post_6 && cnt_34^0==cnt_34^post_6 && ct_115^0==ct_115^post_6 && ct_64^0==ct_64^post_6 && fdoExtension_7^0==fdoExtension_7^post_6 && lt_12^0==lt_12^post_6 && lt_13^0==lt_13^post_6 && ntStatus_8^0==ntStatus_8^post_6 ], cost: 1
      7: l1 -> l5 : Dc_6^0'=Dc_6^post_8, InterfaceType_5^0'=InterfaceType_5^post_8, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_8, Result_4^0'=Result_4^post_8, ___cil_tmp2_11^0'=___cil_tmp2_11^post_8, ___retres1_10^0'=___retres1_10^post_8, cnt_29^0'=cnt_29^post_8, cnt_34^0'=cnt_34^post_8, ct_115^0'=ct_115^post_8, ct_15^0'=ct_15^post_8, ct_64^0'=ct_64^post_8, fdoExtension_7^0'=fdoExtension_7^post_8, lt_12^0'=lt_12^post_8, lt_13^0'=lt_13^post_8, lt_14^0'=lt_14^post_8, lt_16^0'=lt_16^post_8, lt_17^0'=lt_17^post_8, lt_18^0'=lt_18^post_8, lt_19^0'=lt_19^post_8, lt_20^0'=lt_20^post_8, ntStatus_8^0'=ntStatus_8^post_8, [ lt_19^1_4_1==cnt_29^0 && lt_20^1_4_1==cnt_34^0 && 0<=-1-lt_19^1_4_1+lt_20^1_4_1 && lt_19^post_8==lt_19^post_8 && lt_20^post_8==lt_20^post_8 && lt_18^1_4_1==cnt_29^0 && lt_18^post_8==lt_18^post_8 && lt_16^1_4_1==1+cnt_29^0 && lt_17^1_4_1==cnt_34^0 && 0<=lt_16^1_4_1-lt_17^1_4_1 && lt_16^post_8==lt_16^post_8 && lt_17^post_8==lt_17^post_8 && ct_15^1_4==ct_15^1_4 && ct_15^post_8==ct_15^post_8 && lt_14^1_4_1==ct_64^0 && 0<=-1+lt_14^1_4_1 && lt_14^post_8==lt_14^post_8 && lt_13^1_2_1==ct_64^0 && lt_13^1_2_1<=256 && 256<=lt_13^1_2_1 && lt_13^post_8==lt_13^post_8 && Dc_6^0==Dc_6^post_8 && InterfaceType_5^0==InterfaceType_5^post_8 && MaximumInterfaceType_9^0==MaximumInterfaceType_9^post_8 && Result_4^0==Result_4^post_8 && ___cil_tmp2_11^0==___cil_tmp2_11^post_8 && ___retres1_10^0==___retres1_10^post_8 && cnt_29^0==cnt_29^post_8 && cnt_34^0==cnt_34^post_8 && ct_115^0==ct_115^post_8 && ct_64^0==ct_64^post_8 && fdoExtension_7^0==fdoExtension_7^post_8 && lt_12^0==lt_12^post_8 && ntStatus_8^0==ntStatus_8^post_8 ], cost: 1
      9: l1 -> l7 : Dc_6^0'=Dc_6^post_10, InterfaceType_5^0'=InterfaceType_5^post_10, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_10, Result_4^0'=Result_4^post_10, ___cil_tmp2_11^0'=___cil_tmp2_11^post_10, ___retres1_10^0'=___retres1_10^post_10, cnt_29^0'=cnt_29^post_10, cnt_34^0'=cnt_34^post_10, ct_115^0'=ct_115^post_10, ct_15^0'=ct_15^post_10, ct_64^0'=ct_64^post_10, fdoExtension_7^0'=fdoExtension_7^post_10, lt_12^0'=lt_12^post_10, lt_13^0'=lt_13^post_10, lt_14^0'=lt_14^post_10, lt_16^0'=lt_16^post_10, lt_17^0'=lt_17^post_10, lt_18^0'=lt_18^post_10, lt_19^0'=lt_19^post_10, lt_20^0'=lt_20^post_10, ntStatus_8^0'=ntStatus_8^post_10, [ lt_19^1_5_1==cnt_29^0 && lt_20^1_5_1==cnt_34^0 && 0<=-1-lt_19^1_5_1+lt_20^1_5_1 && lt_19^post_10==lt_19^post_10 && lt_20^post_10==lt_20^post_10 && lt_18^1_5_1==cnt_29^0 && lt_18^post_10==lt_18^post_10 && lt_16^1_5_1==1+cnt_29^0 && lt_17^1_5_1==cnt_34^0 && 1-lt_17^1_5_1+lt_16^1_5_1<=0 && lt_16^post_10==lt_16^post_10 && lt_17^post_10==lt_17^post_10 && ct_15^1_5==ct_15^1_5 && ct_15^post_10==ct_15^post_10 && lt_14^1_5_1==ct_115^0 && 0<=-1+lt_14^1_5_1 && lt_14^post_10==lt_14^post_10 && lt_13^post_10==ct_115^0 && Dc_6^0==Dc_6^post_10 && InterfaceType_5^0==InterfaceType_5^post_10 && MaximumInterfaceType_9^0==MaximumInterfaceType_9^post_10 && Result_4^0==Result_4^post_10 && ___cil_tmp2_11^0==___cil_tmp2_11^post_10 && ___retres1_10^0==___retres1_10^post_10 && cnt_29^0==cnt_29^post_10 && cnt_34^0==cnt_34^post_10 && ct_115^0==ct_115^post_10 && ct_64^0==ct_64^post_10 && fdoExtension_7^0==fdoExtension_7^post_10 && lt_12^0==lt_12^post_10 && ntStatus_8^0==ntStatus_8^post_10 ], cost: 1
     13: l1 -> l9 : Dc_6^0'=Dc_6^post_14, InterfaceType_5^0'=InterfaceType_5^post_14, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_14, Result_4^0'=Result_4^post_14, ___cil_tmp2_11^0'=___cil_tmp2_11^post_14, ___retres1_10^0'=___retres1_10^post_14, cnt_29^0'=cnt_29^post_14, cnt_34^0'=cnt_34^post_14, ct_115^0'=ct_115^post_14, ct_15^0'=ct_15^post_14, ct_64^0'=ct_64^post_14, fdoExtension_7^0'=fdoExtension_7^post_14, lt_12^0'=lt_12^post_14, lt_13^0'=lt_13^post_14, lt_14^0'=lt_14^post_14, lt_16^0'=lt_16^post_14, lt_17^0'=lt_17^post_14, lt_18^0'=lt_18^post_14, lt_19^0'=lt_19^post_14, lt_20^0'=lt_20^post_14, ntStatus_8^0'=ntStatus_8^post_14, [ lt_19^1_6_1==cnt_29^0 && lt_20^1_6_1==cnt_34^0 && 0<=-1-lt_19^1_6_1+lt_20^1_6_1 && lt_19^post_14==lt_19^post_14 && lt_20^post_14==lt_20^post_14 && lt_18^1_6_1==cnt_29^0 && lt_18^post_14==lt_18^post_14 && lt_16^1_6_1==1+cnt_29^0 && lt_17^1_6_1==cnt_34^0 && 0<=-lt_17^1_6_1+lt_16^1_6_1 && lt_16^post_14==lt_16^post_14 && lt_17^post_14==lt_17^post_14 && ct_15^1_6==ct_15^1_6 && ct_15^post_14==ct_15^post_14 && lt_14^1_6_1==ct_64^0 && 0<=-1+lt_14^1_6_1 && lt_14^post_14==lt_14^post_14 && lt_13^post_14==ct_64^0 && Dc_6^0==Dc_6^post_14 && InterfaceType_5^0==InterfaceType_5^post_14 && MaximumInterfaceType_9^0==MaximumInterfaceType_9^post_14 && Result_4^0==Result_4^post_14 && ___cil_tmp2_11^0==___cil_tmp2_11^post_14 && ___retres1_10^0==___retres1_10^post_14 && cnt_29^0==cnt_29^post_14 && cnt_34^0==cnt_34^post_14 && ct_115^0==ct_115^post_14 && ct_64^0==ct_64^post_14 && fdoExtension_7^0==fdoExtension_7^post_14 && lt_12^0==lt_12^post_14 && ntStatus_8^0==ntStatus_8^post_14 ], cost: 1
     17: l1 -> l11 : Dc_6^0'=Dc_6^post_18, InterfaceType_5^0'=InterfaceType_5^post_18, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_18, Result_4^0'=Result_4^post_18, ___cil_tmp2_11^0'=___cil_tmp2_11^post_18, ___retres1_10^0'=___retres1_10^post_18, cnt_29^0'=cnt_29^post_18, cnt_34^0'=cnt_34^post_18, ct_115^0'=ct_115^post_18, ct_15^0'=ct_15^post_18, ct_64^0'=ct_64^post_18, fdoExtension_7^0'=fdoExtension_7^post_18, lt_12^0'=lt_12^post_18, lt_13^0'=lt_13^post_18, lt_14^0'=lt_14^post_18, lt_16^0'=lt_16^post_18, lt_17^0'=lt_17^post_18, lt_18^0'=lt_18^post_18, lt_19^0'=lt_19^post_18, lt_20^0'=lt_20^post_18, ntStatus_8^0'=ntStatus_8^post_18, [ lt_19^1_6_2==cnt_29^0 && lt_20^1_7_1==cnt_34^0 && lt_20^1_7_1-lt_19^1_6_2<=0 && lt_19^post_18==lt_19^post_18 && lt_20^post_18==lt_20^post_18 && ___retres1_10^post_18==0 && ___cil_tmp2_11^post_18==___retres1_10^post_18 && Result_4^post_18==___cil_tmp2_11^post_18 && Dc_6^0==Dc_6^post_18 && InterfaceType_5^0==InterfaceType_5^post_18 && MaximumInterfaceType_9^0==MaximumInterfaceType_9^post_18 && cnt_29^0==cnt_29^post_18 && cnt_34^0==cnt_34^post_18 && ct_115^0==ct_115^post_18 && ct_15^0==ct_15^post_18 && ct_64^0==ct_64^post_18 && fdoExtension_7^0==fdoExtension_7^post_18 && lt_12^0==lt_12^post_18 && lt_13^0==lt_13^post_18 && lt_14^0==lt_14^post_18 && lt_16^0==lt_16^post_18 && lt_17^0==lt_17^post_18 && lt_18^0==lt_18^post_18 && ntStatus_8^0==ntStatus_8^post_18 ], cost: 1
      2: l2 -> l1 : Dc_6^0'=Dc_6^post_3, InterfaceType_5^0'=InterfaceType_5^post_3, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_3, Result_4^0'=Result_4^post_3, ___cil_tmp2_11^0'=___cil_tmp2_11^post_3, ___retres1_10^0'=___retres1_10^post_3, cnt_29^0'=cnt_29^post_3, cnt_34^0'=cnt_34^post_3, ct_115^0'=ct_115^post_3, ct_15^0'=ct_15^post_3, ct_64^0'=ct_64^post_3, fdoExtension_7^0'=fdoExtension_7^post_3, lt_12^0'=lt_12^post_3, lt_13^0'=lt_13^post_3, lt_14^0'=lt_14^post_3, lt_16^0'=lt_16^post_3, lt_17^0'=lt_17^post_3, lt_18^0'=lt_18^post_3, lt_19^0'=lt_19^post_3, lt_20^0'=lt_20^post_3, ntStatus_8^0'=ntStatus_8^post_3, [ Dc_6^0==Dc_6^post_3 && InterfaceType_5^0==InterfaceType_5^post_3 && MaximumInterfaceType_9^0==MaximumInterfaceType_9^post_3 && Result_4^0==Result_4^post_3 && ___cil_tmp2_11^0==___cil_tmp2_11^post_3 && ___retres1_10^0==___retres1_10^post_3 && cnt_29^0==cnt_29^post_3 && cnt_34^0==cnt_34^post_3 && ct_115^0==ct_115^post_3 && ct_15^0==ct_15^post_3 && ct_64^0==ct_64^post_3 && fdoExtension_7^0==fdoExtension_7^post_3 && lt_12^0==lt_12^post_3 && lt_13^0==lt_13^post_3 && lt_14^0==lt_14^post_3 && lt_16^0==lt_16^post_3 && lt_17^0==lt_17^post_3 && lt_18^0==lt_18^post_3 && lt_19^0==lt_19^post_3 && lt_20^0==lt_20^post_3 && ntStatus_8^0==ntStatus_8^post_3 ], cost: 1
      4: l3 -> l1 : Dc_6^0'=Dc_6^post_5, InterfaceType_5^0'=InterfaceType_5^post_5, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_5, Result_4^0'=Result_4^post_5, ___cil_tmp2_11^0'=___cil_tmp2_11^post_5, ___retres1_10^0'=___retres1_10^post_5, cnt_29^0'=cnt_29^post_5, cnt_34^0'=cnt_34^post_5, ct_115^0'=ct_115^post_5, ct_15^0'=ct_15^post_5, ct_64^0'=ct_64^post_5, fdoExtension_7^0'=fdoExtension_7^post_5, lt_12^0'=lt_12^post_5, lt_13^0'=lt_13^post_5, lt_14^0'=lt_14^post_5, lt_16^0'=lt_16^post_5, lt_17^0'=lt_17^post_5, lt_18^0'=lt_18^post_5, lt_19^0'=lt_19^post_5, lt_20^0'=lt_20^post_5, ntStatus_8^0'=ntStatus_8^post_5, [ Dc_6^0==Dc_6^post_5 && InterfaceType_5^0==InterfaceType_5^post_5 && MaximumInterfaceType_9^0==MaximumInterfaceType_9^post_5 && Result_4^0==Result_4^post_5 && ___cil_tmp2_11^0==___cil_tmp2_11^post_5 && ___retres1_10^0==___retres1_10^post_5 && cnt_29^0==cnt_29^post_5 && cnt_34^0==cnt_34^post_5 && ct_115^0==ct_115^post_5 && ct_15^0==ct_15^post_5 && ct_64^0==ct_64^post_5 && fdoExtension_7^0==fdoExtension_7^post_5 && lt_12^0==lt_12^post_5 && lt_13^0==lt_13^post_5 && lt_14^0==lt_14^post_5 && lt_16^0==lt_16^post_5 && lt_17^0==lt_17^post_5 && lt_18^0==lt_18^post_5 && lt_19^0==lt_19^post_5 && lt_20^0==lt_20^post_5 && ntStatus_8^0==ntStatus_8^post_5 ], cost: 1
      6: l4 -> l1 : Dc_6^0'=Dc_6^post_7, InterfaceType_5^0'=InterfaceType_5^post_7, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_7, Result_4^0'=Result_4^post_7, ___cil_tmp2_11^0'=___cil_tmp2_11^post_7, ___retres1_10^0'=___retres1_10^post_7, cnt_29^0'=cnt_29^post_7, cnt_34^0'=cnt_34^post_7, ct_115^0'=ct_115^post_7, ct_15^0'=ct_15^post_7, ct_64^0'=ct_64^post_7, fdoExtension_7^0'=fdoExtension_7^post_7, lt_12^0'=lt_12^post_7, lt_13^0'=lt_13^post_7, lt_14^0'=lt_14^post_7, lt_16^0'=lt_16^post_7, lt_17^0'=lt_17^post_7, lt_18^0'=lt_18^post_7, lt_19^0'=lt_19^post_7, lt_20^0'=lt_20^post_7, ntStatus_8^0'=ntStatus_8^post_7, [ Dc_6^0==Dc_6^post_7 && InterfaceType_5^0==InterfaceType_5^post_7 && MaximumInterfaceType_9^0==MaximumInterfaceType_9^post_7 && Result_4^0==Result_4^post_7 && ___cil_tmp2_11^0==___cil_tmp2_11^post_7 && ___retres1_10^0==___retres1_10^post_7 && cnt_29^0==cnt_29^post_7 && cnt_34^0==cnt_34^post_7 && ct_115^0==ct_115^post_7 && ct_15^0==ct_15^post_7 && ct_64^0==ct_64^post_7 && fdoExtension_7^0==fdoExtension_7^post_7 && lt_12^0==lt_12^post_7 && lt_13^0==lt_13^post_7 && lt_14^0==lt_14^post_7 && lt_16^0==lt_16^post_7 && lt_17^0==lt_17^post_7 && lt_18^0==lt_18^post_7 && lt_19^0==lt_19^post_7 && lt_20^0==lt_20^post_7 && ntStatus_8^0==ntStatus_8^post_7 ], cost: 1
      8: l5 -> l1 : Dc_6^0'=Dc_6^post_9, InterfaceType_5^0'=InterfaceType_5^post_9, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_9, Result_4^0'=Result_4^post_9, ___cil_tmp2_11^0'=___cil_tmp2_11^post_9, ___retres1_10^0'=___retres1_10^post_9, cnt_29^0'=cnt_29^post_9, cnt_34^0'=cnt_34^post_9, ct_115^0'=ct_115^post_9, ct_15^0'=ct_15^post_9, ct_64^0'=ct_64^post_9, fdoExtension_7^0'=fdoExtension_7^post_9, lt_12^0'=lt_12^post_9, lt_13^0'=lt_13^post_9, lt_14^0'=lt_14^post_9, lt_16^0'=lt_16^post_9, lt_17^0'=lt_17^post_9, lt_18^0'=lt_18^post_9, lt_19^0'=lt_19^post_9, lt_20^0'=lt_20^post_9, ntStatus_8^0'=ntStatus_8^post_9, [ Dc_6^0==Dc_6^post_9 && InterfaceType_5^0==InterfaceType_5^post_9 && MaximumInterfaceType_9^0==MaximumInterfaceType_9^post_9 && Result_4^0==Result_4^post_9 && ___cil_tmp2_11^0==___cil_tmp2_11^post_9 && ___retres1_10^0==___retres1_10^post_9 && cnt_29^0==cnt_29^post_9 && cnt_34^0==cnt_34^post_9 && ct_115^0==ct_115^post_9 && ct_15^0==ct_15^post_9 && ct_64^0==ct_64^post_9 && fdoExtension_7^0==fdoExtension_7^post_9 && lt_12^0==lt_12^post_9 && lt_13^0==lt_13^post_9 && lt_14^0==lt_14^post_9 && lt_16^0==lt_16^post_9 && lt_17^0==lt_17^post_9 && lt_18^0==lt_18^post_9 && lt_19^0==lt_19^post_9 && lt_20^0==lt_20^post_9 && ntStatus_8^0==ntStatus_8^post_9 ], cost: 1
     10: l7 -> l8 : Dc_6^0'=Dc_6^post_11, InterfaceType_5^0'=InterfaceType_5^post_11, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_11, Result_4^0'=Result_4^post_11, ___cil_tmp2_11^0'=___cil_tmp2_11^post_11, ___retres1_10^0'=___retres1_10^post_11, cnt_29^0'=cnt_29^post_11, cnt_34^0'=cnt_34^post_11, ct_115^0'=ct_115^post_11, ct_15^0'=ct_15^post_11, ct_64^0'=ct_64^post_11, fdoExtension_7^0'=fdoExtension_7^post_11, lt_12^0'=lt_12^post_11, lt_13^0'=lt_13^post_11, lt_14^0'=lt_14^post_11, lt_16^0'=lt_16^post_11, lt_17^0'=lt_17^post_11, lt_18^0'=lt_18^post_11, lt_19^0'=lt_19^post_11, lt_20^0'=lt_20^post_11, ntStatus_8^0'=ntStatus_8^post_11, [ 1+lt_13^0<=256 && Dc_6^0==Dc_6^post_11 && InterfaceType_5^0==InterfaceType_5^post_11 && MaximumInterfaceType_9^0==MaximumInterfaceType_9^post_11 && Result_4^0==Result_4^post_11 && ___cil_tmp2_11^0==___cil_tmp2_11^post_11 && ___retres1_10^0==___retres1_10^post_11 && cnt_29^0==cnt_29^post_11 && cnt_34^0==cnt_34^post_11 && ct_115^0==ct_115^post_11 && ct_15^0==ct_15^post_11 && ct_64^0==ct_64^post_11 && fdoExtension_7^0==fdoExtension_7^post_11 && lt_12^0==lt_12^post_11 && lt_13^0==lt_13^post_11 && lt_14^0==lt_14^post_11 && lt_16^0==lt_16^post_11 && lt_17^0==lt_17^post_11 && lt_18^0==lt_18^post_11 && lt_19^0==lt_19^post_11 && lt_20^0==lt_20^post_11 && ntStatus_8^0==ntStatus_8^post_11 ], cost: 1
     11: l7 -> l8 : Dc_6^0'=Dc_6^post_12, InterfaceType_5^0'=InterfaceType_5^post_12, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_12, Result_4^0'=Result_4^post_12, ___cil_tmp2_11^0'=___cil_tmp2_11^post_12, ___retres1_10^0'=___retres1_10^post_12, cnt_29^0'=cnt_29^post_12, cnt_34^0'=cnt_34^post_12, ct_115^0'=ct_115^post_12, ct_15^0'=ct_15^post_12, ct_64^0'=ct_64^post_12, fdoExtension_7^0'=fdoExtension_7^post_12, lt_12^0'=lt_12^post_12, lt_13^0'=lt_13^post_12, lt_14^0'=lt_14^post_12, lt_16^0'=lt_16^post_12, lt_17^0'=lt_17^post_12, lt_18^0'=lt_18^post_12, lt_19^0'=lt_19^post_12, lt_20^0'=lt_20^post_12, ntStatus_8^0'=ntStatus_8^post_12, [ 257<=lt_13^0 && Dc_6^0==Dc_6^post_12 && InterfaceType_5^0==InterfaceType_5^post_12 && MaximumInterfaceType_9^0==MaximumInterfaceType_9^post_12 && Result_4^0==Result_4^post_12 && ___cil_tmp2_11^0==___cil_tmp2_11^post_12 && ___retres1_10^0==___retres1_10^post_12 && cnt_29^0==cnt_29^post_12 && cnt_34^0==cnt_34^post_12 && ct_115^0==ct_115^post_12 && ct_15^0==ct_15^post_12 && ct_64^0==ct_64^post_12 && fdoExtension_7^0==fdoExtension_7^post_12 && lt_12^0==lt_12^post_12 && lt_13^0==lt_13^post_12 && lt_14^0==lt_14^post_12 && lt_16^0==lt_16^post_12 && lt_17^0==lt_17^post_12 && lt_18^0==lt_18^post_12 && lt_19^0==lt_19^post_12 && lt_20^0==lt_20^post_12 && ntStatus_8^0==ntStatus_8^post_12 ], cost: 1
     12: l8 -> l6 : Dc_6^0'=Dc_6^post_13, InterfaceType_5^0'=InterfaceType_5^post_13, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_13, Result_4^0'=Result_4^post_13, ___cil_tmp2_11^0'=___cil_tmp2_11^post_13, ___retres1_10^0'=___retres1_10^post_13, cnt_29^0'=cnt_29^post_13, cnt_34^0'=cnt_34^post_13, ct_115^0'=ct_115^post_13, ct_15^0'=ct_15^post_13, ct_64^0'=ct_64^post_13, fdoExtension_7^0'=fdoExtension_7^post_13, lt_12^0'=lt_12^post_13, lt_13^0'=lt_13^post_13, lt_14^0'=lt_14^post_13, lt_16^0'=lt_16^post_13, lt_17^0'=lt_17^post_13, lt_18^0'=lt_18^post_13, lt_19^0'=lt_19^post_13, lt_20^0'=lt_20^post_13, ntStatus_8^0'=ntStatus_8^post_13, [ lt_13^post_13==lt_13^post_13 && lt_12^1_1==ct_115^0 && ___retres1_10^post_13==lt_12^1_1 && lt_12^post_13==lt_12^post_13 && ___cil_tmp2_11^post_13==___retres1_10^post_13 && Result_4^post_13==___cil_tmp2_11^post_13 && Dc_6^0==Dc_6^post_13 && InterfaceType_5^0==InterfaceType_5^post_13 && MaximumInterfaceType_9^0==MaximumInterfaceType_9^post_13 && cnt_29^0==cnt_29^post_13 && cnt_34^0==cnt_34^post_13 && ct_115^0==ct_115^post_13 && ct_15^0==ct_15^post_13 && ct_64^0==ct_64^post_13 && fdoExtension_7^0==fdoExtension_7^post_13 && lt_14^0==lt_14^post_13 && lt_16^0==lt_16^post_13 && lt_17^0==lt_17^post_13 && lt_18^0==lt_18^post_13 && lt_19^0==lt_19^post_13 && lt_20^0==lt_20^post_13 && ntStatus_8^0==ntStatus_8^post_13 ], cost: 1
     14: l9 -> l10 : Dc_6^0'=Dc_6^post_15, InterfaceType_5^0'=InterfaceType_5^post_15, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_15, Result_4^0'=Result_4^post_15, ___cil_tmp2_11^0'=___cil_tmp2_11^post_15, ___retres1_10^0'=___retres1_10^post_15, cnt_29^0'=cnt_29^post_15, cnt_34^0'=cnt_34^post_15, ct_115^0'=ct_115^post_15, ct_15^0'=ct_15^post_15, ct_64^0'=ct_64^post_15, fdoExtension_7^0'=fdoExtension_7^post_15, lt_12^0'=lt_12^post_15, lt_13^0'=lt_13^post_15, lt_14^0'=lt_14^post_15, lt_16^0'=lt_16^post_15, lt_17^0'=lt_17^post_15, lt_18^0'=lt_18^post_15, lt_19^0'=lt_19^post_15, lt_20^0'=lt_20^post_15, ntStatus_8^0'=ntStatus_8^post_15, [ 1+lt_13^0<=256 && Dc_6^0==Dc_6^post_15 && InterfaceType_5^0==InterfaceType_5^post_15 && MaximumInterfaceType_9^0==MaximumInterfaceType_9^post_15 && Result_4^0==Result_4^post_15 && ___cil_tmp2_11^0==___cil_tmp2_11^post_15 && ___retres1_10^0==___retres1_10^post_15 && cnt_29^0==cnt_29^post_15 && cnt_34^0==cnt_34^post_15 && ct_115^0==ct_115^post_15 && ct_15^0==ct_15^post_15 && ct_64^0==ct_64^post_15 && fdoExtension_7^0==fdoExtension_7^post_15 && lt_12^0==lt_12^post_15 && lt_13^0==lt_13^post_15 && lt_14^0==lt_14^post_15 && lt_16^0==lt_16^post_15 && lt_17^0==lt_17^post_15 && lt_18^0==lt_18^post_15 && lt_19^0==lt_19^post_15 && lt_20^0==lt_20^post_15 && ntStatus_8^0==ntStatus_8^post_15 ], cost: 1
     15: l9 -> l10 : Dc_6^0'=Dc_6^post_16, InterfaceType_5^0'=InterfaceType_5^post_16, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_16, Result_4^0'=Result_4^post_16, ___cil_tmp2_11^0'=___cil_tmp2_11^post_16, ___retres1_10^0'=___retres1_10^post_16, cnt_29^0'=cnt_29^post_16, cnt_34^0'=cnt_34^post_16, ct_115^0'=ct_115^post_16, ct_15^0'=ct_15^post_16, ct_64^0'=ct_64^post_16, fdoExtension_7^0'=fdoExtension_7^post_16, lt_12^0'=lt_12^post_16, lt_13^0'=lt_13^post_16, lt_14^0'=lt_14^post_16, lt_16^0'=lt_16^post_16, lt_17^0'=lt_17^post_16, lt_18^0'=lt_18^post_16, lt_19^0'=lt_19^post_16, lt_20^0'=lt_20^post_16, ntStatus_8^0'=ntStatus_8^post_16, [ 257<=lt_13^0 && Dc_6^0==Dc_6^post_16 && InterfaceType_5^0==InterfaceType_5^post_16 && MaximumInterfaceType_9^0==MaximumInterfaceType_9^post_16 && Result_4^0==Result_4^post_16 && ___cil_tmp2_11^0==___cil_tmp2_11^post_16 && ___retres1_10^0==___retres1_10^post_16 && cnt_29^0==cnt_29^post_16 && cnt_34^0==cnt_34^post_16 && ct_115^0==ct_115^post_16 && ct_15^0==ct_15^post_16 && ct_64^0==ct_64^post_16 && fdoExtension_7^0==fdoExtension_7^post_16 && lt_12^0==lt_12^post_16 && lt_13^0==lt_13^post_16 && lt_14^0==lt_14^post_16 && lt_16^0==lt_16^post_16 && lt_17^0==lt_17^post_16 && lt_18^0==lt_18^post_16 && lt_19^0==lt_19^post_16 && lt_20^0==lt_20^post_16 && ntStatus_8^0==ntStatus_8^post_16 ], cost: 1
     16: l10 -> l6 : Dc_6^0'=Dc_6^post_17, InterfaceType_5^0'=InterfaceType_5^post_17, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_17, Result_4^0'=Result_4^post_17, ___cil_tmp2_11^0'=___cil_tmp2_11^post_17, ___retres1_10^0'=___retres1_10^post_17, cnt_29^0'=cnt_29^post_17, cnt_34^0'=cnt_34^post_17, ct_115^0'=ct_115^post_17, ct_15^0'=ct_15^post_17, ct_64^0'=ct_64^post_17, fdoExtension_7^0'=fdoExtension_7^post_17, lt_12^0'=lt_12^post_17, lt_13^0'=lt_13^post_17, lt_14^0'=lt_14^post_17, lt_16^0'=lt_16^post_17, lt_17^0'=lt_17^post_17, lt_18^0'=lt_18^post_17, lt_19^0'=lt_19^post_17, lt_20^0'=lt_20^post_17, ntStatus_8^0'=ntStatus_8^post_17, [ lt_13^post_17==lt_13^post_17 && lt_12^1_2==ct_64^0 && ___retres1_10^post_17==lt_12^1_2 && lt_12^post_17==lt_12^post_17 && ___cil_tmp2_11^post_17==___retres1_10^post_17 && Result_4^post_17==___cil_tmp2_11^post_17 && Dc_6^0==Dc_6^post_17 && InterfaceType_5^0==InterfaceType_5^post_17 && MaximumInterfaceType_9^0==MaximumInterfaceType_9^post_17 && cnt_29^0==cnt_29^post_17 && cnt_34^0==cnt_34^post_17 && ct_115^0==ct_115^post_17 && ct_15^0==ct_15^post_17 && ct_64^0==ct_64^post_17 && fdoExtension_7^0==fdoExtension_7^post_17 && lt_14^0==lt_14^post_17 && lt_16^0==lt_16^post_17 && lt_17^0==lt_17^post_17 && lt_18^0==lt_18^post_17 && lt_19^0==lt_19^post_17 && lt_20^0==lt_20^post_17 && ntStatus_8^0==ntStatus_8^post_17 ], cost: 1
     18: l12 -> l0 : Dc_6^0'=Dc_6^post_19, InterfaceType_5^0'=InterfaceType_5^post_19, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_19, Result_4^0'=Result_4^post_19, ___cil_tmp2_11^0'=___cil_tmp2_11^post_19, ___retres1_10^0'=___retres1_10^post_19, cnt_29^0'=cnt_29^post_19, cnt_34^0'=cnt_34^post_19, ct_115^0'=ct_115^post_19, ct_15^0'=ct_15^post_19, ct_64^0'=ct_64^post_19, fdoExtension_7^0'=fdoExtension_7^post_19, lt_12^0'=lt_12^post_19, lt_13^0'=lt_13^post_19, lt_14^0'=lt_14^post_19, lt_16^0'=lt_16^post_19, lt_17^0'=lt_17^post_19, lt_18^0'=lt_18^post_19, lt_19^0'=lt_19^post_19, lt_20^0'=lt_20^post_19, ntStatus_8^0'=ntStatus_8^post_19, [ Dc_6^0==Dc_6^post_19 && InterfaceType_5^0==InterfaceType_5^post_19 && MaximumInterfaceType_9^0==MaximumInterfaceType_9^post_19 && Result_4^0==Result_4^post_19 && ___cil_tmp2_11^0==___cil_tmp2_11^post_19 && ___retres1_10^0==___retres1_10^post_19 && cnt_29^0==cnt_29^post_19 && cnt_34^0==cnt_34^post_19 && ct_115^0==ct_115^post_19 && ct_15^0==ct_15^post_19 && ct_64^0==ct_64^post_19 && fdoExtension_7^0==fdoExtension_7^post_19 && lt_12^0==lt_12^post_19 && lt_13^0==lt_13^post_19 && lt_14^0==lt_14^post_19 && lt_16^0==lt_16^post_19 && lt_17^0==lt_17^post_19 && lt_18^0==lt_18^post_19 && lt_19^0==lt_19^post_19 && lt_20^0==lt_20^post_19 && ntStatus_8^0==ntStatus_8^post_19 ], cost: 1

Checking for constant complexity:
   The following rule is satisfiable with cost >= 1, yielding constant complexity:
     18: l12 -> l0 : Dc_6^0'=Dc_6^post_19, InterfaceType_5^0'=InterfaceType_5^post_19, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_19, Result_4^0'=Result_4^post_19, ___cil_tmp2_11^0'=___cil_tmp2_11^post_19, ___retres1_10^0'=___retres1_10^post_19, cnt_29^0'=cnt_29^post_19, cnt_34^0'=cnt_34^post_19, ct_115^0'=ct_115^post_19, ct_15^0'=ct_15^post_19, ct_64^0'=ct_64^post_19, fdoExtension_7^0'=fdoExtension_7^post_19, lt_12^0'=lt_12^post_19, lt_13^0'=lt_13^post_19, lt_14^0'=lt_14^post_19, lt_16^0'=lt_16^post_19, lt_17^0'=lt_17^post_19, lt_18^0'=lt_18^post_19, lt_19^0'=lt_19^post_19, lt_20^0'=lt_20^post_19, ntStatus_8^0'=ntStatus_8^post_19, [ Dc_6^0==Dc_6^post_19 && InterfaceType_5^0==InterfaceType_5^post_19 && MaximumInterfaceType_9^0==MaximumInterfaceType_9^post_19 && Result_4^0==Result_4^post_19 && ___cil_tmp2_11^0==___cil_tmp2_11^post_19 && ___retres1_10^0==___retres1_10^post_19 && cnt_29^0==cnt_29^post_19 && cnt_34^0==cnt_34^post_19 && ct_115^0==ct_115^post_19 && ct_15^0==ct_15^post_19 && ct_64^0==ct_64^post_19 && fdoExtension_7^0==fdoExtension_7^post_19 && lt_12^0==lt_12^post_19 && lt_13^0==lt_13^post_19 && lt_14^0==lt_14^post_19 && lt_16^0==lt_16^post_19 && lt_17^0==lt_17^post_19 && lt_18^0==lt_18^post_19 && lt_19^0==lt_19^post_19 && lt_20^0==lt_20^post_19 && ntStatus_8^0==ntStatus_8^post_19 ], cost: 1

Removed unreachable and leaf rules:
   Start location: l12
      0: l0 -> l1 : Dc_6^0'=Dc_6^post_1, InterfaceType_5^0'=InterfaceType_5^post_1, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_1, Result_4^0'=Result_4^post_1, ___cil_tmp2_11^0'=___cil_tmp2_11^post_1, ___retres1_10^0'=___retres1_10^post_1, cnt_29^0'=cnt_29^post_1, cnt_34^0'=cnt_34^post_1, ct_115^0'=ct_115^post_1, ct_15^0'=ct_15^post_1, ct_64^0'=ct_64^post_1, fdoExtension_7^0'=fdoExtension_7^post_1, lt_12^0'=lt_12^post_1, lt_13^0'=lt_13^post_1, lt_14^0'=lt_14^post_1, lt_16^0'=lt_16^post_1, lt_17^0'=lt_17^post_1, lt_18^0'=lt_18^post_1, lt_19^0'=lt_19^post_1, lt_20^0'=lt_20^post_1, ntStatus_8^0'=ntStatus_8^post_1, [ MaximumInterfaceType_9^post_1==MaximumInterfaceType_9^post_1 && ntStatus_8^post_1==ntStatus_8^post_1 && fdoExtension_7^post_1==fdoExtension_7^post_1 && Dc_6^post_1==Dc_6^post_1 && InterfaceType_5^post_1==InterfaceType_5^post_1 && Result_4^0==Result_4^post_1 && ___cil_tmp2_11^0==___cil_tmp2_11^post_1 && ___retres1_10^0==___retres1_10^post_1 && cnt_29^0==cnt_29^post_1 && cnt_34^0==cnt_34^post_1 && ct_115^0==ct_115^post_1 && ct_15^0==ct_15^post_1 && ct_64^0==ct_64^post_1 && lt_12^0==lt_12^post_1 && lt_13^0==lt_13^post_1 && lt_14^0==lt_14^post_1 && lt_16^0==lt_16^post_1 && lt_17^0==lt_17^post_1 && lt_18^0==lt_18^post_1 && lt_19^0==lt_19^post_1 && lt_20^0==lt_20^post_1 ], cost: 1
      1: l1 -> l2 : Dc_6^0'=Dc_6^post_2, InterfaceType_5^0'=InterfaceType_5^post_2, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_2, Result_4^0'=Result_4^post_2, ___cil_tmp2_11^0'=___cil_tmp2_11^post_2, ___retres1_10^0'=___retres1_10^post_2, cnt_29^0'=cnt_29^post_2, cnt_34^0'=cnt_34^post_2, ct_115^0'=ct_115^post_2, ct_15^0'=ct_15^post_2, ct_64^0'=ct_64^post_2, fdoExtension_7^0'=fdoExtension_7^post_2, lt_12^0'=lt_12^post_2, lt_13^0'=lt_13^post_2, lt_14^0'=lt_14^post_2, lt_16^0'=lt_16^post_2, lt_17^0'=lt_17^post_2, lt_18^0'=lt_18^post_2, lt_19^0'=lt_19^post_2, lt_20^0'=lt_20^post_2, ntStatus_8^0'=ntStatus_8^post_2, [ lt_19^1_1==cnt_29^0 && lt_20^1_1==cnt_34^0 && 0<=-1+lt_20^1_1-lt_19^1_1 && lt_19^post_2==lt_19^post_2 && lt_20^post_2==lt_20^post_2 && lt_18^1_1==cnt_29^0 && lt_18^post_2==lt_18^post_2 && lt_16^1_1==1+cnt_29^0 && lt_17^1_1==cnt_34^0 && 1+lt_16^1_1-lt_17^1_1<=0 && lt_16^post_2==lt_16^post_2 && lt_17^post_2==lt_17^post_2 && ct_15^1_1==ct_15^1_1 && ct_15^post_2==ct_15^post_2 && lt_14^1_1==ct_115^0 && lt_14^1_1<=0 && lt_14^post_2==lt_14^post_2 && Dc_6^0==Dc_6^post_2 && InterfaceType_5^0==InterfaceType_5^post_2 && MaximumInterfaceType_9^0==MaximumInterfaceType_9^post_2 && Result_4^0==Result_4^post_2 && ___cil_tmp2_11^0==___cil_tmp2_11^post_2 && ___retres1_10^0==___retres1_10^post_2 && cnt_29^0==cnt_29^post_2 && cnt_34^0==cnt_34^post_2 && ct_115^0==ct_115^post_2 && ct_64^0==ct_64^post_2 && fdoExtension_7^0==fdoExtension_7^post_2 && lt_12^0==lt_12^post_2 && lt_13^0==lt_13^post_2 && ntStatus_8^0==ntStatus_8^post_2 ], cost: 1
      3: l1 -> l3 : Dc_6^0'=Dc_6^post_4, InterfaceType_5^0'=InterfaceType_5^post_4, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_4, Result_4^0'=Result_4^post_4, ___cil_tmp2_11^0'=___cil_tmp2_11^post_4, ___retres1_10^0'=___retres1_10^post_4, cnt_29^0'=cnt_29^post_4, cnt_34^0'=cnt_34^post_4, ct_115^0'=ct_115^post_4, ct_15^0'=ct_15^post_4, ct_64^0'=ct_64^post_4, fdoExtension_7^0'=fdoExtension_7^post_4, lt_12^0'=lt_12^post_4, lt_13^0'=lt_13^post_4, lt_14^0'=lt_14^post_4, lt_16^0'=lt_16^post_4, lt_17^0'=lt_17^post_4, lt_18^0'=lt_18^post_4, lt_19^0'=lt_19^post_4, lt_20^0'=lt_20^post_4, ntStatus_8^0'=ntStatus_8^post_4, [ lt_19^1_2_1==cnt_29^0 && lt_20^1_2_1==cnt_34^0 && 0<=-1+lt_20^1_2_1-lt_19^1_2_1 && lt_19^post_4==lt_19^post_4 && lt_20^post_4==lt_20^post_4 && lt_18^1_2_1==cnt_29^0 && lt_18^post_4==lt_18^post_4 && lt_16^1_2_1==1+cnt_29^0 && lt_17^1_2_1==cnt_34^0 && 1+lt_16^1_2_1-lt_17^1_2_1<=0 && lt_16^post_4==lt_16^post_4 && lt_17^post_4==lt_17^post_4 && ct_15^1_2==ct_15^1_2 && ct_15^post_4==ct_15^post_4 && lt_14^1_2_1==ct_115^0 && 0<=-1+lt_14^1_2_1 && lt_14^post_4==lt_14^post_4 && lt_13^1_1==ct_115^0 && lt_13^1_1<=256 && 256<=lt_13^1_1 && lt_13^post_4==lt_13^post_4 && Dc_6^0==Dc_6^post_4 && InterfaceType_5^0==InterfaceType_5^post_4 && MaximumInterfaceType_9^0==MaximumInterfaceType_9^post_4 && Result_4^0==Result_4^post_4 && ___cil_tmp2_11^0==___cil_tmp2_11^post_4 && ___retres1_10^0==___retres1_10^post_4 && cnt_29^0==cnt_29^post_4 && cnt_34^0==cnt_34^post_4 && ct_115^0==ct_115^post_4 && ct_64^0==ct_64^post_4 && fdoExtension_7^0==fdoExtension_7^post_4 && lt_12^0==lt_12^post_4 && ntStatus_8^0==ntStatus_8^post_4 ], cost: 1
      5: l1 -> l4 : Dc_6^0'=Dc_6^post_6, InterfaceType_5^0'=InterfaceType_5^post_6, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_6, Result_4^0'=Result_4^post_6, ___cil_tmp2_11^0'=___cil_tmp2_11^post_6, ___retres1_10^0'=___retres1_10^post_6, cnt_29^0'=cnt_29^post_6, cnt_34^0'=cnt_34^post_6, ct_115^0'=ct_115^post_6, ct_15^0'=ct_15^post_6, ct_64^0'=ct_64^post_6, fdoExtension_7^0'=fdoExtension_7^post_6, lt_12^0'=lt_12^post_6, lt_13^0'=lt_13^post_6, lt_14^0'=lt_14^post_6, lt_16^0'=lt_16^post_6, lt_17^0'=lt_17^post_6, lt_18^0'=lt_18^post_6, lt_19^0'=lt_19^post_6, lt_20^0'=lt_20^post_6, ntStatus_8^0'=ntStatus_8^post_6, [ lt_19^1_3_1==cnt_29^0 && lt_20^1_3_1==cnt_34^0 && 0<=-1-lt_19^1_3_1+lt_20^1_3_1 && lt_19^post_6==lt_19^post_6 && lt_20^post_6==lt_20^post_6 && lt_18^1_3_1==cnt_29^0 && lt_18^post_6==lt_18^post_6 && lt_16^1_3_1==1+cnt_29^0 && lt_17^1_3_1==cnt_34^0 && 0<=lt_16^1_3_1-lt_17^1_3_1 && lt_16^post_6==lt_16^post_6 && lt_17^post_6==lt_17^post_6 && ct_15^1_3==ct_15^1_3 && ct_15^post_6==ct_15^post_6 && lt_14^1_3_1==ct_64^0 && lt_14^1_3_1<=0 && lt_14^post_6==lt_14^post_6 && Dc_6^0==Dc_6^post_6 && InterfaceType_5^0==InterfaceType_5^post_6 && MaximumInterfaceType_9^0==MaximumInterfaceType_9^post_6 && Result_4^0==Result_4^post_6 && ___cil_tmp2_11^0==___cil_tmp2_11^post_6 && ___retres1_10^0==___retres1_10^post_6 && cnt_29^0==cnt_29^post_6 && cnt_34^0==cnt_34^post_6 && ct_115^0==ct_115^post_6 && ct_64^0==ct_64^post_6 && fdoExtension_7^0==fdoExtension_7^post_6 && lt_12^0==lt_12^post_6 && lt_13^0==lt_13^post_6 && ntStatus_8^0==ntStatus_8^post_6 ], cost: 1
      7: l1 -> l5 : Dc_6^0'=Dc_6^post_8, InterfaceType_5^0'=InterfaceType_5^post_8, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_8, Result_4^0'=Result_4^post_8, ___cil_tmp2_11^0'=___cil_tmp2_11^post_8, ___retres1_10^0'=___retres1_10^post_8, cnt_29^0'=cnt_29^post_8, cnt_34^0'=cnt_34^post_8, ct_115^0'=ct_115^post_8, ct_15^0'=ct_15^post_8, ct_64^0'=ct_64^post_8, fdoExtension_7^0'=fdoExtension_7^post_8, lt_12^0'=lt_12^post_8, lt_13^0'=lt_13^post_8, lt_14^0'=lt_14^post_8, lt_16^0'=lt_16^post_8, lt_17^0'=lt_17^post_8, lt_18^0'=lt_18^post_8, lt_19^0'=lt_19^post_8, lt_20^0'=lt_20^post_8, ntStatus_8^0'=ntStatus_8^post_8, [ lt_19^1_4_1==cnt_29^0 && lt_20^1_4_1==cnt_34^0 && 0<=-1-lt_19^1_4_1+lt_20^1_4_1 && lt_19^post_8==lt_19^post_8 && lt_20^post_8==lt_20^post_8 && lt_18^1_4_1==cnt_29^0 && lt_18^post_8==lt_18^post_8 && lt_16^1_4_1==1+cnt_29^0 && lt_17^1_4_1==cnt_34^0 && 0<=lt_16^1_4_1-lt_17^1_4_1 && lt_16^post_8==lt_16^post_8 && lt_17^post_8==lt_17^post_8 && ct_15^1_4==ct_15^1_4 && ct_15^post_8==ct_15^post_8 && lt_14^1_4_1==ct_64^0 && 0<=-1+lt_14^1_4_1 && lt_14^post_8==lt_14^post_8 && lt_13^1_2_1==ct_64^0 && lt_13^1_2_1<=256 && 256<=lt_13^1_2_1 && lt_13^post_8==lt_13^post_8 && Dc_6^0==Dc_6^post_8 && InterfaceType_5^0==InterfaceType_5^post_8 && MaximumInterfaceType_9^0==MaximumInterfaceType_9^post_8 && Result_4^0==Result_4^post_8 && ___cil_tmp2_11^0==___cil_tmp2_11^post_8 && ___retres1_10^0==___retres1_10^post_8 && cnt_29^0==cnt_29^post_8 && cnt_34^0==cnt_34^post_8 && ct_115^0==ct_115^post_8 && ct_64^0==ct_64^post_8 && fdoExtension_7^0==fdoExtension_7^post_8 && lt_12^0==lt_12^post_8 && ntStatus_8^0==ntStatus_8^post_8 ], cost: 1
      2: l2 -> l1 : Dc_6^0'=Dc_6^post_3, InterfaceType_5^0'=InterfaceType_5^post_3, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_3, Result_4^0'=Result_4^post_3, ___cil_tmp2_11^0'=___cil_tmp2_11^post_3, ___retres1_10^0'=___retres1_10^post_3, cnt_29^0'=cnt_29^post_3, cnt_34^0'=cnt_34^post_3, ct_115^0'=ct_115^post_3, ct_15^0'=ct_15^post_3, ct_64^0'=ct_64^post_3, fdoExtension_7^0'=fdoExtension_7^post_3, lt_12^0'=lt_12^post_3, lt_13^0'=lt_13^post_3, lt_14^0'=lt_14^post_3, lt_16^0'=lt_16^post_3, lt_17^0'=lt_17^post_3, lt_18^0'=lt_18^post_3, lt_19^0'=lt_19^post_3, lt_20^0'=lt_20^post_3, ntStatus_8^0'=ntStatus_8^post_3, [ Dc_6^0==Dc_6^post_3 && InterfaceType_5^0==InterfaceType_5^post_3 && MaximumInterfaceType_9^0==MaximumInterfaceType_9^post_3 && Result_4^0==Result_4^post_3 && ___cil_tmp2_11^0==___cil_tmp2_11^post_3 && ___retres1_10^0==___retres1_10^post_3 && cnt_29^0==cnt_29^post_3 && cnt_34^0==cnt_34^post_3 && ct_115^0==ct_115^post_3 && ct_15^0==ct_15^post_3 && ct_64^0==ct_64^post_3 && fdoExtension_7^0==fdoExtension_7^post_3 && lt_12^0==lt_12^post_3 && lt_13^0==lt_13^post_3 && lt_14^0==lt_14^post_3 && lt_16^0==lt_16^post_3 && lt_17^0==lt_17^post_3 && lt_18^0==lt_18^post_3 && lt_19^0==lt_19^post_3 && lt_20^0==lt_20^post_3 && ntStatus_8^0==ntStatus_8^post_3 ], cost: 1
      4: l3 -> l1 : Dc_6^0'=Dc_6^post_5, InterfaceType_5^0'=InterfaceType_5^post_5, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_5, Result_4^0'=Result_4^post_5, ___cil_tmp2_11^0'=___cil_tmp2_11^post_5, ___retres1_10^0'=___retres1_10^post_5, cnt_29^0'=cnt_29^post_5, cnt_34^0'=cnt_34^post_5, ct_115^0'=ct_115^post_5, ct_15^0'=ct_15^post_5, ct_64^0'=ct_64^post_5, fdoExtension_7^0'=fdoExtension_7^post_5, lt_12^0'=lt_12^post_5, lt_13^0'=lt_13^post_5, lt_14^0'=lt_14^post_5, lt_16^0'=lt_16^post_5, lt_17^0'=lt_17^post_5, lt_18^0'=lt_18^post_5, lt_19^0'=lt_19^post_5, lt_20^0'=lt_20^post_5, ntStatus_8^0'=ntStatus_8^post_5, [ Dc_6^0==Dc_6^post_5 && InterfaceType_5^0==InterfaceType_5^post_5 && MaximumInterfaceType_9^0==MaximumInterfaceType_9^post_5 && Result_4^0==Result_4^post_5 && ___cil_tmp2_11^0==___cil_tmp2_11^post_5 && ___retres1_10^0==___retres1_10^post_5 && cnt_29^0==cnt_29^post_5 && cnt_34^0==cnt_34^post_5 && ct_115^0==ct_115^post_5 && ct_15^0==ct_15^post_5 && ct_64^0==ct_64^post_5 && fdoExtension_7^0==fdoExtension_7^post_5 && lt_12^0==lt_12^post_5 && lt_13^0==lt_13^post_5 && lt_14^0==lt_14^post_5 && lt_16^0==lt_16^post_5 && lt_17^0==lt_17^post_5 && lt_18^0==lt_18^post_5 && lt_19^0==lt_19^post_5 && lt_20^0==lt_20^post_5 && ntStatus_8^0==ntStatus_8^post_5 ], cost: 1
      6: l4 -> l1 : Dc_6^0'=Dc_6^post_7, InterfaceType_5^0'=InterfaceType_5^post_7, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_7, Result_4^0'=Result_4^post_7, ___cil_tmp2_11^0'=___cil_tmp2_11^post_7, ___retres1_10^0'=___retres1_10^post_7, cnt_29^0'=cnt_29^post_7, cnt_34^0'=cnt_34^post_7, ct_115^0'=ct_115^post_7, ct_15^0'=ct_15^post_7, ct_64^0'=ct_64^post_7, fdoExtension_7^0'=fdoExtension_7^post_7, lt_12^0'=lt_12^post_7, lt_13^0'=lt_13^post_7, lt_14^0'=lt_14^post_7, lt_16^0'=lt_16^post_7, lt_17^0'=lt_17^post_7, lt_18^0'=lt_18^post_7, lt_19^0'=lt_19^post_7, lt_20^0'=lt_20^post_7, ntStatus_8^0'=ntStatus_8^post_7, [ Dc_6^0==Dc_6^post_7 && InterfaceType_5^0==InterfaceType_5^post_7 && MaximumInterfaceType_9^0==MaximumInterfaceType_9^post_7 && Result_4^0==Result_4^post_7 && ___cil_tmp2_11^0==___cil_tmp2_11^post_7 && ___retres1_10^0==___retres1_10^post_7 && cnt_29^0==cnt_29^post_7 && cnt_34^0==cnt_34^post_7 && ct_115^0==ct_115^post_7 && ct_15^0==ct_15^post_7 && ct_64^0==ct_64^post_7 && fdoExtension_7^0==fdoExtension_7^post_7 && lt_12^0==lt_12^post_7 && lt_13^0==lt_13^post_7 && lt_14^0==lt_14^post_7 && lt_16^0==lt_16^post_7 && lt_17^0==lt_17^post_7 && lt_18^0==lt_18^post_7 && lt_19^0==lt_19^post_7 && lt_20^0==lt_20^post_7 && ntStatus_8^0==ntStatus_8^post_7 ], cost: 1
      8: l5 -> l1 : Dc_6^0'=Dc_6^post_9, InterfaceType_5^0'=InterfaceType_5^post_9, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_9, Result_4^0'=Result_4^post_9, ___cil_tmp2_11^0'=___cil_tmp2_11^post_9, ___retres1_10^0'=___retres1_10^post_9, cnt_29^0'=cnt_29^post_9, cnt_34^0'=cnt_34^post_9, ct_115^0'=ct_115^post_9, ct_15^0'=ct_15^post_9, ct_64^0'=ct_64^post_9, fdoExtension_7^0'=fdoExtension_7^post_9, lt_12^0'=lt_12^post_9, lt_13^0'=lt_13^post_9, lt_14^0'=lt_14^post_9, lt_16^0'=lt_16^post_9, lt_17^0'=lt_17^post_9, lt_18^0'=lt_18^post_9, lt_19^0'=lt_19^post_9, lt_20^0'=lt_20^post_9, ntStatus_8^0'=ntStatus_8^post_9, [ Dc_6^0==Dc_6^post_9 && InterfaceType_5^0==InterfaceType_5^post_9 && MaximumInterfaceType_9^0==MaximumInterfaceType_9^post_9 && Result_4^0==Result_4^post_9 && ___cil_tmp2_11^0==___cil_tmp2_11^post_9 && ___retres1_10^0==___retres1_10^post_9 && cnt_29^0==cnt_29^post_9 && cnt_34^0==cnt_34^post_9 && ct_115^0==ct_115^post_9 && ct_15^0==ct_15^post_9 && ct_64^0==ct_64^post_9 && fdoExtension_7^0==fdoExtension_7^post_9 && lt_12^0==lt_12^post_9 && lt_13^0==lt_13^post_9 && lt_14^0==lt_14^post_9 && lt_16^0==lt_16^post_9 && lt_17^0==lt_17^post_9 && lt_18^0==lt_18^post_9 && lt_19^0==lt_19^post_9 && lt_20^0==lt_20^post_9 && ntStatus_8^0==ntStatus_8^post_9 ], cost: 1
     18: l12 -> l0 : Dc_6^0'=Dc_6^post_19, InterfaceType_5^0'=InterfaceType_5^post_19, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_19, Result_4^0'=Result_4^post_19, ___cil_tmp2_11^0'=___cil_tmp2_11^post_19, ___retres1_10^0'=___retres1_10^post_19, cnt_29^0'=cnt_29^post_19, cnt_34^0'=cnt_34^post_19, ct_115^0'=ct_115^post_19, ct_15^0'=ct_15^post_19, ct_64^0'=ct_64^post_19, fdoExtension_7^0'=fdoExtension_7^post_19, lt_12^0'=lt_12^post_19, lt_13^0'=lt_13^post_19, lt_14^0'=lt_14^post_19, lt_16^0'=lt_16^post_19, lt_17^0'=lt_17^post_19, lt_18^0'=lt_18^post_19, lt_19^0'=lt_19^post_19, lt_20^0'=lt_20^post_19, ntStatus_8^0'=ntStatus_8^post_19, [ Dc_6^0==Dc_6^post_19 && InterfaceType_5^0==InterfaceType_5^post_19 && MaximumInterfaceType_9^0==MaximumInterfaceType_9^post_19 && Result_4^0==Result_4^post_19 && ___cil_tmp2_11^0==___cil_tmp2_11^post_19 && ___retres1_10^0==___retres1_10^post_19 && cnt_29^0==cnt_29^post_19 && cnt_34^0==cnt_34^post_19 && ct_115^0==ct_115^post_19 && ct_15^0==ct_15^post_19 && ct_64^0==ct_64^post_19 && fdoExtension_7^0==fdoExtension_7^post_19 && lt_12^0==lt_12^post_19 && lt_13^0==lt_13^post_19 && lt_14^0==lt_14^post_19 && lt_16^0==lt_16^post_19 && lt_17^0==lt_17^post_19 && lt_18^0==lt_18^post_19 && lt_19^0==lt_19^post_19 && lt_20^0==lt_20^post_19 && ntStatus_8^0==ntStatus_8^post_19 ], cost: 1

Simplified all rules, resulting in:
   Start location: l12
      0: l0 -> l1 : Dc_6^0'=Dc_6^post_1, InterfaceType_5^0'=InterfaceType_5^post_1, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_1, fdoExtension_7^0'=fdoExtension_7^post_1, ntStatus_8^0'=ntStatus_8^post_1, [], cost: 1
      1: l1 -> l2 : ct_15^0'=ct_15^post_2, lt_14^0'=lt_14^post_2, lt_16^0'=lt_16^post_2, lt_17^0'=lt_17^post_2, lt_18^0'=lt_18^post_2, lt_19^0'=lt_19^post_2, lt_20^0'=lt_20^post_2, [ 2-cnt_34^0+cnt_29^0<=0 && ct_115^0<=0 ], cost: 1
      3: l1 -> l3 : ct_15^0'=ct_15^post_4, lt_13^0'=lt_13^post_4, lt_14^0'=lt_14^post_4, lt_16^0'=lt_16^post_4, lt_17^0'=lt_17^post_4, lt_18^0'=lt_18^post_4, lt_19^0'=lt_19^post_4, lt_20^0'=lt_20^post_4, [ 2-cnt_34^0+cnt_29^0<=0 && -256+ct_115^0==0 ], cost: 1
      5: l1 -> l4 : ct_15^0'=ct_15^post_6, lt_14^0'=lt_14^post_6, lt_16^0'=lt_16^post_6, lt_17^0'=lt_17^post_6, lt_18^0'=lt_18^post_6, lt_19^0'=lt_19^post_6, lt_20^0'=lt_20^post_6, [ 1-cnt_34^0+cnt_29^0==0 && ct_64^0<=0 ], cost: 1
      7: l1 -> l5 : ct_15^0'=ct_15^post_8, lt_13^0'=lt_13^post_8, lt_14^0'=lt_14^post_8, lt_16^0'=lt_16^post_8, lt_17^0'=lt_17^post_8, lt_18^0'=lt_18^post_8, lt_19^0'=lt_19^post_8, lt_20^0'=lt_20^post_8, [ 1-cnt_34^0+cnt_29^0==0 && -256+ct_64^0==0 ], cost: 1
      2: l2 -> l1 : [], cost: 1
      4: l3 -> l1 : [], cost: 1
      6: l4 -> l1 : [], cost: 1
      8: l5 -> l1 : [], cost: 1
     18: l12 -> l0 : [], cost: 1

### Simplification by acceleration and chaining ###

Eliminated locations (on linear paths):
   Start location: l12
     20: l1 -> l1 : ct_15^0'=ct_15^post_2, lt_14^0'=lt_14^post_2, lt_16^0'=lt_16^post_2, lt_17^0'=lt_17^post_2, lt_18^0'=lt_18^post_2, lt_19^0'=lt_19^post_2, lt_20^0'=lt_20^post_2, [ 2-cnt_34^0+cnt_29^0<=0 && ct_115^0<=0 ], cost: 2
     21: l1 -> l1 : ct_15^0'=ct_15^post_4, lt_13^0'=lt_13^post_4, lt_14^0'=lt_14^post_4, lt_16^0'=lt_16^post_4, lt_17^0'=lt_17^post_4, lt_18^0'=lt_18^post_4, lt_19^0'=lt_19^post_4, lt_20^0'=lt_20^post_4, [ 2-cnt_34^0+cnt_29^0<=0 && -256+ct_115^0==0 ], cost: 2
     22: l1 -> l1 : ct_15^0'=ct_15^post_6, lt_14^0'=lt_14^post_6, lt_16^0'=lt_16^post_6, lt_17^0'=lt_17^post_6, lt_18^0'=lt_18^post_6, lt_19^0'=lt_19^post_6, lt_20^0'=lt_20^post_6, [ 1-cnt_34^0+cnt_29^0==0 && ct_64^0<=0 ], cost: 2
     23: l1 -> l1 : ct_15^0'=ct_15^post_8, lt_13^0'=lt_13^post_8, lt_14^0'=lt_14^post_8, lt_16^0'=lt_16^post_8, lt_17^0'=lt_17^post_8, lt_18^0'=lt_18^post_8, lt_19^0'=lt_19^post_8, lt_20^0'=lt_20^post_8, [ 1-cnt_34^0+cnt_29^0==0 && -256+ct_64^0==0 ], cost: 2
     19: l12 -> l1 : Dc_6^0'=Dc_6^post_1, InterfaceType_5^0'=InterfaceType_5^post_1, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_1, fdoExtension_7^0'=fdoExtension_7^post_1, ntStatus_8^0'=ntStatus_8^post_1, [], cost: 2

Accelerating simple loops of location 1.
   Accelerating the following rules:
     20: l1 -> l1 : ct_15^0'=ct_15^post_2, lt_14^0'=lt_14^post_2, lt_16^0'=lt_16^post_2, lt_17^0'=lt_17^post_2, lt_18^0'=lt_18^post_2, lt_19^0'=lt_19^post_2, lt_20^0'=lt_20^post_2, [ 2-cnt_34^0+cnt_29^0<=0 && ct_115^0<=0 ], cost: 2
     21: l1 -> l1 : ct_15^0'=ct_15^post_4, lt_13^0'=lt_13^post_4, lt_14^0'=lt_14^post_4, lt_16^0'=lt_16^post_4, lt_17^0'=lt_17^post_4, lt_18^0'=lt_18^post_4, lt_19^0'=lt_19^post_4, lt_20^0'=lt_20^post_4, [ 2-cnt_34^0+cnt_29^0<=0 && -256+ct_115^0==0 ], cost: 2
     22: l1 -> l1 : ct_15^0'=ct_15^post_6, lt_14^0'=lt_14^post_6, lt_16^0'=lt_16^post_6, lt_17^0'=lt_17^post_6, lt_18^0'=lt_18^post_6, lt_19^0'=lt_19^post_6, lt_20^0'=lt_20^post_6, [ 1-cnt_34^0+cnt_29^0==0 && ct_64^0<=0 ], cost: 2
     23: l1 -> l1 : ct_15^0'=ct_15^post_8, lt_13^0'=lt_13^post_8, lt_14^0'=lt_14^post_8, lt_16^0'=lt_16^post_8, lt_17^0'=lt_17^post_8, lt_18^0'=lt_18^post_8, lt_19^0'=lt_19^post_8, lt_20^0'=lt_20^post_8, [ 1-cnt_34^0+cnt_29^0==0 && -256+ct_64^0==0 ], cost: 2

   Accelerated rule 20 with non-termination, yielding the new rule 24.
   Accelerated rule 21 with non-termination, yielding the new rule 25.
   Accelerated rule 22 with non-termination, yielding the new rule 26.
   Accelerated rule 23 with non-termination, yielding the new rule 27.
[accelerate] Nesting with 0 inner and 0 outer candidates
   Removing the simple loops: 20 21 22 23.

Accelerated all simple loops using metering functions (where possible):
   Start location: l12
     24: l1 -> [13] : [ 2-cnt_34^0+cnt_29^0<=0 && ct_115^0<=0 ], cost: NONTERM
     25: l1 -> [13] : [ 2-cnt_34^0+cnt_29^0<=0 && -256+ct_115^0==0 ], cost: NONTERM
     26: l1 -> [13] : [ 1-cnt_34^0+cnt_29^0==0 && ct_64^0<=0 ], cost: NONTERM
     27: l1 -> [13] : [ 1-cnt_34^0+cnt_29^0==0 && -256+ct_64^0==0 ], cost: NONTERM
     19: l12 -> l1 : Dc_6^0'=Dc_6^post_1, InterfaceType_5^0'=InterfaceType_5^post_1, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_1, fdoExtension_7^0'=fdoExtension_7^post_1, ntStatus_8^0'=ntStatus_8^post_1, [], cost: 2

Chained accelerated rules (with incoming rules):
   Start location: l12
     19: l12 -> l1 : Dc_6^0'=Dc_6^post_1, InterfaceType_5^0'=InterfaceType_5^post_1, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post_1, fdoExtension_7^0'=fdoExtension_7^post_1, ntStatus_8^0'=ntStatus_8^post_1, [], cost: 2
     28: l12 -> [13] : [ 2-cnt_34^0+cnt_29^0<=0 && ct_115^0<=0 ], cost: NONTERM
     29: l12 -> [13] : [ 2-cnt_34^0+cnt_29^0<=0 && -256+ct_115^0==0 ], cost: NONTERM
     30: l12 -> [13] : [ 1-cnt_34^0+cnt_29^0==0 && ct_64^0<=0 ], cost: NONTERM
     31: l12 -> [13] : [ 1-cnt_34^0+cnt_29^0==0 && -256+ct_64^0==0 ], cost: NONTERM

Removed unreachable locations (and leaf rules with constant cost):
   Start location: l12
     28: l12 -> [13] : [ 2-cnt_34^0+cnt_29^0<=0 && ct_115^0<=0 ], cost: NONTERM
     29: l12 -> [13] : [ 2-cnt_34^0+cnt_29^0<=0 && -256+ct_115^0==0 ], cost: NONTERM
     30: l12 -> [13] : [ 1-cnt_34^0+cnt_29^0==0 && ct_64^0<=0 ], cost: NONTERM
     31: l12 -> [13] : [ 1-cnt_34^0+cnt_29^0==0 && -256+ct_64^0==0 ], cost: NONTERM

### Computing asymptotic complexity ###

Fully simplified ITS problem
   Start location: l12
     28: l12 -> [13] : [ 2-cnt_34^0+cnt_29^0<=0 && ct_115^0<=0 ], cost: NONTERM
     29: l12 -> [13] : [ 2-cnt_34^0+cnt_29^0<=0 && -256+ct_115^0==0 ], cost: NONTERM
     30: l12 -> [13] : [ 1-cnt_34^0+cnt_29^0==0 && ct_64^0<=0 ], cost: NONTERM
     31: l12 -> [13] : [ 1-cnt_34^0+cnt_29^0==0 && -256+ct_64^0==0 ], cost: NONTERM

Computing asymptotic complexity for rule 28
   Guard is satisfiable, yielding nontermination
   Resulting cost NONTERM has complexity: Nonterm

Found new complexity Nonterm.

Obtained the following overall complexity (w.r.t. the length of the input n):
   Complexity:  Nonterm
   Cpx degree:  Nonterm
   Solved cost: NONTERM
   Rule cost:   NONTERM
   Rule guard:  [ 2-cnt_34^0+cnt_29^0<=0 && ct_115^0<=0 ]

NO